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gerrit-public.fairphone.software / toolchain / llvm-project / f0d042619b0411bf2c211e61a3dbd3ea0ceb7c49 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: efe10e50734c0fe6a7282c3a39fd90b9ddd6e952 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]70def BWDivider : ProcResource<1>;
71// FP division and sqrt on port 0.
72def BWFPDivider : ProcResource<1>;
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]73
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]74// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75// cycles after the memory operand.
76def : ReadAdvance<ReadAfterLd, 5>;
77
78// Many SchedWrites are defined in pairs with and without a folded load.
79// Instructions with folded loads are usually micro-fused, so they only appear
80// as two micro-ops when queued in the reservation station.
81// This multiclass defines the resource usage for variants with and without
82// folded loads.
83multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]84 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]85 int Lat, list<int> Res = [1], int UOps = 1,
86 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]87 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]88 def : WriteRes<SchedRW, ExePorts> {
89 let Latency = Lat;
90 let ResourceCycles = Res;
91 let NumMicroOps = UOps;
92 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]93
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]94 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
95 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]97 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]98 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]99 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]100 }
101}
102
Craig Topperf131b602018-04-06 16:16:46 +0000[diff] [blame]103// A folded store needs a cycle on port 4 for the store data, and an extra port
104// 2/3/7 cycle to recompute the address.
105def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]106
107// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]108defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
109defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
110defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000[diff] [blame]111defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]112def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]113
114def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
115
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]116// Bit counts.
117defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
118defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
119defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
120defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
121
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]122// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]123defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]124
Craig Topper89310f52018-03-29 20:41:39 +0000[diff] [blame]125// BMI1 BEXTR, BMI2 BZHI
126defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
127defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
128
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]129// Loads, stores, and moves, not folded with other operations.
130def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
131def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
132def : WriteRes<WriteMove, [BWPort0156]>;
133
134// Idioms that clear a register, like xorps %xmm0, %xmm0.
135// These can often bypass execution ports completely.
136def : WriteRes<WriteZero, []>;
137
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]138// Treat misc copies as a move.
139def : InstRW<[WriteMove], (instrs COPY)>;
140
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]141// Branches don't produce values, so they have no latency, but they still
142// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]143defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]144
145// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]146def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
147def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
148def : WriteRes<WriteFMove, [BWPort5]>;
149
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]150defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
151defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
152defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
153defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
154defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
155defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
156defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
157defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
158defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
159defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]160
161// FMA Scheduling helper class.
162// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
163
164// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]165def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
166def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
167def : WriteRes<WriteVecMove, [BWPort015]>;
168
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]169defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
170defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
171defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
Craig Topper13a0f832018-03-31 04:54:32 +0000[diff] [blame]172defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]173defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
174defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
175defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
176defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]177
178// Vector bitwise operations.
179// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]180defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]181
182// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]183defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
184defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
185defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]186
187// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]188
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]189// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]190def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]191 let Latency = 11;
192 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]193 let ResourceCycles = [3];
194}
195def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]196 let Latency = 16;
197 let NumMicroOps = 4;
198 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]199}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]200
201// Packed Compare Explicit Length Strings, Return Mask
202def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
203 let Latency = 19;
204 let NumMicroOps = 9;
205 let ResourceCycles = [4,3,1,1];
206}
207def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
208 let Latency = 24;
209 let NumMicroOps = 10;
210 let ResourceCycles = [4,3,1,1,1];
211}
212
213// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]214def : WriteRes<WritePCmpIStrI, [BWPort0]> {
215 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]216 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]217 let ResourceCycles = [3];
218}
219def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]220 let Latency = 16;
221 let NumMicroOps = 4;
222 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]223}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]224
225// Packed Compare Explicit Length Strings, Return Index
226def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
227 let Latency = 18;
228 let NumMicroOps = 8;
229 let ResourceCycles = [4,3,1];
230}
231def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
232 let Latency = 23;
233 let NumMicroOps = 9;
234 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]235}
236
Simon Pilgrima2f26782018-03-27 20:38:54 +0000[diff] [blame]237// MOVMSK Instructions.
238def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
239def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
240def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
241
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]242// AES instructions.
243def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
244 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]245 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]246 let ResourceCycles = [1];
247}
248def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]249 let Latency = 12;
250 let NumMicroOps = 2;
251 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]252}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]253
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]254def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
255 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]256 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]257 let ResourceCycles = [2];
258}
259def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]260 let Latency = 19;
261 let NumMicroOps = 3;
262 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]263}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]264
265def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
266 let Latency = 29;
267 let NumMicroOps = 11;
268 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]269}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]270def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
271 let Latency = 33;
272 let NumMicroOps = 11;
273 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]274}
275
276// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]277defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]278
279// Catch-all for expensive system instructions.
280def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
281
282// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]283defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
284defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
285defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]286
287// Old microcoded instructions that nobody use.
288def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
289
290// Fence instructions.
291def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
292
293// Nop, not very useful expect it provides a model for nops!
294def : WriteRes<WriteNop, []>;
295
296////////////////////////////////////////////////////////////////////////////////
297// Horizontal add/sub instructions.
298////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]299
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]300defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
301defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]302
303// Remaining instrs.
304
305def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
306 let Latency = 1;
307 let NumMicroOps = 1;
308 let ResourceCycles = [1];
309}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]310def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
311 "MMX_MOVD64grr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]312 "MMX_PSLLDri",
313 "MMX_PSLLDrr",
314 "MMX_PSLLQri",
315 "MMX_PSLLQrr",
316 "MMX_PSLLWri",
317 "MMX_PSLLWrr",
318 "MMX_PSRADri",
319 "MMX_PSRADrr",
320 "MMX_PSRAWri",
321 "MMX_PSRAWrr",
322 "MMX_PSRLDri",
323 "MMX_PSRLDrr",
324 "MMX_PSRLQri",
325 "MMX_PSRLQrr",
326 "MMX_PSRLWri",
327 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]328 "(V?)MOVPDI2DIrr",
329 "(V?)MOVPQIto64rr",
330 "(V?)PSLLD(Y?)ri",
331 "(V?)PSLLQ(Y?)ri",
332 "VPSLLVQ(Y?)rr",
333 "(V?)PSLLW(Y?)ri",
334 "(V?)PSRAD(Y?)ri",
335 "(V?)PSRAW(Y?)ri",
336 "(V?)PSRLD(Y?)ri",
337 "(V?)PSRLQ(Y?)ri",
338 "VPSRLVQ(Y?)rr",
339 "(V?)PSRLW(Y?)ri",
340 "VTESTPD(Y?)rr",
341 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]342
343def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
344 let Latency = 1;
345 let NumMicroOps = 1;
346 let ResourceCycles = [1];
347}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]348def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
349 "COM_FST0r",
350 "UCOM_FPr",
351 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]352
353def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
354 let Latency = 1;
355 let NumMicroOps = 1;
356 let ResourceCycles = [1];
357}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]358def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]359 "MMX_MOVD64to64rr",
360 "MMX_MOVQ2DQrr",
361 "MMX_PALIGNRrri",
362 "MMX_PSHUFBrr",
363 "MMX_PSHUFWri",
364 "MMX_PUNPCKHBWirr",
365 "MMX_PUNPCKHDQirr",
366 "MMX_PUNPCKHWDirr",
367 "MMX_PUNPCKLBWirr",
368 "MMX_PUNPCKLDQirr",
369 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]370 "(V?)ANDNPD(Y?)rr",
371 "(V?)ANDNPS(Y?)rr",
372 "(V?)ANDPD(Y?)rr",
373 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]374 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]375 "(V?)INSERTPSrr",
376 "(V?)MOV64toPQIrr",
377 "(V?)MOVAPD(Y?)rr",
378 "(V?)MOVAPS(Y?)rr",
379 "(V?)MOVDDUP(Y?)rr",
380 "(V?)MOVDI2PDIrr",
381 "(V?)MOVHLPSrr",
382 "(V?)MOVLHPSrr",
383 "(V?)MOVSDrr",
384 "(V?)MOVSHDUP(Y?)rr",
385 "(V?)MOVSLDUP(Y?)rr",
386 "(V?)MOVSSrr",
387 "(V?)MOVUPD(Y?)rr",
388 "(V?)MOVUPS(Y?)rr",
389 "(V?)ORPD(Y?)rr",
390 "(V?)ORPS(Y?)rr",
391 "(V?)PACKSSDW(Y?)rr",
392 "(V?)PACKSSWB(Y?)rr",
393 "(V?)PACKUSDW(Y?)rr",
394 "(V?)PACKUSWB(Y?)rr",
395 "(V?)PALIGNR(Y?)rri",
396 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]397 "VPBROADCASTDrr",
398 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]399 "VPERMILPD(Y?)ri",
400 "VPERMILPD(Y?)rr",
401 "VPERMILPS(Y?)ri",
402 "VPERMILPS(Y?)rr",
403 "(V?)PMOVSXBDrr",
404 "(V?)PMOVSXBQrr",
405 "(V?)PMOVSXBWrr",
406 "(V?)PMOVSXDQrr",
407 "(V?)PMOVSXWDrr",
408 "(V?)PMOVSXWQrr",
409 "(V?)PMOVZXBDrr",
410 "(V?)PMOVZXBQrr",
411 "(V?)PMOVZXBWrr",
412 "(V?)PMOVZXDQrr",
413 "(V?)PMOVZXWDrr",
414 "(V?)PMOVZXWQrr",
415 "(V?)PSHUFB(Y?)rr",
416 "(V?)PSHUFD(Y?)ri",
417 "(V?)PSHUFHW(Y?)ri",
418 "(V?)PSHUFLW(Y?)ri",
419 "(V?)PSLLDQ(Y?)ri",
420 "(V?)PSRLDQ(Y?)ri",
421 "(V?)PUNPCKHBW(Y?)rr",
422 "(V?)PUNPCKHDQ(Y?)rr",
423 "(V?)PUNPCKHQDQ(Y?)rr",
424 "(V?)PUNPCKHWD(Y?)rr",
425 "(V?)PUNPCKLBW(Y?)rr",
426 "(V?)PUNPCKLDQ(Y?)rr",
427 "(V?)PUNPCKLQDQ(Y?)rr",
428 "(V?)PUNPCKLWD(Y?)rr",
429 "(V?)SHUFPD(Y?)rri",
430 "(V?)SHUFPS(Y?)rri",
431 "(V?)UNPCKHPD(Y?)rr",
432 "(V?)UNPCKHPS(Y?)rr",
433 "(V?)UNPCKLPD(Y?)rr",
434 "(V?)UNPCKLPS(Y?)rr",
435 "(V?)XORPD(Y?)rr",
436 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]437
438def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
439 let Latency = 1;
440 let NumMicroOps = 1;
441 let ResourceCycles = [1];
442}
443def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
444
445def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
446 let Latency = 1;
447 let NumMicroOps = 1;
448 let ResourceCycles = [1];
449}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]450def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
451 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]452
453def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
454 let Latency = 1;
455 let NumMicroOps = 1;
456 let ResourceCycles = [1];
457}
Craig Topperfbe31322018-04-05 21:56:19 +0000[diff] [blame]458def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]459def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
460 "ADC(16|32|64)i",
461 "ADC(8|16|32|64)rr",
462 "ADCX(32|64)rr",
463 "ADOX(32|64)rr",
464 "BT(16|32|64)ri8",
465 "BT(16|32|64)rr",
466 "BTC(16|32|64)ri8",
467 "BTC(16|32|64)rr",
468 "BTR(16|32|64)ri8",
469 "BTR(16|32|64)rr",
470 "BTS(16|32|64)ri8",
471 "BTS(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]472 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]473 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
474 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
475 "JMP_1",
476 "JMP_4",
477 "RORX(32|64)ri",
478 "SAR(8|16|32|64)r1",
479 "SAR(8|16|32|64)ri",
480 "SARX(32|64)rr",
481 "SBB(16|32|64)ri",
482 "SBB(16|32|64)i",
483 "SBB(8|16|32|64)rr",
484 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
485 "SHL(8|16|32|64)r1",
486 "SHL(8|16|32|64)ri",
487 "SHLX(32|64)rr",
488 "SHR(8|16|32|64)r1",
489 "SHR(8|16|32|64)ri",
490 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]491
492def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
493 let Latency = 1;
494 let NumMicroOps = 1;
495 let ResourceCycles = [1];
496}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]497def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
498 "BLSI(32|64)rr",
499 "BLSMSK(32|64)rr",
500 "BLSR(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]501 "LEA(16|32|64)(_32)?r",
502 "MMX_PABSBrr",
503 "MMX_PABSDrr",
504 "MMX_PABSWrr",
505 "MMX_PADDBirr",
506 "MMX_PADDDirr",
507 "MMX_PADDQirr",
508 "MMX_PADDSBirr",
509 "MMX_PADDSWirr",
510 "MMX_PADDUSBirr",
511 "MMX_PADDUSWirr",
512 "MMX_PADDWirr",
513 "MMX_PAVGBirr",
514 "MMX_PAVGWirr",
515 "MMX_PCMPEQBirr",
516 "MMX_PCMPEQDirr",
517 "MMX_PCMPEQWirr",
518 "MMX_PCMPGTBirr",
519 "MMX_PCMPGTDirr",
520 "MMX_PCMPGTWirr",
521 "MMX_PMAXSWirr",
522 "MMX_PMAXUBirr",
523 "MMX_PMINSWirr",
524 "MMX_PMINUBirr",
525 "MMX_PSIGNBrr",
526 "MMX_PSIGNDrr",
527 "MMX_PSIGNWrr",
528 "MMX_PSUBBirr",
529 "MMX_PSUBDirr",
530 "MMX_PSUBQirr",
531 "MMX_PSUBSBirr",
532 "MMX_PSUBSWirr",
533 "MMX_PSUBUSBirr",
534 "MMX_PSUBUSWirr",
535 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]536 "(V?)PABSB(Y?)rr",
537 "(V?)PABSD(Y?)rr",
538 "(V?)PABSW(Y?)rr",
539 "(V?)PADDB(Y?)rr",
540 "(V?)PADDD(Y?)rr",
541 "(V?)PADDQ(Y?)rr",
542 "(V?)PADDSB(Y?)rr",
543 "(V?)PADDSW(Y?)rr",
544 "(V?)PADDUSB(Y?)rr",
545 "(V?)PADDUSW(Y?)rr",
546 "(V?)PADDW(Y?)rr",
547 "(V?)PAVGB(Y?)rr",
548 "(V?)PAVGW(Y?)rr",
549 "(V?)PCMPEQB(Y?)rr",
550 "(V?)PCMPEQD(Y?)rr",
551 "(V?)PCMPEQQ(Y?)rr",
552 "(V?)PCMPEQW(Y?)rr",
553 "(V?)PCMPGTB(Y?)rr",
554 "(V?)PCMPGTD(Y?)rr",
555 "(V?)PCMPGTW(Y?)rr",
556 "(V?)PMAXSB(Y?)rr",
557 "(V?)PMAXSD(Y?)rr",
558 "(V?)PMAXSW(Y?)rr",
559 "(V?)PMAXUB(Y?)rr",
560 "(V?)PMAXUD(Y?)rr",
561 "(V?)PMAXUW(Y?)rr",
562 "(V?)PMINSB(Y?)rr",
563 "(V?)PMINSD(Y?)rr",
564 "(V?)PMINSW(Y?)rr",
565 "(V?)PMINUB(Y?)rr",
566 "(V?)PMINUD(Y?)rr",
567 "(V?)PMINUW(Y?)rr",
568 "(V?)PSIGNB(Y?)rr",
569 "(V?)PSIGND(Y?)rr",
570 "(V?)PSIGNW(Y?)rr",
571 "(V?)PSUBB(Y?)rr",
572 "(V?)PSUBD(Y?)rr",
573 "(V?)PSUBQ(Y?)rr",
574 "(V?)PSUBSB(Y?)rr",
575 "(V?)PSUBSW(Y?)rr",
576 "(V?)PSUBUSB(Y?)rr",
577 "(V?)PSUBUSW(Y?)rr",
578 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]579
580def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
581 let Latency = 1;
582 let NumMicroOps = 1;
583 let ResourceCycles = [1];
584}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]585def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]586 "MMX_PANDNirr",
587 "MMX_PANDirr",
588 "MMX_PORirr",
589 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]590 "(V?)BLENDPD(Y?)rri",
591 "(V?)BLENDPS(Y?)rri",
592 "(V?)MOVDQA(Y?)rr",
593 "(V?)MOVDQU(Y?)rr",
594 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]595 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]596 "(V?)PANDN(Y?)rr",
597 "(V?)PAND(Y?)rr",
598 "VPBLENDD(Y?)rri",
599 "(V?)POR(Y?)rr",
600 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]601
602def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
603 let Latency = 1;
604 let NumMicroOps = 1;
605 let ResourceCycles = [1];
606}
Craig Topperfbe31322018-04-05 21:56:19 +0000[diff] [blame]607def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
Craig Topperf0d04262018-04-06 16:16:48 +0000[diff] [blame^]608def: InstRW<[BWWriteResGroup9], (instregex "CLC",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]609 "CMC",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]610 "LAHF",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]611 "NOOP",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]612 "SAHF",
613 "SGDT64m",
614 "SIDT64m",
615 "SLDT64m",
616 "SMSW16m",
617 "STC",
618 "STRm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]619 "SYSCALL",
Craig Topperf0d04262018-04-06 16:16:48 +0000[diff] [blame^]620 "XCHG(16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]621
622def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
623 let Latency = 1;
624 let NumMicroOps = 2;
625 let ResourceCycles = [1,1];
626}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]627def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
628 "MMX_MOVD64from64rm",
629 "MMX_MOVD64mr",
630 "MMX_MOVNTQmr",
631 "MMX_MOVQ64mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]632 "MOVNTI_64mr",
633 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]634 "ST_FP32m",
635 "ST_FP64m",
636 "ST_FP80m",
637 "VEXTRACTF128mr",
638 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]639 "(V?)MOVAPD(Y?)mr",
640 "(V?)MOVAPS(Y?)mr",
641 "(V?)MOVDQA(Y?)mr",
642 "(V?)MOVDQU(Y?)mr",
643 "(V?)MOVHPDmr",
644 "(V?)MOVHPSmr",
645 "(V?)MOVLPDmr",
646 "(V?)MOVLPSmr",
647 "(V?)MOVNTDQ(V?)mr",
648 "(V?)MOVNTPD(V?)mr",
649 "(V?)MOVNTPS(V?)mr",
650 "(V?)MOVPDI2DImr",
651 "(V?)MOVPQI2QImr",
652 "(V?)MOVPQIto64mr",
653 "(V?)MOVSDmr",
654 "(V?)MOVSSmr",
655 "(V?)MOVUPD(Y?)mr",
656 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]657
658def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
659 let Latency = 2;
660 let NumMicroOps = 2;
661 let ResourceCycles = [2];
662}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]663def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
664 "BLENDVPSrr0",
665 "MMX_PINSRWrr",
666 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]667 "VBLENDVPD(Y?)rr",
668 "VBLENDVPS(Y?)rr",
669 "VPBLENDVB(Y?)rr",
670 "(V?)PINSRBrr",
671 "(V?)PINSRDrr",
672 "(V?)PINSRQrr",
673 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]674
675def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
676 let Latency = 2;
677 let NumMicroOps = 2;
678 let ResourceCycles = [2];
679}
680def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
681
682def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
683 let Latency = 2;
684 let NumMicroOps = 2;
685 let ResourceCycles = [2];
686}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]687def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
688 "ROL(8|16|32|64)ri",
689 "ROR(8|16|32|64)r1",
690 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]691
692def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
693 let Latency = 2;
694 let NumMicroOps = 2;
695 let ResourceCycles = [2];
696}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]697def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
698 "MFENCE",
699 "WAIT",
700 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]701
702def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
703 let Latency = 2;
704 let NumMicroOps = 2;
705 let ResourceCycles = [1,1];
706}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]707def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
708 "VCVTPH2PS(Y?)rr",
709 "(V?)CVTPS2PDrr",
710 "(V?)CVTSS2SDrr",
711 "(V?)EXTRACTPSrr",
712 "(V?)PEXTRBrr",
713 "(V?)PEXTRDrr",
714 "(V?)PEXTRQrr",
715 "(V?)PEXTRWrr",
716 "(V?)PSLLDrr",
717 "(V?)PSLLQrr",
718 "(V?)PSLLWrr",
719 "(V?)PSRADrr",
720 "(V?)PSRAWrr",
721 "(V?)PSRLDrr",
722 "(V?)PSRLQrr",
723 "(V?)PSRLWrr",
724 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]725
726def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
727 let Latency = 2;
728 let NumMicroOps = 2;
729 let ResourceCycles = [1,1];
730}
731def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
732
733def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
734 let Latency = 2;
735 let NumMicroOps = 2;
736 let ResourceCycles = [1,1];
737}
738def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
739
740def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
741 let Latency = 2;
742 let NumMicroOps = 2;
743 let ResourceCycles = [1,1];
744}
745def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
746
747def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
748 let Latency = 2;
749 let NumMicroOps = 2;
750 let ResourceCycles = [1,1];
751}
Craig Topper498875f2018-04-04 17:54:19 +0000[diff] [blame]752def: InstRW<[BWWriteResGroup19], (instrs BSWAP64r)>;
753
754def BWWriteResGroup19_1 : SchedWriteRes<[BWPort15]> {
755 let Latency = 1;
756 let NumMicroOps = 1;
757 let ResourceCycles = [1];
758}
759def: InstRW<[BWWriteResGroup19_1], (instrs BSWAP32r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]760
761def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
762 let Latency = 2;
763 let NumMicroOps = 2;
764 let ResourceCycles = [1,1];
765}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]766def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]767def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]768def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
769 "ADC8ri",
770 "CMOV(A|BE)(16|32|64)rr",
771 "SBB8i8",
772 "SBB8ri",
773 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]774
775def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
776 let Latency = 2;
777 let NumMicroOps = 3;
778 let ResourceCycles = [1,1,1];
779}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]780def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
781 "(V?)PEXTRBmr",
782 "(V?)PEXTRDmr",
783 "(V?)PEXTRQmr",
784 "(V?)PEXTRWmr",
785 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]786
787def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
788 let Latency = 2;
789 let NumMicroOps = 3;
790 let ResourceCycles = [1,1,1];
791}
792def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
793
794def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
795 let Latency = 2;
796 let NumMicroOps = 3;
797 let ResourceCycles = [1,1,1];
798}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]799def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]800
801def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
802 let Latency = 2;
803 let NumMicroOps = 3;
804 let ResourceCycles = [1,1,1];
805}
806def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
807
808def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
809 let Latency = 2;
810 let NumMicroOps = 3;
811 let ResourceCycles = [1,1,1];
812}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]813def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]814def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
815 "PUSH64i8",
816 "STOSB",
817 "STOSL",
818 "STOSQ",
819 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]820
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]821def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
822 let Latency = 3;
823 let NumMicroOps = 1;
824 let ResourceCycles = [1];
825}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]826def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]827def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]828def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]829 "ADD_FST0r",
830 "ADD_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]831 "MMX_CVTPI2PSirr",
832 "PDEP(32|64)rr",
833 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]834 "SHLD(16|32|64)rri8",
835 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]836 "SUBR_FPrST0",
837 "SUBR_FST0r",
838 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]839 "SUB_FPrST0",
840 "SUB_FST0r",
841 "SUB_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]842 "(V?)ADDPD(Y?)rr",
843 "(V?)ADDPS(Y?)rr",
844 "(V?)ADDSDrr",
845 "(V?)ADDSSrr",
846 "(V?)ADDSUBPD(Y?)rr",
847 "(V?)ADDSUBPS(Y?)rr",
848 "(V?)CMPPD(Y?)rri",
849 "(V?)CMPPS(Y?)rri",
850 "(V?)CMPSDrr",
851 "(V?)CMPSSrr",
852 "(V?)COMISDrr",
853 "(V?)COMISSrr",
854 "(V?)CVTDQ2PS(Y?)rr",
855 "(V?)CVTPS2DQ(Y?)rr",
856 "(V?)CVTTPS2DQ(Y?)rr",
857 "(V?)MAX(C?)PD(Y?)rr",
858 "(V?)MAX(C?)PS(Y?)rr",
859 "(V?)MAX(C?)SDrr",
860 "(V?)MAX(C?)SSrr",
861 "(V?)MIN(C?)PD(Y?)rr",
862 "(V?)MIN(C?)PS(Y?)rr",
863 "(V?)MIN(C?)SDrr",
864 "(V?)MIN(C?)SSrr",
865 "(V?)SUBPD(Y?)rr",
866 "(V?)SUBPS(Y?)rr",
867 "(V?)SUBSDrr",
868 "(V?)SUBSSrr",
869 "(V?)UCOMISDrr",
870 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]871
872def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
873 let Latency = 3;
874 let NumMicroOps = 2;
875 let ResourceCycles = [1,1];
876}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]877def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]878
879def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
880 let Latency = 3;
881 let NumMicroOps = 1;
882 let ResourceCycles = [1];
883}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]884def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
885 "VBROADCASTSSYrr",
886 "VEXTRACTF128rr",
887 "VEXTRACTI128rr",
888 "VINSERTF128rr",
889 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]890 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]891 "VPBROADCASTDYrr",
892 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]893 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]894 "VPERM2F128rr",
895 "VPERM2I128rr",
896 "VPERMDYrr",
897 "VPERMPDYri",
898 "VPERMPSYrr",
899 "VPERMQYri",
900 "VPMOVSXBDYrr",
901 "VPMOVSXBQYrr",
902 "VPMOVSXBWYrr",
903 "VPMOVSXDQYrr",
904 "VPMOVSXWDYrr",
905 "VPMOVSXWQYrr",
906 "VPMOVZXBDYrr",
907 "VPMOVZXBQYrr",
908 "VPMOVZXBWYrr",
909 "VPMOVZXDQYrr",
910 "VPMOVZXWDYrr",
911 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]912
913def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
914 let Latency = 3;
915 let NumMicroOps = 1;
916 let ResourceCycles = [1];
917}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]918def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
919 "(V?)MULPS(Y?)rr",
920 "(V?)MULSDrr",
921 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]922
923def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
924 let Latency = 3;
925 let NumMicroOps = 3;
926 let ResourceCycles = [3];
927}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]928def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
929 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]930
931def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
932 let Latency = 3;
933 let NumMicroOps = 3;
934 let ResourceCycles = [2,1];
935}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]936def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
937 "VPSRAVD(Y?)rr",
938 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]939
940def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
941 let Latency = 3;
942 let NumMicroOps = 3;
943 let ResourceCycles = [2,1];
944}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]945def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
946 "MMX_PHADDSWrr",
947 "MMX_PHADDWrr",
948 "MMX_PHSUBDrr",
949 "MMX_PHSUBSWrr",
950 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]951 "(V?)PHADDD(Y?)rr",
952 "(V?)PHADDSW(Y?)rr",
953 "(V?)PHADDW(Y?)rr",
954 "(V?)PHSUBD(Y?)rr",
955 "(V?)PHSUBSW(Y?)rr",
956 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]957
958def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
959 let Latency = 3;
960 let NumMicroOps = 3;
961 let ResourceCycles = [2,1];
962}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]963def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
964 "MMX_PACKSSWBirr",
965 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]966
967def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
968 let Latency = 3;
969 let NumMicroOps = 3;
970 let ResourceCycles = [1,2];
971}
972def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
973
974def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
975 let Latency = 3;
976 let NumMicroOps = 3;
977 let ResourceCycles = [1,2];
978}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]979def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
980 "RCL(8|16|32|64)ri",
981 "RCR(8|16|32|64)r1",
982 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]983
984def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
985 let Latency = 3;
986 let NumMicroOps = 3;
987 let ResourceCycles = [2,1];
988}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]989def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
990 "ROR(8|16|32|64)rCL",
991 "SAR(8|16|32|64)rCL",
992 "SHL(8|16|32|64)rCL",
993 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]994
995def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
996 let Latency = 3;
997 let NumMicroOps = 4;
998 let ResourceCycles = [1,1,1,1];
999}
1000def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1001
1002def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1003 let Latency = 3;
1004 let NumMicroOps = 4;
1005 let ResourceCycles = [1,1,1,1];
1006}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1007def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1008 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1009
1010def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1011 let Latency = 4;
1012 let NumMicroOps = 2;
1013 let ResourceCycles = [1,1];
1014}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1015def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1016 "(V?)CVTSD2SIrr",
1017 "(V?)CVTSS2SI64rr",
1018 "(V?)CVTSS2SIrr",
1019 "(V?)CVTTSD2SI64rr",
1020 "(V?)CVTTSD2SIrr",
1021 "(V?)CVTTSS2SI64rr",
1022 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1023
1024def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1025 let Latency = 4;
1026 let NumMicroOps = 2;
1027 let ResourceCycles = [1,1];
1028}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1029def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1030 "VPSLLDYrr",
1031 "VPSLLQYrr",
1032 "VPSLLWYrr",
1033 "VPSRADYrr",
1034 "VPSRAWYrr",
1035 "VPSRLDYrr",
1036 "VPSRLQYrr",
1037 "VPSRLWYrr",
1038 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1039
1040def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1041 let Latency = 4;
1042 let NumMicroOps = 2;
1043 let ResourceCycles = [1,1];
1044}
1045def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1046
1047def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1048 let Latency = 4;
1049 let NumMicroOps = 2;
1050 let ResourceCycles = [1,1];
1051}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1052def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1053def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1054 "MMX_CVTPI2PDirr",
1055 "MMX_CVTPS2PIirr",
1056 "MMX_CVTTPD2PIirr",
1057 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1058 "(V?)CVTDQ2PDrr",
1059 "(V?)CVTPD2DQrr",
1060 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1061 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1062 "(V?)CVTSD2SSrr",
1063 "(V?)CVTSI642SDrr",
1064 "(V?)CVTSI2SDrr",
1065 "(V?)CVTSI2SSrr",
1066 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1067
1068def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1069 let Latency = 4;
1070 let NumMicroOps = 4;
1071}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1072def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1073
1074def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1075 let Latency = 4;
1076 let NumMicroOps = 3;
1077 let ResourceCycles = [1,1,1];
1078}
1079def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1080
1081def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1082 let Latency = 4;
1083 let NumMicroOps = 3;
1084 let ResourceCycles = [1,1,1];
1085}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1086def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1087 "ISTT_FP32m",
1088 "ISTT_FP64m",
1089 "IST_F16m",
1090 "IST_F32m",
1091 "IST_FP16m",
1092 "IST_FP32m",
1093 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1094 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1095
1096def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1097 let Latency = 4;
1098 let NumMicroOps = 4;
1099 let ResourceCycles = [4];
1100}
1101def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1102
1103def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1104 let Latency = 4;
1105 let NumMicroOps = 4;
1106 let ResourceCycles = [1,3];
1107}
1108def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1109
1110def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1111 let Latency = 5;
1112 let NumMicroOps = 1;
1113 let ResourceCycles = [1];
1114}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1115def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1116 "MMX_PMADDWDirr",
1117 "MMX_PMULHRSWrr",
1118 "MMX_PMULHUWirr",
1119 "MMX_PMULHWirr",
1120 "MMX_PMULLWirr",
1121 "MMX_PMULUDQirr",
1122 "MMX_PSADBWirr",
1123 "MUL_FPrST0",
1124 "MUL_FST0r",
1125 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1126 "(V?)PCMPGTQ(Y?)rr",
1127 "(V?)PHMINPOSUWrr",
1128 "(V?)PMADDUBSW(Y?)rr",
1129 "(V?)PMADDWD(Y?)rr",
1130 "(V?)PMULDQ(Y?)rr",
1131 "(V?)PMULHRSW(Y?)rr",
1132 "(V?)PMULHUW(Y?)rr",
1133 "(V?)PMULHW(Y?)rr",
1134 "(V?)PMULLW(Y?)rr",
1135 "(V?)PMULUDQ(Y?)rr",
1136 "(V?)PSADBW(Y?)rr",
1137 "(V?)RCPPSr",
1138 "(V?)RCPSSr",
1139 "(V?)RSQRTPSr",
1140 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1141
1142def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1143 let Latency = 5;
1144 let NumMicroOps = 1;
1145 let ResourceCycles = [1];
1146}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1147def: InstRW<[BWWriteResGroup48],
1148 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1149 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1150
1151def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1152 let Latency = 5;
1153 let NumMicroOps = 1;
1154 let ResourceCycles = [1];
1155}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1156def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1157 "MMX_MOVD64to64rm",
1158 "MMX_MOVQ64rm",
1159 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1160 "MOVSX(16|32|64)rm16",
1161 "MOVSX(16|32|64)rm32",
1162 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1163 "MOVZX(16|32|64)rm16",
1164 "MOVZX(16|32|64)rm8",
1165 "PREFETCHNTA",
1166 "PREFETCHT0",
1167 "PREFETCHT1",
1168 "PREFETCHT2",
1169 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1170 "(V?)LDDQUrm",
1171 "(V?)MOV64toPQIrm",
1172 "(V?)MOVAPDrm",
1173 "(V?)MOVAPSrm",
1174 "(V?)MOVDDUPrm",
1175 "(V?)MOVDI2PDIrm",
1176 "(V?)MOVDQArm",
1177 "(V?)MOVDQUrm",
1178 "(V?)MOVNTDQArm",
1179 "(V?)MOVQI2PQIrm",
1180 "(V?)MOVSDrm",
1181 "(V?)MOVSHDUPrm",
1182 "(V?)MOVSLDUPrm",
1183 "(V?)MOVSSrm",
1184 "(V?)MOVUPDrm",
1185 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1186 "VPBROADCASTDrm",
1187 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1188
1189def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1190 let Latency = 5;
1191 let NumMicroOps = 3;
1192 let ResourceCycles = [1,2];
1193}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1194def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1195 "(V?)HADDPD(Y?)rr",
1196 "(V?)HADDPS(Y?)rr",
1197 "(V?)HSUBPD(Y?)rr",
1198 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1199
1200def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1201 let Latency = 5;
1202 let NumMicroOps = 3;
1203 let ResourceCycles = [1,1,1];
1204}
1205def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1206
1207def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1208 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1209 let NumMicroOps = 3;
1210 let ResourceCycles = [1,1,1];
1211}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1212def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1213
1214def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1215 let Latency = 5;
1216 let NumMicroOps = 4;
1217 let ResourceCycles = [1,1,1,1];
1218}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1219def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1220 "VMASKMOVPS(Y?)mr",
1221 "VPMASKMOVD(Y?)mr",
1222 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1223
1224def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1225 let Latency = 5;
1226 let NumMicroOps = 5;
1227 let ResourceCycles = [1,4];
1228}
1229def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1230
1231def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1232 let Latency = 5;
1233 let NumMicroOps = 5;
1234 let ResourceCycles = [1,4];
1235}
1236def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1237
1238def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1239 let Latency = 5;
1240 let NumMicroOps = 5;
1241 let ResourceCycles = [2,3];
1242}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1243def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1244
1245def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1246 let Latency = 5;
1247 let NumMicroOps = 6;
1248 let ResourceCycles = [1,1,4];
1249}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1250def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1251
1252def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1253 let Latency = 6;
1254 let NumMicroOps = 1;
1255 let ResourceCycles = [1];
1256}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1257def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1258 "LD_F64m",
1259 "LD_F80m",
1260 "VBROADCASTF128",
1261 "VBROADCASTI128",
1262 "VBROADCASTSDYrm",
1263 "VBROADCASTSSYrm",
1264 "VLDDQUYrm",
1265 "VMOVAPDYrm",
1266 "VMOVAPSYrm",
1267 "VMOVDDUPYrm",
1268 "VMOVDQAYrm",
1269 "VMOVDQUYrm",
1270 "VMOVNTDQAYrm",
1271 "VMOVSHDUPYrm",
1272 "VMOVSLDUPYrm",
1273 "VMOVUPDYrm",
1274 "VMOVUPSYrm",
1275 "VPBROADCASTDYrm",
1276 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1277 "(V?)ROUNDPD(Y?)r",
1278 "(V?)ROUNDPS(Y?)r",
1279 "(V?)ROUNDSDr",
1280 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1281
1282def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1283 let Latency = 6;
1284 let NumMicroOps = 2;
1285 let ResourceCycles = [1,1];
1286}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1287def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1288 "MMX_PSLLQrm",
1289 "MMX_PSLLWrm",
1290 "MMX_PSRADrm",
1291 "MMX_PSRAWrm",
1292 "MMX_PSRLDrm",
1293 "MMX_PSRLQrm",
1294 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1295 "VCVTPH2PS(Y?)rm",
1296 "(V?)CVTPS2PDrm",
1297 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1298 "VPSLLVQrm",
1299 "VPSRLVQrm",
1300 "VTESTPDrm",
1301 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1302
1303def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1304 let Latency = 6;
1305 let NumMicroOps = 2;
1306 let ResourceCycles = [1,1];
1307}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1308def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1309 "VCVTPD2DQYrr",
1310 "VCVTPD2PSYrr",
1311 "VCVTPS2PHYrr",
1312 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1313
1314def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1315 let Latency = 6;
1316 let NumMicroOps = 2;
1317 let ResourceCycles = [1,1];
1318}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1319def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1320 "MMX_PINSRWrm",
1321 "MMX_PSHUFBrm",
1322 "MMX_PSHUFWmi",
1323 "MMX_PUNPCKHBWirm",
1324 "MMX_PUNPCKHDQirm",
1325 "MMX_PUNPCKHWDirm",
1326 "MMX_PUNPCKLBWirm",
1327 "MMX_PUNPCKLDQirm",
1328 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1329 "(V?)ANDNPDrm",
1330 "(V?)ANDNPSrm",
1331 "(V?)ANDPDrm",
1332 "(V?)ANDPSrm",
1333 "(V?)INSERTPSrm",
1334 "(V?)MOVHPDrm",
1335 "(V?)MOVHPSrm",
1336 "(V?)MOVLPDrm",
1337 "(V?)MOVLPSrm",
1338 "(V?)ORPDrm",
1339 "(V?)ORPSrm",
1340 "(V?)PACKSSDWrm",
1341 "(V?)PACKSSWBrm",
1342 "(V?)PACKUSDWrm",
1343 "(V?)PACKUSWBrm",
1344 "(V?)PALIGNRrmi",
1345 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1346 "VPERMILPDmi",
1347 "VPERMILPDrm",
1348 "VPERMILPSmi",
1349 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1350 "(V?)PINSRBrm",
1351 "(V?)PINSRDrm",
1352 "(V?)PINSRQrm",
1353 "(V?)PINSRWrm",
1354 "(V?)PMOVSXBDrm",
1355 "(V?)PMOVSXBQrm",
1356 "(V?)PMOVSXBWrm",
1357 "(V?)PMOVSXDQrm",
1358 "(V?)PMOVSXWDrm",
1359 "(V?)PMOVSXWQrm",
1360 "(V?)PMOVZXBDrm",
1361 "(V?)PMOVZXBQrm",
1362 "(V?)PMOVZXBWrm",
1363 "(V?)PMOVZXDQrm",
1364 "(V?)PMOVZXWDrm",
1365 "(V?)PMOVZXWQrm",
1366 "(V?)PSHUFBrm",
1367 "(V?)PSHUFDmi",
1368 "(V?)PSHUFHWmi",
1369 "(V?)PSHUFLWmi",
1370 "(V?)PUNPCKHBWrm",
1371 "(V?)PUNPCKHDQrm",
1372 "(V?)PUNPCKHQDQrm",
1373 "(V?)PUNPCKHWDrm",
1374 "(V?)PUNPCKLBWrm",
1375 "(V?)PUNPCKLDQrm",
1376 "(V?)PUNPCKLQDQrm",
1377 "(V?)PUNPCKLWDrm",
1378 "(V?)SHUFPDrmi",
1379 "(V?)SHUFPSrmi",
1380 "(V?)UNPCKHPDrm",
1381 "(V?)UNPCKHPSrm",
1382 "(V?)UNPCKLPDrm",
1383 "(V?)UNPCKLPSrm",
1384 "(V?)XORPDrm",
1385 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1386
1387def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1388 let Latency = 6;
1389 let NumMicroOps = 2;
1390 let ResourceCycles = [1,1];
1391}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1392def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1393 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1394
1395def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1396 let Latency = 6;
1397 let NumMicroOps = 2;
1398 let ResourceCycles = [1,1];
1399}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1400def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1401 "ADCX(32|64)rm",
1402 "ADOX(32|64)rm",
1403 "BT(16|32|64)mi8",
1404 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1405 "RORX(32|64)mi",
1406 "SARX(32|64)rm",
1407 "SBB(8|16|32|64)rm",
1408 "SHLX(32|64)rm",
1409 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1410
1411def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1412 let Latency = 6;
1413 let NumMicroOps = 2;
1414 let ResourceCycles = [1,1];
1415}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1416def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1417 "BLSI(32|64)rm",
1418 "BLSMSK(32|64)rm",
1419 "BLSR(32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1420 "MMX_PABSBrm",
1421 "MMX_PABSDrm",
1422 "MMX_PABSWrm",
1423 "MMX_PADDBirm",
1424 "MMX_PADDDirm",
1425 "MMX_PADDQirm",
1426 "MMX_PADDSBirm",
1427 "MMX_PADDSWirm",
1428 "MMX_PADDUSBirm",
1429 "MMX_PADDUSWirm",
1430 "MMX_PADDWirm",
1431 "MMX_PAVGBirm",
1432 "MMX_PAVGWirm",
1433 "MMX_PCMPEQBirm",
1434 "MMX_PCMPEQDirm",
1435 "MMX_PCMPEQWirm",
1436 "MMX_PCMPGTBirm",
1437 "MMX_PCMPGTDirm",
1438 "MMX_PCMPGTWirm",
1439 "MMX_PMAXSWirm",
1440 "MMX_PMAXUBirm",
1441 "MMX_PMINSWirm",
1442 "MMX_PMINUBirm",
1443 "MMX_PSIGNBrm",
1444 "MMX_PSIGNDrm",
1445 "MMX_PSIGNWrm",
1446 "MMX_PSUBBirm",
1447 "MMX_PSUBDirm",
1448 "MMX_PSUBQirm",
1449 "MMX_PSUBSBirm",
1450 "MMX_PSUBSWirm",
1451 "MMX_PSUBUSBirm",
1452 "MMX_PSUBUSWirm",
1453 "MMX_PSUBWirm",
1454 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1455 "(V?)PABSBrm",
1456 "(V?)PABSDrm",
1457 "(V?)PABSWrm",
1458 "(V?)PADDBrm",
1459 "(V?)PADDDrm",
1460 "(V?)PADDQrm",
1461 "(V?)PADDSBrm",
1462 "(V?)PADDSWrm",
1463 "(V?)PADDUSBrm",
1464 "(V?)PADDUSWrm",
1465 "(V?)PADDWrm",
1466 "(V?)PAVGBrm",
1467 "(V?)PAVGWrm",
1468 "(V?)PCMPEQBrm",
1469 "(V?)PCMPEQDrm",
1470 "(V?)PCMPEQQrm",
1471 "(V?)PCMPEQWrm",
1472 "(V?)PCMPGTBrm",
1473 "(V?)PCMPGTDrm",
1474 "(V?)PCMPGTWrm",
1475 "(V?)PMAXSBrm",
1476 "(V?)PMAXSDrm",
1477 "(V?)PMAXSWrm",
1478 "(V?)PMAXUBrm",
1479 "(V?)PMAXUDrm",
1480 "(V?)PMAXUWrm",
1481 "(V?)PMINSBrm",
1482 "(V?)PMINSDrm",
1483 "(V?)PMINSWrm",
1484 "(V?)PMINUBrm",
1485 "(V?)PMINUDrm",
1486 "(V?)PMINUWrm",
1487 "(V?)PSIGNBrm",
1488 "(V?)PSIGNDrm",
1489 "(V?)PSIGNWrm",
1490 "(V?)PSUBBrm",
1491 "(V?)PSUBDrm",
1492 "(V?)PSUBQrm",
1493 "(V?)PSUBSBrm",
1494 "(V?)PSUBSWrm",
1495 "(V?)PSUBUSBrm",
1496 "(V?)PSUBUSWrm",
1497 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1498
1499def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1500 let Latency = 6;
1501 let NumMicroOps = 2;
1502 let ResourceCycles = [1,1];
1503}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1504def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1505 "MMX_PANDirm",
1506 "MMX_PORirm",
1507 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1508 "(V?)BLENDPDrmi",
1509 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1510 "VINSERTF128rm",
1511 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1512 "(V?)PANDNrm",
1513 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1514 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1515 "(V?)PORrm",
1516 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1517
1518def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1519 let Latency = 6;
1520 let NumMicroOps = 2;
1521 let ResourceCycles = [1,1];
1522}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1523def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topperf0d04262018-04-06 16:16:48 +0000[diff] [blame^]1524def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1525
1526def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1527 let Latency = 6;
1528 let NumMicroOps = 4;
1529 let ResourceCycles = [1,1,2];
1530}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1531def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1532 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1533
1534def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1535 let Latency = 6;
1536 let NumMicroOps = 4;
1537 let ResourceCycles = [1,1,1,1];
1538}
1539def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1540
1541def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1542 let Latency = 6;
1543 let NumMicroOps = 4;
1544 let ResourceCycles = [1,1,1,1];
1545}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1546def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1547 "BTR(16|32|64)mi8",
1548 "BTS(16|32|64)mi8",
1549 "SAR(8|16|32|64)m1",
1550 "SAR(8|16|32|64)mi",
1551 "SHL(8|16|32|64)m1",
1552 "SHL(8|16|32|64)mi",
1553 "SHR(8|16|32|64)m1",
1554 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1555
1556def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1557 let Latency = 6;
1558 let NumMicroOps = 4;
1559 let ResourceCycles = [1,1,1,1];
1560}
Craig Topperf0d04262018-04-06 16:16:48 +0000[diff] [blame^]1561def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1562 "PUSH(16|32|64)rmm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1563
1564def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1565 let Latency = 6;
1566 let NumMicroOps = 6;
1567 let ResourceCycles = [1,5];
1568}
1569def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1570
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1571def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1572 let Latency = 7;
1573 let NumMicroOps = 2;
1574 let ResourceCycles = [1,1];
1575}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1576def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1577 "VPSLLQYrm",
1578 "VPSLLVQYrm",
1579 "VPSLLWYrm",
1580 "VPSRADYrm",
1581 "VPSRAWYrm",
1582 "VPSRLDYrm",
1583 "VPSRLQYrm",
1584 "VPSRLVQYrm",
1585 "VPSRLWYrm",
1586 "VTESTPDYrm",
1587 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1588
1589def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1590 let Latency = 7;
1591 let NumMicroOps = 2;
1592 let ResourceCycles = [1,1];
1593}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1594def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1595 "FCOM64m",
1596 "FCOMP32m",
1597 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1598
1599def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1600 let Latency = 7;
1601 let NumMicroOps = 2;
1602 let ResourceCycles = [1,1];
1603}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1604def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1605 "VANDNPSYrm",
1606 "VANDPDYrm",
1607 "VANDPSYrm",
1608 "VORPDYrm",
1609 "VORPSYrm",
1610 "VPACKSSDWYrm",
1611 "VPACKSSWBYrm",
1612 "VPACKUSDWYrm",
1613 "VPACKUSWBYrm",
1614 "VPALIGNRYrmi",
1615 "VPBLENDWYrmi",
1616 "VPERMILPDYmi",
1617 "VPERMILPDYrm",
1618 "VPERMILPSYmi",
1619 "VPERMILPSYrm",
1620 "VPSHUFBYrm",
1621 "VPSHUFDYmi",
1622 "VPSHUFHWYmi",
1623 "VPSHUFLWYmi",
1624 "VPUNPCKHBWYrm",
1625 "VPUNPCKHDQYrm",
1626 "VPUNPCKHQDQYrm",
1627 "VPUNPCKHWDYrm",
1628 "VPUNPCKLBWYrm",
1629 "VPUNPCKLDQYrm",
1630 "VPUNPCKLQDQYrm",
1631 "VPUNPCKLWDYrm",
1632 "VSHUFPDYrmi",
1633 "VSHUFPSYrmi",
1634 "VUNPCKHPDYrm",
1635 "VUNPCKHPSYrm",
1636 "VUNPCKLPDYrm",
1637 "VUNPCKLPSYrm",
1638 "VXORPDYrm",
1639 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1640
1641def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1642 let Latency = 7;
1643 let NumMicroOps = 2;
1644 let ResourceCycles = [1,1];
1645}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1646def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1647 "VPABSDYrm",
1648 "VPABSWYrm",
1649 "VPADDBYrm",
1650 "VPADDDYrm",
1651 "VPADDQYrm",
1652 "VPADDSBYrm",
1653 "VPADDSWYrm",
1654 "VPADDUSBYrm",
1655 "VPADDUSWYrm",
1656 "VPADDWYrm",
1657 "VPAVGBYrm",
1658 "VPAVGWYrm",
1659 "VPCMPEQBYrm",
1660 "VPCMPEQDYrm",
1661 "VPCMPEQQYrm",
1662 "VPCMPEQWYrm",
1663 "VPCMPGTBYrm",
1664 "VPCMPGTDYrm",
1665 "VPCMPGTWYrm",
1666 "VPMAXSBYrm",
1667 "VPMAXSDYrm",
1668 "VPMAXSWYrm",
1669 "VPMAXUBYrm",
1670 "VPMAXUDYrm",
1671 "VPMAXUWYrm",
1672 "VPMINSBYrm",
1673 "VPMINSDYrm",
1674 "VPMINSWYrm",
1675 "VPMINUBYrm",
1676 "VPMINUDYrm",
1677 "VPMINUWYrm",
1678 "VPSIGNBYrm",
1679 "VPSIGNDYrm",
1680 "VPSIGNWYrm",
1681 "VPSUBBYrm",
1682 "VPSUBDYrm",
1683 "VPSUBQYrm",
1684 "VPSUBSBYrm",
1685 "VPSUBSWYrm",
1686 "VPSUBUSBYrm",
1687 "VPSUBUSWYrm",
1688 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1689
1690def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1691 let Latency = 7;
1692 let NumMicroOps = 2;
1693 let ResourceCycles = [1,1];
1694}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1695def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1696 "VBLENDPSYrmi",
1697 "VPANDNYrm",
1698 "VPANDYrm",
1699 "VPBLENDDYrmi",
1700 "VPORYrm",
1701 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1702
1703def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1704 let Latency = 7;
1705 let NumMicroOps = 3;
1706 let ResourceCycles = [1,2];
1707}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1708def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1709
1710def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1711 let Latency = 7;
1712 let NumMicroOps = 3;
1713 let ResourceCycles = [2,1];
1714}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1715def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1716 "BLENDVPSrm0",
1717 "MMX_PACKSSDWirm",
1718 "MMX_PACKSSWBirm",
1719 "MMX_PACKUSWBirm",
1720 "PBLENDVBrm0",
1721 "VBLENDVPDrm",
1722 "VBLENDVPSrm",
1723 "VMASKMOVPDrm",
1724 "VMASKMOVPSrm",
1725 "VPBLENDVBrm",
1726 "VPMASKMOVDrm",
1727 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1728
1729def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1730 let Latency = 7;
1731 let NumMicroOps = 3;
1732 let ResourceCycles = [1,2];
1733}
Craig Topper3b0b96c2018-04-05 21:16:26 +0000[diff] [blame]1734def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1735 SCASB, SCASL, SCASQ, SCASW)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1736
1737def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1738 let Latency = 7;
1739 let NumMicroOps = 3;
1740 let ResourceCycles = [1,1,1];
1741}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1742def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1743 "PSLLQrm",
1744 "PSLLWrm",
1745 "PSRADrm",
1746 "PSRAWrm",
1747 "PSRLDrm",
1748 "PSRLQrm",
1749 "PSRLWrm",
1750 "PTESTrm",
1751 "VPSLLDrm",
1752 "VPSLLQrm",
1753 "VPSLLWrm",
1754 "VPSRADrm",
1755 "VPSRAWrm",
1756 "VPSRLDrm",
1757 "VPSRLQrm",
1758 "VPSRLWrm",
1759 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1760
1761def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1762 let Latency = 7;
1763 let NumMicroOps = 3;
1764 let ResourceCycles = [1,1,1];
1765}
1766def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1767
1768def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1769 let Latency = 7;
1770 let NumMicroOps = 3;
1771 let ResourceCycles = [1,1,1];
1772}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1773def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1774
1775def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1776 let Latency = 7;
1777 let NumMicroOps = 3;
1778 let ResourceCycles = [1,1,1];
1779}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1780def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1781 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1782
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1783def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1784 let Latency = 7;
1785 let NumMicroOps = 3;
1786 let ResourceCycles = [1,1,1];
1787}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1788def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1789
1790def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1791 let Latency = 7;
1792 let NumMicroOps = 5;
1793 let ResourceCycles = [1,1,1,2];
1794}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1795def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1796 "ROL(8|16|32|64)mi",
1797 "ROR(8|16|32|64)m1",
1798 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1799
1800def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1801 let Latency = 7;
1802 let NumMicroOps = 5;
1803 let ResourceCycles = [1,1,1,2];
1804}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1805def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1806
1807def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1808 let Latency = 7;
1809 let NumMicroOps = 5;
1810 let ResourceCycles = [1,1,1,1,1];
1811}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1812def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1813 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1814
1815def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1816 let Latency = 7;
1817 let NumMicroOps = 7;
1818 let ResourceCycles = [2,2,1,2];
1819}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1820def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1821
1822def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1823 let Latency = 8;
1824 let NumMicroOps = 2;
1825 let ResourceCycles = [1,1];
1826}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1827def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1828def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]1829def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1830 "MMX_CVTPS2PIirm",
1831 "MMX_CVTTPS2PIirm",
1832 "PDEP(32|64)rm",
1833 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1834 "(V?)ADDPDrm",
1835 "(V?)ADDPSrm",
1836 "(V?)ADDSDrm",
1837 "(V?)ADDSSrm",
1838 "(V?)ADDSUBPDrm",
1839 "(V?)ADDSUBPSrm",
1840 "(V?)CMPPDrmi",
1841 "(V?)CMPPSrmi",
1842 "(V?)CMPSDrm",
1843 "(V?)CMPSSrm",
1844 "(V?)COMISDrm",
1845 "(V?)COMISSrm",
1846 "(V?)CVTDQ2PSrm",
1847 "(V?)CVTPS2DQrm",
1848 "(V?)CVTTPS2DQrm",
1849 "(V?)MAX(C?)PDrm",
1850 "(V?)MAX(C?)PSrm",
1851 "(V?)MAX(C?)SDrm",
1852 "(V?)MAX(C?)SSrm",
1853 "(V?)MIN(C?)PDrm",
1854 "(V?)MIN(C?)PSrm",
1855 "(V?)MIN(C?)SDrm",
1856 "(V?)MIN(C?)SSrm",
1857 "(V?)SUBPDrm",
1858 "(V?)SUBPSrm",
1859 "(V?)SUBSDrm",
1860 "(V?)SUBSSrm",
1861 "(V?)UCOMISDrm",
1862 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1863
1864def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1865 let Latency = 8;
1866 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1867 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1868}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1869def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1870
1871def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1872 let Latency = 8;
1873 let NumMicroOps = 5;
1874}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1875def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1876
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1877def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1878 let Latency = 8;
1879 let NumMicroOps = 2;
1880 let ResourceCycles = [1,1];
1881}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1882def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1883 "VPMOVSXBQYrm",
1884 "VPMOVSXBWYrm",
1885 "VPMOVSXDQYrm",
1886 "VPMOVSXWDYrm",
1887 "VPMOVSXWQYrm",
1888 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1889
1890def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1891 let Latency = 8;
1892 let NumMicroOps = 2;
1893 let ResourceCycles = [1,1];
1894}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1895def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1896 "(V?)MULPSrm",
1897 "(V?)MULSDrm",
1898 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1899
1900def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1901 let Latency = 8;
1902 let NumMicroOps = 3;
1903 let ResourceCycles = [2,1];
1904}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1905def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1906 "VBLENDVPSYrm",
1907 "VMASKMOVPDYrm",
1908 "VMASKMOVPSYrm",
1909 "VPBLENDVBYrm",
1910 "VPMASKMOVDYrm",
1911 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1912
1913def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1914 let Latency = 8;
1915 let NumMicroOps = 4;
1916 let ResourceCycles = [2,1,1];
1917}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1918def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1919 "VPSRAVDrm",
1920 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1921
1922def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1923 let Latency = 8;
1924 let NumMicroOps = 4;
1925 let ResourceCycles = [2,1,1];
1926}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1927def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1928 "MMX_PHADDSWrm",
1929 "MMX_PHADDWrm",
1930 "MMX_PHSUBDrm",
1931 "MMX_PHSUBSWrm",
1932 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1933 "(V?)PHADDDrm",
1934 "(V?)PHADDSWrm",
1935 "(V?)PHADDWrm",
1936 "(V?)PHSUBDrm",
1937 "(V?)PHSUBSWrm",
1938 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1939
1940def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1941 let Latency = 8;
1942 let NumMicroOps = 5;
1943 let ResourceCycles = [1,1,1,2];
1944}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1945def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
1946 "RCL(8|16|32|64)mi",
1947 "RCR(8|16|32|64)m1",
1948 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1949
1950def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1951 let Latency = 8;
1952 let NumMicroOps = 5;
1953 let ResourceCycles = [1,1,2,1];
1954}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]1955def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1956
1957def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1958 let Latency = 8;
1959 let NumMicroOps = 6;
1960 let ResourceCycles = [1,1,1,3];
1961}
Craig Topper9f834812018-04-01 21:54:24 +0000[diff] [blame]1962def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1963
1964def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1965 let Latency = 8;
1966 let NumMicroOps = 6;
1967 let ResourceCycles = [1,1,1,2,1];
1968}
Craig Topper9f834812018-04-01 21:54:24 +0000[diff] [blame]1969def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
1970 "ADC(8|16|32|64)mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1971 "CMPXCHG(8|16|32|64)rm",
1972 "ROL(8|16|32|64)mCL",
1973 "SAR(8|16|32|64)mCL",
1974 "SBB(8|16|32|64)mi",
1975 "SBB(8|16|32|64)mr",
1976 "SHL(8|16|32|64)mCL",
1977 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1978
1979def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1980 let Latency = 9;
1981 let NumMicroOps = 2;
1982 let ResourceCycles = [1,1];
1983}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1984def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
1985 "ADD_F64m",
1986 "ILD_F16m",
1987 "ILD_F32m",
1988 "ILD_F64m",
1989 "SUBR_F32m",
1990 "SUBR_F64m",
1991 "SUB_F32m",
1992 "SUB_F64m",
1993 "VADDPDYrm",
1994 "VADDPSYrm",
1995 "VADDSUBPDYrm",
1996 "VADDSUBPSYrm",
1997 "VCMPPDYrmi",
1998 "VCMPPSYrmi",
1999 "VCVTDQ2PSYrm",
2000 "VCVTPS2DQYrm",
2001 "VCVTTPS2DQYrm",
2002 "VMAX(C?)PDYrm",
2003 "VMAX(C?)PSYrm",
2004 "VMIN(C?)PDYrm",
2005 "VMIN(C?)PSYrm",
2006 "VSUBPDYrm",
2007 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2008
2009def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2010 let Latency = 9;
2011 let NumMicroOps = 2;
2012 let ResourceCycles = [1,1];
2013}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2014def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2015 "VPERM2I128rm",
2016 "VPERMDYrm",
2017 "VPERMPDYmi",
2018 "VPERMPSYrm",
2019 "VPERMQYmi",
2020 "VPMOVZXBDYrm",
2021 "VPMOVZXBQYrm",
2022 "VPMOVZXBWYrm",
2023 "VPMOVZXDQYrm",
2024 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2025
2026def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2027 let Latency = 9;
2028 let NumMicroOps = 2;
2029 let ResourceCycles = [1,1];
2030}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2031def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2032 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2033
2034def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2035 let Latency = 9;
2036 let NumMicroOps = 3;
2037 let ResourceCycles = [1,1,1];
2038}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2039def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2040
2041def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2042 let Latency = 9;
2043 let NumMicroOps = 3;
2044 let ResourceCycles = [1,1,1];
2045}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2046def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2047 "(V?)CVTSD2SIrm",
2048 "(V?)CVTSS2SI64rm",
2049 "(V?)CVTSS2SIrm",
2050 "(V?)CVTTSD2SI64rm",
2051 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2052 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2053 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2054
2055def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2056 let Latency = 9;
2057 let NumMicroOps = 3;
2058 let ResourceCycles = [1,1,1];
2059}
2060def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2061
2062def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2063 let Latency = 9;
2064 let NumMicroOps = 3;
2065 let ResourceCycles = [1,1,1];
2066}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2067def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2068def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2069 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2070 "CVTTPD2DQrm",
2071 "MMX_CVTPD2PIirm",
2072 "MMX_CVTPI2PDirm",
2073 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2074 "(V?)CVTDQ2PDrm",
2075 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2076
2077def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2078 let Latency = 9;
2079 let NumMicroOps = 3;
2080 let ResourceCycles = [1,1,1];
2081}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2082def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2083 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2084
2085def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2086 let Latency = 9;
2087 let NumMicroOps = 4;
2088 let ResourceCycles = [2,1,1];
2089}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2090def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2091 "VPSRAVDYrm",
2092 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2093
2094def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2095 let Latency = 9;
2096 let NumMicroOps = 4;
2097 let ResourceCycles = [2,1,1];
2098}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2099def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2100 "VPHADDSWYrm",
2101 "VPHADDWYrm",
2102 "VPHSUBDYrm",
2103 "VPHSUBSWYrm",
2104 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2105
2106def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2107 let Latency = 9;
2108 let NumMicroOps = 4;
2109 let ResourceCycles = [1,1,1,1];
2110}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2111def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2112 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2113
2114def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2115 let Latency = 9;
2116 let NumMicroOps = 5;
2117 let ResourceCycles = [1,1,3];
2118}
2119def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2120
2121def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2122 let Latency = 9;
2123 let NumMicroOps = 5;
2124 let ResourceCycles = [1,2,1,1];
2125}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2126def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2127 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2128
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2129def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2130 let Latency = 10;
2131 let NumMicroOps = 2;
2132 let ResourceCycles = [1,1];
2133}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2134def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2135 "MMX_PMADDWDirm",
2136 "MMX_PMULHRSWrm",
2137 "MMX_PMULHUWirm",
2138 "MMX_PMULHWirm",
2139 "MMX_PMULLWirm",
2140 "MMX_PMULUDQirm",
2141 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2142 "(V?)PCMPGTQrm",
2143 "(V?)PHMINPOSUWrm",
2144 "(V?)PMADDUBSWrm",
2145 "(V?)PMADDWDrm",
2146 "(V?)PMULDQrm",
2147 "(V?)PMULHRSWrm",
2148 "(V?)PMULHUWrm",
2149 "(V?)PMULHWrm",
2150 "(V?)PMULLWrm",
2151 "(V?)PMULUDQrm",
2152 "(V?)PSADBWrm",
2153 "(V?)RCPPSm",
2154 "(V?)RCPSSm",
2155 "(V?)RSQRTPSm",
2156 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2157
2158def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2159 let Latency = 10;
2160 let NumMicroOps = 2;
2161 let ResourceCycles = [1,1];
2162}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2163def: InstRW<[BWWriteResGroup116],
2164 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2165 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2166
2167def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2168 let Latency = 10;
2169 let NumMicroOps = 3;
2170 let ResourceCycles = [2,1];
2171}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2172def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2173 "FICOM32m",
2174 "FICOMP16m",
2175 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2176
2177def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2178 let Latency = 10;
2179 let NumMicroOps = 3;
2180 let ResourceCycles = [1,1,1];
2181}
2182def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2183
2184def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2185 let Latency = 10;
2186 let NumMicroOps = 4;
2187 let ResourceCycles = [1,2,1];
2188}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2189def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2190 "(V?)HADDPSrm",
2191 "(V?)HSUBPDrm",
2192 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2193
2194def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2195 let Latency = 10;
2196 let NumMicroOps = 4;
2197 let ResourceCycles = [1,1,1,1];
2198}
2199def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2200
2201def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2202 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2203 let NumMicroOps = 4;
2204 let ResourceCycles = [1,1,1,1];
2205}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2206def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2207
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2208def BWWriteResGroup122 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2209 let Latency = 11;
2210 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2211 let ResourceCycles = [1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2212}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2213def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr")>;
2214
2215def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2216 let Latency = 11;
2217 let NumMicroOps = 1;
2218 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
2219}
2220def: InstRW<[BWWriteResGroup122_1], (instregex "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2221
2222def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2223 let Latency = 11;
2224 let NumMicroOps = 2;
2225 let ResourceCycles = [1,1];
2226}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2227def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2228 "MUL_F64m",
2229 "VPCMPGTQYrm",
2230 "VPMADDUBSWYrm",
2231 "VPMADDWDYrm",
2232 "VPMULDQYrm",
2233 "VPMULHRSWYrm",
2234 "VPMULHUWYrm",
2235 "VPMULHWYrm",
2236 "VPMULLWYrm",
2237 "VPMULUDQYrm",
2238 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2239
2240def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2241 let Latency = 11;
2242 let NumMicroOps = 2;
2243 let ResourceCycles = [1,1];
2244}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2245def: InstRW<[BWWriteResGroup124],
2246 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2247
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2248def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2249 let Latency = 11;
2250 let NumMicroOps = 3;
2251 let ResourceCycles = [2,1];
2252}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2253def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2254 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2255
2256def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2257 let Latency = 11;
2258 let NumMicroOps = 3;
2259 let ResourceCycles = [2,1];
2260}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2261def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2262 "(V?)ROUNDPSm",
2263 "(V?)ROUNDSDm",
2264 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2265
2266def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2267 let Latency = 11;
2268 let NumMicroOps = 3;
2269 let ResourceCycles = [1,1,1];
2270}
2271def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2272
2273def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2274 let Latency = 11;
2275 let NumMicroOps = 4;
2276 let ResourceCycles = [1,2,1];
2277}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2278def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2279 "VHADDPSYrm",
2280 "VHSUBPDYrm",
2281 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2282
2283def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2284 let Latency = 11;
2285 let NumMicroOps = 6;
2286 let ResourceCycles = [1,1,1,1,2];
2287}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2288def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2289 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2290
2291def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2292 let Latency = 11;
2293 let NumMicroOps = 7;
2294 let ResourceCycles = [2,2,3];
2295}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2296def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2297 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2298
2299def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2300 let Latency = 11;
2301 let NumMicroOps = 9;
2302 let ResourceCycles = [1,4,1,3];
2303}
2304def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2305
2306def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2307 let Latency = 11;
2308 let NumMicroOps = 11;
2309 let ResourceCycles = [2,9];
2310}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2311def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2312def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2313
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2314def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2315 let Latency = 12;
2316 let NumMicroOps = 3;
2317 let ResourceCycles = [2,1];
2318}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2319def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2320 "ADD_FI32m",
2321 "SUBR_FI16m",
2322 "SUBR_FI32m",
2323 "SUB_FI16m",
2324 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2325 "VROUNDPDYm",
2326 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2327
2328def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2329 let Latency = 12;
2330 let NumMicroOps = 4;
2331 let ResourceCycles = [1,2,1];
2332}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2333def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2334
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2335def BWWriteResGroup137 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2336 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2337 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2338 let ResourceCycles = [1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2339}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2340def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr")>;
2341
2342def BWWriteResGroup137_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2343 let Latency = 11;
2344 let NumMicroOps = 1;
2345 let ResourceCycles = [1,4];
2346}
2347def: InstRW<[BWWriteResGroup137_1], (instregex "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2348
2349def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2350 let Latency = 13;
2351 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2352 let ResourceCycles = [1,2,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2353}
2354def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2355
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2356def BWWriteResGroup139 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2357 let Latency = 14;
2358 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2359 let ResourceCycles = [1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2360}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2361def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr")>;
2362
2363def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2364 let Latency = 14;
2365 let NumMicroOps = 1;
2366 let ResourceCycles = [1,4];
2367}
2368def: InstRW<[BWWriteResGroup139_1], (instregex "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2369
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2370def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2371 let Latency = 14;
2372 let NumMicroOps = 3;
2373 let ResourceCycles = [1,1,1];
2374}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2375def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2376 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2377
2378def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2379 let Latency = 14;
2380 let NumMicroOps = 4;
2381 let ResourceCycles = [2,1,1];
2382}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2383def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2384
2385def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2386 let Latency = 14;
2387 let NumMicroOps = 4;
2388 let ResourceCycles = [1,1,1,1];
2389}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2390def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2391
2392def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2393 let Latency = 14;
2394 let NumMicroOps = 8;
2395 let ResourceCycles = [2,2,1,3];
2396}
2397def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2398
2399def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2400 let Latency = 14;
2401 let NumMicroOps = 10;
2402 let ResourceCycles = [2,3,1,4];
2403}
2404def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2405
2406def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2407 let Latency = 14;
2408 let NumMicroOps = 12;
2409 let ResourceCycles = [2,1,4,5];
2410}
2411def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2412
2413def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2414 let Latency = 15;
2415 let NumMicroOps = 1;
2416 let ResourceCycles = [1];
2417}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2418def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2419 "DIVR_FST0r",
2420 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2421
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2422def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2423 let Latency = 15;
2424 let NumMicroOps = 10;
2425 let ResourceCycles = [1,1,1,4,1,2];
2426}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2427def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2428
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2429def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2430 let Latency = 16;
2431 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2432 let ResourceCycles = [1,1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2433}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2434def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2435 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2436
2437def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2438 let Latency = 16;
2439 let NumMicroOps = 3;
2440 let ResourceCycles = [2,1];
2441}
2442def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2443
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2444def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2445 let Latency = 16;
2446 let NumMicroOps = 14;
2447 let ResourceCycles = [1,1,1,4,2,5];
2448}
2449def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2450
2451def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2452 let Latency = 16;
2453 let NumMicroOps = 16;
2454 let ResourceCycles = [16];
2455}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2456def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2457
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2458def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2459 let Latency = 17;
2460 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2461 let ResourceCycles = [2,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2462}
2463def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2464
2465def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2466 let Latency = 17;
2467 let NumMicroOps = 4;
2468 let ResourceCycles = [2,1,1];
2469}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2470def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2471 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2472
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2473def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2474 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2475 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2476 let ResourceCycles = [1,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2477}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2478def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
2479 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2480
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2481def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2482 let Latency = 18;
2483 let NumMicroOps = 8;
2484 let ResourceCycles = [1,1,1,5];
2485}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2486def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2487def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2488
2489def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2490 let Latency = 18;
2491 let NumMicroOps = 11;
2492 let ResourceCycles = [2,1,1,3,1,3];
2493}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2494def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2495
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2496def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2497 let Latency = 19;
2498 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2499 let ResourceCycles = [1,1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2500}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2501def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2502 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2503
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2504def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2505 let Latency = 19;
2506 let NumMicroOps = 5;
2507 let ResourceCycles = [2,1,1,1];
2508}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2509def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2510
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2511def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2512 let Latency = 20;
2513 let NumMicroOps = 1;
2514 let ResourceCycles = [1];
2515}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2516def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2517 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2518 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2519
2520def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2521 let Latency = 20;
2522 let NumMicroOps = 5;
2523 let ResourceCycles = [2,1,1,1];
2524}
2525def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2526
2527def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2528 let Latency = 20;
2529 let NumMicroOps = 8;
2530 let ResourceCycles = [1,1,1,1,1,1,2];
2531}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2532def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2533 "INSL",
2534 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2535
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2536def BWWriteResGroup168 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2537 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2538 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2539 let ResourceCycles = [1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2540}
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2541def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr")>;
2542
2543def BWWriteResGroup168_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2544 let Latency = 16;
2545 let NumMicroOps = 1;
2546 let ResourceCycles = [1,8];
2547}
2548def: InstRW<[BWWriteResGroup168_1], (instregex "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2549
2550def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2551 let Latency = 21;
2552 let NumMicroOps = 2;
2553 let ResourceCycles = [1,1];
2554}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2555def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2556 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2557
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2558def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2559 let Latency = 21;
2560 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2561 let ResourceCycles = [2,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2562}
2563def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2564
2565def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2566 let Latency = 21;
2567 let NumMicroOps = 19;
2568 let ResourceCycles = [2,1,4,1,1,4,6];
2569}
2570def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2571
2572def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2573 let Latency = 22;
2574 let NumMicroOps = 18;
2575 let ResourceCycles = [1,1,16];
2576}
2577def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2578
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2579def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2580 let Latency = 23;
2581 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2582 let ResourceCycles = [2,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2583}
2584def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2585
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2586def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2587 let Latency = 23;
2588 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2589 let ResourceCycles = [2,1,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2590}
2591def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2592
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2593def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2594 let Latency = 23;
2595 let NumMicroOps = 19;
2596 let ResourceCycles = [3,1,15];
2597}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2598def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2599
2600def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2601 let Latency = 24;
2602 let NumMicroOps = 3;
2603 let ResourceCycles = [1,1,1];
2604}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2605def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2606 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2607
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2608def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2609 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2610 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2611 let ResourceCycles = [1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2612}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2613def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2614 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2615
2616def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2617 let Latency = 26;
2618 let NumMicroOps = 2;
2619 let ResourceCycles = [1,1];
2620}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2621def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2622 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2623
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2624def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2625 let Latency = 27;
2626 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2627 let ResourceCycles = [2,1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2628}
2629def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2630
2631def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2632 let Latency = 29;
2633 let NumMicroOps = 3;
2634 let ResourceCycles = [1,1,1];
2635}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2636def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2637 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2638
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2639def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2640 let Latency = 29;
2641 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2642 let ResourceCycles = [2,1,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2643}
2644def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2645
2646def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2647 let Latency = 22;
2648 let NumMicroOps = 7;
2649 let ResourceCycles = [1,3,2,1];
2650}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2651def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2652
2653def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2654 let Latency = 23;
2655 let NumMicroOps = 9;
2656 let ResourceCycles = [1,3,4,1];
2657}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2658def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2659
2660def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2661 let Latency = 24;
2662 let NumMicroOps = 9;
2663 let ResourceCycles = [1,5,2,1];
2664}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2665def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2666
2667def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2668 let Latency = 25;
2669 let NumMicroOps = 7;
2670 let ResourceCycles = [1,3,2,1];
2671}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2672def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2673 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2674
2675def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2676 let Latency = 26;
2677 let NumMicroOps = 9;
2678 let ResourceCycles = [1,5,2,1];
2679}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2680def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2681
2682def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2683 let Latency = 26;
2684 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2685 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2686}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2687def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2688
2689def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2690 let Latency = 27;
2691 let NumMicroOps = 9;
2692 let ResourceCycles = [1,5,2,1];
2693}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2694def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2695
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2696def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2697 let Latency = 29;
2698 let NumMicroOps = 27;
2699 let ResourceCycles = [1,5,1,1,19];
2700}
2701def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2702
2703def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2704 let Latency = 30;
2705 let NumMicroOps = 28;
2706 let ResourceCycles = [1,6,1,1,19];
2707}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2708def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2709
2710def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2711 let Latency = 31;
2712 let NumMicroOps = 31;
2713 let ResourceCycles = [8,1,21,1];
2714}
2715def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2716
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2717def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
2718 let Latency = 29;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2719 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2720 let ResourceCycles = [2,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2721}
2722def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2723
2724def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2725 let Latency = 34;
2726 let NumMicroOps = 8;
2727 let ResourceCycles = [2,2,2,1,1];
2728}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2729def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2730
2731def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2732 let Latency = 34;
2733 let NumMicroOps = 23;
2734 let ResourceCycles = [1,5,3,4,10];
2735}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2736def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2737 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2738
2739def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2740 let Latency = 35;
2741 let NumMicroOps = 8;
2742 let ResourceCycles = [2,2,2,1,1];
2743}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2744def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2745
2746def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2747 let Latency = 35;
2748 let NumMicroOps = 23;
2749 let ResourceCycles = [1,5,2,1,4,10];
2750}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2751def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2752 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2753
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2754def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
2755 let Latency = 35;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2756 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +0000[diff] [blame]2757 let ResourceCycles = [2,1,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2758}
2759def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2760
2761def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2762 let Latency = 42;
2763 let NumMicroOps = 22;
2764 let ResourceCycles = [2,20];
2765}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2766def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2767
2768def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2769 let Latency = 60;
2770 let NumMicroOps = 64;
2771 let ResourceCycles = [2,2,8,1,10,2,39];
2772}
2773def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2774
2775def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2776 let Latency = 63;
2777 let NumMicroOps = 88;
2778 let ResourceCycles = [4,4,31,1,2,1,45];
2779}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2780def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2781
2782def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2783 let Latency = 63;
2784 let NumMicroOps = 90;
2785 let ResourceCycles = [4,2,33,1,2,1,47];
2786}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2787def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2788
2789def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2790 let Latency = 75;
2791 let NumMicroOps = 15;
2792 let ResourceCycles = [6,3,6];
2793}
2794def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2795
2796def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2797 let Latency = 80;
2798 let NumMicroOps = 32;
2799 let ResourceCycles = [7,7,3,3,1,11];
2800}
2801def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2802
2803def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2804 let Latency = 115;
2805 let NumMicroOps = 100;
2806 let ResourceCycles = [9,9,11,8,1,11,21,30];
2807}
2808def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2809
2810} // SchedModel
2811