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Christian Konig72d5d5c2013-02-21 15:16:44 +00001//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
Tom Stellard75aadc22012-12-11 21:25:42 +000012//===----------------------------------------------------------------------===//
13
Matt Arsenault90c75932017-10-03 00:06:41 +000014def isGCN : Predicate<"Subtarget->getGeneration() "
15 ">= SISubtarget::SOUTHERN_ISLANDS">,
16 AssemblerPredicate<"FeatureGCN">;
17def isSI : Predicate<"Subtarget->getGeneration() "
18 "== SISubtarget::SOUTHERN_ISLANDS">,
19 AssemblerPredicate<"FeatureSouthernIslands">;
20
21
Matt Arsenault9babdf42016-06-22 20:15:28 +000022class InstSI <dag outs, dag ins, string asm = "",
23 list<dag> pattern = []> :
24 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
Matt Arsenault90c75932017-10-03 00:06:41 +000025 let SubtargetPredicate = isGCN;
Tom Stellard75aadc22012-12-11 21:25:42 +000026
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000027 // Low bits - basic encoding information.
Sam Koltonc01faa32016-11-15 13:39:07 +000028 field bit SALU = 0;
29 field bit VALU = 0;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000030
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000031 // SALU instruction formats.
Sam Koltonc01faa32016-11-15 13:39:07 +000032 field bit SOP1 = 0;
33 field bit SOP2 = 0;
34 field bit SOPC = 0;
35 field bit SOPK = 0;
36 field bit SOPP = 0;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000037
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000038 // VALU instruction formats.
Sam Koltonc01faa32016-11-15 13:39:07 +000039 field bit VOP1 = 0;
40 field bit VOP2 = 0;
Sam Koltonc01faa32016-11-15 13:39:07 +000041 field bit VOPC = 0;
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000042 field bit VOP3 = 0;
Matt Arsenault9be7b0d2017-02-27 18:49:11 +000043 field bit VOP3P = 0;
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000044 field bit VINTRP = 0;
Sam Koltonc01faa32016-11-15 13:39:07 +000045 field bit SDWA = 0;
46 field bit DPP = 0;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000047
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000048 // Memory instruction formats.
Sam Koltonc01faa32016-11-15 13:39:07 +000049 field bit MUBUF = 0;
50 field bit MTBUF = 0;
51 field bit SMRD = 0;
Sam Koltonc01faa32016-11-15 13:39:07 +000052 field bit MIMG = 0;
Matt Arsenault7bee6ac2016-12-05 20:23:10 +000053 field bit EXP = 0;
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000054 field bit FLAT = 0;
55 field bit DS = 0;
Nicolai Haehnle8a482b32016-08-02 19:31:14 +000056
Konstantin Zhuravlyov070d88e2017-07-21 21:05:45 +000057 // Pseudo instruction formats.
Sam Koltonc01faa32016-11-15 13:39:07 +000058 field bit VGPRSpill = 0;
59 field bit SGPRSpill = 0;
Tom Stellard75aadc22012-12-11 21:25:42 +000060
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000061 // High bits - other information.
62 field bit VM_CNT = 0;
63 field bit EXP_CNT = 0;
64 field bit LGKM_CNT = 0;
Tom Stellard88e0b252015-10-06 15:57:53 +000065
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000066 // Whether WQM _must_ be enabled for this instruction.
67 field bit WQM = 0;
Nicolai Haehnlec06bfa12016-07-11 21:59:43 +000068
Nicolai Haehnle8a482b32016-08-02 19:31:14 +000069 // Whether WQM _must_ be disabled for this instruction.
Sam Koltonc01faa32016-11-15 13:39:07 +000070 field bit DisableWQM = 0;
Nicolai Haehnle8a482b32016-08-02 19:31:14 +000071
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000072 field bit Gather4 = 0;
73
Matt Arsenault7ccf6cd2016-09-16 21:41:16 +000074 // Most sopk treat the immediate as a signed 16-bit, however some
75 // use it as unsigned.
Sam Koltonc01faa32016-11-15 13:39:07 +000076 field bit SOPKZext = 0;
Matt Arsenault7ccf6cd2016-09-16 21:41:16 +000077
Matt Arsenault7b647552016-10-28 21:55:15 +000078 // This is an s_store_dword* instruction that requires a cache flush
79 // on wave termination. It is necessary to distinguish from mayStore
80 // SMEM instructions like the cache flush ones.
Sam Koltonc01faa32016-11-15 13:39:07 +000081 field bit ScalarStore = 0;
Matt Arsenault7b647552016-10-28 21:55:15 +000082
Matt Arsenault2d8c2892016-11-01 20:42:24 +000083 // Whether the operands can be ignored when computing the
84 // instruction size.
Sam Koltonc01faa32016-11-15 13:39:07 +000085 field bit FixedSize = 0;
Matt Arsenault2d8c2892016-11-01 20:42:24 +000086
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000087 // This bit tells the assembler to use the 32-bit encoding in case it
88 // is unable to infer the encoding from the operands.
89 field bit VOPAsmPrefer32Bit = 0;
90
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +000091 // This bit indicates that this is a VOP3 opcode which supports op_sel
92 // modifier (gfx9 only).
93 field bit VOP3_OPSEL = 0;
94
Konstantin Zhuravlyov070d88e2017-07-21 21:05:45 +000095 // Is it possible for this instruction to be atomic?
96 field bit maybeAtomic = 0;
97
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +000098 // This bit indicates that this is a VI instruction which is renamed
99 // in GFX9. Required for correct mapping from pseudo to MC.
100 field bit renamedInGFX9 = 0;
Dmitry Preobrazhensky1e325502017-08-09 17:10:47 +0000101
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000102 // This bit indicates that this has a floating point result type, so
103 // the clamp modifier has floating point semantics.
104 field bit FPClamp = 0;
105
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000106 // This bit indicates that instruction may support integer clamping
107 // which depends on GPU features.
108 field bit IntClamp = 0;
109
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000110 // This field indicates that the clamp applies to the low component
111 // of a packed output register.
112 field bit ClampLo = 0;
113
114 // This field indicates that the clamp applies to the high component
115 // of a packed output register.
116 field bit ClampHi = 0;
117
Dmitry Preobrazhensky682a6542017-11-17 15:15:40 +0000118 // This bit indicates that this is a packed VOP3P instruction
119 field bit IsPacked = 0;
120
Changpeng Fang4737e892018-01-18 22:08:53 +0000121 // This bit indicates that this is a D16 instruction.
122 field bit D16 = 0;
123
Matt Arsenaulte2fabd32014-07-29 18:51:56 +0000124 // These need to be kept in sync with the enum in SIInstrFlags.
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000125 let TSFlags{0} = SALU;
126 let TSFlags{1} = VALU;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +0000127
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000128 let TSFlags{2} = SOP1;
129 let TSFlags{3} = SOP2;
130 let TSFlags{4} = SOPC;
131 let TSFlags{5} = SOPK;
132 let TSFlags{6} = SOPP;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +0000133
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000134 let TSFlags{7} = VOP1;
135 let TSFlags{8} = VOP2;
136 let TSFlags{9} = VOPC;
137 let TSFlags{10} = VOP3;
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000138 let TSFlags{12} = VOP3P;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +0000139
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000140 let TSFlags{13} = VINTRP;
Sam Kolton3025e7f2016-04-26 13:33:56 +0000141 let TSFlags{14} = SDWA;
142 let TSFlags{15} = DPP;
Matt Arsenaultc5f174d2014-12-01 15:52:46 +0000143
Sam Kolton3025e7f2016-04-26 13:33:56 +0000144 let TSFlags{16} = MUBUF;
145 let TSFlags{17} = MTBUF;
146 let TSFlags{18} = SMRD;
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000147 let TSFlags{19} = MIMG;
148 let TSFlags{20} = EXP;
Sam Kolton3025e7f2016-04-26 13:33:56 +0000149 let TSFlags{21} = FLAT;
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000150 let TSFlags{22} = DS;
151
152 let TSFlags{23} = VGPRSpill;
153 let TSFlags{24} = SGPRSpill;
154
155 let TSFlags{32} = VM_CNT;
156 let TSFlags{33} = EXP_CNT;
157 let TSFlags{34} = LGKM_CNT;
158
159 let TSFlags{35} = WQM;
160 let TSFlags{36} = DisableWQM;
161 let TSFlags{37} = Gather4;
162
163 let TSFlags{38} = SOPKZext;
164 let TSFlags{39} = ScalarStore;
165 let TSFlags{40} = FixedSize;
166 let TSFlags{41} = VOPAsmPrefer32Bit;
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000167 let TSFlags{42} = VOP3_OPSEL;
Matt Arsenaultcb0ac3d2014-09-26 17:54:59 +0000168
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000169 let TSFlags{43} = maybeAtomic;
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +0000170 let TSFlags{44} = renamedInGFX9;
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000171
172 let TSFlags{45} = FPClamp;
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000173 let TSFlags{46} = IntClamp;
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +0000174 let TSFlags{47} = ClampLo;
175 let TSFlags{48} = ClampHi;
Konstantin Zhuravlyov070d88e2017-07-21 21:05:45 +0000176
Dmitry Preobrazhensky682a6542017-11-17 15:15:40 +0000177 let TSFlags{49} = IsPacked;
178
Changpeng Fang4737e892018-01-18 22:08:53 +0000179 let TSFlags{50} = D16;
180
Tom Stellardae38f302015-01-14 01:13:19 +0000181 let SchedRW = [Write32Bit];
Tom Stellarde1818af2016-02-18 03:42:32 +0000182
183 field bits<1> DisableSIDecoder = 0;
184 field bits<1> DisableVIDecoder = 0;
185 field bits<1> DisableDecoder = 0;
186
187 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
Sam Koltond63d8a72016-09-09 09:37:51 +0000188 let AsmVariantName = AMDGPUAsmVariants.Default;
Geoff Berryf8bf2ec2018-02-23 18:25:08 +0000189
190 // Avoid changing source registers in a way that violates constant bus read limitations.
191 let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0))))));
Tom Stellard75aadc22012-12-11 21:25:42 +0000192}
193
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +0000194class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
195 : InstSI<outs, ins, asm, pattern> {
Matt Arsenaultfc7e6a02016-07-12 00:23:17 +0000196 let isPseudo = 1;
197 let isCodeGenOnly = 1;
198}
199
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +0000200class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
201 : PseudoInstSI<outs, ins, pattern, asm> {
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000202 let SALU = 1;
203}
204
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +0000205class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
206 : PseudoInstSI<outs, ins, pattern, asm> {
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000207 let VALU = 1;
208 let Uses = [EXEC];
209}
210
211class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],
212 bit UseExec = 0, bit DefExec = 0> :
213 SPseudoInstSI<outs, ins, pattern> {
214
215 let Uses = !if(UseExec, [EXEC], []);
216 let Defs = !if(DefExec, [EXEC, SCC], [SCC]);
Matt Arsenault6408c912016-09-16 22:11:18 +0000217 let mayLoad = 0;
218 let mayStore = 0;
219 let hasSideEffects = 0;
Matt Arsenault71ed8a62016-08-27 03:00:51 +0000220}
221
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000222class Enc32 {
Christian Konig72d5d5c2013-02-21 15:16:44 +0000223 field bits<32> Inst;
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000224 int Size = 4;
Tom Stellard75aadc22012-12-11 21:25:42 +0000225}
226
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000227class Enc64 {
Christian Konig72d5d5c2013-02-21 15:16:44 +0000228 field bits<64> Inst;
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000229 int Size = 8;
Tom Stellard75aadc22012-12-11 21:25:42 +0000230}
231
Tom Stellardc0503922015-03-12 21:34:22 +0000232class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
Tom Stellardc0503922015-03-12 21:34:22 +0000233
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000234class VINTRPe <bits<2> op> : Enc32 {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000235 bits<8> vdst;
236 bits<8> vsrc;
237 bits<2> attrchan;
238 bits<6> attr;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000239
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000240 let Inst{7-0} = vsrc;
241 let Inst{9-8} = attrchan;
242 let Inst{15-10} = attr;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000243 let Inst{17-16} = op;
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000244 let Inst{25-18} = vdst;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000245 let Inst{31-26} = 0x32; // encoding
Christian Konige3cba882013-02-16 11:28:02 +0000246}
247
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000248class MIMGe <bits<7> op> : Enc64 {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000249 bits<8> vdata;
250 bits<4> dmask;
251 bits<1> unorm;
252 bits<1> glc;
253 bits<1> da;
254 bits<1> r128;
255 bits<1> tfe;
256 bits<1> lwe;
257 bits<1> slc;
Changpeng Fang4737e892018-01-18 22:08:53 +0000258 bits<1> d16 = 0;
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000259 bits<8> vaddr;
260 bits<7> srsrc;
261 bits<7> ssamp;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000262
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000263 let Inst{11-8} = dmask;
264 let Inst{12} = unorm;
265 let Inst{13} = glc;
266 let Inst{14} = da;
267 let Inst{15} = r128;
268 let Inst{16} = tfe;
269 let Inst{17} = lwe;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000270 let Inst{24-18} = op;
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000271 let Inst{25} = slc;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000272 let Inst{31-26} = 0x3c;
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000273 let Inst{39-32} = vaddr;
274 let Inst{47-40} = vdata;
275 let Inst{52-48} = srsrc{6-2};
276 let Inst{57-53} = ssamp{6-2};
Changpeng Fang4737e892018-01-18 22:08:53 +0000277 let Inst{63} = d16;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000278}
279
Matt Arsenault3f981402014-09-15 15:41:53 +0000280class EXPe : Enc64 {
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000281 bits<4> en;
282 bits<6> tgt;
283 bits<1> compr;
284 bits<1> done;
285 bits<1> vm;
Dmitry Preobrazhensky9321e8f2017-05-19 13:36:09 +0000286 bits<8> src0;
287 bits<8> src1;
288 bits<8> src2;
289 bits<8> src3;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000290
Matt Arsenaulte3dbcf62015-02-18 02:15:35 +0000291 let Inst{3-0} = en;
292 let Inst{9-4} = tgt;
293 let Inst{10} = compr;
294 let Inst{11} = done;
295 let Inst{12} = vm;
Christian Konig72d5d5c2013-02-21 15:16:44 +0000296 let Inst{31-26} = 0x3e;
Dmitry Preobrazhensky9321e8f2017-05-19 13:36:09 +0000297 let Inst{39-32} = src0;
298 let Inst{47-40} = src1;
299 let Inst{55-48} = src2;
300 let Inst{63-56} = src3;
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000301}
302
303let Uses = [EXEC] in {
304
Marek Olsak5df00d62014-12-07 12:18:57 +0000305class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
306 InstSI <outs, ins, asm, pattern> {
Matt Arsenaultf0c86252016-12-10 00:29:55 +0000307 let VINTRP = 1;
Tom Stellard2a484332016-12-09 15:57:15 +0000308 // VINTRP instructions read parameter values from LDS, but these parameter
309 // values are stored outside of the LDS memory that is allocated to the
310 // shader for general purpose use.
311 //
312 // While it may be possible for ds_read/ds_write instructions to access
313 // the parameter values in LDS, this would essentially be an out-of-bounds
314 // memory access which we consider to be undefined behavior.
315 //
316 // So even though these instructions read memory, this memory is outside the
317 // addressable memory space for the shader, and we consider these instructions
318 // to be readnone.
319 let mayLoad = 0;
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000320 let mayStore = 0;
Matt Arsenault9a072c12014-11-18 23:57:33 +0000321 let hasSideEffects = 0;
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000322}
323
Matt Arsenault7bee6ac2016-12-05 20:23:10 +0000324class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
325 InstSI<outs, ins, asm, pattern> {
326 let EXP = 1;
327 let EXP_CNT = 1;
328 let mayLoad = 0; // Set to 1 if done bit is set.
329 let mayStore = 1;
330 let UseNamedOperandTable = 1;
331 let Uses = [EXEC];
332 let SchedRW = [WriteExport];
333}
334
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000335} // End Uses = [EXEC]
336
Nikolay Haustov5bf46ac12016-03-04 10:39:50 +0000337class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
338 InstSI <outs, ins, asm, pattern> {
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000339
340 let VM_CNT = 1;
341 let EXP_CNT = 1;
342 let MIMG = 1;
Matt Arsenault80f766a2015-09-10 01:23:28 +0000343 let Uses = [EXEC];
Matt Arsenault9a072c12014-11-18 23:57:33 +0000344
Tom Stellard1397d492016-02-11 21:45:07 +0000345 let UseNamedOperandTable = 1;
Matt Arsenault9a072c12014-11-18 23:57:33 +0000346 let hasSideEffects = 0; // XXX ????
Tom Stellarde5a1cda2014-07-21 17:44:28 +0000347}