Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 1 | //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // SI Instruction format definitions. |
| 11 | // |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 14 | def isGCN : Predicate<"Subtarget->getGeneration() " |
| 15 | ">= SISubtarget::SOUTHERN_ISLANDS">, |
| 16 | AssemblerPredicate<"FeatureGCN">; |
| 17 | def isSI : Predicate<"Subtarget->getGeneration() " |
| 18 | "== SISubtarget::SOUTHERN_ISLANDS">, |
| 19 | AssemblerPredicate<"FeatureSouthernIslands">; |
| 20 | |
| 21 | |
Matt Arsenault | 9babdf4 | 2016-06-22 20:15:28 +0000 | [diff] [blame] | 22 | class InstSI <dag outs, dag ins, string asm = "", |
| 23 | list<dag> pattern = []> : |
| 24 | AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 25 | let SubtargetPredicate = isGCN; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 26 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 27 | // Low bits - basic encoding information. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 28 | field bit SALU = 0; |
| 29 | field bit VALU = 0; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 30 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 31 | // SALU instruction formats. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 32 | field bit SOP1 = 0; |
| 33 | field bit SOP2 = 0; |
| 34 | field bit SOPC = 0; |
| 35 | field bit SOPK = 0; |
| 36 | field bit SOPP = 0; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 37 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 38 | // VALU instruction formats. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 39 | field bit VOP1 = 0; |
| 40 | field bit VOP2 = 0; |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 41 | field bit VOPC = 0; |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 42 | field bit VOP3 = 0; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 43 | field bit VOP3P = 0; |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 44 | field bit VINTRP = 0; |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 45 | field bit SDWA = 0; |
| 46 | field bit DPP = 0; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 47 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 48 | // Memory instruction formats. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 49 | field bit MUBUF = 0; |
| 50 | field bit MTBUF = 0; |
| 51 | field bit SMRD = 0; |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 52 | field bit MIMG = 0; |
Matt Arsenault | 7bee6ac | 2016-12-05 20:23:10 +0000 | [diff] [blame] | 53 | field bit EXP = 0; |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 54 | field bit FLAT = 0; |
| 55 | field bit DS = 0; |
Nicolai Haehnle | 8a482b3 | 2016-08-02 19:31:14 +0000 | [diff] [blame] | 56 | |
Konstantin Zhuravlyov | 070d88e | 2017-07-21 21:05:45 +0000 | [diff] [blame] | 57 | // Pseudo instruction formats. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 58 | field bit VGPRSpill = 0; |
| 59 | field bit SGPRSpill = 0; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 60 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 61 | // High bits - other information. |
| 62 | field bit VM_CNT = 0; |
| 63 | field bit EXP_CNT = 0; |
| 64 | field bit LGKM_CNT = 0; |
Tom Stellard | 88e0b25 | 2015-10-06 15:57:53 +0000 | [diff] [blame] | 65 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 66 | // Whether WQM _must_ be enabled for this instruction. |
| 67 | field bit WQM = 0; |
Nicolai Haehnle | c06bfa1 | 2016-07-11 21:59:43 +0000 | [diff] [blame] | 68 | |
Nicolai Haehnle | 8a482b3 | 2016-08-02 19:31:14 +0000 | [diff] [blame] | 69 | // Whether WQM _must_ be disabled for this instruction. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 70 | field bit DisableWQM = 0; |
Nicolai Haehnle | 8a482b3 | 2016-08-02 19:31:14 +0000 | [diff] [blame] | 71 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 72 | field bit Gather4 = 0; |
| 73 | |
Matt Arsenault | 7ccf6cd | 2016-09-16 21:41:16 +0000 | [diff] [blame] | 74 | // Most sopk treat the immediate as a signed 16-bit, however some |
| 75 | // use it as unsigned. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 76 | field bit SOPKZext = 0; |
Matt Arsenault | 7ccf6cd | 2016-09-16 21:41:16 +0000 | [diff] [blame] | 77 | |
Matt Arsenault | 7b64755 | 2016-10-28 21:55:15 +0000 | [diff] [blame] | 78 | // This is an s_store_dword* instruction that requires a cache flush |
| 79 | // on wave termination. It is necessary to distinguish from mayStore |
| 80 | // SMEM instructions like the cache flush ones. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 81 | field bit ScalarStore = 0; |
Matt Arsenault | 7b64755 | 2016-10-28 21:55:15 +0000 | [diff] [blame] | 82 | |
Matt Arsenault | 2d8c289 | 2016-11-01 20:42:24 +0000 | [diff] [blame] | 83 | // Whether the operands can be ignored when computing the |
| 84 | // instruction size. |
Sam Kolton | c01faa3 | 2016-11-15 13:39:07 +0000 | [diff] [blame] | 85 | field bit FixedSize = 0; |
Matt Arsenault | 2d8c289 | 2016-11-01 20:42:24 +0000 | [diff] [blame] | 86 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 87 | // This bit tells the assembler to use the 32-bit encoding in case it |
| 88 | // is unable to infer the encoding from the operands. |
| 89 | field bit VOPAsmPrefer32Bit = 0; |
| 90 | |
Dmitry Preobrazhensky | abf2839 | 2017-07-21 13:54:11 +0000 | [diff] [blame] | 91 | // This bit indicates that this is a VOP3 opcode which supports op_sel |
| 92 | // modifier (gfx9 only). |
| 93 | field bit VOP3_OPSEL = 0; |
| 94 | |
Konstantin Zhuravlyov | 070d88e | 2017-07-21 21:05:45 +0000 | [diff] [blame] | 95 | // Is it possible for this instruction to be atomic? |
| 96 | field bit maybeAtomic = 0; |
| 97 | |
Dmitry Preobrazhensky | a0342dc | 2017-11-20 18:24:21 +0000 | [diff] [blame] | 98 | // This bit indicates that this is a VI instruction which is renamed |
| 99 | // in GFX9. Required for correct mapping from pseudo to MC. |
| 100 | field bit renamedInGFX9 = 0; |
Dmitry Preobrazhensky | 1e32550 | 2017-08-09 17:10:47 +0000 | [diff] [blame] | 101 | |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 102 | // This bit indicates that this has a floating point result type, so |
| 103 | // the clamp modifier has floating point semantics. |
| 104 | field bit FPClamp = 0; |
| 105 | |
Dmitry Preobrazhensky | ff64aa5 | 2017-08-16 13:51:56 +0000 | [diff] [blame] | 106 | // This bit indicates that instruction may support integer clamping |
| 107 | // which depends on GPU features. |
| 108 | field bit IntClamp = 0; |
| 109 | |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 110 | // This field indicates that the clamp applies to the low component |
| 111 | // of a packed output register. |
| 112 | field bit ClampLo = 0; |
| 113 | |
| 114 | // This field indicates that the clamp applies to the high component |
| 115 | // of a packed output register. |
| 116 | field bit ClampHi = 0; |
| 117 | |
Dmitry Preobrazhensky | 682a654 | 2017-11-17 15:15:40 +0000 | [diff] [blame] | 118 | // This bit indicates that this is a packed VOP3P instruction |
| 119 | field bit IsPacked = 0; |
| 120 | |
Changpeng Fang | 4737e89 | 2018-01-18 22:08:53 +0000 | [diff] [blame] | 121 | // This bit indicates that this is a D16 instruction. |
| 122 | field bit D16 = 0; |
| 123 | |
Matt Arsenault | e2fabd3 | 2014-07-29 18:51:56 +0000 | [diff] [blame] | 124 | // These need to be kept in sync with the enum in SIInstrFlags. |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 125 | let TSFlags{0} = SALU; |
| 126 | let TSFlags{1} = VALU; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 127 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 128 | let TSFlags{2} = SOP1; |
| 129 | let TSFlags{3} = SOP2; |
| 130 | let TSFlags{4} = SOPC; |
| 131 | let TSFlags{5} = SOPK; |
| 132 | let TSFlags{6} = SOPP; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 133 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 134 | let TSFlags{7} = VOP1; |
| 135 | let TSFlags{8} = VOP2; |
| 136 | let TSFlags{9} = VOPC; |
| 137 | let TSFlags{10} = VOP3; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 138 | let TSFlags{12} = VOP3P; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 139 | |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 140 | let TSFlags{13} = VINTRP; |
Sam Kolton | 3025e7f | 2016-04-26 13:33:56 +0000 | [diff] [blame] | 141 | let TSFlags{14} = SDWA; |
| 142 | let TSFlags{15} = DPP; |
Matt Arsenault | c5f174d | 2014-12-01 15:52:46 +0000 | [diff] [blame] | 143 | |
Sam Kolton | 3025e7f | 2016-04-26 13:33:56 +0000 | [diff] [blame] | 144 | let TSFlags{16} = MUBUF; |
| 145 | let TSFlags{17} = MTBUF; |
| 146 | let TSFlags{18} = SMRD; |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 147 | let TSFlags{19} = MIMG; |
| 148 | let TSFlags{20} = EXP; |
Sam Kolton | 3025e7f | 2016-04-26 13:33:56 +0000 | [diff] [blame] | 149 | let TSFlags{21} = FLAT; |
Matt Arsenault | eb4a55e | 2016-12-09 17:49:08 +0000 | [diff] [blame] | 150 | let TSFlags{22} = DS; |
| 151 | |
| 152 | let TSFlags{23} = VGPRSpill; |
| 153 | let TSFlags{24} = SGPRSpill; |
| 154 | |
| 155 | let TSFlags{32} = VM_CNT; |
| 156 | let TSFlags{33} = EXP_CNT; |
| 157 | let TSFlags{34} = LGKM_CNT; |
| 158 | |
| 159 | let TSFlags{35} = WQM; |
| 160 | let TSFlags{36} = DisableWQM; |
| 161 | let TSFlags{37} = Gather4; |
| 162 | |
| 163 | let TSFlags{38} = SOPKZext; |
| 164 | let TSFlags{39} = ScalarStore; |
| 165 | let TSFlags{40} = FixedSize; |
| 166 | let TSFlags{41} = VOPAsmPrefer32Bit; |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 167 | let TSFlags{42} = VOP3_OPSEL; |
Matt Arsenault | cb0ac3d | 2014-09-26 17:54:59 +0000 | [diff] [blame] | 168 | |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 169 | let TSFlags{43} = maybeAtomic; |
Dmitry Preobrazhensky | a0342dc | 2017-11-20 18:24:21 +0000 | [diff] [blame] | 170 | let TSFlags{44} = renamedInGFX9; |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 171 | |
| 172 | let TSFlags{45} = FPClamp; |
Dmitry Preobrazhensky | ff64aa5 | 2017-08-16 13:51:56 +0000 | [diff] [blame] | 173 | let TSFlags{46} = IntClamp; |
Matt Arsenault | ab4a5cd | 2017-08-31 23:53:50 +0000 | [diff] [blame] | 174 | let TSFlags{47} = ClampLo; |
| 175 | let TSFlags{48} = ClampHi; |
Konstantin Zhuravlyov | 070d88e | 2017-07-21 21:05:45 +0000 | [diff] [blame] | 176 | |
Dmitry Preobrazhensky | 682a654 | 2017-11-17 15:15:40 +0000 | [diff] [blame] | 177 | let TSFlags{49} = IsPacked; |
| 178 | |
Changpeng Fang | 4737e89 | 2018-01-18 22:08:53 +0000 | [diff] [blame] | 179 | let TSFlags{50} = D16; |
| 180 | |
Tom Stellard | ae38f30 | 2015-01-14 01:13:19 +0000 | [diff] [blame] | 181 | let SchedRW = [Write32Bit]; |
Tom Stellard | e1818af | 2016-02-18 03:42:32 +0000 | [diff] [blame] | 182 | |
| 183 | field bits<1> DisableSIDecoder = 0; |
| 184 | field bits<1> DisableVIDecoder = 0; |
| 185 | field bits<1> DisableDecoder = 0; |
| 186 | |
| 187 | let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); |
Sam Kolton | d63d8a7 | 2016-09-09 09:37:51 +0000 | [diff] [blame] | 188 | let AsmVariantName = AMDGPUAsmVariants.Default; |
Geoff Berry | f8bf2ec | 2018-02-23 18:25:08 +0000 | [diff] [blame] | 189 | |
| 190 | // Avoid changing source registers in a way that violates constant bus read limitations. |
| 191 | let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)))))); |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 192 | } |
| 193 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 194 | class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> |
| 195 | : InstSI<outs, ins, asm, pattern> { |
Matt Arsenault | fc7e6a0 | 2016-07-12 00:23:17 +0000 | [diff] [blame] | 196 | let isPseudo = 1; |
| 197 | let isCodeGenOnly = 1; |
| 198 | } |
| 199 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 200 | class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> |
| 201 | : PseudoInstSI<outs, ins, pattern, asm> { |
Matt Arsenault | 71ed8a6 | 2016-08-27 03:00:51 +0000 | [diff] [blame] | 202 | let SALU = 1; |
| 203 | } |
| 204 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 205 | class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = ""> |
| 206 | : PseudoInstSI<outs, ins, pattern, asm> { |
Matt Arsenault | 71ed8a6 | 2016-08-27 03:00:51 +0000 | [diff] [blame] | 207 | let VALU = 1; |
| 208 | let Uses = [EXEC]; |
| 209 | } |
| 210 | |
| 211 | class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], |
| 212 | bit UseExec = 0, bit DefExec = 0> : |
| 213 | SPseudoInstSI<outs, ins, pattern> { |
| 214 | |
| 215 | let Uses = !if(UseExec, [EXEC], []); |
| 216 | let Defs = !if(DefExec, [EXEC, SCC], [SCC]); |
Matt Arsenault | 6408c91 | 2016-09-16 22:11:18 +0000 | [diff] [blame] | 217 | let mayLoad = 0; |
| 218 | let mayStore = 0; |
| 219 | let hasSideEffects = 0; |
Matt Arsenault | 71ed8a6 | 2016-08-27 03:00:51 +0000 | [diff] [blame] | 220 | } |
| 221 | |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 222 | class Enc32 { |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 223 | field bits<32> Inst; |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 224 | int Size = 4; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 225 | } |
| 226 | |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 227 | class Enc64 { |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 228 | field bits<64> Inst; |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 229 | int Size = 8; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 230 | } |
| 231 | |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 232 | class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; |
Tom Stellard | c050392 | 2015-03-12 21:34:22 +0000 | [diff] [blame] | 233 | |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 234 | class VINTRPe <bits<2> op> : Enc32 { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 235 | bits<8> vdst; |
| 236 | bits<8> vsrc; |
| 237 | bits<2> attrchan; |
| 238 | bits<6> attr; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 239 | |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 240 | let Inst{7-0} = vsrc; |
| 241 | let Inst{9-8} = attrchan; |
| 242 | let Inst{15-10} = attr; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 243 | let Inst{17-16} = op; |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 244 | let Inst{25-18} = vdst; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 245 | let Inst{31-26} = 0x32; // encoding |
Christian Konig | e3cba88 | 2013-02-16 11:28:02 +0000 | [diff] [blame] | 246 | } |
| 247 | |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 248 | class MIMGe <bits<7> op> : Enc64 { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 249 | bits<8> vdata; |
| 250 | bits<4> dmask; |
| 251 | bits<1> unorm; |
| 252 | bits<1> glc; |
| 253 | bits<1> da; |
| 254 | bits<1> r128; |
| 255 | bits<1> tfe; |
| 256 | bits<1> lwe; |
| 257 | bits<1> slc; |
Changpeng Fang | 4737e89 | 2018-01-18 22:08:53 +0000 | [diff] [blame] | 258 | bits<1> d16 = 0; |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 259 | bits<8> vaddr; |
| 260 | bits<7> srsrc; |
| 261 | bits<7> ssamp; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 262 | |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 263 | let Inst{11-8} = dmask; |
| 264 | let Inst{12} = unorm; |
| 265 | let Inst{13} = glc; |
| 266 | let Inst{14} = da; |
| 267 | let Inst{15} = r128; |
| 268 | let Inst{16} = tfe; |
| 269 | let Inst{17} = lwe; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 270 | let Inst{24-18} = op; |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 271 | let Inst{25} = slc; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 272 | let Inst{31-26} = 0x3c; |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 273 | let Inst{39-32} = vaddr; |
| 274 | let Inst{47-40} = vdata; |
| 275 | let Inst{52-48} = srsrc{6-2}; |
| 276 | let Inst{57-53} = ssamp{6-2}; |
Changpeng Fang | 4737e89 | 2018-01-18 22:08:53 +0000 | [diff] [blame] | 277 | let Inst{63} = d16; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 278 | } |
| 279 | |
Matt Arsenault | 3f98140 | 2014-09-15 15:41:53 +0000 | [diff] [blame] | 280 | class EXPe : Enc64 { |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 281 | bits<4> en; |
| 282 | bits<6> tgt; |
| 283 | bits<1> compr; |
| 284 | bits<1> done; |
| 285 | bits<1> vm; |
Dmitry Preobrazhensky | 9321e8f | 2017-05-19 13:36:09 +0000 | [diff] [blame] | 286 | bits<8> src0; |
| 287 | bits<8> src1; |
| 288 | bits<8> src2; |
| 289 | bits<8> src3; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 290 | |
Matt Arsenault | e3dbcf6 | 2015-02-18 02:15:35 +0000 | [diff] [blame] | 291 | let Inst{3-0} = en; |
| 292 | let Inst{9-4} = tgt; |
| 293 | let Inst{10} = compr; |
| 294 | let Inst{11} = done; |
| 295 | let Inst{12} = vm; |
Christian Konig | 72d5d5c | 2013-02-21 15:16:44 +0000 | [diff] [blame] | 296 | let Inst{31-26} = 0x3e; |
Dmitry Preobrazhensky | 9321e8f | 2017-05-19 13:36:09 +0000 | [diff] [blame] | 297 | let Inst{39-32} = src0; |
| 298 | let Inst{47-40} = src1; |
| 299 | let Inst{55-48} = src2; |
| 300 | let Inst{63-56} = src3; |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | let Uses = [EXEC] in { |
| 304 | |
Marek Olsak | 5df00d6 | 2014-12-07 12:18:57 +0000 | [diff] [blame] | 305 | class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : |
| 306 | InstSI <outs, ins, asm, pattern> { |
Matt Arsenault | f0c8625 | 2016-12-10 00:29:55 +0000 | [diff] [blame] | 307 | let VINTRP = 1; |
Tom Stellard | 2a48433 | 2016-12-09 15:57:15 +0000 | [diff] [blame] | 308 | // VINTRP instructions read parameter values from LDS, but these parameter |
| 309 | // values are stored outside of the LDS memory that is allocated to the |
| 310 | // shader for general purpose use. |
| 311 | // |
| 312 | // While it may be possible for ds_read/ds_write instructions to access |
| 313 | // the parameter values in LDS, this would essentially be an out-of-bounds |
| 314 | // memory access which we consider to be undefined behavior. |
| 315 | // |
| 316 | // So even though these instructions read memory, this memory is outside the |
| 317 | // addressable memory space for the shader, and we consider these instructions |
| 318 | // to be readnone. |
| 319 | let mayLoad = 0; |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 320 | let mayStore = 0; |
Matt Arsenault | 9a072c1 | 2014-11-18 23:57:33 +0000 | [diff] [blame] | 321 | let hasSideEffects = 0; |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 322 | } |
| 323 | |
Matt Arsenault | 7bee6ac | 2016-12-05 20:23:10 +0000 | [diff] [blame] | 324 | class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> : |
| 325 | InstSI<outs, ins, asm, pattern> { |
| 326 | let EXP = 1; |
| 327 | let EXP_CNT = 1; |
| 328 | let mayLoad = 0; // Set to 1 if done bit is set. |
| 329 | let mayStore = 1; |
| 330 | let UseNamedOperandTable = 1; |
| 331 | let Uses = [EXEC]; |
| 332 | let SchedRW = [WriteExport]; |
| 333 | } |
| 334 | |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 335 | } // End Uses = [EXEC] |
| 336 | |
Nikolay Haustov | 5bf46ac1 | 2016-03-04 10:39:50 +0000 | [diff] [blame] | 337 | class MIMG <dag outs, dag ins, string asm, list<dag> pattern> : |
| 338 | InstSI <outs, ins, asm, pattern> { |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 339 | |
| 340 | let VM_CNT = 1; |
| 341 | let EXP_CNT = 1; |
| 342 | let MIMG = 1; |
Matt Arsenault | 80f766a | 2015-09-10 01:23:28 +0000 | [diff] [blame] | 343 | let Uses = [EXEC]; |
Matt Arsenault | 9a072c1 | 2014-11-18 23:57:33 +0000 | [diff] [blame] | 344 | |
Tom Stellard | 1397d49 | 2016-02-11 21:45:07 +0000 | [diff] [blame] | 345 | let UseNamedOperandTable = 1; |
Matt Arsenault | 9a072c1 | 2014-11-18 23:57:33 +0000 | [diff] [blame] | 346 | let hasSideEffects = 0; // XXX ???? |
Tom Stellard | e5a1cda | 2014-07-21 17:44:28 +0000 | [diff] [blame] | 347 | } |