Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 43 | #define MDP_MIN_FETCH 9 |
| 44 | #define MDSS_MDP_MAX_FETCH 12 |
| 45 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 46 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 47 | |
| 48 | static int mdp_rev; |
| 49 | |
| 50 | void mdp_set_revision(int rev) |
| 51 | { |
| 52 | mdp_rev = rev; |
| 53 | } |
| 54 | |
| 55 | int mdp_get_revision() |
| 56 | { |
| 57 | return mdp_rev; |
| 58 | } |
| 59 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 60 | uint32_t mdss_mdp_intf_offset() |
| 61 | { |
| 62 | uint32_t mdss_mdp_intf_off; |
| 63 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 64 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 65 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 66 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 67 | mdss_mdp_intf_off = 0x59100; |
| 68 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 69 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 70 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 71 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 72 | |
| 73 | return mdss_mdp_intf_off; |
| 74 | } |
| 75 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 76 | static uint32_t mdss_mdp_get_ppb_offset() |
| 77 | { |
| 78 | uint32_t mdss_mdp_ppb_off = 0; |
| 79 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 80 | |
| 81 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
| 82 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) |
| 83 | mdss_mdp_ppb_off = 0x1420; |
| 84 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 85 | mdss_mdp_ppb_off = 0x1334; |
| 86 | else |
| 87 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 88 | |
| 89 | return mdss_mdp_ppb_off; |
| 90 | } |
| 91 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 92 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 93 | { |
| 94 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 95 | |
| 96 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 97 | return 0xB0020; |
| 98 | else |
| 99 | return 0xC8020; |
| 100 | } |
| 101 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 102 | void mdp_clk_gating_ctrl(void) |
| 103 | { |
| 104 | writel(0x40000000, MDP_CLK_CTRL0); |
| 105 | udelay(20); |
| 106 | writel(0x40000040, MDP_CLK_CTRL0); |
| 107 | writel(0x40000000, MDP_CLK_CTRL1); |
| 108 | writel(0x00400000, MDP_CLK_CTRL3); |
| 109 | udelay(20); |
| 110 | writel(0x00404000, MDP_CLK_CTRL3); |
| 111 | writel(0x40000000, MDP_CLK_CTRL4); |
| 112 | } |
| 113 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 114 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 115 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 116 | { |
| 117 | switch (pinfo->pipe_type) { |
| 118 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 119 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 120 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 121 | break; |
| 122 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 123 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 124 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 125 | break; |
| 126 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 127 | default: |
| 128 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 129 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 130 | break; |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 135 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 136 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 137 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 138 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 139 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 140 | switch (pinfo->pipe_type) { |
| 141 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 142 | if (dual_pipe_single_ctl) |
| 143 | *ctl0_reg_val = 0x220D8; |
| 144 | else |
| 145 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 146 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 147 | |
| 148 | if (pinfo->lcdc.dst_split) |
| 149 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 150 | break; |
| 151 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 152 | if (dual_pipe_single_ctl) |
| 153 | *ctl0_reg_val = 0x238C0; |
| 154 | else |
| 155 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 156 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 157 | if (pinfo->lcdc.dst_split) |
| 158 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 159 | break; |
| 160 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 161 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 162 | if (dual_pipe_single_ctl) |
| 163 | *ctl0_reg_val = 0x220C3; |
| 164 | else |
| 165 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 166 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 167 | if (pinfo->lcdc.dst_split) |
| 168 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 169 | break; |
| 170 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 171 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 172 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 173 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 174 | if (pinfo->dest == DISPLAY_2) { |
| 175 | *ctl0_reg_val |= BIT(31); |
| 176 | *ctl1_reg_val |= BIT(30); |
| 177 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 178 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 179 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 180 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 181 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame^] | 182 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
| 183 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 184 | if (pinfo->dest == DISPLAY_2) { |
| 185 | *ctl0_reg_val |= BIT(29); |
| 186 | *ctl1_reg_val |= BIT(30); |
| 187 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 188 | *ctl0_reg_val |= BIT(30); |
| 189 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 190 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 191 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 192 | } |
| 193 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 194 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 195 | *pinfo, uint32_t pipe_base) |
| 196 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 197 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 198 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 199 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 200 | uint32_t src_xy = 0, dst_xy = 0; |
| 201 | uint32_t height, width; |
| 202 | |
| 203 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 204 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 205 | |
| 206 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 207 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 208 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 209 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 210 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 211 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 212 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 213 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 214 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | stride = (fb->stride * fb->bpp/8); |
| 218 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 219 | if (fb_off == 0) { /* left */ |
| 220 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 221 | src_xy = dst_xy; |
| 222 | } else { /* right */ |
| 223 | dst_xy = (pinfo->border_top << 16); |
| 224 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 225 | } |
| 226 | |
| 227 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 228 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 229 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 230 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 231 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 232 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 233 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 234 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 235 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 236 | |
| 237 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 238 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 239 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 240 | |
| 241 | /* bit(0) is set if hflip is required. |
| 242 | * bit(1) is set if vflip is required. |
| 243 | */ |
| 244 | if (pinfo->orientation & 0x1) |
| 245 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 246 | if (pinfo->orientation & 0x2) |
| 247 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
| 248 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 249 | } |
| 250 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 251 | static void mdss_vbif_setup() |
| 252 | { |
| 253 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 254 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 255 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 256 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 257 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 258 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 259 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 260 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 261 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 262 | |
| 263 | /* |
| 264 | * Following configuration is needed because on some versions, |
| 265 | * recommended reset values are not stored. |
| 266 | */ |
| 267 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 268 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 269 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 270 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 271 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 272 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 273 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 274 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 275 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 276 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 277 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 278 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 279 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 280 | } |
| 281 | } |
| 282 | } |
| 283 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 284 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 285 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 286 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 287 | uint32_t i, j; |
| 288 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 289 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 290 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 291 | /* max 3 MMB per register */ |
| 292 | reg_val |= client_id << (((j++) % 3) * 8); |
| 293 | if ((j % 3) == 0) { |
| 294 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 295 | free_smp_offset); |
| 296 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 297 | free_smp_offset); |
| 298 | reg_val = 0; |
| 299 | free_smp_offset += 4; |
| 300 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 301 | } |
| 302 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 303 | if (j % 3) { |
| 304 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 305 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 306 | free_smp_offset += 4; |
| 307 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 308 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 309 | return free_smp_offset; |
| 310 | } |
| 311 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 312 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 313 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 314 | { |
| 315 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 316 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 317 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 318 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
| 319 | switch (pinfo->pipe_type) { |
| 320 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 321 | *left_sspp_client_id = 0x7; /* 7 */ |
| 322 | *right_sspp_client_id = 0x11; /* 17 */ |
| 323 | break; |
| 324 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 325 | *left_sspp_client_id = 0x4; /* 4 */ |
| 326 | *right_sspp_client_id = 0xD; /* 13 */ |
| 327 | break; |
| 328 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 329 | default: |
| 330 | *left_sspp_client_id = 0x1; /* 1 */ |
| 331 | *right_sspp_client_id = 0x4; /* 4 */ |
| 332 | break; |
| 333 | } |
| 334 | } else { |
| 335 | switch (pinfo->pipe_type) { |
| 336 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 337 | *left_sspp_client_id = 0x10; /* 16 */ |
| 338 | *right_sspp_client_id = 0x11; /* 17 */ |
| 339 | break; |
| 340 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 341 | *left_sspp_client_id = 0xA; /* 10 */ |
| 342 | *right_sspp_client_id = 0xD; /* 13 */ |
| 343 | break; |
| 344 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 345 | default: |
| 346 | *left_sspp_client_id = 0x1; /* 1 */ |
| 347 | *right_sspp_client_id = 0x4; /* 4 */ |
| 348 | break; |
| 349 | } |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 354 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 355 | { |
| 356 | switch (pinfo->pipe_type) { |
| 357 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 358 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 359 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 360 | break; |
| 361 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 362 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 363 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 364 | break; |
| 365 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 366 | default: |
| 367 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 368 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 369 | break; |
| 370 | } |
| 371 | } |
| 372 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 373 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 374 | uint32_t right_pipe) |
| 375 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 376 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 377 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 378 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 379 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 380 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 381 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 382 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 383 | /* 8Kb per SMP on 8916 */ |
| 384 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 385 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 386 | /* 10Kb per SMP on 8939 */ |
| 387 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 388 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 389 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 390 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 391 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 392 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 393 | fixed_smp_cnt = 2; |
| 394 | else |
| 395 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 396 | } |
| 397 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 398 | mdp_select_pipe_client_id(pinfo, |
| 399 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 400 | |
| 401 | /* Each pipe driving half the screen */ |
| 402 | if (pinfo->lcdc.dual_pipe) |
| 403 | xres /= 2; |
| 404 | |
| 405 | /* bpp = bytes per pixel of input image */ |
| 406 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 407 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 408 | |
| 409 | if (smp_cnt > 4) { |
| 410 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 411 | smp_cnt); |
| 412 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 413 | } |
| 414 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 415 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 416 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 417 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 418 | |
| 419 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 420 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 421 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 422 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 423 | } |
| 424 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 425 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 426 | fixed_smp_cnt, free_smp_offset); |
| 427 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 428 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 429 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 430 | } |
| 431 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 432 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 433 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 434 | uint32_t hsync_period, vsync_period; |
| 435 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 436 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 437 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 438 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 439 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 440 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 441 | |
| 442 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 443 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 444 | |
| 445 | lcdc = &(pinfo->lcdc); |
| 446 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 447 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 448 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 449 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 450 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 451 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 452 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 453 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 454 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 455 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 456 | } |
| 457 | } |
| 458 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 459 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 460 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 461 | writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 462 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 463 | } |
| 464 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 465 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 466 | pinfo->fbc.comp_ratio = 1; |
| 467 | |
| 468 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 469 | itp.yres = pinfo->yres; |
| 470 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 471 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 472 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 473 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 474 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 475 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 476 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 477 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 478 | |
| 479 | itp.border_clr = pinfo->lcdc.border_clr; |
| 480 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 481 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 482 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 483 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 484 | itp.width + itp.h_front_porch; |
| 485 | |
| 486 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 487 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 488 | |
| 489 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 490 | itp.hsync_pulse_width + |
| 491 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 492 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 493 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 494 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 495 | display_vstart = (itp.vsync_pulse_width + |
| 496 | itp.v_back_porch) |
| 497 | * hsync_period + itp.hsync_skew; |
| 498 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 499 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 500 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 501 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 502 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 503 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 504 | } |
| 505 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 506 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 507 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 508 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 509 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 510 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 511 | intf_base); |
| 512 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 513 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 514 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 515 | intf_base); |
| 516 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 517 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 518 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 519 | intf_base); |
| 520 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 521 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 522 | intf_base); |
| 523 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 524 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 525 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 526 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 527 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 528 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 529 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 530 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 531 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 532 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 533 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 534 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 535 | } |
| 536 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 537 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 538 | uint32_t intf_base) |
| 539 | { |
| 540 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 541 | uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines; |
| 542 | uint32_t adjust_xres = 0; |
| 543 | |
| 544 | struct lcdc_panel_info *lcdc = NULL; |
| 545 | |
| 546 | if (pinfo == NULL) |
| 547 | return; |
| 548 | |
| 549 | lcdc = &(pinfo->lcdc); |
| 550 | if (lcdc == NULL) |
| 551 | return; |
| 552 | |
| 553 | /* |
| 554 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 555 | * Programmable fetch is not needed if vertical back porch |
| 556 | * is >= 9. |
| 557 | */ |
| 558 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
| 559 | lcdc->v_back_porch >= MDP_MIN_FETCH) |
| 560 | return; |
| 561 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 562 | adjust_xres = pinfo->xres; |
| 563 | if (pinfo->lcdc.split_display) |
| 564 | adjust_xres /= 2; |
| 565 | |
| 566 | /* |
| 567 | * Fetch should always be outside the active lines. If the fetching |
| 568 | * is programmed within active region, hardware behavior is unknown. |
| 569 | */ |
| 570 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 571 | lcdc->v_front_porch; |
| 572 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 573 | lcdc->h_front_porch; |
| 574 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 575 | |
| 576 | fetch_lines = v_total - vfp_start; |
| 577 | |
| 578 | /* |
| 579 | * In some cases, vertical front porch is too high. In such cases limit |
| 580 | * the mdp fetch lines as the last 12 lines of vertical front porch. |
| 581 | */ |
| 582 | if (fetch_lines > MDSS_MDP_MAX_FETCH) |
| 583 | fetch_lines = MDSS_MDP_MAX_FETCH; |
| 584 | |
| 585 | fetch_start = (v_total - fetch_lines) * h_total + 1; |
| 586 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 587 | writel(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 588 | writel(BIT(31), MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 589 | } |
| 590 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 591 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 592 | *pinfo) |
| 593 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 594 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 595 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 596 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 597 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 598 | width = fb->width; |
| 599 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 600 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 601 | width /= 2; |
| 602 | |
| 603 | /* write active region size*/ |
| 604 | mdp_rgb_size = (height << 16) | width; |
| 605 | |
| 606 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 607 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 608 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 609 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 610 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 611 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 612 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 613 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 614 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 615 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 616 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 617 | switch (pinfo->pipe_type) { |
| 618 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 619 | left_staging_level = 0x0000200; |
| 620 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 621 | break; |
| 622 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 623 | left_staging_level = 0x0040000; |
| 624 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 625 | break; |
| 626 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 627 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 628 | left_staging_level = 0x1; |
| 629 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 630 | break; |
| 631 | } |
| 632 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 633 | /* |
| 634 | * When ping-pong split is enabled and two pipes are used, |
| 635 | * both the pipes need to be staged on the same layer mixer. |
| 636 | */ |
| 637 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 638 | left_staging_level |= right_staging_level; |
| 639 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 640 | /* Base layer for layer mixer 0 */ |
| 641 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 642 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 643 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 644 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 645 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 646 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 647 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 648 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 649 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 650 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 651 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 652 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 653 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 654 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 655 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 656 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 657 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 658 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 659 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 660 | } |
| 661 | } |
| 662 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 663 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 664 | { |
| 665 | uint32_t mode = 0; |
| 666 | uint32_t budget_ctl = 0; |
| 667 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 668 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 669 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 670 | |
| 671 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 672 | |
| 673 | if (!pinfo->fbc.enabled) |
| 674 | return; |
| 675 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 676 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 677 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 678 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 679 | width = pinfo->xres; |
| 680 | if (enc_mode) |
| 681 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 682 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 683 | if (pinfo->mipi.dual_dsi) |
| 684 | width /= 2; |
| 685 | |
| 686 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 687 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 688 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 689 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 690 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 691 | |
| 692 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 693 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 694 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 695 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 696 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 697 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 698 | |
| 699 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 700 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 701 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 702 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 703 | ((fbc->lossy_mode_thd) << 8) | |
| 704 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 705 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 706 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 707 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 708 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 709 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 710 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 711 | |
| 712 | if (pinfo->mipi.dual_dsi) { |
| 713 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 714 | writel(budget_ctl, MDP_PP_1_BASE + |
| 715 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 716 | writel(lossy_mode, MDP_PP_1_BASE + |
| 717 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 718 | } |
| 719 | } |
| 720 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 721 | void mdss_qos_remapper_setup(void) |
| 722 | { |
| 723 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 724 | uint32_t map; |
| 725 | |
| 726 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 727 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 728 | MDSS_MDP_HW_REV_102)) |
| 729 | map = 0xE9; |
| 730 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 731 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 732 | map = 0xA5; |
| 733 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 734 | MDSS_MDP_HW_REV_106) || |
| 735 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 736 | MDSS_MDP_HW_REV_108)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 737 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 738 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 739 | MDSS_MDP_HW_REV_105) || |
| 740 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame^] | 741 | MDSS_MDP_HW_REV_109) || |
| 742 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 743 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 744 | map = 0xA4; |
| 745 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 746 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 747 | map = 0xFA; |
| 748 | else |
| 749 | return; |
| 750 | |
| 751 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 752 | } |
| 753 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 754 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 755 | { |
| 756 | uint32_t mask, reg_val, i; |
| 757 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 758 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 759 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 760 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 761 | |
| 762 | mdp_select_pipe_xin_id(pinfo, |
| 763 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 764 | |
| 765 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
| 766 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) { |
| 767 | vbif_qos[0] = 2; |
| 768 | vbif_qos[1] = 2; |
| 769 | vbif_qos[2] = 2; |
| 770 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 771 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame^] | 772 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
| 773 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 774 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 775 | vbif_qos[1] = 2; |
| 776 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 777 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 778 | } else { |
| 779 | return; |
| 780 | } |
| 781 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 782 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 783 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 784 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 785 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 786 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 787 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 788 | reg_val &= ~(mask); |
| 789 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 790 | |
| 791 | if (pinfo->lcdc.dual_pipe) { |
| 792 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 793 | reg_val &= ~(mask); |
| 794 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 795 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 796 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 797 | } |
| 798 | } |
| 799 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 800 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 801 | int is_main_ctl) |
| 802 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 803 | uint32_t mctl_intf_sel; |
| 804 | uint32_t sctl_intf_sel; |
| 805 | |
| 806 | if ((pinfo->dest == DISPLAY_2) || |
| 807 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 808 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 809 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 810 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 811 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 812 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 813 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 814 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 815 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 816 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 817 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 818 | } |
| 819 | |
| 820 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 821 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 822 | uint32_t *intf_base, uint32_t *sintf_base) |
| 823 | { |
| 824 | if (pinfo->dest == DISPLAY_2) { |
| 825 | *intf_sel = BIT(16); |
| 826 | *sintf_sel = BIT(8); |
| 827 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 828 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 829 | } else { |
| 830 | *intf_sel = BIT(8); |
| 831 | *sintf_sel = BIT(16); |
| 832 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 833 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 834 | } |
| 835 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 836 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 837 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 838 | } |
| 839 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 840 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 841 | struct fbcon_config *fb) |
| 842 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 843 | uint32_t intf_sel, sintf_sel; |
| 844 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 845 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 846 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 847 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 848 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 849 | |
| 850 | mdss_intf_tg_setup(pinfo, intf_base); |
| 851 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 852 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 853 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 854 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 855 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 856 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 857 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 858 | mdp_clk_gating_ctrl(); |
| 859 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 860 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 861 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 862 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 863 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 864 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 865 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 866 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 867 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 868 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 869 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 870 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 871 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 872 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 873 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 874 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 875 | |
| 876 | /* enable 3D mux for dual_pipe but single interface config */ |
| 877 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 878 | !pinfo->lcdc.split_display) |
| 879 | reg |= BIT(19) | BIT(20); |
| 880 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 881 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 882 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 883 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 884 | CTL_1 path should not be set since CTL_0 itself is going |
| 885 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 886 | if (pinfo->fbc.enabled) |
| 887 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 888 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 889 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 890 | if (!pinfo->lcdc.dst_split) { |
| 891 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 892 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 893 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 894 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 895 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 896 | |
| 897 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 898 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 899 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 900 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 901 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 902 | |
| 903 | return 0; |
| 904 | } |
| 905 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 906 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 907 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 908 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 909 | |
| 910 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 911 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 912 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 913 | mdp_clk_gating_ctrl(); |
| 914 | |
| 915 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 916 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 917 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 918 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 919 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 920 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 921 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 922 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 923 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 924 | |
| 925 | mdss_layer_mixer_setup(fb, pinfo); |
| 926 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 927 | if (pinfo->lcdc.dual_pipe) |
| 928 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 929 | else |
| 930 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 931 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 932 | writel(0x9, MDP_DISP_INTF_SEL); |
| 933 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 934 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 935 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 936 | |
| 937 | return 0; |
| 938 | } |
| 939 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 940 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 941 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 942 | uint32_t left_pipe, right_pipe; |
| 943 | |
| 944 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); |
| 945 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 946 | |
| 947 | mdp_clk_gating_ctrl(); |
| 948 | mdss_vbif_setup(); |
| 949 | |
| 950 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 951 | |
| 952 | mdss_qos_remapper_setup(); |
| 953 | |
| 954 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 955 | if (pinfo->lcdc.dual_pipe) |
| 956 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 957 | |
| 958 | mdss_layer_mixer_setup(fb, pinfo); |
| 959 | |
| 960 | if (pinfo->lcdc.dual_pipe) |
| 961 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 962 | else |
| 963 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 964 | |
| 965 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 966 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 967 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 968 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 969 | |
| 970 | return 0; |
| 971 | } |
| 972 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 973 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 974 | struct fbcon_config *fb) |
| 975 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 976 | uint32_t intf_sel, sintf_sel; |
| 977 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 978 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 979 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 980 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 981 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 982 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 983 | |
| 984 | if (pinfo == NULL) |
| 985 | return ERR_INVALID_ARGS; |
| 986 | |
| 987 | lcdc = &(pinfo->lcdc); |
| 988 | if (lcdc == NULL) |
| 989 | return ERR_INVALID_ARGS; |
| 990 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 991 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 992 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 993 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 994 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 995 | if (pinfo->lcdc.dst_split) |
| 996 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 997 | if (pinfo->lcdc.pipe_swap) |
| 998 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 999 | else |
| 1000 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1001 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1002 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1003 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1004 | } |
| 1005 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1006 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1007 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 1008 | writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 1009 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1010 | } |
| 1011 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1012 | mdp_clk_gating_ctrl(); |
| 1013 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1014 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1015 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1016 | |
| 1017 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1018 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1019 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1020 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1021 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1022 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1023 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1024 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1025 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1026 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1027 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1028 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1029 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1030 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1031 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1032 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1033 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 1034 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1035 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1036 | if (pinfo->fbc.enabled) |
| 1037 | mdss_fbc_cfg(pinfo); |
| 1038 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1039 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1040 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1041 | if (!pinfo->lcdc.dst_split) { |
| 1042 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1043 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1044 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1045 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1046 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1047 | return ret; |
| 1048 | } |
| 1049 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1050 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1051 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1052 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1053 | uint32_t timing_engine_en; |
| 1054 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1055 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1056 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1057 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1058 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1059 | |
| 1060 | if (pinfo->dest == DISPLAY_1) |
| 1061 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1062 | else |
| 1063 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1064 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1065 | |
| 1066 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1067 | } |
| 1068 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1069 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1070 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1071 | uint32_t timing_engine_en; |
| 1072 | |
| 1073 | if (pinfo->dest == DISPLAY_1) |
| 1074 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1075 | else |
| 1076 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1077 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1078 | if(!target_cont_splash_screen()) |
| 1079 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1080 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1081 | mdelay(60); |
| 1082 | /* Ping-Pong done Tear Check Read/Write */ |
| 1083 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1084 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1085 | } |
| 1086 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1087 | writel(0x00000000, MDP_INTR_EN); |
| 1088 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1089 | return NO_ERROR; |
| 1090 | } |
| 1091 | |
| 1092 | int mdp_dsi_cmd_off() |
| 1093 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1094 | if(!target_cont_splash_screen()) |
| 1095 | { |
| 1096 | /* Ping-Pong done Tear Check Read/Write */ |
| 1097 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1098 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1099 | } |
| 1100 | writel(0x00000000, MDP_INTR_EN); |
| 1101 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1102 | return NO_ERROR; |
| 1103 | } |
| 1104 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1105 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1106 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1107 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1108 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1109 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1110 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1111 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1112 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1113 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1114 | return NO_ERROR; |
| 1115 | } |
| 1116 | |
| 1117 | void mdp_disable(void) |
| 1118 | { |
| 1119 | |
| 1120 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1121 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1122 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1123 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1124 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1125 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1126 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1127 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1128 | return NO_ERROR; |
| 1129 | } |
| 1130 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1131 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1132 | { |
| 1133 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1134 | |
| 1135 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1136 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1137 | |
| 1138 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1139 | |
| 1140 | return NO_ERROR; |
| 1141 | } |
| 1142 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1143 | int mdp_edp_off(void) |
| 1144 | { |
| 1145 | if (!target_cont_splash_screen()) { |
| 1146 | |
| 1147 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1148 | mdss_mdp_intf_offset()); |
| 1149 | mdelay(60); |
| 1150 | /* Ping-Pong done Tear Check Read/Write */ |
| 1151 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1152 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1153 | writel(0x00000000, MDP_INTR_EN); |
| 1154 | } |
| 1155 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1156 | writel(0x00000000, MDP_INTR_EN); |
| 1157 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1158 | return NO_ERROR; |
| 1159 | } |