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gerrit-public.fairphone.software / kernel / msm-4.19 / be76fd3197df608e1b010bf5ab90377205f54344 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 3a3fde1f84c7b92d2a689d35810281a637aa7580 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]14/ {
15 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]16 interrupt-parent = <&intc>;
Javier Martinez Canillasf8bf0162016-08-31 12:35:21 +0200[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
Dave Gerlach0f416d12016-09-14 16:26:53 -0700[diff] [blame]48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]106 wkup_m3: wkup_m3@100000 {
107 compatible = "ti,am3352-wkup-m3";
108 reg = <0x100000 0x4000>,
109 <0x180000 0x2000>;
110 reg-names = "umem", "dmem";
111 ti,hwmods = "wkup_m3";
112 ti,pm-firmware = "am335x-pm-firmware.elf";
113 };
114
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]115 prcm: prcm@200000 {
116 compatible = "ti,am3-prcm";
117 reg = <0x200000 0x4000>;
118
119 prcm_clocks: clocks {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123
124 prcm_clockdomains: clockdomains {
125 };
126 };
127
128 scm: scm@210000 {
129 compatible = "ti,am3-scm", "simple-bus";
130 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]131 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]132 #size-cells = <1>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame^]133 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]134 ranges = <0 0x210000 0x2000>;
135
136 am33xx_pinmux: pinmux@800 {
137 compatible = "pinctrl-single";
138 reg = <0x800 0x238>;
139 #address-cells = <1>;
140 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame^]141 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]142 pinctrl-single,register-width = <32>;
143 pinctrl-single,function-mask = <0x7f>;
144 };
145
146 scm_conf: scm_conf@0 {
147 compatible = "syscon";
148 reg = <0x0 0x800>;
149 #address-cells = <1>;
150 #size-cells = <1>;
151
152 scm_clocks: clocks {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 };
156 };
157
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]158 wkup_m3_ipc: wkup_m3_ipc@1324 {
159 compatible = "ti,am3352-wkup-m3-ipc";
160 reg = <0x1324 0x24>;
161 interrupts = <78>;
162 ti,rproc = <&wkup_m3>;
163 mboxes = <&mailbox &mbox_wkupm3>;
164 };
165
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]166 edma_xbar: dma-router@f90 {
167 compatible = "ti,am335x-edma-crossbar";
168 reg = <0xf90 0x40>;
169 #dma-cells = <3>;
170 dma-requests = <32>;
171 dma-masters = <&edma>;
172 };
173
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]174 scm_clockdomains: clockdomains {
175 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]176 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]177 };
178
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]179 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]180 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 interrupt-controller;
182 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]183 reg = <0x48200000 0x1000>;
184 };
185
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]186 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]187 compatible = "ti,edma3-tpcc";
188 ti,hwmods = "tpcc";
189 reg = <0x49000000 0x10000>;
190 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]191 interrupts = <12 13 14>;
Robert P. J. Daya5206552016-05-24 17:20:28 -0400[diff] [blame]192 interrupt-names = "edma3_ccint", "edma3_mperr",
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]193 "edma3_ccerrint";
194 dma-requests = <64>;
195 #dma-cells = <2>;
196
197 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
198 <&edma_tptc2 0>;
199
200 ti,edma-memcpy-channels = <20 21>;
201 };
202
203 edma_tptc0: tptc@49800000 {
204 compatible = "ti,edma3-tptc";
205 ti,hwmods = "tptc0";
206 reg = <0x49800000 0x100000>;
207 interrupts = <112>;
208 interrupt-names = "edma3_tcerrint";
209 };
210
211 edma_tptc1: tptc@49900000 {
212 compatible = "ti,edma3-tptc";
213 ti,hwmods = "tptc1";
214 reg = <0x49900000 0x100000>;
215 interrupts = <113>;
216 interrupt-names = "edma3_tcerrint";
217 };
218
219 edma_tptc2: tptc@49a00000 {
220 compatible = "ti,edma3-tptc";
221 ti,hwmods = "tptc2";
222 reg = <0x49a00000 0x100000>;
223 interrupts = <114>;
224 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]225 };
226
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]227 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]228 compatible = "ti,omap4-gpio";
229 ti,hwmods = "gpio1";
230 gpio-controller;
231 #gpio-cells = <2>;
232 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]233 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]234 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]236 };
237
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]238 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]239 compatible = "ti,omap4-gpio";
240 ti,hwmods = "gpio2";
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]244 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]245 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]246 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]247 };
248
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]249 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]250 compatible = "ti,omap4-gpio";
251 ti,hwmods = "gpio3";
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]255 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]256 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]257 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]258 };
259
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]260 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]261 compatible = "ti,omap4-gpio";
262 ti,hwmods = "gpio4";
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]266 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]267 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]268 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]269 };
270
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]271 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]272 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]273 ti,hwmods = "uart1";
274 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]275 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]276 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]277 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]278 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]279 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]280 };
281
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]282 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]283 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]284 ti,hwmods = "uart2";
285 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]286 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]287 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]288 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]289 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]290 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]291 };
292
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]293 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]294 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]295 ti,hwmods = "uart3";
296 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]297 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]298 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]299 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]300 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]301 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]302 };
303
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]304 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]305 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]306 ti,hwmods = "uart4";
307 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]308 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]309 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]310 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]311 };
312
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]313 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]314 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]315 ti,hwmods = "uart5";
316 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]317 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]318 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]319 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]320 };
321
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]322 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]323 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]324 ti,hwmods = "uart6";
325 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]326 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]327 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]328 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]329 };
330
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]331 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]332 compatible = "ti,omap4-i2c";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]336 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]337 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]338 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]339 };
340
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]341 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]342 compatible = "ti,omap4-i2c";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]346 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]347 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]348 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]349 };
350
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]351 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]352 compatible = "ti,omap4-i2c";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]356 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]357 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]358 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]359 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]360
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]361 mmc1: mmc@48060000 {
362 compatible = "ti,omap4-hsmmc";
363 ti,hwmods = "mmc1";
364 ti,dual-volt;
365 ti,needs-special-reset;
366 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]367 dmas = <&edma_xbar 24 0 0
368 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]369 dma-names = "tx", "rx";
370 interrupts = <64>;
371 interrupt-parent = <&intc>;
372 reg = <0x48060000 0x1000>;
373 status = "disabled";
374 };
375
376 mmc2: mmc@481d8000 {
377 compatible = "ti,omap4-hsmmc";
378 ti,hwmods = "mmc2";
379 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]380 dmas = <&edma 2 0
381 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]382 dma-names = "tx", "rx";
383 interrupts = <28>;
384 interrupt-parent = <&intc>;
385 reg = <0x481d8000 0x1000>;
386 status = "disabled";
387 };
388
389 mmc3: mmc@47810000 {
390 compatible = "ti,omap4-hsmmc";
391 ti,hwmods = "mmc3";
392 ti,needs-special-reset;
393 interrupts = <29>;
394 interrupt-parent = <&intc>;
395 reg = <0x47810000 0x1000>;
396 status = "disabled";
397 };
398
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]399 hwspinlock: spinlock@480ca000 {
400 compatible = "ti,omap4-hwspinlock";
401 reg = <0x480ca000 0x1000>;
402 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]403 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]404 };
405
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]406 wdt2: wdt@44e35000 {
407 compatible = "ti,omap3-wdt";
408 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]409 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]410 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]411 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]412
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]413 dcan0: can@481cc000 {
414 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]415 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]416 reg = <0x481cc000 0x2000>;
417 clocks = <&dcan0_fck>;
418 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]419 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]420 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]421 status = "disabled";
422 };
423
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]424 dcan1: can@481d0000 {
425 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]426 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]427 reg = <0x481d0000 0x2000>;
428 clocks = <&dcan1_fck>;
429 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]430 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]431 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]432 status = "disabled";
433 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]434
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]435 mailbox: mailbox@480C8000 {
436 compatible = "ti,omap4-mailbox";
437 reg = <0x480C8000 0x200>;
438 interrupts = <77>;
439 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]440 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]441 ti,mbox-num-users = <4>;
442 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]443 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]444 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]445 ti,mbox-tx = <0 0 0>;
446 ti,mbox-rx = <0 0 3>;
447 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]448 };
449
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]450 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]451 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]452 reg = <0x44e31000 0x400>;
453 interrupts = <67>;
454 ti,hwmods = "timer1";
455 ti,timer-alwon;
456 };
457
458 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]459 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]460 reg = <0x48040000 0x400>;
461 interrupts = <68>;
462 ti,hwmods = "timer2";
463 };
464
465 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]466 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]467 reg = <0x48042000 0x400>;
468 interrupts = <69>;
469 ti,hwmods = "timer3";
470 };
471
472 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]473 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]474 reg = <0x48044000 0x400>;
475 interrupts = <92>;
476 ti,hwmods = "timer4";
477 ti,timer-pwm;
478 };
479
480 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]481 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]482 reg = <0x48046000 0x400>;
483 interrupts = <93>;
484 ti,hwmods = "timer5";
485 ti,timer-pwm;
486 };
487
488 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]489 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]490 reg = <0x48048000 0x400>;
491 interrupts = <94>;
492 ti,hwmods = "timer6";
493 ti,timer-pwm;
494 };
495
496 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]497 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]498 reg = <0x4804a000 0x400>;
499 interrupts = <95>;
500 ti,hwmods = "timer7";
501 ti,timer-pwm;
502 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]503
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]504 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]505 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]506 reg = <0x44e3e000 0x1000>;
507 interrupts = <75
508 76>;
509 ti,hwmods = "rtc";
510 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]511
512 spi0: spi@48030000 {
513 compatible = "ti,omap4-mcspi";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]517 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]518 ti,spi-num-cs = <2>;
519 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]520 dmas = <&edma 16 0
521 &edma 17 0
522 &edma 18 0
523 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]524 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]525 status = "disabled";
526 };
527
528 spi1: spi@481a0000 {
529 compatible = "ti,omap4-mcspi";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]533 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]534 ti,spi-num-cs = <2>;
535 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]536 dmas = <&edma 42 0
537 &edma 43 0
538 &edma 44 0
539 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]540 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]541 status = "disabled";
542 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]543
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]544 usb: usb@47400000 {
545 compatible = "ti,am33xx-usb";
546 reg = <0x47400000 0x1000>;
547 ranges;
548 #address-cells = <1>;
549 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]550 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]551 status = "disabled";
552
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]553 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]554 compatible = "ti,am335x-usb-ctrl-module";
555 reg = <0x44e10620 0x10
556 0x44e10648 0x4>;
557 reg-names = "phy_ctrl", "wakeup";
558 status = "disabled";
559 };
560
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]561 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]562 compatible = "ti,am335x-usb-phy";
563 reg = <0x47401300 0x100>;
564 reg-names = "phy";
565 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]566 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]567 };
568
569 usb0: usb@47401000 {
570 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]571 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]572 reg = <0x47401400 0x400
573 0x47401000 0x200>;
574 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]575
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]576 interrupts = <18>;
577 interrupt-names = "mc";
578 dr_mode = "otg";
579 mentor,multipoint = <1>;
580 mentor,num-eps = <16>;
581 mentor,ram-bits = <12>;
582 mentor,power = <500>;
583 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]584
585 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
586 &cppi41dma 2 0 &cppi41dma 3 0
587 &cppi41dma 4 0 &cppi41dma 5 0
588 &cppi41dma 6 0 &cppi41dma 7 0
589 &cppi41dma 8 0 &cppi41dma 9 0
590 &cppi41dma 10 0 &cppi41dma 11 0
591 &cppi41dma 12 0 &cppi41dma 13 0
592 &cppi41dma 14 0 &cppi41dma 0 1
593 &cppi41dma 1 1 &cppi41dma 2 1
594 &cppi41dma 3 1 &cppi41dma 4 1
595 &cppi41dma 5 1 &cppi41dma 6 1
596 &cppi41dma 7 1 &cppi41dma 8 1
597 &cppi41dma 9 1 &cppi41dma 10 1
598 &cppi41dma 11 1 &cppi41dma 12 1
599 &cppi41dma 13 1 &cppi41dma 14 1>;
600 dma-names =
601 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
602 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
603 "rx14", "rx15",
604 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
605 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
606 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]607 };
608
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]609 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]610 compatible = "ti,am335x-usb-phy";
611 reg = <0x47401b00 0x100>;
612 reg-names = "phy";
613 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]614 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]615 };
616
617 usb1: usb@47401800 {
618 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]619 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]620 reg = <0x47401c00 0x400
621 0x47401800 0x200>;
622 reg-names = "mc", "control";
623 interrupts = <19>;
624 interrupt-names = "mc";
625 dr_mode = "otg";
626 mentor,multipoint = <1>;
627 mentor,num-eps = <16>;
628 mentor,ram-bits = <12>;
629 mentor,power = <500>;
630 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]631
632 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
633 &cppi41dma 17 0 &cppi41dma 18 0
634 &cppi41dma 19 0 &cppi41dma 20 0
635 &cppi41dma 21 0 &cppi41dma 22 0
636 &cppi41dma 23 0 &cppi41dma 24 0
637 &cppi41dma 25 0 &cppi41dma 26 0
638 &cppi41dma 27 0 &cppi41dma 28 0
639 &cppi41dma 29 0 &cppi41dma 15 1
640 &cppi41dma 16 1 &cppi41dma 17 1
641 &cppi41dma 18 1 &cppi41dma 19 1
642 &cppi41dma 20 1 &cppi41dma 21 1
643 &cppi41dma 22 1 &cppi41dma 23 1
644 &cppi41dma 24 1 &cppi41dma 25 1
645 &cppi41dma 26 1 &cppi41dma 27 1
646 &cppi41dma 28 1 &cppi41dma 29 1>;
647 dma-names =
648 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
649 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
650 "rx14", "rx15",
651 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
652 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
653 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]654 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]655
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]656 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]657 compatible = "ti,am3359-cppi41";
658 reg = <0x47400000 0x1000
659 0x47402000 0x1000
660 0x47403000 0x1000
661 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]662 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]663 interrupts = <17>;
664 interrupt-names = "glue";
665 #dma-cells = <2>;
666 #dma-channels = <30>;
667 #dma-requests = <256>;
668 status = "disabled";
669 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]670 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]671
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]672 epwmss0: epwmss@48300000 {
673 compatible = "ti,am33xx-pwmss";
674 reg = <0x48300000 0x10>;
675 ti,hwmods = "epwmss0";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 status = "disabled";
679 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
680 0x48300180 0x48300180 0x80 /* EQEP */
681 0x48300200 0x48300200 0x80>; /* EHRPWM */
682
683 ecap0: ecap@48300100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]684 compatible = "ti,am3352-ecap",
685 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]686 #pwm-cells = <3>;
687 reg = <0x48300100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]688 clocks = <&l4ls_gclk>;
689 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]690 interrupts = <31>;
691 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]692 status = "disabled";
693 };
694
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]695 ehrpwm0: pwm@48300200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]696 compatible = "ti,am3352-ehrpwm",
697 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]698 #pwm-cells = <3>;
699 reg = <0x48300200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]700 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
701 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]702 status = "disabled";
703 };
704 };
705
706 epwmss1: epwmss@48302000 {
707 compatible = "ti,am33xx-pwmss";
708 reg = <0x48302000 0x10>;
709 ti,hwmods = "epwmss1";
710 #address-cells = <1>;
711 #size-cells = <1>;
712 status = "disabled";
713 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
714 0x48302180 0x48302180 0x80 /* EQEP */
715 0x48302200 0x48302200 0x80>; /* EHRPWM */
716
717 ecap1: ecap@48302100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]718 compatible = "ti,am3352-ecap",
719 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]720 #pwm-cells = <3>;
721 reg = <0x48302100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]722 clocks = <&l4ls_gclk>;
723 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]724 interrupts = <47>;
725 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]726 status = "disabled";
727 };
728
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]729 ehrpwm1: pwm@48302200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]730 compatible = "ti,am3352-ehrpwm",
731 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]732 #pwm-cells = <3>;
733 reg = <0x48302200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]734 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
735 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]736 status = "disabled";
737 };
738 };
739
740 epwmss2: epwmss@48304000 {
741 compatible = "ti,am33xx-pwmss";
742 reg = <0x48304000 0x10>;
743 ti,hwmods = "epwmss2";
744 #address-cells = <1>;
745 #size-cells = <1>;
746 status = "disabled";
747 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
748 0x48304180 0x48304180 0x80 /* EQEP */
749 0x48304200 0x48304200 0x80>; /* EHRPWM */
750
751 ecap2: ecap@48304100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]752 compatible = "ti,am3352-ecap",
753 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]754 #pwm-cells = <3>;
755 reg = <0x48304100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]756 clocks = <&l4ls_gclk>;
757 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]758 interrupts = <61>;
759 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]760 status = "disabled";
761 };
762
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]763 ehrpwm2: pwm@48304200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]764 compatible = "ti,am3352-ehrpwm",
765 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]766 #pwm-cells = <3>;
767 reg = <0x48304200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]768 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
769 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]770 status = "disabled";
771 };
772 };
773
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]774 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]775 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]776 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]777 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
778 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]779 cpdma_channels = <8>;
780 ale_entries = <1024>;
781 bd_ram_size = <0x2000>;
782 no_bd_ram = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]783 mac_control = <0x20>;
784 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]785 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]786 cpts_clock_mult = <0x80000000>;
787 cpts_clock_shift = <29>;
788 reg = <0x4a100000 0x800
789 0x4a101200 0x100>;
790 #address-cells = <1>;
791 #size-cells = <1>;
792 interrupt-parent = <&intc>;
793 /*
794 * c0_rx_thresh_pend
795 * c0_rx_pend
796 * c0_tx_pend
797 * c0_misc_pend
798 */
799 interrupts = <40 41 42 43>;
800 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]801 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]802 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]803
804 davinci_mdio: mdio@4a101000 {
Grygorii Strashko9efd1a62016-06-24 21:23:55 +0300[diff] [blame]805 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]806 #address-cells = <1>;
807 #size-cells = <0>;
808 ti,hwmods = "davinci_mdio";
809 bus_freq = <1000000>;
810 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]811 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]812 };
813
814 cpsw_emac0: slave@4a100200 {
815 /* Filled in by U-Boot */
816 mac-address = [ 00 00 00 00 00 00 ];
817 };
818
819 cpsw_emac1: slave@4a100300 {
820 /* Filled in by U-Boot */
821 mac-address = [ 00 00 00 00 00 00 ];
822 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]823
824 phy_sel: cpsw-phy-sel@44e10650 {
825 compatible = "ti,am3352-cpsw-phy-sel";
826 reg= <0x44e10650 0x4>;
827 reg-names = "gmii-sel";
828 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]829 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]830
831 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]832 compatible = "mmio-sram";
833 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]834 };
835
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]836 elm: elm@48080000 {
837 compatible = "ti,am3352-elm";
838 reg = <0x48080000 0x2000>;
839 interrupts = <4>;
840 ti,hwmods = "elm";
841 status = "disabled";
842 };
843
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]844 lcdc: lcdc@4830e000 {
845 compatible = "ti,am33xx-tilcdc";
846 reg = <0x4830e000 0x1000>;
847 interrupt-parent = <&intc>;
848 interrupts = <36>;
849 ti,hwmods = "lcdc";
850 status = "disabled";
851 };
852
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]853 tscadc: tscadc@44e0d000 {
854 compatible = "ti,am3359-tscadc";
855 reg = <0x44e0d000 0x1000>;
856 interrupt-parent = <&intc>;
857 interrupts = <16>;
858 ti,hwmods = "adc_tsc";
859 status = "disabled";
860
861 tsc {
862 compatible = "ti,am3359-tsc";
863 };
864 am335x_adc: adc {
865 #io-channel-cells = <1>;
866 compatible = "ti,am3359-adc";
867 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]868 };
869
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]870 gpmc: gpmc@50000000 {
871 compatible = "ti,am3352-gpmc";
872 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]873 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]874 reg = <0x50000000 0x2000>;
875 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame]876 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]877 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]878 gpmc,num-cs = <7>;
879 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]880 #address-cells = <2>;
881 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]882 interrupt-controller;
883 #interrupt-cells = <2>;
Roger Quadros4eb4dd52016-04-07 13:25:32 +0300[diff] [blame]884 gpio-controller;
885 #gpio-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]886 status = "disabled";
887 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]888
889 sham: sham@53100000 {
890 compatible = "ti,omap4-sham";
891 ti,hwmods = "sham";
892 reg = <0x53100000 0x200>;
893 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]894 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]895 dma-names = "rx";
896 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]897
898 aes: aes@53500000 {
899 compatible = "ti,omap4-aes";
900 ti,hwmods = "aes";
901 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]902 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]903 dmas = <&edma 6 0>,
904 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]905 dma-names = "tx", "rx";
906 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]907
908 mcasp0: mcasp@48038000 {
909 compatible = "ti,am33xx-mcasp-audio";
910 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]911 reg = <0x48038000 0x2000>,
912 <0x46000000 0x400000>;
913 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]914 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]915 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]916 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]917 dmas = <&edma 8 2>,
918 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]919 dma-names = "tx", "rx";
920 };
921
922 mcasp1: mcasp@4803C000 {
923 compatible = "ti,am33xx-mcasp-audio";
924 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]925 reg = <0x4803C000 0x2000>,
926 <0x46400000 0x400000>;
927 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]928 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]929 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]930 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]931 dmas = <&edma 10 2>,
932 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]933 dma-names = "tx", "rx";
934 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]935
936 rng: rng@48310000 {
937 compatible = "ti,omap4-rng";
938 ti,hwmods = "rng";
939 reg = <0x48310000 0x2000>;
940 interrupts = <111>;
941 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]942 };
943};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]944
945/include/ "am33xx-clocks.dtsi"