blob: a215a4641b25697208db743c040d0bc6079e156f [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
Clint Taylor01527b32014-07-07 13:01:46 -070031#include <linux/notifier.h>
32#include <linux/reboot.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070037#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010038#include <drm/i915_drm.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070039#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070040
Keith Packarda4fc5ed2009-04-07 16:16:42 -070041#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080043struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080062static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
Chon Ming Lee58f6e632013-09-25 15:47:51 +080064 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080065 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
Chon Ming Leeef9348c2014-04-09 13:28:18 +030069/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070087/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070099}
100
Imre Deak68b4d822013-05-08 13:14:06 +0300101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700102{
Imre Deak68b4d822013-05-08 13:14:06 +0300103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700106}
107
Chris Wilsondf0e9242010-09-09 16:20:55 +0100108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
Paulo Zanonifa90ece2012-10-26 19:05:44 -0200110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +0100111}
112
Chris Wilsonea5b2132010-08-04 13:50:23 +0100113static void intel_dp_link_down(struct intel_dp *intel_dp);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +0300114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +0100115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700116
Dave Airlie0e32b392014-05-02 14:02:48 +1000117int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100118intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700119{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Todd Previte06ea66b2014-01-20 10:19:39 -0700121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
Imre Deakd4eead52013-07-09 17:05:26 +0300127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
Paulo Zanoni9bbfd202014-04-29 11:00:22 -0300128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
Todd Previte06ea66b2014-01-20 10:19:39 -0700130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
Imre Deakd4eead52013-07-09 17:05:26 +0300134 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700135 default:
Imre Deakd4eead52013-07-09 17:05:26 +0300136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
Paulo Zanonieeb63242014-05-06 14:56:50 +0300144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700177static int
Keith Packardc8982612012-01-25 08:16:25 -0800178intel_dp_link_required(int pixel_clock, int bpp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700179{
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400180 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700181}
182
183static int
Dave Airliefe27d532010-06-30 11:46:17 +1000184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000189static enum drm_mode_status
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100193 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +0300194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Daniel Vetter36008362013-03-27 00:44:59 +0100196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700198
Jani Nikuladd06f902012-10-19 14:51:50 +0300199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100201 return MODE_PANEL;
202
Jani Nikuladd06f902012-10-19 14:51:50 +0300203 if (mode->vdisplay > fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100204 return MODE_PANEL;
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200205
206 target_clock = fixed_mode->clock;
Zhao Yakui7de56f42010-07-19 09:43:14 +0100207 }
208
Daniel Vetter36008362013-03-27 00:44:59 +0100209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
Paulo Zanonieeb63242014-05-06 14:56:50 +0300210 max_lanes = intel_dp_max_lane_count(intel_dp);
Daniel Vetter36008362013-03-27 00:44:59 +0100211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
Daniel Vetterc4867932012-04-10 10:42:36 +0200216 return MODE_CLOCK_HIGH;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
Daniel Vetter0af78a22012-05-23 11:30:55 +0200221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
Vijay Purushothaman9473c8f2012-09-27 19:13:01 +0530257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
Jani Nikulabf13e812013-09-06 07:40:05 +0300284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300303 lockdep_assert_held(&dev_priv->pps_mutex);
304
Jani Nikulabf13e812013-09-06 07:40:05 +0300305 /* modeset should have pipe */
306 if (crtc)
307 return to_intel_crtc(crtc)->pipe;
308
309 /* init time, try to find a pipe with this port selected */
310 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
311 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
312 PANEL_PORT_SELECT_MASK;
Ville Syrjäläad933b52014-08-18 22:15:56 +0300313 if (port_sel == PANEL_PORT_SELECT_VLV(port))
Jani Nikulabf13e812013-09-06 07:40:05 +0300314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
Clint Taylor01527b32014-07-07 13:01:46 -0700341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
Clint Taylor01527b32014-07-07 13:01:46 -0700352
353 if (!is_edp(intel_dp) || code != SYS_RESTART)
354 return 0;
355
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300356 mutex_lock(&dev_priv->pps_mutex);
357
Clint Taylor01527b32014-07-07 13:01:46 -0700358 if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300359 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
360
Clint Taylor01527b32014-07-07 13:01:46 -0700361 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
362 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
363 pp_div = I915_READ(pp_div_reg);
364 pp_div &= PP_REFERENCE_DIVIDER_MASK;
365
366 /* 0x1F write to PP_DIV_REG sets max cycle delay */
367 I915_WRITE(pp_div_reg, pp_div | 0x1F);
368 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
369 msleep(intel_dp->panel_power_cycle_delay);
370 }
371
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300372 mutex_unlock(&dev_priv->pps_mutex);
373
Clint Taylor01527b32014-07-07 13:01:46 -0700374 return 0;
375}
376
Daniel Vetter4be73782014-01-17 14:39:48 +0100377static bool edp_have_panel_power(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700378{
Paulo Zanoni30add222012-10-26 19:05:45 -0200379 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700380 struct drm_i915_private *dev_priv = dev->dev_private;
381
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300382 lockdep_assert_held(&dev_priv->pps_mutex);
383
Jani Nikulabf13e812013-09-06 07:40:05 +0300384 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700385}
386
Daniel Vetter4be73782014-01-17 14:39:48 +0100387static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700388{
Paulo Zanoni30add222012-10-26 19:05:45 -0200389 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700390 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbb4932c2014-04-14 20:24:33 +0300391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
392 struct intel_encoder *intel_encoder = &intel_dig_port->base;
393 enum intel_display_power_domain power_domain;
Keith Packardebf33b12011-09-29 15:53:27 -0700394
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300395 lockdep_assert_held(&dev_priv->pps_mutex);
396
Imre Deakbb4932c2014-04-14 20:24:33 +0300397 power_domain = intel_display_port_power_domain(intel_encoder);
398 return intel_display_power_enabled(dev_priv, power_domain) &&
Paulo Zanoniefbc20a2014-04-01 14:55:09 -0300399 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700400}
401
Keith Packard9b984da2011-09-19 13:54:47 -0700402static void
403intel_dp_check_edp(struct intel_dp *intel_dp)
404{
Paulo Zanoni30add222012-10-26 19:05:45 -0200405 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard9b984da2011-09-19 13:54:47 -0700406 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700407
Keith Packard9b984da2011-09-19 13:54:47 -0700408 if (!is_edp(intel_dp))
409 return;
Jesse Barnes453c5422013-03-28 09:55:41 -0700410
Daniel Vetter4be73782014-01-17 14:39:48 +0100411 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700412 WARN(1, "eDP powered off while attempting aux channel communication.\n");
413 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Jani Nikulabf13e812013-09-06 07:40:05 +0300414 I915_READ(_pp_stat_reg(intel_dp)),
415 I915_READ(_pp_ctrl_reg(intel_dp)));
Keith Packard9b984da2011-09-19 13:54:47 -0700416 }
417}
418
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100419static uint32_t
420intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
421{
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300425 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100426 uint32_t status;
427 bool done;
428
Daniel Vetteref04f002012-12-01 21:03:59 +0100429#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100430 if (has_aux_irq)
Paulo Zanonib18ac462013-02-18 19:00:24 -0300431 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
Imre Deak35987062013-05-21 20:03:20 +0300432 msecs_to_jiffies_timeout(10));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100433 else
434 done = wait_for_atomic(C, 10) == 0;
435 if (!done)
436 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
437 has_aux_irq);
438#undef C
439
440 return status;
441}
442
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000443static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
444{
445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
446 struct drm_device *dev = intel_dig_port->base.base.dev;
447
448 /*
449 * The clock divider is based off the hrawclk, and would like to run at
450 * 2MHz. So, take the hrawclk value and divide by 2 and use that
451 */
452 return index ? 0 : intel_hrawclk(dev) / 2;
453}
454
455static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
456{
457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
458 struct drm_device *dev = intel_dig_port->base.base.dev;
459
460 if (index)
461 return 0;
462
463 if (intel_dig_port->port == PORT_A) {
464 if (IS_GEN6(dev) || IS_GEN7(dev))
465 return 200; /* SNB & IVB eDP input clock at 400Mhz */
466 else
467 return 225; /* eDP input clock at 450Mhz */
468 } else {
469 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
470 }
471}
472
473static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300474{
475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
476 struct drm_device *dev = intel_dig_port->base.base.dev;
477 struct drm_i915_private *dev_priv = dev->dev_private;
478
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000479 if (intel_dig_port->port == PORT_A) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100480 if (index)
481 return 0;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000482 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300483 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
484 /* Workaround for non-ULT HSW */
Chris Wilsonbc866252013-07-21 16:00:03 +0100485 switch (index) {
486 case 0: return 63;
487 case 1: return 72;
488 default: return 0;
489 }
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000490 } else {
Chris Wilsonbc866252013-07-21 16:00:03 +0100491 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300492 }
493}
494
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000495static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
496{
497 return index ? 0 : 100;
498}
499
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000500static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
501 bool has_aux_irq,
502 int send_bytes,
503 uint32_t aux_clock_divider)
504{
505 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
506 struct drm_device *dev = intel_dig_port->base.base.dev;
507 uint32_t precharge, timeout;
508
509 if (IS_GEN6(dev))
510 precharge = 3;
511 else
512 precharge = 5;
513
514 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
515 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
516 else
517 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
518
519 return DP_AUX_CH_CTL_SEND_BUSY |
Damien Lespiau788d4432014-01-20 15:52:31 +0000520 DP_AUX_CH_CTL_DONE |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000521 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000522 DP_AUX_CH_CTL_TIME_OUT_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000523 timeout |
Damien Lespiau788d4432014-01-20 15:52:31 +0000524 DP_AUX_CH_CTL_RECEIVE_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000525 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
526 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000527 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000528}
529
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700530static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100531intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700532 uint8_t *send, int send_bytes,
533 uint8_t *recv, int recv_size)
534{
Paulo Zanoni174edf12012-10-26 19:05:50 -0200535 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
536 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700537 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300538 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700539 uint32_t ch_data = ch_ctl + 4;
Chris Wilsonbc866252013-07-21 16:00:03 +0100540 uint32_t aux_clock_divider;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100541 int i, ret, recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700542 uint32_t status;
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000543 int try, clock = 0;
Daniel Vetter4e6b7882014-02-07 16:33:20 +0100544 bool has_aux_irq = HAS_AUX_IRQ(dev);
Jani Nikula884f19e2014-03-14 16:51:14 +0200545 bool vdd;
546
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300547 mutex_lock(&dev_priv->pps_mutex);
548
Ville Syrjälä72c35002014-08-18 22:16:00 +0300549 /*
550 * We will be called with VDD already enabled for dpcd/edid/oui reads.
551 * In such cases we want to leave VDD enabled and it's up to upper layers
552 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
553 * ourselves.
554 */
Ville Syrjälä1e0560e2014-08-19 13:24:25 +0300555 vdd = edp_panel_vdd_on(intel_dp);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100556
557 /* dp aux is extremely sensitive to irq latency, hence request the
558 * lowest possible wakeup latency and so prevent the cpu from going into
559 * deep sleep states.
560 */
561 pm_qos_update_request(&dev_priv->pm_qos, 0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700562
Keith Packard9b984da2011-09-19 13:54:47 -0700563 intel_dp_check_edp(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800564
Paulo Zanonic67a4702013-08-19 13:18:09 -0300565 intel_aux_display_runtime_get(dev_priv);
566
Jesse Barnes11bee432011-08-01 15:02:20 -0700567 /* Try to wait for any previous AUX channel activity */
568 for (try = 0; try < 3; try++) {
Daniel Vetteref04f002012-12-01 21:03:59 +0100569 status = I915_READ_NOTRACE(ch_ctl);
Jesse Barnes11bee432011-08-01 15:02:20 -0700570 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
571 break;
572 msleep(1);
573 }
574
575 if (try == 3) {
576 WARN(1, "dp_aux_ch not started status 0x%08x\n",
577 I915_READ(ch_ctl));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100578 ret = -EBUSY;
579 goto out;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100580 }
581
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300582 /* Only 5 data registers! */
583 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
584 ret = -E2BIG;
585 goto out;
586 }
587
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000588 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Damien Lespiau153b1102014-01-21 13:37:15 +0000589 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
590 has_aux_irq,
591 send_bytes,
592 aux_clock_divider);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000593
Chris Wilsonbc866252013-07-21 16:00:03 +0100594 /* Must try at least 3 times according to DP spec */
595 for (try = 0; try < 5; try++) {
596 /* Load the send data into the aux channel data registers */
597 for (i = 0; i < send_bytes; i += 4)
598 I915_WRITE(ch_data + i,
599 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400600
Chris Wilsonbc866252013-07-21 16:00:03 +0100601 /* Send the command and wait for it to complete */
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000602 I915_WRITE(ch_ctl, send_ctl);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100603
Chris Wilsonbc866252013-07-21 16:00:03 +0100604 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
Akshay Joshi0206e352011-08-16 15:34:10 -0400605
Chris Wilsonbc866252013-07-21 16:00:03 +0100606 /* Clear done status and any errors */
607 I915_WRITE(ch_ctl,
608 status |
609 DP_AUX_CH_CTL_DONE |
610 DP_AUX_CH_CTL_TIME_OUT_ERROR |
611 DP_AUX_CH_CTL_RECEIVE_ERROR);
Adam Jacksond7e96fe2011-07-26 15:39:46 -0400612
Chris Wilsonbc866252013-07-21 16:00:03 +0100613 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
614 DP_AUX_CH_CTL_RECEIVE_ERROR))
615 continue;
616 if (status & DP_AUX_CH_CTL_DONE)
617 break;
618 }
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100619 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700620 break;
621 }
622
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700623 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700624 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100625 ret = -EBUSY;
626 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700627 }
628
629 /* Check for timeout or receive error.
630 * Timeouts occur when the sink is not connected
631 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700632 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700633 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100634 ret = -EIO;
635 goto out;
Keith Packarda5b3da52009-06-11 22:30:32 -0700636 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700637
638 /* Timeouts occur when the device isn't connected, so they're
639 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700640 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800641 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100642 ret = -ETIMEDOUT;
643 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700644 }
645
646 /* Unload any bytes sent back from the other side */
647 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
648 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700649 if (recv_bytes > recv_size)
650 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400651
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100652 for (i = 0; i < recv_bytes; i += 4)
653 unpack_aux(I915_READ(ch_data + i),
654 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700655
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100656 ret = recv_bytes;
657out:
658 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
Paulo Zanonic67a4702013-08-19 13:18:09 -0300659 intel_aux_display_runtime_put(dev_priv);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100660
Jani Nikula884f19e2014-03-14 16:51:14 +0200661 if (vdd)
662 edp_panel_vdd_off(intel_dp, false);
663
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300664 mutex_unlock(&dev_priv->pps_mutex);
665
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100666 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700667}
668
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300669#define BARE_ADDRESS_SIZE 3
670#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
Jani Nikula9d1a1032014-03-14 16:51:15 +0200671static ssize_t
672intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700673{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200674 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
675 uint8_t txbuf[20], rxbuf[20];
676 size_t txsize, rxsize;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700677 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700678
Jani Nikula9d1a1032014-03-14 16:51:15 +0200679 txbuf[0] = msg->request << 4;
680 txbuf[1] = msg->address >> 8;
681 txbuf[2] = msg->address & 0xff;
682 txbuf[3] = msg->size - 1;
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300683
Jani Nikula9d1a1032014-03-14 16:51:15 +0200684 switch (msg->request & ~DP_AUX_I2C_MOT) {
685 case DP_AUX_NATIVE_WRITE:
686 case DP_AUX_I2C_WRITE:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300687 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200688 rxsize = 1;
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200689
Jani Nikula9d1a1032014-03-14 16:51:15 +0200690 if (WARN_ON(txsize > 20))
691 return -E2BIG;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700692
Jani Nikula9d1a1032014-03-14 16:51:15 +0200693 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700694
Jani Nikula9d1a1032014-03-14 16:51:15 +0200695 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
696 if (ret > 0) {
697 msg->reply = rxbuf[0] >> 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700698
Jani Nikula9d1a1032014-03-14 16:51:15 +0200699 /* Return payload size. */
700 ret = msg->size;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700701 }
Jani Nikula9d1a1032014-03-14 16:51:15 +0200702 break;
703
704 case DP_AUX_NATIVE_READ:
705 case DP_AUX_I2C_READ:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300706 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200707 rxsize = msg->size + 1;
708
709 if (WARN_ON(rxsize > 20))
710 return -E2BIG;
711
712 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
713 if (ret > 0) {
714 msg->reply = rxbuf[0] >> 4;
715 /*
716 * Assume happy day, and copy the data. The caller is
717 * expected to check msg->reply before touching it.
718 *
719 * Return payload size.
720 */
721 ret--;
722 memcpy(msg->buffer, rxbuf + 1, ret);
723 }
724 break;
725
726 default:
727 ret = -EINVAL;
728 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700729 }
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200730
Jani Nikula9d1a1032014-03-14 16:51:15 +0200731 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700732}
733
Jani Nikula9d1a1032014-03-14 16:51:15 +0200734static void
735intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700736{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jani Nikula33ad6622014-03-14 16:51:16 +0200738 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
739 enum port port = intel_dig_port->port;
Jani Nikula0b998362014-03-14 16:51:17 +0200740 const char *name = NULL;
Dave Airlieab2c0672009-12-04 10:55:24 +1000741 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700742
Jani Nikula33ad6622014-03-14 16:51:16 +0200743 switch (port) {
744 case PORT_A:
745 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200746 name = "DPDDC-A";
Dave Airlieab2c0672009-12-04 10:55:24 +1000747 break;
Jani Nikula33ad6622014-03-14 16:51:16 +0200748 case PORT_B:
749 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200750 name = "DPDDC-B";
Jani Nikula33ad6622014-03-14 16:51:16 +0200751 break;
752 case PORT_C:
753 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200754 name = "DPDDC-C";
Jani Nikula33ad6622014-03-14 16:51:16 +0200755 break;
756 case PORT_D:
757 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200758 name = "DPDDC-D";
Dave Airlieab2c0672009-12-04 10:55:24 +1000759 break;
760 default:
Jani Nikula33ad6622014-03-14 16:51:16 +0200761 BUG();
Dave Airlieab2c0672009-12-04 10:55:24 +1000762 }
763
Jani Nikula33ad6622014-03-14 16:51:16 +0200764 if (!HAS_DDI(dev))
765 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
David Flynn8316f332010-12-08 16:10:21 +0000766
Jani Nikula0b998362014-03-14 16:51:17 +0200767 intel_dp->aux.name = name;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200768 intel_dp->aux.dev = dev->dev;
769 intel_dp->aux.transfer = intel_dp_aux_transfer;
David Flynn8316f332010-12-08 16:10:21 +0000770
Jani Nikula0b998362014-03-14 16:51:17 +0200771 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
772 connector->base.kdev->kobj.name);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700773
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000774 ret = drm_dp_aux_register(&intel_dp->aux);
Jani Nikula0b998362014-03-14 16:51:17 +0200775 if (ret < 0) {
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000776 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
Jani Nikula0b998362014-03-14 16:51:17 +0200777 name, ret);
778 return;
Dave Airlieab2c0672009-12-04 10:55:24 +1000779 }
David Flynn8316f332010-12-08 16:10:21 +0000780
Jani Nikula0b998362014-03-14 16:51:17 +0200781 ret = sysfs_create_link(&connector->base.kdev->kobj,
782 &intel_dp->aux.ddc.dev.kobj,
783 intel_dp->aux.ddc.dev.kobj.name);
784 if (ret < 0) {
785 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000786 drm_dp_aux_unregister(&intel_dp->aux);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700787 }
788}
789
Imre Deak80f65de2014-02-11 17:12:49 +0200790static void
791intel_dp_connector_unregister(struct intel_connector *intel_connector)
792{
793 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
794
Dave Airlie0e32b392014-05-02 14:02:48 +1000795 if (!intel_connector->mst_port)
796 sysfs_remove_link(&intel_connector->base.kdev->kobj,
797 intel_dp->aux.ddc.dev.kobj.name);
Imre Deak80f65de2014-02-11 17:12:49 +0200798 intel_connector_unregister(intel_connector);
799}
800
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200801static void
Daniel Vetter0e503382014-07-04 11:26:04 -0300802hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
803{
804 switch (link_bw) {
805 case DP_LINK_BW_1_62:
806 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
807 break;
808 case DP_LINK_BW_2_7:
809 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
810 break;
811 case DP_LINK_BW_5_4:
812 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
813 break;
814 }
815}
816
817static void
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200818intel_dp_set_clock(struct intel_encoder *encoder,
819 struct intel_crtc_config *pipe_config, int link_bw)
820{
821 struct drm_device *dev = encoder->base.dev;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800822 const struct dp_link_dpll *divisor = NULL;
823 int i, count = 0;
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200824
825 if (IS_G4X(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800826 divisor = gen4_dpll;
827 count = ARRAY_SIZE(gen4_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200828 } else if (HAS_PCH_SPLIT(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800829 divisor = pch_dpll;
830 count = ARRAY_SIZE(pch_dpll);
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300831 } else if (IS_CHERRYVIEW(dev)) {
832 divisor = chv_dpll;
833 count = ARRAY_SIZE(chv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200834 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +0800835 divisor = vlv_dpll;
836 count = ARRAY_SIZE(vlv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200837 }
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800838
839 if (divisor && count) {
840 for (i = 0; i < count; i++) {
841 if (link_bw == divisor[i].link_bw) {
842 pipe_config->dpll = divisor[i].dpll;
843 pipe_config->clock_set = true;
844 break;
845 }
846 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200847 }
848}
849
Paulo Zanoni00c09d72012-10-26 19:05:52 -0200850bool
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100851intel_dp_compute_config(struct intel_encoder *encoder,
852 struct intel_crtc_config *pipe_config)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700853{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100854 struct drm_device *dev = encoder->base.dev;
Daniel Vetter36008362013-03-27 00:44:59 +0100855 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100856 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100857 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300858 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700859 struct intel_crtc *intel_crtc = encoder->new_crtc;
Jani Nikuladd06f902012-10-19 14:51:50 +0300860 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700861 int lane_count, clock;
Jani Nikula56071a22014-05-06 14:56:52 +0300862 int min_lane_count = 1;
Paulo Zanonieeb63242014-05-06 14:56:50 +0300863 int max_lane_count = intel_dp_max_lane_count(intel_dp);
Todd Previte06ea66b2014-01-20 10:19:39 -0700864 /* Conveniently, the link BW constants become indices with a shift...*/
Jani Nikula56071a22014-05-06 14:56:52 +0300865 int min_clock = 0;
Todd Previte06ea66b2014-01-20 10:19:39 -0700866 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
Daniel Vetter083f9562012-04-20 20:23:49 +0200867 int bpp, mode_rate;
Todd Previte06ea66b2014-01-20 10:19:39 -0700868 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
Daniel Vetterff9a6752013-06-01 17:16:21 +0200869 int link_avail, link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700870
Imre Deakbc7d38a2013-05-16 14:40:36 +0300871 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100872 pipe_config->has_pch_encoder = true;
873
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200874 pipe_config->has_dp_encoder = true;
Vandana Kannanf769cd22014-08-05 07:51:22 -0700875 pipe_config->has_drrs = false;
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200876 pipe_config->has_audio = intel_dp->has_audio;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700877
Jani Nikuladd06f902012-10-19 14:51:50 +0300878 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
879 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
880 adjusted_mode);
Jesse Barnes2dd24552013-04-25 12:55:01 -0700881 if (!HAS_PCH_SPLIT(dev))
882 intel_gmch_panel_fitting(intel_crtc, pipe_config,
883 intel_connector->panel.fitting_mode);
884 else
Jesse Barnesb074cec2013-04-25 12:55:02 -0700885 intel_pch_panel_fitting(intel_crtc, pipe_config,
886 intel_connector->panel.fitting_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100887 }
888
Daniel Vettercb1793c2012-06-04 18:39:21 +0200889 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
Daniel Vetter0af78a22012-05-23 11:30:55 +0200890 return false;
891
Daniel Vetter083f9562012-04-20 20:23:49 +0200892 DRM_DEBUG_KMS("DP link computation with max lane count %i "
893 "max bw %02x pixel clock %iKHz\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +0100894 max_lane_count, bws[max_clock],
895 adjusted_mode->crtc_clock);
Daniel Vetter083f9562012-04-20 20:23:49 +0200896
Daniel Vetter36008362013-03-27 00:44:59 +0100897 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
898 * bpc in between. */
Daniel Vetter3e7ca982013-06-01 19:45:56 +0200899 bpp = pipe_config->pipe_bpp;
Jani Nikula56071a22014-05-06 14:56:52 +0300900 if (is_edp(intel_dp)) {
901 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
902 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
903 dev_priv->vbt.edp_bpp);
904 bpp = dev_priv->vbt.edp_bpp;
905 }
906
Jani Nikulaf4cdbc22014-05-14 13:02:19 +0300907 if (IS_BROADWELL(dev)) {
908 /* Yes, it's an ugly hack. */
909 min_lane_count = max_lane_count;
910 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
911 min_lane_count);
912 } else if (dev_priv->vbt.edp_lanes) {
Jani Nikula56071a22014-05-06 14:56:52 +0300913 min_lane_count = min(dev_priv->vbt.edp_lanes,
914 max_lane_count);
915 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
916 min_lane_count);
917 }
918
919 if (dev_priv->vbt.edp_rate) {
920 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
921 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
922 bws[min_clock]);
923 }
Imre Deak79842112013-07-18 17:44:13 +0300924 }
Daniel Vetter657445f2013-05-04 10:09:18 +0200925
Daniel Vetter36008362013-03-27 00:44:59 +0100926 for (; bpp >= 6*3; bpp -= 2*3) {
Damien Lespiau241bfc32013-09-25 16:45:37 +0100927 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
928 bpp);
Daniel Vetterc4867932012-04-10 10:42:36 +0200929
Dave Airliec6930992014-07-14 11:04:39 +1000930 for (clock = min_clock; clock <= max_clock; clock++) {
931 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
Daniel Vetter36008362013-03-27 00:44:59 +0100932 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
933 link_avail = intel_dp_max_data_rate(link_clock,
934 lane_count);
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200935
Daniel Vetter36008362013-03-27 00:44:59 +0100936 if (mode_rate <= link_avail) {
937 goto found;
938 }
939 }
940 }
941 }
942
943 return false;
944
945found:
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200946 if (intel_dp->color_range_auto) {
947 /*
948 * See:
949 * CEA-861-E - 5.1 Default Encoding Parameters
950 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
951 */
Thierry Reding18316c82012-12-20 15:41:44 +0100952 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200953 intel_dp->color_range = DP_COLOR_RANGE_16_235;
954 else
955 intel_dp->color_range = 0;
956 }
957
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200958 if (intel_dp->color_range)
Daniel Vetter50f3b012013-03-27 00:44:56 +0100959 pipe_config->limited_color_range = true;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200960
Daniel Vetter36008362013-03-27 00:44:59 +0100961 intel_dp->link_bw = bws[clock];
962 intel_dp->lane_count = lane_count;
Daniel Vetter657445f2013-05-04 10:09:18 +0200963 pipe_config->pipe_bpp = bpp;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200964 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
Daniel Vetterc4867932012-04-10 10:42:36 +0200965
Daniel Vetter36008362013-03-27 00:44:59 +0100966 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
967 intel_dp->link_bw, intel_dp->lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +0200968 pipe_config->port_clock, bpp);
Daniel Vetter36008362013-03-27 00:44:59 +0100969 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
970 mode_rate, link_avail);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700971
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200972 intel_link_compute_m_n(bpp, lane_count,
Damien Lespiau241bfc32013-09-25 16:45:37 +0100973 adjusted_mode->crtc_clock,
974 pipe_config->port_clock,
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200975 &pipe_config->dp_m_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700976
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530977 if (intel_connector->panel.downclock_mode != NULL &&
978 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
Vandana Kannanf769cd22014-08-05 07:51:22 -0700979 pipe_config->has_drrs = true;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530980 intel_link_compute_m_n(bpp, lane_count,
981 intel_connector->panel.downclock_mode->clock,
982 pipe_config->port_clock,
983 &pipe_config->dp_m2_n2);
984 }
985
Damien Lespiauea155f32014-07-29 18:06:20 +0100986 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Daniel Vetter0e503382014-07-04 11:26:04 -0300987 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
988 else
989 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200990
Daniel Vetter36008362013-03-27 00:44:59 +0100991 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700992}
993
Daniel Vetter7c62a162013-06-01 17:16:20 +0200994static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
Daniel Vetterea9b6002012-11-29 15:59:31 +0100995{
Daniel Vetter7c62a162013-06-01 17:16:20 +0200996 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
997 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
998 struct drm_device *dev = crtc->base.dev;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 u32 dpa_ctl;
1001
Daniel Vetterff9a6752013-06-01 17:16:21 +02001002 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
Daniel Vetterea9b6002012-11-29 15:59:31 +01001003 dpa_ctl = I915_READ(DP_A);
1004 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1005
Daniel Vetterff9a6752013-06-01 17:16:21 +02001006 if (crtc->config.port_clock == 162000) {
Daniel Vetter1ce17032012-11-29 15:59:32 +01001007 /* For a long time we've carried around a ILK-DevA w/a for the
1008 * 160MHz clock. If we're really unlucky, it's still required.
1009 */
1010 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
Daniel Vetterea9b6002012-11-29 15:59:31 +01001011 dpa_ctl |= DP_PLL_FREQ_160MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +02001012 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +01001013 } else {
1014 dpa_ctl |= DP_PLL_FREQ_270MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +02001015 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +01001016 }
Daniel Vetter1ce17032012-11-29 15:59:32 +01001017
Daniel Vetterea9b6002012-11-29 15:59:31 +01001018 I915_WRITE(DP_A, dpa_ctl);
1019
1020 POSTING_READ(DP_A);
1021 udelay(500);
1022}
1023
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02001024static void intel_dp_prepare(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001025{
Daniel Vetterb934223d2013-07-21 21:37:05 +02001026 struct drm_device *dev = encoder->base.dev;
Keith Packard417e8222011-11-01 19:54:11 -07001027 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb934223d2013-07-21 21:37:05 +02001028 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001029 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetterb934223d2013-07-21 21:37:05 +02001030 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1031 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001032
Keith Packard417e8222011-11-01 19:54:11 -07001033 /*
Keith Packard1a2eb462011-11-16 16:26:07 -08001034 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -07001035 *
1036 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -08001037 * SNB CPU
1038 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -07001039 * CPT PCH
1040 *
1041 * IBX PCH and CPU are the same for almost everything,
1042 * except that the CPU DP PLL is configured in this
1043 * register
1044 *
1045 * CPT PCH is quite different, having many bits moved
1046 * to the TRANS_DP_CTL register instead. That
1047 * configuration happens (oddly) in ironlake_pch_enable
1048 */
Adam Jackson9c9e7922010-04-05 17:57:59 -04001049
Keith Packard417e8222011-11-01 19:54:11 -07001050 /* Preserve the BIOS-computed detected bit. This is
1051 * supposed to be read-only.
1052 */
1053 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001054
Keith Packard417e8222011-11-01 19:54:11 -07001055 /* Handle DP bits in common between all three register formats */
Keith Packard417e8222011-11-01 19:54:11 -07001056 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Daniel Vetter17aa6be2013-04-30 14:01:40 +02001057 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001058
Daniel Vetter9ed109a2014-04-24 23:54:52 +02001059 if (crtc->config.has_audio) {
Wu Fengguange0dac652011-09-05 14:25:34 +08001060 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
Daniel Vetter7c62a162013-06-01 17:16:20 +02001061 pipe_name(crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +01001062 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Daniel Vetterb934223d2013-07-21 21:37:05 +02001063 intel_write_eld(&encoder->base, adjusted_mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08001064 }
Paulo Zanoni247d89f2012-10-15 15:51:33 -03001065
Keith Packard417e8222011-11-01 19:54:11 -07001066 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001067
Imre Deakbc7d38a2013-05-16 14:40:36 +03001068 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Keith Packard1a2eb462011-11-16 16:26:07 -08001069 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1070 intel_dp->DP |= DP_SYNC_HS_HIGH;
1071 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1072 intel_dp->DP |= DP_SYNC_VS_HIGH;
1073 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1074
Jani Nikula6aba5b62013-10-04 15:08:10 +03001075 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard1a2eb462011-11-16 16:26:07 -08001076 intel_dp->DP |= DP_ENHANCED_FRAMING;
1077
Daniel Vetter7c62a162013-06-01 17:16:20 +02001078 intel_dp->DP |= crtc->pipe << 29;
Imre Deakbc7d38a2013-05-16 14:40:36 +03001079 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Jesse Barnesb2634012013-03-28 09:55:40 -07001080 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02001081 intel_dp->DP |= intel_dp->color_range;
Keith Packard417e8222011-11-01 19:54:11 -07001082
1083 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1084 intel_dp->DP |= DP_SYNC_HS_HIGH;
1085 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1086 intel_dp->DP |= DP_SYNC_VS_HIGH;
1087 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1088
Jani Nikula6aba5b62013-10-04 15:08:10 +03001089 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard417e8222011-11-01 19:54:11 -07001090 intel_dp->DP |= DP_ENHANCED_FRAMING;
1091
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001092 if (!IS_CHERRYVIEW(dev)) {
1093 if (crtc->pipe == 1)
1094 intel_dp->DP |= DP_PIPEB_SELECT;
1095 } else {
1096 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1097 }
Keith Packard417e8222011-11-01 19:54:11 -07001098 } else {
1099 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001100 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001101}
1102
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001103#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1104#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001105
Paulo Zanoni1a5ef5b2013-12-19 14:29:43 -02001106#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1107#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
Keith Packard99ea7122011-11-01 19:57:50 -07001108
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001109#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1110#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001111
Daniel Vetter4be73782014-01-17 14:39:48 +01001112static void wait_panel_status(struct intel_dp *intel_dp,
Keith Packard99ea7122011-11-01 19:57:50 -07001113 u32 mask,
1114 u32 value)
1115{
Paulo Zanoni30add222012-10-26 19:05:45 -02001116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001117 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07001118 u32 pp_stat_reg, pp_ctrl_reg;
1119
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001120 lockdep_assert_held(&dev_priv->pps_mutex);
1121
Jani Nikulabf13e812013-09-06 07:40:05 +03001122 pp_stat_reg = _pp_stat_reg(intel_dp);
1123 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001124
1125 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001126 mask, value,
1127 I915_READ(pp_stat_reg),
1128 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001129
Jesse Barnes453c5422013-03-28 09:55:41 -07001130 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001131 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001132 I915_READ(pp_stat_reg),
1133 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001134 }
Chris Wilson54c136d2013-12-02 09:57:16 +00001135
1136 DRM_DEBUG_KMS("Wait complete\n");
Keith Packard99ea7122011-11-01 19:57:50 -07001137}
1138
Daniel Vetter4be73782014-01-17 14:39:48 +01001139static void wait_panel_on(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001140{
1141 DRM_DEBUG_KMS("Wait for panel power on\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001142 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001143}
1144
Daniel Vetter4be73782014-01-17 14:39:48 +01001145static void wait_panel_off(struct intel_dp *intel_dp)
Keith Packardbd943152011-09-18 23:09:52 -07001146{
Keith Packardbd943152011-09-18 23:09:52 -07001147 DRM_DEBUG_KMS("Wait for panel power off time\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001148 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -07001149}
Keith Packardbd943152011-09-18 23:09:52 -07001150
Daniel Vetter4be73782014-01-17 14:39:48 +01001151static void wait_panel_power_cycle(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001152{
1153 DRM_DEBUG_KMS("Wait for panel power cycle\n");
Paulo Zanonidce56b32013-12-19 14:29:40 -02001154
1155 /* When we disable the VDD override bit last we have to do the manual
1156 * wait. */
1157 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1158 intel_dp->panel_power_cycle_delay);
1159
Daniel Vetter4be73782014-01-17 14:39:48 +01001160 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001161}
Keith Packardbd943152011-09-18 23:09:52 -07001162
Daniel Vetter4be73782014-01-17 14:39:48 +01001163static void wait_backlight_on(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001164{
1165 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1166 intel_dp->backlight_on_delay);
1167}
1168
Daniel Vetter4be73782014-01-17 14:39:48 +01001169static void edp_wait_backlight_off(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001170{
1171 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1172 intel_dp->backlight_off_delay);
1173}
Keith Packard99ea7122011-11-01 19:57:50 -07001174
Keith Packard832dd3c2011-11-01 19:34:06 -07001175/* Read the current pp_control value, unlocking the register if it
1176 * is locked
1177 */
1178
Jesse Barnes453c5422013-03-28 09:55:41 -07001179static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
Keith Packard832dd3c2011-11-01 19:34:06 -07001180{
Jesse Barnes453c5422013-03-28 09:55:41 -07001181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 control;
Jesse Barnes453c5422013-03-28 09:55:41 -07001184
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001185 lockdep_assert_held(&dev_priv->pps_mutex);
1186
Jani Nikulabf13e812013-09-06 07:40:05 +03001187 control = I915_READ(_pp_ctrl_reg(intel_dp));
Keith Packard832dd3c2011-11-01 19:34:06 -07001188 control &= ~PANEL_UNLOCK_MASK;
1189 control |= PANEL_UNLOCK_REGS;
1190 return control;
Keith Packardbd943152011-09-18 23:09:52 -07001191}
1192
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03001193static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001194{
Paulo Zanoni30add222012-10-26 19:05:45 -02001195 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1197 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jesse Barnes5d613502011-01-24 17:10:54 -08001198 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001199 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001200 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001201 u32 pp_stat_reg, pp_ctrl_reg;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001202 bool need_to_disable = !intel_dp->want_panel_vdd;
Jesse Barnes5d613502011-01-24 17:10:54 -08001203
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001204 lockdep_assert_held(&dev_priv->pps_mutex);
1205
Keith Packard97af61f572011-09-28 16:23:51 -07001206 if (!is_edp(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001207 return false;
Keith Packardbd943152011-09-18 23:09:52 -07001208
1209 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -07001210
Daniel Vetter4be73782014-01-17 14:39:48 +01001211 if (edp_have_panel_vdd(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001212 return need_to_disable;
Paulo Zanonib0665d52013-10-30 19:50:27 -02001213
Imre Deak4e6e1a52014-03-27 17:45:11 +02001214 power_domain = intel_display_port_power_domain(intel_encoder);
1215 intel_display_power_get(dev_priv, power_domain);
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001216
Paulo Zanonib0665d52013-10-30 19:50:27 -02001217 DRM_DEBUG_KMS("Turning eDP VDD on\n");
Keith Packardbd943152011-09-18 23:09:52 -07001218
Daniel Vetter4be73782014-01-17 14:39:48 +01001219 if (!edp_have_panel_power(intel_dp))
1220 wait_panel_power_cycle(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001221
Jesse Barnes453c5422013-03-28 09:55:41 -07001222 pp = ironlake_get_pp_control(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001223 pp |= EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -07001224
Jani Nikulabf13e812013-09-06 07:40:05 +03001225 pp_stat_reg = _pp_stat_reg(intel_dp);
1226 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001227
1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packardebf33b12011-09-29 15:53:27 -07001232 /*
1233 * If the panel wasn't on, delay before accessing aux channel
1234 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001235 if (!edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -07001236 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -07001237 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001238 }
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001239
1240 return need_to_disable;
1241}
1242
Daniel Vetterb80d6c72014-03-19 15:54:37 +01001243void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001244{
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001245 struct drm_i915_private *dev_priv =
1246 intel_dp_to_dev(intel_dp)->dev_private;
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001247 bool vdd;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001248
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001249 if (!is_edp(intel_dp))
1250 return;
1251
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001252 mutex_lock(&dev_priv->pps_mutex);
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001253 vdd = edp_panel_vdd_on(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001254 mutex_unlock(&dev_priv->pps_mutex);
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001255
1256 WARN(!vdd, "eDP VDD already requested on\n");
Jesse Barnes5d613502011-01-24 17:10:54 -08001257}
1258
Daniel Vetter4be73782014-01-17 14:39:48 +01001259static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001260{
Paulo Zanoni30add222012-10-26 19:05:45 -02001261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001262 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001263 struct intel_digital_port *intel_dig_port =
1264 dp_to_dig_port(intel_dp);
1265 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1266 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001267 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001268 u32 pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001269
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001270 lockdep_assert_held(&dev_priv->pps_mutex);
Daniel Vettera0e99e62012-12-02 01:05:46 +01001271
Ville Syrjälä15e899a2014-08-18 22:16:02 +03001272 WARN_ON(intel_dp->want_panel_vdd);
1273
1274 if (!edp_have_panel_vdd(intel_dp))
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001275 return;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001276
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001277 DRM_DEBUG_KMS("Turning eDP VDD off\n");
Paulo Zanonib0665d52013-10-30 19:50:27 -02001278
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001279 pp = ironlake_get_pp_control(intel_dp);
1280 pp &= ~EDP_FORCE_VDD;
Jesse Barnes453c5422013-03-28 09:55:41 -07001281
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001282 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1283 pp_stat_reg = _pp_stat_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001284
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001285 I915_WRITE(pp_ctrl_reg, pp);
1286 POSTING_READ(pp_ctrl_reg);
Jesse Barnes5d613502011-01-24 17:10:54 -08001287
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001288 /* Make sure sequencer is idle before allowing subsequent activity */
1289 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1290 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Paulo Zanoni90791a52013-12-06 17:32:42 -02001291
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001292 if ((pp & POWER_TARGET_ON) == 0)
1293 intel_dp->last_power_cycle = jiffies;
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001294
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001295 power_domain = intel_display_port_power_domain(intel_encoder);
1296 intel_display_power_put(dev_priv, power_domain);
Keith Packardbd943152011-09-18 23:09:52 -07001297}
1298
Daniel Vetter4be73782014-01-17 14:39:48 +01001299static void edp_panel_vdd_work(struct work_struct *__work)
Keith Packardbd943152011-09-18 23:09:52 -07001300{
1301 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1302 struct intel_dp, panel_vdd_work);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001303 struct drm_i915_private *dev_priv =
1304 intel_dp_to_dev(intel_dp)->dev_private;
Keith Packardbd943152011-09-18 23:09:52 -07001305
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001306 mutex_lock(&dev_priv->pps_mutex);
Ville Syrjälä15e899a2014-08-18 22:16:02 +03001307 if (!intel_dp->want_panel_vdd)
1308 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001309 mutex_unlock(&dev_priv->pps_mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001310}
1311
Imre Deakaba86892014-07-30 15:57:31 +03001312static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1313{
1314 unsigned long delay;
1315
1316 /*
1317 * Queue the timer to fire a long time from now (relative to the power
1318 * down delay) to keep the panel power up across a sequence of
1319 * operations.
1320 */
1321 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1322 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1323}
1324
Daniel Vetter4be73782014-01-17 14:39:48 +01001325static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
Keith Packardbd943152011-09-18 23:09:52 -07001326{
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001327 struct drm_i915_private *dev_priv =
1328 intel_dp_to_dev(intel_dp)->dev_private;
1329
1330 lockdep_assert_held(&dev_priv->pps_mutex);
1331
Keith Packard97af61f572011-09-28 16:23:51 -07001332 if (!is_edp(intel_dp))
1333 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001334
Keith Packardbd943152011-09-18 23:09:52 -07001335 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
Keith Packardf2e8b182011-11-01 20:01:35 -07001336
Keith Packardbd943152011-09-18 23:09:52 -07001337 intel_dp->want_panel_vdd = false;
1338
Imre Deakaba86892014-07-30 15:57:31 +03001339 if (sync)
Daniel Vetter4be73782014-01-17 14:39:48 +01001340 edp_panel_vdd_off_sync(intel_dp);
Imre Deakaba86892014-07-30 15:57:31 +03001341 else
1342 edp_panel_vdd_schedule_off(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001343}
1344
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03001345static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1346{
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001347 struct drm_i915_private *dev_priv =
1348 intel_dp_to_dev(intel_dp)->dev_private;
1349
1350 if (!is_edp(intel_dp))
1351 return;
1352
1353 mutex_lock(&dev_priv->pps_mutex);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03001354 edp_panel_vdd_off(intel_dp, sync);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001355 mutex_unlock(&dev_priv->pps_mutex);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03001356}
1357
Daniel Vetter4be73782014-01-17 14:39:48 +01001358void intel_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001359{
Paulo Zanoni30add222012-10-26 19:05:45 -02001360 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001361 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001362 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001363 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001364
Keith Packard97af61f572011-09-28 16:23:51 -07001365 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001366 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001367
1368 DRM_DEBUG_KMS("Turn eDP power on\n");
1369
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001370 mutex_lock(&dev_priv->pps_mutex);
1371
Daniel Vetter4be73782014-01-17 14:39:48 +01001372 if (edp_have_panel_power(intel_dp)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001373 DRM_DEBUG_KMS("eDP power already on\n");
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001374 goto out;
Keith Packard99ea7122011-11-01 19:57:50 -07001375 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001376
Daniel Vetter4be73782014-01-17 14:39:48 +01001377 wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001378
Jani Nikulabf13e812013-09-06 07:40:05 +03001379 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001380 pp = ironlake_get_pp_control(intel_dp);
Keith Packard05ce1a42011-09-29 16:33:01 -07001381 if (IS_GEN5(dev)) {
1382 /* ILK workaround: disable reset around power sequence */
1383 pp &= ~PANEL_POWER_RESET;
Jani Nikulabf13e812013-09-06 07:40:05 +03001384 I915_WRITE(pp_ctrl_reg, pp);
1385 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001386 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001387
Keith Packard1c0ae802011-09-19 13:59:29 -07001388 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07001389 if (!IS_GEN5(dev))
1390 pp |= PANEL_POWER_RESET;
1391
Jesse Barnes453c5422013-03-28 09:55:41 -07001392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001394
Daniel Vetter4be73782014-01-17 14:39:48 +01001395 wait_panel_on(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001396 intel_dp->last_power_on = jiffies;
Jesse Barnes9934c132010-07-22 13:18:19 -07001397
Keith Packard05ce1a42011-09-29 16:33:01 -07001398 if (IS_GEN5(dev)) {
1399 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
Jani Nikulabf13e812013-09-06 07:40:05 +03001400 I915_WRITE(pp_ctrl_reg, pp);
1401 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001402 }
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001403
1404 out:
1405 mutex_unlock(&dev_priv->pps_mutex);
Jesse Barnes9934c132010-07-22 13:18:19 -07001406}
1407
Daniel Vetter4be73782014-01-17 14:39:48 +01001408void intel_edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001409{
Imre Deak4e6e1a52014-03-27 17:45:11 +02001410 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1411 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanoni30add222012-10-26 19:05:45 -02001412 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001413 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001414 enum intel_display_power_domain power_domain;
Keith Packard99ea7122011-11-01 19:57:50 -07001415 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001416 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001417
Keith Packard97af61f572011-09-28 16:23:51 -07001418 if (!is_edp(intel_dp))
1419 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001420
Keith Packard99ea7122011-11-01 19:57:50 -07001421 DRM_DEBUG_KMS("Turn eDP power off\n");
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001422
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001423 mutex_lock(&dev_priv->pps_mutex);
1424
Jani Nikula24f3e092014-03-17 16:43:36 +02001425 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1426
Jesse Barnes453c5422013-03-28 09:55:41 -07001427 pp = ironlake_get_pp_control(intel_dp);
Daniel Vetter35a38552012-08-12 22:17:14 +02001428 /* We need to switch off panel power _and_ force vdd, for otherwise some
1429 * panels get very unhappy and cease to work. */
Patrik Jakobssonb3064152014-03-04 00:42:44 +01001430 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1431 EDP_BLC_ENABLE);
Jesse Barnes453c5422013-03-28 09:55:41 -07001432
Jani Nikulabf13e812013-09-06 07:40:05 +03001433 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001434
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001435 intel_dp->want_panel_vdd = false;
1436
Jesse Barnes453c5422013-03-28 09:55:41 -07001437 I915_WRITE(pp_ctrl_reg, pp);
1438 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001439
Paulo Zanonidce56b32013-12-19 14:29:40 -02001440 intel_dp->last_power_cycle = jiffies;
Daniel Vetter4be73782014-01-17 14:39:48 +01001441 wait_panel_off(intel_dp);
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001442
1443 /* We got a reference when we enabled the VDD. */
Imre Deak4e6e1a52014-03-27 17:45:11 +02001444 power_domain = intel_display_port_power_domain(intel_encoder);
1445 intel_display_power_put(dev_priv, power_domain);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001446
1447 mutex_unlock(&dev_priv->pps_mutex);
Jesse Barnes9934c132010-07-22 13:18:19 -07001448}
1449
Jani Nikula1250d102014-08-12 17:11:39 +03001450/* Enable backlight in the panel power control. */
1451static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001452{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1454 struct drm_device *dev = intel_dig_port->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001455 struct drm_i915_private *dev_priv = dev->dev_private;
1456 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001457 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001458
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001459 /*
1460 * If we enable the backlight right away following a panel power
1461 * on, we may see slight flicker as the panel syncs with the eDP
1462 * link. So delay a bit to make sure the image is solid before
1463 * allowing it to appear.
1464 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001465 wait_backlight_on(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001466
1467 mutex_lock(&dev_priv->pps_mutex);
1468
Jesse Barnes453c5422013-03-28 09:55:41 -07001469 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001470 pp |= EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001471
Jani Nikulabf13e812013-09-06 07:40:05 +03001472 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001473
1474 I915_WRITE(pp_ctrl_reg, pp);
1475 POSTING_READ(pp_ctrl_reg);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001476
1477 mutex_unlock(&dev_priv->pps_mutex);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001478}
1479
Jani Nikula1250d102014-08-12 17:11:39 +03001480/* Enable backlight PWM and backlight PP control. */
1481void intel_edp_backlight_on(struct intel_dp *intel_dp)
1482{
1483 if (!is_edp(intel_dp))
1484 return;
1485
1486 DRM_DEBUG_KMS("\n");
1487
1488 intel_panel_enable_backlight(intel_dp->attached_connector);
1489 _intel_edp_backlight_on(intel_dp);
1490}
1491
1492/* Disable backlight in the panel power control. */
1493static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001494{
Paulo Zanoni30add222012-10-26 19:05:45 -02001495 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001498 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001499
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001500 if (!is_edp(intel_dp))
1501 return;
1502
1503 mutex_lock(&dev_priv->pps_mutex);
1504
Jesse Barnes453c5422013-03-28 09:55:41 -07001505 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001506 pp &= ~EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001507
Jani Nikulabf13e812013-09-06 07:40:05 +03001508 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001509
1510 I915_WRITE(pp_ctrl_reg, pp);
1511 POSTING_READ(pp_ctrl_reg);
Jesse Barnesf7d23232014-03-31 11:13:56 -07001512
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001513 mutex_unlock(&dev_priv->pps_mutex);
1514
1515 intel_dp->last_backlight_off = jiffies;
Jesse Barnesf7d23232014-03-31 11:13:56 -07001516 edp_wait_backlight_off(intel_dp);
Jani Nikula1250d102014-08-12 17:11:39 +03001517}
Jesse Barnesf7d23232014-03-31 11:13:56 -07001518
Jani Nikula1250d102014-08-12 17:11:39 +03001519/* Disable backlight PP control and backlight PWM. */
1520void intel_edp_backlight_off(struct intel_dp *intel_dp)
1521{
1522 if (!is_edp(intel_dp))
1523 return;
1524
1525 DRM_DEBUG_KMS("\n");
1526
1527 _intel_edp_backlight_off(intel_dp);
Jesse Barnesf7d23232014-03-31 11:13:56 -07001528 intel_panel_disable_backlight(intel_dp->attached_connector);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001529}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001530
Jani Nikula73580fb72014-08-12 17:11:41 +03001531/*
1532 * Hook for controlling the panel power control backlight through the bl_power
1533 * sysfs attribute. Take care to handle multiple calls.
1534 */
1535static void intel_edp_backlight_power(struct intel_connector *connector,
1536 bool enable)
1537{
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001538 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
Jani Nikula73580fb72014-08-12 17:11:41 +03001539 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001540 bool is_enabled;
1541
1542 mutex_lock(&dev_priv->pps_mutex);
1543 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1544 mutex_unlock(&dev_priv->pps_mutex);
Jani Nikula73580fb72014-08-12 17:11:41 +03001545
1546 if (is_enabled == enable)
1547 return;
1548
Jani Nikula23ba9372014-08-27 14:08:43 +03001549 DRM_DEBUG_KMS("panel power control backlight %s\n",
1550 enable ? "enable" : "disable");
Jani Nikula73580fb72014-08-12 17:11:41 +03001551
1552 if (enable)
1553 _intel_edp_backlight_on(intel_dp);
1554 else
1555 _intel_edp_backlight_off(intel_dp);
1556}
1557
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001558static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001559{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1561 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1562 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 u32 dpa_ctl;
1565
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001566 assert_pipe_disabled(dev_priv,
1567 to_intel_crtc(crtc)->pipe);
1568
Jesse Barnesd240f202010-08-13 15:43:26 -07001569 DRM_DEBUG_KMS("\n");
1570 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001571 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1572 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1573
1574 /* We don't adjust intel_dp->DP while tearing down the link, to
1575 * facilitate link retraining (e.g. after hotplug). Hence clear all
1576 * enable bits here to ensure that we don't enable too much. */
1577 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1578 intel_dp->DP |= DP_PLL_ENABLE;
1579 I915_WRITE(DP_A, intel_dp->DP);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001580 POSTING_READ(DP_A);
1581 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001582}
1583
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001584static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001585{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1587 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1588 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 u32 dpa_ctl;
1591
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001592 assert_pipe_disabled(dev_priv,
1593 to_intel_crtc(crtc)->pipe);
1594
Jesse Barnesd240f202010-08-13 15:43:26 -07001595 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001596 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1597 "dp pll off, should be on\n");
1598 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1599
1600 /* We can't rely on the value tracked for the DP register in
1601 * intel_dp->DP because link_down must not change that (otherwise link
1602 * re-training will fail. */
Jesse Barnes298b0b32010-10-07 16:01:24 -07001603 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001604 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001605 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001606 udelay(200);
1607}
1608
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001609/* If the sink supports it, try to set the power state appropriately */
Paulo Zanonic19b0662012-10-15 15:51:41 -03001610void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001611{
1612 int ret, i;
1613
1614 /* Should have a valid DPCD by this point */
1615 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1616 return;
1617
1618 if (mode != DRM_MODE_DPMS_ON) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001619 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1620 DP_SET_POWER_D3);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001621 } else {
1622 /*
1623 * When turning on, we need to retry for 1ms to give the sink
1624 * time to wake up.
1625 */
1626 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001627 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1628 DP_SET_POWER_D0);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001629 if (ret == 1)
1630 break;
1631 msleep(1);
1632 }
1633 }
Jani Nikulaf9cac722014-09-02 16:33:52 +03001634
1635 if (ret != 1)
1636 DRM_DEBUG_KMS("failed to %s sink power state\n",
1637 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001638}
1639
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001640static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1641 enum pipe *pipe)
Jesse Barnesd240f202010-08-13 15:43:26 -07001642{
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001643 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001644 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001645 struct drm_device *dev = encoder->base.dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak6d129be2014-03-05 16:20:54 +02001647 enum intel_display_power_domain power_domain;
1648 u32 tmp;
1649
1650 power_domain = intel_display_port_power_domain(encoder);
1651 if (!intel_display_power_enabled(dev_priv, power_domain))
1652 return false;
1653
1654 tmp = I915_READ(intel_dp->output_reg);
Jesse Barnesd240f202010-08-13 15:43:26 -07001655
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001656 if (!(tmp & DP_PORT_EN))
1657 return false;
1658
Imre Deakbc7d38a2013-05-16 14:40:36 +03001659 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001660 *pipe = PORT_TO_PIPE_CPT(tmp);
Ville Syrjälä71485e02014-04-09 13:28:55 +03001661 } else if (IS_CHERRYVIEW(dev)) {
1662 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001663 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001664 *pipe = PORT_TO_PIPE(tmp);
1665 } else {
1666 u32 trans_sel;
1667 u32 trans_dp;
1668 int i;
1669
1670 switch (intel_dp->output_reg) {
1671 case PCH_DP_B:
1672 trans_sel = TRANS_DP_PORT_SEL_B;
1673 break;
1674 case PCH_DP_C:
1675 trans_sel = TRANS_DP_PORT_SEL_C;
1676 break;
1677 case PCH_DP_D:
1678 trans_sel = TRANS_DP_PORT_SEL_D;
1679 break;
1680 default:
1681 return true;
1682 }
1683
Damien Lespiau055e3932014-08-18 13:49:10 +01001684 for_each_pipe(dev_priv, i) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001685 trans_dp = I915_READ(TRANS_DP_CTL(i));
1686 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1687 *pipe = i;
1688 return true;
1689 }
1690 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001691
Daniel Vetter4a0833e2012-10-26 10:58:11 +02001692 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1693 intel_dp->output_reg);
1694 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001695
1696 return true;
1697}
1698
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001699static void intel_dp_get_config(struct intel_encoder *encoder,
1700 struct intel_crtc_config *pipe_config)
1701{
1702 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001703 u32 tmp, flags = 0;
Xiong Zhang63000ef2013-06-28 12:59:06 +08001704 struct drm_device *dev = encoder->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 enum port port = dp_to_dig_port(intel_dp)->port;
1707 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä18442d02013-09-13 16:00:08 +03001708 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001709
Daniel Vetter9ed109a2014-04-24 23:54:52 +02001710 tmp = I915_READ(intel_dp->output_reg);
1711 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1712 pipe_config->has_audio = true;
1713
Xiong Zhang63000ef2013-06-28 12:59:06 +08001714 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
Xiong Zhang63000ef2013-06-28 12:59:06 +08001715 if (tmp & DP_SYNC_HS_HIGH)
1716 flags |= DRM_MODE_FLAG_PHSYNC;
1717 else
1718 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001719
Xiong Zhang63000ef2013-06-28 12:59:06 +08001720 if (tmp & DP_SYNC_VS_HIGH)
1721 flags |= DRM_MODE_FLAG_PVSYNC;
1722 else
1723 flags |= DRM_MODE_FLAG_NVSYNC;
1724 } else {
1725 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1726 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1727 flags |= DRM_MODE_FLAG_PHSYNC;
1728 else
1729 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001730
Xiong Zhang63000ef2013-06-28 12:59:06 +08001731 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1732 flags |= DRM_MODE_FLAG_PVSYNC;
1733 else
1734 flags |= DRM_MODE_FLAG_NVSYNC;
1735 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001736
1737 pipe_config->adjusted_mode.flags |= flags;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001738
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03001739 pipe_config->has_dp_encoder = true;
1740
1741 intel_dp_get_m_n(crtc, pipe_config);
1742
Ville Syrjälä18442d02013-09-13 16:00:08 +03001743 if (port == PORT_A) {
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001744 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1745 pipe_config->port_clock = 162000;
1746 else
1747 pipe_config->port_clock = 270000;
1748 }
Ville Syrjälä18442d02013-09-13 16:00:08 +03001749
1750 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1751 &pipe_config->dp_m_n);
1752
1753 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1754 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1755
Damien Lespiau241bfc32013-09-25 16:45:37 +01001756 pipe_config->adjusted_mode.crtc_clock = dotclock;
Daniel Vetter7f16e5c2013-11-04 16:28:47 +01001757
Jani Nikulac6cd2ee2013-10-21 10:52:07 +03001758 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1759 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1760 /*
1761 * This is a big fat ugly hack.
1762 *
1763 * Some machines in UEFI boot mode provide us a VBT that has 18
1764 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1765 * unknown we fail to light up. Yet the same BIOS boots up with
1766 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1767 * max, not what it tells us to use.
1768 *
1769 * Note: This will still be broken if the eDP panel is not lit
1770 * up by the BIOS, and thus we can't get the mode at module
1771 * load.
1772 */
1773 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1774 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1775 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1776 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001777}
1778
Rodrigo Vivi34eb7572014-06-12 10:16:40 -07001779static bool is_edp_psr(struct intel_dp *intel_dp)
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001780{
Rodrigo Vivi34eb7572014-06-12 10:16:40 -07001781 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001782}
1783
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001784static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1785{
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787
Ben Widawsky18b59922013-09-20 09:35:30 -07001788 if (!HAS_PSR(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001789 return false;
1790
Ben Widawsky18b59922013-09-20 09:35:30 -07001791 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001792}
1793
1794static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1795 struct edp_vsc_psr *vsc_psr)
1796{
1797 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1798 struct drm_device *dev = dig_port->base.base.dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1801 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1802 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1803 uint32_t *data = (uint32_t *) vsc_psr;
1804 unsigned int i;
1805
1806 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1807 the video DIP being updated before program video DIP data buffer
1808 registers for DIP being updated. */
1809 I915_WRITE(ctl_reg, 0);
1810 POSTING_READ(ctl_reg);
1811
1812 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1813 if (i < sizeof(struct edp_vsc_psr))
1814 I915_WRITE(data_reg + i, *data++);
1815 else
1816 I915_WRITE(data_reg + i, 0);
1817 }
1818
1819 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1820 POSTING_READ(ctl_reg);
1821}
1822
1823static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1824{
1825 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct edp_vsc_psr psr_vsc;
1828
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001829 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1830 memset(&psr_vsc, 0, sizeof(psr_vsc));
1831 psr_vsc.sdp_header.HB0 = 0;
1832 psr_vsc.sdp_header.HB1 = 0x7;
1833 psr_vsc.sdp_header.HB2 = 0x2;
1834 psr_vsc.sdp_header.HB3 = 0x8;
1835 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1836
1837 /* Avoid continuous PSR exit by masking memup and hpd */
Ben Widawsky18b59922013-09-20 09:35:30 -07001838 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
Rodrigo Vivi0cc4b692013-10-03 13:31:26 -03001839 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001840}
1841
1842static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1843{
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001844 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1845 struct drm_device *dev = dig_port->base.base.dev;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001846 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001847 uint32_t aux_clock_divider;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001848 int precharge = 0x3;
1849 int msg_size = 5; /* Header(4) + Message(1) */
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001850 bool only_standby = false;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001851
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001852 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1853
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001854 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1855 only_standby = true;
1856
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001857 /* Enable PSR in sink */
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001858 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
Jani Nikula9d1a1032014-03-14 16:51:15 +02001859 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1860 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001861 else
Jani Nikula9d1a1032014-03-14 16:51:15 +02001862 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1863 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001864
1865 /* Setup AUX registers */
Ben Widawsky18b59922013-09-20 09:35:30 -07001866 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1867 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1868 I915_WRITE(EDP_PSR_AUX_CTL(dev),
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001869 DP_AUX_CH_CTL_TIME_OUT_400us |
1870 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1871 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1872 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1873}
1874
1875static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1876{
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001877 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_device *dev = dig_port->base.base.dev;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 uint32_t max_sleep_time = 0x1f;
1881 uint32_t idle_frames = 1;
1882 uint32_t val = 0x0;
Ben Widawskyed8546a2013-11-04 22:45:05 -08001883 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001884 bool only_standby = false;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001885
Rodrigo Vivi0e0ae652014-06-12 10:16:44 -07001886 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1887 only_standby = true;
1888
1889 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001890 val |= EDP_PSR_LINK_STANDBY;
1891 val |= EDP_PSR_TP2_TP3_TIME_0us;
1892 val |= EDP_PSR_TP1_TIME_0us;
1893 val |= EDP_PSR_SKIP_AUX_EXIT;
Rodrigo Vivi82c56252014-06-12 10:16:42 -07001894 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001895 } else
1896 val |= EDP_PSR_LINK_DISABLE;
1897
Ben Widawsky18b59922013-09-20 09:35:30 -07001898 I915_WRITE(EDP_PSR_CTL(dev), val |
Ben Widawsky24bd9bf2014-03-04 22:38:10 -08001899 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001900 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1901 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1902 EDP_PSR_ENABLE);
1903}
1904
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001905static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1906{
1907 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1908 struct drm_device *dev = dig_port->base.base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct drm_crtc *crtc = dig_port->base.base.crtc;
1911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001912
Daniel Vetterf0355c42014-07-11 10:30:15 -07001913 lockdep_assert_held(&dev_priv->psr.lock);
Daniel Vetterf0355c42014-07-11 10:30:15 -07001914 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1915 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1916
Rodrigo Vivia031d702013-10-03 16:15:06 -03001917 dev_priv->psr.source_ok = false;
1918
Daniel Vetter9ca15302014-07-11 10:30:16 -07001919 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001920 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001921 return false;
1922 }
1923
Jani Nikulad330a952014-01-21 11:24:25 +02001924 if (!i915.enable_psr) {
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001925 DRM_DEBUG_KMS("PSR disable by flag\n");
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001926 return false;
1927 }
1928
Rodrigo Vivi4c8c7002014-06-12 10:16:43 -07001929 /* Below limitations aren't valid for Broadwell */
1930 if (IS_BROADWELL(dev))
1931 goto out;
1932
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001933 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1934 S3D_ENABLE) {
1935 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001936 return false;
1937 }
1938
Ville Syrjäläca73b4f2013-09-04 18:25:24 +03001939 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001940 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001941 return false;
1942 }
1943
Rodrigo Vivi4c8c7002014-06-12 10:16:43 -07001944 out:
Rodrigo Vivia031d702013-10-03 16:15:06 -03001945 dev_priv->psr.source_ok = true;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001946 return true;
1947}
1948
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001949static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001950{
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07001951 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1952 struct drm_device *dev = intel_dig_port->base.base.dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001954
Daniel Vetter36383792014-07-11 10:30:13 -07001955 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1956 WARN_ON(dev_priv->psr.active);
Daniel Vetterf0355c42014-07-11 10:30:15 -07001957 lockdep_assert_held(&dev_priv->psr.lock);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001958
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001959 /* Enable PSR on the panel */
1960 intel_edp_psr_enable_sink(intel_dp);
1961
1962 /* Enable PSR on the host */
1963 intel_edp_psr_enable_source(intel_dp);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07001964
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07001965 dev_priv->psr.active = true;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001966}
1967
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001968void intel_edp_psr_enable(struct intel_dp *intel_dp)
1969{
1970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Daniel Vetter109fc2a2014-07-11 10:30:14 -07001971 struct drm_i915_private *dev_priv = dev->dev_private;
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001972
Rodrigo Vivi4704c572014-06-12 10:16:38 -07001973 if (!HAS_PSR(dev)) {
1974 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1975 return;
1976 }
1977
Rodrigo Vivi34eb7572014-06-12 10:16:40 -07001978 if (!is_edp_psr(intel_dp)) {
1979 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1980 return;
1981 }
1982
Daniel Vetterf0355c42014-07-11 10:30:15 -07001983 mutex_lock(&dev_priv->psr.lock);
Daniel Vetter109fc2a2014-07-11 10:30:14 -07001984 if (dev_priv->psr.enabled) {
1985 DRM_DEBUG_KMS("PSR already in use\n");
Daniel Vetterf0355c42014-07-11 10:30:15 -07001986 mutex_unlock(&dev_priv->psr.lock);
Daniel Vetter109fc2a2014-07-11 10:30:14 -07001987 return;
1988 }
1989
Daniel Vetter9ca15302014-07-11 10:30:16 -07001990 dev_priv->psr.busy_frontbuffer_bits = 0;
1991
Rodrigo Vivi16487252014-06-12 10:16:39 -07001992 /* Setup PSR once */
1993 intel_edp_psr_setup(intel_dp);
1994
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07001995 if (intel_edp_psr_match_conditions(intel_dp))
Daniel Vetter9ca15302014-07-11 10:30:16 -07001996 dev_priv->psr.enabled = intel_dp;
Daniel Vetterf0355c42014-07-11 10:30:15 -07001997 mutex_unlock(&dev_priv->psr.lock);
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001998}
1999
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002000void intel_edp_psr_disable(struct intel_dp *intel_dp)
2001{
2002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004
Daniel Vetterf0355c42014-07-11 10:30:15 -07002005 mutex_lock(&dev_priv->psr.lock);
2006 if (!dev_priv->psr.enabled) {
2007 mutex_unlock(&dev_priv->psr.lock);
2008 return;
2009 }
2010
Daniel Vetter36383792014-07-11 10:30:13 -07002011 if (dev_priv->psr.active) {
2012 I915_WRITE(EDP_PSR_CTL(dev),
2013 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002014
Daniel Vetter36383792014-07-11 10:30:13 -07002015 /* Wait till PSR is idle */
2016 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2017 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2018 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2019
2020 dev_priv->psr.active = false;
2021 } else {
2022 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2023 }
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002024
Daniel Vetter2807cf62014-07-11 10:30:11 -07002025 dev_priv->psr.enabled = NULL;
Daniel Vetterf0355c42014-07-11 10:30:15 -07002026 mutex_unlock(&dev_priv->psr.lock);
Daniel Vetter9ca15302014-07-11 10:30:16 -07002027
2028 cancel_delayed_work_sync(&dev_priv->psr.work);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03002029}
2030
Daniel Vetterf02a3262014-06-16 19:51:21 +02002031static void intel_edp_psr_work(struct work_struct *work)
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002032{
2033 struct drm_i915_private *dev_priv =
2034 container_of(work, typeof(*dev_priv), psr.work.work);
Daniel Vetter2807cf62014-07-11 10:30:11 -07002035 struct intel_dp *intel_dp = dev_priv->psr.enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002036
Daniel Vetterf0355c42014-07-11 10:30:15 -07002037 mutex_lock(&dev_priv->psr.lock);
2038 intel_dp = dev_priv->psr.enabled;
2039
Daniel Vetter2807cf62014-07-11 10:30:11 -07002040 if (!intel_dp)
Daniel Vetterf0355c42014-07-11 10:30:15 -07002041 goto unlock;
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03002042
Daniel Vetter9ca15302014-07-11 10:30:16 -07002043 /*
2044 * The delayed work can race with an invalidate hence we need to
2045 * recheck. Since psr_flush first clears this and then reschedules we
2046 * won't ever miss a flush when bailing out here.
2047 */
2048 if (dev_priv->psr.busy_frontbuffer_bits)
2049 goto unlock;
2050
2051 intel_edp_psr_do_enable(intel_dp);
Daniel Vetterf0355c42014-07-11 10:30:15 -07002052unlock:
2053 mutex_unlock(&dev_priv->psr.lock);
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03002054}
2055
Daniel Vetter9ca15302014-07-11 10:30:16 -07002056static void intel_edp_psr_do_exit(struct drm_device *dev)
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002057{
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059
Daniel Vetter36383792014-07-11 10:30:13 -07002060 if (dev_priv->psr.active) {
2061 u32 val = I915_READ(EDP_PSR_CTL(dev));
2062
2063 WARN_ON(!(val & EDP_PSR_ENABLE));
2064
2065 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2066
2067 dev_priv->psr.active = false;
2068 }
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002069
Daniel Vetter9ca15302014-07-11 10:30:16 -07002070}
2071
2072void intel_edp_psr_invalidate(struct drm_device *dev,
2073 unsigned frontbuffer_bits)
2074{
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct drm_crtc *crtc;
2077 enum pipe pipe;
2078
Daniel Vetter9ca15302014-07-11 10:30:16 -07002079 mutex_lock(&dev_priv->psr.lock);
2080 if (!dev_priv->psr.enabled) {
2081 mutex_unlock(&dev_priv->psr.lock);
2082 return;
2083 }
2084
2085 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2086 pipe = to_intel_crtc(crtc)->pipe;
2087
2088 intel_edp_psr_do_exit(dev);
2089
2090 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2091
2092 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2093 mutex_unlock(&dev_priv->psr.lock);
2094}
2095
2096void intel_edp_psr_flush(struct drm_device *dev,
2097 unsigned frontbuffer_bits)
2098{
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 struct drm_crtc *crtc;
2101 enum pipe pipe;
2102
Daniel Vetter9ca15302014-07-11 10:30:16 -07002103 mutex_lock(&dev_priv->psr.lock);
2104 if (!dev_priv->psr.enabled) {
2105 mutex_unlock(&dev_priv->psr.lock);
2106 return;
2107 }
2108
2109 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2110 pipe = to_intel_crtc(crtc)->pipe;
2111 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2112
2113 /*
2114 * On Haswell sprite plane updates don't result in a psr invalidating
2115 * signal in the hardware. Which means we need to manually fake this in
2116 * software for all flushes, not just when we've seen a preceding
2117 * invalidation through frontbuffer rendering.
2118 */
2119 if (IS_HASWELL(dev) &&
2120 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2121 intel_edp_psr_do_exit(dev);
2122
2123 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2124 schedule_delayed_work(&dev_priv->psr.work,
2125 msecs_to_jiffies(100));
Daniel Vetterf0355c42014-07-11 10:30:15 -07002126 mutex_unlock(&dev_priv->psr.lock);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002127}
2128
2129void intel_edp_psr_init(struct drm_device *dev)
2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002133 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
Daniel Vetterf0355c42014-07-11 10:30:15 -07002134 mutex_init(&dev_priv->psr.lock);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07002135}
2136
Daniel Vettere8cb4552012-07-01 13:05:48 +02002137static void intel_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002138{
Daniel Vettere8cb4552012-07-01 13:05:48 +02002139 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03002140 enum port port = dp_to_dig_port(intel_dp)->port;
2141 struct drm_device *dev = encoder->base.dev;
Daniel Vetter6cb49832012-05-20 17:14:50 +02002142
2143 /* Make sure the panel is off before trying to change the mode. But also
2144 * ensure that we have vdd while we switch off the panel. */
Jani Nikula24f3e092014-03-17 16:43:36 +02002145 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01002146 intel_edp_backlight_off(intel_dp);
Jani Nikulafdbc3b12013-11-12 17:10:13 +02002147 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Daniel Vetter4be73782014-01-17 14:39:48 +01002148 intel_edp_panel_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02002149
2150 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
Imre Deak982a3862013-05-23 19:39:40 +03002151 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
Daniel Vetter37398502012-09-06 22:15:44 +02002152 intel_dp_link_down(intel_dp);
Jesse Barnesd240f202010-08-13 15:43:26 -07002153}
2154
Ville Syrjälä49277c32014-03-31 18:21:26 +03002155static void g4x_post_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002156{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002157 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03002158 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002159
Ville Syrjälä49277c32014-03-31 18:21:26 +03002160 if (port != PORT_A)
2161 return;
2162
2163 intel_dp_link_down(intel_dp);
2164 ironlake_edp_pll_off(intel_dp);
2165}
2166
2167static void vlv_post_disable_dp(struct intel_encoder *encoder)
2168{
2169 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2170
2171 intel_dp_link_down(intel_dp);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002172}
2173
Ville Syrjälä580d3812014-04-09 13:29:00 +03002174static void chv_post_disable_dp(struct intel_encoder *encoder)
2175{
2176 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2177 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2178 struct drm_device *dev = encoder->base.dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc =
2181 to_intel_crtc(encoder->base.crtc);
2182 enum dpio_channel ch = vlv_dport_to_channel(dport);
2183 enum pipe pipe = intel_crtc->pipe;
2184 u32 val;
2185
2186 intel_dp_link_down(intel_dp);
2187
2188 mutex_lock(&dev_priv->dpio_lock);
2189
2190 /* Propagate soft reset to data lane reset */
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002191 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
Ville Syrjäläd2152b22014-04-28 14:15:24 +03002192 val |= CHV_PCS_REQ_SOFTRESET_EN;
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002193 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
Ville Syrjäläd2152b22014-04-28 14:15:24 +03002194
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002195 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2196 val |= CHV_PCS_REQ_SOFTRESET_EN;
2197 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2198
2199 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
Ville Syrjälä580d3812014-04-09 13:29:00 +03002200 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002201 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2202
2203 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2204 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2205 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
Ville Syrjälä580d3812014-04-09 13:29:00 +03002206
2207 mutex_unlock(&dev_priv->dpio_lock);
2208}
2209
Daniel Vettere8cb4552012-07-01 13:05:48 +02002210static void intel_enable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002211{
Daniel Vettere8cb4552012-07-01 13:05:48 +02002212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2213 struct drm_device *dev = encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002214 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002215 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002216
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02002217 if (WARN_ON(dp_reg & DP_PORT_EN))
2218 return;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002219
Jani Nikula24f3e092014-03-17 16:43:36 +02002220 intel_edp_panel_vdd_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002221 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2222 intel_dp_start_link_train(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01002223 intel_edp_panel_on(intel_dp);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03002224 intel_edp_panel_vdd_off(intel_dp, true);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002225 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03002226 intel_dp_stop_link_train(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002227}
Jesse Barnes89b667f2013-04-18 14:51:36 -07002228
Jani Nikulaecff4f32013-09-06 07:38:29 +03002229static void g4x_enable_dp(struct intel_encoder *encoder)
2230{
Jani Nikula828f5c62013-09-05 16:44:45 +03002231 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2232
Jani Nikulaecff4f32013-09-06 07:38:29 +03002233 intel_enable_dp(encoder);
Daniel Vetter4be73782014-01-17 14:39:48 +01002234 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002235}
Jesse Barnes89b667f2013-04-18 14:51:36 -07002236
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002237static void vlv_enable_dp(struct intel_encoder *encoder)
2238{
Jani Nikula828f5c62013-09-05 16:44:45 +03002239 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2240
Daniel Vetter4be73782014-01-17 14:39:48 +01002241 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002242}
2243
Jani Nikulaecff4f32013-09-06 07:38:29 +03002244static void g4x_pre_enable_dp(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002245{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002246 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002247 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002248
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02002249 intel_dp_prepare(encoder);
2250
Daniel Vetterd41f1ef2014-04-24 23:54:53 +02002251 /* Only ilk+ has port A */
2252 if (dport->port == PORT_A) {
2253 ironlake_set_pll_cpu_edp(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002254 ironlake_edp_pll_on(intel_dp);
Daniel Vetterd41f1ef2014-04-24 23:54:53 +02002255 }
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002256}
2257
2258static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2259{
2260 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2261 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07002262 struct drm_device *dev = encoder->base.dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07002263 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002264 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002265 enum dpio_channel port = vlv_dport_to_channel(dport);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002266 int pipe = intel_crtc->pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +03002267 struct edp_power_seq power_seq;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002268 u32 val;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002269
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002270 mutex_lock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002271
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002272 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002273 val = 0;
2274 if (pipe)
2275 val |= (1<<21);
2276 else
2277 val &= ~(1<<21);
2278 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002279 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2280 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2281 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002282
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002283 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002284
Imre Deak2cac6132014-01-30 16:50:42 +02002285 if (is_edp(intel_dp)) {
2286 /* init power sequencer on this pipe and port */
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002287 mutex_lock(&dev_priv->pps_mutex);
Imre Deak2cac6132014-01-30 16:50:42 +02002288 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2289 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2290 &power_seq);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002291 mutex_unlock(&dev_priv->pps_mutex);
Imre Deak2cac6132014-01-30 16:50:42 +02002292 }
Jani Nikulabf13e812013-09-06 07:40:05 +03002293
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002294 intel_enable_dp(encoder);
2295
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002296 vlv_wait_port_ready(dev_priv, dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002297}
2298
Jani Nikulaecff4f32013-09-06 07:38:29 +03002299static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07002300{
2301 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2302 struct drm_device *dev = encoder->base.dev;
2303 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002304 struct intel_crtc *intel_crtc =
2305 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002306 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002307 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07002308
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02002309 intel_dp_prepare(encoder);
2310
Jesse Barnes89b667f2013-04-18 14:51:36 -07002311 /* Program Tx lane resets to default */
Chris Wilson0980a602013-07-26 19:57:35 +01002312 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002313 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07002314 DPIO_PCS_TX_LANE2_RESET |
2315 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002316 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07002317 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2318 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2319 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2320 DPIO_PCS_CLK_SOFT_RESET);
2321
2322 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002323 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2324 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2325 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Chris Wilson0980a602013-07-26 19:57:35 +01002326 mutex_unlock(&dev_priv->dpio_lock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002327}
2328
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002329static void chv_pre_enable_dp(struct intel_encoder *encoder)
2330{
2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2333 struct drm_device *dev = encoder->base.dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct edp_power_seq power_seq;
2336 struct intel_crtc *intel_crtc =
2337 to_intel_crtc(encoder->base.crtc);
2338 enum dpio_channel ch = vlv_dport_to_channel(dport);
2339 int pipe = intel_crtc->pipe;
2340 int data, i;
Ville Syrjälä949c1d42014-04-09 13:28:58 +03002341 u32 val;
2342
2343 mutex_lock(&dev_priv->dpio_lock);
2344
2345 /* Deassert soft data lane reset*/
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002346 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
Ville Syrjäläd2152b22014-04-28 14:15:24 +03002347 val |= CHV_PCS_REQ_SOFTRESET_EN;
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002348 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
Ville Syrjäläd2152b22014-04-28 14:15:24 +03002349
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002350 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2351 val |= CHV_PCS_REQ_SOFTRESET_EN;
2352 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2353
2354 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
Ville Syrjälä949c1d42014-04-09 13:28:58 +03002355 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
Ville Syrjälä97fd4d52014-04-09 13:29:02 +03002356 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2357
2358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2359 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2360 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002361
2362 /* Program Tx lane latency optimal setting*/
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002363 for (i = 0; i < 4; i++) {
2364 /* Set the latency optimal bit */
2365 data = (i == 1) ? 0x0 : 0x6;
2366 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2367 data << DPIO_FRC_LATENCY_SHFIT);
2368
2369 /* Set the upar bit */
2370 data = (i == 1) ? 0x0 : 0x1;
2371 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2372 data << DPIO_UPAR_SHIFT);
2373 }
2374
2375 /* Data lane stagger programming */
2376 /* FIXME: Fix up value only after power analysis */
2377
2378 mutex_unlock(&dev_priv->dpio_lock);
2379
2380 if (is_edp(intel_dp)) {
2381 /* init power sequencer on this pipe and port */
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002382 mutex_lock(&dev_priv->pps_mutex);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002383 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2384 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2385 &power_seq);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002386 mutex_unlock(&dev_priv->pps_mutex);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002387 }
2388
2389 intel_enable_dp(encoder);
2390
2391 vlv_wait_port_ready(dev_priv, dport);
2392}
2393
Ville Syrjälä9197c882014-04-09 13:29:05 +03002394static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2395{
2396 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2397 struct drm_device *dev = encoder->base.dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc =
2400 to_intel_crtc(encoder->base.crtc);
2401 enum dpio_channel ch = vlv_dport_to_channel(dport);
2402 enum pipe pipe = intel_crtc->pipe;
2403 u32 val;
2404
Ville Syrjälä625695f2014-06-28 02:04:02 +03002405 intel_dp_prepare(encoder);
2406
Ville Syrjälä9197c882014-04-09 13:29:05 +03002407 mutex_lock(&dev_priv->dpio_lock);
2408
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03002409 /* program left/right clock distribution */
2410 if (pipe != PIPE_B) {
2411 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2412 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2413 if (ch == DPIO_CH0)
2414 val |= CHV_BUFLEFTENA1_FORCE;
2415 if (ch == DPIO_CH1)
2416 val |= CHV_BUFRIGHTENA1_FORCE;
2417 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2418 } else {
2419 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2420 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2421 if (ch == DPIO_CH0)
2422 val |= CHV_BUFLEFTENA2_FORCE;
2423 if (ch == DPIO_CH1)
2424 val |= CHV_BUFRIGHTENA2_FORCE;
2425 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2426 }
2427
Ville Syrjälä9197c882014-04-09 13:29:05 +03002428 /* program clock channel usage */
2429 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2430 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2431 if (pipe != PIPE_B)
2432 val &= ~CHV_PCS_USEDCLKCHANNEL;
2433 else
2434 val |= CHV_PCS_USEDCLKCHANNEL;
2435 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2436
2437 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2438 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2439 if (pipe != PIPE_B)
2440 val &= ~CHV_PCS_USEDCLKCHANNEL;
2441 else
2442 val |= CHV_PCS_USEDCLKCHANNEL;
2443 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2444
2445 /*
2446 * This a a bit weird since generally CL
2447 * matches the pipe, but here we need to
2448 * pick the CL based on the port.
2449 */
2450 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2451 if (pipe != PIPE_B)
2452 val &= ~CHV_CMN_USEDCLKCHANNEL;
2453 else
2454 val |= CHV_CMN_USEDCLKCHANNEL;
2455 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2456
2457 mutex_unlock(&dev_priv->dpio_lock);
2458}
2459
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002460/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002461 * Native read with retry for link status and receiver capability reads for
2462 * cases where the sink may still be asleep.
Jani Nikula9d1a1032014-03-14 16:51:15 +02002463 *
2464 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2465 * supposed to retry 3 times per the spec.
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002466 */
Jani Nikula9d1a1032014-03-14 16:51:15 +02002467static ssize_t
2468intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2469 void *buffer, size_t size)
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002470{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002471 ssize_t ret;
2472 int i;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002473
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002474 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02002475 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2476 if (ret == size)
2477 return ret;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002478 msleep(1);
2479 }
2480
Jani Nikula9d1a1032014-03-14 16:51:15 +02002481 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002482}
2483
2484/*
2485 * Fetch AUX CH registers 0x202 - 0x207 which contain
2486 * link status information
2487 */
2488static bool
Keith Packard93f62da2011-11-01 19:45:03 -07002489intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002490{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002491 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2492 DP_LANE0_1_STATUS,
2493 link_status,
2494 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002495}
2496
Paulo Zanoni11002442014-06-13 18:45:41 -03002497/* These are source-specific values. */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002498static uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08002499intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002500{
Paulo Zanoni30add222012-10-26 19:05:45 -02002501 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002502 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002503
Paulo Zanoni9576c272014-06-13 18:45:40 -03002504 if (IS_VALLEYVIEW(dev))
Sonika Jindalbd600182014-08-08 16:23:41 +05302505 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002506 else if (IS_GEN7(dev) && port == PORT_A)
Sonika Jindalbd600182014-08-08 16:23:41 +05302507 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002508 else if (HAS_PCH_CPT(dev) && port != PORT_A)
Sonika Jindalbd600182014-08-08 16:23:41 +05302509 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
Keith Packard1a2eb462011-11-16 16:26:07 -08002510 else
Sonika Jindalbd600182014-08-08 16:23:41 +05302511 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
Keith Packard1a2eb462011-11-16 16:26:07 -08002512}
2513
2514static uint8_t
2515intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2516{
Paulo Zanoni30add222012-10-26 19:05:45 -02002517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002518 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002519
Paulo Zanoni9576c272014-06-13 18:45:40 -03002520 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002521 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2523 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2525 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2527 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002529 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05302530 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002531 }
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002532 } else if (IS_VALLEYVIEW(dev)) {
2533 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302534 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2535 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2537 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2539 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002541 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05302542 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002543 }
Imre Deakbc7d38a2013-05-16 14:40:36 +03002544 } else if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08002545 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302546 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2547 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2550 return DP_TRAIN_PRE_EMPH_LEVEL_1;
Keith Packard1a2eb462011-11-16 16:26:07 -08002551 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05302552 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Keith Packard1a2eb462011-11-16 16:26:07 -08002553 }
2554 } else {
2555 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302556 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2557 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2559 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2561 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Keith Packard1a2eb462011-11-16 16:26:07 -08002563 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05302564 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Keith Packard1a2eb462011-11-16 16:26:07 -08002565 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002566 }
2567}
2568
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002569static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2570{
2571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002574 struct intel_crtc *intel_crtc =
2575 to_intel_crtc(dport->base.base.crtc);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002576 unsigned long demph_reg_value, preemph_reg_value,
2577 uniqtranscale_reg_value;
2578 uint8_t train_set = intel_dp->train_set[0];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002579 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002580 int pipe = intel_crtc->pipe;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002581
2582 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302583 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002584 preemph_reg_value = 0x0004000;
2585 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302586 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002587 demph_reg_value = 0x2B405555;
2588 uniqtranscale_reg_value = 0x552AB83A;
2589 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302590 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002591 demph_reg_value = 0x2B404040;
2592 uniqtranscale_reg_value = 0x5548B83A;
2593 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302594 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002595 demph_reg_value = 0x2B245555;
2596 uniqtranscale_reg_value = 0x5560B83A;
2597 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302598 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002599 demph_reg_value = 0x2B405555;
2600 uniqtranscale_reg_value = 0x5598DA3A;
2601 break;
2602 default:
2603 return 0;
2604 }
2605 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302606 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002607 preemph_reg_value = 0x0002000;
2608 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302609 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002610 demph_reg_value = 0x2B404040;
2611 uniqtranscale_reg_value = 0x5552B83A;
2612 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302613 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002614 demph_reg_value = 0x2B404848;
2615 uniqtranscale_reg_value = 0x5580B83A;
2616 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302617 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002618 demph_reg_value = 0x2B404040;
2619 uniqtranscale_reg_value = 0x55ADDA3A;
2620 break;
2621 default:
2622 return 0;
2623 }
2624 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302625 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002626 preemph_reg_value = 0x0000000;
2627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302628 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002629 demph_reg_value = 0x2B305555;
2630 uniqtranscale_reg_value = 0x5570B83A;
2631 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002633 demph_reg_value = 0x2B2B4040;
2634 uniqtranscale_reg_value = 0x55ADDA3A;
2635 break;
2636 default:
2637 return 0;
2638 }
2639 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302640 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002641 preemph_reg_value = 0x0006000;
2642 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302643 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002644 demph_reg_value = 0x1B405555;
2645 uniqtranscale_reg_value = 0x55ADDA3A;
2646 break;
2647 default:
2648 return 0;
2649 }
2650 break;
2651 default:
2652 return 0;
2653 }
2654
Chris Wilson0980a602013-07-26 19:57:35 +01002655 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002656 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2657 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2658 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002659 uniqtranscale_reg_value);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002660 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2661 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2662 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2663 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
Chris Wilson0980a602013-07-26 19:57:35 +01002664 mutex_unlock(&dev_priv->dpio_lock);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002665
2666 return 0;
2667}
2668
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002669static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2670{
2671 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2674 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002675 u32 deemph_reg_value, margin_reg_value, val;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002676 uint8_t train_set = intel_dp->train_set[0];
2677 enum dpio_channel ch = vlv_dport_to_channel(dport);
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002678 enum pipe pipe = intel_crtc->pipe;
2679 int i;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002680
2681 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302682 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002683 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302684 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002685 deemph_reg_value = 128;
2686 margin_reg_value = 52;
2687 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302688 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002689 deemph_reg_value = 128;
2690 margin_reg_value = 77;
2691 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302692 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002693 deemph_reg_value = 128;
2694 margin_reg_value = 102;
2695 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302696 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002697 deemph_reg_value = 128;
2698 margin_reg_value = 154;
2699 /* FIXME extra to set for 1200 */
2700 break;
2701 default:
2702 return 0;
2703 }
2704 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302705 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002706 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302707 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002708 deemph_reg_value = 85;
2709 margin_reg_value = 78;
2710 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302711 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002712 deemph_reg_value = 85;
2713 margin_reg_value = 116;
2714 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302715 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002716 deemph_reg_value = 85;
2717 margin_reg_value = 154;
2718 break;
2719 default:
2720 return 0;
2721 }
2722 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302723 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002724 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002726 deemph_reg_value = 64;
2727 margin_reg_value = 104;
2728 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002730 deemph_reg_value = 64;
2731 margin_reg_value = 154;
2732 break;
2733 default:
2734 return 0;
2735 }
2736 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302737 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002738 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002740 deemph_reg_value = 43;
2741 margin_reg_value = 154;
2742 break;
2743 default:
2744 return 0;
2745 }
2746 break;
2747 default:
2748 return 0;
2749 }
2750
2751 mutex_lock(&dev_priv->dpio_lock);
2752
2753 /* Clear calc init */
Ville Syrjälä1966e592014-04-09 13:29:04 +03002754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2755 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2756 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2757
2758 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2759 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2760 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002761
2762 /* Program swing deemph */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002763 for (i = 0; i < 4; i++) {
2764 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2765 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2766 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2767 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2768 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002769
2770 /* Program swing margin */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002771 for (i = 0; i < 4; i++) {
2772 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
Ville Syrjälä1fb44502014-06-28 02:04:03 +03002773 val &= ~DPIO_SWING_MARGIN000_MASK;
2774 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002775 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2776 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002777
2778 /* Disable unique transition scale */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002779 for (i = 0; i < 4; i++) {
2780 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2781 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2782 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2783 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002784
2785 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
Sonika Jindalbd600182014-08-08 16:23:41 +05302786 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002787 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
Sonika Jindalbd600182014-08-08 16:23:41 +05302788 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002789
2790 /*
2791 * The document said it needs to set bit 27 for ch0 and bit 26
2792 * for ch1. Might be a typo in the doc.
2793 * For now, for this unique transition scale selection, set bit
2794 * 27 for ch0 and ch1.
2795 */
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002796 for (i = 0; i < 4; i++) {
2797 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2798 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2799 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2800 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002801
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03002802 for (i = 0; i < 4; i++) {
2803 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2804 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2805 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2806 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2807 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002808 }
2809
2810 /* Start swing calculation */
Ville Syrjälä1966e592014-04-09 13:29:04 +03002811 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2812 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2813 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2814
2815 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2816 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002818
2819 /* LRC Bypass */
2820 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2821 val |= DPIO_LRC_BYPASS;
2822 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2823
2824 mutex_unlock(&dev_priv->dpio_lock);
2825
2826 return 0;
2827}
2828
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002829static void
Jani Nikula0301b3a2013-10-15 09:36:08 +03002830intel_get_adjust_train(struct intel_dp *intel_dp,
2831 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002832{
2833 uint8_t v = 0;
2834 uint8_t p = 0;
2835 int lane;
Keith Packard1a2eb462011-11-16 16:26:07 -08002836 uint8_t voltage_max;
2837 uint8_t preemph_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002838
Jesse Barnes33a34e42010-09-08 12:42:02 -07002839 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Daniel Vetter0f037bd2012-10-18 10:15:27 +02002840 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2841 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002842
2843 if (this_v > v)
2844 v = this_v;
2845 if (this_p > p)
2846 p = this_p;
2847 }
2848
Keith Packard1a2eb462011-11-16 16:26:07 -08002849 voltage_max = intel_dp_voltage_max(intel_dp);
Keith Packard417e8222011-11-01 19:54:11 -07002850 if (v >= voltage_max)
2851 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002852
Keith Packard1a2eb462011-11-16 16:26:07 -08002853 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2854 if (p >= preemph_max)
2855 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002856
2857 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07002858 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002859}
2860
2861static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002862intel_gen4_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002863{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002864 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002865
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002866 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002868 default:
2869 signal_levels |= DP_VOLTAGE_0_4;
2870 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302871 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002872 signal_levels |= DP_VOLTAGE_0_6;
2873 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002875 signal_levels |= DP_VOLTAGE_0_8;
2876 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002878 signal_levels |= DP_VOLTAGE_1_2;
2879 break;
2880 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002881 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302882 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002883 default:
2884 signal_levels |= DP_PRE_EMPHASIS_0;
2885 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302886 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002887 signal_levels |= DP_PRE_EMPHASIS_3_5;
2888 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302889 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002890 signal_levels |= DP_PRE_EMPHASIS_6;
2891 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05302892 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002893 signal_levels |= DP_PRE_EMPHASIS_9_5;
2894 break;
2895 }
2896 return signal_levels;
2897}
2898
Zhenyu Wange3421a12010-04-08 09:43:27 +08002899/* Gen6's DP voltage swing and pre-emphasis control */
2900static uint32_t
2901intel_gen6_edp_signal_levels(uint8_t train_set)
2902{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002903 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2904 DP_TRAIN_PRE_EMPHASIS_MASK);
2905 switch (signal_levels) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002908 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05302909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002910 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05302911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002913 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05302914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002916 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05302917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002919 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002920 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002921 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2922 "0x%x\n", signal_levels);
2923 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002924 }
2925}
2926
Keith Packard1a2eb462011-11-16 16:26:07 -08002927/* Gen7's DP voltage swing and pre-emphasis control */
2928static uint32_t
2929intel_gen7_edp_signal_levels(uint8_t train_set)
2930{
2931 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2932 DP_TRAIN_PRE_EMPHASIS_MASK);
2933 switch (signal_levels) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08002935 return EDP_LINK_TRAIN_400MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05302936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08002937 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05302938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Keith Packard1a2eb462011-11-16 16:26:07 -08002939 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2940
Sonika Jindalbd600182014-08-08 16:23:41 +05302941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08002942 return EDP_LINK_TRAIN_600MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05302943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08002944 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2945
Sonika Jindalbd600182014-08-08 16:23:41 +05302946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08002947 return EDP_LINK_TRAIN_800MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05302948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08002949 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2950
2951 default:
2952 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2953 "0x%x\n", signal_levels);
2954 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2955 }
2956}
2957
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002958/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2959static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002960intel_hsw_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002961{
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002962 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2963 DP_TRAIN_PRE_EMPHASIS_MASK);
2964 switch (signal_levels) {
Sonika Jindalbd600182014-08-08 16:23:41 +05302965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302966 return DDI_BUF_TRANS_SELECT(0);
Sonika Jindalbd600182014-08-08 16:23:41 +05302967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302968 return DDI_BUF_TRANS_SELECT(1);
Sonika Jindalbd600182014-08-08 16:23:41 +05302969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302970 return DDI_BUF_TRANS_SELECT(2);
Sonika Jindalbd600182014-08-08 16:23:41 +05302971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302972 return DDI_BUF_TRANS_SELECT(3);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002973
Sonika Jindalbd600182014-08-08 16:23:41 +05302974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302975 return DDI_BUF_TRANS_SELECT(4);
Sonika Jindalbd600182014-08-08 16:23:41 +05302976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302977 return DDI_BUF_TRANS_SELECT(5);
Sonika Jindalbd600182014-08-08 16:23:41 +05302978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302979 return DDI_BUF_TRANS_SELECT(6);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002980
Sonika Jindalbd600182014-08-08 16:23:41 +05302981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302982 return DDI_BUF_TRANS_SELECT(7);
Sonika Jindalbd600182014-08-08 16:23:41 +05302983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302984 return DDI_BUF_TRANS_SELECT(8);
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002985 default:
2986 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2987 "0x%x\n", signal_levels);
Sonika Jindalc5fe6a02014-08-11 08:57:36 +05302988 return DDI_BUF_TRANS_SELECT(0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002989 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002990}
2991
Paulo Zanonif0a34242012-12-06 16:51:50 -02002992/* Properly updates "DP" with the correct signal levels. */
2993static void
2994intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2995{
2996 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002997 enum port port = intel_dig_port->port;
Paulo Zanonif0a34242012-12-06 16:51:50 -02002998 struct drm_device *dev = intel_dig_port->base.base.dev;
2999 uint32_t signal_levels, mask;
3000 uint8_t train_set = intel_dp->train_set[0];
3001
Paulo Zanoni9576c272014-06-13 18:45:40 -03003002 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02003003 signal_levels = intel_hsw_signal_levels(train_set);
3004 mask = DDI_BUF_EMP_MASK;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003005 } else if (IS_CHERRYVIEW(dev)) {
3006 signal_levels = intel_chv_signal_levels(intel_dp);
3007 mask = 0;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003008 } else if (IS_VALLEYVIEW(dev)) {
3009 signal_levels = intel_vlv_signal_levels(intel_dp);
3010 mask = 0;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003011 } else if (IS_GEN7(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02003012 signal_levels = intel_gen7_edp_signal_levels(train_set);
3013 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003014 } else if (IS_GEN6(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02003015 signal_levels = intel_gen6_edp_signal_levels(train_set);
3016 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3017 } else {
3018 signal_levels = intel_gen4_signal_levels(train_set);
3019 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3020 }
3021
3022 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3023
3024 *DP = (*DP & ~mask) | signal_levels;
3025}
3026
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003027static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01003028intel_dp_set_link_train(struct intel_dp *intel_dp,
Jani Nikula70aff662013-09-27 15:10:44 +03003029 uint32_t *DP,
Chris Wilson58e10eb2010-10-03 10:56:11 +01003030 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003031{
Paulo Zanoni174edf12012-10-26 19:05:50 -02003032 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3033 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003034 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02003035 enum port port = intel_dig_port->port;
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03003036 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3037 int ret, len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003038
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03003039 if (HAS_DDI(dev)) {
Imre Deak3ab9c632013-05-03 12:57:41 +03003040 uint32_t temp = I915_READ(DP_TP_CTL(port));
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003041
3042 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3043 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3044 else
3045 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3046
3047 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3048 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3049 case DP_TRAINING_PATTERN_DISABLE:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003050 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3051
3052 break;
3053 case DP_TRAINING_PATTERN_1:
3054 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3055 break;
3056 case DP_TRAINING_PATTERN_2:
3057 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3058 break;
3059 case DP_TRAINING_PATTERN_3:
3060 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3061 break;
3062 }
Paulo Zanoni174edf12012-10-26 19:05:50 -02003063 I915_WRITE(DP_TP_CTL(port), temp);
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003064
Imre Deakbc7d38a2013-05-16 14:40:36 +03003065 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Jani Nikula70aff662013-09-27 15:10:44 +03003066 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003067
3068 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3069 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03003070 *DP |= DP_LINK_TRAIN_OFF_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003071 break;
3072 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03003073 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003074 break;
3075 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03003076 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003077 break;
3078 case DP_TRAINING_PATTERN_3:
3079 DRM_ERROR("DP training pattern 3 not supported\n");
Jani Nikula70aff662013-09-27 15:10:44 +03003080 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003081 break;
3082 }
3083
3084 } else {
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003085 if (IS_CHERRYVIEW(dev))
3086 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3087 else
3088 *DP &= ~DP_LINK_TRAIN_MASK;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003089
3090 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3091 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03003092 *DP |= DP_LINK_TRAIN_OFF;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003093 break;
3094 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03003095 *DP |= DP_LINK_TRAIN_PAT_1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003096 break;
3097 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03003098 *DP |= DP_LINK_TRAIN_PAT_2;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003099 break;
3100 case DP_TRAINING_PATTERN_3:
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003101 if (IS_CHERRYVIEW(dev)) {
3102 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3103 } else {
3104 DRM_ERROR("DP training pattern 3 not supported\n");
3105 *DP |= DP_LINK_TRAIN_PAT_2;
3106 }
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003107 break;
3108 }
3109 }
3110
Jani Nikula70aff662013-09-27 15:10:44 +03003111 I915_WRITE(intel_dp->output_reg, *DP);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003112 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003113
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03003114 buf[0] = dp_train_pat;
3115 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003116 DP_TRAINING_PATTERN_DISABLE) {
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03003117 /* don't write DP_TRAINING_LANEx_SET on disable */
3118 len = 1;
3119 } else {
3120 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3121 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3122 len = intel_dp->lane_count + 1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003123 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003124
Jani Nikula9d1a1032014-03-14 16:51:15 +02003125 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3126 buf, len);
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03003127
3128 return ret == len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003129}
3130
Jani Nikula70aff662013-09-27 15:10:44 +03003131static bool
3132intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3133 uint8_t dp_train_pat)
3134{
Jani Nikula953d22e2013-10-04 15:08:47 +03003135 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
Jani Nikula70aff662013-09-27 15:10:44 +03003136 intel_dp_set_signal_levels(intel_dp, DP);
3137 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3138}
3139
3140static bool
3141intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
Jani Nikula0301b3a2013-10-15 09:36:08 +03003142 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Jani Nikula70aff662013-09-27 15:10:44 +03003143{
3144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3145 struct drm_device *dev = intel_dig_port->base.base.dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int ret;
3148
3149 intel_get_adjust_train(intel_dp, link_status);
3150 intel_dp_set_signal_levels(intel_dp, DP);
3151
3152 I915_WRITE(intel_dp->output_reg, *DP);
3153 POSTING_READ(intel_dp->output_reg);
3154
Jani Nikula9d1a1032014-03-14 16:51:15 +02003155 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3156 intel_dp->train_set, intel_dp->lane_count);
Jani Nikula70aff662013-09-27 15:10:44 +03003157
3158 return ret == intel_dp->lane_count;
3159}
3160
Imre Deak3ab9c632013-05-03 12:57:41 +03003161static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3162{
3163 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3164 struct drm_device *dev = intel_dig_port->base.base.dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 enum port port = intel_dig_port->port;
3167 uint32_t val;
3168
3169 if (!HAS_DDI(dev))
3170 return;
3171
3172 val = I915_READ(DP_TP_CTL(port));
3173 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3174 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3175 I915_WRITE(DP_TP_CTL(port), val);
3176
3177 /*
3178 * On PORT_A we can have only eDP in SST mode. There the only reason
3179 * we need to set idle transmission mode is to work around a HW issue
3180 * where we enable the pipe while not in idle link-training mode.
3181 * In this case there is requirement to wait for a minimum number of
3182 * idle patterns to be sent.
3183 */
3184 if (port == PORT_A)
3185 return;
3186
3187 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3188 1))
3189 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3190}
3191
Jesse Barnes33a34e42010-09-08 12:42:02 -07003192/* Enable corresponding port and start training pattern 1 */
Paulo Zanonic19b0662012-10-15 15:51:41 -03003193void
Jesse Barnes33a34e42010-09-08 12:42:02 -07003194intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003195{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003196 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
Paulo Zanonic19b0662012-10-15 15:51:41 -03003197 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003198 int i;
3199 uint8_t voltage;
Keith Packardcdb0e952011-11-01 20:00:06 -07003200 int voltage_tries, loop_tries;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003201 uint32_t DP = intel_dp->DP;
Jani Nikula6aba5b62013-10-04 15:08:10 +03003202 uint8_t link_config[2];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003203
Paulo Zanoniaffa9352012-11-23 15:30:39 -02003204 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03003205 intel_ddi_prepare_link_retrain(encoder);
3206
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003207 /* Write the link configuration data */
Jani Nikula6aba5b62013-10-04 15:08:10 +03003208 link_config[0] = intel_dp->link_bw;
3209 link_config[1] = intel_dp->lane_count;
3210 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3211 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003212 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
Jani Nikula6aba5b62013-10-04 15:08:10 +03003213
3214 link_config[0] = 0;
3215 link_config[1] = DP_SET_ANSI_8B10B;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003216 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003217
3218 DP |= DP_PORT_EN;
Keith Packard1a2eb462011-11-16 16:26:07 -08003219
Jani Nikula70aff662013-09-27 15:10:44 +03003220 /* clock recovery */
3221 if (!intel_dp_reset_link_train(intel_dp, &DP,
3222 DP_TRAINING_PATTERN_1 |
3223 DP_LINK_SCRAMBLING_DISABLE)) {
3224 DRM_ERROR("failed to enable link training\n");
3225 return;
3226 }
3227
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003228 voltage = 0xff;
Keith Packardcdb0e952011-11-01 20:00:06 -07003229 voltage_tries = 0;
3230 loop_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003231 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03003232 uint8_t link_status[DP_LINK_STATUS_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003233
Daniel Vettera7c96552012-10-18 10:15:30 +02003234 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
Keith Packard93f62da2011-11-01 19:45:03 -07003235 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3236 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003237 break;
Keith Packard93f62da2011-11-01 19:45:03 -07003238 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003239
Daniel Vetter01916272012-10-18 10:15:25 +02003240 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Keith Packard93f62da2011-11-01 19:45:03 -07003241 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003242 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003243 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003244
3245 /* Check to see if we've tried the max voltage */
3246 for (i = 0; i < intel_dp->lane_count; i++)
3247 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3248 break;
Takashi Iwai3b4f8192013-03-11 18:40:16 +01003249 if (i == intel_dp->lane_count) {
Daniel Vetterb06fbda2012-10-16 09:50:25 +02003250 ++loop_tries;
3251 if (loop_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03003252 DRM_ERROR("too many full retries, give up\n");
Keith Packardcdb0e952011-11-01 20:00:06 -07003253 break;
3254 }
Jani Nikula70aff662013-09-27 15:10:44 +03003255 intel_dp_reset_link_train(intel_dp, &DP,
3256 DP_TRAINING_PATTERN_1 |
3257 DP_LINK_SCRAMBLING_DISABLE);
Keith Packardcdb0e952011-11-01 20:00:06 -07003258 voltage_tries = 0;
3259 continue;
3260 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003261
3262 /* Check to see if we've tried the same voltage 5 times */
Daniel Vetterb06fbda2012-10-16 09:50:25 +02003263 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
Chris Wilson24773672012-09-26 16:48:30 +01003264 ++voltage_tries;
Daniel Vetterb06fbda2012-10-16 09:50:25 +02003265 if (voltage_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03003266 DRM_ERROR("too many voltage retries, give up\n");
Daniel Vetterb06fbda2012-10-16 09:50:25 +02003267 break;
3268 }
3269 } else
3270 voltage_tries = 0;
3271 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003272
Jani Nikula70aff662013-09-27 15:10:44 +03003273 /* Update training set as requested by target */
3274 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3275 DRM_ERROR("failed to update link training\n");
3276 break;
3277 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003278 }
3279
Jesse Barnes33a34e42010-09-08 12:42:02 -07003280 intel_dp->DP = DP;
3281}
3282
Paulo Zanonic19b0662012-10-15 15:51:41 -03003283void
Jesse Barnes33a34e42010-09-08 12:42:02 -07003284intel_dp_complete_link_train(struct intel_dp *intel_dp)
3285{
Jesse Barnes33a34e42010-09-08 12:42:02 -07003286 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08003287 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07003288 uint32_t DP = intel_dp->DP;
Todd Previte06ea66b2014-01-20 10:19:39 -07003289 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3290
3291 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3292 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3293 training_pattern = DP_TRAINING_PATTERN_3;
Jesse Barnes33a34e42010-09-08 12:42:02 -07003294
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003295 /* channel equalization */
Jani Nikula70aff662013-09-27 15:10:44 +03003296 if (!intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07003297 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03003298 DP_LINK_SCRAMBLING_DISABLE)) {
3299 DRM_ERROR("failed to start channel equalization\n");
3300 return;
3301 }
3302
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003303 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08003304 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003305 channel_eq = false;
3306 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03003307 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08003308
Jesse Barnes37f80972011-01-05 14:45:24 -08003309 if (cr_tries > 5) {
3310 DRM_ERROR("failed to train DP, aborting\n");
Jesse Barnes37f80972011-01-05 14:45:24 -08003311 break;
3312 }
3313
Daniel Vettera7c96552012-10-18 10:15:30 +02003314 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
Jani Nikula70aff662013-09-27 15:10:44 +03003315 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3316 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003317 break;
Jani Nikula70aff662013-09-27 15:10:44 +03003318 }
Jesse Barnes869184a2010-10-07 16:01:22 -07003319
Jesse Barnes37f80972011-01-05 14:45:24 -08003320 /* Make sure clock is still ok */
Daniel Vetter01916272012-10-18 10:15:25 +02003321 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08003322 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03003323 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07003324 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03003325 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08003326 cr_tries++;
3327 continue;
3328 }
3329
Daniel Vetter1ffdff12012-10-18 10:15:24 +02003330 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003331 channel_eq = true;
3332 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003333 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003334
Jesse Barnes37f80972011-01-05 14:45:24 -08003335 /* Try 5 times, then try clock recovery if that fails */
3336 if (tries > 5) {
3337 intel_dp_link_down(intel_dp);
3338 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03003339 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07003340 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03003341 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08003342 tries = 0;
3343 cr_tries++;
3344 continue;
3345 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003346
Jani Nikula70aff662013-09-27 15:10:44 +03003347 /* Update training set as requested by target */
3348 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3349 DRM_ERROR("failed to update link training\n");
3350 break;
3351 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003352 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003353 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003354
Imre Deak3ab9c632013-05-03 12:57:41 +03003355 intel_dp_set_idle_link_train(intel_dp);
3356
3357 intel_dp->DP = DP;
3358
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003359 if (channel_eq)
Masanari Iida07f42252013-03-20 11:00:34 +09003360 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003361
Imre Deak3ab9c632013-05-03 12:57:41 +03003362}
3363
3364void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3365{
Jani Nikula70aff662013-09-27 15:10:44 +03003366 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
Imre Deak3ab9c632013-05-03 12:57:41 +03003367 DP_TRAINING_PATTERN_DISABLE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003368}
3369
3370static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01003371intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003372{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03003374 enum port port = intel_dig_port->port;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003375 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003376 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterab527ef2012-11-29 15:59:33 +01003377 struct intel_crtc *intel_crtc =
3378 to_intel_crtc(intel_dig_port->base.base.crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003379 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003380
Daniel Vetterbc76e322014-05-20 22:46:50 +02003381 if (WARN_ON(HAS_DDI(dev)))
Paulo Zanonic19b0662012-10-15 15:51:41 -03003382 return;
3383
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02003384 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
Chris Wilson1b39d6f2010-12-06 11:20:45 +00003385 return;
3386
Zhao Yakui28c97732009-10-09 11:39:41 +08003387 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003388
Imre Deakbc7d38a2013-05-16 14:40:36 +03003389 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08003390 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003391 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08003392 } else {
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003393 if (IS_CHERRYVIEW(dev))
3394 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3395 else
3396 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003397 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08003398 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01003399 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003400
Daniel Vetter493a7082012-05-30 12:31:56 +02003401 if (HAS_PCH_IBX(dev) &&
Chris Wilson1b39d6f2010-12-06 11:20:45 +00003402 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003403 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
Chris Wilson31acbcc2011-04-17 06:38:35 +01003404
Eric Anholt5bddd172010-11-18 09:32:59 +08003405 /* Hardware workaround: leaving our transcoder select
3406 * set to transcoder B while it's off will prevent the
3407 * corresponding HDMI output on transcoder A.
3408 *
3409 * Combine this with another hardware workaround:
3410 * transcoder select bit can only be cleared while the
3411 * port is enabled.
3412 */
3413 DP &= ~DP_PIPEB_SELECT;
3414 I915_WRITE(intel_dp->output_reg, DP);
3415
3416 /* Changes to enable or select take place the vblank
3417 * after being written.
3418 */
Daniel Vetterff50afe2012-11-29 15:59:34 +01003419 if (WARN_ON(crtc == NULL)) {
3420 /* We should never try to disable a port without a crtc
3421 * attached. For paranoia keep the code around for a
3422 * bit. */
Chris Wilson31acbcc2011-04-17 06:38:35 +01003423 POSTING_READ(intel_dp->output_reg);
3424 msleep(50);
3425 } else
Daniel Vetterab527ef2012-11-29 15:59:33 +01003426 intel_wait_for_vblank(dev, intel_crtc->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08003427 }
3428
Wu Fengguang832afda2011-12-09 20:42:21 +08003429 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003430 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3431 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07003432 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003433}
3434
Keith Packard26d61aa2011-07-25 20:01:09 -07003435static bool
3436intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07003437{
Rodrigo Vivia031d702013-10-03 16:15:06 -03003438 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3439 struct drm_device *dev = dig_port->base.base.dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441
Jani Nikula9d1a1032014-03-14 16:51:15 +02003442 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3443 sizeof(intel_dp->dpcd)) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003444 return false; /* aux transfer failed */
Keith Packard92fd8fd2011-07-25 19:50:10 -07003445
Andy Shevchenkoa8e98152014-09-01 14:12:01 +03003446 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
Damien Lespiau577c7a52012-12-13 16:09:02 +00003447
Adam Jacksonedb39242012-09-18 10:58:49 -04003448 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3449 return false; /* DPCD not present */
3450
Shobhit Kumar2293bb52013-07-11 18:44:56 -03003451 /* Check if the panel supports PSR */
3452 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
Jani Nikula50003932013-09-20 16:42:17 +03003453 if (is_edp(intel_dp)) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02003454 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3455 intel_dp->psr_dpcd,
3456 sizeof(intel_dp->psr_dpcd));
Rodrigo Vivia031d702013-10-03 16:15:06 -03003457 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3458 dev_priv->psr.sink_support = true;
Jani Nikula50003932013-09-20 16:42:17 +03003459 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
Rodrigo Vivia031d702013-10-03 16:15:06 -03003460 }
Jani Nikula50003932013-09-20 16:42:17 +03003461 }
3462
Todd Previte06ea66b2014-01-20 10:19:39 -07003463 /* Training Pattern 3 support */
3464 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3465 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3466 intel_dp->use_tps3 = true;
3467 DRM_DEBUG_KMS("Displayport TPS3 supported");
3468 } else
3469 intel_dp->use_tps3 = false;
3470
Adam Jacksonedb39242012-09-18 10:58:49 -04003471 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3472 DP_DWN_STRM_PORT_PRESENT))
3473 return true; /* native DP sink */
3474
3475 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3476 return true; /* no per-port downstream info */
3477
Jani Nikula9d1a1032014-03-14 16:51:15 +02003478 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3479 intel_dp->downstream_ports,
3480 DP_MAX_DOWNSTREAM_PORTS) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003481 return false; /* downstream port status fetch failed */
3482
3483 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07003484}
3485
Adam Jackson0d198322012-05-14 16:05:47 -04003486static void
3487intel_dp_probe_oui(struct intel_dp *intel_dp)
3488{
3489 u8 buf[3];
3490
3491 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3492 return;
3493
Jani Nikula24f3e092014-03-17 16:43:36 +02003494 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter351cfc32012-06-12 13:20:47 +02003495
Jani Nikula9d1a1032014-03-14 16:51:15 +02003496 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003497 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3498 buf[0], buf[1], buf[2]);
3499
Jani Nikula9d1a1032014-03-14 16:51:15 +02003500 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003501 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3502 buf[0], buf[1], buf[2]);
Daniel Vetter351cfc32012-06-12 13:20:47 +02003503
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03003504 intel_edp_panel_vdd_off(intel_dp, false);
Adam Jackson0d198322012-05-14 16:05:47 -04003505}
3506
Dave Airlie0e32b392014-05-02 14:02:48 +10003507static bool
3508intel_dp_probe_mst(struct intel_dp *intel_dp)
3509{
3510 u8 buf[1];
3511
3512 if (!intel_dp->can_mst)
3513 return false;
3514
3515 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3516 return false;
3517
Ville Syrjäläd337a342014-08-18 22:15:58 +03003518 intel_edp_panel_vdd_on(intel_dp);
Dave Airlie0e32b392014-05-02 14:02:48 +10003519 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3520 if (buf[0] & DP_MST_CAP) {
3521 DRM_DEBUG_KMS("Sink is MST capable\n");
3522 intel_dp->is_mst = true;
3523 } else {
3524 DRM_DEBUG_KMS("Sink is not MST capable\n");
3525 intel_dp->is_mst = false;
3526 }
3527 }
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03003528 intel_edp_panel_vdd_off(intel_dp, false);
Dave Airlie0e32b392014-05-02 14:02:48 +10003529
3530 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3531 return intel_dp->is_mst;
3532}
3533
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003534int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3535{
3536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3537 struct drm_device *dev = intel_dig_port->base.base.dev;
3538 struct intel_crtc *intel_crtc =
3539 to_intel_crtc(intel_dig_port->base.base.crtc);
3540 u8 buf[1];
3541
Jani Nikula9d1a1032014-03-14 16:51:15 +02003542 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003543 return -EAGAIN;
3544
3545 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3546 return -ENOTTY;
3547
Jani Nikula9d1a1032014-03-14 16:51:15 +02003548 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3549 DP_TEST_SINK_START) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003550 return -EAGAIN;
3551
3552 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3553 intel_wait_for_vblank(dev, intel_crtc->pipe);
3554 intel_wait_for_vblank(dev, intel_crtc->pipe);
3555
Jani Nikula9d1a1032014-03-14 16:51:15 +02003556 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003557 return -EAGAIN;
3558
Jani Nikula9d1a1032014-03-14 16:51:15 +02003559 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003560 return 0;
3561}
3562
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003563static bool
3564intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3565{
Jani Nikula9d1a1032014-03-14 16:51:15 +02003566 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3567 DP_DEVICE_SERVICE_IRQ_VECTOR,
3568 sink_irq_vector, 1) == 1;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003569}
3570
Dave Airlie0e32b392014-05-02 14:02:48 +10003571static bool
3572intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3573{
3574 int ret;
3575
3576 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3577 DP_SINK_COUNT_ESI,
3578 sink_irq_vector, 14);
3579 if (ret != 14)
3580 return false;
3581
3582 return true;
3583}
3584
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003585static void
3586intel_dp_handle_test_request(struct intel_dp *intel_dp)
3587{
3588 /* NAK by default */
Jani Nikula9d1a1032014-03-14 16:51:15 +02003589 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003590}
3591
Dave Airlie0e32b392014-05-02 14:02:48 +10003592static int
3593intel_dp_check_mst_status(struct intel_dp *intel_dp)
3594{
3595 bool bret;
3596
3597 if (intel_dp->is_mst) {
3598 u8 esi[16] = { 0 };
3599 int ret = 0;
3600 int retry;
3601 bool handled;
3602 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3603go_again:
3604 if (bret == true) {
3605
3606 /* check link status - esi[10] = 0x200c */
3607 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3608 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3609 intel_dp_start_link_train(intel_dp);
3610 intel_dp_complete_link_train(intel_dp);
3611 intel_dp_stop_link_train(intel_dp);
3612 }
3613
3614 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3615 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3616
3617 if (handled) {
3618 for (retry = 0; retry < 3; retry++) {
3619 int wret;
3620 wret = drm_dp_dpcd_write(&intel_dp->aux,
3621 DP_SINK_COUNT_ESI+1,
3622 &esi[1], 3);
3623 if (wret == 3) {
3624 break;
3625 }
3626 }
3627
3628 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3629 if (bret == true) {
3630 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3631 goto go_again;
3632 }
3633 } else
3634 ret = 0;
3635
3636 return ret;
3637 } else {
3638 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3639 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3640 intel_dp->is_mst = false;
3641 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3642 /* send a hotplug event */
3643 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3644 }
3645 }
3646 return -EINVAL;
3647}
3648
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003649/*
3650 * According to DP spec
3651 * 5.1.2:
3652 * 1. Read DPCD
3653 * 2. Configure link according to Receiver Capabilities
3654 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3655 * 4. Check link status on receipt of hot-plug interrupt
3656 */
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003657void
Chris Wilsonea5b2132010-08-04 13:50:23 +01003658intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003659{
Dave Airlie5b215bc2014-08-05 10:40:20 +10003660 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003661 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003662 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07003663 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003664
Dave Airlie5b215bc2014-08-05 10:40:20 +10003665 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3666
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003667 if (!intel_encoder->connectors_active)
Keith Packardd2b996a2011-07-25 22:37:51 -07003668 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07003669
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003670 if (WARN_ON(!intel_encoder->base.crtc))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003671 return;
3672
Imre Deak1a125d82014-08-18 14:42:46 +03003673 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3674 return;
3675
Keith Packard92fd8fd2011-07-25 19:50:10 -07003676 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07003677 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003678 return;
3679 }
3680
Keith Packard92fd8fd2011-07-25 19:50:10 -07003681 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07003682 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07003683 return;
3684 }
3685
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003686 /* Try to read the source of the interrupt */
3687 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3688 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3689 /* Clear interrupt source */
Jani Nikula9d1a1032014-03-14 16:51:15 +02003690 drm_dp_dpcd_writeb(&intel_dp->aux,
3691 DP_DEVICE_SERVICE_IRQ_VECTOR,
3692 sink_irq_vector);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003693
3694 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3695 intel_dp_handle_test_request(intel_dp);
3696 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3697 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3698 }
3699
Daniel Vetter1ffdff12012-10-18 10:15:24 +02003700 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07003701 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
Jani Nikula8e329a02014-06-03 14:56:21 +03003702 intel_encoder->base.name);
Jesse Barnes33a34e42010-09-08 12:42:02 -07003703 intel_dp_start_link_train(intel_dp);
3704 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03003705 intel_dp_stop_link_train(intel_dp);
Jesse Barnes33a34e42010-09-08 12:42:02 -07003706 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003707}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003708
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003709/* XXX this is probably wrong for multiple downstream ports */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003710static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07003711intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04003712{
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003713 uint8_t *dpcd = intel_dp->dpcd;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003714 uint8_t type;
3715
3716 if (!intel_dp_get_dpcd(intel_dp))
3717 return connector_status_disconnected;
3718
3719 /* if there's no downstream port, we're done */
3720 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
Keith Packard26d61aa2011-07-25 20:01:09 -07003721 return connector_status_connected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003722
3723 /* If we're HPD-aware, SINK_COUNT changes dynamically */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003724 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3725 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
Adam Jackson23235172012-09-20 16:42:45 -04003726 uint8_t reg;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003727
3728 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3729 &reg, 1) < 0)
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003730 return connector_status_unknown;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003731
Adam Jackson23235172012-09-20 16:42:45 -04003732 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3733 : connector_status_disconnected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003734 }
3735
3736 /* If no HPD, poke DDC gently */
Jani Nikula0b998362014-03-14 16:51:17 +02003737 if (drm_probe_ddc(&intel_dp->aux.ddc))
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003738 return connector_status_connected;
3739
3740 /* Well we tried, say unknown for unreliable port types */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003741 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3742 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3743 if (type == DP_DS_PORT_TYPE_VGA ||
3744 type == DP_DS_PORT_TYPE_NON_EDID)
3745 return connector_status_unknown;
3746 } else {
3747 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3748 DP_DWN_STRM_PORT_TYPE_MASK;
3749 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3750 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3751 return connector_status_unknown;
3752 }
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003753
3754 /* Anything else is out of spec, warn and ignore */
3755 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
Keith Packard26d61aa2011-07-25 20:01:09 -07003756 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04003757}
3758
3759static enum drm_connector_status
Chris Wilsond410b562014-09-02 20:03:59 +01003760edp_detect(struct intel_dp *intel_dp)
3761{
3762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3763 enum drm_connector_status status;
3764
3765 status = intel_panel_detect(dev);
3766 if (status == connector_status_unknown)
3767 status = connector_status_connected;
3768
3769 return status;
3770}
3771
3772static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003773ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003774{
Paulo Zanoni30add222012-10-26 19:05:45 -02003775 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Damien Lespiau1b469632012-12-13 16:09:01 +00003776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003778
Damien Lespiau1b469632012-12-13 16:09:01 +00003779 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3780 return connector_status_disconnected;
3781
Keith Packard26d61aa2011-07-25 20:01:09 -07003782 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003783}
3784
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003785static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003786g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003787{
Paulo Zanoni30add222012-10-26 19:05:45 -02003788 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003789 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02003790 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Chris Wilson10f76a32012-05-11 18:01:32 +01003791 uint32_t bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003792
Todd Previte232a6ee2014-01-23 00:13:41 -07003793 if (IS_VALLEYVIEW(dev)) {
3794 switch (intel_dig_port->port) {
3795 case PORT_B:
3796 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3797 break;
3798 case PORT_C:
3799 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3800 break;
3801 case PORT_D:
3802 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3803 break;
3804 default:
3805 return connector_status_unknown;
3806 }
3807 } else {
3808 switch (intel_dig_port->port) {
3809 case PORT_B:
3810 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3811 break;
3812 case PORT_C:
3813 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3814 break;
3815 case PORT_D:
3816 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3817 break;
3818 default:
3819 return connector_status_unknown;
3820 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003821 }
3822
Chris Wilson10f76a32012-05-11 18:01:32 +01003823 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003824 return connector_status_disconnected;
3825
Keith Packard26d61aa2011-07-25 20:01:09 -07003826 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003827}
3828
Keith Packard8c241fe2011-09-28 16:38:44 -07003829static struct edid *
Chris Wilsonbeb60602014-09-02 20:04:00 +01003830intel_dp_get_edid(struct intel_dp *intel_dp)
Keith Packard8c241fe2011-09-28 16:38:44 -07003831{
Chris Wilsonbeb60602014-09-02 20:04:00 +01003832 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packard8c241fe2011-09-28 16:38:44 -07003833
Jani Nikula9cd300e2012-10-19 14:51:52 +03003834 /* use cached edid if we have one */
3835 if (intel_connector->edid) {
Jani Nikula9cd300e2012-10-19 14:51:52 +03003836 /* invalid edid */
3837 if (IS_ERR(intel_connector->edid))
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003838 return NULL;
3839
Jani Nikula55e9ede2013-10-01 10:38:54 +03003840 return drm_edid_duplicate(intel_connector->edid);
Chris Wilsonbeb60602014-09-02 20:04:00 +01003841 } else
3842 return drm_get_edid(&intel_connector->base,
3843 &intel_dp->aux.ddc);
Keith Packard8c241fe2011-09-28 16:38:44 -07003844}
3845
Chris Wilsonbeb60602014-09-02 20:04:00 +01003846static void
3847intel_dp_set_edid(struct intel_dp *intel_dp)
Keith Packard8c241fe2011-09-28 16:38:44 -07003848{
Chris Wilsonbeb60602014-09-02 20:04:00 +01003849 struct intel_connector *intel_connector = intel_dp->attached_connector;
3850 struct edid *edid;
Keith Packard8c241fe2011-09-28 16:38:44 -07003851
Chris Wilsonbeb60602014-09-02 20:04:00 +01003852 edid = intel_dp_get_edid(intel_dp);
3853 intel_connector->detect_edid = edid;
Jani Nikula9cd300e2012-10-19 14:51:52 +03003854
Chris Wilsonbeb60602014-09-02 20:04:00 +01003855 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
3856 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
3857 else
3858 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3859}
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003860
Chris Wilsonbeb60602014-09-02 20:04:00 +01003861static void
3862intel_dp_unset_edid(struct intel_dp *intel_dp)
3863{
3864 struct intel_connector *intel_connector = intel_dp->attached_connector;
3865
3866 kfree(intel_connector->detect_edid);
3867 intel_connector->detect_edid = NULL;
3868
3869 intel_dp->has_audio = false;
3870}
3871
3872static enum intel_display_power_domain
3873intel_dp_power_get(struct intel_dp *dp)
3874{
3875 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3876 enum intel_display_power_domain power_domain;
3877
3878 power_domain = intel_display_port_power_domain(encoder);
3879 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
3880
3881 return power_domain;
3882}
3883
3884static void
3885intel_dp_power_put(struct intel_dp *dp,
3886 enum intel_display_power_domain power_domain)
3887{
3888 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3889 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
Keith Packard8c241fe2011-09-28 16:38:44 -07003890}
3891
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003892static enum drm_connector_status
3893intel_dp_detect(struct drm_connector *connector, bool force)
3894{
3895 struct intel_dp *intel_dp = intel_attached_dp(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -02003896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3897 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003898 struct drm_device *dev = connector->dev;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003899 enum drm_connector_status status;
Imre Deak671dedd2014-03-05 16:20:53 +02003900 enum intel_display_power_domain power_domain;
Dave Airlie0e32b392014-05-02 14:02:48 +10003901 bool ret;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003902
Chris Wilson164c8592013-07-20 20:27:08 +01003903 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03003904 connector->base.id, connector->name);
Chris Wilsonbeb60602014-09-02 20:04:00 +01003905 intel_dp_unset_edid(intel_dp);
Chris Wilson164c8592013-07-20 20:27:08 +01003906
Dave Airlie0e32b392014-05-02 14:02:48 +10003907 if (intel_dp->is_mst) {
3908 /* MST devices are disconnected from a monitor POV */
3909 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3910 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Chris Wilsonbeb60602014-09-02 20:04:00 +01003911 return connector_status_disconnected;
Dave Airlie0e32b392014-05-02 14:02:48 +10003912 }
3913
Chris Wilsonbeb60602014-09-02 20:04:00 +01003914 power_domain = intel_dp_power_get(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003915
Chris Wilsond410b562014-09-02 20:03:59 +01003916 /* Can't disconnect eDP, but you can close the lid... */
3917 if (is_edp(intel_dp))
3918 status = edp_detect(intel_dp);
3919 else if (HAS_PCH_SPLIT(dev))
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003920 status = ironlake_dp_detect(intel_dp);
3921 else
3922 status = g4x_dp_detect(intel_dp);
3923 if (status != connector_status_connected)
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003924 goto out;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003925
Adam Jackson0d198322012-05-14 16:05:47 -04003926 intel_dp_probe_oui(intel_dp);
3927
Dave Airlie0e32b392014-05-02 14:02:48 +10003928 ret = intel_dp_probe_mst(intel_dp);
3929 if (ret) {
3930 /* if we are in MST mode then this connector
3931 won't appear connected or have anything with EDID on it */
3932 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3933 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3934 status = connector_status_disconnected;
3935 goto out;
3936 }
3937
Chris Wilsonbeb60602014-09-02 20:04:00 +01003938 intel_dp_set_edid(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003939
Paulo Zanonid63885d2012-10-26 19:05:49 -02003940 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3941 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003942 status = connector_status_connected;
3943
3944out:
Chris Wilsonbeb60602014-09-02 20:04:00 +01003945 intel_dp_power_put(intel_dp, power_domain);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003946 return status;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003947}
3948
Chris Wilsonbeb60602014-09-02 20:04:00 +01003949static void
3950intel_dp_force(struct drm_connector *connector)
3951{
3952 struct intel_dp *intel_dp = intel_attached_dp(connector);
3953 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3954 enum intel_display_power_domain power_domain;
3955
3956 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3957 connector->base.id, connector->name);
3958 intel_dp_unset_edid(intel_dp);
3959
3960 if (connector->status != connector_status_connected)
3961 return;
3962
3963 power_domain = intel_dp_power_get(intel_dp);
3964
3965 intel_dp_set_edid(intel_dp);
3966
3967 intel_dp_power_put(intel_dp, power_domain);
3968
3969 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3970 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3971}
3972
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003973static int intel_dp_get_modes(struct drm_connector *connector)
3974{
Jani Nikuladd06f902012-10-19 14:51:50 +03003975 struct intel_connector *intel_connector = to_intel_connector(connector);
Chris Wilsonbeb60602014-09-02 20:04:00 +01003976 struct edid *edid;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003977
Chris Wilsonbeb60602014-09-02 20:04:00 +01003978 edid = intel_connector->detect_edid;
3979 if (edid) {
3980 int ret = intel_connector_update_modes(connector, edid);
3981 if (ret)
3982 return ret;
3983 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003984
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003985 /* if eDP has no EDID, fall back to fixed mode */
Chris Wilsonbeb60602014-09-02 20:04:00 +01003986 if (is_edp(intel_attached_dp(connector)) &&
3987 intel_connector->panel.fixed_mode) {
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003988 struct drm_display_mode *mode;
Chris Wilsonbeb60602014-09-02 20:04:00 +01003989
3990 mode = drm_mode_duplicate(connector->dev,
Jani Nikuladd06f902012-10-19 14:51:50 +03003991 intel_connector->panel.fixed_mode);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003992 if (mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003993 drm_mode_probed_add(connector, mode);
3994 return 1;
3995 }
3996 }
Chris Wilsonbeb60602014-09-02 20:04:00 +01003997
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003998 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003999}
4000
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004001static bool
4002intel_dp_detect_audio(struct drm_connector *connector)
4003{
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004004 bool has_audio = false;
Chris Wilsonbeb60602014-09-02 20:04:00 +01004005 struct edid *edid;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004006
Chris Wilsonbeb60602014-09-02 20:04:00 +01004007 edid = to_intel_connector(connector)->detect_edid;
4008 if (edid)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004009 has_audio = drm_detect_monitor_audio(edid);
Imre Deak671dedd2014-03-05 16:20:53 +02004010
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004011 return has_audio;
4012}
4013
Chris Wilsonf6849602010-09-19 09:29:33 +01004014static int
4015intel_dp_set_property(struct drm_connector *connector,
4016 struct drm_property *property,
4017 uint64_t val)
4018{
Chris Wilsone953fd72011-02-21 22:23:52 +00004019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Yuly Novikov53b41832012-10-26 12:04:00 +03004020 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004021 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4022 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonf6849602010-09-19 09:29:33 +01004023 int ret;
4024
Rob Clark662595d2012-10-11 20:36:04 -05004025 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilsonf6849602010-09-19 09:29:33 +01004026 if (ret)
4027 return ret;
4028
Chris Wilson3f43c482011-05-12 22:17:24 +01004029 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004030 int i = val;
4031 bool has_audio;
4032
4033 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01004034 return 0;
4035
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004036 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01004037
Daniel Vetterc3e5f672012-02-23 17:14:47 +01004038 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004039 has_audio = intel_dp_detect_audio(connector);
4040 else
Daniel Vetterc3e5f672012-02-23 17:14:47 +01004041 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004042
4043 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01004044 return 0;
4045
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004046 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01004047 goto done;
4048 }
4049
Chris Wilsone953fd72011-02-21 22:23:52 +00004050 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02004051 bool old_auto = intel_dp->color_range_auto;
4052 uint32_t old_range = intel_dp->color_range;
4053
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004054 switch (val) {
4055 case INTEL_BROADCAST_RGB_AUTO:
4056 intel_dp->color_range_auto = true;
4057 break;
4058 case INTEL_BROADCAST_RGB_FULL:
4059 intel_dp->color_range_auto = false;
4060 intel_dp->color_range = 0;
4061 break;
4062 case INTEL_BROADCAST_RGB_LIMITED:
4063 intel_dp->color_range_auto = false;
4064 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4065 break;
4066 default:
4067 return -EINVAL;
4068 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02004069
4070 if (old_auto == intel_dp->color_range_auto &&
4071 old_range == intel_dp->color_range)
4072 return 0;
4073
Chris Wilsone953fd72011-02-21 22:23:52 +00004074 goto done;
4075 }
4076
Yuly Novikov53b41832012-10-26 12:04:00 +03004077 if (is_edp(intel_dp) &&
4078 property == connector->dev->mode_config.scaling_mode_property) {
4079 if (val == DRM_MODE_SCALE_NONE) {
4080 DRM_DEBUG_KMS("no scaling not supported\n");
4081 return -EINVAL;
4082 }
4083
4084 if (intel_connector->panel.fitting_mode == val) {
4085 /* the eDP scaling property is not changed */
4086 return 0;
4087 }
4088 intel_connector->panel.fitting_mode = val;
4089
4090 goto done;
4091 }
4092
Chris Wilsonf6849602010-09-19 09:29:33 +01004093 return -EINVAL;
4094
4095done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00004096 if (intel_encoder->base.crtc)
4097 intel_crtc_restore_mode(intel_encoder->base.crtc);
Chris Wilsonf6849602010-09-19 09:29:33 +01004098
4099 return 0;
4100}
4101
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004102static void
Paulo Zanoni73845ad2013-06-12 17:27:30 -03004103intel_dp_connector_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004104{
Jani Nikula1d508702012-10-19 14:51:49 +03004105 struct intel_connector *intel_connector = to_intel_connector(connector);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02004106
Chris Wilsonbeb60602014-09-02 20:04:00 +01004107 intel_dp_unset_edid(intel_attached_dp(connector));
4108
Jani Nikula9cd300e2012-10-19 14:51:52 +03004109 if (!IS_ERR_OR_NULL(intel_connector->edid))
4110 kfree(intel_connector->edid);
4111
Paulo Zanoniacd8db102013-06-12 17:27:23 -03004112 /* Can't call is_edp() since the encoder may have been destroyed
4113 * already. */
4114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
Jani Nikula1d508702012-10-19 14:51:49 +03004115 intel_panel_fini(&intel_connector->panel);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02004116
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004117 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08004118 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004119}
4120
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004121void intel_dp_encoder_destroy(struct drm_encoder *encoder)
Daniel Vetter24d05922010-08-20 18:08:28 +02004122{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004123 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4124 struct intel_dp *intel_dp = &intel_dig_port->dp;
Daniel Vetterbd173812013-03-25 11:24:10 +01004125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004126 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter24d05922010-08-20 18:08:28 +02004127
Dave Airlie4f71d0c2014-06-04 16:02:28 +10004128 drm_dp_aux_unregister(&intel_dp->aux);
Dave Airlie0e32b392014-05-02 14:02:48 +10004129 intel_dp_mst_encoder_cleanup(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02004130 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07004131 if (is_edp(intel_dp)) {
4132 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004133 mutex_lock(&dev_priv->pps_mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01004134 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004135 mutex_unlock(&dev_priv->pps_mutex);
Clint Taylor01527b32014-07-07 13:01:46 -07004136 if (intel_dp->edp_notifier.notifier_call) {
4137 unregister_reboot_notifier(&intel_dp->edp_notifier);
4138 intel_dp->edp_notifier.notifier_call = NULL;
4139 }
Keith Packardbd943152011-09-18 23:09:52 -07004140 }
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004141 kfree(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02004142}
4143
Imre Deak07f9cd02014-08-18 14:42:45 +03004144static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4145{
4146 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004147 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4148 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak07f9cd02014-08-18 14:42:45 +03004149
4150 if (!is_edp(intel_dp))
4151 return;
4152
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004153 mutex_lock(&dev_priv->pps_mutex);
Imre Deak07f9cd02014-08-18 14:42:45 +03004154 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004155 mutex_unlock(&dev_priv->pps_mutex);
Imre Deak07f9cd02014-08-18 14:42:45 +03004156}
4157
Imre Deak6d93c0c2014-07-31 14:03:36 +03004158static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4159{
4160 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4161}
4162
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004163static const struct drm_connector_funcs intel_dp_connector_funcs = {
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02004164 .dpms = intel_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004165 .detect = intel_dp_detect,
Chris Wilsonbeb60602014-09-02 20:04:00 +01004166 .force = intel_dp_force,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004167 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01004168 .set_property = intel_dp_set_property,
Paulo Zanoni73845ad2013-06-12 17:27:30 -03004169 .destroy = intel_dp_connector_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004170};
4171
4172static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4173 .get_modes = intel_dp_get_modes,
4174 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01004175 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004176};
4177
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004178static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Imre Deak6d93c0c2014-07-31 14:03:36 +03004179 .reset = intel_dp_encoder_reset,
Daniel Vetter24d05922010-08-20 18:08:28 +02004180 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004181};
4182
Dave Airlie0e32b392014-05-02 14:02:48 +10004183void
Eric Anholt21d40d32010-03-25 11:11:14 -07004184intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07004185{
Dave Airlie0e32b392014-05-02 14:02:48 +10004186 return;
Keith Packardc8110e52009-05-06 11:51:10 -07004187}
4188
Dave Airlie13cf5502014-06-18 11:29:35 +10004189bool
4190intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4191{
4192 struct intel_dp *intel_dp = &intel_dig_port->dp;
Imre Deak1c767b32014-08-18 14:42:42 +03004193 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Dave Airlie0e32b392014-05-02 14:02:48 +10004194 struct drm_device *dev = intel_dig_port->base.base.dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak1c767b32014-08-18 14:42:42 +03004196 enum intel_display_power_domain power_domain;
4197 bool ret = true;
4198
Dave Airlie0e32b392014-05-02 14:02:48 +10004199 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4200 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
Dave Airlie13cf5502014-06-18 11:29:35 +10004201
Ville Syrjälä26fbb772014-08-11 18:37:37 +03004202 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4203 port_name(intel_dig_port->port),
Dave Airlie0e32b392014-05-02 14:02:48 +10004204 long_hpd ? "long" : "short");
Dave Airlie13cf5502014-06-18 11:29:35 +10004205
Imre Deak1c767b32014-08-18 14:42:42 +03004206 power_domain = intel_display_port_power_domain(intel_encoder);
4207 intel_display_power_get(dev_priv, power_domain);
4208
Dave Airlie0e32b392014-05-02 14:02:48 +10004209 if (long_hpd) {
4210 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4211 goto mst_fail;
4212
4213 if (!intel_dp_get_dpcd(intel_dp)) {
4214 goto mst_fail;
4215 }
4216
4217 intel_dp_probe_oui(intel_dp);
4218
4219 if (!intel_dp_probe_mst(intel_dp))
4220 goto mst_fail;
4221
4222 } else {
4223 if (intel_dp->is_mst) {
Imre Deak1c767b32014-08-18 14:42:42 +03004224 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
Dave Airlie0e32b392014-05-02 14:02:48 +10004225 goto mst_fail;
4226 }
4227
4228 if (!intel_dp->is_mst) {
4229 /*
4230 * we'll check the link status via the normal hot plug path later -
4231 * but for short hpds we should check it now
4232 */
Dave Airlie5b215bc2014-08-05 10:40:20 +10004233 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
Dave Airlie0e32b392014-05-02 14:02:48 +10004234 intel_dp_check_link_status(intel_dp);
Dave Airlie5b215bc2014-08-05 10:40:20 +10004235 drm_modeset_unlock(&dev->mode_config.connection_mutex);
Dave Airlie0e32b392014-05-02 14:02:48 +10004236 }
4237 }
Imre Deak1c767b32014-08-18 14:42:42 +03004238 ret = false;
4239 goto put_power;
Dave Airlie0e32b392014-05-02 14:02:48 +10004240mst_fail:
4241 /* if we were in MST mode, and device is not there get out of MST mode */
4242 if (intel_dp->is_mst) {
4243 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4244 intel_dp->is_mst = false;
4245 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4246 }
Imre Deak1c767b32014-08-18 14:42:42 +03004247put_power:
4248 intel_display_power_put(dev_priv, power_domain);
4249
4250 return ret;
Dave Airlie13cf5502014-06-18 11:29:35 +10004251}
4252
Zhenyu Wange3421a12010-04-08 09:43:27 +08004253/* Return which DP Port should be selected for Transcoder DP control */
4254int
Akshay Joshi0206e352011-08-16 15:34:10 -04004255intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08004256{
4257 struct drm_device *dev = crtc->dev;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02004258 struct intel_encoder *intel_encoder;
4259 struct intel_dp *intel_dp;
Zhenyu Wange3421a12010-04-08 09:43:27 +08004260
Paulo Zanonifa90ece2012-10-26 19:05:44 -02004261 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4262 intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004263
Paulo Zanonifa90ece2012-10-26 19:05:44 -02004264 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4265 intel_encoder->type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01004266 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08004267 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01004268
Zhenyu Wange3421a12010-04-08 09:43:27 +08004269 return -1;
4270}
4271
Zhao Yakui36e83a12010-06-12 14:32:21 +08004272/* check the VBT to see whether the eDP is on DP-D port */
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02004273bool intel_dp_is_edp(struct drm_device *dev, enum port port)
Zhao Yakui36e83a12010-06-12 14:32:21 +08004274{
4275 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03004276 union child_device_config *p_child;
Zhao Yakui36e83a12010-06-12 14:32:21 +08004277 int i;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02004278 static const short port_mapping[] = {
4279 [PORT_B] = PORT_IDPB,
4280 [PORT_C] = PORT_IDPC,
4281 [PORT_D] = PORT_IDPD,
4282 };
Zhao Yakui36e83a12010-06-12 14:32:21 +08004283
Ville Syrjälä3b32a352013-11-01 18:22:41 +02004284 if (port == PORT_A)
4285 return true;
4286
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004287 if (!dev_priv->vbt.child_dev_num)
Zhao Yakui36e83a12010-06-12 14:32:21 +08004288 return false;
4289
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004290 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4291 p_child = dev_priv->vbt.child_dev + i;
Zhao Yakui36e83a12010-06-12 14:32:21 +08004292
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02004293 if (p_child->common.dvo_port == port_mapping[port] &&
Ville Syrjäläf02586d2013-11-01 20:32:08 +02004294 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4295 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
Zhao Yakui36e83a12010-06-12 14:32:21 +08004296 return true;
4297 }
4298 return false;
4299}
4300
Dave Airlie0e32b392014-05-02 14:02:48 +10004301void
Chris Wilsonf6849602010-09-19 09:29:33 +01004302intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4303{
Yuly Novikov53b41832012-10-26 12:04:00 +03004304 struct intel_connector *intel_connector = to_intel_connector(connector);
4305
Chris Wilson3f43c482011-05-12 22:17:24 +01004306 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00004307 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004308 intel_dp->color_range_auto = true;
Yuly Novikov53b41832012-10-26 12:04:00 +03004309
4310 if (is_edp(intel_dp)) {
4311 drm_mode_create_scaling_mode_property(connector->dev);
Rob Clark6de6d842012-10-11 20:36:04 -05004312 drm_object_attach_property(
4313 &connector->base,
Yuly Novikov53b41832012-10-26 12:04:00 +03004314 connector->dev->mode_config.scaling_mode_property,
Yuly Novikov8e740cd2012-10-26 12:04:01 +03004315 DRM_MODE_SCALE_ASPECT);
4316 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
Yuly Novikov53b41832012-10-26 12:04:00 +03004317 }
Chris Wilsonf6849602010-09-19 09:29:33 +01004318}
4319
Imre Deakdada1a92014-01-29 13:25:41 +02004320static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4321{
4322 intel_dp->last_power_cycle = jiffies;
4323 intel_dp->last_power_on = jiffies;
4324 intel_dp->last_backlight_off = jiffies;
4325}
4326
Daniel Vetter67a54562012-10-20 20:57:45 +02004327static void
4328intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Jani Nikulaf30d26e2013-01-16 10:53:40 +02004329 struct intel_dp *intel_dp,
4330 struct edp_power_seq *out)
Daniel Vetter67a54562012-10-20 20:57:45 +02004331{
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333 struct edp_power_seq cur, vbt, spec, final;
4334 u32 pp_on, pp_off, pp_div, pp;
Jani Nikulabf13e812013-09-06 07:40:05 +03004335 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07004336
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004337 lockdep_assert_held(&dev_priv->pps_mutex);
4338
Jesse Barnes453c5422013-03-28 09:55:41 -07004339 if (HAS_PCH_SPLIT(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03004340 pp_ctrl_reg = PCH_PP_CONTROL;
Jesse Barnes453c5422013-03-28 09:55:41 -07004341 pp_on_reg = PCH_PP_ON_DELAYS;
4342 pp_off_reg = PCH_PP_OFF_DELAYS;
4343 pp_div_reg = PCH_PP_DIVISOR;
4344 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03004345 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4346
4347 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4348 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4349 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4350 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07004351 }
Daniel Vetter67a54562012-10-20 20:57:45 +02004352
4353 /* Workaround: Need to write PP_CONTROL with the unlock key as
4354 * the very first thing. */
Jesse Barnes453c5422013-03-28 09:55:41 -07004355 pp = ironlake_get_pp_control(intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +03004356 I915_WRITE(pp_ctrl_reg, pp);
Daniel Vetter67a54562012-10-20 20:57:45 +02004357
Jesse Barnes453c5422013-03-28 09:55:41 -07004358 pp_on = I915_READ(pp_on_reg);
4359 pp_off = I915_READ(pp_off_reg);
4360 pp_div = I915_READ(pp_div_reg);
Daniel Vetter67a54562012-10-20 20:57:45 +02004361
4362 /* Pull timing values out of registers */
4363 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4364 PANEL_POWER_UP_DELAY_SHIFT;
4365
4366 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4367 PANEL_LIGHT_ON_DELAY_SHIFT;
4368
4369 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4370 PANEL_LIGHT_OFF_DELAY_SHIFT;
4371
4372 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4373 PANEL_POWER_DOWN_DELAY_SHIFT;
4374
4375 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4376 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4377
4378 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4379 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4380
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004381 vbt = dev_priv->vbt.edp_pps;
Daniel Vetter67a54562012-10-20 20:57:45 +02004382
4383 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4384 * our hw here, which are all in 100usec. */
4385 spec.t1_t3 = 210 * 10;
4386 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4387 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4388 spec.t10 = 500 * 10;
4389 /* This one is special and actually in units of 100ms, but zero
4390 * based in the hw (so we need to add 100 ms). But the sw vbt
4391 * table multiplies it with 1000 to make it in units of 100usec,
4392 * too. */
4393 spec.t11_t12 = (510 + 100) * 10;
4394
4395 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4396 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4397
4398 /* Use the max of the register settings and vbt. If both are
4399 * unset, fall back to the spec limits. */
4400#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4401 spec.field : \
4402 max(cur.field, vbt.field))
4403 assign_final(t1_t3);
4404 assign_final(t8);
4405 assign_final(t9);
4406 assign_final(t10);
4407 assign_final(t11_t12);
4408#undef assign_final
4409
4410#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4411 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4412 intel_dp->backlight_on_delay = get_delay(t8);
4413 intel_dp->backlight_off_delay = get_delay(t9);
4414 intel_dp->panel_power_down_delay = get_delay(t10);
4415 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4416#undef get_delay
4417
Jani Nikulaf30d26e2013-01-16 10:53:40 +02004418 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4419 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4420 intel_dp->panel_power_cycle_delay);
4421
4422 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4423 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4424
4425 if (out)
4426 *out = final;
4427}
4428
4429static void
4430intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4431 struct intel_dp *intel_dp,
4432 struct edp_power_seq *seq)
4433{
4434 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07004435 u32 pp_on, pp_off, pp_div, port_sel = 0;
4436 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4437 int pp_on_reg, pp_off_reg, pp_div_reg;
Ville Syrjäläad933b52014-08-18 22:15:56 +03004438 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnes453c5422013-03-28 09:55:41 -07004439
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004440 lockdep_assert_held(&dev_priv->pps_mutex);
4441
Jesse Barnes453c5422013-03-28 09:55:41 -07004442 if (HAS_PCH_SPLIT(dev)) {
4443 pp_on_reg = PCH_PP_ON_DELAYS;
4444 pp_off_reg = PCH_PP_OFF_DELAYS;
4445 pp_div_reg = PCH_PP_DIVISOR;
4446 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03004447 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4448
4449 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4450 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4451 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07004452 }
4453
Paulo Zanonib2f19d12013-12-19 14:29:44 -02004454 /*
4455 * And finally store the new values in the power sequencer. The
4456 * backlight delays are set to 1 because we do manual waits on them. For
4457 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4458 * we'll end up waiting for the backlight off delay twice: once when we
4459 * do the manual sleep, and once when we disable the panel and wait for
4460 * the PP_STATUS bit to become zero.
4461 */
Jani Nikulaf30d26e2013-01-16 10:53:40 +02004462 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
Paulo Zanonib2f19d12013-12-19 14:29:44 -02004463 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4464 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
Jani Nikulaf30d26e2013-01-16 10:53:40 +02004465 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
Daniel Vetter67a54562012-10-20 20:57:45 +02004466 /* Compute the divisor for the pp clock, simply match the Bspec
4467 * formula. */
Jesse Barnes453c5422013-03-28 09:55:41 -07004468 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
Jani Nikulaf30d26e2013-01-16 10:53:40 +02004469 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
Daniel Vetter67a54562012-10-20 20:57:45 +02004470 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4471
4472 /* Haswell doesn't have any port selection bits for the panel
4473 * power sequencer any more. */
Imre Deakbc7d38a2013-05-16 14:40:36 +03004474 if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläad933b52014-08-18 22:15:56 +03004475 port_sel = PANEL_PORT_SELECT_VLV(port);
Imre Deakbc7d38a2013-05-16 14:40:36 +03004476 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
Ville Syrjäläad933b52014-08-18 22:15:56 +03004477 if (port == PORT_A)
Jani Nikulaa24c1442013-09-05 16:44:46 +03004478 port_sel = PANEL_PORT_SELECT_DPA;
Daniel Vetter67a54562012-10-20 20:57:45 +02004479 else
Jani Nikulaa24c1442013-09-05 16:44:46 +03004480 port_sel = PANEL_PORT_SELECT_DPD;
Daniel Vetter67a54562012-10-20 20:57:45 +02004481 }
4482
Jesse Barnes453c5422013-03-28 09:55:41 -07004483 pp_on |= port_sel;
4484
4485 I915_WRITE(pp_on_reg, pp_on);
4486 I915_WRITE(pp_off_reg, pp_off);
4487 I915_WRITE(pp_div_reg, pp_div);
Daniel Vetter67a54562012-10-20 20:57:45 +02004488
Daniel Vetter67a54562012-10-20 20:57:45 +02004489 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07004490 I915_READ(pp_on_reg),
4491 I915_READ(pp_off_reg),
4492 I915_READ(pp_div_reg));
Keith Packardc8110e52009-05-06 11:51:10 -07004493}
4494
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304495void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4496{
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 struct intel_encoder *encoder;
4499 struct intel_dp *intel_dp = NULL;
4500 struct intel_crtc_config *config = NULL;
4501 struct intel_crtc *intel_crtc = NULL;
4502 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4503 u32 reg, val;
4504 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4505
4506 if (refresh_rate <= 0) {
4507 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4508 return;
4509 }
4510
4511 if (intel_connector == NULL) {
4512 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4513 return;
4514 }
4515
Daniel Vetter1fcc9d12014-07-11 10:30:10 -07004516 /*
4517 * FIXME: This needs proper synchronization with psr state. But really
4518 * hard to tell without seeing the user of this function of this code.
4519 * Check locking and ordering once that lands.
4520 */
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304521 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4522 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4523 return;
4524 }
4525
4526 encoder = intel_attached_encoder(&intel_connector->base);
4527 intel_dp = enc_to_intel_dp(&encoder->base);
4528 intel_crtc = encoder->new_crtc;
4529
4530 if (!intel_crtc) {
4531 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4532 return;
4533 }
4534
4535 config = &intel_crtc->config;
4536
4537 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4538 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4539 return;
4540 }
4541
4542 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4543 index = DRRS_LOW_RR;
4544
4545 if (index == intel_dp->drrs_state.refresh_rate_type) {
4546 DRM_DEBUG_KMS(
4547 "DRRS requested for previously set RR...ignoring\n");
4548 return;
4549 }
4550
4551 if (!intel_crtc->active) {
4552 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4553 return;
4554 }
4555
4556 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4557 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4558 val = I915_READ(reg);
4559 if (index > DRRS_HIGH_RR) {
4560 val |= PIPECONF_EDP_RR_MODE_SWITCH;
Vandana Kannanf769cd22014-08-05 07:51:22 -07004561 intel_dp_set_m_n(intel_crtc);
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304562 } else {
4563 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4564 }
4565 I915_WRITE(reg, val);
4566 }
4567
4568 /*
4569 * mutex taken to ensure that there is no race between differnt
4570 * drrs calls trying to update refresh rate. This scenario may occur
4571 * in future when idleness detection based DRRS in kernel and
4572 * possible calls from user space to set differnt RR are made.
4573 */
4574
4575 mutex_lock(&intel_dp->drrs_state.mutex);
4576
4577 intel_dp->drrs_state.refresh_rate_type = index;
4578
4579 mutex_unlock(&intel_dp->drrs_state.mutex);
4580
4581 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4582}
4583
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304584static struct drm_display_mode *
4585intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4586 struct intel_connector *intel_connector,
4587 struct drm_display_mode *fixed_mode)
4588{
4589 struct drm_connector *connector = &intel_connector->base;
4590 struct intel_dp *intel_dp = &intel_dig_port->dp;
4591 struct drm_device *dev = intel_dig_port->base.base.dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 struct drm_display_mode *downclock_mode = NULL;
4594
4595 if (INTEL_INFO(dev)->gen <= 6) {
4596 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4597 return NULL;
4598 }
4599
4600 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
Damien Lespiau4079b8d2014-08-05 10:39:42 +01004601 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304602 return NULL;
4603 }
4604
4605 downclock_mode = intel_find_panel_downclock
4606 (dev, fixed_mode, connector);
4607
4608 if (!downclock_mode) {
Damien Lespiau4079b8d2014-08-05 10:39:42 +01004609 DRM_DEBUG_KMS("DRRS not supported\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304610 return NULL;
4611 }
4612
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304613 dev_priv->drrs.connector = intel_connector;
4614
4615 mutex_init(&intel_dp->drrs_state.mutex);
4616
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304617 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4618
4619 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
Damien Lespiau4079b8d2014-08-05 10:39:42 +01004620 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304621 return downclock_mode;
4622}
4623
Imre Deakaba86892014-07-30 15:57:31 +03004624void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4625{
4626 struct drm_device *dev = intel_encoder->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_dp *intel_dp;
4629 enum intel_display_power_domain power_domain;
4630
4631 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4632 return;
4633
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004634 mutex_lock(&dev_priv->pps_mutex);
4635
Imre Deakaba86892014-07-30 15:57:31 +03004636 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4637 if (!edp_have_panel_vdd(intel_dp))
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004638 goto out;
Imre Deakaba86892014-07-30 15:57:31 +03004639 /*
4640 * The VDD bit needs a power domain reference, so if the bit is
4641 * already enabled when we boot or resume, grab this reference and
4642 * schedule a vdd off, so we don't hold on to the reference
4643 * indefinitely.
4644 */
4645 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4646 power_domain = intel_display_port_power_domain(intel_encoder);
4647 intel_display_power_get(dev_priv, power_domain);
4648
4649 edp_panel_vdd_schedule_off(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004650 out:
4651 mutex_unlock(&dev_priv->pps_mutex);
Imre Deakaba86892014-07-30 15:57:31 +03004652}
4653
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004654static bool intel_edp_init_connector(struct intel_dp *intel_dp,
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004655 struct intel_connector *intel_connector,
4656 struct edp_power_seq *power_seq)
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004657{
4658 struct drm_connector *connector = &intel_connector->base;
4659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Paulo Zanoni63635212014-04-22 19:55:42 -03004660 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4661 struct drm_device *dev = intel_encoder->base.dev;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct drm_display_mode *fixed_mode = NULL;
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304664 struct drm_display_mode *downclock_mode = NULL;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004665 bool has_dpcd;
4666 struct drm_display_mode *scan;
4667 struct edid *edid;
4668
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304669 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4670
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004671 if (!is_edp(intel_dp))
4672 return true;
4673
Imre Deakaba86892014-07-30 15:57:31 +03004674 intel_edp_panel_vdd_sanitize(intel_encoder);
Paulo Zanoni63635212014-04-22 19:55:42 -03004675
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004676 /* Cache DPCD and EDID for edp. */
Jani Nikula24f3e092014-03-17 16:43:36 +02004677 intel_edp_panel_vdd_on(intel_dp);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004678 has_dpcd = intel_dp_get_dpcd(intel_dp);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03004679 intel_edp_panel_vdd_off(intel_dp, false);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004680
4681 if (has_dpcd) {
4682 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4683 dev_priv->no_aux_handshake =
4684 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4685 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4686 } else {
4687 /* if this fails, presume the device is a ghost */
4688 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004689 return false;
4690 }
4691
4692 /* We now know it's not a ghost, init power sequence regs. */
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004693 mutex_lock(&dev_priv->pps_mutex);
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004694 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004695 mutex_unlock(&dev_priv->pps_mutex);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004696
Daniel Vetter060c8772014-03-21 23:22:35 +01004697 mutex_lock(&dev->mode_config.mutex);
Jani Nikula0b998362014-03-14 16:51:17 +02004698 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004699 if (edid) {
4700 if (drm_add_edid_modes(connector, edid)) {
4701 drm_mode_connector_update_edid_property(connector,
4702 edid);
4703 drm_edid_to_eld(connector, edid);
4704 } else {
4705 kfree(edid);
4706 edid = ERR_PTR(-EINVAL);
4707 }
4708 } else {
4709 edid = ERR_PTR(-ENOENT);
4710 }
4711 intel_connector->edid = edid;
4712
4713 /* prefer fixed mode from EDID if available */
4714 list_for_each_entry(scan, &connector->probed_modes, head) {
4715 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4716 fixed_mode = drm_mode_duplicate(dev, scan);
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304717 downclock_mode = intel_dp_drrs_init(
4718 intel_dig_port,
4719 intel_connector, fixed_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004720 break;
4721 }
4722 }
4723
4724 /* fallback to VBT if available for eDP */
4725 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4726 fixed_mode = drm_mode_duplicate(dev,
4727 dev_priv->vbt.lfp_lvds_vbt_mode);
4728 if (fixed_mode)
4729 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4730 }
Daniel Vetter060c8772014-03-21 23:22:35 +01004731 mutex_unlock(&dev->mode_config.mutex);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004732
Clint Taylor01527b32014-07-07 13:01:46 -07004733 if (IS_VALLEYVIEW(dev)) {
4734 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4735 register_reboot_notifier(&intel_dp->edp_notifier);
4736 }
4737
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304738 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
Jani Nikula73580fb72014-08-12 17:11:41 +03004739 intel_connector->panel.backlight_power = intel_edp_backlight_power;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004740 intel_panel_setup_backlight(connector);
4741
4742 return true;
4743}
4744
Paulo Zanoni16c25532013-06-12 17:27:25 -03004745bool
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004746intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4747 struct intel_connector *intel_connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004748{
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004749 struct drm_connector *connector = &intel_connector->base;
4750 struct intel_dp *intel_dp = &intel_dig_port->dp;
4751 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4752 struct drm_device *dev = intel_encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004753 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02004754 enum port port = intel_dig_port->port;
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004755 struct edp_power_seq power_seq = { 0 };
Jani Nikula0b998362014-03-14 16:51:17 +02004756 int type;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004757
Damien Lespiauec5b01d2014-01-21 13:35:39 +00004758 /* intel_dp vfuncs */
4759 if (IS_VALLEYVIEW(dev))
4760 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4761 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4762 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4763 else if (HAS_PCH_SPLIT(dev))
4764 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4765 else
4766 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4767
Damien Lespiau153b1102014-01-21 13:37:15 +00004768 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4769
Daniel Vetter07679352012-09-06 22:15:42 +02004770 /* Preserve the current hw state. */
4771 intel_dp->DP = I915_READ(intel_dp->output_reg);
Jani Nikuladd06f902012-10-19 14:51:50 +03004772 intel_dp->attached_connector = intel_connector;
Chris Wilson3d3dc142011-02-12 10:33:12 +00004773
Ville Syrjälä3b32a352013-11-01 18:22:41 +02004774 if (intel_dp_is_edp(dev, port))
Gajanan Bhat19c03922012-09-27 19:13:07 +05304775 type = DRM_MODE_CONNECTOR_eDP;
Ville Syrjälä3b32a352013-11-01 18:22:41 +02004776 else
4777 type = DRM_MODE_CONNECTOR_DisplayPort;
Adam Jacksonb3295302010-07-16 14:46:28 -04004778
Imre Deakf7d24902013-05-08 13:14:05 +03004779 /*
4780 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4781 * for DP the encoder type can be set by the caller to
4782 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4783 */
4784 if (type == DRM_MODE_CONNECTOR_eDP)
4785 intel_encoder->type = INTEL_OUTPUT_EDP;
4786
Imre Deake7281ea2013-05-08 13:14:08 +03004787 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4788 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4789 port_name(port));
4790
Adam Jacksonb3295302010-07-16 14:46:28 -04004791 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004792 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4793
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004794 connector->interlace_allowed = true;
4795 connector->doublescan_allowed = 0;
Ma Lingf8aed702009-08-24 13:50:24 +08004796
Daniel Vetter66a92782012-07-12 20:08:18 +02004797 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
Daniel Vetter4be73782014-01-17 14:39:48 +01004798 edp_panel_vdd_work);
Zhenyu Wang6251ec02010-01-12 05:38:32 +08004799
Chris Wilsondf0e9242010-09-09 16:20:55 +01004800 intel_connector_attach_encoder(intel_connector, intel_encoder);
Thomas Wood34ea3d32014-05-29 16:57:41 +01004801 drm_connector_register(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004802
Paulo Zanoniaffa9352012-11-23 15:30:39 -02004803 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02004804 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4805 else
4806 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak80f65de2014-02-11 17:12:49 +02004807 intel_connector->unregister = intel_dp_connector_unregister;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02004808
Jani Nikula0b998362014-03-14 16:51:17 +02004809 /* Set up the hotplug pin. */
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004810 switch (port) {
4811 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05004812 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004813 break;
4814 case PORT_B:
Egbert Eich1d843f92013-02-25 12:06:49 -05004815 intel_encoder->hpd_pin = HPD_PORT_B;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004816 break;
4817 case PORT_C:
Egbert Eich1d843f92013-02-25 12:06:49 -05004818 intel_encoder->hpd_pin = HPD_PORT_C;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004819 break;
4820 case PORT_D:
Egbert Eich1d843f92013-02-25 12:06:49 -05004821 intel_encoder->hpd_pin = HPD_PORT_D;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004822 break;
4823 default:
Damien Lespiauad1c0b12013-03-07 15:30:28 +00004824 BUG();
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004825 }
4826
Imre Deakdada1a92014-01-29 13:25:41 +02004827 if (is_edp(intel_dp)) {
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004828 mutex_lock(&dev_priv->pps_mutex);
Imre Deakdada1a92014-01-29 13:25:41 +02004829 intel_dp_init_panel_power_timestamps(intel_dp);
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004830 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004831 mutex_unlock(&dev_priv->pps_mutex);
Imre Deakdada1a92014-01-29 13:25:41 +02004832 }
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004833
Jani Nikula9d1a1032014-03-14 16:51:15 +02004834 intel_dp_aux_init(intel_dp, intel_connector);
Dave Airliec1f05262012-08-30 11:06:18 +10004835
Dave Airlie0e32b392014-05-02 14:02:48 +10004836 /* init MST on ports that can support it */
4837 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4838 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4839 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4840 }
4841 }
4842
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004843 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
Dave Airlie4f71d0c2014-06-04 16:02:28 +10004844 drm_dp_aux_unregister(&intel_dp->aux);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004845 if (is_edp(intel_dp)) {
4846 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004847 mutex_lock(&dev_priv->pps_mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01004848 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03004849 mutex_unlock(&dev_priv->pps_mutex);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004850 }
Thomas Wood34ea3d32014-05-29 16:57:41 +01004851 drm_connector_unregister(connector);
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004852 drm_connector_cleanup(connector);
Paulo Zanoni16c25532013-06-12 17:27:25 -03004853 return false;
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004854 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004855
Chris Wilsonf6849602010-09-19 09:29:33 +01004856 intel_dp_add_properties(intel_dp, connector);
4857
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004858 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4859 * 0xd. Failure to do so will result in spurious interrupts being
4860 * generated on the port when a cable is not attached.
4861 */
4862 if (IS_G4X(dev) && !IS_GM45(dev)) {
4863 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4864 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4865 }
Paulo Zanoni16c25532013-06-12 17:27:25 -03004866
4867 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004868}
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004869
4870void
4871intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4872{
Dave Airlie13cf5502014-06-18 11:29:35 +10004873 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004874 struct intel_digital_port *intel_dig_port;
4875 struct intel_encoder *intel_encoder;
4876 struct drm_encoder *encoder;
4877 struct intel_connector *intel_connector;
4878
Daniel Vetterb14c5672013-09-19 12:18:32 +02004879 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004880 if (!intel_dig_port)
4881 return;
4882
Daniel Vetterb14c5672013-09-19 12:18:32 +02004883 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004884 if (!intel_connector) {
4885 kfree(intel_dig_port);
4886 return;
4887 }
4888
4889 intel_encoder = &intel_dig_port->base;
4890 encoder = &intel_encoder->base;
4891
4892 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4893 DRM_MODE_ENCODER_TMDS);
4894
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004895 intel_encoder->compute_config = intel_dp_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004896 intel_encoder->disable = intel_disable_dp;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004897 intel_encoder->get_hw_state = intel_dp_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07004898 intel_encoder->get_config = intel_dp_get_config;
Imre Deak07f9cd02014-08-18 14:42:45 +03004899 intel_encoder->suspend = intel_dp_encoder_suspend;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03004900 if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä9197c882014-04-09 13:29:05 +03004901 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03004902 intel_encoder->pre_enable = chv_pre_enable_dp;
4903 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä580d3812014-04-09 13:29:00 +03004904 intel_encoder->post_disable = chv_post_disable_dp;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03004905 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004906 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004907 intel_encoder->pre_enable = vlv_pre_enable_dp;
4908 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004909 intel_encoder->post_disable = vlv_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004910 } else {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004911 intel_encoder->pre_enable = g4x_pre_enable_dp;
4912 intel_encoder->enable = g4x_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004913 intel_encoder->post_disable = g4x_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004914 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004915
Paulo Zanoni174edf12012-10-26 19:05:50 -02004916 intel_dig_port->port = port;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004917 intel_dig_port->dp.output_reg = output_reg;
4918
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004919 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Ville Syrjälä882ec382014-04-28 14:07:43 +03004920 if (IS_CHERRYVIEW(dev)) {
4921 if (port == PORT_D)
4922 intel_encoder->crtc_mask = 1 << 2;
4923 else
4924 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4925 } else {
4926 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4927 }
Ville Syrjäläbc079e82014-03-03 16:15:28 +02004928 intel_encoder->cloneable = 0;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004929 intel_encoder->hot_plug = intel_dp_hot_plug;
4930
Dave Airlie13cf5502014-06-18 11:29:35 +10004931 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4932 dev_priv->hpd_irq_port[port] = intel_dig_port;
4933
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004934 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4935 drm_encoder_cleanup(encoder);
4936 kfree(intel_dig_port);
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004937 kfree(intel_connector);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004938 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004939}
Dave Airlie0e32b392014-05-02 14:02:48 +10004940
4941void intel_dp_mst_suspend(struct drm_device *dev)
4942{
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 int i;
4945
4946 /* disable MST */
4947 for (i = 0; i < I915_MAX_PORTS; i++) {
4948 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4949 if (!intel_dig_port)
4950 continue;
4951
4952 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4953 if (!intel_dig_port->dp.can_mst)
4954 continue;
4955 if (intel_dig_port->dp.is_mst)
4956 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4957 }
4958 }
4959}
4960
4961void intel_dp_mst_resume(struct drm_device *dev)
4962{
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 int i;
4965
4966 for (i = 0; i < I915_MAX_PORTS; i++) {
4967 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4968 if (!intel_dig_port)
4969 continue;
4970 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4971 int ret;
4972
4973 if (!intel_dig_port->dp.can_mst)
4974 continue;
4975
4976 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4977 if (ret != 0) {
4978 intel_dp_check_mst_status(&intel_dig_port->dp);
4979 }
4980 }
4981 }
4982}