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gerrit-public.fairphone.software / kernel / msm-4.9 / 599119f683e623ff2517c318ac20655e8c135574 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu_core.c
blob: d97de86d88df8a13248cd659680abcbe32c00fd2 [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
Jes Sorenseneb188062016-04-14 16:37:14 -0400[diff] [blame]4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]45int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
Jes Sorensenb001e082016-02-29 17:04:02 -0500[diff] [blame]57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]95 .hw_value = 1, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]97 .hw_value = 2, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]99 .hw_value = 3, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]101 .hw_value = 4, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]103 .hw_value = 5, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]105 .hw_value = 6, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]107 .hw_value = 7, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]109 .hw_value = 8, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]111 .hw_value = 9, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]113 .hw_value = 10, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]115 .hw_value = 11, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]117 .hw_value = 12, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]119 .hw_value = 13, .max_power = 30 },
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
Jes Sorensen8db71452016-04-18 11:49:33 -0400[diff] [blame]131static struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
Jes Sorensenb7dd8ff2016-02-29 17:04:17 -0500[diff] [blame]156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
Arnd Bergmann06d05462016-04-18 23:59:31 +0200[diff] [blame]187#ifdef CONFIG_RTL8XXXU_UNTESTED
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]188static struct rtl8xxxu_power_base rtl8188r_power_base = {
189 .reg_0e00 = 0x06080808,
190 .reg_0e04 = 0x00040406,
191 .reg_0e08 = 0x00000000,
192 .reg_086c = 0x00000000,
193
194 .reg_0e10 = 0x04060608,
195 .reg_0e14 = 0x00020204,
196 .reg_0e18 = 0x04060608,
197 .reg_0e1c = 0x00020204,
198
199 .reg_0830 = 0x06080808,
200 .reg_0834 = 0x00040406,
201 .reg_0838 = 0x00000000,
202 .reg_086c_2 = 0x00000000,
203
204 .reg_083c = 0x04060608,
205 .reg_0848 = 0x00020204,
206 .reg_084c = 0x04060608,
207 .reg_0868 = 0x00020204,
208};
209
210static struct rtl8xxxu_power_base rtl8192c_power_base = {
211 .reg_0e00 = 0x07090c0c,
212 .reg_0e04 = 0x01020405,
213 .reg_0e08 = 0x00000000,
214 .reg_086c = 0x00000000,
215
216 .reg_0e10 = 0x0b0c0c0e,
217 .reg_0e14 = 0x01030506,
218 .reg_0e18 = 0x0b0c0d0e,
219 .reg_0e1c = 0x01030509,
220
221 .reg_0830 = 0x07090c0c,
222 .reg_0834 = 0x01020405,
223 .reg_0838 = 0x00000000,
224 .reg_086c_2 = 0x00000000,
225
226 .reg_083c = 0x0b0c0d0e,
227 .reg_0848 = 0x01030509,
228 .reg_084c = 0x0b0c0d0e,
229 .reg_0868 = 0x01030509,
230};
Arnd Bergmann06d05462016-04-18 23:59:31 +0200[diff] [blame]231#endif
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]232
233static struct rtl8xxxu_power_base rtl8723a_power_base = {
234 .reg_0e00 = 0x0a0c0c0c,
235 .reg_0e04 = 0x02040608,
236 .reg_0e08 = 0x00000000,
237 .reg_086c = 0x00000000,
238
239 .reg_0e10 = 0x0a0c0d0e,
240 .reg_0e14 = 0x02040608,
241 .reg_0e18 = 0x0a0c0d0e,
242 .reg_0e1c = 0x02040608,
243
244 .reg_0830 = 0x0a0c0c0c,
245 .reg_0834 = 0x02040608,
246 .reg_0838 = 0x00000000,
247 .reg_086c_2 = 0x00000000,
248
249 .reg_083c = 0x0a0c0d0e,
250 .reg_0848 = 0x02040608,
251 .reg_084c = 0x0a0c0d0e,
252 .reg_0868 = 0x02040608,
253};
254
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]255static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
256 {0x800, 0x80040000}, {0x804, 0x00000003},
257 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
258 {0x810, 0x10001331}, {0x814, 0x020c3d10},
259 {0x818, 0x02200385}, {0x81c, 0x00000000},
260 {0x820, 0x01000100}, {0x824, 0x00390004},
261 {0x828, 0x00000000}, {0x82c, 0x00000000},
262 {0x830, 0x00000000}, {0x834, 0x00000000},
263 {0x838, 0x00000000}, {0x83c, 0x00000000},
264 {0x840, 0x00010000}, {0x844, 0x00000000},
265 {0x848, 0x00000000}, {0x84c, 0x00000000},
266 {0x850, 0x00000000}, {0x854, 0x00000000},
267 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
268 {0x860, 0x66f60110}, {0x864, 0x061f0130},
269 {0x868, 0x00000000}, {0x86c, 0x32323200},
270 {0x870, 0x07000760}, {0x874, 0x22004000},
271 {0x878, 0x00000808}, {0x87c, 0x00000000},
272 {0x880, 0xc0083070}, {0x884, 0x000004d5},
273 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
274 {0x890, 0x00000800}, {0x894, 0xfffffffe},
275 {0x898, 0x40302010}, {0x89c, 0x00706050},
276 {0x900, 0x00000000}, {0x904, 0x00000023},
277 {0x908, 0x00000000}, {0x90c, 0x81121111},
278 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
279 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
280 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
281 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
282 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
283 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
284 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
285 {0xa78, 0x00000900},
286 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
287 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
288 {0xc10, 0x08800000}, {0xc14, 0x40000100},
289 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
290 {0xc20, 0x00000000}, {0xc24, 0x00000000},
291 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
292 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
293 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
294 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
295 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
296 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
297 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
298 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
299 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
300 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
301 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
302 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
303 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
304 {0xc90, 0x00121820}, {0xc94, 0x00000000},
305 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
306 {0xca0, 0x00000000}, {0xca4, 0x00000080},
307 {0xca8, 0x00000000}, {0xcac, 0x00000000},
308 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
309 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
310 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
311 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
312 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
313 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
314 {0xce0, 0x00222222}, {0xce4, 0x00000000},
315 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
316 {0xd00, 0x00080740}, {0xd04, 0x00020401},
317 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
318 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
319 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
320 {0xd30, 0x00000000}, {0xd34, 0x80608000},
321 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
322 {0xd40, 0x00000000}, {0xd44, 0x00000000},
323 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
324 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
325 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
326 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
327 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
328 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
329 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
330 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
331 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
332 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
333 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
334 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
335 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
336 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
337 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
338 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
339 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
340 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
341 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
342 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
343 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
344 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
345 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
346 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
347 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
348 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
349 {0xf00, 0x00000300},
350 {0xffff, 0xffffffff},
351};
352
Jes Sorensen36c32582016-02-29 17:04:14 -0500[diff] [blame]353static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
354 {0x800, 0x80040000}, {0x804, 0x00000003},
355 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
356 {0x810, 0x10001331}, {0x814, 0x020c3d10},
357 {0x818, 0x02200385}, {0x81c, 0x00000000},
358 {0x820, 0x01000100}, {0x824, 0x00190204},
359 {0x828, 0x00000000}, {0x82c, 0x00000000},
360 {0x830, 0x00000000}, {0x834, 0x00000000},
361 {0x838, 0x00000000}, {0x83c, 0x00000000},
362 {0x840, 0x00010000}, {0x844, 0x00000000},
363 {0x848, 0x00000000}, {0x84c, 0x00000000},
364 {0x850, 0x00000000}, {0x854, 0x00000000},
365 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
366 {0x860, 0x66f60110}, {0x864, 0x061f0649},
367 {0x868, 0x00000000}, {0x86c, 0x27272700},
368 {0x870, 0x07000760}, {0x874, 0x25004000},
369 {0x878, 0x00000808}, {0x87c, 0x00000000},
370 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
371 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
372 {0x890, 0x00000800}, {0x894, 0xfffffffe},
373 {0x898, 0x40302010}, {0x89c, 0x00706050},
374 {0x900, 0x00000000}, {0x904, 0x00000023},
375 {0x908, 0x00000000}, {0x90c, 0x81121111},
376 {0x910, 0x00000002}, {0x914, 0x00000201},
377 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
378 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
379 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
380 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
381 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
382 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
383 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
384 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
385 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
386 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
387 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
388 {0xc10, 0x08800000}, {0xc14, 0x40000100},
389 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
390 {0xc20, 0x00000000}, {0xc24, 0x00000000},
391 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
392 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
393 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
394 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
395 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
396 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
397 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
398 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
399 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
400 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
401 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
402 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
403 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
404 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
405 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
406 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
407 {0xca8, 0x00000000}, {0xcac, 0x00000000},
408 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
409 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
410 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
411 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
412 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
413 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
414 {0xce0, 0x00222222}, {0xce4, 0x00000000},
415 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
416 {0xd00, 0x00000740}, {0xd04, 0x40020401},
417 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
418 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
419 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
420 {0xd30, 0x00000000}, {0xd34, 0x80608000},
421 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
422 {0xd40, 0x00000000}, {0xd44, 0x00000000},
423 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
424 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
425 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
426 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
427 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
428 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
429 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
430 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
431 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
432 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
433 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
434 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
435 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
436 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
437 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
438 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
439 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
440 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
441 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
442 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
443 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
444 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
445 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
446 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
447 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
448 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
449 {0xf00, 0x00000300},
450 {0x820, 0x01000100}, {0x800, 0x83040000},
451 {0xffff, 0xffffffff},
452};
453
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]454static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
455 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
456 {0x800, 0x80040002}, {0x804, 0x00000003},
457 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
458 {0x810, 0x10000330}, {0x814, 0x020c3d10},
459 {0x818, 0x02200385}, {0x81c, 0x00000000},
460 {0x820, 0x01000100}, {0x824, 0x00390004},
461 {0x828, 0x01000100}, {0x82c, 0x00390004},
462 {0x830, 0x27272727}, {0x834, 0x27272727},
463 {0x838, 0x27272727}, {0x83c, 0x27272727},
464 {0x840, 0x00010000}, {0x844, 0x00010000},
465 {0x848, 0x27272727}, {0x84c, 0x27272727},
466 {0x850, 0x00000000}, {0x854, 0x00000000},
467 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
468 {0x860, 0x66e60230}, {0x864, 0x061f0130},
469 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
470 {0x870, 0x07000700}, {0x874, 0x22184000},
471 {0x878, 0x08080808}, {0x87c, 0x00000000},
472 {0x880, 0xc0083070}, {0x884, 0x000004d5},
473 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
474 {0x890, 0x00000800}, {0x894, 0xfffffffe},
475 {0x898, 0x40302010}, {0x89c, 0x00706050},
476 {0x900, 0x00000000}, {0x904, 0x00000023},
477 {0x908, 0x00000000}, {0x90c, 0x81121313},
478 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
479 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
480 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
481 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
482 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
483 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
484 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
485 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
486 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
487 {0xc10, 0x08800000}, {0xc14, 0x40000100},
488 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
489 {0xc20, 0x00000000}, {0xc24, 0x00000000},
490 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
491 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
492 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
493 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
494 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
495 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
496 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
497 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
498 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
499 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
500 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
501 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
502 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
503 {0xc90, 0x00121820}, {0xc94, 0x00000000},
504 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
505 {0xca0, 0x00000000}, {0xca4, 0x00000080},
506 {0xca8, 0x00000000}, {0xcac, 0x00000000},
507 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
508 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
509 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
510 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
511 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
512 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
513 {0xce0, 0x00222222}, {0xce4, 0x00000000},
514 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
515 {0xd00, 0x00080740}, {0xd04, 0x00020403},
516 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
517 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
518 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
519 {0xd30, 0x00000000}, {0xd34, 0x80608000},
520 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
521 {0xd40, 0x00000000}, {0xd44, 0x00000000},
522 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
523 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
524 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
525 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
526 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
527 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
528 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
529 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
530 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
531 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
532 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
533 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
534 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
535 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
536 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
537 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
538 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
539 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
540 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
541 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
542 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
543 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
544 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
545 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
546 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
547 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
548 {0xf00, 0x00000300},
549 {0xffff, 0xffffffff},
550};
551
552static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
553 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
554 {0x040, 0x000c0004}, {0x800, 0x80040000},
555 {0x804, 0x00000001}, {0x808, 0x0000fc00},
556 {0x80c, 0x0000000a}, {0x810, 0x10005388},
557 {0x814, 0x020c3d10}, {0x818, 0x02200385},
558 {0x81c, 0x00000000}, {0x820, 0x01000100},
559 {0x824, 0x00390204}, {0x828, 0x00000000},
560 {0x82c, 0x00000000}, {0x830, 0x00000000},
561 {0x834, 0x00000000}, {0x838, 0x00000000},
562 {0x83c, 0x00000000}, {0x840, 0x00010000},
563 {0x844, 0x00000000}, {0x848, 0x00000000},
564 {0x84c, 0x00000000}, {0x850, 0x00000000},
565 {0x854, 0x00000000}, {0x858, 0x569a569a},
566 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
567 {0x864, 0x061f0130}, {0x868, 0x00000000},
568 {0x86c, 0x20202000}, {0x870, 0x03000300},
569 {0x874, 0x22004000}, {0x878, 0x00000808},
570 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
571 {0x884, 0x000004d5}, {0x888, 0x00000000},
572 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
573 {0x894, 0xfffffffe}, {0x898, 0x40302010},
574 {0x89c, 0x00706050}, {0x900, 0x00000000},
575 {0x904, 0x00000023}, {0x908, 0x00000000},
576 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
577 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
578 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
579 {0xa14, 0x11144028}, {0xa18, 0x00881117},
580 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
581 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
582 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
583 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
584 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
585 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
586 {0xc14, 0x40000100}, {0xc18, 0x08800000},
587 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
588 {0xc24, 0x00000000}, {0xc28, 0x00000000},
589 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
590 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
591 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
592 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
593 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
594 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
595 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
596 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
597 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
598 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
599 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
600 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
601 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
602 {0xc94, 0x00000000}, {0xc98, 0x00121820},
603 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
604 {0xca4, 0x00000080}, {0xca8, 0x00000000},
605 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
606 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
607 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
608 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
609 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
610 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
611 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
612 {0xce4, 0x00000000}, {0xce8, 0x37644302},
613 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
614 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
615 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
616 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
617 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
618 {0xd34, 0x80608000}, {0xd38, 0x00000000},
619 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
620 {0xd44, 0x00000000}, {0xd48, 0x00000000},
621 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
622 {0xd54, 0x00000000}, {0xd58, 0x00000000},
623 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
624 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
625 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
626 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
627 {0xe00, 0x24242424}, {0xe04, 0x24242424},
628 {0xe08, 0x03902024}, {0xe10, 0x24242424},
629 {0xe14, 0x24242424}, {0xe18, 0x24242424},
630 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
631 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
632 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
633 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
634 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
635 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
636 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
637 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
638 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
639 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
640 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
641 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
642 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
643 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
644 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
645 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
646 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
647 {0xf00, 0x00000300},
648 {0xffff, 0xffffffff},
649};
650
651static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
652 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
653 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
654 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
655 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
656 {0xc78, 0x78080001}, {0xc78, 0x77090001},
657 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
658 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
659 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
660 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
661 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
662 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
663 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
664 {0xc78, 0x68180001}, {0xc78, 0x67190001},
665 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
666 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
667 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
668 {0xc78, 0x60200001}, {0xc78, 0x49210001},
669 {0xc78, 0x48220001}, {0xc78, 0x47230001},
670 {0xc78, 0x46240001}, {0xc78, 0x45250001},
671 {0xc78, 0x44260001}, {0xc78, 0x43270001},
672 {0xc78, 0x42280001}, {0xc78, 0x41290001},
673 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
674 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
675 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
676 {0xc78, 0x21300001}, {0xc78, 0x20310001},
677 {0xc78, 0x06320001}, {0xc78, 0x05330001},
678 {0xc78, 0x04340001}, {0xc78, 0x03350001},
679 {0xc78, 0x02360001}, {0xc78, 0x01370001},
680 {0xc78, 0x00380001}, {0xc78, 0x00390001},
681 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
682 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
683 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
684 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
685 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
686 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
687 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
688 {0xc78, 0x78480001}, {0xc78, 0x77490001},
689 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
690 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
691 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
692 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
693 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
694 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
695 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
696 {0xc78, 0x68580001}, {0xc78, 0x67590001},
697 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
698 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
699 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
700 {0xc78, 0x60600001}, {0xc78, 0x49610001},
701 {0xc78, 0x48620001}, {0xc78, 0x47630001},
702 {0xc78, 0x46640001}, {0xc78, 0x45650001},
703 {0xc78, 0x44660001}, {0xc78, 0x43670001},
704 {0xc78, 0x42680001}, {0xc78, 0x41690001},
705 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
706 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
707 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
708 {0xc78, 0x21700001}, {0xc78, 0x20710001},
709 {0xc78, 0x06720001}, {0xc78, 0x05730001},
710 {0xc78, 0x04740001}, {0xc78, 0x03750001},
711 {0xc78, 0x02760001}, {0xc78, 0x01770001},
712 {0xc78, 0x00780001}, {0xc78, 0x00790001},
713 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
714 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
715 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
716 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
717 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
718 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
719 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
720 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
721 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
722 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
723 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
724 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
725 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
726 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
727 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
728 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
729 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
730 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
731 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
732 {0xffff, 0xffffffff}
733};
734
735static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
736 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
737 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
738 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
739 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
740 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
741 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
742 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
743 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
744 {0xc78, 0x73100001}, {0xc78, 0x72110001},
745 {0xc78, 0x71120001}, {0xc78, 0x70130001},
746 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
747 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
748 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
749 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
750 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
751 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
752 {0xc78, 0x63200001}, {0xc78, 0x62210001},
753 {0xc78, 0x61220001}, {0xc78, 0x60230001},
754 {0xc78, 0x46240001}, {0xc78, 0x45250001},
755 {0xc78, 0x44260001}, {0xc78, 0x43270001},
756 {0xc78, 0x42280001}, {0xc78, 0x41290001},
757 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
758 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
759 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
760 {0xc78, 0x21300001}, {0xc78, 0x20310001},
761 {0xc78, 0x06320001}, {0xc78, 0x05330001},
762 {0xc78, 0x04340001}, {0xc78, 0x03350001},
763 {0xc78, 0x02360001}, {0xc78, 0x01370001},
764 {0xc78, 0x00380001}, {0xc78, 0x00390001},
765 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
766 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
767 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
768 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
769 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
770 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
771 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
772 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
773 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
774 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
775 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
776 {0xc78, 0x73500001}, {0xc78, 0x72510001},
777 {0xc78, 0x71520001}, {0xc78, 0x70530001},
778 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
779 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
780 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
781 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
782 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
783 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
784 {0xc78, 0x63600001}, {0xc78, 0x62610001},
785 {0xc78, 0x61620001}, {0xc78, 0x60630001},
786 {0xc78, 0x46640001}, {0xc78, 0x45650001},
787 {0xc78, 0x44660001}, {0xc78, 0x43670001},
788 {0xc78, 0x42680001}, {0xc78, 0x41690001},
789 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
790 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
791 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
792 {0xc78, 0x21700001}, {0xc78, 0x20710001},
793 {0xc78, 0x06720001}, {0xc78, 0x05730001},
794 {0xc78, 0x04740001}, {0xc78, 0x03750001},
795 {0xc78, 0x02760001}, {0xc78, 0x01770001},
796 {0xc78, 0x00780001}, {0xc78, 0x00790001},
797 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
798 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
799 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
800 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
801 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
802 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
803 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
804 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
805 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
806 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
807 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
808 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
809 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
810 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
811 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
812 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
813 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
814 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
815 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
816 {0xffff, 0xffffffff}
817};
818
Jes Sorensenb9f498e2016-02-29 17:04:18 -0500[diff] [blame]819static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
820 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
821 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
822 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
823 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
824 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
825 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
826 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
827 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
828 {0xc78, 0xed100001}, {0xc78, 0xec110001},
829 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
830 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
831 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
832 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
833 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
834 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
835 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
836 {0xc78, 0x65200001}, {0xc78, 0x64210001},
837 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
838 {0xc78, 0x49240001}, {0xc78, 0x48250001},
839 {0xc78, 0x47260001}, {0xc78, 0x46270001},
840 {0xc78, 0x45280001}, {0xc78, 0x44290001},
841 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
842 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
843 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
844 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
845 {0xc78, 0x08320001}, {0xc78, 0x07330001},
846 {0xc78, 0x06340001}, {0xc78, 0x05350001},
847 {0xc78, 0x04360001}, {0xc78, 0x03370001},
848 {0xc78, 0x02380001}, {0xc78, 0x01390001},
849 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
850 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
851 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
852 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
853 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
854 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
855 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
856 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
857 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
858 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
859 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
860 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
861 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
862 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
863 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
864 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
865 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
866 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
867 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
868 {0xc78, 0x65600001}, {0xc78, 0x64610001},
869 {0xc78, 0x63620001}, {0xc78, 0x62630001},
870 {0xc78, 0x61640001}, {0xc78, 0x48650001},
871 {0xc78, 0x47660001}, {0xc78, 0x46670001},
872 {0xc78, 0x45680001}, {0xc78, 0x44690001},
873 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
874 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
875 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
876 {0xc78, 0x24700001}, {0xc78, 0x09710001},
877 {0xc78, 0x08720001}, {0xc78, 0x07730001},
878 {0xc78, 0x06740001}, {0xc78, 0x05750001},
879 {0xc78, 0x04760001}, {0xc78, 0x03770001},
880 {0xc78, 0x02780001}, {0xc78, 0x01790001},
881 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
882 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
883 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
884 {0xc50, 0x69553422},
885 {0xc50, 0x69553420},
886 {0x824, 0x00390204},
887 {0xffff, 0xffffffff}
888};
889
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]890static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
891 {0x00, 0x00030159}, {0x01, 0x00031284},
892 {0x02, 0x00098000}, {0x03, 0x00039c63},
893 {0x04, 0x000210e7}, {0x09, 0x0002044f},
894 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
895 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
896 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
897 {0x19, 0x00000000}, {0x1a, 0x00030355},
898 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
899 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
900 {0x1f, 0x00000000}, {0x20, 0x0000b614},
901 {0x21, 0x0006c000}, {0x22, 0x00000000},
902 {0x23, 0x00001558}, {0x24, 0x00000060},
903 {0x25, 0x00000483}, {0x26, 0x0004f000},
904 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
905 {0x29, 0x00004783}, {0x2a, 0x00000001},
906 {0x2b, 0x00021334}, {0x2a, 0x00000000},
907 {0x2b, 0x00000054}, {0x2a, 0x00000001},
908 {0x2b, 0x00000808}, {0x2b, 0x00053333},
909 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
910 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
911 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
912 {0x2b, 0x00000808}, {0x2b, 0x00063333},
913 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
914 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
915 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
916 {0x2b, 0x00000808}, {0x2b, 0x00073333},
917 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
918 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
919 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
920 {0x2b, 0x00000709}, {0x2b, 0x00063333},
921 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
922 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
923 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
924 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
925 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
926 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
927 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
928 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
929 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
930 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
931 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
932 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
933 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
934 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
935 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
936 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
937 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
938 {0x10, 0x0002000f}, {0x11, 0x000203f9},
939 {0x10, 0x0003000f}, {0x11, 0x000ff500},
940 {0x10, 0x00000000}, {0x11, 0x00000000},
941 {0x10, 0x0008000f}, {0x11, 0x0003f100},
942 {0x10, 0x0009000f}, {0x11, 0x00023100},
943 {0x12, 0x00032000}, {0x12, 0x00071000},
944 {0x12, 0x000b0000}, {0x12, 0x000fc000},
945 {0x13, 0x000287b3}, {0x13, 0x000244b7},
946 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
947 {0x13, 0x00018493}, {0x13, 0x0001429b},
948 {0x13, 0x00010299}, {0x13, 0x0000c29c},
949 {0x13, 0x000081a0}, {0x13, 0x000040ac},
950 {0x13, 0x00000020}, {0x14, 0x0001944c},
951 {0x14, 0x00059444}, {0x14, 0x0009944c},
952 {0x14, 0x000d9444}, {0x15, 0x0000f474},
953 {0x15, 0x0004f477}, {0x15, 0x0008f455},
954 {0x15, 0x000cf455}, {0x16, 0x00000339},
955 {0x16, 0x00040339}, {0x16, 0x00080339},
956 {0x16, 0x000c0366}, {0x00, 0x00010159},
957 {0x18, 0x0000f401}, {0xfe, 0x00000000},
958 {0xfe, 0x00000000}, {0x1f, 0x00000003},
959 {0xfe, 0x00000000}, {0xfe, 0x00000000},
960 {0x1e, 0x00000247}, {0x1f, 0x00000000},
961 {0x00, 0x00030159},
962 {0xff, 0xffffffff}
963};
964
Jes Sorensen22a31d42016-02-29 17:04:15 -0500[diff] [blame]965static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
966 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
967 {0xfe, 0x00000000}, {0xfe, 0x00000000},
968 {0xfe, 0x00000000}, {0xb1, 0x00000018},
969 {0xfe, 0x00000000}, {0xfe, 0x00000000},
970 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
971 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
972 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
973 {0x5c, 0x00000002}, {0x7c, 0x00000002},
974 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
975 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
976 {0x1e, 0x00000000}, {0xdf, 0x00000780},
977 {0x50, 0x00067435},
978 /*
979 * The 8723bu vendor driver indicates that bit 8 should be set in
980 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
981 * they never actually check the package type - and just default
982 * to not setting it.
983 */
984 {0x51, 0x0006b04e},
985 {0x52, 0x000007d2}, {0x53, 0x00000000},
986 {0x54, 0x00050400}, {0x55, 0x0004026e},
987 {0xdd, 0x0000004c}, {0x70, 0x00067435},
988 /*
989 * 0x71 has same package type condition as for register 0x51
990 */
991 {0x71, 0x0006b04e},
992 {0x72, 0x000007d2}, {0x73, 0x00000000},
993 {0x74, 0x00050400}, {0x75, 0x0004026e},
994 {0xef, 0x00000100}, {0x34, 0x0000add7},
995 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
996 {0x35, 0x00005000}, {0x34, 0x00008dd1},
997 {0x35, 0x00004400}, {0x34, 0x00007dce},
998 {0x35, 0x00003800}, {0x34, 0x00006cd1},
999 {0x35, 0x00004400}, {0x34, 0x00005cce},
1000 {0x35, 0x00003800}, {0x34, 0x000048ce},
1001 {0x35, 0x00004400}, {0x34, 0x000034ce},
1002 {0x35, 0x00003800}, {0x34, 0x00002451},
1003 {0x35, 0x00004400}, {0x34, 0x0000144e},
1004 {0x35, 0x00003800}, {0x34, 0x00000051},
1005 {0x35, 0x00004400}, {0xef, 0x00000000},
1006 {0xef, 0x00000100}, {0xed, 0x00000010},
1007 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
1008 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
1009 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
1010 {0x44, 0x000044d1}, {0x44, 0x000034ce},
1011 {0x44, 0x00002451}, {0x44, 0x0000144e},
1012 {0x44, 0x00000051}, {0xef, 0x00000000},
1013 {0xed, 0x00000000}, {0x7f, 0x00020080},
1014 {0xef, 0x00002000}, {0x3b, 0x000380ef},
1015 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
1016 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
1017 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
1018 {0x3b, 0x00000900}, {0xef, 0x00000000},
1019 {0xed, 0x00000001}, {0x40, 0x000380ef},
1020 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
1021 {0x40, 0x000200bc}, {0x40, 0x000188a5},
1022 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
1023 {0x40, 0x00000900}, {0xed, 0x00000000},
1024 {0x82, 0x00080000}, {0x83, 0x00008000},
1025 {0x84, 0x00048d80}, {0x85, 0x00068000},
1026 {0xa2, 0x00080000}, {0xa3, 0x00008000},
1027 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
1028 {0xed, 0x00000002}, {0xef, 0x00000002},
1029 {0x56, 0x00000032}, {0x76, 0x00000032},
1030 {0x01, 0x00000780},
1031 {0xff, 0xffffffff}
1032};
1033
Arnd Bergmann06d05462016-04-18 23:59:31 +0200[diff] [blame]1034#ifdef CONFIG_RTL8XXXU_UNTESTED
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1035static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
1036 {0x00, 0x00030159}, {0x01, 0x00031284},
1037 {0x02, 0x00098000}, {0x03, 0x00018c63},
1038 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1039 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1040 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1041 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1042 {0x19, 0x00000000}, {0x1a, 0x00010255},
1043 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1044 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1045 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1046 {0x21, 0x0006c000}, {0x22, 0x00000000},
1047 {0x23, 0x00001558}, {0x24, 0x00000060},
1048 {0x25, 0x00000483}, {0x26, 0x0004f000},
1049 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1050 {0x29, 0x00004783}, {0x2a, 0x00000001},
1051 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1052 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1053 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1054 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1055 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1056 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1057 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1058 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1059 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1060 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1061 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1062 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1063 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1064 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1065 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1066 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1067 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1068 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1069 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1070 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1071 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1072 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1073 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1074 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1075 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1076 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1077 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1078 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1079 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1080 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1081 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1082 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1083 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1084 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1085 {0x10, 0x00000000}, {0x11, 0x00000000},
1086 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1087 {0x10, 0x0009000f}, {0x11, 0x00023100},
1088 {0x12, 0x00032000}, {0x12, 0x00071000},
1089 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1090 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1091 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1092 {0x13, 0x00018493}, {0x13, 0x0001429b},
1093 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1094 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1095 {0x13, 0x00000020}, {0x14, 0x0001944c},
1096 {0x14, 0x00059444}, {0x14, 0x0009944c},
1097 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1098 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1099 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1100 {0x16, 0x000a0330}, {0x16, 0x00060330},
1101 {0x16, 0x00020330}, {0x00, 0x00010159},
1102 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1103 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1104 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1105 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1106 {0x00, 0x00030159},
1107 {0xff, 0xffffffff}
1108};
1109
1110static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1111 {0x00, 0x00030159}, {0x01, 0x00031284},
1112 {0x02, 0x00098000}, {0x03, 0x00018c63},
1113 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1114 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1115 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1116 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1117 {0x12, 0x00032000}, {0x12, 0x00071000},
1118 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1119 {0x13, 0x000287af}, {0x13, 0x000244b7},
1120 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1121 {0x13, 0x00018493}, {0x13, 0x00014297},
1122 {0x13, 0x00010295}, {0x13, 0x0000c298},
1123 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1124 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1125 {0x14, 0x00059444}, {0x14, 0x0009944c},
1126 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1127 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1128 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1129 {0x16, 0x000a0330}, {0x16, 0x00060330},
1130 {0x16, 0x00020330},
1131 {0xff, 0xffffffff}
1132};
1133
1134static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1135 {0x00, 0x00030159}, {0x01, 0x00031284},
1136 {0x02, 0x00098000}, {0x03, 0x00018c63},
1137 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1138 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1139 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1140 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1141 {0x19, 0x00000000}, {0x1a, 0x00010255},
1142 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1143 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1144 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1145 {0x21, 0x0006c000}, {0x22, 0x00000000},
1146 {0x23, 0x00001558}, {0x24, 0x00000060},
1147 {0x25, 0x00000483}, {0x26, 0x0004f000},
1148 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1149 {0x29, 0x00004783}, {0x2a, 0x00000001},
1150 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1151 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1152 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1153 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1154 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1155 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1156 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1157 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1158 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1159 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1160 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1162 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1164 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1166 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1168 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1170 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1172 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1174 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1176 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1178 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1179 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1180 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1181 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1182 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1183 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1184 {0x10, 0x00000000}, {0x11, 0x00000000},
1185 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1186 {0x10, 0x0009000f}, {0x11, 0x00023100},
1187 {0x12, 0x00032000}, {0x12, 0x00071000},
1188 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1189 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1190 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1191 {0x13, 0x00018493}, {0x13, 0x0001429b},
1192 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1193 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1194 {0x13, 0x00000020}, {0x14, 0x0001944c},
1195 {0x14, 0x00059444}, {0x14, 0x0009944c},
1196 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1197 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1198 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1199 {0x16, 0x000a0330}, {0x16, 0x00060330},
1200 {0x16, 0x00020330}, {0x00, 0x00010159},
1201 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1202 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1203 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1204 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1205 {0x00, 0x00030159},
1206 {0xff, 0xffffffff}
1207};
1208
1209static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1210 {0x00, 0x00030159}, {0x01, 0x00031284},
1211 {0x02, 0x00098000}, {0x03, 0x00018c63},
1212 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1213 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1214 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1215 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1216 {0x19, 0x00000000}, {0x1a, 0x00000255},
1217 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1218 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1219 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1220 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1221 {0x23, 0x00001558}, {0x24, 0x00000060},
1222 {0x25, 0x00000483}, {0x26, 0x0004f000},
1223 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1224 {0x29, 0x00004783}, {0x2a, 0x00000001},
1225 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1226 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1227 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1228 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1229 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1230 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1231 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1232 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1233 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1234 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1235 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1236 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1237 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1238 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1239 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1240 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1241 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1242 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1243 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1244 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1245 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1246 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1247 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1248 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1249 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1250 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1251 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1252 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1253 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1254 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1255 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1256 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1257 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1258 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1259 {0x10, 0x00000000}, {0x11, 0x00000000},
1260 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1261 {0x10, 0x0009000f}, {0x11, 0x00023100},
1262 {0x12, 0x000d8000}, {0x12, 0x00090000},
1263 {0x12, 0x00051000}, {0x12, 0x00012000},
1264 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1265 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1266 {0x13, 0x000183a4}, {0x13, 0x00014398},
1267 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1268 {0x13, 0x000080a4}, {0x13, 0x00004098},
1269 {0x13, 0x00000000}, {0x14, 0x0001944c},
1270 {0x14, 0x00059444}, {0x14, 0x0009944c},
1271 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1272 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1273 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1274 {0x16, 0x000a0330}, {0x16, 0x00060330},
1275 {0x16, 0x00020330}, {0x00, 0x00010159},
1276 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1277 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1278 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1279 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1280 {0x00, 0x00030159},
1281 {0xff, 0xffffffff}
1282};
Arnd Bergmann06d05462016-04-18 23:59:31 +0200[diff] [blame]1283#endif
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1284
1285static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1286 { /* RF_A */
1287 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1288 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1289 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1290 .hspiread = REG_HSPI_XA_READBACK,
1291 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1292 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1293 },
1294 { /* RF_B */
1295 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1296 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1297 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1298 .hspiread = REG_HSPI_XB_READBACK,
1299 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1300 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1301 },
1302};
1303
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1304const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1305 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1306 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1307 REG_OFDM0_ENERGY_CCA_THRES,
1308 REG_OFDM0_AGCR_SSI_TABLE,
1309 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1310 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1311 REG_OFDM0_XC_TX_AFE,
1312 REG_OFDM0_XD_TX_AFE,
1313 REG_OFDM0_RX_IQ_EXT_ANTA
1314};
1315
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1316u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1317{
1318 struct usb_device *udev = priv->udev;
1319 int len;
1320 u8 data;
1321
1322 mutex_lock(&priv->usb_buf_mutex);
1323 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1324 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1325 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1326 RTW_USB_CONTROL_MSG_TIMEOUT);
1327 data = priv->usb_buf.val8;
1328 mutex_unlock(&priv->usb_buf_mutex);
1329
1330 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1331 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1332 __func__, addr, data, len);
1333 return data;
1334}
1335
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1336u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1337{
1338 struct usb_device *udev = priv->udev;
1339 int len;
1340 u16 data;
1341
1342 mutex_lock(&priv->usb_buf_mutex);
1343 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1344 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1345 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1346 RTW_USB_CONTROL_MSG_TIMEOUT);
1347 data = le16_to_cpu(priv->usb_buf.val16);
1348 mutex_unlock(&priv->usb_buf_mutex);
1349
1350 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1351 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1352 __func__, addr, data, len);
1353 return data;
1354}
1355
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1356u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1357{
1358 struct usb_device *udev = priv->udev;
1359 int len;
1360 u32 data;
1361
1362 mutex_lock(&priv->usb_buf_mutex);
1363 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1364 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1365 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1366 RTW_USB_CONTROL_MSG_TIMEOUT);
1367 data = le32_to_cpu(priv->usb_buf.val32);
1368 mutex_unlock(&priv->usb_buf_mutex);
1369
1370 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1371 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1372 __func__, addr, data, len);
1373 return data;
1374}
1375
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1376int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1377{
1378 struct usb_device *udev = priv->udev;
1379 int ret;
1380
1381 mutex_lock(&priv->usb_buf_mutex);
1382 priv->usb_buf.val8 = val;
1383 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1384 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1385 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1386 RTW_USB_CONTROL_MSG_TIMEOUT);
1387
1388 mutex_unlock(&priv->usb_buf_mutex);
1389
1390 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1391 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1392 __func__, addr, val);
1393 return ret;
1394}
1395
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1396int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1397{
1398 struct usb_device *udev = priv->udev;
1399 int ret;
1400
1401 mutex_lock(&priv->usb_buf_mutex);
1402 priv->usb_buf.val16 = cpu_to_le16(val);
1403 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1404 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1405 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1406 RTW_USB_CONTROL_MSG_TIMEOUT);
1407 mutex_unlock(&priv->usb_buf_mutex);
1408
1409 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1410 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1411 __func__, addr, val);
1412 return ret;
1413}
1414
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1415int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1416{
1417 struct usb_device *udev = priv->udev;
1418 int ret;
1419
1420 mutex_lock(&priv->usb_buf_mutex);
1421 priv->usb_buf.val32 = cpu_to_le32(val);
1422 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1423 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1424 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1425 RTW_USB_CONTROL_MSG_TIMEOUT);
1426 mutex_unlock(&priv->usb_buf_mutex);
1427
1428 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1429 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1430 __func__, addr, val);
1431 return ret;
1432}
1433
1434static int
1435rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1436{
1437 struct usb_device *udev = priv->udev;
1438 int blocksize = priv->fops->writeN_block_size;
1439 int ret, i, count, remainder;
1440
1441 count = len / blocksize;
1442 remainder = len % blocksize;
1443
1444 for (i = 0; i < count; i++) {
1445 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1446 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1447 addr, 0, buf, blocksize,
1448 RTW_USB_CONTROL_MSG_TIMEOUT);
1449 if (ret != blocksize)
1450 goto write_error;
1451
1452 addr += blocksize;
1453 buf += blocksize;
1454 }
1455
1456 if (remainder) {
1457 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1458 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1459 addr, 0, buf, remainder,
1460 RTW_USB_CONTROL_MSG_TIMEOUT);
1461 if (ret != remainder)
1462 goto write_error;
1463 }
1464
1465 return len;
1466
1467write_error:
1468 dev_info(&udev->dev,
1469 "%s: Failed to write block at addr: %04x size: %04x\n",
1470 __func__, addr, blocksize);
1471 return -EAGAIN;
1472}
1473
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1474u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1475 enum rtl8xxxu_rfpath path, u8 reg)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1476{
1477 u32 hssia, val32, retval;
1478
1479 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1480 if (path != RF_A)
1481 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1482 else
1483 val32 = hssia;
1484
1485 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1486 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1487 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1488 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1489 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1490
1491 udelay(10);
1492
1493 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1494 udelay(100);
1495
1496 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1497 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1498 udelay(10);
1499
1500 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1501 if (val32 & FPGA0_HSSI_PARM1_PI)
1502 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1503 else
1504 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1505
1506 retval &= 0xfffff;
1507
1508 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1509 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1510 __func__, reg, retval);
1511 return retval;
1512}
1513
Jes Sorensen22a31d42016-02-29 17:04:15 -0500[diff] [blame]1514/*
1515 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1516 * have write issues in high temperature conditions. We may have to
1517 * retry writing them.
1518 */
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1519int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1520 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1521{
1522 int ret, retval;
Jes Sorensen2949b9e2016-04-07 14:19:25 -0400[diff] [blame]1523 u32 dataaddr, val32;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1524
1525 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1526 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1527 __func__, reg, data);
1528
1529 data &= FPGA0_LSSI_PARM_DATA_MASK;
1530 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1531
Jes Sorensen2949b9e2016-04-07 14:19:25 -0400[diff] [blame]1532 if (priv->rtl_chip == RTL8192E) {
1533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1534 val32 &= ~0x20000;
1535 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1536 }
1537
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1538 /* Use XB for path B */
1539 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1540 if (ret != sizeof(dataaddr))
1541 retval = -EIO;
1542 else
1543 retval = 0;
1544
1545 udelay(1);
1546
Jes Sorensen2949b9e2016-04-07 14:19:25 -0400[diff] [blame]1547 if (priv->rtl_chip == RTL8192E) {
1548 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1549 val32 |= 0x20000;
1550 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1551 }
1552
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1553 return retval;
1554}
1555
Jes Sorensen8da91572016-02-29 17:04:29 -0500[diff] [blame]1556static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1557 struct h2c_cmd *h2c, int len)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1558{
1559 struct device *dev = &priv->udev->dev;
1560 int mbox_nr, retry, retval = 0;
1561 int mbox_reg, mbox_ext_reg;
1562 u8 val8;
1563
1564 mutex_lock(&priv->h2c_mutex);
1565
1566 mbox_nr = priv->next_mbox;
1567 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]1568 mbox_ext_reg = priv->fops->mbox_ext_reg +
1569 (mbox_nr * priv->fops->mbox_ext_width);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1570
1571 /*
1572 * MBOX ready?
1573 */
1574 retry = 100;
1575 do {
1576 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1577 if (!(val8 & BIT(mbox_nr)))
1578 break;
1579 } while (retry--);
1580
1581 if (!retry) {
Jes Sorensenc7a5a192016-02-29 17:04:30 -0500[diff] [blame]1582 dev_info(dev, "%s: Mailbox busy\n", __func__);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1583 retval = -EBUSY;
1584 goto error;
1585 }
1586
1587 /*
1588 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1589 */
Jes Sorensen8da91572016-02-29 17:04:29 -0500[diff] [blame]1590 if (len > sizeof(u32)) {
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]1591 if (priv->fops->mbox_ext_width == 4) {
1592 rtl8xxxu_write32(priv, mbox_ext_reg,
1593 le32_to_cpu(h2c->raw_wide.ext));
1594 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1595 dev_info(dev, "H2C_EXT %08x\n",
1596 le32_to_cpu(h2c->raw_wide.ext));
1597 } else {
1598 rtl8xxxu_write16(priv, mbox_ext_reg,
1599 le16_to_cpu(h2c->raw.ext));
1600 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1601 dev_info(dev, "H2C_EXT %04x\n",
1602 le16_to_cpu(h2c->raw.ext));
1603 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1604 }
1605 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1606 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1607 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1608
1609 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1610
1611error:
1612 mutex_unlock(&priv->h2c_mutex);
1613 return retval;
1614}
1615
Jes Sorensen394f1bd2016-02-29 17:04:49 -0500[diff] [blame]1616static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1617{
1618 struct h2c_cmd h2c;
1619 int reqnum = 0;
1620
1621 memset(&h2c, 0, sizeof(struct h2c_cmd));
1622 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1623 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1624 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1625 h2c.bt_mp_oper.data = data;
1626 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1627
1628 reqnum++;
1629 memset(&h2c, 0, sizeof(struct h2c_cmd));
1630 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1631 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1632 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1633 h2c.bt_mp_oper.addr = reg;
1634 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1635}
1636
Jes Sorensen8396a412016-04-18 11:49:32 -0400[diff] [blame]1637static void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1638{
1639 u8 val8;
1640 u32 val32;
1641
1642 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1643 val8 |= BIT(0) | BIT(3);
1644 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1645
1646 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1647 val32 &= ~(BIT(4) | BIT(5));
1648 val32 |= BIT(3);
1649 if (priv->rf_paths == 2) {
1650 val32 &= ~(BIT(20) | BIT(21));
1651 val32 |= BIT(19);
1652 }
1653 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1654
1655 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1656 val32 &= ~OFDM_RF_PATH_TX_MASK;
1657 if (priv->tx_paths == 2)
1658 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]1659 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1660 val32 |= OFDM_RF_PATH_TX_B;
1661 else
1662 val32 |= OFDM_RF_PATH_TX_A;
1663 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1664
1665 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1666 val32 &= ~FPGA_RF_MODE_JAPAN;
1667 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1668
1669 if (priv->rf_paths == 2)
1670 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1671 else
1672 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1673
1674 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1675 if (priv->rf_paths == 2)
1676 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1677
1678 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1679}
1680
Jes Sorensen7eb14002016-04-18 11:49:26 -0400[diff] [blame]1681static void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1682{
1683 u8 sps0;
1684 u32 val32;
1685
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1686 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1687
1688 /* RF RX code for preamble power saving */
1689 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1690 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1691 if (priv->rf_paths == 2)
1692 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1693 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1694
1695 /* Disable TX for four paths */
1696 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1697 val32 &= ~OFDM_RF_PATH_TX_MASK;
1698 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1699
1700 /* Enable power saving */
1701 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1702 val32 |= FPGA_RF_MODE_JAPAN;
1703 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1704
1705 /* AFE control register to power down bits [30:22] */
1706 if (priv->rf_paths == 2)
1707 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1708 else
1709 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1710
1711 /* Power down RF module */
1712 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1713 if (priv->rf_paths == 2)
1714 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1715
1716 sps0 &= ~(BIT(0) | BIT(3));
1717 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1718}
1719
1720
1721static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1722{
1723 u8 val8;
1724
1725 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1726 val8 &= ~BIT(6);
1727 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1728
1729 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1730 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1731 val8 &= ~BIT(0);
1732 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1733}
1734
1735
1736/*
1737 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1738 * supports the 2.4GHz band, so channels 1 - 14:
1739 * group 0: channels 1 - 3
1740 * group 1: channels 4 - 9
1741 * group 2: channels 10 - 14
1742 *
1743 * Note: We index from 0 in the code
1744 */
1745static int rtl8723a_channel_to_group(int channel)
1746{
1747 int group;
1748
1749 if (channel < 4)
1750 group = 0;
1751 else if (channel < 10)
1752 group = 1;
1753 else
1754 group = 2;
1755
1756 return group;
1757}
1758
Jes Sorensen9e247722016-04-07 14:19:23 -0400[diff] [blame]1759/*
1760 * Valid for rtl8723bu and rtl8192eu
1761 */
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1762int rtl8xxxu_gen2_channel_to_group(int channel)
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]1763{
1764 int group;
1765
1766 if (channel < 3)
1767 group = 0;
1768 else if (channel < 6)
1769 group = 1;
1770 else if (channel < 9)
1771 group = 2;
1772 else if (channel < 12)
1773 group = 3;
1774 else
1775 group = 4;
1776
1777 return group;
1778}
1779
Jes Sorensene09718c2016-04-18 11:49:27 -0400[diff] [blame]1780static void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1781{
1782 struct rtl8xxxu_priv *priv = hw->priv;
1783 u32 val32, rsr;
1784 u8 val8, opmode;
1785 bool ht = true;
1786 int sec_ch_above, channel;
1787 int i;
1788
1789 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1790 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1791 channel = hw->conf.chandef.chan->hw_value;
1792
1793 switch (hw->conf.chandef.width) {
1794 case NL80211_CHAN_WIDTH_20_NOHT:
1795 ht = false;
1796 case NL80211_CHAN_WIDTH_20:
1797 opmode |= BW_OPMODE_20MHZ;
1798 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1799
1800 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1801 val32 &= ~FPGA_RF_MODE;
1802 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1803
1804 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1805 val32 &= ~FPGA_RF_MODE;
1806 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1807
1808 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1809 val32 |= FPGA0_ANALOG2_20MHZ;
1810 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1811 break;
1812 case NL80211_CHAN_WIDTH_40:
1813 if (hw->conf.chandef.center_freq1 >
1814 hw->conf.chandef.chan->center_freq) {
1815 sec_ch_above = 1;
1816 channel += 2;
1817 } else {
1818 sec_ch_above = 0;
1819 channel -= 2;
1820 }
1821
1822 opmode &= ~BW_OPMODE_20MHZ;
1823 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1824 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1825 if (sec_ch_above)
1826 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1827 else
1828 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1829 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1830
1831 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1832 val32 |= FPGA_RF_MODE;
1833 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1834
1835 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1836 val32 |= FPGA_RF_MODE;
1837 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1838
1839 /*
1840 * Set Control channel to upper or lower. These settings
1841 * are required only for 40MHz
1842 */
1843 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1844 val32 &= ~CCK0_SIDEBAND;
1845 if (!sec_ch_above)
1846 val32 |= CCK0_SIDEBAND;
1847 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1848
1849 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1850 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1851 if (sec_ch_above)
1852 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1853 else
1854 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1855 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1856
1857 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1858 val32 &= ~FPGA0_ANALOG2_20MHZ;
1859 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1860
1861 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1862 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1863 if (sec_ch_above)
1864 val32 |= FPGA0_PS_UPPER_CHANNEL;
1865 else
1866 val32 |= FPGA0_PS_LOWER_CHANNEL;
1867 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1868 break;
1869
1870 default:
1871 break;
1872 }
1873
1874 for (i = RF_A; i < priv->rf_paths; i++) {
1875 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1876 val32 &= ~MODE_AG_CHANNEL_MASK;
1877 val32 |= channel;
1878 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1879 }
1880
1881 if (ht)
1882 val8 = 0x0e;
1883 else
1884 val8 = 0x0a;
1885
1886 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1887 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1888
1889 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1890 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1891
1892 for (i = RF_A; i < priv->rf_paths; i++) {
1893 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1894 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1895 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1896 else
1897 val32 |= MODE_AG_CHANNEL_20MHZ;
1898 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1899 }
1900}
1901
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]1902void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
Jes Sorensenc3f95062016-02-29 17:04:40 -0500[diff] [blame]1903{
1904 struct rtl8xxxu_priv *priv = hw->priv;
1905 u32 val32, rsr;
Jes Sorensen368633c2016-02-29 17:04:42 -0500[diff] [blame]1906 u8 val8, subchannel;
Jes Sorensenc3f95062016-02-29 17:04:40 -0500[diff] [blame]1907 u16 rf_mode_bw;
1908 bool ht = true;
1909 int sec_ch_above, channel;
1910 int i;
1911
1912 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1913 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1914 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1915 channel = hw->conf.chandef.chan->hw_value;
1916
1917/* Hack */
1918 subchannel = 0;
1919
1920 switch (hw->conf.chandef.width) {
1921 case NL80211_CHAN_WIDTH_20_NOHT:
1922 ht = false;
1923 case NL80211_CHAN_WIDTH_20:
1924 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1925 subchannel = 0;
1926
1927 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1928 val32 &= ~FPGA_RF_MODE;
1929 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1930
1931 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1932 val32 &= ~FPGA_RF_MODE;
1933 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1934
1935 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1936 val32 &= ~(BIT(30) | BIT(31));
1937 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1938
1939 break;
1940 case NL80211_CHAN_WIDTH_40:
1941 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1942
1943 if (hw->conf.chandef.center_freq1 >
1944 hw->conf.chandef.chan->center_freq) {
1945 sec_ch_above = 1;
1946 channel += 2;
1947 } else {
1948 sec_ch_above = 0;
1949 channel -= 2;
1950 }
1951
1952 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1953 val32 |= FPGA_RF_MODE;
1954 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1955
1956 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1957 val32 |= FPGA_RF_MODE;
1958 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1959
1960 /*
1961 * Set Control channel to upper or lower. These settings
1962 * are required only for 40MHz
1963 */
1964 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1965 val32 &= ~CCK0_SIDEBAND;
1966 if (!sec_ch_above)
1967 val32 |= CCK0_SIDEBAND;
1968 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1969
1970 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1971 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1972 if (sec_ch_above)
1973 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1974 else
1975 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1976 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1977
1978 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1979 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1980 if (sec_ch_above)
1981 val32 |= FPGA0_PS_UPPER_CHANNEL;
1982 else
1983 val32 |= FPGA0_PS_LOWER_CHANNEL;
1984 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1985 break;
1986 case NL80211_CHAN_WIDTH_80:
1987 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 for (i = RF_A; i < priv->rf_paths; i++) {
1994 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1995 val32 &= ~MODE_AG_CHANNEL_MASK;
1996 val32 |= channel;
1997 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1998 }
1999
2000 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
2001 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
2002
2003 if (ht)
2004 val8 = 0x0e;
2005 else
2006 val8 = 0x0a;
2007
2008 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2009 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2010
2011 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2012 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2013
2014 for (i = RF_A; i < priv->rf_paths; i++) {
2015 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2016 val32 &= ~MODE_AG_BW_MASK;
2017 switch(hw->conf.chandef.width) {
2018 case NL80211_CHAN_WIDTH_80:
2019 val32 |= MODE_AG_BW_80MHZ_8723B;
2020 break;
2021 case NL80211_CHAN_WIDTH_40:
2022 val32 |= MODE_AG_BW_40MHZ_8723B;
2023 break;
2024 default:
2025 val32 |= MODE_AG_BW_20MHZ_8723B;
2026 break;
2027 }
2028 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2029 }
2030}
2031
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2032static void
Jes Sorensen42a3bc72016-04-18 11:49:31 -0400[diff] [blame]2033rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2034{
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2035 struct rtl8xxxu_power_base *power_base = priv->power_base;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2036 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
2037 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
2038 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
2039 u8 val8;
2040 int group, i;
2041
2042 group = rtl8723a_channel_to_group(channel);
2043
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2044 cck[0] = priv->cck_tx_power_index_A[group] - 1;
2045 cck[1] = priv->cck_tx_power_index_B[group] - 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2046
Jes Sorensenb591e982016-04-14 16:37:09 -0400[diff] [blame]2047 if (priv->hi_pa) {
2048 if (cck[0] > 0x20)
2049 cck[0] = 0x20;
2050 if (cck[1] > 0x20)
2051 cck[1] = 0x20;
2052 }
2053
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2054 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
2055 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2056 if (ofdm[0])
2057 ofdm[0] -= 1;
2058 if (ofdm[1])
2059 ofdm[1] -= 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2060
2061 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
2062 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
2063
2064 mcsbase[0] = ofdm[0];
2065 mcsbase[1] = ofdm[1];
2066 if (!ht40) {
2067 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
2068 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
2069 }
2070
2071 if (priv->tx_paths > 1) {
2072 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
2073 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
2074 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
2075 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
2076 }
2077
2078 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
2079 dev_info(&priv->udev->dev,
2080 "%s: Setting TX power CCK A: %02x, "
2081 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2082 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
2083
2084 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
2085 if (cck[i] > RF6052_MAX_TX_PWR)
2086 cck[i] = RF6052_MAX_TX_PWR;
2087 if (ofdm[i] > RF6052_MAX_TX_PWR)
2088 ofdm[i] = RF6052_MAX_TX_PWR;
2089 }
2090
2091 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2092 val32 &= 0xffff00ff;
2093 val32 |= (cck[0] << 8);
2094 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2095
2096 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2097 val32 &= 0xff;
2098 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2099 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2100
2101 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2102 val32 &= 0xffffff00;
2103 val32 |= cck[1];
2104 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2105
2106 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2107 val32 &= 0xff;
2108 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2109 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2110
2111 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2112 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2113 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2114 ofdmbase[1] << 16 | ofdmbase[1] << 24;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2115
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2116 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
2117 ofdm_a + power_base->reg_0e00);
2118 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
2119 ofdm_b + power_base->reg_0830);
2120
2121 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
2122 ofdm_a + power_base->reg_0e04);
2123 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
2124 ofdm_b + power_base->reg_0834);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2125
2126 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2127 mcsbase[0] << 16 | mcsbase[0] << 24;
2128 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2129 mcsbase[1] << 16 | mcsbase[1] << 24;
2130
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2131 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
2132 mcs_a + power_base->reg_0e10);
2133 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
2134 mcs_b + power_base->reg_083c);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2135
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2136 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
2137 mcs_a + power_base->reg_0e14);
2138 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
2139 mcs_b + power_base->reg_0848);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2140
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2141 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
2142 mcs_a + power_base->reg_0e18);
2143 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
2144 mcs_b + power_base->reg_084c);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2145
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2146 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
2147 mcs_a + power_base->reg_0e1c);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2148 for (i = 0; i < 3; i++) {
2149 if (i != 2)
2150 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2151 else
2152 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2153 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2154 }
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2155 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
2156 mcs_b + power_base->reg_0868);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2157 for (i = 0; i < 3; i++) {
2158 if (i != 2)
2159 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2160 else
2161 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2162 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2163 }
2164}
2165
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]2166static void
2167rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2168{
Jes Sorensen1d3cc442016-02-29 17:05:24 -0500[diff] [blame]2169 u32 val32, ofdm, mcs;
2170 u8 cck, ofdmbase, mcsbase;
Jes Sorensen54bed432016-02-29 17:05:23 -0500[diff] [blame]2171 int group, tx_idx;
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]2172
Jes Sorensen54bed432016-02-29 17:05:23 -0500[diff] [blame]2173 tx_idx = 0;
Jes Sorensen5ac74142016-04-18 11:49:34 -0400[diff] [blame]2174 group = rtl8xxxu_gen2_channel_to_group(channel);
Jes Sorensen54bed432016-02-29 17:05:23 -0500[diff] [blame]2175
2176 cck = priv->cck_tx_power_index_B[group];
2177 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2178 val32 &= 0xffff00ff;
2179 val32 |= (cck << 8);
2180 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2181
2182 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2183 val32 &= 0xff;
2184 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2185 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2186
2187 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2188 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2189 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2190
2191 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2192 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
Jes Sorensen1d3cc442016-02-29 17:05:24 -0500[diff] [blame]2193
2194 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2195 if (ht40)
2196 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2197 else
2198 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2199 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2200
2201 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2202 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]2203}
2204
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2205static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2206 enum nl80211_iftype linktype)
2207{
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]2208 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2209
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]2210 val8 = rtl8xxxu_read8(priv, REG_MSR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2211 val8 &= ~MSR_LINKTYPE_MASK;
2212
2213 switch (linktype) {
2214 case NL80211_IFTYPE_UNSPECIFIED:
2215 val8 |= MSR_LINKTYPE_NONE;
2216 break;
2217 case NL80211_IFTYPE_ADHOC:
2218 val8 |= MSR_LINKTYPE_ADHOC;
2219 break;
2220 case NL80211_IFTYPE_STATION:
2221 val8 |= MSR_LINKTYPE_STATION;
2222 break;
2223 case NL80211_IFTYPE_AP:
2224 val8 |= MSR_LINKTYPE_AP;
2225 break;
2226 default:
2227 goto out;
2228 }
2229
2230 rtl8xxxu_write8(priv, REG_MSR, val8);
2231out:
2232 return;
2233}
2234
2235static void
2236rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2237{
2238 u16 val16;
2239
2240 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2241 RETRY_LIMIT_SHORT_MASK) |
2242 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2243 RETRY_LIMIT_LONG_MASK);
2244
2245 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2246}
2247
2248static void
2249rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2250{
2251 u16 val16;
2252
2253 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2254 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2255
2256 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2257}
2258
2259static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2260{
2261 struct device *dev = &priv->udev->dev;
2262 char *cut;
2263
2264 switch (priv->chip_cut) {
2265 case 0:
2266 cut = "A";
2267 break;
2268 case 1:
2269 cut = "B";
2270 break;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2271 case 2:
2272 cut = "C";
2273 break;
2274 case 3:
2275 cut = "D";
2276 break;
2277 case 4:
2278 cut = "E";
2279 break;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2280 default:
2281 cut = "unknown";
2282 }
2283
2284 dev_info(dev,
2285 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2286 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2287 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2288 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2289
2290 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2291}
2292
2293static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2294{
2295 struct device *dev = &priv->udev->dev;
2296 u32 val32, bonding;
2297 u16 val16;
2298
2299 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2300 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2301 SYS_CFG_CHIP_VERSION_SHIFT;
2302 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2303 dev_info(dev, "Unsupported test chip\n");
2304 return -ENOTSUPP;
2305 }
2306
2307 if (val32 & SYS_CFG_BT_FUNC) {
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2308 if (priv->chip_cut >= 3) {
2309 sprintf(priv->chip_name, "8723BU");
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2310 priv->rtl_chip = RTL8723B;
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2311 } else {
2312 sprintf(priv->chip_name, "8723AU");
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2313 priv->usb_interrupts = 1;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2314 priv->rtl_chip = RTL8723A;
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2315 }
2316
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2317 priv->rf_paths = 1;
2318 priv->rx_paths = 1;
2319 priv->tx_paths = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2320
2321 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2322 if (val32 & MULTI_WIFI_FUNC_EN)
2323 priv->has_wifi = 1;
2324 if (val32 & MULTI_BT_FUNC_EN)
2325 priv->has_bluetooth = 1;
2326 if (val32 & MULTI_GPS_FUNC_EN)
2327 priv->has_gps = 1;
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]2328 priv->is_multi_func = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2329 } else if (val32 & SYS_CFG_TYPE_ID) {
2330 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2331 bonding &= HPON_FSM_BONDING_MASK;
Jes Sorensen55c0b6a2016-04-14 14:58:50 -0400[diff] [blame]2332 if (priv->fops->tx_desc_size ==
2333 sizeof(struct rtl8xxxu_txdesc40)) {
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2334 if (bonding == HPON_FSM_BONDING_1T2R) {
2335 sprintf(priv->chip_name, "8191EU");
2336 priv->rf_paths = 2;
2337 priv->rx_paths = 2;
2338 priv->tx_paths = 1;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2339 priv->rtl_chip = RTL8191E;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2340 } else {
2341 sprintf(priv->chip_name, "8192EU");
2342 priv->rf_paths = 2;
2343 priv->rx_paths = 2;
2344 priv->tx_paths = 2;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2345 priv->rtl_chip = RTL8192E;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2346 }
2347 } else if (bonding == HPON_FSM_BONDING_1T2R) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2348 sprintf(priv->chip_name, "8191CU");
2349 priv->rf_paths = 2;
2350 priv->rx_paths = 2;
2351 priv->tx_paths = 1;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2352 priv->usb_interrupts = 1;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2353 priv->rtl_chip = RTL8191C;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2354 } else {
2355 sprintf(priv->chip_name, "8192CU");
2356 priv->rf_paths = 2;
2357 priv->rx_paths = 2;
2358 priv->tx_paths = 2;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2359 priv->usb_interrupts = 1;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2360 priv->rtl_chip = RTL8192C;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2361 }
2362 priv->has_wifi = 1;
2363 } else {
2364 sprintf(priv->chip_name, "8188CU");
2365 priv->rf_paths = 1;
2366 priv->rx_paths = 1;
2367 priv->tx_paths = 1;
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2368 priv->rtl_chip = RTL8188C;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2369 priv->usb_interrupts = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2370 priv->has_wifi = 1;
2371 }
2372
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2373 switch (priv->rtl_chip) {
2374 case RTL8188E:
2375 case RTL8192E:
2376 case RTL8723B:
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2377 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2378 case SYS_CFG_VENDOR_ID_TSMC:
2379 sprintf(priv->chip_vendor, "TSMC");
2380 break;
2381 case SYS_CFG_VENDOR_ID_SMIC:
2382 sprintf(priv->chip_vendor, "SMIC");
2383 priv->vendor_smic = 1;
2384 break;
2385 case SYS_CFG_VENDOR_ID_UMC:
2386 sprintf(priv->chip_vendor, "UMC");
2387 priv->vendor_umc = 1;
2388 break;
2389 default:
2390 sprintf(priv->chip_vendor, "unknown");
2391 }
2392 break;
2393 default:
2394 if (val32 & SYS_CFG_VENDOR_ID) {
2395 sprintf(priv->chip_vendor, "UMC");
2396 priv->vendor_umc = 1;
2397 } else {
2398 sprintf(priv->chip_vendor, "TSMC");
2399 }
2400 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2401
2402 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2403 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2404
2405 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2406 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2407 priv->ep_tx_high_queue = 1;
2408 priv->ep_tx_count++;
2409 }
2410
2411 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2412 priv->ep_tx_normal_queue = 1;
2413 priv->ep_tx_count++;
2414 }
2415
2416 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2417 priv->ep_tx_low_queue = 1;
2418 priv->ep_tx_count++;
2419 }
2420
2421 /*
2422 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2423 */
2424 if (!priv->ep_tx_count) {
2425 switch (priv->nr_out_eps) {
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2426 case 4:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2427 case 3:
2428 priv->ep_tx_low_queue = 1;
2429 priv->ep_tx_count++;
2430 case 2:
2431 priv->ep_tx_normal_queue = 1;
2432 priv->ep_tx_count++;
2433 case 1:
2434 priv->ep_tx_high_queue = 1;
2435 priv->ep_tx_count++;
2436 break;
2437 default:
2438 dev_info(dev, "Unsupported USB TX end-points\n");
2439 return -ENOTSUPP;
2440 }
2441 }
2442
2443 return 0;
2444}
2445
2446static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2447{
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2448 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2449
2450 if (efuse->rtl_id != cpu_to_le16(0x8129))
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2451 return -EINVAL;
2452
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2453 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2454
2455 memcpy(priv->cck_tx_power_index_A,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2456 efuse->cck_tx_power_index_A,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2457 sizeof(efuse->cck_tx_power_index_A));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2458 memcpy(priv->cck_tx_power_index_B,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2459 efuse->cck_tx_power_index_B,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2460 sizeof(efuse->cck_tx_power_index_B));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2461
2462 memcpy(priv->ht40_1s_tx_power_index_A,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2463 efuse->ht40_1s_tx_power_index_A,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2464 sizeof(efuse->ht40_1s_tx_power_index_A));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2465 memcpy(priv->ht40_1s_tx_power_index_B,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2466 efuse->ht40_1s_tx_power_index_B,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2467 sizeof(efuse->ht40_1s_tx_power_index_B));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2468
2469 memcpy(priv->ht20_tx_power_index_diff,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2470 efuse->ht20_tx_power_index_diff,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2471 sizeof(efuse->ht20_tx_power_index_diff));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2472 memcpy(priv->ofdm_tx_power_index_diff,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2473 efuse->ofdm_tx_power_index_diff,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2474 sizeof(efuse->ofdm_tx_power_index_diff));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2475
2476 memcpy(priv->ht40_max_power_offset,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2477 efuse->ht40_max_power_offset,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2478 sizeof(efuse->ht40_max_power_offset));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2479 memcpy(priv->ht20_max_power_offset,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2480 efuse->ht20_max_power_offset,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2481 sizeof(efuse->ht20_max_power_offset));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2482
Jes Sorensen4ef22eb2016-02-29 17:04:55 -0500[diff] [blame]2483 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2484 priv->has_xtalk = 1;
2485 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2486 }
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2487
2488 priv->power_base = &rtl8723a_power_base;
2489
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2490 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2491 efuse->vendor_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2492 dev_info(&priv->udev->dev, "Product: %.41s\n",
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2493 efuse->device_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2494 return 0;
2495}
2496
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]2497static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2498{
Jes Sorensenb8ba8602016-02-29 17:04:28 -0500[diff] [blame]2499 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
Jes Sorensen3be26992016-02-29 17:05:22 -0500[diff] [blame]2500 int i;
Jes Sorensenb8ba8602016-02-29 17:04:28 -0500[diff] [blame]2501
2502 if (efuse->rtl_id != cpu_to_le16(0x8129))
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]2503 return -EINVAL;
2504
Jes Sorensenb8ba8602016-02-29 17:04:28 -0500[diff] [blame]2505 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]2506
Jes Sorensen3be26992016-02-29 17:05:22 -0500[diff] [blame]2507 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2508 sizeof(efuse->tx_power_index_A.cck_base));
2509 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2510 sizeof(efuse->tx_power_index_B.cck_base));
2511
2512 memcpy(priv->ht40_1s_tx_power_index_A,
2513 efuse->tx_power_index_A.ht40_base,
2514 sizeof(efuse->tx_power_index_A.ht40_base));
2515 memcpy(priv->ht40_1s_tx_power_index_B,
2516 efuse->tx_power_index_B.ht40_base,
2517 sizeof(efuse->tx_power_index_B.ht40_base));
2518
2519 priv->ofdm_tx_power_diff[0].a =
2520 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2521 priv->ofdm_tx_power_diff[0].b =
2522 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2523
2524 priv->ht20_tx_power_diff[0].a =
2525 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2526 priv->ht20_tx_power_diff[0].b =
2527 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2528
2529 priv->ht40_tx_power_diff[0].a = 0;
2530 priv->ht40_tx_power_diff[0].b = 0;
2531
2532 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2533 priv->ofdm_tx_power_diff[i].a =
2534 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2535 priv->ofdm_tx_power_diff[i].b =
2536 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2537
2538 priv->ht20_tx_power_diff[i].a =
2539 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2540 priv->ht20_tx_power_diff[i].b =
2541 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2542
2543 priv->ht40_tx_power_diff[i].a =
2544 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2545 priv->ht40_tx_power_diff[i].b =
2546 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2547 }
2548
Jes Sorensen4ef22eb2016-02-29 17:04:55 -0500[diff] [blame]2549 priv->has_xtalk = 1;
2550 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2551
Jes Sorensenb8ba8602016-02-29 17:04:28 -0500[diff] [blame]2552 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2553 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]2554
2555 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2556 int i;
2557 unsigned char *raw = priv->efuse_wifi.raw;
2558
2559 dev_info(&priv->udev->dev,
2560 "%s: dumping efuse (0x%02zx bytes):\n",
2561 __func__, sizeof(struct rtl8723bu_efuse));
2562 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2563 dev_info(&priv->udev->dev, "%02x: "
2564 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2565 raw[i], raw[i + 1], raw[i + 2],
2566 raw[i + 3], raw[i + 4], raw[i + 5],
2567 raw[i + 6], raw[i + 7]);
2568 }
2569 }
2570
2571 return 0;
2572}
2573
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2574#ifdef CONFIG_RTL8XXXU_UNTESTED
2575
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2576static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2577{
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2578 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2579 int i;
2580
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2581 if (efuse->rtl_id != cpu_to_le16(0x8129))
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2582 return -EINVAL;
2583
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2584 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2585
2586 memcpy(priv->cck_tx_power_index_A,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2587 efuse->cck_tx_power_index_A,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2588 sizeof(efuse->cck_tx_power_index_A));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2589 memcpy(priv->cck_tx_power_index_B,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2590 efuse->cck_tx_power_index_B,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2591 sizeof(efuse->cck_tx_power_index_B));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2592
2593 memcpy(priv->ht40_1s_tx_power_index_A,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2594 efuse->ht40_1s_tx_power_index_A,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2595 sizeof(efuse->ht40_1s_tx_power_index_A));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2596 memcpy(priv->ht40_1s_tx_power_index_B,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2597 efuse->ht40_1s_tx_power_index_B,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2598 sizeof(efuse->ht40_1s_tx_power_index_B));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2599 memcpy(priv->ht40_2s_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2600 efuse->ht40_2s_tx_power_index_diff,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2601 sizeof(efuse->ht40_2s_tx_power_index_diff));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2602
2603 memcpy(priv->ht20_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2604 efuse->ht20_tx_power_index_diff,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2605 sizeof(efuse->ht20_tx_power_index_diff));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2606 memcpy(priv->ofdm_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2607 efuse->ofdm_tx_power_index_diff,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2608 sizeof(efuse->ofdm_tx_power_index_diff));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2609
2610 memcpy(priv->ht40_max_power_offset,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2611 efuse->ht40_max_power_offset,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2612 sizeof(efuse->ht40_max_power_offset));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2613 memcpy(priv->ht20_max_power_offset,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2614 efuse->ht20_max_power_offset,
Jes Sorensen3e84f932016-02-29 17:05:20 -0500[diff] [blame]2615 sizeof(efuse->ht20_max_power_offset));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2616
2617 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2618 efuse->vendor_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2619 dev_info(&priv->udev->dev, "Product: %.20s\n",
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2620 efuse->device_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2621
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2622 priv->power_base = &rtl8192c_power_base;
2623
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame]2624 if (efuse->rf_regulatory & 0x20) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2625 sprintf(priv->chip_name, "8188RU");
Jes Sorensen8d95c802016-04-14 16:37:11 -0400[diff] [blame]2626 priv->rtl_chip = RTL8188R;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2627 priv->hi_pa = 1;
Jes Sorensencabb5502016-04-14 16:37:17 -0400[diff] [blame]2628 priv->no_pape = 1;
Jes Sorensen2fc0b8e2016-04-14 16:37:16 -0400[diff] [blame]2629 priv->power_base = &rtl8188r_power_base;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2630 }
2631
2632 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2633 unsigned char *raw = priv->efuse_wifi.raw;
2634
2635 dev_info(&priv->udev->dev,
2636 "%s: dumping efuse (0x%02zx bytes):\n",
2637 __func__, sizeof(struct rtl8192cu_efuse));
2638 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2639 dev_info(&priv->udev->dev, "%02x: "
2640 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2641 raw[i], raw[i + 1], raw[i + 2],
2642 raw[i + 3], raw[i + 4], raw[i + 5],
2643 raw[i + 6], raw[i + 7]);
2644 }
2645 }
2646 return 0;
2647}
2648
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2649#endif
2650
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2651static int
2652rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2653{
2654 int i;
2655 u8 val8;
2656 u32 val32;
2657
2658 /* Write Address */
2659 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2660 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2661 val8 &= 0xfc;
2662 val8 |= (offset >> 8) & 0x03;
2663 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2664
2665 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2666 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2667
2668 /* Poll for data read */
2669 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2670 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2671 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2672 if (val32 & BIT(31))
2673 break;
2674 }
2675
2676 if (i == RTL8XXXU_MAX_REG_POLL)
2677 return -EIO;
2678
2679 udelay(50);
2680 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2681
2682 *data = val32 & 0xff;
2683 return 0;
2684}
2685
2686static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2687{
2688 struct device *dev = &priv->udev->dev;
2689 int i, ret = 0;
2690 u8 val8, word_mask, header, extheader;
2691 u16 val16, efuse_addr, offset;
2692 u32 val32;
2693
2694 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2695 if (val16 & EEPROM_ENABLE)
2696 priv->has_eeprom = 1;
2697 if (val16 & EEPROM_BOOT)
2698 priv->boot_eeprom = 1;
2699
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]2700 if (priv->is_multi_func) {
2701 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2702 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2703 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2704 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2705
2706 dev_dbg(dev, "Booting from %s\n",
2707 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2708
2709 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2710
2711 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2712 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2713 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2714 val16 |= SYS_ISO_PWC_EV12V;
2715 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2716 }
2717 /* Reset: 0x0000[28], default valid */
2718 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2719 if (!(val16 & SYS_FUNC_ELDR)) {
2720 val16 |= SYS_FUNC_ELDR;
2721 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2722 }
2723
2724 /*
2725 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2726 */
2727 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2728 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2729 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2730 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2731 }
2732
2733 /* Default value is 0xff */
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2734 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2735
2736 efuse_addr = 0;
2737 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2738 u16 map_addr;
2739
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2740 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2741 if (ret || header == 0xff)
2742 goto exit;
2743
2744 if ((header & 0x1f) == 0x0f) { /* extended header */
2745 offset = (header & 0xe0) >> 5;
2746
2747 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2748 &extheader);
2749 if (ret)
2750 goto exit;
2751 /* All words disabled */
2752 if ((extheader & 0x0f) == 0x0f)
2753 continue;
2754
2755 offset |= ((extheader & 0xf0) >> 1);
2756 word_mask = extheader & 0x0f;
2757 } else {
2758 offset = (header >> 4) & 0x0f;
2759 word_mask = header & 0x0f;
2760 }
2761
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2762 /* Get word enable value from PG header */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2763
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2764 /* We have 8 bits to indicate validity */
2765 map_addr = offset * 8;
2766 if (map_addr >= EFUSE_MAP_LEN) {
2767 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2768 "efuse corrupt!\n",
2769 __func__, map_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2770 ret = -EINVAL;
2771 goto exit;
2772 }
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2773 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2774 /* Check word enable condition in the section */
Jakub Sitnicki32a39dd2016-02-29 17:04:24 -0500[diff] [blame]2775 if (word_mask & BIT(i)) {
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2776 map_addr += 2;
Jakub Sitnicki32a39dd2016-02-29 17:04:24 -0500[diff] [blame]2777 continue;
2778 }
2779
2780 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2781 if (ret)
2782 goto exit;
2783 priv->efuse_wifi.raw[map_addr++] = val8;
2784
2785 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2786 if (ret)
2787 goto exit;
2788 priv->efuse_wifi.raw[map_addr++] = val8;
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2789 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2790 }
2791
2792exit:
2793 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2794
2795 return ret;
2796}
2797
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]2798void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2799{
2800 u8 val8;
2801 u16 sys_func;
2802
2803 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2804 val8 &= ~BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2805 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]2806
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2807 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2808 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2809 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]2810
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2811 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2812 val8 |= BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2813 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]2814
2815 sys_func |= SYS_FUNC_CPU_ENABLE;
2816 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2817}
2818
2819static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
2820{
2821 u8 val8;
2822 u16 sys_func;
2823
2824 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2825 val8 &= ~BIT(1);
2826 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2827
2828 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2829 val8 &= ~BIT(0);
2830 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2831
2832 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2833 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2834 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2835
2836 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
2837 val8 &= ~BIT(1);
2838 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
2839
2840 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2841 val8 |= BIT(0);
2842 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2843
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2844 sys_func |= SYS_FUNC_CPU_ENABLE;
2845 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2846}
2847
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2848static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2849{
2850 struct device *dev = &priv->udev->dev;
2851 int ret = 0, i;
2852 u32 val32;
2853
2854 /* Poll checksum report */
2855 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2856 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2857 if (val32 & MCU_FW_DL_CSUM_REPORT)
2858 break;
2859 }
2860
2861 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2862 dev_warn(dev, "Firmware checksum poll timed out\n");
2863 ret = -EAGAIN;
2864 goto exit;
2865 }
2866
2867 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2868 val32 |= MCU_FW_DL_READY;
2869 val32 &= ~MCU_WINT_INIT_READY;
2870 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2871
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2872 /*
2873 * Reset the 8051 in order for the firmware to start running,
2874 * otherwise it won't come up on the 8192eu
2875 */
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]2876 priv->fops->reset_8051(priv);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2877
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2878 /* Wait for firmware to become ready */
2879 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2880 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2881 if (val32 & MCU_WINT_INIT_READY)
2882 break;
2883
2884 udelay(100);
2885 }
2886
2887 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2888 dev_warn(dev, "Firmware failed to start\n");
2889 ret = -EAGAIN;
2890 goto exit;
2891 }
2892
Jes Sorensen3a4be6a2016-02-29 17:04:58 -0500[diff] [blame]2893 /*
2894 * Init H2C command
2895 */
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]2896 if (priv->rtl_chip == RTL8723B)
Jes Sorensen3a4be6a2016-02-29 17:04:58 -0500[diff] [blame]2897 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2898exit:
2899 return ret;
2900}
2901
2902static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2903{
2904 int pages, remainder, i, ret;
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2905 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2906 u16 val16;
2907 u32 val32;
2908 u8 *fwptr;
2909
2910 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2911 val8 |= 4;
2912 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2913
2914 /* 8051 enable */
2915 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame]2916 val16 |= SYS_FUNC_CPU_ENABLE;
2917 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2918
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2919 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2920 if (val8 & MCU_FW_RAM_SEL) {
2921 pr_info("do the RAM reset\n");
2922 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]2923 priv->fops->reset_8051(priv);
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2924 }
2925
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2926 /* MCU firmware download enable */
2927 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2928 val8 |= MCU_FW_DL_ENABLE;
2929 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2930
2931 /* 8051 reset */
2932 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2933 val32 &= ~BIT(19);
2934 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2935
2936 /* Reset firmware download checksum */
2937 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2938 val8 |= MCU_FW_DL_CSUM_REPORT;
2939 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2940
2941 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2942 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2943
2944 fwptr = priv->fw_data->data;
2945
2946 for (i = 0; i < pages; i++) {
2947 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2948 val8 |= i;
2949 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2950
2951 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2952 fwptr, RTL_FW_PAGE_SIZE);
2953 if (ret != RTL_FW_PAGE_SIZE) {
2954 ret = -EAGAIN;
2955 goto fw_abort;
2956 }
2957
2958 fwptr += RTL_FW_PAGE_SIZE;
2959 }
2960
2961 if (remainder) {
2962 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2963 val8 |= i;
2964 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2965 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2966 fwptr, remainder);
2967 if (ret != remainder) {
2968 ret = -EAGAIN;
2969 goto fw_abort;
2970 }
2971 }
2972
2973 ret = 0;
2974fw_abort:
2975 /* MCU firmware download disable */
2976 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2977 val16 &= ~MCU_FW_DL_ENABLE;
2978 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2979
2980 return ret;
2981}
2982
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]2983int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2984{
2985 struct device *dev = &priv->udev->dev;
2986 const struct firmware *fw;
2987 int ret = 0;
2988 u16 signature;
2989
2990 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2991 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2992 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2993 ret = -EAGAIN;
2994 goto exit;
2995 }
2996 if (!fw) {
2997 dev_warn(dev, "Firmware data not available\n");
2998 ret = -EINVAL;
2999 goto exit;
3000 }
3001
3002 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
Tobias Klauser98e27cb2016-02-03 13:39:43 -0500[diff] [blame]3003 if (!priv->fw_data) {
3004 ret = -ENOMEM;
3005 goto exit;
3006 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3007 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
3008
3009 signature = le16_to_cpu(priv->fw_data->signature);
3010 switch (signature & 0xfff0) {
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]3011 case 0x92e0:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3012 case 0x92c0:
3013 case 0x88c0:
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]3014 case 0x5300:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3015 case 0x2300:
3016 break;
3017 default:
3018 ret = -EINVAL;
3019 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
3020 __func__, signature);
3021 }
3022
3023 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
3024 le16_to_cpu(priv->fw_data->major_version),
3025 priv->fw_data->minor_version, signature);
3026
3027exit:
3028 release_firmware(fw);
3029 return ret;
3030}
3031
3032static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
3033{
3034 char *fw_name;
3035 int ret;
3036
3037 switch (priv->chip_cut) {
3038 case 0:
3039 fw_name = "rtlwifi/rtl8723aufw_A.bin";
3040 break;
3041 case 1:
3042 if (priv->enable_bluetooth)
3043 fw_name = "rtlwifi/rtl8723aufw_B.bin";
3044 else
3045 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
3046
3047 break;
3048 default:
3049 return -EINVAL;
3050 }
3051
3052 ret = rtl8xxxu_load_firmware(priv, fw_name);
3053 return ret;
3054}
3055
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]3056static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
3057{
3058 char *fw_name;
3059 int ret;
3060
3061 if (priv->enable_bluetooth)
3062 fw_name = "rtlwifi/rtl8723bu_bt.bin";
3063 else
3064 fw_name = "rtlwifi/rtl8723bu_nic.bin";
3065
3066 ret = rtl8xxxu_load_firmware(priv, fw_name);
3067 return ret;
3068}
3069
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3070#ifdef CONFIG_RTL8XXXU_UNTESTED
3071
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3072static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
3073{
3074 char *fw_name;
3075 int ret;
3076
3077 if (!priv->vendor_umc)
3078 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]3079 else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3080 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3081 else
3082 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3083
3084 ret = rtl8xxxu_load_firmware(priv, fw_name);
3085
3086 return ret;
3087}
3088
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3089#endif
3090
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3091static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3092{
3093 u16 val16;
3094 int i = 100;
3095
3096 /* Inform 8051 to perform reset */
3097 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3098
3099 for (i = 100; i > 0; i--) {
3100 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3101
3102 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3103 dev_dbg(&priv->udev->dev,
3104 "%s: Firmware self reset success!\n", __func__);
3105 break;
3106 }
3107 udelay(50);
3108 }
3109
3110 if (!i) {
3111 /* Force firmware reset */
3112 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3113 val16 &= ~SYS_FUNC_CPU_ENABLE;
3114 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3115 }
3116}
3117
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3118static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3119{
3120 u32 val32;
3121
Jes Sorensen70bc1e22016-04-07 14:19:31 -0400[diff] [blame]3122 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3123 val32 &= ~(BIT(20) | BIT(24));
Jes Sorensen70bc1e22016-04-07 14:19:31 -0400[diff] [blame]3124 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3125
3126 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3127 val32 &= ~BIT(4);
Jes Sorensen3a4be6a2016-02-29 17:04:58 -0500[diff] [blame]3128 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3129
3130 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3131 val32 |= BIT(3);
3132 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3133
3134 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3135 val32 |= BIT(24);
3136 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3137
Jes Sorensen3a4be6a2016-02-29 17:04:58 -0500[diff] [blame]3138 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3139 val32 &= ~BIT(23);
3140 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3141
Jes Sorensen120e6272016-02-29 17:05:14 -0500[diff] [blame]3142 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3143 val32 |= (BIT(0) | BIT(1));
Jes Sorensen120e6272016-02-29 17:05:14 -0500[diff] [blame]3144 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3145
Jes Sorensen59b74392016-02-29 17:05:15 -0500[diff] [blame]3146 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3147 val32 &= 0xffffff00;
3148 val32 |= 0x77;
Jes Sorensen59b74392016-02-29 17:05:15 -0500[diff] [blame]3149 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
Jes Sorensen3a4be6a2016-02-29 17:04:58 -0500[diff] [blame]3150
3151 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3152 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3153 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]3154}
3155
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3156static int
Jes Sorensenc606e662016-04-07 14:19:16 -0400[diff] [blame]3157rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3158{
Jes Sorensenc606e662016-04-07 14:19:16 -0400[diff] [blame]3159 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3160 int i, ret;
3161 u16 reg;
3162 u8 val;
3163
3164 for (i = 0; ; i++) {
3165 reg = array[i].reg;
3166 val = array[i].val;
3167
3168 if (reg == 0xffff && val == 0xff)
3169 break;
3170
3171 ret = rtl8xxxu_write8(priv, reg, val);
3172 if (ret != 1) {
3173 dev_warn(&priv->udev->dev,
Jes Sorensenc606e662016-04-07 14:19:16 -0400[diff] [blame]3174 "Failed to initialize MAC "
3175 "(reg: %04x, val %02x)\n", reg, val);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3176 return -EAGAIN;
3177 }
3178 }
3179
Jes Sorensen8a594852016-04-07 14:19:26 -0400[diff] [blame]3180 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
Jes Sorensen8baf6702016-02-29 17:04:54 -0500[diff] [blame]3181 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3182
3183 return 0;
3184}
3185
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3186int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3187 struct rtl8xxxu_reg32val *array)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3188{
3189 int i, ret;
3190 u16 reg;
3191 u32 val;
3192
3193 for (i = 0; ; i++) {
3194 reg = array[i].reg;
3195 val = array[i].val;
3196
3197 if (reg == 0xffff && val == 0xffffffff)
3198 break;
3199
3200 ret = rtl8xxxu_write32(priv, reg, val);
3201 if (ret != sizeof(val)) {
3202 dev_warn(&priv->udev->dev,
3203 "Failed to initialize PHY\n");
3204 return -EAGAIN;
3205 }
3206 udelay(1);
3207 }
3208
3209 return 0;
3210}
3211
Jes Sorensende7c1892016-04-18 11:49:30 -0400[diff] [blame]3212static void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3213{
Jes Sorensenb84cac12016-04-14 14:59:00 -0400[diff] [blame]3214 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
Jes Sorensen04313eb2016-02-29 17:04:51 -0500[diff] [blame]3215 u16 val16;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3216 u32 val32;
3217
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3218 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3219 udelay(2);
3220 val8 |= AFE_PLL_320_ENABLE;
3221 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3222 udelay(2);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3223
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3224 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3225 udelay(2);
Jes Sorensen8baf6702016-02-29 17:04:54 -0500[diff] [blame]3226
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3227 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3228 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3229 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3230
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3231 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3232 val32 &= ~AFE_XTAL_RF_GATE;
3233 if (priv->has_bluetooth)
3234 val32 &= ~AFE_XTAL_BT_GATE;
3235 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3236
3237 /* 6. 0x1f[7:0] = 0x07 */
3238 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3239 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3240
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3241 if (priv->hi_pa)
Jes Sorensenabd71bd2016-04-07 14:19:22 -0400[diff] [blame]3242 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3243 else if (priv->tx_paths == 2)
3244 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3245 else
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3246 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3247
Jes Sorensen78a84212016-04-14 16:37:10 -0400[diff] [blame]3248 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3249 priv->vendor_umc && priv->chip_cut == 1)
3250 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
Jes Sorensenc82f8d12016-04-14 14:58:59 -0400[diff] [blame]3251
3252 if (priv->hi_pa)
3253 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3254 else
3255 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
Jes Sorensenb84cac12016-04-14 14:59:00 -0400[diff] [blame]3256
3257 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3258 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3259 ldohci12 = 0x57;
3260 lpldo = 1;
3261 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
3262 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3263}
3264
3265static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
3266{
3267 u8 val8;
3268 u16 val16;
3269
3270 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3271 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
3272 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3273
3274 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3275
3276 /* 6. 0x1f[7:0] = 0x07 */
3277 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3278 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3279
3280 /* Why? */
3281 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3282 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3283 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
Jes Sorensenc82f8d12016-04-14 14:58:59 -0400[diff] [blame]3284
3285 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3286}
3287
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3288/*
3289 * Most of this is black magic retrieved from the old rtl8723au driver
3290 */
3291static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3292{
Jes Sorensenb84cac12016-04-14 14:59:00 -0400[diff] [blame]3293 u8 val8;
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]3294 u32 val32;
3295
3296 priv->fops->init_phy_bb(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3297
3298 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3299 /*
3300 * For 1T2R boards, patch the registers.
3301 *
3302 * It looks like 8191/2 1T2R boards use path B for TX
3303 */
3304 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3305 val32 &= ~(BIT(0) | BIT(1));
3306 val32 |= BIT(1);
3307 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3308
3309 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3310 val32 &= ~0x300033;
3311 val32 |= 0x200022;
3312 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3313
3314 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
Jes Sorensenbd8fe402016-04-14 14:58:56 -0400[diff] [blame]3315 val32 &= ~CCK0_AFE_RX_MASK;
Jes Sorensen90683082016-04-14 14:58:55 -0400[diff] [blame]3316 val32 &= 0x00ffffff;
Jes Sorensenbd8fe402016-04-14 14:58:56 -0400[diff] [blame]3317 val32 |= 0x40000000;
3318 val32 |= CCK0_AFE_RX_ANT_B;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3319 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3320
3321 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3322 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3323 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3324 OFDM_RF_PATH_TX_B);
3325 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3326
3327 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3328 val32 &= ~(BIT(4) | BIT(5));
3329 val32 |= BIT(4);
3330 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3331
3332 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3333 val32 &= ~(BIT(27) | BIT(26));
3334 val32 |= BIT(27);
3335 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3336
3337 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3338 val32 &= ~(BIT(27) | BIT(26));
3339 val32 |= BIT(27);
3340 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3341
3342 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3343 val32 &= ~(BIT(27) | BIT(26));
3344 val32 |= BIT(27);
3345 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3346
3347 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3348 val32 &= ~(BIT(27) | BIT(26));
3349 val32 |= BIT(27);
3350 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3351
3352 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3353 val32 &= ~(BIT(27) | BIT(26));
3354 val32 |= BIT(27);
3355 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3356 }
3357
Jes Sorensen4ef22eb2016-02-29 17:04:55 -0500[diff] [blame]3358 if (priv->has_xtalk) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3359 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3360
Jes Sorensen4ef22eb2016-02-29 17:04:55 -0500[diff] [blame]3361 val8 = priv->xtalk;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3362 val32 &= 0xff000fff;
3363 val32 |= ((val8 | (val8 << 6)) << 12);
3364
3365 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3366 }
3367
Jes Sorensen8a594852016-04-07 14:19:26 -0400[diff] [blame]3368 if (priv->rtl_chip == RTL8192E)
3369 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
3370
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3371 return 0;
3372}
3373
3374static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3375 struct rtl8xxxu_rfregval *array,
3376 enum rtl8xxxu_rfpath path)
3377{
3378 int i, ret;
3379 u8 reg;
3380 u32 val;
3381
3382 for (i = 0; ; i++) {
3383 reg = array[i].reg;
3384 val = array[i].val;
3385
3386 if (reg == 0xff && val == 0xffffffff)
3387 break;
3388
3389 switch (reg) {
3390 case 0xfe:
3391 msleep(50);
3392 continue;
3393 case 0xfd:
3394 mdelay(5);
3395 continue;
3396 case 0xfc:
3397 mdelay(1);
3398 continue;
3399 case 0xfb:
3400 udelay(50);
3401 continue;
3402 case 0xfa:
3403 udelay(5);
3404 continue;
3405 case 0xf9:
3406 udelay(1);
3407 continue;
3408 }
3409
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3410 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3411 if (ret) {
3412 dev_warn(&priv->udev->dev,
3413 "Failed to initialize RF\n");
3414 return -EAGAIN;
3415 }
3416 udelay(1);
3417 }
3418
3419 return 0;
3420}
3421
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3422int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3423 struct rtl8xxxu_rfregval *table,
3424 enum rtl8xxxu_rfpath path)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3425{
3426 u32 val32;
3427 u16 val16, rfsi_rfenv;
3428 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3429
3430 switch (path) {
3431 case RF_A:
3432 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3433 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3434 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3435 break;
3436 case RF_B:
3437 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3438 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3439 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3440 break;
3441 default:
3442 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3443 __func__, path + 'A');
3444 return -EINVAL;
3445 }
3446 /* For path B, use XB */
3447 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3448 rfsi_rfenv &= FPGA0_RF_RFENV;
3449
3450 /*
3451 * These two we might be able to optimize into one
3452 */
3453 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3454 val32 |= BIT(20); /* 0x10 << 16 */
3455 rtl8xxxu_write32(priv, reg_int_oe, val32);
3456 udelay(1);
3457
3458 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3459 val32 |= BIT(4);
3460 rtl8xxxu_write32(priv, reg_int_oe, val32);
3461 udelay(1);
3462
3463 /*
3464 * These two we might be able to optimize into one
3465 */
3466 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3467 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3468 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3469 udelay(1);
3470
3471 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3472 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3473 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3474 udelay(1);
3475
3476 rtl8xxxu_init_rf_regs(priv, table, path);
3477
3478 /* For path B, use XB */
3479 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3480 val16 &= ~FPGA0_RF_RFENV;
3481 val16 |= rfsi_rfenv;
3482 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3483
3484 return 0;
3485}
3486
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]3487static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
3488{
3489 int ret;
3490
3491 ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
3492
3493 /* Reduce 80M spur */
3494 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
3495 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
3496 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
3497 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
3498
3499 return ret;
3500}
3501
3502static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
3503{
3504 int ret;
3505
3506 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
3507 /*
3508 * PHY LCK
3509 */
3510 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
3511 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
3512 msleep(200);
3513 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
3514
3515 return ret;
3516}
3517
3518#ifdef CONFIG_RTL8XXXU_UNTESTED
3519static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv)
3520{
3521 struct rtl8xxxu_rfregval *rftable;
3522 int ret;
3523
Jes Sorensen8d95c802016-04-14 16:37:11 -0400[diff] [blame]3524 if (priv->rtl_chip == RTL8188R) {
3525 rftable = rtl8188ru_radioa_1t_highpa_table;
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]3526 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
3527 } else if (priv->rf_paths == 1) {
3528 rftable = rtl8192cu_radioa_1t_init_table;
3529 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
3530 } else {
3531 rftable = rtl8192cu_radioa_2t_init_table;
3532 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
3533 if (ret)
3534 goto exit;
3535 rftable = rtl8192cu_radiob_2t_init_table;
3536 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
3537 }
3538
3539exit:
3540 return ret;
3541}
3542#endif
3543
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3544static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3545{
3546 int ret = -EBUSY;
3547 int count = 0;
3548 u32 value;
3549
3550 value = LLT_OP_WRITE | address << 8 | data;
3551
3552 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3553
3554 do {
3555 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3556 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3557 ret = 0;
3558 break;
3559 }
3560 } while (count++ < 20);
3561
3562 return ret;
3563}
3564
3565static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3566{
3567 int ret;
3568 int i;
3569
3570 for (i = 0; i < last_tx_page; i++) {
3571 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3572 if (ret)
3573 goto exit;
3574 }
3575
3576 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3577 if (ret)
3578 goto exit;
3579
3580 /* Mark remaining pages as a ring buffer */
3581 for (i = last_tx_page + 1; i < 0xff; i++) {
3582 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3583 if (ret)
3584 goto exit;
3585 }
3586
3587 /* Let last entry point to the start entry of ring buffer */
3588 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3589 if (ret)
3590 goto exit;
3591
3592exit:
3593 return ret;
3594}
3595
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3596int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3597{
3598 u32 val32;
3599 int ret = 0;
3600 int i;
3601
3602 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3603 val32 |= AUTO_LLT_INIT_LLT;
3604 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3605
3606 for (i = 500; i; i--) {
3607 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3608 if (!(val32 & AUTO_LLT_INIT_LLT))
3609 break;
3610 usleep_range(2, 4);
3611 }
3612
Jes Sorensen4de24812016-02-29 17:04:07 -0500[diff] [blame]3613 if (!i) {
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3614 ret = -EBUSY;
3615 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3616 }
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3617
3618 return ret;
3619}
3620
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3621static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3622{
3623 u16 val16, hi, lo;
3624 u16 hiq, mgq, bkq, beq, viq, voq;
3625 int hip, mgp, bkp, bep, vip, vop;
3626 int ret = 0;
3627
3628 switch (priv->ep_tx_count) {
3629 case 1:
3630 if (priv->ep_tx_high_queue) {
3631 hi = TRXDMA_QUEUE_HIGH;
3632 } else if (priv->ep_tx_low_queue) {
3633 hi = TRXDMA_QUEUE_LOW;
3634 } else if (priv->ep_tx_normal_queue) {
3635 hi = TRXDMA_QUEUE_NORMAL;
3636 } else {
3637 hi = 0;
3638 ret = -EINVAL;
3639 }
3640
3641 hiq = hi;
3642 mgq = hi;
3643 bkq = hi;
3644 beq = hi;
3645 viq = hi;
3646 voq = hi;
3647
3648 hip = 0;
3649 mgp = 0;
3650 bkp = 0;
3651 bep = 0;
3652 vip = 0;
3653 vop = 0;
3654 break;
3655 case 2:
3656 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3657 hi = TRXDMA_QUEUE_HIGH;
3658 lo = TRXDMA_QUEUE_LOW;
3659 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3660 hi = TRXDMA_QUEUE_NORMAL;
3661 lo = TRXDMA_QUEUE_LOW;
3662 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3663 hi = TRXDMA_QUEUE_HIGH;
3664 lo = TRXDMA_QUEUE_NORMAL;
3665 } else {
3666 ret = -EINVAL;
3667 hi = 0;
3668 lo = 0;
3669 }
3670
3671 hiq = hi;
3672 mgq = hi;
3673 bkq = lo;
3674 beq = lo;
3675 viq = hi;
3676 voq = hi;
3677
3678 hip = 0;
3679 mgp = 0;
3680 bkp = 1;
3681 bep = 1;
3682 vip = 0;
3683 vop = 0;
3684 break;
3685 case 3:
3686 beq = TRXDMA_QUEUE_LOW;
3687 bkq = TRXDMA_QUEUE_LOW;
3688 viq = TRXDMA_QUEUE_NORMAL;
3689 voq = TRXDMA_QUEUE_HIGH;
3690 mgq = TRXDMA_QUEUE_HIGH;
3691 hiq = TRXDMA_QUEUE_HIGH;
3692
3693 hip = hiq ^ 3;
3694 mgp = mgq ^ 3;
3695 bkp = bkq ^ 3;
3696 bep = beq ^ 3;
3697 vip = viq ^ 3;
3698 vop = viq ^ 3;
3699 break;
3700 default:
3701 ret = -EINVAL;
3702 }
3703
3704 /*
3705 * None of the vendor drivers are configuring the beacon
3706 * queue here .... why?
3707 */
3708 if (!ret) {
3709 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3710 val16 &= 0x7;
3711 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3712 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3713 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3714 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3715 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3716 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3717 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3718
3719 priv->pipe_out[TXDESC_QUEUE_VO] =
3720 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3721 priv->pipe_out[TXDESC_QUEUE_VI] =
3722 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3723 priv->pipe_out[TXDESC_QUEUE_BE] =
3724 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3725 priv->pipe_out[TXDESC_QUEUE_BK] =
3726 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3727 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3728 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3729 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3730 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3731 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3732 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3733 priv->pipe_out[TXDESC_QUEUE_CMD] =
3734 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3735 }
3736
3737 return ret;
3738}
3739
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3740void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
3741 int result[][8], int candidate, bool tx_only)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3742{
3743 u32 oldval, x, tx0_a, reg;
3744 int y, tx0_c;
3745 u32 val32;
3746
3747 if (!iqk_ok)
3748 return;
3749
3750 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3751 oldval = val32 >> 22;
3752
3753 x = result[candidate][0];
3754 if ((x & 0x00000200) != 0)
3755 x = x | 0xfffffc00;
3756 tx0_a = (x * oldval) >> 8;
3757
3758 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3759 val32 &= ~0x3ff;
3760 val32 |= tx0_a;
3761 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3762
3763 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3764 val32 &= ~BIT(31);
3765 if ((x * oldval >> 7) & 0x1)
3766 val32 |= BIT(31);
3767 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3768
3769 y = result[candidate][1];
3770 if ((y & 0x00000200) != 0)
3771 y = y | 0xfffffc00;
3772 tx0_c = (y * oldval) >> 8;
3773
3774 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3775 val32 &= ~0xf0000000;
3776 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3777 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3778
3779 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3780 val32 &= ~0x003f0000;
3781 val32 |= ((tx0_c & 0x3f) << 16);
3782 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3783
3784 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3785 val32 &= ~BIT(29);
3786 if ((y * oldval >> 7) & 0x1)
3787 val32 |= BIT(29);
3788 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3789
3790 if (tx_only) {
3791 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3792 return;
3793 }
3794
3795 reg = result[candidate][2];
3796
3797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3798 val32 &= ~0x3ff;
3799 val32 |= (reg & 0x3ff);
3800 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3801
3802 reg = result[candidate][3] & 0x3F;
3803
3804 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3805 val32 &= ~0xfc00;
3806 val32 |= ((reg << 10) & 0xfc00);
3807 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3808
3809 reg = (result[candidate][3] >> 6) & 0xF;
3810
3811 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3812 val32 &= ~0xf0000000;
3813 val32 |= (reg << 28);
3814 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3815}
3816
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3817void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
3818 int result[][8], int candidate, bool tx_only)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3819{
3820 u32 oldval, x, tx1_a, reg;
3821 int y, tx1_c;
3822 u32 val32;
3823
3824 if (!iqk_ok)
3825 return;
3826
3827 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3828 oldval = val32 >> 22;
3829
3830 x = result[candidate][4];
3831 if ((x & 0x00000200) != 0)
3832 x = x | 0xfffffc00;
3833 tx1_a = (x * oldval) >> 8;
3834
3835 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3836 val32 &= ~0x3ff;
3837 val32 |= tx1_a;
3838 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3839
3840 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3841 val32 &= ~BIT(27);
3842 if ((x * oldval >> 7) & 0x1)
3843 val32 |= BIT(27);
3844 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3845
3846 y = result[candidate][5];
3847 if ((y & 0x00000200) != 0)
3848 y = y | 0xfffffc00;
3849 tx1_c = (y * oldval) >> 8;
3850
3851 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3852 val32 &= ~0xf0000000;
3853 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3854 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3855
3856 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3857 val32 &= ~0x003f0000;
3858 val32 |= ((tx1_c & 0x3f) << 16);
3859 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3860
3861 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3862 val32 &= ~BIT(25);
3863 if ((y * oldval >> 7) & 0x1)
3864 val32 |= BIT(25);
3865 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3866
3867 if (tx_only) {
3868 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3869 return;
3870 }
3871
3872 reg = result[candidate][6];
3873
3874 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3875 val32 &= ~0x3ff;
3876 val32 |= (reg & 0x3ff);
3877 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3878
3879 reg = result[candidate][7] & 0x3f;
3880
3881 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3882 val32 &= ~0xfc00;
3883 val32 |= ((reg << 10) & 0xfc00);
3884 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3885
3886 reg = (result[candidate][7] >> 6) & 0xf;
3887
3888 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3889 val32 &= ~0x0000f000;
3890 val32 |= (reg << 12);
3891 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3892}
3893
3894#define MAX_TOLERANCE 5
3895
3896static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3897 int result[][8], int c1, int c2)
3898{
3899 u32 i, j, diff, simubitmap, bound = 0;
3900 int candidate[2] = {-1, -1}; /* for path A and path B */
3901 bool retval = true;
3902
3903 if (priv->tx_paths > 1)
3904 bound = 8;
3905 else
3906 bound = 4;
3907
3908 simubitmap = 0;
3909
3910 for (i = 0; i < bound; i++) {
3911 diff = (result[c1][i] > result[c2][i]) ?
3912 (result[c1][i] - result[c2][i]) :
3913 (result[c2][i] - result[c1][i]);
3914 if (diff > MAX_TOLERANCE) {
3915 if ((i == 2 || i == 6) && !simubitmap) {
3916 if (result[c1][i] + result[c1][i + 1] == 0)
3917 candidate[(i / 4)] = c2;
3918 else if (result[c2][i] + result[c2][i + 1] == 0)
3919 candidate[(i / 4)] = c1;
3920 else
3921 simubitmap = simubitmap | (1 << i);
3922 } else {
3923 simubitmap = simubitmap | (1 << i);
3924 }
3925 }
3926 }
3927
3928 if (simubitmap == 0) {
3929 for (i = 0; i < (bound / 4); i++) {
3930 if (candidate[i] >= 0) {
3931 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3932 result[3][j] = result[candidate[i]][j];
3933 retval = false;
3934 }
3935 }
3936 return retval;
3937 } else if (!(simubitmap & 0x0f)) {
3938 /* path A OK */
3939 for (i = 0; i < 4; i++)
3940 result[3][i] = result[c1][i];
3941 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3942 /* path B OK */
3943 for (i = 4; i < 8; i++)
3944 result[3][i] = result[c1][i];
3945 }
3946
3947 return false;
3948}
3949
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]3950bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
3951 int result[][8], int c1, int c2)
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]3952{
3953 u32 i, j, diff, simubitmap, bound = 0;
3954 int candidate[2] = {-1, -1}; /* for path A and path B */
3955 int tmp1, tmp2;
3956 bool retval = true;
3957
3958 if (priv->tx_paths > 1)
3959 bound = 8;
3960 else
3961 bound = 4;
3962
3963 simubitmap = 0;
3964
3965 for (i = 0; i < bound; i++) {
3966 if (i & 1) {
3967 if ((result[c1][i] & 0x00000200))
3968 tmp1 = result[c1][i] | 0xfffffc00;
3969 else
3970 tmp1 = result[c1][i];
3971
3972 if ((result[c2][i]& 0x00000200))
3973 tmp2 = result[c2][i] | 0xfffffc00;
3974 else
3975 tmp2 = result[c2][i];
3976 } else {
3977 tmp1 = result[c1][i];
3978 tmp2 = result[c2][i];
3979 }
3980
3981 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3982
3983 if (diff > MAX_TOLERANCE) {
3984 if ((i == 2 || i == 6) && !simubitmap) {
3985 if (result[c1][i] + result[c1][i + 1] == 0)
3986 candidate[(i / 4)] = c2;
3987 else if (result[c2][i] + result[c2][i + 1] == 0)
3988 candidate[(i / 4)] = c1;
3989 else
3990 simubitmap = simubitmap | (1 << i);
3991 } else {
3992 simubitmap = simubitmap | (1 << i);
3993 }
3994 }
3995 }
3996
3997 if (simubitmap == 0) {
3998 for (i = 0; i < (bound / 4); i++) {
3999 if (candidate[i] >= 0) {
4000 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4001 result[3][j] = result[candidate[i]][j];
4002 retval = false;
4003 }
4004 }
4005 return retval;
4006 } else {
4007 if (!(simubitmap & 0x03)) {
4008 /* path A TX OK */
4009 for (i = 0; i < 2; i++)
4010 result[3][i] = result[c1][i];
4011 }
4012
4013 if (!(simubitmap & 0x0c)) {
4014 /* path A RX OK */
4015 for (i = 2; i < 4; i++)
4016 result[3][i] = result[c1][i];
4017 }
4018
4019 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4020 /* path B RX OK */
4021 for (i = 4; i < 6; i++)
4022 result[3][i] = result[c1][i];
4023 }
4024
4025 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4026 /* path B RX OK */
4027 for (i = 6; i < 8; i++)
4028 result[3][i] = result[c1][i];
4029 }
4030 }
4031
4032 return false;
4033}
4034
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4035void
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4036rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
4037{
4038 int i;
4039
4040 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4041 backup[i] = rtl8xxxu_read8(priv, reg[i]);
4042
4043 backup[i] = rtl8xxxu_read32(priv, reg[i]);
4044}
4045
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4046void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
4047 const u32 *reg, u32 *backup)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4048{
4049 int i;
4050
4051 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4052 rtl8xxxu_write8(priv, reg[i], backup[i]);
4053
4054 rtl8xxxu_write32(priv, reg[i], backup[i]);
4055}
4056
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4057void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4058 u32 *backup, int count)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4059{
4060 int i;
4061
4062 for (i = 0; i < count; i++)
4063 backup[i] = rtl8xxxu_read32(priv, regs[i]);
4064}
4065
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4066void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4067 u32 *backup, int count)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4068{
4069 int i;
4070
4071 for (i = 0; i < count; i++)
4072 rtl8xxxu_write32(priv, regs[i], backup[i]);
4073}
4074
4075
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4076void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
4077 bool path_a_on)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4078{
4079 u32 path_on;
4080 int i;
4081
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4082 if (priv->tx_paths == 1) {
Jes Sorensen8634af52016-02-29 17:04:33 -0500[diff] [blame]4083 path_on = priv->fops->adda_1t_path_on;
4084 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4085 } else {
Jes Sorensen8634af52016-02-29 17:04:33 -0500[diff] [blame]4086 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
4087 priv->fops->adda_2t_path_on_b;
4088
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4089 rtl8xxxu_write32(priv, regs[0], path_on);
4090 }
4091
4092 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
4093 rtl8xxxu_write32(priv, regs[i], path_on);
4094}
4095
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]4096void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
4097 const u32 *regs, u32 *backup)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4098{
4099 int i = 0;
4100
4101 rtl8xxxu_write8(priv, regs[i], 0x3f);
4102
4103 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
4104 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
4105
4106 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
4107}
4108
4109static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
4110{
4111 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
4112 int result = 0;
4113
4114 /* path-A IQK setting */
4115 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
4116 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
4117 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
4118
4119 val32 = (priv->rf_paths > 1) ? 0x28160202 :
4120 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4121 0x28160502;
4122 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
4123
4124 /* path-B IQK setting */
4125 if (priv->rf_paths > 1) {
4126 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
4127 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
4128 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4129 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4130 }
4131
4132 /* LO calibration setting */
4133 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4134
4135 /* One shot, path A LOK & IQK */
4136 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4137 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4138
4139 mdelay(1);
4140
4141 /* Check failed */
4142 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4143 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4144 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4145 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4146
4147 if (!(reg_eac & BIT(28)) &&
4148 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4149 ((reg_e9c & 0x03ff0000) != 0x00420000))
4150 result |= 0x01;
4151 else /* If TX not OK, ignore RX */
4152 goto out;
4153
4154 /* If TX is OK, check whether RX is OK */
4155 if (!(reg_eac & BIT(27)) &&
4156 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4157 ((reg_eac & 0x03ff0000) != 0x00360000))
4158 result |= 0x02;
4159 else
4160 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4161 __func__);
4162out:
4163 return result;
4164}
4165
4166static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4167{
4168 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4169 int result = 0;
4170
4171 /* One shot, path B LOK & IQK */
4172 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4173 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4174
4175 mdelay(1);
4176
4177 /* Check failed */
4178 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4179 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4180 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4181 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4182 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4183
4184 if (!(reg_eac & BIT(31)) &&
4185 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4186 ((reg_ebc & 0x03ff0000) != 0x00420000))
4187 result |= 0x01;
4188 else
4189 goto out;
4190
4191 if (!(reg_eac & BIT(30)) &&
4192 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4193 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4194 result |= 0x02;
4195 else
4196 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4197 __func__);
4198out:
4199 return result;
4200}
4201
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]4202static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4203{
4204 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4205 int result = 0;
4206
4207 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4208
4209 /*
4210 * Leave IQK mode
4211 */
4212 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4213 val32 &= 0x000000ff;
4214 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4215
4216 /*
4217 * Enable path A PA in TX IQK mode
4218 */
4219 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4220 val32 |= 0x80000;
4221 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4222 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4223 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4224 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4225
4226 /*
4227 * Tx IQK setting
4228 */
4229 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4230 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4231
4232 /* path-A IQK setting */
4233 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4234 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4235 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4236 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4237
4238 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4239 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4240 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4241 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4242
4243 /* LO calibration setting */
4244 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4245
4246 /*
4247 * Enter IQK mode
4248 */
4249 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4250 val32 &= 0x000000ff;
4251 val32 |= 0x80800000;
4252 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4253
4254 /*
4255 * The vendor driver indicates the USB module is always using
4256 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4257 */
4258 if (priv->rf_paths > 1)
4259 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4260 else
4261 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4262
4263 /*
4264 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4265 * No trace of this in the 8192eu or 8188eu vendor drivers.
4266 */
4267 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4268
4269 /* One shot, path A LOK & IQK */
4270 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4271 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4272
4273 mdelay(1);
4274
4275 /* Restore Ant Path */
4276 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4277#ifdef RTL8723BU_BT
4278 /* GNT_BT = 1 */
4279 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4280#endif
4281
4282 /*
4283 * Leave IQK mode
4284 */
4285 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4286 val32 &= 0x000000ff;
4287 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4288
4289 /* Check failed */
4290 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4291 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4292 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4293
4294 val32 = (reg_e9c >> 16) & 0x3ff;
4295 if (val32 & 0x200)
4296 val32 = 0x400 - val32;
4297
4298 if (!(reg_eac & BIT(28)) &&
4299 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4300 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4301 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4302 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4303 val32 < 0xf)
4304 result |= 0x01;
4305 else /* If TX not OK, ignore RX */
4306 goto out;
4307
4308out:
4309 return result;
4310}
4311
4312static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4313{
4314 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4315 int result = 0;
4316
4317 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4318
4319 /*
4320 * Leave IQK mode
4321 */
4322 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4323 val32 &= 0x000000ff;
4324 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4325
4326 /*
4327 * Enable path A PA in TX IQK mode
4328 */
4329 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4330 val32 |= 0x80000;
4331 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4332 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4333 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4334 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4335
4336 /*
4337 * Tx IQK setting
4338 */
4339 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4340 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4341
4342 /* path-A IQK setting */
4343 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4344 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4345 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4346 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4347
4348 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4349 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4350 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4351 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4352
4353 /* LO calibration setting */
4354 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4355
4356 /*
4357 * Enter IQK mode
4358 */
4359 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4360 val32 &= 0x000000ff;
4361 val32 |= 0x80800000;
4362 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4363
4364 /*
4365 * The vendor driver indicates the USB module is always using
4366 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4367 */
4368 if (priv->rf_paths > 1)
4369 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4370 else
4371 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4372
4373 /*
4374 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4375 * No trace of this in the 8192eu or 8188eu vendor drivers.
4376 */
4377 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4378
4379 /* One shot, path A LOK & IQK */
4380 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4381 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4382
4383 mdelay(1);
4384
4385 /* Restore Ant Path */
4386 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4387#ifdef RTL8723BU_BT
4388 /* GNT_BT = 1 */
4389 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4390#endif
4391
4392 /*
4393 * Leave IQK mode
4394 */
4395 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4396 val32 &= 0x000000ff;
4397 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4398
4399 /* Check failed */
4400 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4401 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4402 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4403
4404 val32 = (reg_e9c >> 16) & 0x3ff;
4405 if (val32 & 0x200)
4406 val32 = 0x400 - val32;
4407
4408 if (!(reg_eac & BIT(28)) &&
4409 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4410 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4411 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4412 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4413 val32 < 0xf)
4414 result |= 0x01;
4415 else /* If TX not OK, ignore RX */
4416 goto out;
4417
4418 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4419 ((reg_e9c & 0x3ff0000) >> 16);
4420 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4421
4422 /*
4423 * Modify RX IQK mode
4424 */
4425 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4426 val32 &= 0x000000ff;
4427 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4428 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4429 val32 |= 0x80000;
4430 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4431 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4432 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4433 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4434
4435 /*
4436 * PA, PAD setting
4437 */
4438 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4439 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4440
4441 /*
4442 * RX IQK setting
4443 */
4444 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4445
4446 /* path-A IQK setting */
4447 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4448 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4449 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4450 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4451
4452 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4453 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4454 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4455 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4456
4457 /* LO calibration setting */
4458 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4459
4460 /*
4461 * Enter IQK mode
4462 */
4463 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4464 val32 &= 0x000000ff;
4465 val32 |= 0x80800000;
4466 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4467
4468 if (priv->rf_paths > 1)
4469 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4470 else
4471 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4472
4473 /*
4474 * Disable BT
4475 */
4476 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4477
4478 /* One shot, path A LOK & IQK */
4479 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4480 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4481
4482 mdelay(1);
4483
4484 /* Restore Ant Path */
4485 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4486#ifdef RTL8723BU_BT
4487 /* GNT_BT = 1 */
4488 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4489#endif
4490
4491 /*
4492 * Leave IQK mode
4493 */
4494 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4495 val32 &= 0x000000ff;
4496 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4497
4498 /* Check failed */
4499 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4500 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4501
4502 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4503
4504 val32 = (reg_eac >> 16) & 0x3ff;
4505 if (val32 & 0x200)
4506 val32 = 0x400 - val32;
4507
4508 if (!(reg_eac & BIT(27)) &&
4509 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4510 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4511 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4512 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4513 val32 < 0xf)
4514 result |= 0x02;
4515 else /* If TX not OK, ignore RX */
4516 goto out;
4517out:
4518 return result;
4519}
4520
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4521static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4522 int result[][8], int t)
4523{
4524 struct device *dev = &priv->udev->dev;
4525 u32 i, val32;
4526 int path_a_ok, path_b_ok;
4527 int retry = 2;
4528 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4529 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4530 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4531 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4532 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4533 REG_TX_TO_TX, REG_RX_CCK,
4534 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4535 REG_RX_TO_RX, REG_STANDBY,
4536 REG_SLEEP, REG_PMPD_ANAEN
4537 };
4538 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4539 REG_TXPAUSE, REG_BEACON_CTRL,
4540 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4541 };
4542 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4543 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4544 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4545 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4546 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4547 };
4548
4549 /*
4550 * Note: IQ calibration must be performed after loading
4551 * PHY_REG.txt , and radio_a, radio_b.txt
4552 */
4553
4554 if (t == 0) {
4555 /* Save ADDA parameters, turn Path A ADDA on */
4556 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4557 RTL8XXXU_ADDA_REGS);
4558 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4559 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4560 priv->bb_backup, RTL8XXXU_BB_REGS);
4561 }
4562
4563 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4564
4565 if (t == 0) {
4566 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4567 if (val32 & FPGA0_HSSI_PARM1_PI)
4568 priv->pi_enabled = 1;
4569 }
4570
4571 if (!priv->pi_enabled) {
4572 /* Switch BB to PI mode to do IQ Calibration. */
4573 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4574 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4575 }
4576
4577 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4578 val32 &= ~FPGA_RF_MODE_CCK;
4579 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4580
4581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4582 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4583 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4584
Jes Sorensencabb5502016-04-14 16:37:17 -0400[diff] [blame]4585 if (!priv->no_pape) {
4586 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4587 val32 |= (FPGA0_RF_PAPE |
4588 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4589 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4590 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4591
4592 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4593 val32 &= ~BIT(10);
4594 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4595 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4596 val32 &= ~BIT(10);
4597 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4598
4599 if (priv->tx_paths > 1) {
4600 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4601 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4602 }
4603
4604 /* MAC settings */
4605 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4606
4607 /* Page B init */
4608 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4609
4610 if (priv->tx_paths > 1)
4611 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4612
4613 /* IQ calibration setting */
4614 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4615 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4616 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4617
4618 for (i = 0; i < retry; i++) {
4619 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4620 if (path_a_ok == 0x03) {
4621 val32 = rtl8xxxu_read32(priv,
4622 REG_TX_POWER_BEFORE_IQK_A);
4623 result[t][0] = (val32 >> 16) & 0x3ff;
4624 val32 = rtl8xxxu_read32(priv,
4625 REG_TX_POWER_AFTER_IQK_A);
4626 result[t][1] = (val32 >> 16) & 0x3ff;
4627 val32 = rtl8xxxu_read32(priv,
4628 REG_RX_POWER_BEFORE_IQK_A_2);
4629 result[t][2] = (val32 >> 16) & 0x3ff;
4630 val32 = rtl8xxxu_read32(priv,
4631 REG_RX_POWER_AFTER_IQK_A_2);
4632 result[t][3] = (val32 >> 16) & 0x3ff;
4633 break;
4634 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4635 /* TX IQK OK */
4636 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4637 __func__);
4638
4639 val32 = rtl8xxxu_read32(priv,
4640 REG_TX_POWER_BEFORE_IQK_A);
4641 result[t][0] = (val32 >> 16) & 0x3ff;
4642 val32 = rtl8xxxu_read32(priv,
4643 REG_TX_POWER_AFTER_IQK_A);
4644 result[t][1] = (val32 >> 16) & 0x3ff;
4645 }
4646 }
4647
4648 if (!path_a_ok)
4649 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4650
4651 if (priv->tx_paths > 1) {
4652 /*
4653 * Path A into standby
4654 */
4655 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4656 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4657 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4658
4659 /* Turn Path B ADDA on */
4660 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4661
4662 for (i = 0; i < retry; i++) {
4663 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4664 if (path_b_ok == 0x03) {
4665 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4666 result[t][4] = (val32 >> 16) & 0x3ff;
4667 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4668 result[t][5] = (val32 >> 16) & 0x3ff;
4669 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4670 result[t][6] = (val32 >> 16) & 0x3ff;
4671 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4672 result[t][7] = (val32 >> 16) & 0x3ff;
4673 break;
4674 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4675 /* TX IQK OK */
4676 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4677 result[t][4] = (val32 >> 16) & 0x3ff;
4678 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4679 result[t][5] = (val32 >> 16) & 0x3ff;
4680 }
4681 }
4682
4683 if (!path_b_ok)
4684 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4685 }
4686
4687 /* Back to BB mode, load original value */
4688 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4689
4690 if (t) {
4691 if (!priv->pi_enabled) {
4692 /*
4693 * Switch back BB to SI mode after finishing
4694 * IQ Calibration
4695 */
4696 val32 = 0x01000000;
4697 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4698 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4699 }
4700
4701 /* Reload ADDA power saving parameters */
4702 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4703 RTL8XXXU_ADDA_REGS);
4704
4705 /* Reload MAC parameters */
4706 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4707
4708 /* Reload BB parameters */
4709 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4710 priv->bb_backup, RTL8XXXU_BB_REGS);
4711
4712 /* Restore RX initial gain */
4713 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4714
4715 if (priv->tx_paths > 1) {
4716 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4717 0x00032ed3);
4718 }
4719
4720 /* Load 0xe30 IQC default value */
4721 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4722 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4723 }
4724}
4725
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]4726static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4727 int result[][8], int t)
4728{
4729 struct device *dev = &priv->udev->dev;
4730 u32 i, val32;
4731 int path_a_ok /*, path_b_ok */;
4732 int retry = 2;
4733 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4734 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4735 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4736 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4737 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4738 REG_TX_TO_TX, REG_RX_CCK,
4739 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4740 REG_RX_TO_RX, REG_STANDBY,
4741 REG_SLEEP, REG_PMPD_ANAEN
4742 };
4743 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4744 REG_TXPAUSE, REG_BEACON_CTRL,
4745 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4746 };
4747 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4748 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4749 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4750 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4751 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4752 };
4753 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4754 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4755
4756 /*
4757 * Note: IQ calibration must be performed after loading
4758 * PHY_REG.txt , and radio_a, radio_b.txt
4759 */
4760
4761 if (t == 0) {
4762 /* Save ADDA parameters, turn Path A ADDA on */
4763 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4764 RTL8XXXU_ADDA_REGS);
4765 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4766 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4767 priv->bb_backup, RTL8XXXU_BB_REGS);
4768 }
4769
4770 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4771
4772 /* MAC settings */
4773 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4774
4775 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4776 val32 |= 0x0f000000;
4777 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4778
4779 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4780 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4781 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4782
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]4783 /*
4784 * RX IQ calibration setting for 8723B D cut large current issue
4785 * when leaving IPS
4786 */
4787 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4788 val32 &= 0x000000ff;
4789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4790
4791 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4792 val32 |= 0x80000;
4793 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4794
4795 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4796 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4797 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4798
4799 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4800 val32 |= 0x20;
4801 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4802
4803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4804
4805 for (i = 0; i < retry; i++) {
4806 path_a_ok = rtl8723bu_iqk_path_a(priv);
4807 if (path_a_ok == 0x01) {
4808 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4809 val32 &= 0x000000ff;
4810 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4811
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]4812 val32 = rtl8xxxu_read32(priv,
4813 REG_TX_POWER_BEFORE_IQK_A);
4814 result[t][0] = (val32 >> 16) & 0x3ff;
4815 val32 = rtl8xxxu_read32(priv,
4816 REG_TX_POWER_AFTER_IQK_A);
4817 result[t][1] = (val32 >> 16) & 0x3ff;
4818
4819 break;
4820 }
4821 }
4822
4823 if (!path_a_ok)
4824 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4825
4826 for (i = 0; i < retry; i++) {
4827 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4828 if (path_a_ok == 0x03) {
4829 val32 = rtl8xxxu_read32(priv,
4830 REG_RX_POWER_BEFORE_IQK_A_2);
4831 result[t][2] = (val32 >> 16) & 0x3ff;
4832 val32 = rtl8xxxu_read32(priv,
4833 REG_RX_POWER_AFTER_IQK_A_2);
4834 result[t][3] = (val32 >> 16) & 0x3ff;
4835
4836 break;
4837 }
4838 }
4839
4840 if (!path_a_ok)
4841 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4842
4843 if (priv->tx_paths > 1) {
4844#if 1
4845 dev_warn(dev, "%s: Path B not supported\n", __func__);
4846#else
4847
4848 /*
4849 * Path A into standby
4850 */
4851 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4852 val32 &= 0x000000ff;
4853 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4854 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4855
4856 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4857 val32 &= 0x000000ff;
4858 val32 |= 0x80800000;
4859 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4860
4861 /* Turn Path B ADDA on */
4862 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4863
4864 for (i = 0; i < retry; i++) {
4865 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4866 if (path_b_ok == 0x03) {
4867 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4868 result[t][4] = (val32 >> 16) & 0x3ff;
4869 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4870 result[t][5] = (val32 >> 16) & 0x3ff;
4871 break;
4872 }
4873 }
4874
4875 if (!path_b_ok)
4876 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4877
4878 for (i = 0; i < retry; i++) {
4879 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4880 if (path_a_ok == 0x03) {
4881 val32 = rtl8xxxu_read32(priv,
4882 REG_RX_POWER_BEFORE_IQK_B_2);
4883 result[t][6] = (val32 >> 16) & 0x3ff;
4884 val32 = rtl8xxxu_read32(priv,
4885 REG_RX_POWER_AFTER_IQK_B_2);
4886 result[t][7] = (val32 >> 16) & 0x3ff;
4887 break;
4888 }
4889 }
4890
4891 if (!path_b_ok)
4892 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4893#endif
4894 }
4895
4896 /* Back to BB mode, load original value */
4897 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4898 val32 &= 0x000000ff;
4899 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4900
4901 if (t) {
4902 /* Reload ADDA power saving parameters */
4903 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4904 RTL8XXXU_ADDA_REGS);
4905
4906 /* Reload MAC parameters */
4907 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4908
4909 /* Reload BB parameters */
4910 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4911 priv->bb_backup, RTL8XXXU_BB_REGS);
4912
4913 /* Restore RX initial gain */
4914 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4915 val32 &= 0xffffff00;
4916 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4917 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4918
4919 if (priv->tx_paths > 1) {
4920 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4921 val32 &= 0xffffff00;
4922 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4923 val32 | 0x50);
4924 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4925 val32 | xb_agc);
4926 }
4927
4928 /* Load 0xe30 IQC default value */
4929 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4930 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4931 }
4932}
4933
Jes Sorensenc7a5a192016-02-29 17:04:30 -0500[diff] [blame]4934static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4935{
4936 struct h2c_cmd h2c;
4937
4938 if (priv->fops->mbox_ext_width < 4)
4939 return;
4940
4941 memset(&h2c, 0, sizeof(struct h2c_cmd));
4942 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4943 h2c.bt_wlan_calibration.data = start;
4944
4945 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4946}
4947
Jes Sorensen28466e92016-04-18 11:49:29 -0400[diff] [blame]4948static void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4949{
4950 struct device *dev = &priv->udev->dev;
4951 int result[4][8]; /* last is final result */
4952 int i, candidate;
4953 bool path_a_ok, path_b_ok;
4954 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4955 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4956 s32 reg_tmp = 0;
4957 bool simu;
4958
Jes Sorensenc7a5a192016-02-29 17:04:30 -0500[diff] [blame]4959 rtl8xxxu_prepare_calibrate(priv, 1);
4960
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4961 memset(result, 0, sizeof(result));
4962 candidate = -1;
4963
4964 path_a_ok = false;
4965 path_b_ok = false;
4966
4967 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4968
4969 for (i = 0; i < 3; i++) {
4970 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4971
4972 if (i == 1) {
4973 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4974 if (simu) {
4975 candidate = 0;
4976 break;
4977 }
4978 }
4979
4980 if (i == 2) {
4981 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4982 if (simu) {
4983 candidate = 0;
4984 break;
4985 }
4986
4987 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4988 if (simu) {
4989 candidate = 1;
4990 } else {
4991 for (i = 0; i < 8; i++)
4992 reg_tmp += result[3][i];
4993
4994 if (reg_tmp)
4995 candidate = 3;
4996 else
4997 candidate = -1;
4998 }
4999 }
5000 }
5001
5002 for (i = 0; i < 4; i++) {
5003 reg_e94 = result[i][0];
5004 reg_e9c = result[i][1];
5005 reg_ea4 = result[i][2];
5006 reg_eac = result[i][3];
5007 reg_eb4 = result[i][4];
5008 reg_ebc = result[i][5];
5009 reg_ec4 = result[i][6];
5010 reg_ecc = result[i][7];
5011 }
5012
5013 if (candidate >= 0) {
5014 reg_e94 = result[candidate][0];
5015 priv->rege94 = reg_e94;
5016 reg_e9c = result[candidate][1];
5017 priv->rege9c = reg_e9c;
5018 reg_ea4 = result[candidate][2];
5019 reg_eac = result[candidate][3];
5020 reg_eb4 = result[candidate][4];
5021 priv->regeb4 = reg_eb4;
5022 reg_ebc = result[candidate][5];
5023 priv->regebc = reg_ebc;
5024 reg_ec4 = result[candidate][6];
5025 reg_ecc = result[candidate][7];
5026 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5027 dev_dbg(dev,
5028 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5029 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5030 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5031 path_a_ok = true;
5032 path_b_ok = true;
5033 } else {
5034 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5035 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5036 }
5037
5038 if (reg_e94 && candidate >= 0)
5039 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5040 candidate, (reg_ea4 == 0));
5041
5042 if (priv->tx_paths > 1 && reg_eb4)
5043 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5044 candidate, (reg_ec4 == 0));
5045
Jes Sorensen04a74a92016-04-18 11:49:36 -0400[diff] [blame]5046 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5047 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
Jes Sorensenc7a5a192016-02-29 17:04:30 -0500[diff] [blame]5048
5049 rtl8xxxu_prepare_calibrate(priv, 0);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5050}
5051
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5052static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
5053{
5054 struct device *dev = &priv->udev->dev;
5055 int result[4][8]; /* last is final result */
5056 int i, candidate;
5057 bool path_a_ok, path_b_ok;
5058 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
5059 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
5060 u32 val32, bt_control;
5061 s32 reg_tmp = 0;
5062 bool simu;
5063
5064 rtl8xxxu_prepare_calibrate(priv, 1);
5065
5066 memset(result, 0, sizeof(result));
5067 candidate = -1;
5068
5069 path_a_ok = false;
5070 path_b_ok = false;
5071
5072 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
5073
5074 for (i = 0; i < 3; i++) {
5075 rtl8723bu_phy_iqcalibrate(priv, result, i);
5076
5077 if (i == 1) {
Jes Sorensen85f46632016-04-18 11:49:35 -0400[diff] [blame]5078 simu = rtl8xxxu_gen2_simularity_compare(priv,
5079 result, 0, 1);
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5080 if (simu) {
5081 candidate = 0;
5082 break;
5083 }
5084 }
5085
5086 if (i == 2) {
Jes Sorensen85f46632016-04-18 11:49:35 -0400[diff] [blame]5087 simu = rtl8xxxu_gen2_simularity_compare(priv,
5088 result, 0, 2);
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5089 if (simu) {
5090 candidate = 0;
5091 break;
5092 }
5093
Jes Sorensen85f46632016-04-18 11:49:35 -0400[diff] [blame]5094 simu = rtl8xxxu_gen2_simularity_compare(priv,
5095 result, 1, 2);
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5096 if (simu) {
5097 candidate = 1;
5098 } else {
5099 for (i = 0; i < 8; i++)
5100 reg_tmp += result[3][i];
5101
5102 if (reg_tmp)
5103 candidate = 3;
5104 else
5105 candidate = -1;
5106 }
5107 }
5108 }
5109
5110 for (i = 0; i < 4; i++) {
5111 reg_e94 = result[i][0];
5112 reg_e9c = result[i][1];
5113 reg_ea4 = result[i][2];
5114 reg_eac = result[i][3];
5115 reg_eb4 = result[i][4];
5116 reg_ebc = result[i][5];
5117 reg_ec4 = result[i][6];
5118 reg_ecc = result[i][7];
5119 }
5120
5121 if (candidate >= 0) {
5122 reg_e94 = result[candidate][0];
5123 priv->rege94 = reg_e94;
5124 reg_e9c = result[candidate][1];
5125 priv->rege9c = reg_e9c;
5126 reg_ea4 = result[candidate][2];
5127 reg_eac = result[candidate][3];
5128 reg_eb4 = result[candidate][4];
5129 priv->regeb4 = reg_eb4;
5130 reg_ebc = result[candidate][5];
5131 priv->regebc = reg_ebc;
5132 reg_ec4 = result[candidate][6];
5133 reg_ecc = result[candidate][7];
5134 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5135 dev_dbg(dev,
5136 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5137 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5138 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5139 path_a_ok = true;
5140 path_b_ok = true;
5141 } else {
5142 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5143 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5144 }
5145
5146 if (reg_e94 && candidate >= 0)
5147 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5148 candidate, (reg_ea4 == 0));
5149
5150 if (priv->tx_paths > 1 && reg_eb4)
5151 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5152 candidate, (reg_ec4 == 0));
5153
Jes Sorensen04a74a92016-04-18 11:49:36 -0400[diff] [blame]5154 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5155 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5156
5157 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5158
5159 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5160 val32 |= 0x80000;
5161 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5162 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5163 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5164 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5165 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5166 val32 |= 0x20;
5167 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5168 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5169
Jes Sorensen15f9dc92016-04-14 14:58:54 -0400[diff] [blame]5170 if (priv->rf_paths > 1)
5171 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
5172
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]5173 rtl8xxxu_prepare_calibrate(priv, 0);
5174}
5175
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5176static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5177{
5178 u32 val32;
5179 u32 rf_amode, rf_bmode = 0, lstf;
5180
5181 /* Check continuous TX and Packet TX */
5182 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5183
5184 if (lstf & OFDM_LSTF_MASK) {
5185 /* Disable all continuous TX */
5186 val32 = lstf & ~OFDM_LSTF_MASK;
5187 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5188
5189 /* Read original RF mode Path A */
5190 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5191
5192 /* Set RF mode to standby Path A */
5193 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5194 (rf_amode & 0x8ffff) | 0x10000);
5195
5196 /* Path-B */
5197 if (priv->tx_paths > 1) {
5198 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5199 RF6052_REG_AC);
5200
5201 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5202 (rf_bmode & 0x8ffff) | 0x10000);
5203 }
5204 } else {
5205 /* Deal with Packet TX case */
5206 /* block all queues */
5207 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5208 }
5209
5210 /* Start LC calibration */
Jes Sorensen0d698de2016-02-29 17:04:36 -0500[diff] [blame]5211 if (priv->fops->has_s0s1)
5212 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5213 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5214 val32 |= 0x08000;
5215 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5216
5217 msleep(100);
5218
Jes Sorensen0d698de2016-02-29 17:04:36 -0500[diff] [blame]5219 if (priv->fops->has_s0s1)
5220 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5221
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5222 /* Restore original parameters */
5223 if (lstf & OFDM_LSTF_MASK) {
5224 /* Path-A */
5225 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5226 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5227
5228 /* Path-B */
5229 if (priv->tx_paths > 1)
5230 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5231 rf_bmode);
5232 } else /* Deal with Packet TX case */
5233 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5234}
5235
5236static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5237{
5238 int i;
5239 u16 reg;
5240
5241 reg = REG_MACID;
5242
5243 for (i = 0; i < ETH_ALEN; i++)
5244 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5245
5246 return 0;
5247}
5248
5249static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5250{
5251 int i;
5252 u16 reg;
5253
5254 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5255
5256 reg = REG_BSSID;
5257
5258 for (i = 0; i < ETH_ALEN; i++)
5259 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5260
5261 return 0;
5262}
5263
5264static void
5265rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5266{
5267 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5268 u8 max_agg = 0xf;
5269 int i;
5270
5271 ampdu_factor = 1 << (ampdu_factor + 2);
5272 if (ampdu_factor > max_agg)
5273 ampdu_factor = max_agg;
5274
5275 for (i = 0; i < 4; i++) {
5276 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5277 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5278
5279 if ((vals[i] & 0x0f) > ampdu_factor)
5280 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5281
5282 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5283 }
5284}
5285
5286static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5287{
5288 u8 val8;
5289
5290 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5291 val8 &= 0xf8;
5292 val8 |= density;
5293 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5294}
5295
5296static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5297{
5298 u8 val8;
Colin Ian King37ba4b62016-04-14 16:37:07 -0400[diff] [blame]5299 int count, ret = 0;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5300
5301 /* Start of rtl8723AU_card_enable_flow */
5302 /* Act to Cardemu sequence*/
5303 /* Turn off RF */
5304 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5305
5306 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5307 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5308 val8 &= ~LEDCFG2_DPDT_SELECT;
5309 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5310
5311 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5312 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5313 val8 |= BIT(1);
5314 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5315
5316 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5317 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5318 if ((val8 & BIT(1)) == 0)
5319 break;
5320 udelay(10);
5321 }
5322
5323 if (!count) {
5324 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5325 __func__);
5326 ret = -EBUSY;
5327 goto exit;
5328 }
5329
5330 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5331 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5332 val8 |= SYS_ISO_ANALOG_IPS;
5333 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5334
5335 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5336 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5337 val8 &= ~LDOA15_ENABLE;
5338 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5339
5340exit:
5341 return ret;
5342}
5343
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]5344static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
5345{
5346 u8 val8;
5347 u16 val16;
5348 u32 val32;
Colin Ian King37ba4b62016-04-14 16:37:07 -0400[diff] [blame]5349 int count, ret = 0;
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]5350
5351 /* Turn off RF */
5352 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5353
5354 /* Enable rising edge triggering interrupt */
5355 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
5356 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
5357 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
5358
5359 /* Release WLON reset 0x04[16]= 1*/
Jes Sorensen8e254962016-04-14 16:37:12 -0400[diff] [blame]5360 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]5361 val32 |= APS_FSMCO_WLON_RESET;
Jes Sorensen8e254962016-04-14 16:37:12 -0400[diff] [blame]5362 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]5363
5364 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5365 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5366 val8 |= BIT(1);
5367 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5368
5369 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5370 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5371 if ((val8 & BIT(1)) == 0)
5372 break;
5373 udelay(10);
5374 }
5375
5376 if (!count) {
5377 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5378 __func__);
5379 ret = -EBUSY;
5380 goto exit;
5381 }
5382
5383 /* Enable BT control XTAL setting */
5384 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5385 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
5386 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5387
5388 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5389 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5390 val8 |= SYS_ISO_ANALOG_IPS;
5391 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5392
5393 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5394 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5395 val8 &= ~LDOA15_ENABLE;
5396 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5397
5398exit:
5399 return ret;
5400}
5401
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5402static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5403{
5404 u8 val8;
5405 u8 val32;
Colin Ian King37ba4b62016-04-14 16:37:07 -0400[diff] [blame]5406 int count, ret = 0;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5407
5408 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5409
5410 /*
5411 * Poll - wait for RX packet to complete
5412 */
5413 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5414 val32 = rtl8xxxu_read32(priv, 0x5f8);
5415 if (!val32)
5416 break;
5417 udelay(10);
5418 }
5419
5420 if (!count) {
5421 dev_warn(&priv->udev->dev,
5422 "%s: RX poll timed out (0x05f8)\n", __func__);
5423 ret = -EBUSY;
5424 goto exit;
5425 }
5426
5427 /* Disable CCK and OFDM, clock gated */
5428 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5429 val8 &= ~SYS_FUNC_BBRSTB;
5430 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5431
5432 udelay(2);
5433
5434 /* Reset baseband */
5435 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5436 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5437 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5438
5439 /* Reset MAC TRX */
5440 val8 = rtl8xxxu_read8(priv, REG_CR);
5441 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5442 rtl8xxxu_write8(priv, REG_CR, val8);
5443
5444 /* Reset MAC TRX */
5445 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5446 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5447 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5448
5449 /* Respond TX OK to scheduler */
5450 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5451 val8 |= DUAL_TSF_TX_OK;
5452 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5453
5454exit:
5455 return ret;
5456}
5457
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]5458static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5459{
5460 u8 val8;
5461
5462 /* Clear suspend enable and power down enable*/
5463 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5464 val8 &= ~(BIT(3) | BIT(7));
5465 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5466
5467 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5468 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5469 val8 &= ~BIT(0);
5470 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5471
5472 /* 0x04[12:11] = 11 enable WL suspend*/
5473 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5474 val8 &= ~(BIT(3) | BIT(4));
5475 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5476}
5477
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]5478static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5479{
5480 u8 val8;
5481 u32 val32;
5482 int count, ret = 0;
5483
5484 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5485 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5486 val8 |= LDOA15_ENABLE;
5487 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5488
5489 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5490 val8 = rtl8xxxu_read8(priv, 0x0067);
5491 val8 &= ~BIT(4);
5492 rtl8xxxu_write8(priv, 0x0067, val8);
5493
5494 mdelay(1);
5495
5496 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5497 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5498 val8 &= ~SYS_ISO_ANALOG_IPS;
5499 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5500
5501 /* disable SW LPS 0x04[10]= 0 */
5502 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5503 val8 &= ~BIT(2);
5504 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5505
5506 /* wait till 0x04[17] = 1 power ready*/
5507 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5508 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5509 if (val32 & BIT(17))
5510 break;
5511
5512 udelay(10);
5513 }
5514
5515 if (!count) {
5516 ret = -EBUSY;
5517 goto exit;
5518 }
5519
5520 /* We should be able to optimize the following three entries into one */
5521
5522 /* release WLON reset 0x04[16]= 1*/
5523 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5524 val8 |= BIT(0);
5525 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5526
5527 /* disable HWPDN 0x04[15]= 0*/
5528 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5529 val8 &= ~BIT(7);
5530 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5531
5532 /* disable WL suspend*/
5533 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5534 val8 &= ~(BIT(3) | BIT(4));
5535 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5536
5537 /* set, then poll until 0 */
5538 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5539 val32 |= APS_FSMCO_MAC_ENABLE;
5540 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5541
5542 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5543 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5544 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5545 ret = 0;
5546 break;
5547 }
5548 udelay(10);
5549 }
5550
5551 if (!count) {
5552 ret = -EBUSY;
5553 goto exit;
5554 }
5555
5556 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5557 /*
5558 * Note: Vendor driver actually clears this bit, despite the
5559 * documentation claims it's being set!
5560 */
5561 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5562 val8 |= LEDCFG2_DPDT_SELECT;
5563 val8 &= ~LEDCFG2_DPDT_SELECT;
5564 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5565
5566exit:
5567 return ret;
5568}
5569
Jes Sorensen42836db2016-02-29 17:04:52 -0500[diff] [blame]5570static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5571{
5572 u8 val8;
5573 u32 val32;
5574 int count, ret = 0;
5575
5576 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5577 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5578 val8 |= LDOA15_ENABLE;
5579 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5580
5581 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5582 val8 = rtl8xxxu_read8(priv, 0x0067);
5583 val8 &= ~BIT(4);
5584 rtl8xxxu_write8(priv, 0x0067, val8);
5585
5586 mdelay(1);
5587
5588 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5589 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5590 val8 &= ~SYS_ISO_ANALOG_IPS;
5591 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5592
5593 /* Disable SW LPS 0x04[10]= 0 */
5594 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5595 val32 &= ~APS_FSMCO_SW_LPS;
5596 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5597
5598 /* Wait until 0x04[17] = 1 power ready */
5599 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5600 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5601 if (val32 & BIT(17))
5602 break;
5603
5604 udelay(10);
5605 }
5606
5607 if (!count) {
5608 ret = -EBUSY;
5609 goto exit;
5610 }
5611
5612 /* We should be able to optimize the following three entries into one */
5613
5614 /* Release WLON reset 0x04[16]= 1*/
5615 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5616 val32 |= APS_FSMCO_WLON_RESET;
5617 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5618
5619 /* Disable HWPDN 0x04[15]= 0*/
5620 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5621 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5622 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5623
5624 /* Disable WL suspend*/
5625 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5626 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5627 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5628
5629 /* Set, then poll until 0 */
5630 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5631 val32 |= APS_FSMCO_MAC_ENABLE;
5632 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5633
5634 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5635 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5636 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5637 ret = 0;
5638 break;
5639 }
5640 udelay(10);
5641 }
5642
5643 if (!count) {
5644 ret = -EBUSY;
5645 goto exit;
5646 }
5647
5648 /* Enable WL control XTAL setting */
5649 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5650 val8 |= AFE_MISC_WL_XTAL_CTRL;
5651 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5652
5653 /* Enable falling edge triggering interrupt */
5654 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5655 val8 |= BIT(1);
5656 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5657
5658 /* Enable GPIO9 interrupt mode */
5659 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5660 val8 |= BIT(1);
5661 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5662
5663 /* Enable GPIO9 input mode */
5664 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5665 val8 &= ~BIT(1);
5666 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5667
5668 /* Enable HSISR GPIO[C:0] interrupt */
5669 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5670 val8 |= BIT(0);
5671 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5672
5673 /* Enable HSISR GPIO9 interrupt */
5674 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5675 val8 |= BIT(1);
5676 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5677
5678 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5679 val8 |= MULTI_WIFI_HW_ROF_EN;
5680 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5681
5682 /* For GPIO9 internal pull high setting BIT(14) */
5683 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5684 val8 |= BIT(6);
5685 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5686
5687exit:
5688 return ret;
5689}
5690
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5691static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5692{
5693 u8 val8;
5694
5695 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5696 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5697
5698 /* 0x04[12:11] = 01 enable WL suspend */
5699 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5700 val8 &= ~BIT(4);
5701 val8 |= BIT(3);
5702 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5703
5704 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5705 val8 |= BIT(7);
5706 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5707
5708 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5709 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5710 val8 |= BIT(0);
5711 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5712
5713 return 0;
5714}
5715
Jes Sorensen430b4542016-02-29 17:05:48 -0500[diff] [blame]5716static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
5717{
Jes Sorensen145428e2016-02-29 17:05:49 -0500[diff] [blame]5718 struct device *dev = &priv->udev->dev;
Jes Sorensen430b4542016-02-29 17:05:48 -0500[diff] [blame]5719 u32 val32;
5720 int retry, retval;
5721
5722 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5723
5724 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5725 val32 |= RXPKT_NUM_RW_RELEASE_EN;
5726 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
5727
5728 retry = 100;
5729 retval = -EBUSY;
5730
5731 do {
5732 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
5733 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
5734 retval = 0;
5735 break;
5736 }
5737 } while (retry--);
5738
5739 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
5740 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
5741 mdelay(2);
Jes Sorensen145428e2016-02-29 17:05:49 -0500[diff] [blame]5742
5743 if (!retry)
5744 dev_warn(dev, "Failed to flush FIFO\n");
Jes Sorensen430b4542016-02-29 17:05:48 -0500[diff] [blame]5745
5746 return retval;
5747}
5748
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]5749static void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
5750{
5751 /* Fix USB interface interference issue */
5752 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5753 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
5754 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5755 /*
5756 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
5757 * 8 and 5, for which I have found no documentation.
5758 */
5759 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
5760
5761 /*
5762 * Solve too many protocol error on USB bus.
5763 * Can't do this for 8188/8192 UMC A cut parts
5764 */
5765 if (!(!priv->chip_cut && priv->vendor_umc)) {
5766 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
5767 rtl8xxxu_write8(priv, 0xfe41, 0x94);
5768 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5769
5770 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5771 rtl8xxxu_write8(priv, 0xfe41, 0x19);
5772 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5773
5774 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
5775 rtl8xxxu_write8(priv, 0xfe41, 0x91);
5776 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5777
5778 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
5779 rtl8xxxu_write8(priv, 0xfe41, 0x81);
5780 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5781 }
5782}
5783
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]5784void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]5785{
5786 u32 val32;
5787
5788 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
5789 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
5790 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
5791}
5792
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5793static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5794{
5795 u8 val8;
5796 u16 val16;
5797 u32 val32;
5798 int ret;
5799
5800 /*
5801 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5802 */
5803 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5804
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]5805 rtl8723a_disabled_to_emu(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5806
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]5807 ret = rtl8723a_emu_to_active(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5808 if (ret)
5809 goto exit;
5810
5811 /*
5812 * 0x0004[19] = 1, reset 8051
5813 */
5814 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5815 val8 |= BIT(3);
5816 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5817
5818 /*
5819 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5820 * Set CR bit10 to enable 32k calibration.
5821 */
5822 val16 = rtl8xxxu_read16(priv, REG_CR);
5823 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5824 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5825 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5826 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5827 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5828 rtl8xxxu_write16(priv, REG_CR, val16);
5829
5830 /* For EFuse PG */
5831 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5832 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5833 val32 |= (0x06 << 28);
5834 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5835exit:
5836 return ret;
5837}
5838
Jes Sorensen42836db2016-02-29 17:04:52 -0500[diff] [blame]5839static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5840{
5841 u8 val8;
5842 u16 val16;
5843 u32 val32;
5844 int ret;
5845
5846 rtl8723a_disabled_to_emu(priv);
5847
5848 ret = rtl8723b_emu_to_active(priv);
5849 if (ret)
5850 goto exit;
5851
5852 /*
5853 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5854 * Set CR bit10 to enable 32k calibration.
5855 */
5856 val16 = rtl8xxxu_read16(priv, REG_CR);
5857 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5858 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5859 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5860 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5861 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5862 rtl8xxxu_write16(priv, REG_CR, val16);
5863
5864 /*
5865 * BT coexist power on settings. This is identical for 1 and 2
5866 * antenna parts.
5867 */
5868 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5869
5870 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5871 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5872 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5873
5874 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5875 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5876 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5877 /* Antenna inverse */
5878 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5879
5880 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5881 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5882 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5883
5884 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5885 val32 |= LEDCFG0_DPDT_SELECT;
5886 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5887
5888 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5889 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5890 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5891exit:
5892 return ret;
5893}
5894
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5895#ifdef CONFIG_RTL8XXXU_UNTESTED
5896
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5897static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5898{
5899 u8 val8;
5900 u16 val16;
5901 u32 val32;
5902 int i;
5903
5904 for (i = 100; i; i--) {
5905 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5906 if (val8 & APS_FSMCO_PFM_ALDN)
5907 break;
5908 }
5909
5910 if (!i) {
5911 pr_info("%s: Poll failed\n", __func__);
5912 return -ENODEV;
5913 }
5914
5915 /*
5916 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5917 */
5918 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5919 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5920 udelay(100);
5921
5922 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5923 if (!(val8 & LDOV12D_ENABLE)) {
5924 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5925 val8 |= LDOV12D_ENABLE;
5926 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5927
5928 udelay(100);
5929
5930 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5931 val8 &= ~SYS_ISO_MD2PP;
5932 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5933 }
5934
5935 /*
5936 * Auto enable WLAN
5937 */
5938 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5939 val16 |= APS_FSMCO_MAC_ENABLE;
5940 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5941
5942 for (i = 1000; i; i--) {
5943 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5944 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5945 break;
5946 }
5947 if (!i) {
5948 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5949 return -EBUSY;
5950 }
5951
5952 /*
5953 * Enable radio, GPIO, LED
5954 */
5955 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5956 APS_FSMCO_PFM_ALDN;
5957 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5958
5959 /*
5960 * Release RF digital isolation
5961 */
5962 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5963 val16 &= ~SYS_ISO_DIOR;
5964 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5965
5966 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5967 val8 &= ~APSD_CTRL_OFF;
5968 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5969 for (i = 200; i; i--) {
5970 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5971 if (!(val8 & APSD_CTRL_OFF_STATUS))
5972 break;
5973 }
5974
5975 if (!i) {
5976 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5977 return -EBUSY;
5978 }
5979
5980 /*
5981 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5982 */
5983 val16 = rtl8xxxu_read16(priv, REG_CR);
5984 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5985 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5986 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5987 rtl8xxxu_write16(priv, REG_CR, val16);
5988
Jes Sorensenb9f9d692016-04-14 16:37:15 -0400[diff] [blame]5989 rtl8xxxu_write8(priv, 0xfe10, 0x19);
5990
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5991 /*
5992 * Workaround for 8188RU LNA power leakage problem.
5993 */
Jes Sorensen8d95c802016-04-14 16:37:11 -0400[diff] [blame]5994 if (priv->rtl_chip == RTL8188R) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5995 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5996 val32 &= ~BIT(1);
5997 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5998 }
5999 return 0;
6000}
6001
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]6002#endif
6003
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]6004void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6005{
6006 u8 val8;
6007 u16 val16;
6008 u32 val32;
6009
6010 /*
6011 * Workaround for 8188RU LNA power leakage problem.
6012 */
Jes Sorensen8d95c802016-04-14 16:37:11 -0400[diff] [blame]6013 if (priv->rtl_chip == RTL8188R) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6014 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
6015 val32 |= BIT(1);
6016 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
6017 }
6018
Jes Sorensen430b4542016-02-29 17:05:48 -0500[diff] [blame]6019 rtl8xxxu_flush_fifo(priv);
6020
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6021 rtl8xxxu_active_to_lps(priv);
6022
6023 /* Turn off RF */
6024 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
6025
6026 /* Reset Firmware if running in RAM */
6027 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6028 rtl8xxxu_firmware_self_reset(priv);
6029
6030 /* Reset MCU */
6031 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6032 val16 &= ~SYS_FUNC_CPU_ENABLE;
6033 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6034
6035 /* Reset MCU ready status */
6036 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6037
6038 rtl8xxxu_active_to_emu(priv);
6039 rtl8xxxu_emu_to_disabled(priv);
6040
6041 /* Reset MCU IO Wrapper */
6042 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6043 val8 &= ~BIT(0);
6044 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6045
6046 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
6047 val8 |= BIT(0);
6048 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
6049
6050 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
6051 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
6052}
6053
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]6054static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
6055{
6056 u8 val8;
6057 u16 val16;
6058
Jes Sorensen430b4542016-02-29 17:05:48 -0500[diff] [blame]6059 rtl8xxxu_flush_fifo(priv);
6060
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]6061 /*
6062 * Disable TX report timer
6063 */
6064 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6065 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
6066 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6067
Jes Sorensen8e254962016-04-14 16:37:12 -0400[diff] [blame]6068 rtl8xxxu_write8(priv, REG_CR, 0x0000);
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]6069
6070 rtl8xxxu_active_to_lps(priv);
6071
6072 /* Reset Firmware if running in RAM */
6073 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
6074 rtl8xxxu_firmware_self_reset(priv);
6075
6076 /* Reset MCU */
6077 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
6078 val16 &= ~SYS_FUNC_CPU_ENABLE;
6079 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
6080
6081 /* Reset MCU ready status */
6082 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
6083
6084 rtl8723bu_active_to_emu(priv);
Jes Sorensen8e254962016-04-14 16:37:12 -0400[diff] [blame]6085
6086 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6087 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
6088 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6089
6090 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
6091 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
6092 val8 |= BIT(0);
6093 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]6094}
6095
Jes Sorensena3a5dac2016-02-29 17:05:16 -0500[diff] [blame]6096#ifdef NEED_PS_TDMA
Jes Sorensen3ca7b322016-02-29 17:04:43 -0500[diff] [blame]6097static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
6098 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
6099{
6100 struct h2c_cmd h2c;
6101
6102 memset(&h2c, 0, sizeof(struct h2c_cmd));
6103 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
6104 h2c.b_type_dma.data1 = arg1;
6105 h2c.b_type_dma.data2 = arg2;
6106 h2c.b_type_dma.data3 = arg3;
6107 h2c.b_type_dma.data4 = arg4;
6108 h2c.b_type_dma.data5 = arg5;
6109 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
6110}
Jes Sorensena3a5dac2016-02-29 17:05:16 -0500[diff] [blame]6111#endif
Jes Sorensen3ca7b322016-02-29 17:04:43 -0500[diff] [blame]6112
Jes Sorensen0290e7d2016-02-29 17:05:44 -0500[diff] [blame]6113static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6114{
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6115 struct h2c_cmd h2c;
6116 u32 val32;
6117 u8 val8;
6118
6119 /*
6120 * No indication anywhere as to what 0x0790 does. The 2 antenna
6121 * vendor code preserves bits 6-7 here.
6122 */
6123 rtl8xxxu_write8(priv, 0x0790, 0x05);
6124 /*
6125 * 0x0778 seems to be related to enabling the number of antennas
6126 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
6127 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
6128 */
6129 rtl8xxxu_write8(priv, 0x0778, 0x01);
6130
6131 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
6132 val8 |= BIT(5);
6133 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
6134
6135 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
6136
Jes Sorensen394f1bd2016-02-29 17:04:49 -0500[diff] [blame]6137 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
6138
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6139 /*
6140 * Set BT grant to low
6141 */
6142 memset(&h2c, 0, sizeof(struct h2c_cmd));
6143 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
6144 h2c.bt_grant.data = 0;
6145 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
6146
6147 /*
6148 * WLAN action by PTA
6149 */
Jes Sorensenfc1c89b2016-02-29 17:05:12 -0500[diff] [blame]6150 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6151
6152 /*
6153 * BT select S0/S1 controlled by WiFi
6154 */
6155 val8 = rtl8xxxu_read8(priv, 0x0067);
6156 val8 |= BIT(5);
6157 rtl8xxxu_write8(priv, 0x0067, val8);
6158
6159 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
Jes Sorensen37f44dc2016-02-29 17:05:45 -0500[diff] [blame]6160 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6161 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
6162
6163 /*
6164 * Bits 6/7 are marked in/out ... but for what?
6165 */
6166 rtl8xxxu_write8(priv, 0x0974, 0xff);
6167
Jes Sorensen120e6272016-02-29 17:05:14 -0500[diff] [blame]6168 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6169 val32 |= (BIT(0) | BIT(1));
Jes Sorensen120e6272016-02-29 17:05:14 -0500[diff] [blame]6170 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
Jes Sorensenf37e9222016-02-29 17:04:41 -0500[diff] [blame]6171
6172 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6173
6174 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6175 val32 &= ~BIT(24);
6176 val32 |= BIT(23);
6177 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6178
6179 /*
6180 * Fix external switch Main->S1, Aux->S0
6181 */
6182 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6183 val8 &= ~BIT(0);
6184 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6185
6186 memset(&h2c, 0, sizeof(struct h2c_cmd));
6187 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6188 h2c.ant_sel_rsv.ant_inverse = 1;
6189 h2c.ant_sel_rsv.int_switch_type = 0;
6190 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6191
6192 /*
6193 * 0x280, 0x00, 0x200, 0x80 - not clear
6194 */
Jes Sorensen3ca7b322016-02-29 17:04:43 -0500[diff] [blame]6195 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6196
6197 /*
6198 * Software control, antenna at WiFi side
6199 */
Jes Sorensena3a5dac2016-02-29 17:05:16 -0500[diff] [blame]6200#ifdef NEED_PS_TDMA
Jes Sorensena228a5d2016-02-29 17:04:45 -0500[diff] [blame]6201 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
Jes Sorensena3a5dac2016-02-29 17:05:16 -0500[diff] [blame]6202#endif
6203
6204 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6205 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6206 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6207 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
Jes Sorensen3ca7b322016-02-29 17:04:43 -0500[diff] [blame]6208
Jes Sorensen6b9eae02016-02-29 17:04:50 -0500[diff] [blame]6209 memset(&h2c, 0, sizeof(struct h2c_cmd));
6210 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6211 h2c.bt_info.data = BIT(0);
6212 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6213
Jes Sorensen6b9eae02016-02-29 17:04:50 -0500[diff] [blame]6214 memset(&h2c, 0, sizeof(struct h2c_cmd));
6215 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6216 h2c.ignore_wlan.data = 0;
6217 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6218}
6219
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]6220void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
Jes Sorensenfc89a412016-02-29 17:05:46 -0500[diff] [blame]6221{
6222 u32 val32;
6223
Jes Sorensenfc89a412016-02-29 17:05:46 -0500[diff] [blame]6224 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
6225 val32 &= ~(BIT(22) | BIT(23));
6226 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
6227}
6228
Jes Sorensen3e88ca42016-02-29 17:05:08 -0500[diff] [blame]6229static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6230{
6231 u32 agg_rx;
6232 u8 agg_ctrl;
6233
6234 /*
6235 * For now simply disable RX aggregation
6236 */
6237 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6238 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6239
6240 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6241 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6242 agg_rx &= ~0xff0f;
6243
6244 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6245 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6246}
6247
Jes Sorensen9c79bf92016-02-29 17:05:10 -0500[diff] [blame]6248static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6249{
6250 u32 val32;
6251
6252 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6253 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6254 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6255 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6256 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6257 /* TH8 */
6258 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6259 val32 |= 0xff;
6260 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6261 /* Enable CCK */
6262 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6263 val32 |= BIT(8) | BIT(9) | BIT(10);
6264 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6265 /* Max power amongst all RX antennas */
6266 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6267 val32 |= BIT(7);
6268 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6269}
6270
Jes Sorensen89c2a092016-04-14 14:58:44 -0400[diff] [blame]6271static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
6272{
6273 u8 val8;
6274 u32 val32;
6275
6276 if (priv->ep_tx_normal_queue)
6277 val8 = TX_PAGE_NUM_NORM_PQ;
6278 else
6279 val8 = 0;
6280
6281 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6282
6283 val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD;
6284
6285 if (priv->ep_tx_high_queue)
6286 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6287 if (priv->ep_tx_low_queue)
6288 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6289
6290 rtl8xxxu_write32(priv, REG_RQPN, val32);
6291}
6292
6293static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
6294{
6295 struct rtl8xxxu_fileops *fops = priv->fops;
6296 u32 hq, lq, nq, eq, pubq;
6297 u32 val32;
6298
6299 hq = 0;
6300 lq = 0;
6301 nq = 0;
6302 eq = 0;
6303 pubq = 0;
6304
6305 if (priv->ep_tx_high_queue)
6306 hq = fops->page_num_hi;
6307 if (priv->ep_tx_low_queue)
6308 lq = fops->page_num_lo;
6309 if (priv->ep_tx_normal_queue)
6310 nq = fops->page_num_norm;
6311
6312 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
6313 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
6314
6315 pubq = fops->total_page_num - hq - lq - nq;
6316
6317 val32 = RQPN_LOAD;
6318 val32 |= (hq << RQPN_HI_PQ_SHIFT);
6319 val32 |= (lq << RQPN_LO_PQ_SHIFT);
6320 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
6321
6322 rtl8xxxu_write32(priv, REG_RQPN, val32);
6323}
6324
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6325static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6326{
6327 struct rtl8xxxu_priv *priv = hw->priv;
6328 struct device *dev = &priv->udev->dev;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6329 bool macpower;
6330 int ret;
6331 u8 val8;
6332 u16 val16;
6333 u32 val32;
6334
6335 /* Check if MAC is already powered on */
6336 val8 = rtl8xxxu_read8(priv, REG_CR);
6337
6338 /*
6339 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6340 * initialized. First MAC returns 0xea, second MAC returns 0x00
6341 */
6342 if (val8 == 0xea)
6343 macpower = false;
6344 else
6345 macpower = true;
6346
6347 ret = priv->fops->power_on(priv);
6348 if (ret < 0) {
6349 dev_warn(dev, "%s: Failed power on\n", __func__);
6350 goto exit;
6351 }
6352
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6353 if (!macpower) {
Jes Sorensen89c2a092016-04-14 14:58:44 -0400[diff] [blame]6354 if (priv->fops->total_page_num)
6355 rtl8xxxu_init_queue_reserved_page(priv);
Jes Sorensen59b24da2016-04-14 14:58:43 -0400[diff] [blame]6356 else
Jes Sorensen89c2a092016-04-14 14:58:44 -0400[diff] [blame]6357 rtl8xxxu_old_init_queue_reserved_page(priv);
Jes Sorensen07bb46b2016-02-29 17:04:05 -0500[diff] [blame]6358 }
6359
Jes Sorensen59b24da2016-04-14 14:58:43 -0400[diff] [blame]6360 ret = rtl8xxxu_init_queue_priority(priv);
6361 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6362 if (ret)
6363 goto exit;
6364
6365 /*
6366 * Set RX page boundary
6367 */
Jes Sorensen24e8e7e2016-04-14 14:59:01 -0400[diff] [blame]6368 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary);
Jes Sorensen59b24da2016-04-14 14:58:43 -0400[diff] [blame]6369
Jes Sorensena47b9d42016-02-29 17:04:06 -0500[diff] [blame]6370 ret = rtl8xxxu_download_firmware(priv);
6371 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6372 if (ret)
6373 goto exit;
6374 ret = rtl8xxxu_start_firmware(priv);
6375 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6376 if (ret)
6377 goto exit;
6378
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]6379 if (priv->fops->phy_init_antenna_selection)
6380 priv->fops->phy_init_antenna_selection(priv);
6381
Jes Sorensenc606e662016-04-07 14:19:16 -0400[diff] [blame]6382 ret = rtl8xxxu_init_mac(priv);
Jes Sorensenb7dd8ff2016-02-29 17:04:17 -0500[diff] [blame]6383
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6384 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6385 if (ret)
6386 goto exit;
6387
6388 ret = rtl8xxxu_init_phy_bb(priv);
6389 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6390 if (ret)
6391 goto exit;
6392
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]6393 ret = priv->fops->init_phy_rf(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6394 if (ret)
6395 goto exit;
6396
Jes Sorensenc1578632016-04-14 14:58:42 -0400[diff] [blame]6397 /* RFSW Control - clear bit 14 ?? */
Jes Sorensenb8169012016-04-14 14:58:47 -0400[diff] [blame]6398 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
Jes Sorensenc1578632016-04-14 14:58:42 -0400[diff] [blame]6399 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
Jes Sorensen31133da2016-04-14 14:59:05 -0400[diff] [blame]6400
6401 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
Jes Sorensencabb5502016-04-14 16:37:17 -0400[diff] [blame]6402 FPGA0_RF_ANTSWB |
6403 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
6404 if (!priv->no_pape) {
6405 val32 |= (FPGA0_RF_PAPE |
6406 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
6407 }
Jes Sorensenc1578632016-04-14 14:58:42 -0400[diff] [blame]6408 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
Jes Sorensencabb5502016-04-14 16:37:17 -0400[diff] [blame]6409
Jes Sorensenc1578632016-04-14 14:58:42 -0400[diff] [blame]6410 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6411 if (priv->rtl_chip != RTL8192E)
6412 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
6413
Jes Sorensenf2a41632016-02-29 17:05:09 -0500[diff] [blame]6414 if (!macpower) {
Jes Sorensen1f1b20f2016-02-29 17:05:00 -0500[diff] [blame]6415 /*
6416 * Set TX buffer boundary
6417 */
Jes Sorensen80805aa2016-04-07 14:19:18 -0400[diff] [blame]6418 if (priv->rtl_chip == RTL8192E)
6419 val8 = TX_TOTAL_PAGE_NUM_8192E + 1;
6420 else
6421 val8 = TX_TOTAL_PAGE_NUM + 1;
Jes Sorensen1f1b20f2016-02-29 17:05:00 -0500[diff] [blame]6422
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]6423 if (priv->rtl_chip == RTL8723B)
Jes Sorensen1f1b20f2016-02-29 17:05:00 -0500[diff] [blame]6424 val8 -= 1;
6425
6426 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6427 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6428 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6429 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6430 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6431 }
6432
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6433 /*
Jes Sorensen9b323ee2016-04-14 14:59:03 -0400[diff] [blame]6434 * The vendor drivers set PBP for all devices, except 8192e.
6435 * There is no explanation for this in any of the sources.
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6436 */
Jes Sorensen9b323ee2016-04-14 14:59:03 -0400[diff] [blame]6437 val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
6438 (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
Jes Sorensen2e7c7b32016-04-14 14:58:46 -0400[diff] [blame]6439 if (priv->rtl_chip != RTL8192E)
6440 rtl8xxxu_write8(priv, REG_PBP, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6441
Jes Sorensen59b24da2016-04-14 14:58:43 -0400[diff] [blame]6442 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6443 if (!macpower) {
6444 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6445 if (ret) {
6446 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6447 goto exit;
6448 }
6449
6450 /*
Jes Sorensen0486e802016-04-14 14:58:45 -0400[diff] [blame]6451 * Chip specific quirks
6452 */
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]6453 priv->fops->usb_quirks(priv);
Jes Sorensen0486e802016-04-14 14:58:45 -0400[diff] [blame]6454
6455 /*
Jes Sorensen59b24da2016-04-14 14:58:43 -0400[diff] [blame]6456 * Presumably this is for 8188EU as well
6457 * Enable TX report and TX report timer
6458 */
6459 if (priv->rtl_chip == RTL8723B) {
6460 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6461 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
6462 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6463 /* Set MAX RPT MACID */
6464 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6465 /* TX report Timer. Unit: 32us */
6466 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6467
6468 /* tmp ps ? */
6469 val8 = rtl8xxxu_read8(priv, 0xa3);
6470 val8 &= 0xf8;
6471 rtl8xxxu_write8(priv, 0xa3, val8);
6472 }
6473 }
6474
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6475 /*
6476 * Unit in 8 bytes, not obvious what it is used for
6477 */
6478 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6479
Jes Sorensen57e5e2e2016-04-07 14:19:27 -0400[diff] [blame]6480 if (priv->rtl_chip == RTL8192E) {
6481 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6482 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6483 } else {
6484 /*
6485 * Enable all interrupts - not obvious USB needs to do this
6486 */
6487 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6488 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6489 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6490
6491 rtl8xxxu_set_mac(priv);
6492 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6493
6494 /*
6495 * Configure initial WMAC settings
6496 */
6497 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6498 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6499 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6500 rtl8xxxu_write32(priv, REG_RCR, val32);
6501
6502 /*
6503 * Accept all multicast
6504 */
6505 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6506 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6507
6508 /*
6509 * Init adaptive controls
6510 */
6511 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6512 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6513 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6514 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6515
6516 /* CCK = 0x0a, OFDM = 0x10 */
6517 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6518 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6519 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6520
6521 /*
6522 * Init EDCA
6523 */
6524 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6525
6526 /* Set CCK SIFS */
6527 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6528
6529 /* Set OFDM SIFS */
6530 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6531
6532 /* TXOP */
6533 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6534 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6535 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6536 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6537
6538 /* Set data auto rate fallback retry count */
6539 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6540 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6541 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6542 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6543
6544 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6545 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6546 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6547
6548 /* Set ACK timeout */
6549 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6550
6551 /*
6552 * Initialize beacon parameters
6553 */
6554 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6555 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6556 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6557 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6558 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6559 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6560
6561 /*
Jes Sorensenc3690602016-02-29 17:05:03 -0500[diff] [blame]6562 * Initialize burst parameters
6563 */
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]6564 if (priv->rtl_chip == RTL8723B) {
Jes Sorensenc3690602016-02-29 17:05:03 -0500[diff] [blame]6565 /*
6566 * For USB high speed set 512B packets
6567 */
6568 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6569 val8 &= ~(BIT(4) | BIT(5));
6570 val8 |= BIT(4);
6571 val8 |= BIT(1) | BIT(2) | BIT(3);
6572 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6573
6574 /*
6575 * For USB high speed set 512B packets
6576 */
6577 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6578 val8 |= BIT(7);
6579 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6580
6581 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6582 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6583 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6584 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6585 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6586 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6587 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6588
6589 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6590 val8 |= BIT(5) | BIT(6);
6591 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6592 }
6593
Jes Sorensen3e88ca42016-02-29 17:05:08 -0500[diff] [blame]6594 if (priv->fops->init_aggregation)
6595 priv->fops->init_aggregation(priv);
6596
Jes Sorensenc3690602016-02-29 17:05:03 -0500[diff] [blame]6597 /*
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6598 * Enable CCK and OFDM block
6599 */
6600 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6601 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6602 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6603
6604 /*
6605 * Invalidate all CAM entries - bit 30 is undocumented
6606 */
6607 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6608
6609 /*
6610 * Start out with default power levels for channel 6, 20MHz
6611 */
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]6612 priv->fops->set_tx_power(priv, 1, false);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6613
6614 /* Let the 8051 take control of antenna setting */
Jes Sorensen5bdb6b02016-04-14 14:58:48 -0400[diff] [blame]6615 if (priv->rtl_chip != RTL8192E) {
6616 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6617 val8 |= LEDCFG2_DPDT_SELECT;
6618 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6619 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6620
6621 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6622
6623 /* Disable BAR - not sure if this has any effect on USB */
6624 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6625
6626 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6627
Jes Sorensen9c79bf92016-02-29 17:05:10 -0500[diff] [blame]6628 if (priv->fops->init_statistics)
6629 priv->fops->init_statistics(priv);
6630
Jes Sorensenb052b7f2016-04-07 14:19:30 -0400[diff] [blame]6631 if (priv->rtl_chip == RTL8192E) {
6632 /*
6633 * 0x4c6[3] 1: RTS BW = Data BW
6634 * 0: RTS BW depends on CCA / secondary CCA result.
6635 */
6636 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
6637 val8 &= ~BIT(3);
6638 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
6639 /*
6640 * Reset USB mode switch setting
6641 */
6642 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
6643 }
6644
Jes Sorensenfa0f2d42016-02-29 17:04:37 -0500[diff] [blame]6645 rtl8723a_phy_lc_calibrate(priv);
6646
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]6647 priv->fops->phy_iq_calibrate(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6648
6649 /*
6650 * This should enable thermal meter
6651 */
Jes Sorensen55c0b6a2016-04-14 14:58:50 -0400[diff] [blame]6652 if (priv->fops->tx_desc_size == sizeof(struct rtl8xxxu_txdesc40))
Jes Sorensen72143b92016-02-29 17:05:25 -0500[diff] [blame]6653 rtl8xxxu_write_rfreg(priv,
6654 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
6655 else
6656 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6657
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6658 /* Set NAV_UPPER to 30000us */
6659 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6660 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6661
Jes Sorensenba17d822016-03-31 17:08:39 -0400[diff] [blame]6662 if (priv->rtl_chip == RTL8723A) {
Jes Sorensen4042e612016-02-03 13:40:01 -0500[diff] [blame]6663 /*
6664 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6665 * but we need to find root cause.
6666 * This is 8723au only.
6667 */
6668 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6669 if ((val32 & 0xff000000) != 0x83000000) {
6670 val32 |= FPGA_RF_MODE_CCK;
6671 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6672 }
Jes Sorensen3021e512016-04-07 14:19:28 -0400[diff] [blame]6673 } else if (priv->rtl_chip == RTL8192E) {
6674 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6675 }
6676
6677 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6678 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6679 /* ack for xmit mgmt frames. */
6680 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6681
Jes Sorensene1394fe2016-04-07 14:19:29 -0400[diff] [blame]6682 if (priv->rtl_chip == RTL8192E) {
6683 /*
6684 * Fix LDPC rx hang issue.
6685 */
6686 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
6687 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
6688 val32 &= 0xfff00fff;
6689 val32 |= 0x0007e000;
Jes Sorensen46b37832016-04-14 14:59:06 -0400[diff] [blame]6690 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
Jes Sorensene1394fe2016-04-07 14:19:29 -0400[diff] [blame]6691 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6692exit:
6693 return ret;
6694}
6695
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6696static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6697 struct ieee80211_key_conf *key, const u8 *mac)
6698{
6699 u32 cmd, val32, addr, ctrl;
6700 int j, i, tmp_debug;
6701
6702 tmp_debug = rtl8xxxu_debug;
6703 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6704 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6705
6706 /*
6707 * This is a bit of a hack - the lower bits of the cipher
6708 * suite selector happens to match the cipher index in the CAM
6709 */
6710 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6711 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6712
6713 for (j = 5; j >= 0; j--) {
6714 switch (j) {
6715 case 0:
6716 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6717 break;
6718 case 1:
6719 val32 = mac[2] | (mac[3] << 8) |
6720 (mac[4] << 16) | (mac[5] << 24);
6721 break;
6722 default:
6723 i = (j - 2) << 2;
6724 val32 = key->key[i] | (key->key[i + 1] << 8) |
6725 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6726 break;
6727 }
6728
6729 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6730 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6731 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6732 udelay(100);
6733 }
6734
6735 rtl8xxxu_debug = tmp_debug;
6736}
6737
6738static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
Jes Sorensen56e43742016-02-03 13:39:50 -0500[diff] [blame]6739 struct ieee80211_vif *vif, const u8 *mac)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6740{
6741 struct rtl8xxxu_priv *priv = hw->priv;
6742 u8 val8;
6743
6744 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6745 val8 |= BEACON_DISABLE_TSF_UPDATE;
6746 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6747}
6748
6749static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6750 struct ieee80211_vif *vif)
6751{
6752 struct rtl8xxxu_priv *priv = hw->priv;
6753 u8 val8;
6754
6755 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6756 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6757 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6758}
6759
Jes Sorensenc6e39da2016-04-18 11:49:28 -0400[diff] [blame]6760static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6761 u32 ramask, int sgi)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6762{
6763 struct h2c_cmd h2c;
6764
Jes Sorensenf653e692016-02-29 17:05:38 -0500[diff] [blame]6765 memset(&h2c, 0, sizeof(struct h2c_cmd));
6766
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6767 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6768 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6769 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6770
6771 h2c.ramask.arg = 0x80;
6772 if (sgi)
6773 h2c.ramask.arg |= 0x20;
6774
Jes Sorensen7ff8c1a2016-02-29 17:04:32 -0500[diff] [blame]6775 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
Jes Sorensen8da91572016-02-29 17:04:29 -0500[diff] [blame]6776 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6777 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6778}
6779
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]6780void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
6781 u32 ramask, int sgi)
Jes Sorensenf653e692016-02-29 17:05:38 -0500[diff] [blame]6782{
6783 struct h2c_cmd h2c;
6784 u8 bw = 0;
6785
6786 memset(&h2c, 0, sizeof(struct h2c_cmd));
6787
6788 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
6789 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
6790 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
6791 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
6792 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
6793
6794 h2c.ramask.arg = 0x80;
6795 h2c.b_macid_cfg.data1 = 0;
6796 if (sgi)
6797 h2c.b_macid_cfg.data1 |= BIT(7);
6798
6799 h2c.b_macid_cfg.data2 = bw;
6800
6801 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6802 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
6803 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
6804}
6805
Jes Sorensenbeb55312016-04-18 11:49:23 -0400[diff] [blame]6806static void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
6807 u8 macid, bool connect)
Jes Sorensen7d794ea2016-02-29 17:05:39 -0500[diff] [blame]6808{
6809 struct h2c_cmd h2c;
6810
6811 memset(&h2c, 0, sizeof(struct h2c_cmd));
6812
6813 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6814
6815 if (connect)
6816 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6817 else
6818 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6819
6820 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6821}
6822
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]6823void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
6824 u8 macid, bool connect)
Jes Sorensen7d794ea2016-02-29 17:05:39 -0500[diff] [blame]6825{
6826 struct h2c_cmd h2c;
6827
6828 memset(&h2c, 0, sizeof(struct h2c_cmd));
6829
6830 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
6831 if (connect)
6832 h2c.media_status_rpt.parm |= BIT(0);
6833 else
6834 h2c.media_status_rpt.parm &= ~BIT(0);
6835
6836 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
6837}
6838
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6839static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6840{
6841 u32 val32;
6842 u8 rate_idx = 0;
6843
6844 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6845
6846 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6847 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6848 val32 |= rate_cfg;
6849 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6850
6851 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6852
6853 while (rate_cfg) {
6854 rate_cfg = (rate_cfg >> 1);
6855 rate_idx++;
6856 }
6857 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6858}
6859
6860static void
6861rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6862 struct ieee80211_bss_conf *bss_conf, u32 changed)
6863{
6864 struct rtl8xxxu_priv *priv = hw->priv;
6865 struct device *dev = &priv->udev->dev;
6866 struct ieee80211_sta *sta;
6867 u32 val32;
6868 u8 val8;
6869
6870 if (changed & BSS_CHANGED_ASSOC) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6871 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6872
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6873 rtl8xxxu_set_linktype(priv, vif->type);
6874
6875 if (bss_conf->assoc) {
6876 u32 ramask;
6877 int sgi = 0;
6878
6879 rcu_read_lock();
6880 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6881 if (!sta) {
6882 dev_info(dev, "%s: ASSOC no sta found\n",
6883 __func__);
6884 rcu_read_unlock();
6885 goto error;
6886 }
6887
6888 if (sta->ht_cap.ht_supported)
6889 dev_info(dev, "%s: HT supported\n", __func__);
6890 if (sta->vht_cap.vht_supported)
6891 dev_info(dev, "%s: VHT supported\n", __func__);
6892
6893 /* TODO: Set bits 28-31 for rate adaptive id */
6894 ramask = (sta->supp_rates[0] & 0xfff) |
6895 sta->ht_cap.mcs.rx_mask[0] << 12 |
6896 sta->ht_cap.mcs.rx_mask[1] << 20;
6897 if (sta->ht_cap.cap &
6898 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6899 sgi = 1;
6900 rcu_read_unlock();
6901
Jes Sorensenf653e692016-02-29 17:05:38 -0500[diff] [blame]6902 priv->fops->update_rate_mask(priv, ramask, sgi);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6903
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6904 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6905
6906 rtl8723a_stop_tx_beacon(priv);
6907
6908 /* joinbss sequence */
6909 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6910 0xc000 | bss_conf->aid);
6911
Jes Sorensen7d794ea2016-02-29 17:05:39 -0500[diff] [blame]6912 priv->fops->report_connect(priv, 0, true);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6913 } else {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6914 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6915 val8 |= BEACON_DISABLE_TSF_UPDATE;
6916 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6917
Jes Sorensen7d794ea2016-02-29 17:05:39 -0500[diff] [blame]6918 priv->fops->report_connect(priv, 0, false);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6919 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6920 }
6921
6922 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6923 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6924 bss_conf->use_short_preamble);
6925 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6926 if (bss_conf->use_short_preamble)
6927 val32 |= RSR_ACK_SHORT_PREAMBLE;
6928 else
6929 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6930 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6931 }
6932
6933 if (changed & BSS_CHANGED_ERP_SLOT) {
6934 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6935 bss_conf->use_short_slot);
6936
6937 if (bss_conf->use_short_slot)
6938 val8 = 9;
6939 else
6940 val8 = 20;
6941 rtl8xxxu_write8(priv, REG_SLOT, val8);
6942 }
6943
6944 if (changed & BSS_CHANGED_BSSID) {
6945 dev_dbg(dev, "Changed BSSID!\n");
6946 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6947 }
6948
6949 if (changed & BSS_CHANGED_BASIC_RATES) {
6950 dev_dbg(dev, "Changed BASIC_RATES!\n");
6951 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6952 }
6953error:
6954 return;
6955}
6956
6957static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6958{
6959 u32 rtlqueue;
6960
6961 switch (queue) {
6962 case IEEE80211_AC_VO:
6963 rtlqueue = TXDESC_QUEUE_VO;
6964 break;
6965 case IEEE80211_AC_VI:
6966 rtlqueue = TXDESC_QUEUE_VI;
6967 break;
6968 case IEEE80211_AC_BE:
6969 rtlqueue = TXDESC_QUEUE_BE;
6970 break;
6971 case IEEE80211_AC_BK:
6972 rtlqueue = TXDESC_QUEUE_BK;
6973 break;
6974 default:
6975 rtlqueue = TXDESC_QUEUE_BE;
6976 }
6977
6978 return rtlqueue;
6979}
6980
6981static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6982{
6983 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6984 u32 queue;
6985
6986 if (ieee80211_is_mgmt(hdr->frame_control))
6987 queue = TXDESC_QUEUE_MGNT;
6988 else
6989 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6990
6991 return queue;
6992}
6993
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]6994/*
6995 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
6996 * format. The descriptor checksum is still only calculated over the
6997 * initial 32 bytes of the descriptor!
6998 */
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]6999static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7000{
7001 __le16 *ptr = (__le16 *)tx_desc;
7002 u16 csum = 0;
7003 int i;
7004
7005 /*
7006 * Clear csum field before calculation, as the csum field is
7007 * in the middle of the struct.
7008 */
7009 tx_desc->csum = cpu_to_le16(0);
7010
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]7011 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7012 csum = csum ^ le16_to_cpu(ptr[i]);
7013
7014 tx_desc->csum |= cpu_to_le16(csum);
7015}
7016
7017static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
7018{
7019 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
7020 unsigned long flags;
7021
7022 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7023 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
7024 list_del(&tx_urb->list);
7025 priv->tx_urb_free_count--;
7026 usb_free_urb(&tx_urb->urb);
7027 }
7028 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7029}
7030
7031static struct rtl8xxxu_tx_urb *
7032rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
7033{
7034 struct rtl8xxxu_tx_urb *tx_urb;
7035 unsigned long flags;
7036
7037 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7038 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
7039 struct rtl8xxxu_tx_urb, list);
7040 if (tx_urb) {
7041 list_del(&tx_urb->list);
7042 priv->tx_urb_free_count--;
7043 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
7044 !priv->tx_stopped) {
7045 priv->tx_stopped = true;
7046 ieee80211_stop_queues(priv->hw);
7047 }
7048 }
7049
7050 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7051
7052 return tx_urb;
7053}
7054
7055static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
7056 struct rtl8xxxu_tx_urb *tx_urb)
7057{
7058 unsigned long flags;
7059
7060 INIT_LIST_HEAD(&tx_urb->list);
7061
7062 spin_lock_irqsave(&priv->tx_urb_lock, flags);
7063
7064 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7065 priv->tx_urb_free_count++;
7066 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
7067 priv->tx_stopped) {
7068 priv->tx_stopped = false;
7069 ieee80211_wake_queues(priv->hw);
7070 }
7071
7072 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
7073}
7074
7075static void rtl8xxxu_tx_complete(struct urb *urb)
7076{
7077 struct sk_buff *skb = (struct sk_buff *)urb->context;
7078 struct ieee80211_tx_info *tx_info;
7079 struct ieee80211_hw *hw;
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7080 struct rtl8xxxu_priv *priv;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7081 struct rtl8xxxu_tx_urb *tx_urb =
7082 container_of(urb, struct rtl8xxxu_tx_urb, urb);
7083
7084 tx_info = IEEE80211_SKB_CB(skb);
7085 hw = tx_info->rate_driver_data[0];
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7086 priv = hw->priv;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7087
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7088 skb_pull(skb, priv->fops->tx_desc_size);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7089
7090 ieee80211_tx_info_clear_status(tx_info);
7091 tx_info->status.rates[0].idx = -1;
7092 tx_info->status.rates[0].count = 0;
7093
7094 if (!urb->status)
7095 tx_info->flags |= IEEE80211_TX_STAT_ACK;
7096
7097 ieee80211_tx_status_irqsafe(hw, skb);
7098
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7099 rtl8xxxu_free_tx_urb(priv, tx_urb);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7100}
7101
7102static void rtl8xxxu_dump_action(struct device *dev,
7103 struct ieee80211_hdr *hdr)
7104{
7105 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
7106 u16 cap, timeout;
7107
7108 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
7109 return;
7110
7111 switch (mgmt->u.action.u.addba_resp.action_code) {
7112 case WLAN_ACTION_ADDBA_RESP:
7113 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
7114 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
7115 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
7116 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
7117 "status %02x\n",
7118 timeout,
7119 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7120 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7121 (cap >> 1) & 0x1,
7122 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
7123 break;
7124 case WLAN_ACTION_ADDBA_REQ:
7125 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
7126 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
7127 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
7128 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
7129 timeout,
7130 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
7131 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
7132 (cap >> 1) & 0x1);
7133 break;
7134 default:
7135 dev_info(dev, "action frame %02x\n",
7136 mgmt->u.action.u.addba_resp.action_code);
7137 break;
7138 }
7139}
7140
7141static void rtl8xxxu_tx(struct ieee80211_hw *hw,
7142 struct ieee80211_tx_control *control,
7143 struct sk_buff *skb)
7144{
7145 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
7146 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
7147 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
7148 struct rtl8xxxu_priv *priv = hw->priv;
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]7149 struct rtl8xxxu_txdesc32 *tx_desc;
7150 struct rtl8xxxu_txdesc40 *tx_desc40;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7151 struct rtl8xxxu_tx_urb *tx_urb;
7152 struct ieee80211_sta *sta = NULL;
7153 struct ieee80211_vif *vif = tx_info->control.vif;
7154 struct device *dev = &priv->udev->dev;
7155 u32 queue, rate;
7156 u16 pktlen = skb->len;
7157 u16 seq_number;
7158 u16 rate_flag = tx_info->control.rates[0].flags;
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7159 int tx_desc_size = priv->fops->tx_desc_size;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7160 int ret;
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7161 bool usedesc40, ampdu_enable;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7162
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7163 if (skb_headroom(skb) < tx_desc_size) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7164 dev_warn(dev,
7165 "%s: Not enough headroom (%i) for tx descriptor\n",
7166 __func__, skb_headroom(skb));
7167 goto error;
7168 }
7169
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7170 if (unlikely(skb->len > (65535 - tx_desc_size))) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7171 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
7172 __func__, skb->len);
7173 goto error;
7174 }
7175
7176 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
7177 if (!tx_urb) {
7178 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
7179 goto error;
7180 }
7181
7182 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
7183 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
7184 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
7185
7186 if (ieee80211_is_action(hdr->frame_control))
7187 rtl8xxxu_dump_action(dev, hdr);
7188
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7189 usedesc40 = (tx_desc_size == 40);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7190 tx_info->rate_driver_data[0] = hw;
7191
7192 if (control && control->sta)
7193 sta = control->sta;
7194
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]7195 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7196
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7197 memset(tx_desc, 0, tx_desc_size);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7198 tx_desc->pkt_size = cpu_to_le16(pktlen);
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]7199 tx_desc->pkt_offset = tx_desc_size;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7200
7201 tx_desc->txdw0 =
7202 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
7203 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
7204 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
7205 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
7206
7207 queue = rtl8xxxu_queue_select(hw, skb);
7208 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
7209
7210 if (tx_info->control.hw_key) {
7211 switch (tx_info->control.hw_key->cipher) {
7212 case WLAN_CIPHER_SUITE_WEP40:
7213 case WLAN_CIPHER_SUITE_WEP104:
7214 case WLAN_CIPHER_SUITE_TKIP:
7215 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
7216 break;
7217 case WLAN_CIPHER_SUITE_CCMP:
7218 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
7219 break;
7220 default:
7221 break;
7222 }
7223 }
7224
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7225 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7226 ampdu_enable = false;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7227 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7228 if (sta->ht_cap.ht_supported) {
7229 u32 ampdu, val32;
7230
7231 ampdu = (u32)sta->ht_cap.ampdu_density;
7232 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7233 tx_desc->txdw2 |= cpu_to_le32(val32);
Jes Sorensence2d1db2016-02-29 17:05:30 -0500[diff] [blame]7234
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7235 ampdu_enable = true;
7236 }
7237 }
7238
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7239 if (rate_flag & IEEE80211_TX_RC_MCS)
7240 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7241 else
7242 rate = tx_rate->hw_value;
7243
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7244 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
7245 if (!usedesc40) {
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7246 tx_desc->txdw5 = cpu_to_le32(rate);
7247
7248 if (ieee80211_is_data(hdr->frame_control))
7249 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7250
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7251 tx_desc->txdw3 =
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7252 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7253
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7254 if (ampdu_enable)
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7255 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7256 else
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7257 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7258
7259 if (ieee80211_is_mgmt(hdr->frame_control)) {
7260 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7261 tx_desc->txdw4 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7262 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7263 tx_desc->txdw5 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7264 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7265 tx_desc->txdw5 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7266 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7267 }
7268
7269 if (ieee80211_is_data_qos(hdr->frame_control))
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7270 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7271
7272 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7273 (sta && vif && vif->bss_conf.use_short_preamble))
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7274 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7275
7276 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7277 (ieee80211_is_data_qos(hdr->frame_control) &&
7278 sta && sta->ht_cap.cap &
7279 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
Jes Sorensen1df1de32016-03-31 17:08:36 -0400[diff] [blame]7280 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7281 }
7282
7283 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7284 /*
7285 * Use RTS rate 24M - does the mac80211 tell
7286 * us which to use?
7287 */
7288 tx_desc->txdw4 |=
7289 cpu_to_le32(DESC_RATE_24M <<
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7290 TXDESC32_RTS_RATE_SHIFT);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7291 tx_desc->txdw4 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7292 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
7293 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7294 }
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7295 } else {
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]7296 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7297
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7298 tx_desc40->txdw4 = cpu_to_le32(rate);
7299 if (ieee80211_is_data(hdr->frame_control)) {
7300 tx_desc->txdw4 |=
7301 cpu_to_le32(0x1f <<
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7302 TXDESC40_DATA_RATE_FB_SHIFT);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7303 }
7304
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7305 tx_desc40->txdw9 =
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7306 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
Jes Sorensencc2646d2016-02-29 17:05:32 -0500[diff] [blame]7307
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7308 if (ampdu_enable)
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7309 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
Jes Sorensena40ace42016-02-29 17:05:31 -0500[diff] [blame]7310 else
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7311 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7312
7313 if (ieee80211_is_mgmt(hdr->frame_control)) {
7314 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
7315 tx_desc40->txdw3 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7316 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7317 tx_desc40->txdw4 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7318 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7319 tx_desc40->txdw4 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7320 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7321 }
7322
7323 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7324 (sta && vif && vif->bss_conf.use_short_preamble))
7325 tx_desc40->txdw5 |=
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7326 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7327
7328 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7329 /*
7330 * Use RTS rate 24M - does the mac80211 tell
7331 * us which to use?
7332 */
7333 tx_desc->txdw4 |=
7334 cpu_to_le32(DESC_RATE_24M <<
Jes Sorensen33f37242016-03-31 17:08:34 -0400[diff] [blame]7335 TXDESC40_RTS_RATE_SHIFT);
7336 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
7337 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
Jes Sorensen4c683602016-02-29 17:05:35 -0500[diff] [blame]7338 }
Jes Sorensen69794942016-02-29 17:05:43 -0500[diff] [blame]7339 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7340
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7341 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7342
7343 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7344 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7345
7346 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7347 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7348 if (ret) {
7349 usb_unanchor_urb(&tx_urb->urb);
7350 rtl8xxxu_free_tx_urb(priv, tx_urb);
7351 goto error;
7352 }
7353 return;
7354error:
7355 dev_kfree_skb(skb);
7356}
7357
7358static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7359 struct ieee80211_rx_status *rx_status,
Jes Sorensen87957082016-02-29 17:05:42 -0500[diff] [blame]7360 struct rtl8723au_phy_stats *phy_stats,
7361 u32 rxmcs)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7362{
7363 if (phy_stats->sgi_en)
7364 rx_status->flag |= RX_FLAG_SHORT_GI;
7365
Jes Sorensen87957082016-02-29 17:05:42 -0500[diff] [blame]7366 if (rxmcs < DESC_RATE_6M) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7367 /*
7368 * Handle PHY stats for CCK rates
7369 */
7370 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7371
7372 switch (cck_agc_rpt & 0xc0) {
7373 case 0xc0:
7374 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7375 break;
7376 case 0x80:
7377 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7378 break;
7379 case 0x40:
7380 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7381 break;
7382 case 0x00:
7383 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7384 break;
7385 }
7386 } else {
7387 rx_status->signal =
7388 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7389 }
7390}
7391
7392static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7393{
7394 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7395 unsigned long flags;
7396
7397 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7398
7399 list_for_each_entry_safe(rx_urb, tmp,
7400 &priv->rx_urb_pending_list, list) {
7401 list_del(&rx_urb->list);
7402 priv->rx_urb_pending_count--;
7403 usb_free_urb(&rx_urb->urb);
7404 }
7405
7406 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7407}
7408
7409static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7410 struct rtl8xxxu_rx_urb *rx_urb)
7411{
7412 struct sk_buff *skb;
7413 unsigned long flags;
7414 int pending = 0;
7415
7416 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7417
7418 if (!priv->shutdown) {
7419 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7420 priv->rx_urb_pending_count++;
7421 pending = priv->rx_urb_pending_count;
7422 } else {
7423 skb = (struct sk_buff *)rx_urb->urb.context;
7424 dev_kfree_skb(skb);
7425 usb_free_urb(&rx_urb->urb);
7426 }
7427
7428 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7429
7430 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7431 schedule_work(&priv->rx_urb_wq);
7432}
7433
7434static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7435{
7436 struct rtl8xxxu_priv *priv;
7437 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7438 struct list_head local;
7439 struct sk_buff *skb;
7440 unsigned long flags;
7441 int ret;
7442
7443 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7444 INIT_LIST_HEAD(&local);
7445
7446 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7447
7448 list_splice_init(&priv->rx_urb_pending_list, &local);
7449 priv->rx_urb_pending_count = 0;
7450
7451 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7452
7453 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7454 list_del_init(&rx_urb->list);
7455 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7456 /*
7457 * If out of memory or temporary error, put it back on the
7458 * queue and try again. Otherwise the device is dead/gone
7459 * and we should drop it.
7460 */
7461 switch (ret) {
7462 case 0:
7463 break;
7464 case -ENOMEM:
7465 case -EAGAIN:
7466 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7467 break;
7468 default:
7469 pr_info("failed to requeue urb %i\n", ret);
7470 skb = (struct sk_buff *)rx_urb->urb.context;
7471 dev_kfree_skb(skb);
7472 usb_free_urb(&rx_urb->urb);
7473 }
7474 }
7475}
7476
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7477static int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv,
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7478 struct sk_buff *skb,
7479 struct ieee80211_rx_status *rx_status)
7480{
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7481 struct rtl8xxxu_rxdesc16 *rx_desc =
7482 (struct rtl8xxxu_rxdesc16 *)skb->data;
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7483 struct rtl8723au_phy_stats *phy_stats;
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7484 __le32 *_rx_desc_le = (__le32 *)skb->data;
7485 u32 *_rx_desc = (u32 *)skb->data;
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7486 int drvinfo_sz, desc_shift;
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7487 int i;
7488
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7489 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7490 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7491
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7492 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7493
7494 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7495
7496 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7497 desc_shift = rx_desc->shift;
7498 skb_pull(skb, drvinfo_sz + desc_shift);
7499
7500 if (rx_desc->phy_stats)
Jes Sorensen87957082016-02-29 17:05:42 -0500[diff] [blame]7501 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7502 rx_desc->rxmcs);
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7503
7504 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7505 rx_status->flag |= RX_FLAG_MACTIME_START;
7506
7507 if (!rx_desc->swdec)
7508 rx_status->flag |= RX_FLAG_DECRYPTED;
7509 if (rx_desc->crc32)
7510 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7511 if (rx_desc->bw)
7512 rx_status->flag |= RX_FLAG_40MHZ;
7513
7514 if (rx_desc->rxht) {
7515 rx_status->flag |= RX_FLAG_HT;
7516 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7517 } else {
7518 rx_status->rate_idx = rx_desc->rxmcs;
7519 }
7520
7521 return RX_TYPE_DATA_PKT;
7522}
7523
Jes Sorensen599119f2016-04-28 15:19:06 -0400[diff] [blame^]7524int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb,
7525 struct ieee80211_rx_status *rx_status)
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7526{
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7527 struct rtl8xxxu_rxdesc24 *rx_desc =
7528 (struct rtl8xxxu_rxdesc24 *)skb->data;
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7529 struct rtl8723au_phy_stats *phy_stats;
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7530 __le32 *_rx_desc_le = (__le32 *)skb->data;
7531 u32 *_rx_desc = (u32 *)skb->data;
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7532 int drvinfo_sz, desc_shift;
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7533 int i;
7534
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7535 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7536 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7537
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7538 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7539
7540 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7541
7542 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7543 desc_shift = rx_desc->shift;
7544 skb_pull(skb, drvinfo_sz + desc_shift);
7545
Jes Sorensene975b872016-02-29 17:05:36 -0500[diff] [blame]7546 if (rx_desc->rpt_sel) {
7547 struct device *dev = &priv->udev->dev;
7548 dev_dbg(dev, "%s: C2H packet\n", __func__);
7549 return RX_TYPE_C2H;
7550 }
7551
Jes Sorensen87957082016-02-29 17:05:42 -0500[diff] [blame]7552 if (rx_desc->phy_stats)
7553 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
7554 rx_desc->rxmcs);
7555
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7556 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7557 rx_status->flag |= RX_FLAG_MACTIME_START;
7558
7559 if (!rx_desc->swdec)
7560 rx_status->flag |= RX_FLAG_DECRYPTED;
7561 if (rx_desc->crc32)
7562 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7563 if (rx_desc->bw)
7564 rx_status->flag |= RX_FLAG_40MHZ;
7565
7566 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7567 rx_status->flag |= RX_FLAG_HT;
7568 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7569 } else {
7570 rx_status->rate_idx = rx_desc->rxmcs;
7571 }
7572
Jes Sorensene975b872016-02-29 17:05:36 -0500[diff] [blame]7573 return RX_TYPE_DATA_PKT;
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7574}
7575
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7576static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7577 struct sk_buff *skb)
7578{
7579 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7580 struct device *dev = &priv->udev->dev;
7581 int len;
7582
7583 len = skb->len - 2;
7584
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7585 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7586 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7587
7588 switch(c2h->id) {
7589 case C2H_8723B_BT_INFO:
7590 if (c2h->bt_info.response_source >
7591 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7592 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7593 else
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7594 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7595
7596 if (c2h->bt_info.bt_has_reset)
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7597 dev_dbg(dev, "BT has been reset\n");
Jes Sorensen394f1bd2016-02-29 17:04:49 -0500[diff] [blame]7598 if (c2h->bt_info.tx_rx_mask)
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7599 dev_dbg(dev, "BT TRx mask\n");
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7600
7601 break;
Jes Sorensen394f1bd2016-02-29 17:04:49 -0500[diff] [blame]7602 case C2H_8723B_BT_MP_INFO:
Jes Sorensen5e00d502016-02-29 17:05:28 -0500[diff] [blame]7603 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7604 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
Jes Sorensen394f1bd2016-02-29 17:04:49 -0500[diff] [blame]7605 break;
Jes Sorensen55a18dd2016-02-29 17:05:41 -0500[diff] [blame]7606 case C2H_8723B_RA_REPORT:
7607 dev_dbg(dev,
7608 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
7609 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
7610 c2h->ra_report.macid, c2h->ra_report.noisy_state);
7611 break;
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7612 default:
Jes Sorensen739dc9f2016-02-29 17:05:40 -0500[diff] [blame]7613 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
7614 c2h->id, c2h->seq);
7615 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
7616 16, 1, c2h->raw.payload, len, false);
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7617 break;
7618 }
7619}
7620
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7621static void rtl8xxxu_rx_complete(struct urb *urb)
7622{
7623 struct rtl8xxxu_rx_urb *rx_urb =
7624 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7625 struct ieee80211_hw *hw = rx_urb->hw;
7626 struct rtl8xxxu_priv *priv = hw->priv;
7627 struct sk_buff *skb = (struct sk_buff *)urb->context;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7628 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7629 struct device *dev = &priv->udev->dev;
Jes Sorensen2cb79eb2016-04-14 14:58:51 -0400[diff] [blame]7630 int rx_type;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7631
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7632 skb_put(skb, urb->actual_length);
7633
7634 if (urb->status == 0) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7635 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7636
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7637 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7638
7639 rx_status->freq = hw->conf.chandef.chan->center_freq;
7640 rx_status->band = hw->conf.chandef.chan->band;
7641
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7642 if (rx_type == RX_TYPE_DATA_PKT)
7643 ieee80211_rx_irqsafe(hw, skb);
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7644 else {
7645 rtl8723bu_handle_c2h(priv, skb);
Jes Sorensenb18cdfd2016-02-29 17:04:47 -0500[diff] [blame]7646 dev_kfree_skb(skb);
Jes Sorensenb2b43b72016-02-29 17:04:48 -0500[diff] [blame]7647 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7648
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7649 skb = NULL;
7650 rx_urb->urb.context = NULL;
7651 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7652 } else {
7653 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7654 goto cleanup;
7655 }
7656 return;
7657
7658cleanup:
7659 usb_free_urb(urb);
7660 dev_kfree_skb(skb);
7661 return;
7662}
7663
7664static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7665 struct rtl8xxxu_rx_urb *rx_urb)
7666{
7667 struct sk_buff *skb;
7668 int skb_size;
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7669 int ret, rx_desc_sz;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7670
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7671 rx_desc_sz = priv->fops->rx_desc_size;
7672 skb_size = rx_desc_sz + RTL_RX_BUFFER_SIZE;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7673 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7674 if (!skb)
7675 return -ENOMEM;
7676
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]7677 memset(skb->data, 0, rx_desc_sz);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7678 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7679 skb_size, rtl8xxxu_rx_complete, skb);
7680 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7681 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7682 if (ret)
7683 usb_unanchor_urb(&rx_urb->urb);
7684 return ret;
7685}
7686
7687static void rtl8xxxu_int_complete(struct urb *urb)
7688{
7689 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7690 struct device *dev = &priv->udev->dev;
7691 int ret;
7692
7693 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7694 if (urb->status == 0) {
7695 usb_anchor_urb(urb, &priv->int_anchor);
7696 ret = usb_submit_urb(urb, GFP_ATOMIC);
7697 if (ret)
7698 usb_unanchor_urb(urb);
7699 } else {
7700 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7701 }
7702}
7703
7704
7705static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7706{
7707 struct rtl8xxxu_priv *priv = hw->priv;
7708 struct urb *urb;
7709 u32 val32;
7710 int ret;
7711
7712 urb = usb_alloc_urb(0, GFP_KERNEL);
7713 if (!urb)
7714 return -ENOMEM;
7715
7716 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7717 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7718 rtl8xxxu_int_complete, priv, 1);
7719 usb_anchor_urb(urb, &priv->int_anchor);
7720 ret = usb_submit_urb(urb, GFP_KERNEL);
7721 if (ret) {
7722 usb_unanchor_urb(urb);
7723 goto error;
7724 }
7725
7726 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7727 val32 |= USB_HIMR_CPWM;
7728 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7729
7730error:
7731 return ret;
7732}
7733
7734static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7735 struct ieee80211_vif *vif)
7736{
7737 struct rtl8xxxu_priv *priv = hw->priv;
7738 int ret;
7739 u8 val8;
7740
7741 switch (vif->type) {
7742 case NL80211_IFTYPE_STATION:
7743 rtl8723a_stop_tx_beacon(priv);
7744
7745 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7746 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7747 BEACON_DISABLE_TSF_UPDATE;
7748 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7749 ret = 0;
7750 break;
7751 default:
7752 ret = -EOPNOTSUPP;
7753 }
7754
7755 rtl8xxxu_set_linktype(priv, vif->type);
7756
7757 return ret;
7758}
7759
7760static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7761 struct ieee80211_vif *vif)
7762{
7763 struct rtl8xxxu_priv *priv = hw->priv;
7764
7765 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7766}
7767
7768static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7769{
7770 struct rtl8xxxu_priv *priv = hw->priv;
7771 struct device *dev = &priv->udev->dev;
7772 u16 val16;
7773 int ret = 0, channel;
7774 bool ht40;
7775
7776 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7777 dev_info(dev,
7778 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7779 __func__, hw->conf.chandef.chan->hw_value,
7780 changed, hw->conf.chandef.width);
7781
7782 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7783 val16 = ((hw->conf.long_frame_max_tx_count <<
7784 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7785 ((hw->conf.short_frame_max_tx_count <<
7786 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7787 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7788 }
7789
7790 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7791 switch (hw->conf.chandef.width) {
7792 case NL80211_CHAN_WIDTH_20_NOHT:
7793 case NL80211_CHAN_WIDTH_20:
7794 ht40 = false;
7795 break;
7796 case NL80211_CHAN_WIDTH_40:
7797 ht40 = true;
7798 break;
7799 default:
7800 ret = -ENOTSUPP;
7801 goto exit;
7802 }
7803
7804 channel = hw->conf.chandef.chan->hw_value;
7805
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]7806 priv->fops->set_tx_power(priv, channel, ht40);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7807
Jes Sorensen1ea8e842016-02-29 17:05:04 -0500[diff] [blame]7808 priv->fops->config_channel(hw);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7809 }
7810
7811exit:
7812 return ret;
7813}
7814
7815static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7816 struct ieee80211_vif *vif, u16 queue,
7817 const struct ieee80211_tx_queue_params *param)
7818{
7819 struct rtl8xxxu_priv *priv = hw->priv;
7820 struct device *dev = &priv->udev->dev;
7821 u32 val32;
7822 u8 aifs, acm_ctrl, acm_bit;
7823
7824 aifs = param->aifs;
7825
7826 val32 = aifs |
7827 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7828 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7829 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7830
7831 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7832 dev_dbg(dev,
7833 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7834 __func__, queue, val32, param->acm, acm_ctrl);
7835
7836 switch (queue) {
7837 case IEEE80211_AC_VO:
7838 acm_bit = ACM_HW_CTRL_VO;
7839 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7840 break;
7841 case IEEE80211_AC_VI:
7842 acm_bit = ACM_HW_CTRL_VI;
7843 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7844 break;
7845 case IEEE80211_AC_BE:
7846 acm_bit = ACM_HW_CTRL_BE;
7847 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7848 break;
7849 case IEEE80211_AC_BK:
7850 acm_bit = ACM_HW_CTRL_BK;
7851 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7852 break;
7853 default:
7854 acm_bit = 0;
7855 break;
7856 }
7857
7858 if (param->acm)
7859 acm_ctrl |= acm_bit;
7860 else
7861 acm_ctrl &= ~acm_bit;
7862 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7863
7864 return 0;
7865}
7866
7867static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7868 unsigned int changed_flags,
7869 unsigned int *total_flags, u64 multicast)
7870{
7871 struct rtl8xxxu_priv *priv = hw->priv;
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]7872 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7873
7874 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7875 __func__, changed_flags, *total_flags);
7876
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]7877 /*
7878 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7879 */
7880
7881 if (*total_flags & FIF_FCSFAIL)
7882 rcr |= RCR_ACCEPT_CRC32;
7883 else
7884 rcr &= ~RCR_ACCEPT_CRC32;
7885
7886 /*
7887 * FIF_PLCPFAIL not supported?
7888 */
7889
7890 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7891 rcr &= ~RCR_CHECK_BSSID_BEACON;
7892 else
7893 rcr |= RCR_CHECK_BSSID_BEACON;
7894
7895 if (*total_flags & FIF_CONTROL)
7896 rcr |= RCR_ACCEPT_CTRL_FRAME;
7897 else
7898 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7899
7900 if (*total_flags & FIF_OTHER_BSS) {
7901 rcr |= RCR_ACCEPT_AP;
7902 rcr &= ~RCR_CHECK_BSSID_MATCH;
7903 } else {
7904 rcr &= ~RCR_ACCEPT_AP;
7905 rcr |= RCR_CHECK_BSSID_MATCH;
7906 }
7907
7908 if (*total_flags & FIF_PSPOLL)
7909 rcr |= RCR_ACCEPT_PM;
7910 else
7911 rcr &= ~RCR_ACCEPT_PM;
7912
7913 /*
7914 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7915 */
7916
7917 rtl8xxxu_write32(priv, REG_RCR, rcr);
7918
Jes Sorensen755bda12016-02-03 13:39:54 -0500[diff] [blame]7919 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7920 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7921 FIF_PROBE_REQ);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]7922}
7923
7924static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7925{
7926 if (rts > 2347)
7927 return -EINVAL;
7928
7929 return 0;
7930}
7931
7932static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7933 struct ieee80211_vif *vif,
7934 struct ieee80211_sta *sta,
7935 struct ieee80211_key_conf *key)
7936{
7937 struct rtl8xxxu_priv *priv = hw->priv;
7938 struct device *dev = &priv->udev->dev;
7939 u8 mac_addr[ETH_ALEN];
7940 u8 val8;
7941 u16 val16;
7942 u32 val32;
7943 int retval = -EOPNOTSUPP;
7944
7945 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7946 __func__, cmd, key->cipher, key->keyidx);
7947
7948 if (vif->type != NL80211_IFTYPE_STATION)
7949 return -EOPNOTSUPP;
7950
7951 if (key->keyidx > 3)
7952 return -EOPNOTSUPP;
7953
7954 switch (key->cipher) {
7955 case WLAN_CIPHER_SUITE_WEP40:
7956 case WLAN_CIPHER_SUITE_WEP104:
7957
7958 break;
7959 case WLAN_CIPHER_SUITE_CCMP:
7960 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7961 break;
7962 case WLAN_CIPHER_SUITE_TKIP:
7963 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7964 default:
7965 return -EOPNOTSUPP;
7966 }
7967
7968 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7969 dev_dbg(dev, "%s: pairwise key\n", __func__);
7970 ether_addr_copy(mac_addr, sta->addr);
7971 } else {
7972 dev_dbg(dev, "%s: group key\n", __func__);
7973 eth_broadcast_addr(mac_addr);
7974 }
7975
7976 val16 = rtl8xxxu_read16(priv, REG_CR);
7977 val16 |= CR_SECURITY_ENABLE;
7978 rtl8xxxu_write16(priv, REG_CR, val16);
7979
7980 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7981 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7982 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7983 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7984
7985 switch (cmd) {
7986 case SET_KEY:
7987 key->hw_key_idx = key->keyidx;
7988 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7989 rtl8xxxu_cam_write(priv, key, mac_addr);
7990 retval = 0;
7991 break;
7992 case DISABLE_KEY:
7993 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7994 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7995 key->keyidx << CAM_CMD_KEY_SHIFT;
7996 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7997 retval = 0;
7998 break;
7999 default:
8000 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
8001 }
8002
8003 return retval;
8004}
8005
8006static int
8007rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]8008 struct ieee80211_ampdu_params *params)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8009{
8010 struct rtl8xxxu_priv *priv = hw->priv;
8011 struct device *dev = &priv->udev->dev;
8012 u8 ampdu_factor, ampdu_density;
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]8013 struct ieee80211_sta *sta = params->sta;
8014 enum ieee80211_ampdu_mlme_action action = params->action;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8015
8016 switch (action) {
8017 case IEEE80211_AMPDU_TX_START:
8018 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
8019 ampdu_factor = sta->ht_cap.ampdu_factor;
8020 ampdu_density = sta->ht_cap.ampdu_density;
8021 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
8022 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
8023 dev_dbg(dev,
8024 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
8025 ampdu_factor, ampdu_density);
8026 break;
8027 case IEEE80211_AMPDU_TX_STOP_FLUSH:
8028 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
8029 rtl8xxxu_set_ampdu_factor(priv, 0);
8030 rtl8xxxu_set_ampdu_min_space(priv, 0);
8031 break;
8032 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8033 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
8034 __func__);
8035 rtl8xxxu_set_ampdu_factor(priv, 0);
8036 rtl8xxxu_set_ampdu_min_space(priv, 0);
8037 break;
8038 case IEEE80211_AMPDU_RX_START:
8039 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
8040 break;
8041 case IEEE80211_AMPDU_RX_STOP:
8042 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
8043 break;
8044 default:
8045 break;
8046 }
8047 return 0;
8048}
8049
8050static int rtl8xxxu_start(struct ieee80211_hw *hw)
8051{
8052 struct rtl8xxxu_priv *priv = hw->priv;
8053 struct rtl8xxxu_rx_urb *rx_urb;
8054 struct rtl8xxxu_tx_urb *tx_urb;
8055 unsigned long flags;
8056 int ret, i;
8057
8058 ret = 0;
8059
8060 init_usb_anchor(&priv->rx_anchor);
8061 init_usb_anchor(&priv->tx_anchor);
8062 init_usb_anchor(&priv->int_anchor);
8063
Jes Sorensendb08de92016-02-29 17:05:17 -0500[diff] [blame]8064 priv->fops->enable_rf(priv);
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]8065 if (priv->usb_interrupts) {
8066 ret = rtl8xxxu_submit_int_urb(hw);
8067 if (ret)
8068 goto exit;
8069 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8070
8071 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
8072 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
8073 if (!tx_urb) {
8074 if (!i)
8075 ret = -ENOMEM;
8076
8077 goto error_out;
8078 }
8079 usb_init_urb(&tx_urb->urb);
8080 INIT_LIST_HEAD(&tx_urb->list);
8081 tx_urb->hw = hw;
8082 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8083 priv->tx_urb_free_count++;
8084 }
8085
8086 priv->tx_stopped = false;
8087
8088 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8089 priv->shutdown = false;
8090 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8091
8092 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
8093 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
8094 if (!rx_urb) {
8095 if (!i)
8096 ret = -ENOMEM;
8097
8098 goto error_out;
8099 }
8100 usb_init_urb(&rx_urb->urb);
8101 INIT_LIST_HEAD(&rx_urb->list);
8102 rx_urb->hw = hw;
8103
8104 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8105 }
8106exit:
8107 /*
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]8108 * Accept all data and mgmt frames
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8109 */
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]8110 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8111 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
8112
8113 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
8114
8115 return ret;
8116
8117error_out:
8118 rtl8xxxu_free_tx_resources(priv);
8119 /*
8120 * Disable all data and mgmt frames
8121 */
8122 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8123 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8124
8125 return ret;
8126}
8127
8128static void rtl8xxxu_stop(struct ieee80211_hw *hw)
8129{
8130 struct rtl8xxxu_priv *priv = hw->priv;
8131 unsigned long flags;
8132
8133 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
8134
8135 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
8136 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
8137
8138 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8139 priv->shutdown = true;
8140 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8141
8142 usb_kill_anchored_urbs(&priv->rx_anchor);
8143 usb_kill_anchored_urbs(&priv->tx_anchor);
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]8144 if (priv->usb_interrupts)
8145 usb_kill_anchored_urbs(&priv->int_anchor);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8146
Jes Sorensen265697e2016-04-14 16:37:20 -0400[diff] [blame]8147 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
8148
Jes Sorensenfc89a412016-02-29 17:05:46 -0500[diff] [blame]8149 priv->fops->disable_rf(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8150
8151 /*
8152 * Disable interrupts
8153 */
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]8154 if (priv->usb_interrupts)
8155 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8156
8157 rtl8xxxu_free_rx_resources(priv);
8158 rtl8xxxu_free_tx_resources(priv);
8159}
8160
8161static const struct ieee80211_ops rtl8xxxu_ops = {
8162 .tx = rtl8xxxu_tx,
8163 .add_interface = rtl8xxxu_add_interface,
8164 .remove_interface = rtl8xxxu_remove_interface,
8165 .config = rtl8xxxu_config,
8166 .conf_tx = rtl8xxxu_conf_tx,
8167 .bss_info_changed = rtl8xxxu_bss_info_changed,
8168 .configure_filter = rtl8xxxu_configure_filter,
8169 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
8170 .start = rtl8xxxu_start,
8171 .stop = rtl8xxxu_stop,
8172 .sw_scan_start = rtl8xxxu_sw_scan_start,
8173 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
8174 .set_key = rtl8xxxu_set_key,
8175 .ampdu_action = rtl8xxxu_ampdu_action,
8176};
8177
8178static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
8179 struct usb_interface *interface)
8180{
8181 struct usb_interface_descriptor *interface_desc;
8182 struct usb_host_interface *host_interface;
8183 struct usb_endpoint_descriptor *endpoint;
8184 struct device *dev = &priv->udev->dev;
8185 int i, j = 0, endpoints;
8186 u8 dir, xtype, num;
8187 int ret = 0;
8188
8189 host_interface = &interface->altsetting[0];
8190 interface_desc = &host_interface->desc;
8191 endpoints = interface_desc->bNumEndpoints;
8192
8193 for (i = 0; i < endpoints; i++) {
8194 endpoint = &host_interface->endpoint[i].desc;
8195
8196 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
8197 num = usb_endpoint_num(endpoint);
8198 xtype = usb_endpoint_type(endpoint);
8199 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8200 dev_dbg(dev,
8201 "%s: endpoint: dir %02x, # %02x, type %02x\n",
8202 __func__, dir, num, xtype);
8203 if (usb_endpoint_dir_in(endpoint) &&
8204 usb_endpoint_xfer_bulk(endpoint)) {
8205 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8206 dev_dbg(dev, "%s: in endpoint num %i\n",
8207 __func__, num);
8208
8209 if (priv->pipe_in) {
8210 dev_warn(dev,
8211 "%s: Too many IN pipes\n", __func__);
8212 ret = -EINVAL;
8213 goto exit;
8214 }
8215
8216 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
8217 }
8218
8219 if (usb_endpoint_dir_in(endpoint) &&
8220 usb_endpoint_xfer_int(endpoint)) {
8221 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8222 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
8223 __func__, num);
8224
8225 if (priv->pipe_interrupt) {
8226 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
8227 __func__);
8228 ret = -EINVAL;
8229 goto exit;
8230 }
8231
8232 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
8233 }
8234
8235 if (usb_endpoint_dir_out(endpoint) &&
8236 usb_endpoint_xfer_bulk(endpoint)) {
8237 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
8238 dev_dbg(dev, "%s: out endpoint num %i\n",
8239 __func__, num);
8240 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
8241 dev_warn(dev,
8242 "%s: Too many OUT pipes\n", __func__);
8243 ret = -EINVAL;
8244 goto exit;
8245 }
8246 priv->out_ep[j++] = num;
8247 }
8248 }
8249exit:
8250 priv->nr_out_eps = j;
8251 return ret;
8252}
8253
8254static int rtl8xxxu_probe(struct usb_interface *interface,
8255 const struct usb_device_id *id)
8256{
8257 struct rtl8xxxu_priv *priv;
8258 struct ieee80211_hw *hw;
8259 struct usb_device *udev;
8260 struct ieee80211_supported_band *sband;
8261 int ret = 0;
8262 int untested = 1;
8263
8264 udev = usb_get_dev(interface_to_usbdev(interface));
8265
8266 switch (id->idVendor) {
8267 case USB_VENDOR_ID_REALTEK:
8268 switch(id->idProduct) {
8269 case 0x1724:
8270 case 0x8176:
8271 case 0x8178:
8272 case 0x817f:
8273 untested = 0;
8274 break;
8275 }
8276 break;
8277 case 0x7392:
8278 if (id->idProduct == 0x7811)
8279 untested = 0;
8280 break;
Jes Sorensene1d70c92016-04-14 16:37:06 -0400[diff] [blame]8281 case 0x050d:
8282 if (id->idProduct == 0x1004)
8283 untested = 0;
8284 break;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8285 default:
8286 break;
8287 }
8288
8289 if (untested) {
Jes Sorenseneaa4d142016-02-29 17:04:31 -0500[diff] [blame]8290 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8291 dev_info(&udev->dev,
8292 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
8293 id->idVendor, id->idProduct);
8294 dev_info(&udev->dev,
8295 "Please report results to Jes.Sorensen@gmail.com\n");
8296 }
8297
8298 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
8299 if (!hw) {
8300 ret = -ENOMEM;
8301 goto exit;
8302 }
8303
8304 priv = hw->priv;
8305 priv->hw = hw;
8306 priv->udev = udev;
8307 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
8308 mutex_init(&priv->usb_buf_mutex);
8309 mutex_init(&priv->h2c_mutex);
8310 INIT_LIST_HEAD(&priv->tx_urb_free_list);
8311 spin_lock_init(&priv->tx_urb_lock);
8312 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
8313 spin_lock_init(&priv->rx_urb_lock);
8314 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
8315
8316 usb_set_intfdata(interface, hw);
8317
8318 ret = rtl8xxxu_parse_usb(priv, interface);
8319 if (ret)
8320 goto exit;
8321
8322 ret = rtl8xxxu_identify_chip(priv);
8323 if (ret) {
8324 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8325 goto exit;
8326 }
8327
8328 ret = rtl8xxxu_read_efuse(priv);
8329 if (ret) {
8330 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8331 goto exit;
8332 }
8333
8334 ret = priv->fops->parse_efuse(priv);
8335 if (ret) {
8336 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8337 goto exit;
8338 }
8339
8340 rtl8xxxu_print_chipinfo(priv);
8341
8342 ret = priv->fops->load_firmware(priv);
8343 if (ret) {
8344 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8345 goto exit;
8346 }
8347
8348 ret = rtl8xxxu_init_device(hw);
8349
8350 hw->wiphy->max_scan_ssids = 1;
8351 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8352 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8353 hw->queues = 4;
8354
8355 sband = &rtl8xxxu_supported_band;
8356 sband->ht_cap.ht_supported = true;
8357 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8358 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8359 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8360 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8361 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8362 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8363 if (priv->rf_paths > 1) {
8364 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8365 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8366 }
8367 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8368 /*
8369 * Some APs will negotiate HT20_40 in a noisy environment leading
8370 * to miserable performance. Rather than defaulting to this, only
8371 * enable it if explicitly requested at module load time.
8372 */
8373 if (rtl8xxxu_ht40_2g) {
8374 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8375 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8376 }
Johannes Berg57fbcce2016-04-12 15:56:15 +0200[diff] [blame]8377 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8378
8379 hw->wiphy->rts_threshold = 2347;
8380
8381 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8382 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8383
Jes Sorensen179e1742016-02-29 17:05:27 -0500[diff] [blame]8384 hw->extra_tx_headroom = priv->fops->tx_desc_size;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8385 ieee80211_hw_set(hw, SIGNAL_DBM);
8386 /*
8387 * The firmware handles rate control
8388 */
8389 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8390 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8391
8392 ret = ieee80211_register_hw(priv->hw);
8393 if (ret) {
8394 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8395 __func__, ret);
8396 goto exit;
8397 }
8398
8399exit:
8400 if (ret < 0)
8401 usb_put_dev(udev);
8402 return ret;
8403}
8404
8405static void rtl8xxxu_disconnect(struct usb_interface *interface)
8406{
8407 struct rtl8xxxu_priv *priv;
8408 struct ieee80211_hw *hw;
8409
8410 hw = usb_get_intfdata(interface);
8411 priv = hw->priv;
8412
Jes Sorensen8cae2f12016-04-14 16:37:13 -0400[diff] [blame]8413 ieee80211_unregister_hw(hw);
8414
8415 priv->fops->power_off(priv);
8416
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8417 usb_set_intfdata(interface, NULL);
8418
8419 dev_info(&priv->udev->dev, "disconnecting\n");
8420
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8421 kfree(priv->fw_data);
8422 mutex_destroy(&priv->usb_buf_mutex);
8423 mutex_destroy(&priv->h2c_mutex);
8424
8425 usb_put_dev(priv->udev);
8426 ieee80211_free_hw(hw);
8427}
8428
8429static struct rtl8xxxu_fileops rtl8723au_fops = {
8430 .parse_efuse = rtl8723au_parse_efuse,
8431 .load_firmware = rtl8723au_load_firmware,
8432 .power_on = rtl8723au_power_on,
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]8433 .power_off = rtl8xxxu_power_off,
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]8434 .reset_8051 = rtl8xxxu_reset_8051,
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]8435 .llt_init = rtl8xxxu_init_llt_table,
Jes Sorensende7c1892016-04-18 11:49:30 -0400[diff] [blame]8436 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]8437 .init_phy_rf = rtl8723au_init_phy_rf,
Jes Sorensen28466e92016-04-18 11:49:29 -0400[diff] [blame]8438 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
Jes Sorensene09718c2016-04-18 11:49:27 -0400[diff] [blame]8439 .config_channel = rtl8xxxu_gen1_config_channel,
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8440 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
Jes Sorensen8396a412016-04-18 11:49:32 -0400[diff] [blame]8441 .enable_rf = rtl8xxxu_gen1_enable_rf,
Jes Sorensen7eb14002016-04-18 11:49:26 -0400[diff] [blame]8442 .disable_rf = rtl8xxxu_gen1_disable_rf,
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]8443 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
Jes Sorensen42a3bc72016-04-18 11:49:31 -0400[diff] [blame]8444 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
Jes Sorensenc6e39da2016-04-18 11:49:28 -0400[diff] [blame]8445 .update_rate_mask = rtl8xxxu_update_rate_mask,
Jes Sorensenbeb55312016-04-18 11:49:23 -0400[diff] [blame]8446 .report_connect = rtl8xxxu_gen1_report_connect,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8447 .writeN_block_size = 1024,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]8448 .mbox_ext_reg = REG_HMBOX_EXT_0,
8449 .mbox_ext_width = 2,
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]8450 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8451 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
Jes Sorensen8634af52016-02-29 17:04:33 -0500[diff] [blame]8452 .adda_1t_init = 0x0b1b25a0,
8453 .adda_1t_path_on = 0x0bdb25a0,
8454 .adda_2t_path_on_a = 0x04db25a4,
8455 .adda_2t_path_on_b = 0x0b1b25a4,
Jes Sorensen24e8e7e2016-04-14 14:59:01 -0400[diff] [blame]8456 .trxff_boundary = 0x27ff,
Jes Sorensen9b323ee2016-04-14 14:59:03 -0400[diff] [blame]8457 .pbp_rx = PBP_PAGE_SIZE_128,
8458 .pbp_tx = PBP_PAGE_SIZE_128,
Jes Sorensen8db71452016-04-18 11:49:33 -0400[diff] [blame]8459 .mactable = rtl8xxxu_gen1_mac_init_table,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8460};
8461
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]8462static struct rtl8xxxu_fileops rtl8723bu_fops = {
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]8463 .parse_efuse = rtl8723bu_parse_efuse,
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]8464 .load_firmware = rtl8723bu_load_firmware,
Jes Sorensen42836db2016-02-29 17:04:52 -0500[diff] [blame]8465 .power_on = rtl8723bu_power_on,
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]8466 .power_off = rtl8723bu_power_off,
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]8467 .reset_8051 = rtl8723bu_reset_8051,
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]8468 .llt_init = rtl8xxxu_auto_llt_table,
Jes Sorensencb877252016-04-14 14:58:57 -0400[diff] [blame]8469 .init_phy_bb = rtl8723bu_init_phy_bb,
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]8470 .init_phy_rf = rtl8723bu_init_phy_rf,
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]8471 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
Jes Sorensene1547c52016-02-29 17:04:35 -0500[diff] [blame]8472 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
Jes Sorensen3a56bf62016-04-18 11:49:24 -0400[diff] [blame]8473 .config_channel = rtl8xxxu_gen2_config_channel,
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8474 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
Jes Sorensen3e88ca42016-02-29 17:05:08 -0500[diff] [blame]8475 .init_aggregation = rtl8723bu_init_aggregation,
Jes Sorensen9c79bf92016-02-29 17:05:10 -0500[diff] [blame]8476 .init_statistics = rtl8723bu_init_statistics,
Jes Sorensendb08de92016-02-29 17:05:17 -0500[diff] [blame]8477 .enable_rf = rtl8723b_enable_rf,
Jes Sorensen6a07b792016-04-18 11:49:25 -0400[diff] [blame]8478 .disable_rf = rtl8xxxu_gen2_disable_rf,
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]8479 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
Jes Sorensene796dab2016-02-29 17:05:19 -0500[diff] [blame]8480 .set_tx_power = rtl8723b_set_tx_power,
Jes Sorensena8c8dfa2016-04-18 11:49:21 -0400[diff] [blame]8481 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
Jes Sorensen32353a72016-04-18 11:49:22 -0400[diff] [blame]8482 .report_connect = rtl8xxxu_gen2_report_connect,
Jes Sorensenadfc0122016-02-29 17:04:12 -0500[diff] [blame]8483 .writeN_block_size = 1024,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]8484 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8485 .mbox_ext_width = 4,
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]8486 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8487 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
Jes Sorensen0d698de2016-02-29 17:04:36 -0500[diff] [blame]8488 .has_s0s1 = 1,
Jes Sorensen8634af52016-02-29 17:04:33 -0500[diff] [blame]8489 .adda_1t_init = 0x01c00014,
8490 .adda_1t_path_on = 0x01c00014,
8491 .adda_2t_path_on_a = 0x01c00014,
8492 .adda_2t_path_on_b = 0x01c00014,
Jes Sorensen24e8e7e2016-04-14 14:59:01 -0400[diff] [blame]8493 .trxff_boundary = 0x3f7f,
Jes Sorensen9b323ee2016-04-14 14:59:03 -0400[diff] [blame]8494 .pbp_rx = PBP_PAGE_SIZE_256,
8495 .pbp_tx = PBP_PAGE_SIZE_256,
Jes Sorensenc606e662016-04-07 14:19:16 -0400[diff] [blame]8496 .mactable = rtl8723b_mac_init_table,
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]8497};
8498
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]8499#ifdef CONFIG_RTL8XXXU_UNTESTED
8500
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8501static struct rtl8xxxu_fileops rtl8192cu_fops = {
8502 .parse_efuse = rtl8192cu_parse_efuse,
8503 .load_firmware = rtl8192cu_load_firmware,
8504 .power_on = rtl8192cu_power_on,
Jes Sorensenfe37d5f2016-02-29 17:05:47 -0500[diff] [blame]8505 .power_off = rtl8xxxu_power_off,
Jes Sorensen7d4ccb82016-02-29 17:05:50 -0500[diff] [blame]8506 .reset_8051 = rtl8xxxu_reset_8051,
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]8507 .llt_init = rtl8xxxu_init_llt_table,
Jes Sorensende7c1892016-04-18 11:49:30 -0400[diff] [blame]8508 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
Jes Sorensen4062b8f2016-04-14 16:37:08 -0400[diff] [blame]8509 .init_phy_rf = rtl8192cu_init_phy_rf,
Jes Sorensen28466e92016-04-18 11:49:29 -0400[diff] [blame]8510 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
Jes Sorensene09718c2016-04-18 11:49:27 -0400[diff] [blame]8511 .config_channel = rtl8xxxu_gen1_config_channel,
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8512 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
Jes Sorensen8396a412016-04-18 11:49:32 -0400[diff] [blame]8513 .enable_rf = rtl8xxxu_gen1_enable_rf,
Jes Sorensen7eb14002016-04-18 11:49:26 -0400[diff] [blame]8514 .disable_rf = rtl8xxxu_gen1_disable_rf,
Jes Sorensen747bf232016-04-14 14:59:04 -0400[diff] [blame]8515 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
Jes Sorensen42a3bc72016-04-18 11:49:31 -0400[diff] [blame]8516 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
Jes Sorensenc6e39da2016-04-18 11:49:28 -0400[diff] [blame]8517 .update_rate_mask = rtl8xxxu_update_rate_mask,
Jes Sorensenbeb55312016-04-18 11:49:23 -0400[diff] [blame]8518 .report_connect = rtl8xxxu_gen1_report_connect,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8519 .writeN_block_size = 128,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]8520 .mbox_ext_reg = REG_HMBOX_EXT_0,
8521 .mbox_ext_width = 2,
Jes Sorensendbb28962016-03-31 17:08:33 -0400[diff] [blame]8522 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
Jes Sorensena49c7ce2016-04-14 14:58:52 -0400[diff] [blame]8523 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
Jes Sorensen8634af52016-02-29 17:04:33 -0500[diff] [blame]8524 .adda_1t_init = 0x0b1b25a0,
8525 .adda_1t_path_on = 0x0bdb25a0,
8526 .adda_2t_path_on_a = 0x04db25a4,
8527 .adda_2t_path_on_b = 0x0b1b25a4,
Jes Sorensen24e8e7e2016-04-14 14:59:01 -0400[diff] [blame]8528 .trxff_boundary = 0x27ff,
Jes Sorensen9b323ee2016-04-14 14:59:03 -0400[diff] [blame]8529 .pbp_rx = PBP_PAGE_SIZE_128,
8530 .pbp_tx = PBP_PAGE_SIZE_128,
Jes Sorensen8db71452016-04-18 11:49:33 -0400[diff] [blame]8531 .mactable = rtl8xxxu_gen1_mac_init_table,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8532};
8533
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]8534#endif
8535
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8536static struct usb_device_id dev_table[] = {
8537{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8538 .driver_info = (unsigned long)&rtl8723au_fops},
8539{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8540 .driver_info = (unsigned long)&rtl8723au_fops},
8541{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8542 .driver_info = (unsigned long)&rtl8723au_fops},
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]8543{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8544 .driver_info = (unsigned long)&rtl8192eu_fops},
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]8545{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8546 .driver_info = (unsigned long)&rtl8723bu_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]8547#ifdef CONFIG_RTL8XXXU_UNTESTED
8548/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8549{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8550 .driver_info = (unsigned long)&rtl8192cu_fops},
8551{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8552 .driver_info = (unsigned long)&rtl8192cu_fops},
8553{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8554 .driver_info = (unsigned long)&rtl8192cu_fops},
8555/* Tested by Larry Finger */
8556{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8557 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensene1d70c92016-04-14 16:37:06 -0400[diff] [blame]8558/* Tested by Andrea Merello */
8559{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8560 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8561/* Currently untested 8188 series devices */
8562{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8563 .driver_info = (unsigned long)&rtl8192cu_fops},
8564{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8565 .driver_info = (unsigned long)&rtl8192cu_fops},
8566{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8567 .driver_info = (unsigned long)&rtl8192cu_fops},
8568{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8569 .driver_info = (unsigned long)&rtl8192cu_fops},
8570{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8571 .driver_info = (unsigned long)&rtl8192cu_fops},
8572{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8573 .driver_info = (unsigned long)&rtl8192cu_fops},
8574{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8575 .driver_info = (unsigned long)&rtl8192cu_fops},
8576{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8577 .driver_info = (unsigned long)&rtl8192cu_fops},
8578{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8579 .driver_info = (unsigned long)&rtl8192cu_fops},
8580{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8581 .driver_info = (unsigned long)&rtl8192cu_fops},
8582{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8583 .driver_info = (unsigned long)&rtl8192cu_fops},
8584{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8585 .driver_info = (unsigned long)&rtl8192cu_fops},
8586{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8587 .driver_info = (unsigned long)&rtl8192cu_fops},
8588{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8589 .driver_info = (unsigned long)&rtl8192cu_fops},
8590{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8591 .driver_info = (unsigned long)&rtl8192cu_fops},
8592{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8593 .driver_info = (unsigned long)&rtl8192cu_fops},
8594{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8595 .driver_info = (unsigned long)&rtl8192cu_fops},
8596{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8597 .driver_info = (unsigned long)&rtl8192cu_fops},
8598{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8599 .driver_info = (unsigned long)&rtl8192cu_fops},
8600{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8601 .driver_info = (unsigned long)&rtl8192cu_fops},
8602{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8603 .driver_info = (unsigned long)&rtl8192cu_fops},
8604{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8605 .driver_info = (unsigned long)&rtl8192cu_fops},
8606{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8607 .driver_info = (unsigned long)&rtl8192cu_fops},
8608{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8609 .driver_info = (unsigned long)&rtl8192cu_fops},
8610{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8611 .driver_info = (unsigned long)&rtl8192cu_fops},
8612{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8613 .driver_info = (unsigned long)&rtl8192cu_fops},
8614{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8615 .driver_info = (unsigned long)&rtl8192cu_fops},
8616{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8617 .driver_info = (unsigned long)&rtl8192cu_fops},
8618{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8619 .driver_info = (unsigned long)&rtl8192cu_fops},
8620{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8621 .driver_info = (unsigned long)&rtl8192cu_fops},
8622{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8623 .driver_info = (unsigned long)&rtl8192cu_fops},
8624{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8625 .driver_info = (unsigned long)&rtl8192cu_fops},
8626{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8627 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8628{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8629 .driver_info = (unsigned long)&rtl8192cu_fops},
8630{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8631 .driver_info = (unsigned long)&rtl8192cu_fops},
8632{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8633 .driver_info = (unsigned long)&rtl8192cu_fops},
8634{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8635 .driver_info = (unsigned long)&rtl8192cu_fops},
8636{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8637 .driver_info = (unsigned long)&rtl8192cu_fops},
8638{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8639 .driver_info = (unsigned long)&rtl8192cu_fops},
8640{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8641 .driver_info = (unsigned long)&rtl8192cu_fops},
8642/* Currently untested 8192 series devices */
8643{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8644 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8645{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8646 .driver_info = (unsigned long)&rtl8192cu_fops},
8647{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8648 .driver_info = (unsigned long)&rtl8192cu_fops},
8649{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8650 .driver_info = (unsigned long)&rtl8192cu_fops},
8651{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8652 .driver_info = (unsigned long)&rtl8192cu_fops},
8653{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8654 .driver_info = (unsigned long)&rtl8192cu_fops},
8655{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8656 .driver_info = (unsigned long)&rtl8192cu_fops},
8657{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8658 .driver_info = (unsigned long)&rtl8192cu_fops},
8659{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8660 .driver_info = (unsigned long)&rtl8192cu_fops},
8661{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8662 .driver_info = (unsigned long)&rtl8192cu_fops},
8663{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8664 .driver_info = (unsigned long)&rtl8192cu_fops},
8665{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8666 .driver_info = (unsigned long)&rtl8192cu_fops},
8667{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8668 .driver_info = (unsigned long)&rtl8192cu_fops},
8669{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8670 .driver_info = (unsigned long)&rtl8192cu_fops},
8671{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8672 .driver_info = (unsigned long)&rtl8192cu_fops},
8673{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8674 .driver_info = (unsigned long)&rtl8192cu_fops},
8675{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8676 .driver_info = (unsigned long)&rtl8192cu_fops},
8677{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8678 .driver_info = (unsigned long)&rtl8192cu_fops},
8679{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8680 .driver_info = (unsigned long)&rtl8192cu_fops},
8681{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8682 .driver_info = (unsigned long)&rtl8192cu_fops},
8683{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8684 .driver_info = (unsigned long)&rtl8192cu_fops},
8685{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8686 .driver_info = (unsigned long)&rtl8192cu_fops},
8687{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8688 .driver_info = (unsigned long)&rtl8192cu_fops},
8689{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8690 .driver_info = (unsigned long)&rtl8192cu_fops},
8691#endif
8692{ }
8693};
8694
8695static struct usb_driver rtl8xxxu_driver = {
8696 .name = DRIVER_NAME,
8697 .probe = rtl8xxxu_probe,
8698 .disconnect = rtl8xxxu_disconnect,
8699 .id_table = dev_table,
Jes Sorensen6a62f9d2016-04-14 16:37:18 -0400[diff] [blame]8700 .no_dynamic_id = 1,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]8701 .disable_hub_initiated_lpm = 1,
8702};
8703
8704static int __init rtl8xxxu_module_init(void)
8705{
8706 int res;
8707
8708 res = usb_register(&rtl8xxxu_driver);
8709 if (res < 0)
8710 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8711
8712 return res;
8713}
8714
8715static void __exit rtl8xxxu_module_exit(void)
8716{
8717 usb_deregister(&rtl8xxxu_driver);
8718}
8719
8720
8721MODULE_DEVICE_TABLE(usb, dev_table);
8722
8723module_init(rtl8xxxu_module_init);
8724module_exit(rtl8xxxu_module_exit);