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Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.c: Broadcom NX2 network driver.
2 *
Michael Chana6952b52009-02-12 16:54:48 -08003 * Copyright (c) 2004-2009 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
Michael Chanf2a4f052006-03-23 01:13:12 -080012
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070029#include <linux/bitops.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080030#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
Michael Chanc86a31f2006-06-13 15:03:47 -070034#include <asm/page.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080035#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080038#include <linux/if_vlan.h>
David S. Miller08013fa2008-08-15 19:46:01 -070039#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
Michael Chanf2a4f052006-03-23 01:13:12 -080040#define BCM_VLAN 1
41#endif
Michael Chanf2a4f052006-03-23 01:13:12 -080042#include <net/ip.h>
Linus Torvaldsde081fa2007-07-12 16:40:08 -070043#include <net/tcp.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080044#include <net/checksum.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080045#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
Michael Chan29b12172006-03-23 01:13:43 -080048#include <linux/cache.h>
Michael Chan57579f72009-04-04 16:51:14 -070049#include <linux/firmware.h>
Benjamin Li706bf242008-07-18 17:55:11 -070050#include <linux/log2.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080051
Michael Chanb6016b72005-05-26 13:03:09 -070052#include "bnx2.h"
53#include "bnx2_fw.h"
Denys Vlasenkob3448b02007-09-30 17:55:51 -070054
Michael Chanb6016b72005-05-26 13:03:09 -070055#define DRV_MODULE_NAME "bnx2"
56#define PFX DRV_MODULE_NAME ": "
Michael Chan57579f72009-04-04 16:51:14 -070057#define DRV_MODULE_VERSION "2.0.0"
58#define DRV_MODULE_RELDATE "April 2, 2009"
59#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-4.6.16.fw"
60#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-4.6.16.fw"
61#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-4.6.17.fw"
62#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-4.6.15.fw"
Michael Chanb6016b72005-05-26 13:03:09 -070063
64#define RUN_AT(x) (jiffies + (x))
65
66/* Time in jiffies before concluding the transmitter is hung. */
67#define TX_TIMEOUT (5*HZ)
68
Andrew Mortonfefa8642008-02-09 23:17:15 -080069static char version[] __devinitdata =
Michael Chanb6016b72005-05-26 13:03:09 -070070 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71
72MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
Benjamin Li453a9c62008-09-18 16:39:16 -070073MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
Michael Chanb6016b72005-05-26 13:03:09 -070074MODULE_LICENSE("GPL");
75MODULE_VERSION(DRV_MODULE_VERSION);
Michael Chan57579f72009-04-04 16:51:14 -070076MODULE_FIRMWARE(FW_MIPS_FILE_06);
77MODULE_FIRMWARE(FW_RV2P_FILE_06);
78MODULE_FIRMWARE(FW_MIPS_FILE_09);
79MODULE_FIRMWARE(FW_RV2P_FILE_09);
Michael Chanb6016b72005-05-26 13:03:09 -070080
81static int disable_msi = 0;
82
83module_param(disable_msi, int, 0);
84MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
85
86typedef enum {
87 BCM5706 = 0,
88 NC370T,
89 NC370I,
90 BCM5706S,
91 NC370F,
Michael Chan5b0c76a2005-11-04 08:45:49 -080092 BCM5708,
93 BCM5708S,
Michael Chanbac0dff2006-11-19 14:15:05 -080094 BCM5709,
Michael Chan27a005b2007-05-03 13:23:41 -070095 BCM5709S,
Michael Chan7bb0a042008-07-14 22:37:47 -070096 BCM5716,
Michael Chan1caacec2008-11-12 16:01:12 -080097 BCM5716S,
Michael Chanb6016b72005-05-26 13:03:09 -070098} board_t;
99
100/* indexed by board_t, above */
Andrew Mortonfefa8642008-02-09 23:17:15 -0800101static struct {
Michael Chanb6016b72005-05-26 13:03:09 -0700102 char *name;
103} board_info[] __devinitdata = {
104 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
105 { "HP NC370T Multifunction Gigabit Server Adapter" },
106 { "HP NC370i Multifunction Gigabit Server Adapter" },
107 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
108 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800109 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
110 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
Michael Chanbac0dff2006-11-19 14:15:05 -0800111 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
Michael Chan27a005b2007-05-03 13:23:41 -0700112 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
Michael Chan7bb0a042008-07-14 22:37:47 -0700113 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
Michael Chan1caacec2008-11-12 16:01:12 -0800114 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
Michael Chanb6016b72005-05-26 13:03:09 -0700115 };
116
Michael Chan7bb0a042008-07-14 22:37:47 -0700117static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
Michael Chanb6016b72005-05-26 13:03:09 -0700118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
119 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
121 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
Michael Chanb6016b72005-05-26 13:03:09 -0700126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
127 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
Michael Chanbac0dff2006-11-19 14:15:05 -0800132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
Michael Chan27a005b2007-05-03 13:23:41 -0700134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
Michael Chan7bb0a042008-07-14 22:37:47 -0700136 { PCI_VENDOR_ID_BROADCOM, 0x163b,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
Michael Chan1caacec2008-11-12 16:01:12 -0800138 { PCI_VENDOR_ID_BROADCOM, 0x163c,
Michael Chan1f2435e2008-12-16 20:28:13 -0800139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
Michael Chanb6016b72005-05-26 13:03:09 -0700140 { 0, }
141};
142
143static struct flash_spec flash_table[] =
144{
Michael Chane30372c2007-07-16 18:26:23 -0700145#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
146#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
Michael Chanb6016b72005-05-26 13:03:09 -0700147 /* Slow EEPROM */
Michael Chan37137702005-11-04 08:49:17 -0800148 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700149 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700150 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
151 "EEPROM - slow"},
Michael Chan37137702005-11-04 08:49:17 -0800152 /* Expansion entry 0001 */
153 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700154 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
156 "Entry 0001"},
Michael Chanb6016b72005-05-26 13:03:09 -0700157 /* Saifun SA25F010 (non-buffered flash) */
158 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800159 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700161 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
162 "Non-buffered flash (128kB)"},
163 /* Saifun SA25F020 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800165 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
168 "Non-buffered flash (256kB)"},
Michael Chan37137702005-11-04 08:49:17 -0800169 /* Expansion entry 0100 */
170 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800172 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
173 "Entry 0100"},
174 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400175 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700176 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800177 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
178 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
179 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
180 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
183 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
184 /* Saifun SA25F005 (non-buffered flash) */
185 /* strap, cfg1, & write1 need updates */
186 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700187 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800188 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
189 "Non-buffered flash (64kB)"},
190 /* Fast EEPROM */
191 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700192 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800193 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
194 "EEPROM - fast"},
195 /* Expansion entry 1001 */
196 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700197 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199 "Entry 1001"},
200 /* Expansion entry 1010 */
201 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1010"},
205 /* ATMEL AT45DB011B (buffered flash) */
206 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700207 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800208 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
209 "Buffered flash (128kB)"},
210 /* Expansion entry 1100 */
211 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
214 "Entry 1100"},
215 /* Expansion entry 1101 */
216 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1101"},
220 /* Ateml Expansion entry 1110 */
221 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700222 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800223 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1110 (Atmel)"},
225 /* ATMEL AT45DB021B (buffered flash) */
226 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800228 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
229 "Buffered flash (256kB)"},
Michael Chanb6016b72005-05-26 13:03:09 -0700230};
231
Michael Chane30372c2007-07-16 18:26:23 -0700232static struct flash_spec flash_5709 = {
233 .flags = BNX2_NV_BUFFERED,
234 .page_bits = BCM5709_FLASH_PAGE_BITS,
235 .page_size = BCM5709_FLASH_PAGE_SIZE,
236 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
237 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
238 .name = "5709 Buffered flash (256kB)",
239};
240
Michael Chanb6016b72005-05-26 13:03:09 -0700241MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
242
Michael Chan35e90102008-06-19 16:37:42 -0700243static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
Michael Chane89bbf12005-08-25 15:36:58 -0700244{
Michael Chan2f8af122006-08-15 01:39:10 -0700245 u32 diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700246
Michael Chan2f8af122006-08-15 01:39:10 -0700247 smp_mb();
Michael Chanfaac9c42006-12-14 15:56:32 -0800248
249 /* The ring uses 256 indices for 255 entries, one of them
250 * needs to be skipped.
251 */
Michael Chan35e90102008-06-19 16:37:42 -0700252 diff = txr->tx_prod - txr->tx_cons;
Michael Chanfaac9c42006-12-14 15:56:32 -0800253 if (unlikely(diff >= TX_DESC_CNT)) {
254 diff &= 0xffff;
255 if (diff == TX_DESC_CNT)
256 diff = MAX_TX_DESC_CNT;
257 }
Michael Chane89bbf12005-08-25 15:36:58 -0700258 return (bp->tx_ring_size - diff);
259}
260
Michael Chanb6016b72005-05-26 13:03:09 -0700261static u32
262bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
263{
Michael Chan1b8227c2007-05-03 13:24:05 -0700264 u32 val;
265
266 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700267 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
Michael Chan1b8227c2007-05-03 13:24:05 -0700268 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
269 spin_unlock_bh(&bp->indirect_lock);
270 return val;
Michael Chanb6016b72005-05-26 13:03:09 -0700271}
272
273static void
274bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
275{
Michael Chan1b8227c2007-05-03 13:24:05 -0700276 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700277 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
Michael Chan1b8227c2007-05-03 13:24:05 -0700279 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700280}
281
282static void
Michael Chan2726d6e2008-01-29 21:35:05 -0800283bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
284{
285 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
286}
287
288static u32
289bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
290{
291 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
292}
293
294static void
Michael Chanb6016b72005-05-26 13:03:09 -0700295bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
296{
297 offset += cid_addr;
Michael Chan1b8227c2007-05-03 13:24:05 -0700298 spin_lock_bh(&bp->indirect_lock);
Michael Chan59b47d82006-11-19 14:10:45 -0800299 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
300 int i;
301
302 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
303 REG_WR(bp, BNX2_CTX_CTX_CTRL,
304 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
305 for (i = 0; i < 5; i++) {
Michael Chan59b47d82006-11-19 14:10:45 -0800306 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
307 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
308 break;
309 udelay(5);
310 }
311 } else {
312 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
313 REG_WR(bp, BNX2_CTX_DATA, val);
314 }
Michael Chan1b8227c2007-05-03 13:24:05 -0700315 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700316}
317
318static int
319bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
320{
321 u32 val1;
322 int i, ret;
323
Michael Chan583c28e2008-01-21 19:51:35 -0800324 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700325 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
326 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
327
328 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
329 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
330
331 udelay(40);
332 }
333
334 val1 = (bp->phy_addr << 21) | (reg << 16) |
335 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
336 BNX2_EMAC_MDIO_COMM_START_BUSY;
337 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
338
339 for (i = 0; i < 50; i++) {
340 udelay(10);
341
342 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
343 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
344 udelay(5);
345
346 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
347 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
348
349 break;
350 }
351 }
352
353 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
354 *val = 0x0;
355 ret = -EBUSY;
356 }
357 else {
358 *val = val1;
359 ret = 0;
360 }
361
Michael Chan583c28e2008-01-21 19:51:35 -0800362 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700363 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
364 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
365
366 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
367 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
368
369 udelay(40);
370 }
371
372 return ret;
373}
374
375static int
376bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
377{
378 u32 val1;
379 int i, ret;
380
Michael Chan583c28e2008-01-21 19:51:35 -0800381 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700382 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
383 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
384
385 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
386 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
387
388 udelay(40);
389 }
390
391 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
392 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
393 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
394 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400395
Michael Chanb6016b72005-05-26 13:03:09 -0700396 for (i = 0; i < 50; i++) {
397 udelay(10);
398
399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
400 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
401 udelay(5);
402 break;
403 }
404 }
405
406 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
407 ret = -EBUSY;
408 else
409 ret = 0;
410
Michael Chan583c28e2008-01-21 19:51:35 -0800411 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700412 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
413 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
414
415 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
416 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
417
418 udelay(40);
419 }
420
421 return ret;
422}
423
424static void
425bnx2_disable_int(struct bnx2 *bp)
426{
Michael Chanb4b36042007-12-20 19:59:30 -0800427 int i;
428 struct bnx2_napi *bnapi;
429
430 for (i = 0; i < bp->irq_nvecs; i++) {
431 bnapi = &bp->bnx2_napi[i];
432 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
433 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
434 }
Michael Chanb6016b72005-05-26 13:03:09 -0700435 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
436}
437
438static void
439bnx2_enable_int(struct bnx2 *bp)
440{
Michael Chanb4b36042007-12-20 19:59:30 -0800441 int i;
442 struct bnx2_napi *bnapi;
Michael Chan1269a8a2006-01-23 16:11:03 -0800443
Michael Chanb4b36042007-12-20 19:59:30 -0800444 for (i = 0; i < bp->irq_nvecs; i++) {
445 bnapi = &bp->bnx2_napi[i];
Michael Chan35efa7c2007-12-20 19:56:37 -0800446
Michael Chanb4b36042007-12-20 19:59:30 -0800447 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
448 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
449 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
450 bnapi->last_status_idx);
Michael Chanb6016b72005-05-26 13:03:09 -0700451
Michael Chanb4b36042007-12-20 19:59:30 -0800452 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
453 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
454 bnapi->last_status_idx);
455 }
Michael Chanbf5295b2006-03-23 01:11:56 -0800456 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -0700457}
458
459static void
460bnx2_disable_int_sync(struct bnx2 *bp)
461{
Michael Chanb4b36042007-12-20 19:59:30 -0800462 int i;
463
Michael Chanb6016b72005-05-26 13:03:09 -0700464 atomic_inc(&bp->intr_sem);
465 bnx2_disable_int(bp);
Michael Chanb4b36042007-12-20 19:59:30 -0800466 for (i = 0; i < bp->irq_nvecs; i++)
467 synchronize_irq(bp->irq_tbl[i].vector);
Michael Chanb6016b72005-05-26 13:03:09 -0700468}
469
470static void
Michael Chan35efa7c2007-12-20 19:56:37 -0800471bnx2_napi_disable(struct bnx2 *bp)
472{
Michael Chanb4b36042007-12-20 19:59:30 -0800473 int i;
474
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_disable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800477}
478
479static void
480bnx2_napi_enable(struct bnx2 *bp)
481{
Michael Chanb4b36042007-12-20 19:59:30 -0800482 int i;
483
484 for (i = 0; i < bp->irq_nvecs; i++)
485 napi_enable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800486}
487
488static void
Michael Chanb6016b72005-05-26 13:03:09 -0700489bnx2_netif_stop(struct bnx2 *bp)
490{
491 bnx2_disable_int_sync(bp);
492 if (netif_running(bp->dev)) {
Michael Chan35efa7c2007-12-20 19:56:37 -0800493 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700494 netif_tx_disable(bp->dev);
495 bp->dev->trans_start = jiffies; /* prevent tx timeout */
496 }
497}
498
499static void
500bnx2_netif_start(struct bnx2 *bp)
501{
502 if (atomic_dec_and_test(&bp->intr_sem)) {
503 if (netif_running(bp->dev)) {
Benjamin Li706bf242008-07-18 17:55:11 -0700504 netif_tx_wake_all_queues(bp->dev);
Michael Chan35efa7c2007-12-20 19:56:37 -0800505 bnx2_napi_enable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700506 bnx2_enable_int(bp);
507 }
508 }
509}
510
511static void
Michael Chan35e90102008-06-19 16:37:42 -0700512bnx2_free_tx_mem(struct bnx2 *bp)
513{
514 int i;
515
516 for (i = 0; i < bp->num_tx_rings; i++) {
517 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
518 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
519
520 if (txr->tx_desc_ring) {
521 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
522 txr->tx_desc_ring,
523 txr->tx_desc_mapping);
524 txr->tx_desc_ring = NULL;
525 }
526 kfree(txr->tx_buf_ring);
527 txr->tx_buf_ring = NULL;
528 }
529}
530
Michael Chanbb4f98a2008-06-19 16:38:19 -0700531static void
532bnx2_free_rx_mem(struct bnx2 *bp)
533{
534 int i;
535
536 for (i = 0; i < bp->num_rx_rings; i++) {
537 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
538 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
539 int j;
540
541 for (j = 0; j < bp->rx_max_ring; j++) {
542 if (rxr->rx_desc_ring[j])
543 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
544 rxr->rx_desc_ring[j],
545 rxr->rx_desc_mapping[j]);
546 rxr->rx_desc_ring[j] = NULL;
547 }
548 if (rxr->rx_buf_ring)
549 vfree(rxr->rx_buf_ring);
550 rxr->rx_buf_ring = NULL;
551
552 for (j = 0; j < bp->rx_max_pg_ring; j++) {
553 if (rxr->rx_pg_desc_ring[j])
554 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
Michael Chan3298a732008-12-17 19:06:08 -0800555 rxr->rx_pg_desc_ring[j],
556 rxr->rx_pg_desc_mapping[j]);
557 rxr->rx_pg_desc_ring[j] = NULL;
Michael Chanbb4f98a2008-06-19 16:38:19 -0700558 }
559 if (rxr->rx_pg_ring)
560 vfree(rxr->rx_pg_ring);
561 rxr->rx_pg_ring = NULL;
562 }
563}
564
Michael Chan35e90102008-06-19 16:37:42 -0700565static int
566bnx2_alloc_tx_mem(struct bnx2 *bp)
567{
568 int i;
569
570 for (i = 0; i < bp->num_tx_rings; i++) {
571 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
572 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
573
574 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
575 if (txr->tx_buf_ring == NULL)
576 return -ENOMEM;
577
578 txr->tx_desc_ring =
579 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
580 &txr->tx_desc_mapping);
581 if (txr->tx_desc_ring == NULL)
582 return -ENOMEM;
583 }
584 return 0;
585}
586
Michael Chanbb4f98a2008-06-19 16:38:19 -0700587static int
588bnx2_alloc_rx_mem(struct bnx2 *bp)
589{
590 int i;
591
592 for (i = 0; i < bp->num_rx_rings; i++) {
593 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
594 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
595 int j;
596
597 rxr->rx_buf_ring =
598 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
599 if (rxr->rx_buf_ring == NULL)
600 return -ENOMEM;
601
602 memset(rxr->rx_buf_ring, 0,
603 SW_RXBD_RING_SIZE * bp->rx_max_ring);
604
605 for (j = 0; j < bp->rx_max_ring; j++) {
606 rxr->rx_desc_ring[j] =
607 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
608 &rxr->rx_desc_mapping[j]);
609 if (rxr->rx_desc_ring[j] == NULL)
610 return -ENOMEM;
611
612 }
613
614 if (bp->rx_pg_ring_size) {
615 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
616 bp->rx_max_pg_ring);
617 if (rxr->rx_pg_ring == NULL)
618 return -ENOMEM;
619
620 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
621 bp->rx_max_pg_ring);
622 }
623
624 for (j = 0; j < bp->rx_max_pg_ring; j++) {
625 rxr->rx_pg_desc_ring[j] =
626 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
627 &rxr->rx_pg_desc_mapping[j]);
628 if (rxr->rx_pg_desc_ring[j] == NULL)
629 return -ENOMEM;
630
631 }
632 }
633 return 0;
634}
635
Michael Chan35e90102008-06-19 16:37:42 -0700636static void
Michael Chanb6016b72005-05-26 13:03:09 -0700637bnx2_free_mem(struct bnx2 *bp)
638{
Michael Chan13daffa2006-03-20 17:49:20 -0800639 int i;
Michael Chan43e80b82008-06-19 16:41:08 -0700640 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan13daffa2006-03-20 17:49:20 -0800641
Michael Chan35e90102008-06-19 16:37:42 -0700642 bnx2_free_tx_mem(bp);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700643 bnx2_free_rx_mem(bp);
Michael Chan35e90102008-06-19 16:37:42 -0700644
Michael Chan59b47d82006-11-19 14:10:45 -0800645 for (i = 0; i < bp->ctx_pages; i++) {
646 if (bp->ctx_blk[i]) {
647 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
648 bp->ctx_blk[i],
649 bp->ctx_blk_mapping[i]);
650 bp->ctx_blk[i] = NULL;
651 }
652 }
Michael Chan43e80b82008-06-19 16:41:08 -0700653 if (bnapi->status_blk.msi) {
Michael Chan0f31f992006-03-23 01:12:38 -0800654 pci_free_consistent(bp->pdev, bp->status_stats_size,
Michael Chan43e80b82008-06-19 16:41:08 -0700655 bnapi->status_blk.msi,
656 bp->status_blk_mapping);
657 bnapi->status_blk.msi = NULL;
Michael Chan0f31f992006-03-23 01:12:38 -0800658 bp->stats_blk = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700659 }
Michael Chanb6016b72005-05-26 13:03:09 -0700660}
661
662static int
663bnx2_alloc_mem(struct bnx2 *bp)
664{
Michael Chan35e90102008-06-19 16:37:42 -0700665 int i, status_blk_size, err;
Michael Chan43e80b82008-06-19 16:41:08 -0700666 struct bnx2_napi *bnapi;
667 void *status_blk;
Michael Chanb6016b72005-05-26 13:03:09 -0700668
Michael Chan0f31f992006-03-23 01:12:38 -0800669 /* Combine status and statistics blocks into one allocation. */
670 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
David S. Millerf86e82f2008-01-21 17:15:40 -0800671 if (bp->flags & BNX2_FLAG_MSIX_CAP)
Michael Chanb4b36042007-12-20 19:59:30 -0800672 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
673 BNX2_SBLK_MSIX_ALIGN_SIZE);
Michael Chan0f31f992006-03-23 01:12:38 -0800674 bp->status_stats_size = status_blk_size +
675 sizeof(struct statistics_block);
676
Michael Chan43e80b82008-06-19 16:41:08 -0700677 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
678 &bp->status_blk_mapping);
679 if (status_blk == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -0700680 goto alloc_mem_err;
681
Michael Chan43e80b82008-06-19 16:41:08 -0700682 memset(status_blk, 0, bp->status_stats_size);
Michael Chanb6016b72005-05-26 13:03:09 -0700683
Michael Chan43e80b82008-06-19 16:41:08 -0700684 bnapi = &bp->bnx2_napi[0];
685 bnapi->status_blk.msi = status_blk;
686 bnapi->hw_tx_cons_ptr =
687 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
688 bnapi->hw_rx_cons_ptr =
689 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
David S. Millerf86e82f2008-01-21 17:15:40 -0800690 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
Michael Chanb4b36042007-12-20 19:59:30 -0800691 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan43e80b82008-06-19 16:41:08 -0700692 struct status_block_msix *sblk;
Michael Chanb4b36042007-12-20 19:59:30 -0800693
Michael Chan43e80b82008-06-19 16:41:08 -0700694 bnapi = &bp->bnx2_napi[i];
695
696 sblk = (void *) (status_blk +
697 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
698 bnapi->status_blk.msix = sblk;
699 bnapi->hw_tx_cons_ptr =
700 &sblk->status_tx_quick_consumer_index;
701 bnapi->hw_rx_cons_ptr =
702 &sblk->status_rx_quick_consumer_index;
Michael Chanb4b36042007-12-20 19:59:30 -0800703 bnapi->int_num = i << 24;
704 }
705 }
Michael Chan35efa7c2007-12-20 19:56:37 -0800706
Michael Chan43e80b82008-06-19 16:41:08 -0700707 bp->stats_blk = status_blk + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700708
Michael Chan0f31f992006-03-23 01:12:38 -0800709 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700710
Michael Chan59b47d82006-11-19 14:10:45 -0800711 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
712 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
713 if (bp->ctx_pages == 0)
714 bp->ctx_pages = 1;
715 for (i = 0; i < bp->ctx_pages; i++) {
716 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
717 BCM_PAGE_SIZE,
718 &bp->ctx_blk_mapping[i]);
719 if (bp->ctx_blk[i] == NULL)
720 goto alloc_mem_err;
721 }
722 }
Michael Chan35e90102008-06-19 16:37:42 -0700723
Michael Chanbb4f98a2008-06-19 16:38:19 -0700724 err = bnx2_alloc_rx_mem(bp);
725 if (err)
726 goto alloc_mem_err;
727
Michael Chan35e90102008-06-19 16:37:42 -0700728 err = bnx2_alloc_tx_mem(bp);
729 if (err)
730 goto alloc_mem_err;
731
Michael Chanb6016b72005-05-26 13:03:09 -0700732 return 0;
733
734alloc_mem_err:
735 bnx2_free_mem(bp);
736 return -ENOMEM;
737}
738
739static void
Michael Chane3648b32005-11-04 08:51:21 -0800740bnx2_report_fw_link(struct bnx2 *bp)
741{
742 u32 fw_link_status = 0;
743
Michael Chan583c28e2008-01-21 19:51:35 -0800744 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -0700745 return;
746
Michael Chane3648b32005-11-04 08:51:21 -0800747 if (bp->link_up) {
748 u32 bmsr;
749
750 switch (bp->line_speed) {
751 case SPEED_10:
752 if (bp->duplex == DUPLEX_HALF)
753 fw_link_status = BNX2_LINK_STATUS_10HALF;
754 else
755 fw_link_status = BNX2_LINK_STATUS_10FULL;
756 break;
757 case SPEED_100:
758 if (bp->duplex == DUPLEX_HALF)
759 fw_link_status = BNX2_LINK_STATUS_100HALF;
760 else
761 fw_link_status = BNX2_LINK_STATUS_100FULL;
762 break;
763 case SPEED_1000:
764 if (bp->duplex == DUPLEX_HALF)
765 fw_link_status = BNX2_LINK_STATUS_1000HALF;
766 else
767 fw_link_status = BNX2_LINK_STATUS_1000FULL;
768 break;
769 case SPEED_2500:
770 if (bp->duplex == DUPLEX_HALF)
771 fw_link_status = BNX2_LINK_STATUS_2500HALF;
772 else
773 fw_link_status = BNX2_LINK_STATUS_2500FULL;
774 break;
775 }
776
777 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
778
779 if (bp->autoneg) {
780 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
781
Michael Chanca58c3a2007-05-03 13:22:52 -0700782 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
783 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chane3648b32005-11-04 08:51:21 -0800784
785 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
Michael Chan583c28e2008-01-21 19:51:35 -0800786 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
Michael Chane3648b32005-11-04 08:51:21 -0800787 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
788 else
789 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
790 }
791 }
792 else
793 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
794
Michael Chan2726d6e2008-01-29 21:35:05 -0800795 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
Michael Chane3648b32005-11-04 08:51:21 -0800796}
797
Michael Chan9b1084b2007-07-07 22:50:37 -0700798static char *
799bnx2_xceiver_str(struct bnx2 *bp)
800{
801 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
Michael Chan583c28e2008-01-21 19:51:35 -0800802 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
Michael Chan9b1084b2007-07-07 22:50:37 -0700803 "Copper"));
804}
805
Michael Chane3648b32005-11-04 08:51:21 -0800806static void
Michael Chanb6016b72005-05-26 13:03:09 -0700807bnx2_report_link(struct bnx2 *bp)
808{
809 if (bp->link_up) {
810 netif_carrier_on(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700811 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
812 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700813
814 printk("%d Mbps ", bp->line_speed);
815
816 if (bp->duplex == DUPLEX_FULL)
817 printk("full duplex");
818 else
819 printk("half duplex");
820
821 if (bp->flow_ctrl) {
822 if (bp->flow_ctrl & FLOW_CTRL_RX) {
823 printk(", receive ");
824 if (bp->flow_ctrl & FLOW_CTRL_TX)
825 printk("& transmit ");
826 }
827 else {
828 printk(", transmit ");
829 }
830 printk("flow control ON");
831 }
832 printk("\n");
833 }
834 else {
835 netif_carrier_off(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700836 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
837 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700838 }
Michael Chane3648b32005-11-04 08:51:21 -0800839
840 bnx2_report_fw_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700841}
842
843static void
844bnx2_resolve_flow_ctrl(struct bnx2 *bp)
845{
846 u32 local_adv, remote_adv;
847
848 bp->flow_ctrl = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400849 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
Michael Chanb6016b72005-05-26 13:03:09 -0700850 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
851
852 if (bp->duplex == DUPLEX_FULL) {
853 bp->flow_ctrl = bp->req_flow_ctrl;
854 }
855 return;
856 }
857
858 if (bp->duplex != DUPLEX_FULL) {
859 return;
860 }
861
Michael Chan583c28e2008-01-21 19:51:35 -0800862 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan5b0c76a2005-11-04 08:45:49 -0800863 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
864 u32 val;
865
866 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
867 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
868 bp->flow_ctrl |= FLOW_CTRL_TX;
869 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
870 bp->flow_ctrl |= FLOW_CTRL_RX;
871 return;
872 }
873
Michael Chanca58c3a2007-05-03 13:22:52 -0700874 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
875 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -0700876
Michael Chan583c28e2008-01-21 19:51:35 -0800877 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -0700878 u32 new_local_adv = 0;
879 u32 new_remote_adv = 0;
880
881 if (local_adv & ADVERTISE_1000XPAUSE)
882 new_local_adv |= ADVERTISE_PAUSE_CAP;
883 if (local_adv & ADVERTISE_1000XPSE_ASYM)
884 new_local_adv |= ADVERTISE_PAUSE_ASYM;
885 if (remote_adv & ADVERTISE_1000XPAUSE)
886 new_remote_adv |= ADVERTISE_PAUSE_CAP;
887 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
888 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
889
890 local_adv = new_local_adv;
891 remote_adv = new_remote_adv;
892 }
893
894 /* See Table 28B-3 of 802.3ab-1999 spec. */
895 if (local_adv & ADVERTISE_PAUSE_CAP) {
896 if(local_adv & ADVERTISE_PAUSE_ASYM) {
897 if (remote_adv & ADVERTISE_PAUSE_CAP) {
898 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
899 }
900 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
901 bp->flow_ctrl = FLOW_CTRL_RX;
902 }
903 }
904 else {
905 if (remote_adv & ADVERTISE_PAUSE_CAP) {
906 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
907 }
908 }
909 }
910 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
911 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
912 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
913
914 bp->flow_ctrl = FLOW_CTRL_TX;
915 }
916 }
917}
918
919static int
Michael Chan27a005b2007-05-03 13:23:41 -0700920bnx2_5709s_linkup(struct bnx2 *bp)
921{
922 u32 val, speed;
923
924 bp->link_up = 1;
925
926 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
927 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
928 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
929
930 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
931 bp->line_speed = bp->req_line_speed;
932 bp->duplex = bp->req_duplex;
933 return 0;
934 }
935 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
936 switch (speed) {
937 case MII_BNX2_GP_TOP_AN_SPEED_10:
938 bp->line_speed = SPEED_10;
939 break;
940 case MII_BNX2_GP_TOP_AN_SPEED_100:
941 bp->line_speed = SPEED_100;
942 break;
943 case MII_BNX2_GP_TOP_AN_SPEED_1G:
944 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
945 bp->line_speed = SPEED_1000;
946 break;
947 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
948 bp->line_speed = SPEED_2500;
949 break;
950 }
951 if (val & MII_BNX2_GP_TOP_AN_FD)
952 bp->duplex = DUPLEX_FULL;
953 else
954 bp->duplex = DUPLEX_HALF;
955 return 0;
956}
957
958static int
Michael Chan5b0c76a2005-11-04 08:45:49 -0800959bnx2_5708s_linkup(struct bnx2 *bp)
960{
961 u32 val;
962
963 bp->link_up = 1;
964 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
965 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
966 case BCM5708S_1000X_STAT1_SPEED_10:
967 bp->line_speed = SPEED_10;
968 break;
969 case BCM5708S_1000X_STAT1_SPEED_100:
970 bp->line_speed = SPEED_100;
971 break;
972 case BCM5708S_1000X_STAT1_SPEED_1G:
973 bp->line_speed = SPEED_1000;
974 break;
975 case BCM5708S_1000X_STAT1_SPEED_2G5:
976 bp->line_speed = SPEED_2500;
977 break;
978 }
979 if (val & BCM5708S_1000X_STAT1_FD)
980 bp->duplex = DUPLEX_FULL;
981 else
982 bp->duplex = DUPLEX_HALF;
983
984 return 0;
985}
986
987static int
988bnx2_5706s_linkup(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -0700989{
990 u32 bmcr, local_adv, remote_adv, common;
991
992 bp->link_up = 1;
993 bp->line_speed = SPEED_1000;
994
Michael Chanca58c3a2007-05-03 13:22:52 -0700995 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -0700996 if (bmcr & BMCR_FULLDPLX) {
997 bp->duplex = DUPLEX_FULL;
998 }
999 else {
1000 bp->duplex = DUPLEX_HALF;
1001 }
1002
1003 if (!(bmcr & BMCR_ANENABLE)) {
1004 return 0;
1005 }
1006
Michael Chanca58c3a2007-05-03 13:22:52 -07001007 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1008 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001009
1010 common = local_adv & remote_adv;
1011 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1012
1013 if (common & ADVERTISE_1000XFULL) {
1014 bp->duplex = DUPLEX_FULL;
1015 }
1016 else {
1017 bp->duplex = DUPLEX_HALF;
1018 }
1019 }
1020
1021 return 0;
1022}
1023
1024static int
1025bnx2_copper_linkup(struct bnx2 *bp)
1026{
1027 u32 bmcr;
1028
Michael Chanca58c3a2007-05-03 13:22:52 -07001029 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001030 if (bmcr & BMCR_ANENABLE) {
1031 u32 local_adv, remote_adv, common;
1032
1033 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1034 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1035
1036 common = local_adv & (remote_adv >> 2);
1037 if (common & ADVERTISE_1000FULL) {
1038 bp->line_speed = SPEED_1000;
1039 bp->duplex = DUPLEX_FULL;
1040 }
1041 else if (common & ADVERTISE_1000HALF) {
1042 bp->line_speed = SPEED_1000;
1043 bp->duplex = DUPLEX_HALF;
1044 }
1045 else {
Michael Chanca58c3a2007-05-03 13:22:52 -07001046 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1047 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001048
1049 common = local_adv & remote_adv;
1050 if (common & ADVERTISE_100FULL) {
1051 bp->line_speed = SPEED_100;
1052 bp->duplex = DUPLEX_FULL;
1053 }
1054 else if (common & ADVERTISE_100HALF) {
1055 bp->line_speed = SPEED_100;
1056 bp->duplex = DUPLEX_HALF;
1057 }
1058 else if (common & ADVERTISE_10FULL) {
1059 bp->line_speed = SPEED_10;
1060 bp->duplex = DUPLEX_FULL;
1061 }
1062 else if (common & ADVERTISE_10HALF) {
1063 bp->line_speed = SPEED_10;
1064 bp->duplex = DUPLEX_HALF;
1065 }
1066 else {
1067 bp->line_speed = 0;
1068 bp->link_up = 0;
1069 }
1070 }
1071 }
1072 else {
1073 if (bmcr & BMCR_SPEED100) {
1074 bp->line_speed = SPEED_100;
1075 }
1076 else {
1077 bp->line_speed = SPEED_10;
1078 }
1079 if (bmcr & BMCR_FULLDPLX) {
1080 bp->duplex = DUPLEX_FULL;
1081 }
1082 else {
1083 bp->duplex = DUPLEX_HALF;
1084 }
1085 }
1086
1087 return 0;
1088}
1089
Michael Chan83e3fc82008-01-29 21:37:17 -08001090static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07001091bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
Michael Chan83e3fc82008-01-29 21:37:17 -08001092{
Michael Chanbb4f98a2008-06-19 16:38:19 -07001093 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08001094
1095 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1096 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1097 val |= 0x02 << 8;
1098
1099 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1100 u32 lo_water, hi_water;
1101
1102 if (bp->flow_ctrl & FLOW_CTRL_TX)
1103 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1104 else
1105 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1106 if (lo_water >= bp->rx_ring_size)
1107 lo_water = 0;
1108
1109 hi_water = bp->rx_ring_size / 4;
1110
1111 if (hi_water <= lo_water)
1112 lo_water = 0;
1113
1114 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1115 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1116
1117 if (hi_water > 0xf)
1118 hi_water = 0xf;
1119 else if (hi_water == 0)
1120 lo_water = 0;
1121 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1122 }
1123 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1124}
1125
Michael Chanbb4f98a2008-06-19 16:38:19 -07001126static void
1127bnx2_init_all_rx_contexts(struct bnx2 *bp)
1128{
1129 int i;
1130 u32 cid;
1131
1132 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1133 if (i == 1)
1134 cid = RX_RSS_CID;
1135 bnx2_init_rx_context(bp, cid);
1136 }
1137}
1138
Benjamin Li344478d2008-09-18 16:38:24 -07001139static void
Michael Chanb6016b72005-05-26 13:03:09 -07001140bnx2_set_mac_link(struct bnx2 *bp)
1141{
1142 u32 val;
1143
1144 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1145 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1146 (bp->duplex == DUPLEX_HALF)) {
1147 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1148 }
1149
1150 /* Configure the EMAC mode register. */
1151 val = REG_RD(bp, BNX2_EMAC_MODE);
1152
1153 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
Michael Chan5b0c76a2005-11-04 08:45:49 -08001154 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08001155 BNX2_EMAC_MODE_25G_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001156
1157 if (bp->link_up) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001158 switch (bp->line_speed) {
1159 case SPEED_10:
Michael Chan59b47d82006-11-19 14:10:45 -08001160 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1161 val |= BNX2_EMAC_MODE_PORT_MII_10M;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001162 break;
1163 }
1164 /* fall through */
1165 case SPEED_100:
1166 val |= BNX2_EMAC_MODE_PORT_MII;
1167 break;
1168 case SPEED_2500:
Michael Chan59b47d82006-11-19 14:10:45 -08001169 val |= BNX2_EMAC_MODE_25G_MODE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001170 /* fall through */
1171 case SPEED_1000:
1172 val |= BNX2_EMAC_MODE_PORT_GMII;
1173 break;
1174 }
Michael Chanb6016b72005-05-26 13:03:09 -07001175 }
1176 else {
1177 val |= BNX2_EMAC_MODE_PORT_GMII;
1178 }
1179
1180 /* Set the MAC to operate in the appropriate duplex mode. */
1181 if (bp->duplex == DUPLEX_HALF)
1182 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1183 REG_WR(bp, BNX2_EMAC_MODE, val);
1184
1185 /* Enable/disable rx PAUSE. */
1186 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1187
1188 if (bp->flow_ctrl & FLOW_CTRL_RX)
1189 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1190 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1191
1192 /* Enable/disable tx PAUSE. */
1193 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1194 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1195
1196 if (bp->flow_ctrl & FLOW_CTRL_TX)
1197 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1198 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1199
1200 /* Acknowledge the interrupt. */
1201 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1202
Michael Chan83e3fc82008-01-29 21:37:17 -08001203 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chanbb4f98a2008-06-19 16:38:19 -07001204 bnx2_init_all_rx_contexts(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001205}
1206
Michael Chan27a005b2007-05-03 13:23:41 -07001207static void
1208bnx2_enable_bmsr1(struct bnx2 *bp)
1209{
Michael Chan583c28e2008-01-21 19:51:35 -08001210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_GP_STATUS);
1214}
1215
1216static void
1217bnx2_disable_bmsr1(struct bnx2 *bp)
1218{
Michael Chan583c28e2008-01-21 19:51:35 -08001219 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001220 (CHIP_NUM(bp) == CHIP_NUM_5709))
1221 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1222 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1223}
1224
Michael Chanb6016b72005-05-26 13:03:09 -07001225static int
Michael Chan605a9e22007-05-03 13:23:13 -07001226bnx2_test_and_enable_2g5(struct bnx2 *bp)
1227{
1228 u32 up1;
1229 int ret = 1;
1230
Michael Chan583c28e2008-01-21 19:51:35 -08001231 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001232 return 0;
1233
1234 if (bp->autoneg & AUTONEG_SPEED)
1235 bp->advertising |= ADVERTISED_2500baseX_Full;
1236
Michael Chan27a005b2007-05-03 13:23:41 -07001237 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1238 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1239
Michael Chan605a9e22007-05-03 13:23:13 -07001240 bnx2_read_phy(bp, bp->mii_up1, &up1);
1241 if (!(up1 & BCM5708S_UP1_2G5)) {
1242 up1 |= BCM5708S_UP1_2G5;
1243 bnx2_write_phy(bp, bp->mii_up1, up1);
1244 ret = 0;
1245 }
1246
Michael Chan27a005b2007-05-03 13:23:41 -07001247 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1248 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1249 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1250
Michael Chan605a9e22007-05-03 13:23:13 -07001251 return ret;
1252}
1253
1254static int
1255bnx2_test_and_disable_2g5(struct bnx2 *bp)
1256{
1257 u32 up1;
1258 int ret = 0;
1259
Michael Chan583c28e2008-01-21 19:51:35 -08001260 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001261 return 0;
1262
Michael Chan27a005b2007-05-03 13:23:41 -07001263 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1264 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1265
Michael Chan605a9e22007-05-03 13:23:13 -07001266 bnx2_read_phy(bp, bp->mii_up1, &up1);
1267 if (up1 & BCM5708S_UP1_2G5) {
1268 up1 &= ~BCM5708S_UP1_2G5;
1269 bnx2_write_phy(bp, bp->mii_up1, up1);
1270 ret = 1;
1271 }
1272
Michael Chan27a005b2007-05-03 13:23:41 -07001273 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1274 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1275 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1276
Michael Chan605a9e22007-05-03 13:23:13 -07001277 return ret;
1278}
1279
1280static void
1281bnx2_enable_forced_2g5(struct bnx2 *bp)
1282{
1283 u32 bmcr;
1284
Michael Chan583c28e2008-01-21 19:51:35 -08001285 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001286 return;
1287
Michael Chan27a005b2007-05-03 13:23:41 -07001288 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1289 u32 val;
1290
1291 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1292 MII_BNX2_BLK_ADDR_SERDES_DIG);
1293 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1294 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1295 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1296 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1297
1298 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1299 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1300 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1301
1302 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001303 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1304 bmcr |= BCM5708S_BMCR_FORCE_2500;
1305 }
1306
1307 if (bp->autoneg & AUTONEG_SPEED) {
1308 bmcr &= ~BMCR_ANENABLE;
1309 if (bp->req_duplex == DUPLEX_FULL)
1310 bmcr |= BMCR_FULLDPLX;
1311 }
1312 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1313}
1314
1315static void
1316bnx2_disable_forced_2g5(struct bnx2 *bp)
1317{
1318 u32 bmcr;
1319
Michael Chan583c28e2008-01-21 19:51:35 -08001320 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001321 return;
1322
Michael Chan27a005b2007-05-03 13:23:41 -07001323 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1324 u32 val;
1325
1326 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1327 MII_BNX2_BLK_ADDR_SERDES_DIG);
1328 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1329 val &= ~MII_BNX2_SD_MISC1_FORCE;
1330 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1331
1332 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1333 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1334 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1335
1336 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001337 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1338 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1339 }
1340
1341 if (bp->autoneg & AUTONEG_SPEED)
1342 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1343 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1344}
1345
Michael Chanb2fadea2008-01-21 17:07:06 -08001346static void
1347bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1348{
1349 u32 val;
1350
1351 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1352 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1353 if (start)
1354 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1355 else
1356 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1357}
1358
Michael Chan605a9e22007-05-03 13:23:13 -07001359static int
Michael Chanb6016b72005-05-26 13:03:09 -07001360bnx2_set_link(struct bnx2 *bp)
1361{
1362 u32 bmsr;
1363 u8 link_up;
1364
Michael Chan80be4432006-11-19 14:07:28 -08001365 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
Michael Chanb6016b72005-05-26 13:03:09 -07001366 bp->link_up = 1;
1367 return 0;
1368 }
1369
Michael Chan583c28e2008-01-21 19:51:35 -08001370 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001371 return 0;
1372
Michael Chanb6016b72005-05-26 13:03:09 -07001373 link_up = bp->link_up;
1374
Michael Chan27a005b2007-05-03 13:23:41 -07001375 bnx2_enable_bmsr1(bp);
1376 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1377 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1378 bnx2_disable_bmsr1(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001379
Michael Chan583c28e2008-01-21 19:51:35 -08001380 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chanb6016b72005-05-26 13:03:09 -07001381 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
Michael Chana2724e22008-02-23 19:47:44 -08001382 u32 val, an_dbg;
Michael Chanb6016b72005-05-26 13:03:09 -07001383
Michael Chan583c28e2008-01-21 19:51:35 -08001384 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001385 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08001386 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08001387 }
Michael Chanb6016b72005-05-26 13:03:09 -07001388 val = REG_RD(bp, BNX2_EMAC_STATUS);
Michael Chana2724e22008-02-23 19:47:44 -08001389
1390 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1391 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1392 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1393
1394 if ((val & BNX2_EMAC_STATUS_LINK) &&
1395 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
Michael Chanb6016b72005-05-26 13:03:09 -07001396 bmsr |= BMSR_LSTATUS;
1397 else
1398 bmsr &= ~BMSR_LSTATUS;
1399 }
1400
1401 if (bmsr & BMSR_LSTATUS) {
1402 bp->link_up = 1;
1403
Michael Chan583c28e2008-01-21 19:51:35 -08001404 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001405 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1406 bnx2_5706s_linkup(bp);
1407 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1408 bnx2_5708s_linkup(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07001409 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1410 bnx2_5709s_linkup(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001411 }
1412 else {
1413 bnx2_copper_linkup(bp);
1414 }
1415 bnx2_resolve_flow_ctrl(bp);
1416 }
1417 else {
Michael Chan583c28e2008-01-21 19:51:35 -08001418 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan605a9e22007-05-03 13:23:13 -07001419 (bp->autoneg & AUTONEG_SPEED))
1420 bnx2_disable_forced_2g5(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001421
Michael Chan583c28e2008-01-21 19:51:35 -08001422 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001423 u32 bmcr;
1424
1425 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1426 bmcr |= BMCR_ANENABLE;
1427 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1428
Michael Chan583c28e2008-01-21 19:51:35 -08001429 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb2fadea2008-01-21 17:07:06 -08001430 }
Michael Chanb6016b72005-05-26 13:03:09 -07001431 bp->link_up = 0;
1432 }
1433
1434 if (bp->link_up != link_up) {
1435 bnx2_report_link(bp);
1436 }
1437
1438 bnx2_set_mac_link(bp);
1439
1440 return 0;
1441}
1442
1443static int
1444bnx2_reset_phy(struct bnx2 *bp)
1445{
1446 int i;
1447 u32 reg;
1448
Michael Chanca58c3a2007-05-03 13:22:52 -07001449 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07001450
1451#define PHY_RESET_MAX_WAIT 100
1452 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1453 udelay(10);
1454
Michael Chanca58c3a2007-05-03 13:22:52 -07001455 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001456 if (!(reg & BMCR_RESET)) {
1457 udelay(20);
1458 break;
1459 }
1460 }
1461 if (i == PHY_RESET_MAX_WAIT) {
1462 return -EBUSY;
1463 }
1464 return 0;
1465}
1466
1467static u32
1468bnx2_phy_get_pause_adv(struct bnx2 *bp)
1469{
1470 u32 adv = 0;
1471
1472 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1473 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1474
Michael Chan583c28e2008-01-21 19:51:35 -08001475 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001476 adv = ADVERTISE_1000XPAUSE;
1477 }
1478 else {
1479 adv = ADVERTISE_PAUSE_CAP;
1480 }
1481 }
1482 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001483 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001484 adv = ADVERTISE_1000XPSE_ASYM;
1485 }
1486 else {
1487 adv = ADVERTISE_PAUSE_ASYM;
1488 }
1489 }
1490 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001491 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001492 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1493 }
1494 else {
1495 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496 }
1497 }
1498 return adv;
1499}
1500
Michael Chana2f13892008-07-14 22:38:23 -07001501static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
Michael Chan0d8a6572007-07-07 22:49:43 -07001502
Michael Chanb6016b72005-05-26 13:03:09 -07001503static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001504bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001505__releases(&bp->phy_lock)
1506__acquires(&bp->phy_lock)
Michael Chan0d8a6572007-07-07 22:49:43 -07001507{
1508 u32 speed_arg = 0, pause_adv;
1509
1510 pause_adv = bnx2_phy_get_pause_adv(bp);
1511
1512 if (bp->autoneg & AUTONEG_SPEED) {
1513 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1514 if (bp->advertising & ADVERTISED_10baseT_Half)
1515 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1516 if (bp->advertising & ADVERTISED_10baseT_Full)
1517 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1518 if (bp->advertising & ADVERTISED_100baseT_Half)
1519 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1520 if (bp->advertising & ADVERTISED_100baseT_Full)
1521 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1522 if (bp->advertising & ADVERTISED_1000baseT_Full)
1523 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1524 if (bp->advertising & ADVERTISED_2500baseX_Full)
1525 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1526 } else {
1527 if (bp->req_line_speed == SPEED_2500)
1528 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1529 else if (bp->req_line_speed == SPEED_1000)
1530 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1531 else if (bp->req_line_speed == SPEED_100) {
1532 if (bp->req_duplex == DUPLEX_FULL)
1533 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1534 else
1535 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1536 } else if (bp->req_line_speed == SPEED_10) {
1537 if (bp->req_duplex == DUPLEX_FULL)
1538 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1539 else
1540 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1541 }
1542 }
1543
1544 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1545 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
Michael Chanc26736e2008-01-31 17:07:21 -08001546 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
Michael Chan0d8a6572007-07-07 22:49:43 -07001547 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1548
1549 if (port == PORT_TP)
1550 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1551 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1552
Michael Chan2726d6e2008-01-29 21:35:05 -08001553 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
Michael Chan0d8a6572007-07-07 22:49:43 -07001554
1555 spin_unlock_bh(&bp->phy_lock);
Michael Chana2f13892008-07-14 22:38:23 -07001556 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
Michael Chan0d8a6572007-07-07 22:49:43 -07001557 spin_lock_bh(&bp->phy_lock);
1558
1559 return 0;
1560}
1561
1562static int
1563bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001564__releases(&bp->phy_lock)
1565__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07001566{
Michael Chan605a9e22007-05-03 13:23:13 -07001567 u32 adv, bmcr;
Michael Chanb6016b72005-05-26 13:03:09 -07001568 u32 new_adv = 0;
1569
Michael Chan583c28e2008-01-21 19:51:35 -08001570 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001571 return (bnx2_setup_remote_phy(bp, port));
1572
Michael Chanb6016b72005-05-26 13:03:09 -07001573 if (!(bp->autoneg & AUTONEG_SPEED)) {
1574 u32 new_bmcr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001575 int force_link_down = 0;
1576
Michael Chan605a9e22007-05-03 13:23:13 -07001577 if (bp->req_line_speed == SPEED_2500) {
1578 if (!bnx2_test_and_enable_2g5(bp))
1579 force_link_down = 1;
1580 } else if (bp->req_line_speed == SPEED_1000) {
1581 if (bnx2_test_and_disable_2g5(bp))
1582 force_link_down = 1;
1583 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001584 bnx2_read_phy(bp, bp->mii_adv, &adv);
Michael Chan80be4432006-11-19 14:07:28 -08001585 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1586
Michael Chanca58c3a2007-05-03 13:22:52 -07001587 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001588 new_bmcr = bmcr & ~BMCR_ANENABLE;
Michael Chan80be4432006-11-19 14:07:28 -08001589 new_bmcr |= BMCR_SPEED1000;
Michael Chan605a9e22007-05-03 13:23:13 -07001590
Michael Chan27a005b2007-05-03 13:23:41 -07001591 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1592 if (bp->req_line_speed == SPEED_2500)
1593 bnx2_enable_forced_2g5(bp);
1594 else if (bp->req_line_speed == SPEED_1000) {
1595 bnx2_disable_forced_2g5(bp);
1596 new_bmcr &= ~0x2000;
1597 }
1598
1599 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001600 if (bp->req_line_speed == SPEED_2500)
1601 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1602 else
1603 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001604 }
1605
Michael Chanb6016b72005-05-26 13:03:09 -07001606 if (bp->req_duplex == DUPLEX_FULL) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001607 adv |= ADVERTISE_1000XFULL;
Michael Chanb6016b72005-05-26 13:03:09 -07001608 new_bmcr |= BMCR_FULLDPLX;
1609 }
1610 else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001611 adv |= ADVERTISE_1000XHALF;
Michael Chanb6016b72005-05-26 13:03:09 -07001612 new_bmcr &= ~BMCR_FULLDPLX;
1613 }
Michael Chan5b0c76a2005-11-04 08:45:49 -08001614 if ((new_bmcr != bmcr) || (force_link_down)) {
Michael Chanb6016b72005-05-26 13:03:09 -07001615 /* Force a link down visible on the other side */
1616 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001617 bnx2_write_phy(bp, bp->mii_adv, adv &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001618 ~(ADVERTISE_1000XFULL |
1619 ADVERTISE_1000XHALF));
Michael Chanca58c3a2007-05-03 13:22:52 -07001620 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
Michael Chanb6016b72005-05-26 13:03:09 -07001621 BMCR_ANRESTART | BMCR_ANENABLE);
1622
1623 bp->link_up = 0;
1624 netif_carrier_off(bp->dev);
Michael Chanca58c3a2007-05-03 13:22:52 -07001625 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan80be4432006-11-19 14:07:28 -08001626 bnx2_report_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001627 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001628 bnx2_write_phy(bp, bp->mii_adv, adv);
1629 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001630 } else {
1631 bnx2_resolve_flow_ctrl(bp);
1632 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001633 }
1634 return 0;
1635 }
1636
Michael Chan605a9e22007-05-03 13:23:13 -07001637 bnx2_test_and_enable_2g5(bp);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001638
Michael Chanb6016b72005-05-26 13:03:09 -07001639 if (bp->advertising & ADVERTISED_1000baseT_Full)
1640 new_adv |= ADVERTISE_1000XFULL;
1641
1642 new_adv |= bnx2_phy_get_pause_adv(bp);
1643
Michael Chanca58c3a2007-05-03 13:22:52 -07001644 bnx2_read_phy(bp, bp->mii_adv, &adv);
1645 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001646
1647 bp->serdes_an_pending = 0;
1648 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1649 /* Force a link down visible on the other side */
1650 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001651 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chan80be4432006-11-19 14:07:28 -08001652 spin_unlock_bh(&bp->phy_lock);
1653 msleep(20);
1654 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07001655 }
1656
Michael Chanca58c3a2007-05-03 13:22:52 -07001657 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1658 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001659 BMCR_ANENABLE);
Michael Chanf8dd0642006-11-19 14:08:29 -08001660 /* Speed up link-up time when the link partner
1661 * does not autonegotiate which is very common
1662 * in blade servers. Some blade servers use
1663 * IPMI for kerboard input and it's important
1664 * to minimize link disruptions. Autoneg. involves
1665 * exchanging base pages plus 3 next pages and
1666 * normally completes in about 120 msec.
1667 */
Michael Chan40105c02008-11-12 16:02:45 -08001668 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08001669 bp->serdes_an_pending = 1;
1670 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chan605a9e22007-05-03 13:23:13 -07001671 } else {
1672 bnx2_resolve_flow_ctrl(bp);
1673 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001674 }
1675
1676 return 0;
1677}
1678
1679#define ETHTOOL_ALL_FIBRE_SPEED \
Michael Chan583c28e2008-01-21 19:51:35 -08001680 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
Michael Chandeaf3912007-07-07 22:48:00 -07001681 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1682 (ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07001683
1684#define ETHTOOL_ALL_COPPER_SPEED \
1685 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1686 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1687 ADVERTISED_1000baseT_Full)
1688
1689#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1690 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001691
Michael Chanb6016b72005-05-26 13:03:09 -07001692#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1693
Michael Chandeaf3912007-07-07 22:48:00 -07001694static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001695bnx2_set_default_remote_link(struct bnx2 *bp)
1696{
1697 u32 link;
1698
1699 if (bp->phy_port == PORT_TP)
Michael Chan2726d6e2008-01-29 21:35:05 -08001700 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001701 else
Michael Chan2726d6e2008-01-29 21:35:05 -08001702 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001703
1704 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1705 bp->req_line_speed = 0;
1706 bp->autoneg |= AUTONEG_SPEED;
1707 bp->advertising = ADVERTISED_Autoneg;
1708 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1709 bp->advertising |= ADVERTISED_10baseT_Half;
1710 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1711 bp->advertising |= ADVERTISED_10baseT_Full;
1712 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1713 bp->advertising |= ADVERTISED_100baseT_Half;
1714 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1715 bp->advertising |= ADVERTISED_100baseT_Full;
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1717 bp->advertising |= ADVERTISED_1000baseT_Full;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1719 bp->advertising |= ADVERTISED_2500baseX_Full;
1720 } else {
1721 bp->autoneg = 0;
1722 bp->advertising = 0;
1723 bp->req_duplex = DUPLEX_FULL;
1724 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1725 bp->req_line_speed = SPEED_10;
1726 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1727 bp->req_duplex = DUPLEX_HALF;
1728 }
1729 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1730 bp->req_line_speed = SPEED_100;
1731 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1732 bp->req_duplex = DUPLEX_HALF;
1733 }
1734 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1735 bp->req_line_speed = SPEED_1000;
1736 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1737 bp->req_line_speed = SPEED_2500;
1738 }
1739}
1740
1741static void
Michael Chandeaf3912007-07-07 22:48:00 -07001742bnx2_set_default_link(struct bnx2 *bp)
1743{
Harvey Harrisonab598592008-05-01 02:47:38 -07001744 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1745 bnx2_set_default_remote_link(bp);
1746 return;
1747 }
Michael Chan0d8a6572007-07-07 22:49:43 -07001748
Michael Chandeaf3912007-07-07 22:48:00 -07001749 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1750 bp->req_line_speed = 0;
Michael Chan583c28e2008-01-21 19:51:35 -08001751 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chandeaf3912007-07-07 22:48:00 -07001752 u32 reg;
1753
1754 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1755
Michael Chan2726d6e2008-01-29 21:35:05 -08001756 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
Michael Chandeaf3912007-07-07 22:48:00 -07001757 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1758 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1759 bp->autoneg = 0;
1760 bp->req_line_speed = bp->line_speed = SPEED_1000;
1761 bp->req_duplex = DUPLEX_FULL;
1762 }
1763 } else
1764 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1765}
1766
Michael Chan0d8a6572007-07-07 22:49:43 -07001767static void
Michael Chandf149d72007-07-07 22:51:36 -07001768bnx2_send_heart_beat(struct bnx2 *bp)
1769{
1770 u32 msg;
1771 u32 addr;
1772
1773 spin_lock(&bp->indirect_lock);
1774 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1775 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1776 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1777 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1778 spin_unlock(&bp->indirect_lock);
1779}
1780
1781static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001782bnx2_remote_phy_event(struct bnx2 *bp)
1783{
1784 u32 msg;
1785 u8 link_up = bp->link_up;
1786 u8 old_port;
1787
Michael Chan2726d6e2008-01-29 21:35:05 -08001788 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07001789
Michael Chandf149d72007-07-07 22:51:36 -07001790 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1791 bnx2_send_heart_beat(bp);
1792
1793 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1794
Michael Chan0d8a6572007-07-07 22:49:43 -07001795 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1796 bp->link_up = 0;
1797 else {
1798 u32 speed;
1799
1800 bp->link_up = 1;
1801 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1802 bp->duplex = DUPLEX_FULL;
1803 switch (speed) {
1804 case BNX2_LINK_STATUS_10HALF:
1805 bp->duplex = DUPLEX_HALF;
1806 case BNX2_LINK_STATUS_10FULL:
1807 bp->line_speed = SPEED_10;
1808 break;
1809 case BNX2_LINK_STATUS_100HALF:
1810 bp->duplex = DUPLEX_HALF;
1811 case BNX2_LINK_STATUS_100BASE_T4:
1812 case BNX2_LINK_STATUS_100FULL:
1813 bp->line_speed = SPEED_100;
1814 break;
1815 case BNX2_LINK_STATUS_1000HALF:
1816 bp->duplex = DUPLEX_HALF;
1817 case BNX2_LINK_STATUS_1000FULL:
1818 bp->line_speed = SPEED_1000;
1819 break;
1820 case BNX2_LINK_STATUS_2500HALF:
1821 bp->duplex = DUPLEX_HALF;
1822 case BNX2_LINK_STATUS_2500FULL:
1823 bp->line_speed = SPEED_2500;
1824 break;
1825 default:
1826 bp->line_speed = 0;
1827 break;
1828 }
1829
Michael Chan0d8a6572007-07-07 22:49:43 -07001830 bp->flow_ctrl = 0;
1831 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1832 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1833 if (bp->duplex == DUPLEX_FULL)
1834 bp->flow_ctrl = bp->req_flow_ctrl;
1835 } else {
1836 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1837 bp->flow_ctrl |= FLOW_CTRL_TX;
1838 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1839 bp->flow_ctrl |= FLOW_CTRL_RX;
1840 }
1841
1842 old_port = bp->phy_port;
1843 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1844 bp->phy_port = PORT_FIBRE;
1845 else
1846 bp->phy_port = PORT_TP;
1847
1848 if (old_port != bp->phy_port)
1849 bnx2_set_default_link(bp);
1850
Michael Chan0d8a6572007-07-07 22:49:43 -07001851 }
1852 if (bp->link_up != link_up)
1853 bnx2_report_link(bp);
1854
1855 bnx2_set_mac_link(bp);
1856}
1857
1858static int
1859bnx2_set_remote_link(struct bnx2 *bp)
1860{
1861 u32 evt_code;
1862
Michael Chan2726d6e2008-01-29 21:35:05 -08001863 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07001864 switch (evt_code) {
1865 case BNX2_FW_EVT_CODE_LINK_EVENT:
1866 bnx2_remote_phy_event(bp);
1867 break;
1868 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1869 default:
Michael Chandf149d72007-07-07 22:51:36 -07001870 bnx2_send_heart_beat(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07001871 break;
1872 }
1873 return 0;
1874}
1875
Michael Chanb6016b72005-05-26 13:03:09 -07001876static int
1877bnx2_setup_copper_phy(struct bnx2 *bp)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001878__releases(&bp->phy_lock)
1879__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07001880{
1881 u32 bmcr;
1882 u32 new_bmcr;
1883
Michael Chanca58c3a2007-05-03 13:22:52 -07001884 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001885
1886 if (bp->autoneg & AUTONEG_SPEED) {
1887 u32 adv_reg, adv1000_reg;
1888 u32 new_adv_reg = 0;
1889 u32 new_adv1000_reg = 0;
1890
Michael Chanca58c3a2007-05-03 13:22:52 -07001891 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001892 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1893 ADVERTISE_PAUSE_ASYM);
1894
1895 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1896 adv1000_reg &= PHY_ALL_1000_SPEED;
1897
1898 if (bp->advertising & ADVERTISED_10baseT_Half)
1899 new_adv_reg |= ADVERTISE_10HALF;
1900 if (bp->advertising & ADVERTISED_10baseT_Full)
1901 new_adv_reg |= ADVERTISE_10FULL;
1902 if (bp->advertising & ADVERTISED_100baseT_Half)
1903 new_adv_reg |= ADVERTISE_100HALF;
1904 if (bp->advertising & ADVERTISED_100baseT_Full)
1905 new_adv_reg |= ADVERTISE_100FULL;
1906 if (bp->advertising & ADVERTISED_1000baseT_Full)
1907 new_adv1000_reg |= ADVERTISE_1000FULL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001908
Michael Chanb6016b72005-05-26 13:03:09 -07001909 new_adv_reg |= ADVERTISE_CSMA;
1910
1911 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1912
1913 if ((adv1000_reg != new_adv1000_reg) ||
1914 (adv_reg != new_adv_reg) ||
1915 ((bmcr & BMCR_ANENABLE) == 0)) {
1916
Michael Chanca58c3a2007-05-03 13:22:52 -07001917 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001918 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
Michael Chanca58c3a2007-05-03 13:22:52 -07001919 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001920 BMCR_ANENABLE);
1921 }
1922 else if (bp->link_up) {
1923 /* Flow ctrl may have changed from auto to forced */
1924 /* or vice-versa. */
1925
1926 bnx2_resolve_flow_ctrl(bp);
1927 bnx2_set_mac_link(bp);
1928 }
1929 return 0;
1930 }
1931
1932 new_bmcr = 0;
1933 if (bp->req_line_speed == SPEED_100) {
1934 new_bmcr |= BMCR_SPEED100;
1935 }
1936 if (bp->req_duplex == DUPLEX_FULL) {
1937 new_bmcr |= BMCR_FULLDPLX;
1938 }
1939 if (new_bmcr != bmcr) {
1940 u32 bmsr;
Michael Chanb6016b72005-05-26 13:03:09 -07001941
Michael Chanca58c3a2007-05-03 13:22:52 -07001942 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1943 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001944
Michael Chanb6016b72005-05-26 13:03:09 -07001945 if (bmsr & BMSR_LSTATUS) {
1946 /* Force link down */
Michael Chanca58c3a2007-05-03 13:22:52 -07001947 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chana16dda02006-11-19 14:08:56 -08001948 spin_unlock_bh(&bp->phy_lock);
1949 msleep(50);
1950 spin_lock_bh(&bp->phy_lock);
1951
Michael Chanca58c3a2007-05-03 13:22:52 -07001952 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1953 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chanb6016b72005-05-26 13:03:09 -07001954 }
1955
Michael Chanca58c3a2007-05-03 13:22:52 -07001956 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001957
1958 /* Normally, the new speed is setup after the link has
1959 * gone down and up again. In some cases, link will not go
1960 * down so we need to set up the new speed here.
1961 */
1962 if (bmsr & BMSR_LSTATUS) {
1963 bp->line_speed = bp->req_line_speed;
1964 bp->duplex = bp->req_duplex;
1965 bnx2_resolve_flow_ctrl(bp);
1966 bnx2_set_mac_link(bp);
1967 }
Michael Chan27a005b2007-05-03 13:23:41 -07001968 } else {
1969 bnx2_resolve_flow_ctrl(bp);
1970 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001971 }
1972 return 0;
1973}
1974
1975static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001976bnx2_setup_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001977__releases(&bp->phy_lock)
1978__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07001979{
1980 if (bp->loopback == MAC_LOOPBACK)
1981 return 0;
1982
Michael Chan583c28e2008-01-21 19:51:35 -08001983 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07001984 return (bnx2_setup_serdes_phy(bp, port));
Michael Chanb6016b72005-05-26 13:03:09 -07001985 }
1986 else {
1987 return (bnx2_setup_copper_phy(bp));
1988 }
1989}
1990
1991static int
Michael Chan9a120bc2008-05-16 22:17:45 -07001992bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan27a005b2007-05-03 13:23:41 -07001993{
1994 u32 val;
1995
1996 bp->mii_bmcr = MII_BMCR + 0x10;
1997 bp->mii_bmsr = MII_BMSR + 0x10;
1998 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1999 bp->mii_adv = MII_ADVERTISE + 0x10;
2000 bp->mii_lpa = MII_LPA + 0x10;
2001 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2002
2003 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2004 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2005
2006 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chan9a120bc2008-05-16 22:17:45 -07002007 if (reset_phy)
2008 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002009
2010 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2011
2012 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2013 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2014 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2015 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2016
2017 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2018 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
Michael Chan583c28e2008-01-21 19:51:35 -08002019 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan27a005b2007-05-03 13:23:41 -07002020 val |= BCM5708S_UP1_2G5;
2021 else
2022 val &= ~BCM5708S_UP1_2G5;
2023 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2024
2025 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2026 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2027 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2028 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2029
2030 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2031
2032 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2033 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2034 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2035
2036 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2037
2038 return 0;
2039}
2040
2041static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002042bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan5b0c76a2005-11-04 08:45:49 -08002043{
2044 u32 val;
2045
Michael Chan9a120bc2008-05-16 22:17:45 -07002046 if (reset_phy)
2047 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002048
2049 bp->mii_up1 = BCM5708S_UP1;
2050
Michael Chan5b0c76a2005-11-04 08:45:49 -08002051 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2052 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2053 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2054
2055 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2056 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2057 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2058
2059 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2060 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2061 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2062
Michael Chan583c28e2008-01-21 19:51:35 -08002063 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002064 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2065 val |= BCM5708S_UP1_2G5;
2066 bnx2_write_phy(bp, BCM5708S_UP1, val);
2067 }
2068
2069 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
Michael Chandda1e392006-01-23 16:08:14 -08002070 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2071 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002072 /* increase tx signal amplitude */
2073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2074 BCM5708S_BLK_ADDR_TX_MISC);
2075 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2076 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2077 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2078 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2079 }
2080
Michael Chan2726d6e2008-01-29 21:35:05 -08002081 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
Michael Chan5b0c76a2005-11-04 08:45:49 -08002082 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2083
2084 if (val) {
2085 u32 is_backplane;
2086
Michael Chan2726d6e2008-01-29 21:35:05 -08002087 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002088 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2089 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2090 BCM5708S_BLK_ADDR_TX_MISC);
2091 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2092 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2093 BCM5708S_BLK_ADDR_DIG);
2094 }
2095 }
2096 return 0;
2097}
2098
2099static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002100bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002101{
Michael Chan9a120bc2008-05-16 22:17:45 -07002102 if (reset_phy)
2103 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002104
Michael Chan583c28e2008-01-21 19:51:35 -08002105 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb6016b72005-05-26 13:03:09 -07002106
Michael Chan59b47d82006-11-19 14:10:45 -08002107 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2108 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
Michael Chanb6016b72005-05-26 13:03:09 -07002109
2110 if (bp->dev->mtu > 1500) {
2111 u32 val;
2112
2113 /* Set extended packet length bit */
2114 bnx2_write_phy(bp, 0x18, 0x7);
2115 bnx2_read_phy(bp, 0x18, &val);
2116 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2117
2118 bnx2_write_phy(bp, 0x1c, 0x6c00);
2119 bnx2_read_phy(bp, 0x1c, &val);
2120 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2121 }
2122 else {
2123 u32 val;
2124
2125 bnx2_write_phy(bp, 0x18, 0x7);
2126 bnx2_read_phy(bp, 0x18, &val);
2127 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2128
2129 bnx2_write_phy(bp, 0x1c, 0x6c00);
2130 bnx2_read_phy(bp, 0x1c, &val);
2131 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2132 }
2133
2134 return 0;
2135}
2136
2137static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002138bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002139{
Michael Chan5b0c76a2005-11-04 08:45:49 -08002140 u32 val;
2141
Michael Chan9a120bc2008-05-16 22:17:45 -07002142 if (reset_phy)
2143 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002144
Michael Chan583c28e2008-01-21 19:51:35 -08002145 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07002146 bnx2_write_phy(bp, 0x18, 0x0c00);
2147 bnx2_write_phy(bp, 0x17, 0x000a);
2148 bnx2_write_phy(bp, 0x15, 0x310b);
2149 bnx2_write_phy(bp, 0x17, 0x201f);
2150 bnx2_write_phy(bp, 0x15, 0x9506);
2151 bnx2_write_phy(bp, 0x17, 0x401f);
2152 bnx2_write_phy(bp, 0x15, 0x14e2);
2153 bnx2_write_phy(bp, 0x18, 0x0400);
2154 }
2155
Michael Chan583c28e2008-01-21 19:51:35 -08002156 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
Michael Chanb659f442007-02-02 00:46:35 -08002157 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2158 MII_BNX2_DSP_EXPAND_REG | 0x8);
2159 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2160 val &= ~(1 << 8);
2161 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2162 }
2163
Michael Chanb6016b72005-05-26 13:03:09 -07002164 if (bp->dev->mtu > 1500) {
Michael Chanb6016b72005-05-26 13:03:09 -07002165 /* Set extended packet length bit */
2166 bnx2_write_phy(bp, 0x18, 0x7);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | 0x4000);
2169
2170 bnx2_read_phy(bp, 0x10, &val);
2171 bnx2_write_phy(bp, 0x10, val | 0x1);
2172 }
2173 else {
Michael Chanb6016b72005-05-26 13:03:09 -07002174 bnx2_write_phy(bp, 0x18, 0x7);
2175 bnx2_read_phy(bp, 0x18, &val);
2176 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2177
2178 bnx2_read_phy(bp, 0x10, &val);
2179 bnx2_write_phy(bp, 0x10, val & ~0x1);
2180 }
2181
Michael Chan5b0c76a2005-11-04 08:45:49 -08002182 /* ethernet@wirespeed */
2183 bnx2_write_phy(bp, 0x18, 0x7007);
2184 bnx2_read_phy(bp, 0x18, &val);
2185 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
Michael Chanb6016b72005-05-26 13:03:09 -07002186 return 0;
2187}
2188
2189
2190static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002191bnx2_init_phy(struct bnx2 *bp, int reset_phy)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002192__releases(&bp->phy_lock)
2193__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002194{
2195 u32 val;
2196 int rc = 0;
2197
Michael Chan583c28e2008-01-21 19:51:35 -08002198 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2199 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
Michael Chanb6016b72005-05-26 13:03:09 -07002200
Michael Chanca58c3a2007-05-03 13:22:52 -07002201 bp->mii_bmcr = MII_BMCR;
2202 bp->mii_bmsr = MII_BMSR;
Michael Chan27a005b2007-05-03 13:23:41 -07002203 bp->mii_bmsr1 = MII_BMSR;
Michael Chanca58c3a2007-05-03 13:22:52 -07002204 bp->mii_adv = MII_ADVERTISE;
2205 bp->mii_lpa = MII_LPA;
2206
Michael Chanb6016b72005-05-26 13:03:09 -07002207 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2208
Michael Chan583c28e2008-01-21 19:51:35 -08002209 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07002210 goto setup_phy;
2211
Michael Chanb6016b72005-05-26 13:03:09 -07002212 bnx2_read_phy(bp, MII_PHYSID1, &val);
2213 bp->phy_id = val << 16;
2214 bnx2_read_phy(bp, MII_PHYSID2, &val);
2215 bp->phy_id |= val & 0xffff;
2216
Michael Chan583c28e2008-01-21 19:51:35 -08002217 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002218 if (CHIP_NUM(bp) == CHIP_NUM_5706)
Michael Chan9a120bc2008-05-16 22:17:45 -07002219 rc = bnx2_init_5706s_phy(bp, reset_phy);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002220 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan9a120bc2008-05-16 22:17:45 -07002221 rc = bnx2_init_5708s_phy(bp, reset_phy);
Michael Chan27a005b2007-05-03 13:23:41 -07002222 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan9a120bc2008-05-16 22:17:45 -07002223 rc = bnx2_init_5709s_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002224 }
2225 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07002226 rc = bnx2_init_copper_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002227 }
2228
Michael Chan0d8a6572007-07-07 22:49:43 -07002229setup_phy:
2230 if (!rc)
2231 rc = bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07002232
2233 return rc;
2234}
2235
2236static int
2237bnx2_set_mac_loopback(struct bnx2 *bp)
2238{
2239 u32 mac_mode;
2240
2241 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2242 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2243 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2244 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2245 bp->link_up = 1;
2246 return 0;
2247}
2248
Michael Chanbc5a0692006-01-23 16:13:22 -08002249static int bnx2_test_link(struct bnx2 *);
2250
2251static int
2252bnx2_set_phy_loopback(struct bnx2 *bp)
2253{
2254 u32 mac_mode;
2255 int rc, i;
2256
2257 spin_lock_bh(&bp->phy_lock);
Michael Chanca58c3a2007-05-03 13:22:52 -07002258 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
Michael Chanbc5a0692006-01-23 16:13:22 -08002259 BMCR_SPEED1000);
2260 spin_unlock_bh(&bp->phy_lock);
2261 if (rc)
2262 return rc;
2263
2264 for (i = 0; i < 10; i++) {
2265 if (bnx2_test_link(bp) == 0)
2266 break;
Michael Chan80be4432006-11-19 14:07:28 -08002267 msleep(100);
Michael Chanbc5a0692006-01-23 16:13:22 -08002268 }
2269
2270 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2271 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2272 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08002273 BNX2_EMAC_MODE_25G_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002274
2275 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2276 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2277 bp->link_up = 1;
2278 return 0;
2279}
2280
Michael Chanb6016b72005-05-26 13:03:09 -07002281static int
Michael Chana2f13892008-07-14 22:38:23 -07002282bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
Michael Chanb6016b72005-05-26 13:03:09 -07002283{
2284 int i;
2285 u32 val;
2286
Michael Chanb6016b72005-05-26 13:03:09 -07002287 bp->fw_wr_seq++;
2288 msg_data |= bp->fw_wr_seq;
2289
Michael Chan2726d6e2008-01-29 21:35:05 -08002290 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002291
Michael Chana2f13892008-07-14 22:38:23 -07002292 if (!ack)
2293 return 0;
2294
Michael Chanb6016b72005-05-26 13:03:09 -07002295 /* wait for an acknowledgement. */
Michael Chan40105c02008-11-12 16:02:45 -08002296 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
Michael Chanb090ae22006-01-23 16:07:10 -08002297 msleep(10);
Michael Chanb6016b72005-05-26 13:03:09 -07002298
Michael Chan2726d6e2008-01-29 21:35:05 -08002299 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
Michael Chanb6016b72005-05-26 13:03:09 -07002300
2301 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2302 break;
2303 }
Michael Chanb090ae22006-01-23 16:07:10 -08002304 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2305 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002306
2307 /* If we timed out, inform the firmware that this is the case. */
Michael Chanb090ae22006-01-23 16:07:10 -08002308 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2309 if (!silent)
2310 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2311 "%x\n", msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002312
2313 msg_data &= ~BNX2_DRV_MSG_CODE;
2314 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2315
Michael Chan2726d6e2008-01-29 21:35:05 -08002316 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002317
Michael Chanb6016b72005-05-26 13:03:09 -07002318 return -EBUSY;
2319 }
2320
Michael Chanb090ae22006-01-23 16:07:10 -08002321 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2322 return -EIO;
2323
Michael Chanb6016b72005-05-26 13:03:09 -07002324 return 0;
2325}
2326
Michael Chan59b47d82006-11-19 14:10:45 -08002327static int
2328bnx2_init_5709_context(struct bnx2 *bp)
2329{
2330 int i, ret = 0;
2331 u32 val;
2332
2333 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2334 val |= (BCM_PAGE_BITS - 8) << 16;
2335 REG_WR(bp, BNX2_CTX_COMMAND, val);
Michael Chan641bdcd2007-06-04 21:22:24 -07002336 for (i = 0; i < 10; i++) {
2337 val = REG_RD(bp, BNX2_CTX_COMMAND);
2338 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2339 break;
2340 udelay(2);
2341 }
2342 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2343 return -EBUSY;
2344
Michael Chan59b47d82006-11-19 14:10:45 -08002345 for (i = 0; i < bp->ctx_pages; i++) {
2346 int j;
2347
Michael Chan352f7682008-05-02 16:57:26 -07002348 if (bp->ctx_blk[i])
2349 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2350 else
2351 return -ENOMEM;
2352
Michael Chan59b47d82006-11-19 14:10:45 -08002353 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2354 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2355 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2356 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2357 (u64) bp->ctx_blk_mapping[i] >> 32);
2358 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2359 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2360 for (j = 0; j < 10; j++) {
2361
2362 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2363 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2364 break;
2365 udelay(5);
2366 }
2367 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2368 ret = -EBUSY;
2369 break;
2370 }
2371 }
2372 return ret;
2373}
2374
Michael Chanb6016b72005-05-26 13:03:09 -07002375static void
2376bnx2_init_context(struct bnx2 *bp)
2377{
2378 u32 vcid;
2379
2380 vcid = 96;
2381 while (vcid) {
2382 u32 vcid_addr, pcid_addr, offset;
Michael Chan7947b202007-06-04 21:17:10 -07002383 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07002384
2385 vcid--;
2386
2387 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2388 u32 new_vcid;
2389
2390 vcid_addr = GET_PCID_ADDR(vcid);
2391 if (vcid & 0x8) {
2392 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2393 }
2394 else {
2395 new_vcid = vcid;
2396 }
2397 pcid_addr = GET_PCID_ADDR(new_vcid);
2398 }
2399 else {
2400 vcid_addr = GET_CID_ADDR(vcid);
2401 pcid_addr = vcid_addr;
2402 }
2403
Michael Chan7947b202007-06-04 21:17:10 -07002404 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2405 vcid_addr += (i << PHY_CTX_SHIFT);
2406 pcid_addr += (i << PHY_CTX_SHIFT);
Michael Chanb6016b72005-05-26 13:03:09 -07002407
Michael Chan5d5d0012007-12-12 11:17:43 -08002408 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
Michael Chan7947b202007-06-04 21:17:10 -07002409 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2410
2411 /* Zero out the context. */
2412 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
Michael Chan62a83132008-01-29 21:35:40 -08002413 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07002414 }
Michael Chanb6016b72005-05-26 13:03:09 -07002415 }
2416}
2417
2418static int
2419bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2420{
2421 u16 *good_mbuf;
2422 u32 good_mbuf_cnt;
2423 u32 val;
2424
2425 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2426 if (good_mbuf == NULL) {
2427 printk(KERN_ERR PFX "Failed to allocate memory in "
2428 "bnx2_alloc_bad_rbuf\n");
2429 return -ENOMEM;
2430 }
2431
2432 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2433 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2434
2435 good_mbuf_cnt = 0;
2436
2437 /* Allocate a bunch of mbufs and save the good ones in an array. */
Michael Chan2726d6e2008-01-29 21:35:05 -08002438 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002439 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
Michael Chan2726d6e2008-01-29 21:35:05 -08002440 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2441 BNX2_RBUF_COMMAND_ALLOC_REQ);
Michael Chanb6016b72005-05-26 13:03:09 -07002442
Michael Chan2726d6e2008-01-29 21:35:05 -08002443 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
Michael Chanb6016b72005-05-26 13:03:09 -07002444
2445 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2446
2447 /* The addresses with Bit 9 set are bad memory blocks. */
2448 if (!(val & (1 << 9))) {
2449 good_mbuf[good_mbuf_cnt] = (u16) val;
2450 good_mbuf_cnt++;
2451 }
2452
Michael Chan2726d6e2008-01-29 21:35:05 -08002453 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002454 }
2455
2456 /* Free the good ones back to the mbuf pool thus discarding
2457 * all the bad ones. */
2458 while (good_mbuf_cnt) {
2459 good_mbuf_cnt--;
2460
2461 val = good_mbuf[good_mbuf_cnt];
2462 val = (val << 9) | val | 1;
2463
Michael Chan2726d6e2008-01-29 21:35:05 -08002464 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07002465 }
2466 kfree(good_mbuf);
2467 return 0;
2468}
2469
2470static void
Benjamin Li5fcaed02008-07-14 22:39:52 -07002471bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
Michael Chanb6016b72005-05-26 13:03:09 -07002472{
2473 u32 val;
Michael Chanb6016b72005-05-26 13:03:09 -07002474
2475 val = (mac_addr[0] << 8) | mac_addr[1];
2476
Benjamin Li5fcaed02008-07-14 22:39:52 -07002477 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002478
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002479 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
Michael Chanb6016b72005-05-26 13:03:09 -07002480 (mac_addr[4] << 8) | mac_addr[5];
2481
Benjamin Li5fcaed02008-07-14 22:39:52 -07002482 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002483}
2484
2485static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002486bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002487{
2488 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002489 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002490 struct rx_bd *rxbd =
Michael Chanbb4f98a2008-06-19 16:38:19 -07002491 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chan47bf4242007-12-12 11:19:12 -08002492 struct page *page = alloc_page(GFP_ATOMIC);
2493
2494 if (!page)
2495 return -ENOMEM;
2496 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2497 PCI_DMA_FROMDEVICE);
Benjamin Li3d16af82008-10-09 12:26:41 -07002498 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2499 __free_page(page);
2500 return -EIO;
2501 }
2502
Michael Chan47bf4242007-12-12 11:19:12 -08002503 rx_pg->page = page;
2504 pci_unmap_addr_set(rx_pg, mapping, mapping);
2505 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2506 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2507 return 0;
2508}
2509
2510static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002511bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002512{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002513 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002514 struct page *page = rx_pg->page;
2515
2516 if (!page)
2517 return;
2518
2519 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2520 PCI_DMA_FROMDEVICE);
2521
2522 __free_page(page);
2523 rx_pg->page = NULL;
2524}
2525
2526static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002527bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chanb6016b72005-05-26 13:03:09 -07002528{
2529 struct sk_buff *skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002530 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
Michael Chanb6016b72005-05-26 13:03:09 -07002531 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002532 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chanb6016b72005-05-26 13:03:09 -07002533 unsigned long align;
2534
Michael Chan932f3772006-08-15 01:39:36 -07002535 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
Michael Chanb6016b72005-05-26 13:03:09 -07002536 if (skb == NULL) {
2537 return -ENOMEM;
2538 }
2539
Michael Chan59b47d82006-11-19 14:10:45 -08002540 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2541 skb_reserve(skb, BNX2_RX_ALIGN - align);
Michael Chanb6016b72005-05-26 13:03:09 -07002542
Michael Chanb6016b72005-05-26 13:03:09 -07002543 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2544 PCI_DMA_FROMDEVICE);
Benjamin Li3d16af82008-10-09 12:26:41 -07002545 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2546 dev_kfree_skb(skb);
2547 return -EIO;
2548 }
Michael Chanb6016b72005-05-26 13:03:09 -07002549
2550 rx_buf->skb = skb;
2551 pci_unmap_addr_set(rx_buf, mapping, mapping);
2552
2553 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2554 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2555
Michael Chanbb4f98a2008-06-19 16:38:19 -07002556 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chanb6016b72005-05-26 13:03:09 -07002557
2558 return 0;
2559}
2560
Michael Chanda3e4fb2007-05-03 13:24:23 -07002561static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002562bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002563{
Michael Chan43e80b82008-06-19 16:41:08 -07002564 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07002565 u32 new_link_state, old_link_state;
2566 int is_set = 1;
2567
2568 new_link_state = sblk->status_attn_bits & event;
2569 old_link_state = sblk->status_attn_bits_ack & event;
2570 if (new_link_state != old_link_state) {
2571 if (new_link_state)
2572 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2573 else
2574 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2575 } else
2576 is_set = 0;
2577
2578 return is_set;
2579}
2580
Michael Chanb6016b72005-05-26 13:03:09 -07002581static void
Michael Chan35efa7c2007-12-20 19:56:37 -08002582bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07002583{
Michael Chan74ecc622008-05-02 16:56:16 -07002584 spin_lock(&bp->phy_lock);
2585
2586 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
Michael Chanb6016b72005-05-26 13:03:09 -07002587 bnx2_set_link(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08002588 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
Michael Chan0d8a6572007-07-07 22:49:43 -07002589 bnx2_set_remote_link(bp);
2590
Michael Chan74ecc622008-05-02 16:56:16 -07002591 spin_unlock(&bp->phy_lock);
2592
Michael Chanb6016b72005-05-26 13:03:09 -07002593}
2594
Michael Chanead72702007-12-20 19:55:39 -08002595static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002596bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
Michael Chanead72702007-12-20 19:55:39 -08002597{
2598 u16 cons;
2599
Michael Chan43e80b82008-06-19 16:41:08 -07002600 /* Tell compiler that status block fields can change. */
2601 barrier();
2602 cons = *bnapi->hw_tx_cons_ptr;
Michael Chanead72702007-12-20 19:55:39 -08002603 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2604 cons++;
2605 return cons;
2606}
2607
Michael Chan57851d82007-12-20 20:01:44 -08002608static int
2609bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002610{
Michael Chan35e90102008-06-19 16:37:42 -07002611 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002612 u16 hw_cons, sw_cons, sw_ring_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002613 int tx_pkt = 0, index;
2614 struct netdev_queue *txq;
2615
2616 index = (bnapi - bp->bnx2_napi);
2617 txq = netdev_get_tx_queue(bp->dev, index);
Michael Chanb6016b72005-05-26 13:03:09 -07002618
Michael Chan35efa7c2007-12-20 19:56:37 -08002619 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chan35e90102008-06-19 16:37:42 -07002620 sw_cons = txr->tx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07002621
2622 while (sw_cons != hw_cons) {
Benjamin Li3d16af82008-10-09 12:26:41 -07002623 struct sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07002624 struct sk_buff *skb;
2625 int i, last;
2626
2627 sw_ring_cons = TX_RING_IDX(sw_cons);
2628
Michael Chan35e90102008-06-19 16:37:42 -07002629 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002630 skb = tx_buf->skb;
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002631
Michael Chanb6016b72005-05-26 13:03:09 -07002632 /* partial BD completions possible with TSO packets */
Herbert Xu89114af2006-07-08 13:34:32 -07002633 if (skb_is_gso(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002634 u16 last_idx, last_ring_idx;
2635
2636 last_idx = sw_cons +
2637 skb_shinfo(skb)->nr_frags + 1;
2638 last_ring_idx = sw_ring_cons +
2639 skb_shinfo(skb)->nr_frags + 1;
2640 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2641 last_idx++;
2642 }
2643 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2644 break;
2645 }
2646 }
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002647
Benjamin Li3d16af82008-10-09 12:26:41 -07002648 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002649
2650 tx_buf->skb = NULL;
2651 last = skb_shinfo(skb)->nr_frags;
2652
2653 for (i = 0; i < last; i++) {
2654 sw_cons = NEXT_TX_BD(sw_cons);
Michael Chanb6016b72005-05-26 13:03:09 -07002655 }
2656
2657 sw_cons = NEXT_TX_BD(sw_cons);
2658
Michael Chan745720e2006-06-29 12:37:41 -07002659 dev_kfree_skb(skb);
Michael Chan57851d82007-12-20 20:01:44 -08002660 tx_pkt++;
2661 if (tx_pkt == budget)
2662 break;
Michael Chanb6016b72005-05-26 13:03:09 -07002663
Michael Chan35efa7c2007-12-20 19:56:37 -08002664 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07002665 }
2666
Michael Chan35e90102008-06-19 16:37:42 -07002667 txr->hw_tx_cons = hw_cons;
2668 txr->tx_cons = sw_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002669
Michael Chan2f8af122006-08-15 01:39:10 -07002670 /* Need to make the tx_cons update visible to bnx2_start_xmit()
Benjamin Li706bf242008-07-18 17:55:11 -07002671 * before checking for netif_tx_queue_stopped(). Without the
Michael Chan2f8af122006-08-15 01:39:10 -07002672 * memory barrier, there is a small possibility that bnx2_start_xmit()
2673 * will miss it and cause the queue to be stopped forever.
2674 */
2675 smp_mb();
Michael Chanb6016b72005-05-26 13:03:09 -07002676
Benjamin Li706bf242008-07-18 17:55:11 -07002677 if (unlikely(netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002678 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
Benjamin Li706bf242008-07-18 17:55:11 -07002679 __netif_tx_lock(txq, smp_processor_id());
2680 if ((netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002681 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
Benjamin Li706bf242008-07-18 17:55:11 -07002682 netif_tx_wake_queue(txq);
2683 __netif_tx_unlock(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07002684 }
Benjamin Li706bf242008-07-18 17:55:11 -07002685
Michael Chan57851d82007-12-20 20:01:44 -08002686 return tx_pkt;
Michael Chanb6016b72005-05-26 13:03:09 -07002687}
2688
Michael Chan1db82f22007-12-12 11:19:35 -08002689static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002690bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
Michael Chana1f60192007-12-20 19:57:19 -08002691 struct sk_buff *skb, int count)
Michael Chan1db82f22007-12-12 11:19:35 -08002692{
2693 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2694 struct rx_bd *cons_bd, *prod_bd;
Michael Chan1db82f22007-12-12 11:19:35 -08002695 int i;
Benjamin Li3d16af82008-10-09 12:26:41 -07002696 u16 hw_prod, prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002697 u16 cons = rxr->rx_pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002698
Benjamin Li3d16af82008-10-09 12:26:41 -07002699 cons_rx_pg = &rxr->rx_pg_ring[cons];
2700
2701 /* The caller was unable to allocate a new page to replace the
2702 * last one in the frags array, so we need to recycle that page
2703 * and then free the skb.
2704 */
2705 if (skb) {
2706 struct page *page;
2707 struct skb_shared_info *shinfo;
2708
2709 shinfo = skb_shinfo(skb);
2710 shinfo->nr_frags--;
2711 page = shinfo->frags[shinfo->nr_frags].page;
2712 shinfo->frags[shinfo->nr_frags].page = NULL;
2713
2714 cons_rx_pg->page = page;
2715 dev_kfree_skb(skb);
2716 }
2717
2718 hw_prod = rxr->rx_pg_prod;
2719
Michael Chan1db82f22007-12-12 11:19:35 -08002720 for (i = 0; i < count; i++) {
2721 prod = RX_PG_RING_IDX(hw_prod);
2722
Michael Chanbb4f98a2008-06-19 16:38:19 -07002723 prod_rx_pg = &rxr->rx_pg_ring[prod];
2724 cons_rx_pg = &rxr->rx_pg_ring[cons];
2725 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2726 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan1db82f22007-12-12 11:19:35 -08002727
Michael Chan1db82f22007-12-12 11:19:35 -08002728 if (prod != cons) {
2729 prod_rx_pg->page = cons_rx_pg->page;
2730 cons_rx_pg->page = NULL;
2731 pci_unmap_addr_set(prod_rx_pg, mapping,
2732 pci_unmap_addr(cons_rx_pg, mapping));
2733
2734 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2735 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2736
2737 }
2738 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2739 hw_prod = NEXT_RX_BD(hw_prod);
2740 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002741 rxr->rx_pg_prod = hw_prod;
2742 rxr->rx_pg_cons = cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002743}
2744
Michael Chanb6016b72005-05-26 13:03:09 -07002745static inline void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002746bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2747 struct sk_buff *skb, u16 cons, u16 prod)
Michael Chanb6016b72005-05-26 13:03:09 -07002748{
Michael Chan236b6392006-03-20 17:49:02 -08002749 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2750 struct rx_bd *cons_bd, *prod_bd;
2751
Michael Chanbb4f98a2008-06-19 16:38:19 -07002752 cons_rx_buf = &rxr->rx_buf_ring[cons];
2753 prod_rx_buf = &rxr->rx_buf_ring[prod];
Michael Chanb6016b72005-05-26 13:03:09 -07002754
2755 pci_dma_sync_single_for_device(bp->pdev,
2756 pci_unmap_addr(cons_rx_buf, mapping),
Benjamin Li601d3d12008-05-16 22:19:35 -07002757 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002758
Michael Chanbb4f98a2008-06-19 16:38:19 -07002759 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chan236b6392006-03-20 17:49:02 -08002760
2761 prod_rx_buf->skb = skb;
2762
2763 if (cons == prod)
2764 return;
2765
Michael Chanb6016b72005-05-26 13:03:09 -07002766 pci_unmap_addr_set(prod_rx_buf, mapping,
2767 pci_unmap_addr(cons_rx_buf, mapping));
2768
Michael Chanbb4f98a2008-06-19 16:38:19 -07002769 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2770 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan236b6392006-03-20 17:49:02 -08002771 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2772 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
Michael Chanb6016b72005-05-26 13:03:09 -07002773}
2774
Michael Chan85833c62007-12-12 11:17:01 -08002775static int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002776bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
Michael Chana1f60192007-12-20 19:57:19 -08002777 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2778 u32 ring_idx)
Michael Chan85833c62007-12-12 11:17:01 -08002779{
2780 int err;
2781 u16 prod = ring_idx & 0xffff;
2782
Michael Chanbb4f98a2008-06-19 16:38:19 -07002783 err = bnx2_alloc_rx_skb(bp, rxr, prod);
Michael Chan85833c62007-12-12 11:17:01 -08002784 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002785 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002786 if (hdr_len) {
2787 unsigned int raw_len = len + 4;
2788 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2789
Michael Chanbb4f98a2008-06-19 16:38:19 -07002790 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
Michael Chan1db82f22007-12-12 11:19:35 -08002791 }
Michael Chan85833c62007-12-12 11:17:01 -08002792 return err;
2793 }
2794
Benjamin Lid89cb6a2008-05-16 22:18:57 -07002795 skb_reserve(skb, BNX2_RX_OFFSET);
Michael Chan85833c62007-12-12 11:17:01 -08002796 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2797 PCI_DMA_FROMDEVICE);
2798
Michael Chan1db82f22007-12-12 11:19:35 -08002799 if (hdr_len == 0) {
2800 skb_put(skb, len);
2801 return 0;
2802 } else {
2803 unsigned int i, frag_len, frag_size, pages;
2804 struct sw_pg *rx_pg;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002805 u16 pg_cons = rxr->rx_pg_cons;
2806 u16 pg_prod = rxr->rx_pg_prod;
Michael Chan1db82f22007-12-12 11:19:35 -08002807
2808 frag_size = len + 4 - hdr_len;
2809 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2810 skb_put(skb, hdr_len);
2811
2812 for (i = 0; i < pages; i++) {
Benjamin Li3d16af82008-10-09 12:26:41 -07002813 dma_addr_t mapping_old;
2814
Michael Chan1db82f22007-12-12 11:19:35 -08002815 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2816 if (unlikely(frag_len <= 4)) {
2817 unsigned int tail = 4 - frag_len;
2818
Michael Chanbb4f98a2008-06-19 16:38:19 -07002819 rxr->rx_pg_cons = pg_cons;
2820 rxr->rx_pg_prod = pg_prod;
2821 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
Michael Chana1f60192007-12-20 19:57:19 -08002822 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002823 skb->len -= tail;
2824 if (i == 0) {
2825 skb->tail -= tail;
2826 } else {
2827 skb_frag_t *frag =
2828 &skb_shinfo(skb)->frags[i - 1];
2829 frag->size -= tail;
2830 skb->data_len -= tail;
2831 skb->truesize -= tail;
2832 }
2833 return 0;
2834 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002835 rx_pg = &rxr->rx_pg_ring[pg_cons];
Michael Chan1db82f22007-12-12 11:19:35 -08002836
Benjamin Li3d16af82008-10-09 12:26:41 -07002837 /* Don't unmap yet. If we're unable to allocate a new
2838 * page, we need to recycle the page and the DMA addr.
2839 */
2840 mapping_old = pci_unmap_addr(rx_pg, mapping);
Michael Chan1db82f22007-12-12 11:19:35 -08002841 if (i == pages - 1)
2842 frag_len -= 4;
2843
2844 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2845 rx_pg->page = NULL;
2846
Michael Chanbb4f98a2008-06-19 16:38:19 -07002847 err = bnx2_alloc_rx_page(bp, rxr,
2848 RX_PG_RING_IDX(pg_prod));
Michael Chan1db82f22007-12-12 11:19:35 -08002849 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002850 rxr->rx_pg_cons = pg_cons;
2851 rxr->rx_pg_prod = pg_prod;
2852 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
Michael Chana1f60192007-12-20 19:57:19 -08002853 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002854 return err;
2855 }
2856
Benjamin Li3d16af82008-10-09 12:26:41 -07002857 pci_unmap_page(bp->pdev, mapping_old,
2858 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2859
Michael Chan1db82f22007-12-12 11:19:35 -08002860 frag_size -= frag_len;
2861 skb->data_len += frag_len;
2862 skb->truesize += frag_len;
2863 skb->len += frag_len;
2864
2865 pg_prod = NEXT_RX_BD(pg_prod);
2866 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2867 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002868 rxr->rx_pg_prod = pg_prod;
2869 rxr->rx_pg_cons = pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002870 }
Michael Chan85833c62007-12-12 11:17:01 -08002871 return 0;
2872}
2873
Michael Chanc09c2622007-12-10 17:18:37 -08002874static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002875bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
Michael Chanc09c2622007-12-10 17:18:37 -08002876{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002877 u16 cons;
2878
Michael Chan43e80b82008-06-19 16:41:08 -07002879 /* Tell compiler that status block fields can change. */
2880 barrier();
2881 cons = *bnapi->hw_rx_cons_ptr;
Michael Chanc09c2622007-12-10 17:18:37 -08002882 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2883 cons++;
2884 return cons;
2885}
2886
Michael Chanb6016b72005-05-26 13:03:09 -07002887static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002888bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002889{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002890 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002891 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2892 struct l2_fhdr *rx_hdr;
Michael Chan1db82f22007-12-12 11:19:35 -08002893 int rx_pkt = 0, pg_ring_used = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002894
Michael Chan35efa7c2007-12-20 19:56:37 -08002895 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanbb4f98a2008-06-19 16:38:19 -07002896 sw_cons = rxr->rx_cons;
2897 sw_prod = rxr->rx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07002898
2899 /* Memory barrier necessary as speculative reads of the rx
2900 * buffer can be ahead of the index in the status block
2901 */
2902 rmb();
2903 while (sw_cons != hw_cons) {
Michael Chan1db82f22007-12-12 11:19:35 -08002904 unsigned int len, hdr_len;
Michael Chanade2bfe2006-01-23 16:09:51 -08002905 u32 status;
Michael Chanb6016b72005-05-26 13:03:09 -07002906 struct sw_bd *rx_buf;
2907 struct sk_buff *skb;
Michael Chan236b6392006-03-20 17:49:02 -08002908 dma_addr_t dma_addr;
Michael Chanf22828e2008-08-14 15:30:14 -07002909 u16 vtag = 0;
2910 int hw_vlan __maybe_unused = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002911
2912 sw_ring_cons = RX_RING_IDX(sw_cons);
2913 sw_ring_prod = RX_RING_IDX(sw_prod);
2914
Michael Chanbb4f98a2008-06-19 16:38:19 -07002915 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002916 skb = rx_buf->skb;
Michael Chan236b6392006-03-20 17:49:02 -08002917
2918 rx_buf->skb = NULL;
2919
2920 dma_addr = pci_unmap_addr(rx_buf, mapping);
2921
2922 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
Benjamin Li601d3d12008-05-16 22:19:35 -07002923 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2924 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002925
2926 rx_hdr = (struct l2_fhdr *) skb->data;
Michael Chan1db82f22007-12-12 11:19:35 -08002927 len = rx_hdr->l2_fhdr_pkt_len;
Michael Chan990ec382009-02-12 16:54:13 -08002928 status = rx_hdr->l2_fhdr_status;
Michael Chanb6016b72005-05-26 13:03:09 -07002929
Michael Chan1db82f22007-12-12 11:19:35 -08002930 hdr_len = 0;
2931 if (status & L2_FHDR_STATUS_SPLIT) {
2932 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2933 pg_ring_used = 1;
2934 } else if (len > bp->rx_jumbo_thresh) {
2935 hdr_len = bp->rx_jumbo_thresh;
2936 pg_ring_used = 1;
2937 }
2938
Michael Chan990ec382009-02-12 16:54:13 -08002939 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
2940 L2_FHDR_ERRORS_PHY_DECODE |
2941 L2_FHDR_ERRORS_ALIGNMENT |
2942 L2_FHDR_ERRORS_TOO_SHORT |
2943 L2_FHDR_ERRORS_GIANT_FRAME))) {
2944
2945 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2946 sw_ring_prod);
2947 if (pg_ring_used) {
2948 int pages;
2949
2950 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
2951
2952 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2953 }
2954 goto next_rx;
2955 }
2956
Michael Chan1db82f22007-12-12 11:19:35 -08002957 len -= 4;
Michael Chanb6016b72005-05-26 13:03:09 -07002958
Michael Chan5d5d0012007-12-12 11:17:43 -08002959 if (len <= bp->rx_copy_thresh) {
Michael Chanb6016b72005-05-26 13:03:09 -07002960 struct sk_buff *new_skb;
2961
Michael Chanf22828e2008-08-14 15:30:14 -07002962 new_skb = netdev_alloc_skb(bp->dev, len + 6);
Michael Chan85833c62007-12-12 11:17:01 -08002963 if (new_skb == NULL) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002964 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
Michael Chan85833c62007-12-12 11:17:01 -08002965 sw_ring_prod);
2966 goto next_rx;
2967 }
Michael Chanb6016b72005-05-26 13:03:09 -07002968
2969 /* aligned copy */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07002970 skb_copy_from_linear_data_offset(skb,
Michael Chanf22828e2008-08-14 15:30:14 -07002971 BNX2_RX_OFFSET - 6,
2972 new_skb->data, len + 6);
2973 skb_reserve(new_skb, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07002974 skb_put(new_skb, len);
Michael Chanb6016b72005-05-26 13:03:09 -07002975
Michael Chanbb4f98a2008-06-19 16:38:19 -07002976 bnx2_reuse_rx_skb(bp, rxr, skb,
Michael Chanb6016b72005-05-26 13:03:09 -07002977 sw_ring_cons, sw_ring_prod);
2978
2979 skb = new_skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002980 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
Michael Chana1f60192007-12-20 19:57:19 -08002981 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
Michael Chanb6016b72005-05-26 13:03:09 -07002982 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07002983
Michael Chanf22828e2008-08-14 15:30:14 -07002984 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2985 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2986 vtag = rx_hdr->l2_fhdr_vlan_tag;
2987#ifdef BCM_VLAN
2988 if (bp->vlgrp)
2989 hw_vlan = 1;
2990 else
2991#endif
2992 {
2993 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2994 __skb_push(skb, 4);
2995
2996 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2997 ve->h_vlan_proto = htons(ETH_P_8021Q);
2998 ve->h_vlan_TCI = htons(vtag);
2999 len += 4;
3000 }
3001 }
3002
Michael Chanb6016b72005-05-26 13:03:09 -07003003 skb->protocol = eth_type_trans(skb, bp->dev);
3004
3005 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
Alexey Dobriyand1e100b2006-06-11 20:57:17 -07003006 (ntohs(skb->protocol) != 0x8100)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003007
Michael Chan745720e2006-06-29 12:37:41 -07003008 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07003009 goto next_rx;
3010
3011 }
3012
Michael Chanb6016b72005-05-26 13:03:09 -07003013 skb->ip_summed = CHECKSUM_NONE;
3014 if (bp->rx_csum &&
3015 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3016 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3017
Michael Chanade2bfe2006-01-23 16:09:51 -08003018 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3019 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
Michael Chanb6016b72005-05-26 13:03:09 -07003020 skb->ip_summed = CHECKSUM_UNNECESSARY;
3021 }
3022
David S. Miller0c8dfc82009-01-27 16:22:32 -08003023 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3024
Michael Chanb6016b72005-05-26 13:03:09 -07003025#ifdef BCM_VLAN
Michael Chanf22828e2008-08-14 15:30:14 -07003026 if (hw_vlan)
3027 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
Michael Chanb6016b72005-05-26 13:03:09 -07003028 else
3029#endif
3030 netif_receive_skb(skb);
3031
Michael Chanb6016b72005-05-26 13:03:09 -07003032 rx_pkt++;
3033
3034next_rx:
Michael Chanb6016b72005-05-26 13:03:09 -07003035 sw_cons = NEXT_RX_BD(sw_cons);
3036 sw_prod = NEXT_RX_BD(sw_prod);
3037
3038 if ((rx_pkt == budget))
3039 break;
Michael Chanf4e418f2005-11-04 08:53:48 -08003040
3041 /* Refresh hw_cons to see if there is new work */
3042 if (sw_cons == hw_cons) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003043 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanf4e418f2005-11-04 08:53:48 -08003044 rmb();
3045 }
Michael Chanb6016b72005-05-26 13:03:09 -07003046 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003047 rxr->rx_cons = sw_cons;
3048 rxr->rx_prod = sw_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003049
Michael Chan1db82f22007-12-12 11:19:35 -08003050 if (pg_ring_used)
Michael Chanbb4f98a2008-06-19 16:38:19 -07003051 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08003052
Michael Chanbb4f98a2008-06-19 16:38:19 -07003053 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003054
Michael Chanbb4f98a2008-06-19 16:38:19 -07003055 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07003056
3057 mmiowb();
3058
3059 return rx_pkt;
3060
3061}
3062
3063/* MSI ISR - The only difference between this and the INTx ISR
3064 * is that the MSI interrupt is always serviced.
3065 */
3066static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003067bnx2_msi(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003068{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003069 struct bnx2_napi *bnapi = dev_instance;
3070 struct bnx2 *bp = bnapi->bp;
Michael Chanb6016b72005-05-26 13:03:09 -07003071
Michael Chan43e80b82008-06-19 16:41:08 -07003072 prefetch(bnapi->status_blk.msi);
Michael Chanb6016b72005-05-26 13:03:09 -07003073 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3074 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3075 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3076
3077 /* Return here if interrupt is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003078 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3079 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003080
Ben Hutchings288379f2009-01-19 16:43:59 -08003081 napi_schedule(&bnapi->napi);
Michael Chanb6016b72005-05-26 13:03:09 -07003082
Michael Chan73eef4c2005-08-25 15:39:15 -07003083 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003084}
3085
3086static irqreturn_t
Michael Chan8e6a72c2007-05-03 13:24:48 -07003087bnx2_msi_1shot(int irq, void *dev_instance)
3088{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003089 struct bnx2_napi *bnapi = dev_instance;
3090 struct bnx2 *bp = bnapi->bp;
Michael Chan8e6a72c2007-05-03 13:24:48 -07003091
Michael Chan43e80b82008-06-19 16:41:08 -07003092 prefetch(bnapi->status_blk.msi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003093
3094 /* Return here if interrupt is disabled. */
3095 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3096 return IRQ_HANDLED;
3097
Ben Hutchings288379f2009-01-19 16:43:59 -08003098 napi_schedule(&bnapi->napi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003099
3100 return IRQ_HANDLED;
3101}
3102
3103static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003104bnx2_interrupt(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003105{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003106 struct bnx2_napi *bnapi = dev_instance;
3107 struct bnx2 *bp = bnapi->bp;
Michael Chan43e80b82008-06-19 16:41:08 -07003108 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanb6016b72005-05-26 13:03:09 -07003109
3110 /* When using INTx, it is possible for the interrupt to arrive
3111 * at the CPU before the status block posted prior to the
3112 * interrupt. Reading a register will flush the status block.
3113 * When using MSI, the MSI message will always complete after
3114 * the status block write.
3115 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003116 if ((sblk->status_idx == bnapi->last_status_idx) &&
Michael Chanb6016b72005-05-26 13:03:09 -07003117 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3118 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
Michael Chan73eef4c2005-08-25 15:39:15 -07003119 return IRQ_NONE;
Michael Chanb6016b72005-05-26 13:03:09 -07003120
3121 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3122 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3123 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3124
Michael Chanb8a7ce72007-07-07 22:51:03 -07003125 /* Read back to deassert IRQ immediately to avoid too many
3126 * spurious interrupts.
3127 */
3128 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3129
Michael Chanb6016b72005-05-26 13:03:09 -07003130 /* Return here if interrupt is shared and is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003131 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3132 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003133
Ben Hutchings288379f2009-01-19 16:43:59 -08003134 if (napi_schedule_prep(&bnapi->napi)) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003135 bnapi->last_status_idx = sblk->status_idx;
Ben Hutchings288379f2009-01-19 16:43:59 -08003136 __napi_schedule(&bnapi->napi);
Michael Chanb8a7ce72007-07-07 22:51:03 -07003137 }
Michael Chanb6016b72005-05-26 13:03:09 -07003138
Michael Chan73eef4c2005-08-25 15:39:15 -07003139 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003140}
3141
Michael Chan43e80b82008-06-19 16:41:08 -07003142static inline int
3143bnx2_has_fast_work(struct bnx2_napi *bnapi)
3144{
3145 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3146 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3147
3148 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3149 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3150 return 1;
3151 return 0;
3152}
3153
Michael Chan0d8a6572007-07-07 22:49:43 -07003154#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3155 STATUS_ATTN_BITS_TIMER_ABORT)
Michael Chanda3e4fb2007-05-03 13:24:23 -07003156
Michael Chanf4e418f2005-11-04 08:53:48 -08003157static inline int
Michael Chan35efa7c2007-12-20 19:56:37 -08003158bnx2_has_work(struct bnx2_napi *bnapi)
Michael Chanf4e418f2005-11-04 08:53:48 -08003159{
Michael Chan43e80b82008-06-19 16:41:08 -07003160 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanf4e418f2005-11-04 08:53:48 -08003161
Michael Chan43e80b82008-06-19 16:41:08 -07003162 if (bnx2_has_fast_work(bnapi))
Michael Chanf4e418f2005-11-04 08:53:48 -08003163 return 1;
3164
Michael Chanda3e4fb2007-05-03 13:24:23 -07003165 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3166 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
Michael Chanf4e418f2005-11-04 08:53:48 -08003167 return 1;
3168
3169 return 0;
3170}
3171
Michael Chanefba0182008-12-03 00:36:15 -08003172static void
3173bnx2_chk_missed_msi(struct bnx2 *bp)
3174{
3175 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3176 u32 msi_ctrl;
3177
3178 if (bnx2_has_work(bnapi)) {
3179 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3180 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3181 return;
3182
3183 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3184 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3185 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3186 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3187 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3188 }
3189 }
3190
3191 bp->idle_chk_status_idx = bnapi->last_status_idx;
3192}
3193
Michael Chan43e80b82008-06-19 16:41:08 -07003194static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07003195{
Michael Chan43e80b82008-06-19 16:41:08 -07003196 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07003197 u32 status_attn_bits = sblk->status_attn_bits;
3198 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
Michael Chanb6016b72005-05-26 13:03:09 -07003199
Michael Chanda3e4fb2007-05-03 13:24:23 -07003200 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3201 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003202
Michael Chan35efa7c2007-12-20 19:56:37 -08003203 bnx2_phy_int(bp, bnapi);
Michael Chanbf5295b2006-03-23 01:11:56 -08003204
3205 /* This is needed to take care of transient status
3206 * during link changes.
3207 */
3208 REG_WR(bp, BNX2_HC_COMMAND,
3209 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3210 REG_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07003211 }
Michael Chan43e80b82008-06-19 16:41:08 -07003212}
3213
3214static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3215 int work_done, int budget)
3216{
3217 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3218 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003219
Michael Chan35e90102008-06-19 16:37:42 -07003220 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
Michael Chan57851d82007-12-20 20:01:44 -08003221 bnx2_tx_int(bp, bnapi, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003222
Michael Chanbb4f98a2008-06-19 16:38:19 -07003223 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
Michael Chan35efa7c2007-12-20 19:56:37 -08003224 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003225
David S. Miller6f535762007-10-11 18:08:29 -07003226 return work_done;
3227}
Michael Chanf4e418f2005-11-04 08:53:48 -08003228
Michael Chanf0ea2e62008-06-19 16:41:57 -07003229static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3230{
3231 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3232 struct bnx2 *bp = bnapi->bp;
3233 int work_done = 0;
3234 struct status_block_msix *sblk = bnapi->status_blk.msix;
3235
3236 while (1) {
3237 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3238 if (unlikely(work_done >= budget))
3239 break;
3240
3241 bnapi->last_status_idx = sblk->status_idx;
3242 /* status idx must be read before checking for more work. */
3243 rmb();
3244 if (likely(!bnx2_has_fast_work(bnapi))) {
3245
Ben Hutchings288379f2009-01-19 16:43:59 -08003246 napi_complete(napi);
Michael Chanf0ea2e62008-06-19 16:41:57 -07003247 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3248 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3249 bnapi->last_status_idx);
3250 break;
3251 }
3252 }
3253 return work_done;
3254}
3255
David S. Miller6f535762007-10-11 18:08:29 -07003256static int bnx2_poll(struct napi_struct *napi, int budget)
3257{
Michael Chan35efa7c2007-12-20 19:56:37 -08003258 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3259 struct bnx2 *bp = bnapi->bp;
David S. Miller6f535762007-10-11 18:08:29 -07003260 int work_done = 0;
Michael Chan43e80b82008-06-19 16:41:08 -07003261 struct status_block *sblk = bnapi->status_blk.msi;
David S. Miller6f535762007-10-11 18:08:29 -07003262
3263 while (1) {
Michael Chan43e80b82008-06-19 16:41:08 -07003264 bnx2_poll_link(bp, bnapi);
3265
Michael Chan35efa7c2007-12-20 19:56:37 -08003266 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07003267
Michael Chan35efa7c2007-12-20 19:56:37 -08003268 /* bnapi->last_status_idx is used below to tell the hw how
Michael Chan6dee6422007-10-12 01:40:38 -07003269 * much work has been processed, so we must read it before
3270 * checking for more work.
3271 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003272 bnapi->last_status_idx = sblk->status_idx;
Michael Chanefba0182008-12-03 00:36:15 -08003273
3274 if (unlikely(work_done >= budget))
3275 break;
3276
Michael Chan6dee6422007-10-12 01:40:38 -07003277 rmb();
Michael Chan35efa7c2007-12-20 19:56:37 -08003278 if (likely(!bnx2_has_work(bnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08003279 napi_complete(napi);
David S. Millerf86e82f2008-01-21 17:15:40 -08003280 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
David S. Miller6f535762007-10-11 18:08:29 -07003281 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3282 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003283 bnapi->last_status_idx);
Michael Chan6dee6422007-10-12 01:40:38 -07003284 break;
David S. Miller6f535762007-10-11 18:08:29 -07003285 }
3286 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3287 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3288 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
Michael Chan35efa7c2007-12-20 19:56:37 -08003289 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003290
Michael Chan1269a8a2006-01-23 16:11:03 -08003291 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3292 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003293 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003294 break;
Michael Chan1269a8a2006-01-23 16:11:03 -08003295 }
Michael Chanb6016b72005-05-26 13:03:09 -07003296 }
3297
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003298 return work_done;
Michael Chanb6016b72005-05-26 13:03:09 -07003299}
3300
Herbert Xu932ff272006-06-09 12:20:56 -07003301/* Called with rtnl_lock from vlan functions and also netif_tx_lock
Michael Chanb6016b72005-05-26 13:03:09 -07003302 * from set_multicast.
3303 */
3304static void
3305bnx2_set_rx_mode(struct net_device *dev)
3306{
Michael Chan972ec0d2006-01-23 16:12:43 -08003307 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07003308 u32 rx_mode, sort_mode;
Benjamin Li5fcaed02008-07-14 22:39:52 -07003309 struct dev_addr_list *uc_ptr;
Michael Chanb6016b72005-05-26 13:03:09 -07003310 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07003311
Michael Chan9f52b562008-10-09 12:21:46 -07003312 if (!netif_running(dev))
3313 return;
3314
Michael Chanc770a652005-08-25 15:38:39 -07003315 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003316
3317 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3318 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3319 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3320#ifdef BCM_VLAN
Michael Chan7c6337a2008-08-14 15:29:09 -07003321 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
Michael Chanb6016b72005-05-26 13:03:09 -07003322 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003323#else
Michael Chan7c6337a2008-08-14 15:29:09 -07003324 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
Michael Chane29054f2006-01-23 16:06:06 -08003325 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003326#endif
3327 if (dev->flags & IFF_PROMISC) {
3328 /* Promiscuous mode. */
3329 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
Michael Chan75108732006-11-19 14:06:40 -08003330 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3331 BNX2_RPM_SORT_USER0_PROM_VLAN;
Michael Chanb6016b72005-05-26 13:03:09 -07003332 }
3333 else if (dev->flags & IFF_ALLMULTI) {
3334 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3335 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3336 0xffffffff);
3337 }
3338 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3339 }
3340 else {
3341 /* Accept one or more multicast(s). */
3342 struct dev_mc_list *mclist;
3343 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3344 u32 regidx;
3345 u32 bit;
3346 u32 crc;
3347
3348 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3349
3350 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3351 i++, mclist = mclist->next) {
3352
3353 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3354 bit = crc & 0xff;
3355 regidx = (bit & 0xe0) >> 5;
3356 bit &= 0x1f;
3357 mc_filter[regidx] |= (1 << bit);
3358 }
3359
3360 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3361 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3362 mc_filter[i]);
3363 }
3364
3365 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3366 }
3367
Benjamin Li5fcaed02008-07-14 22:39:52 -07003368 uc_ptr = NULL;
3369 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3370 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3371 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3372 BNX2_RPM_SORT_USER0_PROM_VLAN;
3373 } else if (!(dev->flags & IFF_PROMISC)) {
3374 uc_ptr = dev->uc_list;
3375
3376 /* Add all entries into to the match filter list */
3377 for (i = 0; i < dev->uc_count; i++) {
3378 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3379 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3380 sort_mode |= (1 <<
3381 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3382 uc_ptr = uc_ptr->next;
3383 }
3384
3385 }
3386
Michael Chanb6016b72005-05-26 13:03:09 -07003387 if (rx_mode != bp->rx_mode) {
3388 bp->rx_mode = rx_mode;
3389 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3390 }
3391
3392 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3393 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3394 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3395
Michael Chanc770a652005-08-25 15:38:39 -07003396 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003397}
3398
Michael Chan57579f72009-04-04 16:51:14 -07003399static int __devinit
3400check_fw_section(const struct firmware *fw,
3401 const struct bnx2_fw_file_section *section,
3402 u32 alignment, bool non_empty)
Michael Chanb6016b72005-05-26 13:03:09 -07003403{
Michael Chan57579f72009-04-04 16:51:14 -07003404 u32 offset = be32_to_cpu(section->offset);
3405 u32 len = be32_to_cpu(section->len);
Michael Chanb6016b72005-05-26 13:03:09 -07003406
Michael Chan57579f72009-04-04 16:51:14 -07003407 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3408 return -EINVAL;
3409 if ((non_empty && len == 0) || len > fw->size - offset ||
3410 len & (alignment - 1))
3411 return -EINVAL;
3412 return 0;
3413}
3414
3415static int __devinit
3416check_mips_fw_entry(const struct firmware *fw,
3417 const struct bnx2_mips_fw_file_entry *entry)
3418{
3419 if (check_fw_section(fw, &entry->text, 4, true) ||
3420 check_fw_section(fw, &entry->data, 4, false) ||
3421 check_fw_section(fw, &entry->rodata, 4, false))
3422 return -EINVAL;
3423 return 0;
3424}
3425
3426static int __devinit
3427bnx2_request_firmware(struct bnx2 *bp)
3428{
3429 const char *mips_fw_file, *rv2p_fw_file;
3430 const struct bnx2_mips_fw_file *mips;
3431 const struct bnx2_rv2p_fw_file *rv2p;
3432 int rc;
3433
3434 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3435 mips_fw_file = FW_MIPS_FILE_09;
3436 rv2p_fw_file = FW_RV2P_FILE_09;
3437 } else {
3438 mips_fw_file = FW_MIPS_FILE_06;
3439 rv2p_fw_file = FW_RV2P_FILE_06;
3440 }
3441
3442 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3443 if (rc) {
3444 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3445 mips_fw_file);
3446 return rc;
3447 }
3448
3449 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3450 if (rc) {
3451 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3452 rv2p_fw_file);
3453 return rc;
3454 }
3455 mips = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3456 rv2p = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3457 if (bp->mips_firmware->size < sizeof(*mips) ||
3458 check_mips_fw_entry(bp->mips_firmware, &mips->com) ||
3459 check_mips_fw_entry(bp->mips_firmware, &mips->cp) ||
3460 check_mips_fw_entry(bp->mips_firmware, &mips->rxp) ||
3461 check_mips_fw_entry(bp->mips_firmware, &mips->tpat) ||
3462 check_mips_fw_entry(bp->mips_firmware, &mips->txp)) {
3463 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3464 mips_fw_file);
3465 return -EINVAL;
3466 }
3467 if (bp->rv2p_firmware->size < sizeof(*rv2p) ||
3468 check_fw_section(bp->rv2p_firmware, &rv2p->proc1.rv2p, 8, true) ||
3469 check_fw_section(bp->rv2p_firmware, &rv2p->proc2.rv2p, 8, true)) {
3470 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3471 rv2p_fw_file);
3472 return -EINVAL;
3473 }
3474
3475 return 0;
3476}
3477
3478static u32
3479rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3480{
3481 switch (idx) {
3482 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3483 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3484 rv2p_code |= RV2P_BD_PAGE_SIZE;
3485 break;
3486 }
3487 return rv2p_code;
3488}
3489
3490static int
3491load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3492 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3493{
3494 u32 rv2p_code_len, file_offset;
3495 __be32 *rv2p_code;
3496 int i;
3497 u32 val, cmd, addr;
3498
3499 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3500 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3501
3502 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3503
3504 if (rv2p_proc == RV2P_PROC1) {
3505 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3506 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3507 } else {
3508 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3509 addr = BNX2_RV2P_PROC2_ADDR_CMD;
Michael Chand25be1d2008-05-02 16:57:59 -07003510 }
Michael Chanb6016b72005-05-26 13:03:09 -07003511
3512 for (i = 0; i < rv2p_code_len; i += 8) {
Michael Chan57579f72009-04-04 16:51:14 -07003513 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003514 rv2p_code++;
Michael Chan57579f72009-04-04 16:51:14 -07003515 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003516 rv2p_code++;
3517
Michael Chan57579f72009-04-04 16:51:14 -07003518 val = (i / 8) | cmd;
3519 REG_WR(bp, addr, val);
3520 }
3521
3522 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3523 for (i = 0; i < 8; i++) {
3524 u32 loc, code;
3525
3526 loc = be32_to_cpu(fw_entry->fixup[i]);
3527 if (loc && ((loc * 4) < rv2p_code_len)) {
3528 code = be32_to_cpu(*(rv2p_code + loc - 1));
3529 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3530 code = be32_to_cpu(*(rv2p_code + loc));
3531 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3532 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3533
3534 val = (loc / 2) | cmd;
3535 REG_WR(bp, addr, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003536 }
3537 }
3538
3539 /* Reset the processor, un-stall is done later. */
3540 if (rv2p_proc == RV2P_PROC1) {
3541 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3542 }
3543 else {
3544 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3545 }
Michael Chan57579f72009-04-04 16:51:14 -07003546
3547 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003548}
3549
Michael Chanaf3ee512006-11-19 14:09:25 -08003550static int
Michael Chan57579f72009-04-04 16:51:14 -07003551load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3552 const struct bnx2_mips_fw_file_entry *fw_entry)
Michael Chanb6016b72005-05-26 13:03:09 -07003553{
Michael Chan57579f72009-04-04 16:51:14 -07003554 u32 addr, len, file_offset;
3555 __be32 *data;
Michael Chanb6016b72005-05-26 13:03:09 -07003556 u32 offset;
3557 u32 val;
3558
3559 /* Halt the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003560 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003561 val |= cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003562 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3563 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
Michael Chanb6016b72005-05-26 13:03:09 -07003564
3565 /* Load the Text area. */
Michael Chan57579f72009-04-04 16:51:14 -07003566 addr = be32_to_cpu(fw_entry->text.addr);
3567 len = be32_to_cpu(fw_entry->text.len);
3568 file_offset = be32_to_cpu(fw_entry->text.offset);
3569 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3570
3571 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3572 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003573 int j;
3574
Michael Chan57579f72009-04-04 16:51:14 -07003575 for (j = 0; j < (len / 4); j++, offset += 4)
3576 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003577 }
3578
3579 /* Load the Data area. */
Michael Chan57579f72009-04-04 16:51:14 -07003580 addr = be32_to_cpu(fw_entry->data.addr);
3581 len = be32_to_cpu(fw_entry->data.len);
3582 file_offset = be32_to_cpu(fw_entry->data.offset);
3583 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3584
3585 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3586 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003587 int j;
3588
Michael Chan57579f72009-04-04 16:51:14 -07003589 for (j = 0; j < (len / 4); j++, offset += 4)
3590 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003591 }
3592
3593 /* Load the Read-Only area. */
Michael Chan57579f72009-04-04 16:51:14 -07003594 addr = be32_to_cpu(fw_entry->rodata.addr);
3595 len = be32_to_cpu(fw_entry->rodata.len);
3596 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3597 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3598
3599 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3600 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003601 int j;
3602
Michael Chan57579f72009-04-04 16:51:14 -07003603 for (j = 0; j < (len / 4); j++, offset += 4)
3604 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003605 }
3606
3607 /* Clear the pre-fetch instruction. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003608 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
Michael Chan57579f72009-04-04 16:51:14 -07003609
3610 val = be32_to_cpu(fw_entry->start_addr);
3611 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003612
3613 /* Start the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003614 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003615 val &= ~cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003616 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3617 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
Michael Chanaf3ee512006-11-19 14:09:25 -08003618
3619 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003620}
3621
Michael Chanfba9fe92006-06-12 22:21:25 -07003622static int
Michael Chanb6016b72005-05-26 13:03:09 -07003623bnx2_init_cpus(struct bnx2 *bp)
3624{
Michael Chan57579f72009-04-04 16:51:14 -07003625 const struct bnx2_mips_fw_file *mips_fw =
3626 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3627 const struct bnx2_rv2p_fw_file *rv2p_fw =
3628 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3629 int rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003630
3631 /* Initialize the RV2P processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003632 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3633 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
Michael Chanb6016b72005-05-26 13:03:09 -07003634
3635 /* Initialize the RX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003636 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003637 if (rc)
3638 goto init_cpu_err;
3639
Michael Chanb6016b72005-05-26 13:03:09 -07003640 /* Initialize the TX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003641 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003642 if (rc)
3643 goto init_cpu_err;
3644
Michael Chanb6016b72005-05-26 13:03:09 -07003645 /* Initialize the TX Patch-up Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003646 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
Michael Chanfba9fe92006-06-12 22:21:25 -07003647 if (rc)
3648 goto init_cpu_err;
3649
Michael Chanb6016b72005-05-26 13:03:09 -07003650 /* Initialize the Completion Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003651 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
Michael Chanfba9fe92006-06-12 22:21:25 -07003652 if (rc)
3653 goto init_cpu_err;
3654
Michael Chand43584c2006-11-19 14:14:35 -08003655 /* Initialize the Command Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003656 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
Michael Chan110d0ef2007-12-12 11:18:34 -08003657
Michael Chanfba9fe92006-06-12 22:21:25 -07003658init_cpu_err:
Michael Chanfba9fe92006-06-12 22:21:25 -07003659 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003660}
3661
3662static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07003663bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07003664{
3665 u16 pmcsr;
3666
3667 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3668
3669 switch (state) {
Pavel Machek829ca9a2005-09-03 15:56:56 -07003670 case PCI_D0: {
Michael Chanb6016b72005-05-26 13:03:09 -07003671 u32 val;
3672
3673 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3674 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3675 PCI_PM_CTRL_PME_STATUS);
3676
3677 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3678 /* delay required during transition out of D3hot */
3679 msleep(20);
3680
3681 val = REG_RD(bp, BNX2_EMAC_MODE);
3682 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3683 val &= ~BNX2_EMAC_MODE_MPKT;
3684 REG_WR(bp, BNX2_EMAC_MODE, val);
3685
3686 val = REG_RD(bp, BNX2_RPM_CONFIG);
3687 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3688 REG_WR(bp, BNX2_RPM_CONFIG, val);
3689 break;
3690 }
Pavel Machek829ca9a2005-09-03 15:56:56 -07003691 case PCI_D3hot: {
Michael Chanb6016b72005-05-26 13:03:09 -07003692 int i;
3693 u32 val, wol_msg;
3694
3695 if (bp->wol) {
3696 u32 advertising;
3697 u8 autoneg;
3698
3699 autoneg = bp->autoneg;
3700 advertising = bp->advertising;
3701
Michael Chan239cd342007-10-17 19:26:15 -07003702 if (bp->phy_port == PORT_TP) {
3703 bp->autoneg = AUTONEG_SPEED;
3704 bp->advertising = ADVERTISED_10baseT_Half |
3705 ADVERTISED_10baseT_Full |
3706 ADVERTISED_100baseT_Half |
3707 ADVERTISED_100baseT_Full |
3708 ADVERTISED_Autoneg;
3709 }
Michael Chanb6016b72005-05-26 13:03:09 -07003710
Michael Chan239cd342007-10-17 19:26:15 -07003711 spin_lock_bh(&bp->phy_lock);
3712 bnx2_setup_phy(bp, bp->phy_port);
3713 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003714
3715 bp->autoneg = autoneg;
3716 bp->advertising = advertising;
3717
Benjamin Li5fcaed02008-07-14 22:39:52 -07003718 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003719
3720 val = REG_RD(bp, BNX2_EMAC_MODE);
3721
3722 /* Enable port mode. */
3723 val &= ~BNX2_EMAC_MODE_PORT;
Michael Chan239cd342007-10-17 19:26:15 -07003724 val |= BNX2_EMAC_MODE_MPKT_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003725 BNX2_EMAC_MODE_ACPI_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003726 BNX2_EMAC_MODE_MPKT;
Michael Chan239cd342007-10-17 19:26:15 -07003727 if (bp->phy_port == PORT_TP)
3728 val |= BNX2_EMAC_MODE_PORT_MII;
3729 else {
3730 val |= BNX2_EMAC_MODE_PORT_GMII;
3731 if (bp->line_speed == SPEED_2500)
3732 val |= BNX2_EMAC_MODE_25G_MODE;
3733 }
Michael Chanb6016b72005-05-26 13:03:09 -07003734
3735 REG_WR(bp, BNX2_EMAC_MODE, val);
3736
3737 /* receive all multicast */
3738 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3739 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3740 0xffffffff);
3741 }
3742 REG_WR(bp, BNX2_EMAC_RX_MODE,
3743 BNX2_EMAC_RX_MODE_SORT_MODE);
3744
3745 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3746 BNX2_RPM_SORT_USER0_MC_EN;
3747 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3748 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3749 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3750 BNX2_RPM_SORT_USER0_ENA);
3751
3752 /* Need to enable EMAC and RPM for WOL. */
3753 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3754 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3755 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3756 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3757
3758 val = REG_RD(bp, BNX2_RPM_CONFIG);
3759 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3760 REG_WR(bp, BNX2_RPM_CONFIG, val);
3761
3762 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3763 }
3764 else {
3765 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3766 }
3767
David S. Millerf86e82f2008-01-21 17:15:40 -08003768 if (!(bp->flags & BNX2_FLAG_NO_WOL))
Michael Chana2f13892008-07-14 22:38:23 -07003769 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3770 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003771
3772 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3773 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3774 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3775
3776 if (bp->wol)
3777 pmcsr |= 3;
3778 }
3779 else {
3780 pmcsr |= 3;
3781 }
3782 if (bp->wol) {
3783 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3784 }
3785 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3786 pmcsr);
3787
3788 /* No more memory access after this point until
3789 * device is brought back to D0.
3790 */
3791 udelay(50);
3792 break;
3793 }
3794 default:
3795 return -EINVAL;
3796 }
3797 return 0;
3798}
3799
3800static int
3801bnx2_acquire_nvram_lock(struct bnx2 *bp)
3802{
3803 u32 val;
3804 int j;
3805
3806 /* Request access to the flash interface. */
3807 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3808 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3809 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3810 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3811 break;
3812
3813 udelay(5);
3814 }
3815
3816 if (j >= NVRAM_TIMEOUT_COUNT)
3817 return -EBUSY;
3818
3819 return 0;
3820}
3821
3822static int
3823bnx2_release_nvram_lock(struct bnx2 *bp)
3824{
3825 int j;
3826 u32 val;
3827
3828 /* Relinquish nvram interface. */
3829 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3830
3831 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3832 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3833 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3834 break;
3835
3836 udelay(5);
3837 }
3838
3839 if (j >= NVRAM_TIMEOUT_COUNT)
3840 return -EBUSY;
3841
3842 return 0;
3843}
3844
3845
3846static int
3847bnx2_enable_nvram_write(struct bnx2 *bp)
3848{
3849 u32 val;
3850
3851 val = REG_RD(bp, BNX2_MISC_CFG);
3852 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3853
Michael Chane30372c2007-07-16 18:26:23 -07003854 if (bp->flash_info->flags & BNX2_NV_WREN) {
Michael Chanb6016b72005-05-26 13:03:09 -07003855 int j;
3856
3857 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3858 REG_WR(bp, BNX2_NVM_COMMAND,
3859 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3860
3861 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3862 udelay(5);
3863
3864 val = REG_RD(bp, BNX2_NVM_COMMAND);
3865 if (val & BNX2_NVM_COMMAND_DONE)
3866 break;
3867 }
3868
3869 if (j >= NVRAM_TIMEOUT_COUNT)
3870 return -EBUSY;
3871 }
3872 return 0;
3873}
3874
3875static void
3876bnx2_disable_nvram_write(struct bnx2 *bp)
3877{
3878 u32 val;
3879
3880 val = REG_RD(bp, BNX2_MISC_CFG);
3881 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3882}
3883
3884
3885static void
3886bnx2_enable_nvram_access(struct bnx2 *bp)
3887{
3888 u32 val;
3889
3890 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3891 /* Enable both bits, even on read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003892 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003893 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3894}
3895
3896static void
3897bnx2_disable_nvram_access(struct bnx2 *bp)
3898{
3899 u32 val;
3900
3901 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3902 /* Disable both bits, even after read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003903 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003904 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3905 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3906}
3907
3908static int
3909bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3910{
3911 u32 cmd;
3912 int j;
3913
Michael Chane30372c2007-07-16 18:26:23 -07003914 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
Michael Chanb6016b72005-05-26 13:03:09 -07003915 /* Buffered flash, no erase needed */
3916 return 0;
3917
3918 /* Build an erase command */
3919 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3920 BNX2_NVM_COMMAND_DOIT;
3921
3922 /* Need to clear DONE bit separately. */
3923 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3924
3925 /* Address of the NVRAM to read from. */
3926 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3927
3928 /* Issue an erase command. */
3929 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3930
3931 /* Wait for completion. */
3932 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3933 u32 val;
3934
3935 udelay(5);
3936
3937 val = REG_RD(bp, BNX2_NVM_COMMAND);
3938 if (val & BNX2_NVM_COMMAND_DONE)
3939 break;
3940 }
3941
3942 if (j >= NVRAM_TIMEOUT_COUNT)
3943 return -EBUSY;
3944
3945 return 0;
3946}
3947
3948static int
3949bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3950{
3951 u32 cmd;
3952 int j;
3953
3954 /* Build the command word. */
3955 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3956
Michael Chane30372c2007-07-16 18:26:23 -07003957 /* Calculate an offset of a buffered flash, not needed for 5709. */
3958 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07003959 offset = ((offset / bp->flash_info->page_size) <<
3960 bp->flash_info->page_bits) +
3961 (offset % bp->flash_info->page_size);
3962 }
3963
3964 /* Need to clear DONE bit separately. */
3965 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3966
3967 /* Address of the NVRAM to read from. */
3968 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3969
3970 /* Issue a read command. */
3971 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3972
3973 /* Wait for completion. */
3974 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3975 u32 val;
3976
3977 udelay(5);
3978
3979 val = REG_RD(bp, BNX2_NVM_COMMAND);
3980 if (val & BNX2_NVM_COMMAND_DONE) {
Al Virob491edd2007-12-22 19:44:51 +00003981 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3982 memcpy(ret_val, &v, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07003983 break;
3984 }
3985 }
3986 if (j >= NVRAM_TIMEOUT_COUNT)
3987 return -EBUSY;
3988
3989 return 0;
3990}
3991
3992
3993static int
3994bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3995{
Al Virob491edd2007-12-22 19:44:51 +00003996 u32 cmd;
3997 __be32 val32;
Michael Chanb6016b72005-05-26 13:03:09 -07003998 int j;
3999
4000 /* Build the command word. */
4001 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4002
Michael Chane30372c2007-07-16 18:26:23 -07004003 /* Calculate an offset of a buffered flash, not needed for 5709. */
4004 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07004005 offset = ((offset / bp->flash_info->page_size) <<
4006 bp->flash_info->page_bits) +
4007 (offset % bp->flash_info->page_size);
4008 }
4009
4010 /* Need to clear DONE bit separately. */
4011 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4012
4013 memcpy(&val32, val, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004014
4015 /* Write the data. */
Al Virob491edd2007-12-22 19:44:51 +00004016 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
Michael Chanb6016b72005-05-26 13:03:09 -07004017
4018 /* Address of the NVRAM to write to. */
4019 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4020
4021 /* Issue the write command. */
4022 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4023
4024 /* Wait for completion. */
4025 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4026 udelay(5);
4027
4028 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4029 break;
4030 }
4031 if (j >= NVRAM_TIMEOUT_COUNT)
4032 return -EBUSY;
4033
4034 return 0;
4035}
4036
4037static int
4038bnx2_init_nvram(struct bnx2 *bp)
4039{
4040 u32 val;
Michael Chane30372c2007-07-16 18:26:23 -07004041 int j, entry_count, rc = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07004042 struct flash_spec *flash;
4043
Michael Chane30372c2007-07-16 18:26:23 -07004044 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4045 bp->flash_info = &flash_5709;
4046 goto get_flash_size;
4047 }
4048
Michael Chanb6016b72005-05-26 13:03:09 -07004049 /* Determine the selected interface. */
4050 val = REG_RD(bp, BNX2_NVM_CFG1);
4051
Denis Chengff8ac602007-09-02 18:30:18 +08004052 entry_count = ARRAY_SIZE(flash_table);
Michael Chanb6016b72005-05-26 13:03:09 -07004053
Michael Chanb6016b72005-05-26 13:03:09 -07004054 if (val & 0x40000000) {
4055
4056 /* Flash interface has been reconfigured */
4057 for (j = 0, flash = &flash_table[0]; j < entry_count;
Michael Chan37137702005-11-04 08:49:17 -08004058 j++, flash++) {
4059 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4060 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004061 bp->flash_info = flash;
4062 break;
4063 }
4064 }
4065 }
4066 else {
Michael Chan37137702005-11-04 08:49:17 -08004067 u32 mask;
Michael Chanb6016b72005-05-26 13:03:09 -07004068 /* Not yet been reconfigured */
4069
Michael Chan37137702005-11-04 08:49:17 -08004070 if (val & (1 << 23))
4071 mask = FLASH_BACKUP_STRAP_MASK;
4072 else
4073 mask = FLASH_STRAP_MASK;
4074
Michael Chanb6016b72005-05-26 13:03:09 -07004075 for (j = 0, flash = &flash_table[0]; j < entry_count;
4076 j++, flash++) {
4077
Michael Chan37137702005-11-04 08:49:17 -08004078 if ((val & mask) == (flash->strapping & mask)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004079 bp->flash_info = flash;
4080
4081 /* Request access to the flash interface. */
4082 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4083 return rc;
4084
4085 /* Enable access to flash interface */
4086 bnx2_enable_nvram_access(bp);
4087
4088 /* Reconfigure the flash interface */
4089 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4090 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4091 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4092 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4093
4094 /* Disable access to flash interface */
4095 bnx2_disable_nvram_access(bp);
4096 bnx2_release_nvram_lock(bp);
4097
4098 break;
4099 }
4100 }
4101 } /* if (val & 0x40000000) */
4102
4103 if (j == entry_count) {
4104 bp->flash_info = NULL;
John W. Linville2f23c522005-11-10 12:57:33 -08004105 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
Michael Chan1122db72006-01-23 16:11:42 -08004106 return -ENODEV;
Michael Chanb6016b72005-05-26 13:03:09 -07004107 }
4108
Michael Chane30372c2007-07-16 18:26:23 -07004109get_flash_size:
Michael Chan2726d6e2008-01-29 21:35:05 -08004110 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
Michael Chan1122db72006-01-23 16:11:42 -08004111 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4112 if (val)
4113 bp->flash_size = val;
4114 else
4115 bp->flash_size = bp->flash_info->total_size;
4116
Michael Chanb6016b72005-05-26 13:03:09 -07004117 return rc;
4118}
4119
4120static int
4121bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4122 int buf_size)
4123{
4124 int rc = 0;
4125 u32 cmd_flags, offset32, len32, extra;
4126
4127 if (buf_size == 0)
4128 return 0;
4129
4130 /* Request access to the flash interface. */
4131 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4132 return rc;
4133
4134 /* Enable access to flash interface */
4135 bnx2_enable_nvram_access(bp);
4136
4137 len32 = buf_size;
4138 offset32 = offset;
4139 extra = 0;
4140
4141 cmd_flags = 0;
4142
4143 if (offset32 & 3) {
4144 u8 buf[4];
4145 u32 pre_len;
4146
4147 offset32 &= ~3;
4148 pre_len = 4 - (offset & 3);
4149
4150 if (pre_len >= len32) {
4151 pre_len = len32;
4152 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4153 BNX2_NVM_COMMAND_LAST;
4154 }
4155 else {
4156 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4157 }
4158
4159 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4160
4161 if (rc)
4162 return rc;
4163
4164 memcpy(ret_buf, buf + (offset & 3), pre_len);
4165
4166 offset32 += 4;
4167 ret_buf += pre_len;
4168 len32 -= pre_len;
4169 }
4170 if (len32 & 3) {
4171 extra = 4 - (len32 & 3);
4172 len32 = (len32 + 4) & ~3;
4173 }
4174
4175 if (len32 == 4) {
4176 u8 buf[4];
4177
4178 if (cmd_flags)
4179 cmd_flags = BNX2_NVM_COMMAND_LAST;
4180 else
4181 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4182 BNX2_NVM_COMMAND_LAST;
4183
4184 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4185
4186 memcpy(ret_buf, buf, 4 - extra);
4187 }
4188 else if (len32 > 0) {
4189 u8 buf[4];
4190
4191 /* Read the first word. */
4192 if (cmd_flags)
4193 cmd_flags = 0;
4194 else
4195 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4196
4197 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4198
4199 /* Advance to the next dword. */
4200 offset32 += 4;
4201 ret_buf += 4;
4202 len32 -= 4;
4203
4204 while (len32 > 4 && rc == 0) {
4205 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4206
4207 /* Advance to the next dword. */
4208 offset32 += 4;
4209 ret_buf += 4;
4210 len32 -= 4;
4211 }
4212
4213 if (rc)
4214 return rc;
4215
4216 cmd_flags = BNX2_NVM_COMMAND_LAST;
4217 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4218
4219 memcpy(ret_buf, buf, 4 - extra);
4220 }
4221
4222 /* Disable access to flash interface */
4223 bnx2_disable_nvram_access(bp);
4224
4225 bnx2_release_nvram_lock(bp);
4226
4227 return rc;
4228}
4229
4230static int
4231bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4232 int buf_size)
4233{
4234 u32 written, offset32, len32;
Michael Chane6be7632007-01-08 19:56:13 -08004235 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004236 int rc = 0;
4237 int align_start, align_end;
4238
4239 buf = data_buf;
4240 offset32 = offset;
4241 len32 = buf_size;
4242 align_start = align_end = 0;
4243
4244 if ((align_start = (offset32 & 3))) {
4245 offset32 &= ~3;
Michael Chanc8738792007-03-30 14:53:06 -07004246 len32 += align_start;
4247 if (len32 < 4)
4248 len32 = 4;
Michael Chanb6016b72005-05-26 13:03:09 -07004249 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4250 return rc;
4251 }
4252
4253 if (len32 & 3) {
Michael Chanc8738792007-03-30 14:53:06 -07004254 align_end = 4 - (len32 & 3);
4255 len32 += align_end;
4256 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4257 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004258 }
4259
4260 if (align_start || align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004261 align_buf = kmalloc(len32, GFP_KERNEL);
4262 if (align_buf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004263 return -ENOMEM;
4264 if (align_start) {
Michael Chane6be7632007-01-08 19:56:13 -08004265 memcpy(align_buf, start, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004266 }
4267 if (align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004268 memcpy(align_buf + len32 - 4, end, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004269 }
Michael Chane6be7632007-01-08 19:56:13 -08004270 memcpy(align_buf + align_start, data_buf, buf_size);
4271 buf = align_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004272 }
4273
Michael Chane30372c2007-07-16 18:26:23 -07004274 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanae181bc2006-05-22 16:39:20 -07004275 flash_buffer = kmalloc(264, GFP_KERNEL);
4276 if (flash_buffer == NULL) {
4277 rc = -ENOMEM;
4278 goto nvram_write_end;
4279 }
4280 }
4281
Michael Chanb6016b72005-05-26 13:03:09 -07004282 written = 0;
4283 while ((written < len32) && (rc == 0)) {
4284 u32 page_start, page_end, data_start, data_end;
4285 u32 addr, cmd_flags;
4286 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07004287
4288 /* Find the page_start addr */
4289 page_start = offset32 + written;
4290 page_start -= (page_start % bp->flash_info->page_size);
4291 /* Find the page_end addr */
4292 page_end = page_start + bp->flash_info->page_size;
4293 /* Find the data_start addr */
4294 data_start = (written == 0) ? offset32 : page_start;
4295 /* Find the data_end addr */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004296 data_end = (page_end > offset32 + len32) ?
Michael Chanb6016b72005-05-26 13:03:09 -07004297 (offset32 + len32) : page_end;
4298
4299 /* Request access to the flash interface. */
4300 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4301 goto nvram_write_end;
4302
4303 /* Enable access to flash interface */
4304 bnx2_enable_nvram_access(bp);
4305
4306 cmd_flags = BNX2_NVM_COMMAND_FIRST;
Michael Chane30372c2007-07-16 18:26:23 -07004307 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004308 int j;
4309
4310 /* Read the whole page into the buffer
4311 * (non-buffer flash only) */
4312 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4313 if (j == (bp->flash_info->page_size - 4)) {
4314 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4315 }
4316 rc = bnx2_nvram_read_dword(bp,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004317 page_start + j,
4318 &flash_buffer[j],
Michael Chanb6016b72005-05-26 13:03:09 -07004319 cmd_flags);
4320
4321 if (rc)
4322 goto nvram_write_end;
4323
4324 cmd_flags = 0;
4325 }
4326 }
4327
4328 /* Enable writes to flash interface (unlock write-protect) */
4329 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4330 goto nvram_write_end;
4331
Michael Chanb6016b72005-05-26 13:03:09 -07004332 /* Loop to write back the buffer data from page_start to
4333 * data_start */
4334 i = 0;
Michael Chane30372c2007-07-16 18:26:23 -07004335 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanc8738792007-03-30 14:53:06 -07004336 /* Erase the page */
4337 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4338 goto nvram_write_end;
4339
4340 /* Re-enable the write again for the actual write */
4341 bnx2_enable_nvram_write(bp);
4342
Michael Chanb6016b72005-05-26 13:03:09 -07004343 for (addr = page_start; addr < data_start;
4344 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004345
Michael Chanb6016b72005-05-26 13:03:09 -07004346 rc = bnx2_nvram_write_dword(bp, addr,
4347 &flash_buffer[i], cmd_flags);
4348
4349 if (rc != 0)
4350 goto nvram_write_end;
4351
4352 cmd_flags = 0;
4353 }
4354 }
4355
4356 /* Loop to write the new data from data_start to data_end */
Michael Chanbae25762006-05-22 16:38:38 -07004357 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
Michael Chanb6016b72005-05-26 13:03:09 -07004358 if ((addr == page_end - 4) ||
Michael Chane30372c2007-07-16 18:26:23 -07004359 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
Michael Chanb6016b72005-05-26 13:03:09 -07004360 (addr == data_end - 4))) {
4361
4362 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4363 }
4364 rc = bnx2_nvram_write_dword(bp, addr, buf,
4365 cmd_flags);
4366
4367 if (rc != 0)
4368 goto nvram_write_end;
4369
4370 cmd_flags = 0;
4371 buf += 4;
4372 }
4373
4374 /* Loop to write back the buffer data from data_end
4375 * to page_end */
Michael Chane30372c2007-07-16 18:26:23 -07004376 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004377 for (addr = data_end; addr < page_end;
4378 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004379
Michael Chanb6016b72005-05-26 13:03:09 -07004380 if (addr == page_end-4) {
4381 cmd_flags = BNX2_NVM_COMMAND_LAST;
4382 }
4383 rc = bnx2_nvram_write_dword(bp, addr,
4384 &flash_buffer[i], cmd_flags);
4385
4386 if (rc != 0)
4387 goto nvram_write_end;
4388
4389 cmd_flags = 0;
4390 }
4391 }
4392
4393 /* Disable writes to flash interface (lock write-protect) */
4394 bnx2_disable_nvram_write(bp);
4395
4396 /* Disable access to flash interface */
4397 bnx2_disable_nvram_access(bp);
4398 bnx2_release_nvram_lock(bp);
4399
4400 /* Increment written */
4401 written += data_end - data_start;
4402 }
4403
4404nvram_write_end:
Michael Chane6be7632007-01-08 19:56:13 -08004405 kfree(flash_buffer);
4406 kfree(align_buf);
Michael Chanb6016b72005-05-26 13:03:09 -07004407 return rc;
4408}
4409
Michael Chan0d8a6572007-07-07 22:49:43 -07004410static void
Michael Chan7c62e832008-07-14 22:39:03 -07004411bnx2_init_fw_cap(struct bnx2 *bp)
Michael Chan0d8a6572007-07-07 22:49:43 -07004412{
Michael Chan7c62e832008-07-14 22:39:03 -07004413 u32 val, sig = 0;
Michael Chan0d8a6572007-07-07 22:49:43 -07004414
Michael Chan583c28e2008-01-21 19:51:35 -08004415 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan7c62e832008-07-14 22:39:03 -07004416 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4417
4418 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4419 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
Michael Chan0d8a6572007-07-07 22:49:43 -07004420
Michael Chan2726d6e2008-01-29 21:35:05 -08004421 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07004422 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4423 return;
4424
Michael Chan7c62e832008-07-14 22:39:03 -07004425 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4426 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4427 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4428 }
4429
4430 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4431 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4432 u32 link;
4433
Michael Chan583c28e2008-01-21 19:51:35 -08004434 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan0d8a6572007-07-07 22:49:43 -07004435
Michael Chan7c62e832008-07-14 22:39:03 -07004436 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4437 if (link & BNX2_LINK_STATUS_SERDES_LINK)
Michael Chan0d8a6572007-07-07 22:49:43 -07004438 bp->phy_port = PORT_FIBRE;
4439 else
4440 bp->phy_port = PORT_TP;
Michael Chan489310a2007-10-10 16:16:31 -07004441
Michael Chan7c62e832008-07-14 22:39:03 -07004442 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4443 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
Michael Chan0d8a6572007-07-07 22:49:43 -07004444 }
Michael Chan7c62e832008-07-14 22:39:03 -07004445
4446 if (netif_running(bp->dev) && sig)
4447 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
Michael Chan0d8a6572007-07-07 22:49:43 -07004448}
4449
Michael Chanb4b36042007-12-20 19:59:30 -08004450static void
4451bnx2_setup_msix_tbl(struct bnx2 *bp)
4452{
4453 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4454
4455 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4456 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4457}
4458
Michael Chanb6016b72005-05-26 13:03:09 -07004459static int
4460bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4461{
4462 u32 val;
4463 int i, rc = 0;
Michael Chan489310a2007-10-10 16:16:31 -07004464 u8 old_port;
Michael Chanb6016b72005-05-26 13:03:09 -07004465
4466 /* Wait for the current PCI transaction to complete before
4467 * issuing a reset. */
4468 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4469 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4470 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4471 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4472 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4473 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4474 udelay(5);
4475
Michael Chanb090ae22006-01-23 16:07:10 -08004476 /* Wait for the firmware to tell us it is ok to issue a reset. */
Michael Chana2f13892008-07-14 22:38:23 -07004477 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
Michael Chanb090ae22006-01-23 16:07:10 -08004478
Michael Chanb6016b72005-05-26 13:03:09 -07004479 /* Deposit a driver reset signature so the firmware knows that
4480 * this is a soft reset. */
Michael Chan2726d6e2008-01-29 21:35:05 -08004481 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4482 BNX2_DRV_RESET_SIGNATURE_MAGIC);
Michael Chanb6016b72005-05-26 13:03:09 -07004483
Michael Chanb6016b72005-05-26 13:03:09 -07004484 /* Do a dummy read to force the chip to complete all current transaction
4485 * before we issue a reset. */
4486 val = REG_RD(bp, BNX2_MISC_ID);
4487
Michael Chan234754d2006-11-19 14:11:41 -08004488 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4489 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4490 REG_RD(bp, BNX2_MISC_COMMAND);
4491 udelay(5);
Michael Chanb6016b72005-05-26 13:03:09 -07004492
Michael Chan234754d2006-11-19 14:11:41 -08004493 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4494 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
Michael Chanb6016b72005-05-26 13:03:09 -07004495
Michael Chan234754d2006-11-19 14:11:41 -08004496 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004497
Michael Chan234754d2006-11-19 14:11:41 -08004498 } else {
4499 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4500 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4501 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4502
4503 /* Chip reset. */
4504 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4505
Michael Chan594a9df2007-08-28 15:39:42 -07004506 /* Reading back any register after chip reset will hang the
4507 * bus on 5706 A0 and A1. The msleep below provides plenty
4508 * of margin for write posting.
4509 */
Michael Chan234754d2006-11-19 14:11:41 -08004510 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
Arjan van de Ven8e545882007-08-28 14:34:43 -07004511 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4512 msleep(20);
Michael Chanb6016b72005-05-26 13:03:09 -07004513
Michael Chan234754d2006-11-19 14:11:41 -08004514 /* Reset takes approximate 30 usec */
4515 for (i = 0; i < 10; i++) {
4516 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4517 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4518 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4519 break;
4520 udelay(10);
4521 }
4522
4523 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4524 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4525 printk(KERN_ERR PFX "Chip reset did not complete\n");
4526 return -EBUSY;
4527 }
Michael Chanb6016b72005-05-26 13:03:09 -07004528 }
4529
4530 /* Make sure byte swapping is properly configured. */
4531 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4532 if (val != 0x01020304) {
4533 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4534 return -ENODEV;
4535 }
4536
Michael Chanb6016b72005-05-26 13:03:09 -07004537 /* Wait for the firmware to finish its initialization. */
Michael Chana2f13892008-07-14 22:38:23 -07004538 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
Michael Chanb090ae22006-01-23 16:07:10 -08004539 if (rc)
4540 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004541
Michael Chan0d8a6572007-07-07 22:49:43 -07004542 spin_lock_bh(&bp->phy_lock);
Michael Chan489310a2007-10-10 16:16:31 -07004543 old_port = bp->phy_port;
Michael Chan7c62e832008-07-14 22:39:03 -07004544 bnx2_init_fw_cap(bp);
Michael Chan583c28e2008-01-21 19:51:35 -08004545 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4546 old_port != bp->phy_port)
Michael Chan0d8a6572007-07-07 22:49:43 -07004547 bnx2_set_default_remote_link(bp);
4548 spin_unlock_bh(&bp->phy_lock);
4549
Michael Chanb6016b72005-05-26 13:03:09 -07004550 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4551 /* Adjust the voltage regular to two steps lower. The default
4552 * of this register is 0x0000000e. */
4553 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4554
4555 /* Remove bad rbuf memory from the free pool. */
4556 rc = bnx2_alloc_bad_rbuf(bp);
4557 }
4558
David S. Millerf86e82f2008-01-21 17:15:40 -08004559 if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08004560 bnx2_setup_msix_tbl(bp);
4561
Michael Chanb6016b72005-05-26 13:03:09 -07004562 return rc;
4563}
4564
4565static int
4566bnx2_init_chip(struct bnx2 *bp)
4567{
Michael Chand8026d92008-11-12 16:02:20 -08004568 u32 val, mtu;
Michael Chanb4b36042007-12-20 19:59:30 -08004569 int rc, i;
Michael Chanb6016b72005-05-26 13:03:09 -07004570
4571 /* Make sure the interrupt is not active. */
4572 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4573
4574 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4575 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4576#ifdef __BIG_ENDIAN
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004577 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004578#endif
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004579 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004580 DMA_READ_CHANS << 12 |
4581 DMA_WRITE_CHANS << 16;
4582
4583 val |= (0x2 << 20) | (1 << 11);
4584
David S. Millerf86e82f2008-01-21 17:15:40 -08004585 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
Michael Chanb6016b72005-05-26 13:03:09 -07004586 val |= (1 << 23);
4587
4588 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08004589 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
Michael Chanb6016b72005-05-26 13:03:09 -07004590 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4591
4592 REG_WR(bp, BNX2_DMA_CONFIG, val);
4593
4594 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4595 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4596 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4597 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4598 }
4599
David S. Millerf86e82f2008-01-21 17:15:40 -08004600 if (bp->flags & BNX2_FLAG_PCIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07004601 u16 val16;
4602
4603 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4604 &val16);
4605 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4606 val16 & ~PCI_X_CMD_ERO);
4607 }
4608
4609 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4610 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4611 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4612 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4613
4614 /* Initialize context mapping and zero out the quick contexts. The
4615 * context block must have already been enabled. */
Michael Chan641bdcd2007-06-04 21:22:24 -07004616 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4617 rc = bnx2_init_5709_context(bp);
4618 if (rc)
4619 return rc;
4620 } else
Michael Chan59b47d82006-11-19 14:10:45 -08004621 bnx2_init_context(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004622
Michael Chanfba9fe92006-06-12 22:21:25 -07004623 if ((rc = bnx2_init_cpus(bp)) != 0)
4624 return rc;
4625
Michael Chanb6016b72005-05-26 13:03:09 -07004626 bnx2_init_nvram(bp);
4627
Benjamin Li5fcaed02008-07-14 22:39:52 -07004628 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004629
4630 val = REG_RD(bp, BNX2_MQ_CONFIG);
4631 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4632 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
Michael Chan68c9f752007-04-24 15:35:53 -07004633 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4634 val |= BNX2_MQ_CONFIG_HALT_DIS;
4635
Michael Chanb6016b72005-05-26 13:03:09 -07004636 REG_WR(bp, BNX2_MQ_CONFIG, val);
4637
4638 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4639 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4640 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4641
4642 val = (BCM_PAGE_BITS - 8) << 24;
4643 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4644
4645 /* Configure page size. */
4646 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4647 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4648 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4649 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4650
4651 val = bp->mac_addr[0] +
4652 (bp->mac_addr[1] << 8) +
4653 (bp->mac_addr[2] << 16) +
4654 bp->mac_addr[3] +
4655 (bp->mac_addr[4] << 8) +
4656 (bp->mac_addr[5] << 16);
4657 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4658
4659 /* Program the MTU. Also include 4 bytes for CRC32. */
Michael Chand8026d92008-11-12 16:02:20 -08004660 mtu = bp->dev->mtu;
4661 val = mtu + ETH_HLEN + ETH_FCS_LEN;
Michael Chanb6016b72005-05-26 13:03:09 -07004662 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4663 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4664 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4665
Michael Chand8026d92008-11-12 16:02:20 -08004666 if (mtu < 1500)
4667 mtu = 1500;
4668
4669 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4670 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4671 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4672
Michael Chanb4b36042007-12-20 19:59:30 -08004673 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4674 bp->bnx2_napi[i].last_status_idx = 0;
4675
Michael Chanefba0182008-12-03 00:36:15 -08004676 bp->idle_chk_status_idx = 0xffff;
4677
Michael Chanb6016b72005-05-26 13:03:09 -07004678 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4679
4680 /* Set up how to generate a link change interrupt. */
4681 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4682
4683 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4684 (u64) bp->status_blk_mapping & 0xffffffff);
4685 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4686
4687 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4688 (u64) bp->stats_blk_mapping & 0xffffffff);
4689 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4690 (u64) bp->stats_blk_mapping >> 32);
4691
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004692 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
Michael Chanb6016b72005-05-26 13:03:09 -07004693 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4694
4695 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4696 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4697
4698 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4699 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4700
4701 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4702
4703 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4704
4705 REG_WR(bp, BNX2_HC_COM_TICKS,
4706 (bp->com_ticks_int << 16) | bp->com_ticks);
4707
4708 REG_WR(bp, BNX2_HC_CMD_TICKS,
4709 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4710
Michael Chan02537b062007-06-04 21:24:07 -07004711 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4712 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4713 else
Michael Chan7ea69202007-07-16 18:27:10 -07004714 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004715 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4716
4717 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004718 val = BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004719 else {
Michael Chan8e6a72c2007-05-03 13:24:48 -07004720 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4721 BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004722 }
4723
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004724 if (bp->irq_nvecs > 1) {
Michael Chanc76c0472007-12-20 20:01:19 -08004725 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4726 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4727
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004728 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4729 }
4730
4731 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4732 val |= BNX2_HC_CONFIG_ONE_SHOT;
4733
4734 REG_WR(bp, BNX2_HC_CONFIG, val);
4735
4736 for (i = 1; i < bp->irq_nvecs; i++) {
4737 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4738 BNX2_HC_SB_CONFIG_1;
4739
Michael Chan6f743ca2008-01-29 21:34:08 -08004740 REG_WR(bp, base,
Michael Chanc76c0472007-12-20 20:01:19 -08004741 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004742 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
Michael Chanc76c0472007-12-20 20:01:19 -08004743 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4744
Michael Chan6f743ca2008-01-29 21:34:08 -08004745 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004746 (bp->tx_quick_cons_trip_int << 16) |
4747 bp->tx_quick_cons_trip);
4748
Michael Chan6f743ca2008-01-29 21:34:08 -08004749 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004750 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4751
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004752 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4753 (bp->rx_quick_cons_trip_int << 16) |
4754 bp->rx_quick_cons_trip);
4755
4756 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4757 (bp->rx_ticks_int << 16) | bp->rx_ticks);
Michael Chanc76c0472007-12-20 20:01:19 -08004758 }
4759
Michael Chanb6016b72005-05-26 13:03:09 -07004760 /* Clear internal stats counters. */
4761 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4762
Michael Chanda3e4fb2007-05-03 13:24:23 -07004763 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
Michael Chanb6016b72005-05-26 13:03:09 -07004764
4765 /* Initialize the receive filter. */
4766 bnx2_set_rx_mode(bp->dev);
4767
Michael Chan0aa38df2007-06-04 21:23:06 -07004768 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4769 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4770 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4771 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4772 }
Michael Chanb090ae22006-01-23 16:07:10 -08004773 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
Michael Chana2f13892008-07-14 22:38:23 -07004774 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004775
Michael Chandf149d72007-07-07 22:51:36 -07004776 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
Michael Chanb6016b72005-05-26 13:03:09 -07004777 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4778
4779 udelay(20);
4780
Michael Chanbf5295b2006-03-23 01:11:56 -08004781 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4782
Michael Chanb090ae22006-01-23 16:07:10 -08004783 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004784}
4785
Michael Chan59b47d82006-11-19 14:10:45 -08004786static void
Michael Chanc76c0472007-12-20 20:01:19 -08004787bnx2_clear_ring_states(struct bnx2 *bp)
4788{
4789 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07004790 struct bnx2_tx_ring_info *txr;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004791 struct bnx2_rx_ring_info *rxr;
Michael Chanc76c0472007-12-20 20:01:19 -08004792 int i;
4793
4794 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4795 bnapi = &bp->bnx2_napi[i];
Michael Chan35e90102008-06-19 16:37:42 -07004796 txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004797 rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08004798
Michael Chan35e90102008-06-19 16:37:42 -07004799 txr->tx_cons = 0;
4800 txr->hw_tx_cons = 0;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004801 rxr->rx_prod_bseq = 0;
4802 rxr->rx_prod = 0;
4803 rxr->rx_cons = 0;
4804 rxr->rx_pg_prod = 0;
4805 rxr->rx_pg_cons = 0;
Michael Chanc76c0472007-12-20 20:01:19 -08004806 }
4807}
4808
4809static void
Michael Chan35e90102008-06-19 16:37:42 -07004810bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
Michael Chan59b47d82006-11-19 14:10:45 -08004811{
4812 u32 val, offset0, offset1, offset2, offset3;
Michael Chan62a83132008-01-29 21:35:40 -08004813 u32 cid_addr = GET_CID_ADDR(cid);
Michael Chan59b47d82006-11-19 14:10:45 -08004814
4815 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4816 offset0 = BNX2_L2CTX_TYPE_XI;
4817 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4818 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4819 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4820 } else {
4821 offset0 = BNX2_L2CTX_TYPE;
4822 offset1 = BNX2_L2CTX_CMD_TYPE;
4823 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4824 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4825 }
4826 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
Michael Chan62a83132008-01-29 21:35:40 -08004827 bnx2_ctx_wr(bp, cid_addr, offset0, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004828
4829 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
Michael Chan62a83132008-01-29 21:35:40 -08004830 bnx2_ctx_wr(bp, cid_addr, offset1, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004831
Michael Chan35e90102008-06-19 16:37:42 -07004832 val = (u64) txr->tx_desc_mapping >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004833 bnx2_ctx_wr(bp, cid_addr, offset2, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004834
Michael Chan35e90102008-06-19 16:37:42 -07004835 val = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004836 bnx2_ctx_wr(bp, cid_addr, offset3, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004837}
Michael Chanb6016b72005-05-26 13:03:09 -07004838
4839static void
Michael Chan35e90102008-06-19 16:37:42 -07004840bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
Michael Chanb6016b72005-05-26 13:03:09 -07004841{
4842 struct tx_bd *txbd;
Michael Chanc76c0472007-12-20 20:01:19 -08004843 u32 cid = TX_CID;
4844 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07004845 struct bnx2_tx_ring_info *txr;
Michael Chanc76c0472007-12-20 20:01:19 -08004846
Michael Chan35e90102008-06-19 16:37:42 -07004847 bnapi = &bp->bnx2_napi[ring_num];
4848 txr = &bnapi->tx_ring;
4849
4850 if (ring_num == 0)
4851 cid = TX_CID;
4852 else
4853 cid = TX_TSS_CID + ring_num - 1;
Michael Chanb6016b72005-05-26 13:03:09 -07004854
Michael Chan2f8af122006-08-15 01:39:10 -07004855 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4856
Michael Chan35e90102008-06-19 16:37:42 -07004857 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004858
Michael Chan35e90102008-06-19 16:37:42 -07004859 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4860 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chanb6016b72005-05-26 13:03:09 -07004861
Michael Chan35e90102008-06-19 16:37:42 -07004862 txr->tx_prod = 0;
4863 txr->tx_prod_bseq = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004864
Michael Chan35e90102008-06-19 16:37:42 -07004865 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4866 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
Michael Chanb6016b72005-05-26 13:03:09 -07004867
Michael Chan35e90102008-06-19 16:37:42 -07004868 bnx2_init_tx_context(bp, cid, txr);
Michael Chanb6016b72005-05-26 13:03:09 -07004869}
4870
4871static void
Michael Chan5d5d0012007-12-12 11:17:43 -08004872bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4873 int num_rings)
Michael Chanb6016b72005-05-26 13:03:09 -07004874{
Michael Chanb6016b72005-05-26 13:03:09 -07004875 int i;
Michael Chan5d5d0012007-12-12 11:17:43 -08004876 struct rx_bd *rxbd;
Michael Chanb6016b72005-05-26 13:03:09 -07004877
Michael Chan5d5d0012007-12-12 11:17:43 -08004878 for (i = 0; i < num_rings; i++) {
Michael Chan13daffa2006-03-20 17:49:20 -08004879 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07004880
Michael Chan5d5d0012007-12-12 11:17:43 -08004881 rxbd = &rx_ring[i][0];
Michael Chan13daffa2006-03-20 17:49:20 -08004882 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
Michael Chan5d5d0012007-12-12 11:17:43 -08004883 rxbd->rx_bd_len = buf_size;
Michael Chan13daffa2006-03-20 17:49:20 -08004884 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4885 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004886 if (i == (num_rings - 1))
Michael Chan13daffa2006-03-20 17:49:20 -08004887 j = 0;
4888 else
4889 j = i + 1;
Michael Chan5d5d0012007-12-12 11:17:43 -08004890 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4891 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
Michael Chan13daffa2006-03-20 17:49:20 -08004892 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004893}
4894
4895static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07004896bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
Michael Chan5d5d0012007-12-12 11:17:43 -08004897{
4898 int i;
4899 u16 prod, ring_prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07004900 u32 cid, rx_cid_addr, val;
4901 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4902 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chan5d5d0012007-12-12 11:17:43 -08004903
Michael Chanbb4f98a2008-06-19 16:38:19 -07004904 if (ring_num == 0)
4905 cid = RX_CID;
4906 else
4907 cid = RX_RSS_CID + ring_num - 1;
4908
4909 rx_cid_addr = GET_CID_ADDR(cid);
4910
4911 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
Michael Chan5d5d0012007-12-12 11:17:43 -08004912 bp->rx_buf_use_size, bp->rx_max_ring);
4913
Michael Chanbb4f98a2008-06-19 16:38:19 -07004914 bnx2_init_rx_context(bp, cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08004915
4916 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4917 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4918 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4919 }
4920
Michael Chan62a83132008-01-29 21:35:40 -08004921 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
Michael Chan47bf4242007-12-12 11:19:12 -08004922 if (bp->rx_pg_ring_size) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004923 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4924 rxr->rx_pg_desc_mapping,
Michael Chan47bf4242007-12-12 11:19:12 -08004925 PAGE_SIZE, bp->rx_max_pg_ring);
4926 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
Michael Chan62a83132008-01-29 21:35:40 -08004927 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4928 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004929 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
Michael Chan47bf4242007-12-12 11:19:12 -08004930
Michael Chanbb4f98a2008-06-19 16:38:19 -07004931 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004932 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004933
Michael Chanbb4f98a2008-06-19 16:38:19 -07004934 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004935 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004936
4937 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4938 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4939 }
Michael Chanb6016b72005-05-26 13:03:09 -07004940
Michael Chanbb4f98a2008-06-19 16:38:19 -07004941 val = (u64) rxr->rx_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004942 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004943
Michael Chanbb4f98a2008-06-19 16:38:19 -07004944 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004945 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004946
Michael Chanbb4f98a2008-06-19 16:38:19 -07004947 ring_prod = prod = rxr->rx_pg_prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004948 for (i = 0; i < bp->rx_pg_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004949 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
Michael Chan47bf4242007-12-12 11:19:12 -08004950 break;
4951 prod = NEXT_RX_BD(prod);
4952 ring_prod = RX_PG_RING_IDX(prod);
4953 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07004954 rxr->rx_pg_prod = prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004955
Michael Chanbb4f98a2008-06-19 16:38:19 -07004956 ring_prod = prod = rxr->rx_prod;
Michael Chan236b6392006-03-20 17:49:02 -08004957 for (i = 0; i < bp->rx_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07004958 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
Michael Chanb6016b72005-05-26 13:03:09 -07004959 break;
Michael Chanb6016b72005-05-26 13:03:09 -07004960 prod = NEXT_RX_BD(prod);
4961 ring_prod = RX_RING_IDX(prod);
4962 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07004963 rxr->rx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07004964
Michael Chanbb4f98a2008-06-19 16:38:19 -07004965 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4966 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4967 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
Michael Chanb6016b72005-05-26 13:03:09 -07004968
Michael Chanbb4f98a2008-06-19 16:38:19 -07004969 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4970 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4971
4972 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07004973}
4974
Michael Chan35e90102008-06-19 16:37:42 -07004975static void
4976bnx2_init_all_rings(struct bnx2 *bp)
4977{
4978 int i;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004979 u32 val;
Michael Chan35e90102008-06-19 16:37:42 -07004980
4981 bnx2_clear_ring_states(bp);
4982
4983 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4984 for (i = 0; i < bp->num_tx_rings; i++)
4985 bnx2_init_tx_ring(bp, i);
4986
4987 if (bp->num_tx_rings > 1)
4988 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4989 (TX_TSS_CID << 7));
4990
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004991 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4992 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4993
Michael Chanbb4f98a2008-06-19 16:38:19 -07004994 for (i = 0; i < bp->num_rx_rings; i++)
4995 bnx2_init_rx_ring(bp, i);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004996
4997 if (bp->num_rx_rings > 1) {
4998 u32 tbl_32;
4999 u8 *tbl = (u8 *) &tbl_32;
5000
5001 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5002 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5003
5004 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5005 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5006 if ((i % 4) == 3)
5007 bnx2_reg_wr_ind(bp,
5008 BNX2_RXP_SCRATCH_RSS_TBL + i,
5009 cpu_to_be32(tbl_32));
5010 }
5011
5012 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5013 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5014
5015 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5016
5017 }
Michael Chan35e90102008-06-19 16:37:42 -07005018}
5019
Michael Chan5d5d0012007-12-12 11:17:43 -08005020static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
Michael Chan13daffa2006-03-20 17:49:20 -08005021{
Michael Chan5d5d0012007-12-12 11:17:43 -08005022 u32 max, num_rings = 1;
Michael Chan13daffa2006-03-20 17:49:20 -08005023
Michael Chan5d5d0012007-12-12 11:17:43 -08005024 while (ring_size > MAX_RX_DESC_CNT) {
5025 ring_size -= MAX_RX_DESC_CNT;
Michael Chan13daffa2006-03-20 17:49:20 -08005026 num_rings++;
5027 }
5028 /* round to next power of 2 */
Michael Chan5d5d0012007-12-12 11:17:43 -08005029 max = max_size;
Michael Chan13daffa2006-03-20 17:49:20 -08005030 while ((max & num_rings) == 0)
5031 max >>= 1;
5032
5033 if (num_rings != max)
5034 max <<= 1;
5035
Michael Chan5d5d0012007-12-12 11:17:43 -08005036 return max;
5037}
5038
5039static void
5040bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5041{
Michael Chan84eaa182007-12-12 11:19:57 -08005042 u32 rx_size, rx_space, jumbo_size;
Michael Chan5d5d0012007-12-12 11:17:43 -08005043
5044 /* 8 for CRC and VLAN */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005045 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
Michael Chan5d5d0012007-12-12 11:17:43 -08005046
Michael Chan84eaa182007-12-12 11:19:57 -08005047 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5048 sizeof(struct skb_shared_info);
5049
Benjamin Li601d3d12008-05-16 22:19:35 -07005050 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
Michael Chan47bf4242007-12-12 11:19:12 -08005051 bp->rx_pg_ring_size = 0;
5052 bp->rx_max_pg_ring = 0;
5053 bp->rx_max_pg_ring_idx = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08005054 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
Michael Chan84eaa182007-12-12 11:19:57 -08005055 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5056
5057 jumbo_size = size * pages;
5058 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5059 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5060
5061 bp->rx_pg_ring_size = jumbo_size;
5062 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5063 MAX_RX_PG_RINGS);
5064 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
Benjamin Li601d3d12008-05-16 22:19:35 -07005065 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
Michael Chan84eaa182007-12-12 11:19:57 -08005066 bp->rx_copy_thresh = 0;
5067 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005068
5069 bp->rx_buf_use_size = rx_size;
5070 /* hw alignment */
5071 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005072 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
Michael Chan5d5d0012007-12-12 11:17:43 -08005073 bp->rx_ring_size = size;
5074 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
Michael Chan13daffa2006-03-20 17:49:20 -08005075 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5076}
5077
5078static void
Michael Chanb6016b72005-05-26 13:03:09 -07005079bnx2_free_tx_skbs(struct bnx2 *bp)
5080{
5081 int i;
5082
Michael Chan35e90102008-06-19 16:37:42 -07005083 for (i = 0; i < bp->num_tx_rings; i++) {
5084 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5085 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5086 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005087
Michael Chan35e90102008-06-19 16:37:42 -07005088 if (txr->tx_buf_ring == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07005089 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005090
Michael Chan35e90102008-06-19 16:37:42 -07005091 for (j = 0; j < TX_DESC_CNT; ) {
Benjamin Li3d16af82008-10-09 12:26:41 -07005092 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
Michael Chan35e90102008-06-19 16:37:42 -07005093 struct sk_buff *skb = tx_buf->skb;
Michael Chan35e90102008-06-19 16:37:42 -07005094
5095 if (skb == NULL) {
5096 j++;
5097 continue;
5098 }
5099
Benjamin Li3d16af82008-10-09 12:26:41 -07005100 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005101
Michael Chan35e90102008-06-19 16:37:42 -07005102 tx_buf->skb = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07005103
Benjamin Li3d16af82008-10-09 12:26:41 -07005104 j += skb_shinfo(skb)->nr_frags + 1;
Michael Chan35e90102008-06-19 16:37:42 -07005105 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005106 }
Michael Chanb6016b72005-05-26 13:03:09 -07005107 }
Michael Chanb6016b72005-05-26 13:03:09 -07005108}
5109
5110static void
5111bnx2_free_rx_skbs(struct bnx2 *bp)
5112{
5113 int i;
5114
Michael Chanbb4f98a2008-06-19 16:38:19 -07005115 for (i = 0; i < bp->num_rx_rings; i++) {
5116 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5117 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5118 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005119
Michael Chanbb4f98a2008-06-19 16:38:19 -07005120 if (rxr->rx_buf_ring == NULL)
5121 return;
Michael Chanb6016b72005-05-26 13:03:09 -07005122
Michael Chanbb4f98a2008-06-19 16:38:19 -07005123 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5124 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5125 struct sk_buff *skb = rx_buf->skb;
Michael Chanb6016b72005-05-26 13:03:09 -07005126
Michael Chanbb4f98a2008-06-19 16:38:19 -07005127 if (skb == NULL)
5128 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005129
Michael Chanbb4f98a2008-06-19 16:38:19 -07005130 pci_unmap_single(bp->pdev,
5131 pci_unmap_addr(rx_buf, mapping),
5132 bp->rx_buf_use_size,
5133 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005134
Michael Chanbb4f98a2008-06-19 16:38:19 -07005135 rx_buf->skb = NULL;
5136
5137 dev_kfree_skb(skb);
5138 }
5139 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5140 bnx2_free_rx_page(bp, rxr, j);
Michael Chanb6016b72005-05-26 13:03:09 -07005141 }
5142}
5143
5144static void
5145bnx2_free_skbs(struct bnx2 *bp)
5146{
5147 bnx2_free_tx_skbs(bp);
5148 bnx2_free_rx_skbs(bp);
5149}
5150
5151static int
5152bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5153{
5154 int rc;
5155
5156 rc = bnx2_reset_chip(bp, reset_code);
5157 bnx2_free_skbs(bp);
5158 if (rc)
5159 return rc;
5160
Michael Chanfba9fe92006-06-12 22:21:25 -07005161 if ((rc = bnx2_init_chip(bp)) != 0)
5162 return rc;
5163
Michael Chan35e90102008-06-19 16:37:42 -07005164 bnx2_init_all_rings(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005165 return 0;
5166}
5167
5168static int
Michael Chan9a120bc2008-05-16 22:17:45 -07005169bnx2_init_nic(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07005170{
5171 int rc;
5172
5173 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5174 return rc;
5175
Michael Chan80be4432006-11-19 14:07:28 -08005176 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005177 bnx2_init_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07005178 bnx2_set_link(bp);
Michael Chan543a8272008-05-02 16:56:44 -07005179 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5180 bnx2_remote_phy_event(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07005181 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07005182 return 0;
5183}
5184
5185static int
Michael Chan74bf4ba2008-10-09 12:21:08 -07005186bnx2_shutdown_chip(struct bnx2 *bp)
5187{
5188 u32 reset_code;
5189
5190 if (bp->flags & BNX2_FLAG_NO_WOL)
5191 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5192 else if (bp->wol)
5193 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5194 else
5195 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5196
5197 return bnx2_reset_chip(bp, reset_code);
5198}
5199
5200static int
Michael Chanb6016b72005-05-26 13:03:09 -07005201bnx2_test_registers(struct bnx2 *bp)
5202{
5203 int ret;
Michael Chan5bae30c2007-05-03 13:18:46 -07005204 int i, is_5709;
Arjan van de Venf71e1302006-03-03 21:33:57 -05005205 static const struct {
Michael Chanb6016b72005-05-26 13:03:09 -07005206 u16 offset;
5207 u16 flags;
Michael Chan5bae30c2007-05-03 13:18:46 -07005208#define BNX2_FL_NOT_5709 1
Michael Chanb6016b72005-05-26 13:03:09 -07005209 u32 rw_mask;
5210 u32 ro_mask;
5211 } reg_tbl[] = {
5212 { 0x006c, 0, 0x00000000, 0x0000003f },
5213 { 0x0090, 0, 0xffffffff, 0x00000000 },
5214 { 0x0094, 0, 0x00000000, 0x00000000 },
5215
Michael Chan5bae30c2007-05-03 13:18:46 -07005216 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5217 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5218 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5219 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5220 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5221 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5222 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5223 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5224 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
Michael Chanb6016b72005-05-26 13:03:09 -07005225
Michael Chan5bae30c2007-05-03 13:18:46 -07005226 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5227 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5228 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5229 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5230 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5231 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
Michael Chanb6016b72005-05-26 13:03:09 -07005232
Michael Chan5bae30c2007-05-03 13:18:46 -07005233 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5234 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5235 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005236
5237 { 0x1000, 0, 0x00000000, 0x00000001 },
Michael Chan15b169c2008-05-02 16:57:08 -07005238 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
Michael Chanb6016b72005-05-26 13:03:09 -07005239
5240 { 0x1408, 0, 0x01c00800, 0x00000000 },
5241 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5242 { 0x14a8, 0, 0x00000000, 0x000001ff },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005243 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005244 { 0x14b0, 0, 0x00000002, 0x00000001 },
5245 { 0x14b8, 0, 0x00000000, 0x00000000 },
5246 { 0x14c0, 0, 0x00000000, 0x00000009 },
5247 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5248 { 0x14cc, 0, 0x00000000, 0x00000001 },
5249 { 0x14d0, 0, 0xffffffff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005250
5251 { 0x1800, 0, 0x00000000, 0x00000001 },
5252 { 0x1804, 0, 0x00000000, 0x00000003 },
Michael Chanb6016b72005-05-26 13:03:09 -07005253
5254 { 0x2800, 0, 0x00000000, 0x00000001 },
5255 { 0x2804, 0, 0x00000000, 0x00003f01 },
5256 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5257 { 0x2810, 0, 0xffff0000, 0x00000000 },
5258 { 0x2814, 0, 0xffff0000, 0x00000000 },
5259 { 0x2818, 0, 0xffff0000, 0x00000000 },
5260 { 0x281c, 0, 0xffff0000, 0x00000000 },
5261 { 0x2834, 0, 0xffffffff, 0x00000000 },
5262 { 0x2840, 0, 0x00000000, 0xffffffff },
5263 { 0x2844, 0, 0x00000000, 0xffffffff },
5264 { 0x2848, 0, 0xffffffff, 0x00000000 },
5265 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5266
5267 { 0x2c00, 0, 0x00000000, 0x00000011 },
5268 { 0x2c04, 0, 0x00000000, 0x00030007 },
5269
Michael Chanb6016b72005-05-26 13:03:09 -07005270 { 0x3c00, 0, 0x00000000, 0x00000001 },
5271 { 0x3c04, 0, 0x00000000, 0x00070000 },
5272 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5273 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5274 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5275 { 0x3c14, 0, 0x00000000, 0xffffffff },
5276 { 0x3c18, 0, 0x00000000, 0xffffffff },
5277 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5278 { 0x3c20, 0, 0xffffff00, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005279
5280 { 0x5004, 0, 0x00000000, 0x0000007f },
5281 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005282
Michael Chanb6016b72005-05-26 13:03:09 -07005283 { 0x5c00, 0, 0x00000000, 0x00000001 },
5284 { 0x5c04, 0, 0x00000000, 0x0003000f },
5285 { 0x5c08, 0, 0x00000003, 0x00000000 },
5286 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5287 { 0x5c10, 0, 0x00000000, 0xffffffff },
5288 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5289 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5290 { 0x5c88, 0, 0x00000000, 0x00077373 },
5291 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5292
5293 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5294 { 0x680c, 0, 0xffffffff, 0x00000000 },
5295 { 0x6810, 0, 0xffffffff, 0x00000000 },
5296 { 0x6814, 0, 0xffffffff, 0x00000000 },
5297 { 0x6818, 0, 0xffffffff, 0x00000000 },
5298 { 0x681c, 0, 0xffffffff, 0x00000000 },
5299 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5300 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5301 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5302 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5303 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5304 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5305 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5306 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5307 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5308 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5309 { 0x684c, 0, 0xffffffff, 0x00000000 },
5310 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5311 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5312 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5313 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5314 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5315 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5316
5317 { 0xffff, 0, 0x00000000, 0x00000000 },
5318 };
5319
5320 ret = 0;
Michael Chan5bae30c2007-05-03 13:18:46 -07005321 is_5709 = 0;
5322 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5323 is_5709 = 1;
5324
Michael Chanb6016b72005-05-26 13:03:09 -07005325 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5326 u32 offset, rw_mask, ro_mask, save_val, val;
Michael Chan5bae30c2007-05-03 13:18:46 -07005327 u16 flags = reg_tbl[i].flags;
5328
5329 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5330 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005331
5332 offset = (u32) reg_tbl[i].offset;
5333 rw_mask = reg_tbl[i].rw_mask;
5334 ro_mask = reg_tbl[i].ro_mask;
5335
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005336 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005337
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005338 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005339
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005340 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005341 if ((val & rw_mask) != 0) {
5342 goto reg_test_err;
5343 }
5344
5345 if ((val & ro_mask) != (save_val & ro_mask)) {
5346 goto reg_test_err;
5347 }
5348
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005349 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005350
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005351 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005352 if ((val & rw_mask) != rw_mask) {
5353 goto reg_test_err;
5354 }
5355
5356 if ((val & ro_mask) != (save_val & ro_mask)) {
5357 goto reg_test_err;
5358 }
5359
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005360 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005361 continue;
5362
5363reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005364 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005365 ret = -ENODEV;
5366 break;
5367 }
5368 return ret;
5369}
5370
5371static int
5372bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5373{
Arjan van de Venf71e1302006-03-03 21:33:57 -05005374 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
Michael Chanb6016b72005-05-26 13:03:09 -07005375 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5376 int i;
5377
5378 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5379 u32 offset;
5380
5381 for (offset = 0; offset < size; offset += 4) {
5382
Michael Chan2726d6e2008-01-29 21:35:05 -08005383 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07005384
Michael Chan2726d6e2008-01-29 21:35:05 -08005385 if (bnx2_reg_rd_ind(bp, start + offset) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005386 test_pattern[i]) {
5387 return -ENODEV;
5388 }
5389 }
5390 }
5391 return 0;
5392}
5393
5394static int
5395bnx2_test_memory(struct bnx2 *bp)
5396{
5397 int ret = 0;
5398 int i;
Michael Chan5bae30c2007-05-03 13:18:46 -07005399 static struct mem_entry {
Michael Chanb6016b72005-05-26 13:03:09 -07005400 u32 offset;
5401 u32 len;
Michael Chan5bae30c2007-05-03 13:18:46 -07005402 } mem_tbl_5706[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07005403 { 0x60000, 0x4000 },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005404 { 0xa0000, 0x3000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005405 { 0xe0000, 0x4000 },
5406 { 0x120000, 0x4000 },
5407 { 0x1a0000, 0x4000 },
5408 { 0x160000, 0x4000 },
5409 { 0xffffffff, 0 },
Michael Chan5bae30c2007-05-03 13:18:46 -07005410 },
5411 mem_tbl_5709[] = {
5412 { 0x60000, 0x4000 },
5413 { 0xa0000, 0x3000 },
5414 { 0xe0000, 0x4000 },
5415 { 0x120000, 0x4000 },
5416 { 0x1a0000, 0x4000 },
5417 { 0xffffffff, 0 },
Michael Chanb6016b72005-05-26 13:03:09 -07005418 };
Michael Chan5bae30c2007-05-03 13:18:46 -07005419 struct mem_entry *mem_tbl;
5420
5421 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5422 mem_tbl = mem_tbl_5709;
5423 else
5424 mem_tbl = mem_tbl_5706;
Michael Chanb6016b72005-05-26 13:03:09 -07005425
5426 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5427 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5428 mem_tbl[i].len)) != 0) {
5429 return ret;
5430 }
5431 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005432
Michael Chanb6016b72005-05-26 13:03:09 -07005433 return ret;
5434}
5435
Michael Chanbc5a0692006-01-23 16:13:22 -08005436#define BNX2_MAC_LOOPBACK 0
5437#define BNX2_PHY_LOOPBACK 1
5438
Michael Chanb6016b72005-05-26 13:03:09 -07005439static int
Michael Chanbc5a0692006-01-23 16:13:22 -08005440bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
Michael Chanb6016b72005-05-26 13:03:09 -07005441{
5442 unsigned int pkt_size, num_pkts, i;
5443 struct sk_buff *skb, *rx_skb;
5444 unsigned char *packet;
Michael Chanbc5a0692006-01-23 16:13:22 -08005445 u16 rx_start_idx, rx_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07005446 dma_addr_t map;
5447 struct tx_bd *txbd;
5448 struct sw_bd *rx_buf;
5449 struct l2_fhdr *rx_hdr;
5450 int ret = -ENODEV;
Michael Chanc76c0472007-12-20 20:01:19 -08005451 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
Michael Chan35e90102008-06-19 16:37:42 -07005452 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005453 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005454
5455 tx_napi = bnapi;
Michael Chanb6016b72005-05-26 13:03:09 -07005456
Michael Chan35e90102008-06-19 16:37:42 -07005457 txr = &tx_napi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005458 rxr = &bnapi->rx_ring;
Michael Chanbc5a0692006-01-23 16:13:22 -08005459 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5460 bp->loopback = MAC_LOOPBACK;
5461 bnx2_set_mac_loopback(bp);
5462 }
5463 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
Michael Chan583c28e2008-01-21 19:51:35 -08005464 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan489310a2007-10-10 16:16:31 -07005465 return 0;
5466
Michael Chan80be4432006-11-19 14:07:28 -08005467 bp->loopback = PHY_LOOPBACK;
Michael Chanbc5a0692006-01-23 16:13:22 -08005468 bnx2_set_phy_loopback(bp);
5469 }
5470 else
5471 return -EINVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07005472
Michael Chan84eaa182007-12-12 11:19:57 -08005473 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
Michael Chan932f3772006-08-15 01:39:36 -07005474 skb = netdev_alloc_skb(bp->dev, pkt_size);
John W. Linvilleb6cbc3b62005-11-10 12:58:00 -08005475 if (!skb)
5476 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07005477 packet = skb_put(skb, pkt_size);
Michael Chan66342922006-12-14 15:57:04 -08005478 memcpy(packet, bp->dev->dev_addr, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07005479 memset(packet + 6, 0x0, 8);
5480 for (i = 14; i < pkt_size; i++)
5481 packet[i] = (unsigned char) (i & 0xff);
5482
Benjamin Li3d16af82008-10-09 12:26:41 -07005483 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5484 dev_kfree_skb(skb);
5485 return -EIO;
5486 }
5487 map = skb_shinfo(skb)->dma_maps[0];
Michael Chanb6016b72005-05-26 13:03:09 -07005488
Michael Chanbf5295b2006-03-23 01:11:56 -08005489 REG_WR(bp, BNX2_HC_COMMAND,
5490 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5491
Michael Chanb6016b72005-05-26 13:03:09 -07005492 REG_RD(bp, BNX2_HC_COMMAND);
5493
5494 udelay(5);
Michael Chan35efa7c2007-12-20 19:56:37 -08005495 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005496
Michael Chanb6016b72005-05-26 13:03:09 -07005497 num_pkts = 0;
5498
Michael Chan35e90102008-06-19 16:37:42 -07005499 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
Michael Chanb6016b72005-05-26 13:03:09 -07005500
5501 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5502 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5503 txbd->tx_bd_mss_nbytes = pkt_size;
5504 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5505
5506 num_pkts++;
Michael Chan35e90102008-06-19 16:37:42 -07005507 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5508 txr->tx_prod_bseq += pkt_size;
Michael Chanb6016b72005-05-26 13:03:09 -07005509
Michael Chan35e90102008-06-19 16:37:42 -07005510 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5511 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005512
5513 udelay(100);
5514
Michael Chanbf5295b2006-03-23 01:11:56 -08005515 REG_WR(bp, BNX2_HC_COMMAND,
5516 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5517
Michael Chanb6016b72005-05-26 13:03:09 -07005518 REG_RD(bp, BNX2_HC_COMMAND);
5519
5520 udelay(5);
5521
Benjamin Li3d16af82008-10-09 12:26:41 -07005522 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
Michael Chan745720e2006-06-29 12:37:41 -07005523 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005524
Michael Chan35e90102008-06-19 16:37:42 -07005525 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
Michael Chanb6016b72005-05-26 13:03:09 -07005526 goto loopback_test_done;
Michael Chanb6016b72005-05-26 13:03:09 -07005527
Michael Chan35efa7c2007-12-20 19:56:37 -08005528 rx_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005529 if (rx_idx != rx_start_idx + num_pkts) {
5530 goto loopback_test_done;
5531 }
5532
Michael Chanbb4f98a2008-06-19 16:38:19 -07005533 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
Michael Chanb6016b72005-05-26 13:03:09 -07005534 rx_skb = rx_buf->skb;
5535
5536 rx_hdr = (struct l2_fhdr *) rx_skb->data;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005537 skb_reserve(rx_skb, BNX2_RX_OFFSET);
Michael Chanb6016b72005-05-26 13:03:09 -07005538
5539 pci_dma_sync_single_for_cpu(bp->pdev,
5540 pci_unmap_addr(rx_buf, mapping),
5541 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5542
Michael Chanade2bfe2006-01-23 16:09:51 -08005543 if (rx_hdr->l2_fhdr_status &
Michael Chanb6016b72005-05-26 13:03:09 -07005544 (L2_FHDR_ERRORS_BAD_CRC |
5545 L2_FHDR_ERRORS_PHY_DECODE |
5546 L2_FHDR_ERRORS_ALIGNMENT |
5547 L2_FHDR_ERRORS_TOO_SHORT |
5548 L2_FHDR_ERRORS_GIANT_FRAME)) {
5549
5550 goto loopback_test_done;
5551 }
5552
5553 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5554 goto loopback_test_done;
5555 }
5556
5557 for (i = 14; i < pkt_size; i++) {
5558 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5559 goto loopback_test_done;
5560 }
5561 }
5562
5563 ret = 0;
5564
5565loopback_test_done:
5566 bp->loopback = 0;
5567 return ret;
5568}
5569
Michael Chanbc5a0692006-01-23 16:13:22 -08005570#define BNX2_MAC_LOOPBACK_FAILED 1
5571#define BNX2_PHY_LOOPBACK_FAILED 2
5572#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5573 BNX2_PHY_LOOPBACK_FAILED)
5574
5575static int
5576bnx2_test_loopback(struct bnx2 *bp)
5577{
5578 int rc = 0;
5579
5580 if (!netif_running(bp->dev))
5581 return BNX2_LOOPBACK_FAILED;
5582
5583 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5584 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005585 bnx2_init_phy(bp, 1);
Michael Chanbc5a0692006-01-23 16:13:22 -08005586 spin_unlock_bh(&bp->phy_lock);
5587 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5588 rc |= BNX2_MAC_LOOPBACK_FAILED;
5589 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5590 rc |= BNX2_PHY_LOOPBACK_FAILED;
5591 return rc;
5592}
5593
Michael Chanb6016b72005-05-26 13:03:09 -07005594#define NVRAM_SIZE 0x200
5595#define CRC32_RESIDUAL 0xdebb20e3
5596
5597static int
5598bnx2_test_nvram(struct bnx2 *bp)
5599{
Al Virob491edd2007-12-22 19:44:51 +00005600 __be32 buf[NVRAM_SIZE / 4];
Michael Chanb6016b72005-05-26 13:03:09 -07005601 u8 *data = (u8 *) buf;
5602 int rc = 0;
5603 u32 magic, csum;
5604
5605 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5606 goto test_nvram_done;
5607
5608 magic = be32_to_cpu(buf[0]);
5609 if (magic != 0x669955aa) {
5610 rc = -ENODEV;
5611 goto test_nvram_done;
5612 }
5613
5614 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5615 goto test_nvram_done;
5616
5617 csum = ether_crc_le(0x100, data);
5618 if (csum != CRC32_RESIDUAL) {
5619 rc = -ENODEV;
5620 goto test_nvram_done;
5621 }
5622
5623 csum = ether_crc_le(0x100, data + 0x100);
5624 if (csum != CRC32_RESIDUAL) {
5625 rc = -ENODEV;
5626 }
5627
5628test_nvram_done:
5629 return rc;
5630}
5631
5632static int
5633bnx2_test_link(struct bnx2 *bp)
5634{
5635 u32 bmsr;
5636
Michael Chan9f52b562008-10-09 12:21:46 -07005637 if (!netif_running(bp->dev))
5638 return -ENODEV;
5639
Michael Chan583c28e2008-01-21 19:51:35 -08005640 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan489310a2007-10-10 16:16:31 -07005641 if (bp->link_up)
5642 return 0;
5643 return -ENODEV;
5644 }
Michael Chanc770a652005-08-25 15:38:39 -07005645 spin_lock_bh(&bp->phy_lock);
Michael Chan27a005b2007-05-03 13:23:41 -07005646 bnx2_enable_bmsr1(bp);
5647 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5648 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5649 bnx2_disable_bmsr1(bp);
Michael Chanc770a652005-08-25 15:38:39 -07005650 spin_unlock_bh(&bp->phy_lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005651
Michael Chanb6016b72005-05-26 13:03:09 -07005652 if (bmsr & BMSR_LSTATUS) {
5653 return 0;
5654 }
5655 return -ENODEV;
5656}
5657
5658static int
5659bnx2_test_intr(struct bnx2 *bp)
5660{
5661 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07005662 u16 status_idx;
5663
5664 if (!netif_running(bp->dev))
5665 return -ENODEV;
5666
5667 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5668
5669 /* This register is not touched during run-time. */
Michael Chanbf5295b2006-03-23 01:11:56 -08005670 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -07005671 REG_RD(bp, BNX2_HC_COMMAND);
5672
5673 for (i = 0; i < 10; i++) {
5674 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5675 status_idx) {
5676
5677 break;
5678 }
5679
5680 msleep_interruptible(10);
5681 }
5682 if (i < 10)
5683 return 0;
5684
5685 return -ENODEV;
5686}
5687
Michael Chan38ea3682008-02-23 19:48:57 -08005688/* Determining link for parallel detection. */
Michael Chanb2fadea2008-01-21 17:07:06 -08005689static int
5690bnx2_5706_serdes_has_link(struct bnx2 *bp)
5691{
5692 u32 mode_ctl, an_dbg, exp;
5693
Michael Chan38ea3682008-02-23 19:48:57 -08005694 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5695 return 0;
5696
Michael Chanb2fadea2008-01-21 17:07:06 -08005697 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5698 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5699
5700 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5701 return 0;
5702
5703 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5704 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5705 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5706
Michael Chanf3014c02008-01-29 21:33:03 -08005707 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
Michael Chanb2fadea2008-01-21 17:07:06 -08005708 return 0;
5709
5710 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5711 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5712 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5713
5714 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5715 return 0;
5716
5717 return 1;
5718}
5719
Michael Chanb6016b72005-05-26 13:03:09 -07005720static void
Michael Chan48b01e22006-11-19 14:08:00 -08005721bnx2_5706_serdes_timer(struct bnx2 *bp)
5722{
Michael Chanb2fadea2008-01-21 17:07:06 -08005723 int check_link = 1;
5724
Michael Chan48b01e22006-11-19 14:08:00 -08005725 spin_lock(&bp->phy_lock);
Michael Chanb2fadea2008-01-21 17:07:06 -08005726 if (bp->serdes_an_pending) {
Michael Chan48b01e22006-11-19 14:08:00 -08005727 bp->serdes_an_pending--;
Michael Chanb2fadea2008-01-21 17:07:06 -08005728 check_link = 0;
5729 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005730 u32 bmcr;
5731
Benjamin Liac392ab2008-09-18 16:40:49 -07005732 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005733
Michael Chanca58c3a2007-05-03 13:22:52 -07005734 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005735
5736 if (bmcr & BMCR_ANENABLE) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005737 if (bnx2_5706_serdes_has_link(bp)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005738 bmcr &= ~BMCR_ANENABLE;
5739 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
Michael Chanca58c3a2007-05-03 13:22:52 -07005740 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan583c28e2008-01-21 19:51:35 -08005741 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005742 }
5743 }
5744 }
5745 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
Michael Chan583c28e2008-01-21 19:51:35 -08005746 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005747 u32 phy2;
5748
5749 bnx2_write_phy(bp, 0x17, 0x0f01);
5750 bnx2_read_phy(bp, 0x15, &phy2);
5751 if (phy2 & 0x20) {
5752 u32 bmcr;
5753
Michael Chanca58c3a2007-05-03 13:22:52 -07005754 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005755 bmcr |= BMCR_ANENABLE;
Michael Chanca58c3a2007-05-03 13:22:52 -07005756 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005757
Michael Chan583c28e2008-01-21 19:51:35 -08005758 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005759 }
5760 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07005761 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005762
Michael Chana2724e22008-02-23 19:47:44 -08005763 if (check_link) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005764 u32 val;
5765
5766 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5767 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5768 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5769
Michael Chana2724e22008-02-23 19:47:44 -08005770 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5771 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5772 bnx2_5706s_force_link_dn(bp, 1);
5773 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5774 } else
5775 bnx2_set_link(bp);
5776 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5777 bnx2_set_link(bp);
Michael Chanb2fadea2008-01-21 17:07:06 -08005778 }
Michael Chan48b01e22006-11-19 14:08:00 -08005779 spin_unlock(&bp->phy_lock);
5780}
5781
5782static void
Michael Chanf8dd0642006-11-19 14:08:29 -08005783bnx2_5708_serdes_timer(struct bnx2 *bp)
5784{
Michael Chan583c28e2008-01-21 19:51:35 -08005785 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07005786 return;
5787
Michael Chan583c28e2008-01-21 19:51:35 -08005788 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005789 bp->serdes_an_pending = 0;
5790 return;
5791 }
5792
5793 spin_lock(&bp->phy_lock);
5794 if (bp->serdes_an_pending)
5795 bp->serdes_an_pending--;
5796 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5797 u32 bmcr;
5798
Michael Chanca58c3a2007-05-03 13:22:52 -07005799 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanf8dd0642006-11-19 14:08:29 -08005800 if (bmcr & BMCR_ANENABLE) {
Michael Chan605a9e22007-05-03 13:23:13 -07005801 bnx2_enable_forced_2g5(bp);
Michael Chan40105c02008-11-12 16:02:45 -08005802 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08005803 } else {
Michael Chan605a9e22007-05-03 13:23:13 -07005804 bnx2_disable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08005805 bp->serdes_an_pending = 2;
Benjamin Liac392ab2008-09-18 16:40:49 -07005806 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08005807 }
5808
5809 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07005810 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08005811
5812 spin_unlock(&bp->phy_lock);
5813}
5814
5815static void
Michael Chanb6016b72005-05-26 13:03:09 -07005816bnx2_timer(unsigned long data)
5817{
5818 struct bnx2 *bp = (struct bnx2 *) data;
Michael Chanb6016b72005-05-26 13:03:09 -07005819
Michael Chancd339a02005-08-25 15:35:24 -07005820 if (!netif_running(bp->dev))
5821 return;
5822
Michael Chanb6016b72005-05-26 13:03:09 -07005823 if (atomic_read(&bp->intr_sem) != 0)
5824 goto bnx2_restart_timer;
5825
Michael Chanefba0182008-12-03 00:36:15 -08005826 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5827 BNX2_FLAG_USING_MSI)
5828 bnx2_chk_missed_msi(bp);
5829
Michael Chandf149d72007-07-07 22:51:36 -07005830 bnx2_send_heart_beat(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005831
Michael Chan2726d6e2008-01-29 21:35:05 -08005832 bp->stats_blk->stat_FwRxDrop =
5833 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
Michael Chancea94db2006-06-12 22:16:13 -07005834
Michael Chan02537b062007-06-04 21:24:07 -07005835 /* workaround occasional corrupted counters */
5836 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5837 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5838 BNX2_HC_COMMAND_STATS_NOW);
5839
Michael Chan583c28e2008-01-21 19:51:35 -08005840 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005841 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5842 bnx2_5706_serdes_timer(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07005843 else
Michael Chanf8dd0642006-11-19 14:08:29 -08005844 bnx2_5708_serdes_timer(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005845 }
5846
5847bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -07005848 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005849}
5850
Michael Chan8e6a72c2007-05-03 13:24:48 -07005851static int
5852bnx2_request_irq(struct bnx2 *bp)
5853{
Michael Chan6d866ff2007-12-20 19:56:09 -08005854 unsigned long flags;
Michael Chanb4b36042007-12-20 19:59:30 -08005855 struct bnx2_irq *irq;
5856 int rc = 0, i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005857
David S. Millerf86e82f2008-01-21 17:15:40 -08005858 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
Michael Chan6d866ff2007-12-20 19:56:09 -08005859 flags = 0;
5860 else
5861 flags = IRQF_SHARED;
Michael Chanb4b36042007-12-20 19:59:30 -08005862
5863 for (i = 0; i < bp->irq_nvecs; i++) {
5864 irq = &bp->irq_tbl[i];
Michael Chanc76c0472007-12-20 20:01:19 -08005865 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
Michael Chanf0ea2e62008-06-19 16:41:57 -07005866 &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08005867 if (rc)
5868 break;
5869 irq->requested = 1;
5870 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07005871 return rc;
5872}
5873
5874static void
5875bnx2_free_irq(struct bnx2 *bp)
5876{
Michael Chanb4b36042007-12-20 19:59:30 -08005877 struct bnx2_irq *irq;
5878 int i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005879
Michael Chanb4b36042007-12-20 19:59:30 -08005880 for (i = 0; i < bp->irq_nvecs; i++) {
5881 irq = &bp->irq_tbl[i];
5882 if (irq->requested)
Michael Chanf0ea2e62008-06-19 16:41:57 -07005883 free_irq(irq->vector, &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08005884 irq->requested = 0;
Michael Chan6d866ff2007-12-20 19:56:09 -08005885 }
David S. Millerf86e82f2008-01-21 17:15:40 -08005886 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb4b36042007-12-20 19:59:30 -08005887 pci_disable_msi(bp->pdev);
David S. Millerf86e82f2008-01-21 17:15:40 -08005888 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08005889 pci_disable_msix(bp->pdev);
5890
David S. Millerf86e82f2008-01-21 17:15:40 -08005891 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
Michael Chanb4b36042007-12-20 19:59:30 -08005892}
5893
5894static void
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005895bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
Michael Chanb4b36042007-12-20 19:59:30 -08005896{
Michael Chan57851d82007-12-20 20:01:44 -08005897 int i, rc;
5898 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
Michael Chan4e1d0de2008-12-16 20:27:45 -08005899 struct net_device *dev = bp->dev;
5900 const int len = sizeof(bp->irq_tbl[0].name);
Michael Chan57851d82007-12-20 20:01:44 -08005901
Michael Chanb4b36042007-12-20 19:59:30 -08005902 bnx2_setup_msix_tbl(bp);
5903 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5904 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5905 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
Michael Chan57851d82007-12-20 20:01:44 -08005906
5907 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5908 msix_ent[i].entry = i;
5909 msix_ent[i].vector = 0;
5910 }
5911
5912 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5913 if (rc != 0)
5914 return;
5915
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005916 bp->irq_nvecs = msix_vecs;
David S. Millerf86e82f2008-01-21 17:15:40 -08005917 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan69010312009-03-18 18:11:51 -07005918 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan57851d82007-12-20 20:01:44 -08005919 bp->irq_tbl[i].vector = msix_ent[i].vector;
Michael Chan69010312009-03-18 18:11:51 -07005920 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
5921 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5922 }
Michael Chan6d866ff2007-12-20 19:56:09 -08005923}
5924
5925static void
5926bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5927{
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005928 int cpus = num_online_cpus();
Benjamin Li706bf242008-07-18 17:55:11 -07005929 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005930
Michael Chan6d866ff2007-12-20 19:56:09 -08005931 bp->irq_tbl[0].handler = bnx2_interrupt;
5932 strcpy(bp->irq_tbl[0].name, bp->dev->name);
Michael Chanb4b36042007-12-20 19:59:30 -08005933 bp->irq_nvecs = 1;
5934 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005935
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005936 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5937 bnx2_enable_msix(bp, msix_vecs);
Michael Chanb4b36042007-12-20 19:59:30 -08005938
David S. Millerf86e82f2008-01-21 17:15:40 -08005939 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5940 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
Michael Chan6d866ff2007-12-20 19:56:09 -08005941 if (pci_enable_msi(bp->pdev) == 0) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005942 bp->flags |= BNX2_FLAG_USING_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005943 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005944 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005945 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5946 } else
5947 bp->irq_tbl[0].handler = bnx2_msi;
Michael Chanb4b36042007-12-20 19:59:30 -08005948
5949 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005950 }
5951 }
Benjamin Li706bf242008-07-18 17:55:11 -07005952
5953 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5954 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5955
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005956 bp->num_rx_rings = bp->irq_nvecs;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005957}
5958
Michael Chanb6016b72005-05-26 13:03:09 -07005959/* Called with rtnl_lock */
5960static int
5961bnx2_open(struct net_device *dev)
5962{
Michael Chan972ec0d2006-01-23 16:12:43 -08005963 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005964 int rc;
5965
Michael Chan1b2f9222007-05-03 13:20:19 -07005966 netif_carrier_off(dev);
5967
Pavel Machek829ca9a2005-09-03 15:56:56 -07005968 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07005969 bnx2_disable_int(bp);
5970
Michael Chan6d866ff2007-12-20 19:56:09 -08005971 bnx2_setup_int_mode(bp, disable_msi);
Michael Chan35efa7c2007-12-20 19:56:37 -08005972 bnx2_napi_enable(bp);
Michael Chan35e90102008-06-19 16:37:42 -07005973 rc = bnx2_alloc_mem(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07005974 if (rc)
5975 goto open_err;
Michael Chan35e90102008-06-19 16:37:42 -07005976
Michael Chan8e6a72c2007-05-03 13:24:48 -07005977 rc = bnx2_request_irq(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07005978 if (rc)
5979 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07005980
Michael Chan9a120bc2008-05-16 22:17:45 -07005981 rc = bnx2_init_nic(bp, 1);
Michael Chan2739a8b2008-06-19 16:44:10 -07005982 if (rc)
5983 goto open_err;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005984
Michael Chancd339a02005-08-25 15:35:24 -07005985 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005986
5987 atomic_set(&bp->intr_sem, 0);
5988
5989 bnx2_enable_int(bp);
5990
David S. Millerf86e82f2008-01-21 17:15:40 -08005991 if (bp->flags & BNX2_FLAG_USING_MSI) {
Michael Chanb6016b72005-05-26 13:03:09 -07005992 /* Test MSI to make sure it is working
5993 * If MSI test fails, go back to INTx mode
5994 */
5995 if (bnx2_test_intr(bp) != 0) {
5996 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5997 " using MSI, switching to INTx mode. Please"
5998 " report this failure to the PCI maintainer"
5999 " and include system chipset information.\n",
6000 bp->dev->name);
6001
6002 bnx2_disable_int(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006003 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006004
Michael Chan6d866ff2007-12-20 19:56:09 -08006005 bnx2_setup_int_mode(bp, 1);
6006
Michael Chan9a120bc2008-05-16 22:17:45 -07006007 rc = bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006008
Michael Chan8e6a72c2007-05-03 13:24:48 -07006009 if (!rc)
6010 rc = bnx2_request_irq(bp);
6011
Michael Chanb6016b72005-05-26 13:03:09 -07006012 if (rc) {
Michael Chanb6016b72005-05-26 13:03:09 -07006013 del_timer_sync(&bp->timer);
Michael Chan2739a8b2008-06-19 16:44:10 -07006014 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07006015 }
6016 bnx2_enable_int(bp);
6017 }
6018 }
David S. Millerf86e82f2008-01-21 17:15:40 -08006019 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb6016b72005-05-26 13:03:09 -07006020 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
David S. Millerf86e82f2008-01-21 17:15:40 -08006021 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chan57851d82007-12-20 20:01:44 -08006022 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
Michael Chanb6016b72005-05-26 13:03:09 -07006023
Benjamin Li706bf242008-07-18 17:55:11 -07006024 netif_tx_start_all_queues(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006025
6026 return 0;
Michael Chan2739a8b2008-06-19 16:44:10 -07006027
6028open_err:
6029 bnx2_napi_disable(bp);
6030 bnx2_free_skbs(bp);
6031 bnx2_free_irq(bp);
6032 bnx2_free_mem(bp);
6033 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07006034}
6035
6036static void
David Howellsc4028952006-11-22 14:57:56 +00006037bnx2_reset_task(struct work_struct *work)
Michael Chanb6016b72005-05-26 13:03:09 -07006038{
David Howellsc4028952006-11-22 14:57:56 +00006039 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07006040
Michael Chanafdc08b2005-08-25 15:34:29 -07006041 if (!netif_running(bp->dev))
6042 return;
6043
Michael Chanb6016b72005-05-26 13:03:09 -07006044 bnx2_netif_stop(bp);
6045
Michael Chan9a120bc2008-05-16 22:17:45 -07006046 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07006047
6048 atomic_set(&bp->intr_sem, 1);
6049 bnx2_netif_start(bp);
6050}
6051
6052static void
6053bnx2_tx_timeout(struct net_device *dev)
6054{
Michael Chan972ec0d2006-01-23 16:12:43 -08006055 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006056
6057 /* This allows the netif to be shutdown gracefully before resetting */
6058 schedule_work(&bp->reset_task);
6059}
6060
6061#ifdef BCM_VLAN
6062/* Called with rtnl_lock */
6063static void
6064bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6065{
Michael Chan972ec0d2006-01-23 16:12:43 -08006066 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006067
6068 bnx2_netif_stop(bp);
6069
6070 bp->vlgrp = vlgrp;
6071 bnx2_set_rx_mode(dev);
Michael Chan7c62e832008-07-14 22:39:03 -07006072 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6073 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07006074
6075 bnx2_netif_start(bp);
6076}
Michael Chanb6016b72005-05-26 13:03:09 -07006077#endif
6078
Herbert Xu932ff272006-06-09 12:20:56 -07006079/* Called with netif_tx_lock.
Michael Chan2f8af122006-08-15 01:39:10 -07006080 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6081 * netif_wake_queue().
Michael Chanb6016b72005-05-26 13:03:09 -07006082 */
6083static int
6084bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6085{
Michael Chan972ec0d2006-01-23 16:12:43 -08006086 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006087 dma_addr_t mapping;
6088 struct tx_bd *txbd;
Benjamin Li3d16af82008-10-09 12:26:41 -07006089 struct sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07006090 u32 len, vlan_tag_flags, last_frag, mss;
6091 u16 prod, ring_prod;
6092 int i;
Benjamin Li706bf242008-07-18 17:55:11 -07006093 struct bnx2_napi *bnapi;
6094 struct bnx2_tx_ring_info *txr;
6095 struct netdev_queue *txq;
Benjamin Li3d16af82008-10-09 12:26:41 -07006096 struct skb_shared_info *sp;
Benjamin Li706bf242008-07-18 17:55:11 -07006097
6098 /* Determine which tx ring we will be placed on */
6099 i = skb_get_queue_mapping(skb);
6100 bnapi = &bp->bnx2_napi[i];
6101 txr = &bnapi->tx_ring;
6102 txq = netdev_get_tx_queue(dev, i);
Michael Chanb6016b72005-05-26 13:03:09 -07006103
Michael Chan35e90102008-06-19 16:37:42 -07006104 if (unlikely(bnx2_tx_avail(bp, txr) <
Michael Chana550c992007-12-20 19:56:59 -08006105 (skb_shinfo(skb)->nr_frags + 1))) {
Benjamin Li706bf242008-07-18 17:55:11 -07006106 netif_tx_stop_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006107 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6108 dev->name);
6109
6110 return NETDEV_TX_BUSY;
6111 }
6112 len = skb_headlen(skb);
Michael Chan35e90102008-06-19 16:37:42 -07006113 prod = txr->tx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006114 ring_prod = TX_RING_IDX(prod);
6115
6116 vlan_tag_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006117 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006118 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6119 }
6120
Michael Chan729b85c2008-08-14 15:29:39 -07006121#ifdef BCM_VLAN
Al Viro79ea13c2008-01-24 02:06:46 -08006122 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07006123 vlan_tag_flags |=
6124 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6125 }
Michael Chan729b85c2008-08-14 15:29:39 -07006126#endif
Michael Chanfde82052007-05-03 17:23:35 -07006127 if ((mss = skb_shinfo(skb)->gso_size)) {
Michael Chana1efb4b2008-10-09 12:24:39 -07006128 u32 tcp_opt_len;
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006129 struct iphdr *iph;
Michael Chanb6016b72005-05-26 13:03:09 -07006130
Michael Chanb6016b72005-05-26 13:03:09 -07006131 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6132
Michael Chan4666f872007-05-03 13:22:28 -07006133 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006134
Michael Chan4666f872007-05-03 13:22:28 -07006135 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6136 u32 tcp_off = skb_transport_offset(skb) -
6137 sizeof(struct ipv6hdr) - ETH_HLEN;
Michael Chanb6016b72005-05-26 13:03:09 -07006138
Michael Chan4666f872007-05-03 13:22:28 -07006139 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6140 TX_BD_FLAGS_SW_FLAGS;
6141 if (likely(tcp_off == 0))
6142 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6143 else {
6144 tcp_off >>= 3;
6145 vlan_tag_flags |= ((tcp_off & 0x3) <<
6146 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6147 ((tcp_off & 0x10) <<
6148 TX_BD_FLAGS_TCP6_OFF4_SHL);
6149 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6150 }
6151 } else {
Michael Chan4666f872007-05-03 13:22:28 -07006152 iph = ip_hdr(skb);
Michael Chan4666f872007-05-03 13:22:28 -07006153 if (tcp_opt_len || (iph->ihl > 5)) {
6154 vlan_tag_flags |= ((iph->ihl - 5) +
6155 (tcp_opt_len >> 2)) << 8;
6156 }
Michael Chanb6016b72005-05-26 13:03:09 -07006157 }
Michael Chan4666f872007-05-03 13:22:28 -07006158 } else
Michael Chanb6016b72005-05-26 13:03:09 -07006159 mss = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006160
Benjamin Li3d16af82008-10-09 12:26:41 -07006161 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6162 dev_kfree_skb(skb);
6163 return NETDEV_TX_OK;
6164 }
6165
6166 sp = skb_shinfo(skb);
6167 mapping = sp->dma_maps[0];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006168
Michael Chan35e90102008-06-19 16:37:42 -07006169 tx_buf = &txr->tx_buf_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006170 tx_buf->skb = skb;
Michael Chanb6016b72005-05-26 13:03:09 -07006171
Michael Chan35e90102008-06-19 16:37:42 -07006172 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006173
6174 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6175 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6176 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6177 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6178
6179 last_frag = skb_shinfo(skb)->nr_frags;
6180
6181 for (i = 0; i < last_frag; i++) {
6182 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6183
6184 prod = NEXT_TX_BD(prod);
6185 ring_prod = TX_RING_IDX(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006186 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006187
6188 len = frag->size;
Benjamin Li3d16af82008-10-09 12:26:41 -07006189 mapping = sp->dma_maps[i + 1];
Michael Chanb6016b72005-05-26 13:03:09 -07006190
6191 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6192 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6193 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6194 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6195
6196 }
6197 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6198
6199 prod = NEXT_TX_BD(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006200 txr->tx_prod_bseq += skb->len;
Michael Chanb6016b72005-05-26 13:03:09 -07006201
Michael Chan35e90102008-06-19 16:37:42 -07006202 REG_WR16(bp, txr->tx_bidx_addr, prod);
6203 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07006204
6205 mmiowb();
6206
Michael Chan35e90102008-06-19 16:37:42 -07006207 txr->tx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006208 dev->trans_start = jiffies;
6209
Michael Chan35e90102008-06-19 16:37:42 -07006210 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
Benjamin Li706bf242008-07-18 17:55:11 -07006211 netif_tx_stop_queue(txq);
Michael Chan35e90102008-06-19 16:37:42 -07006212 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
Benjamin Li706bf242008-07-18 17:55:11 -07006213 netif_tx_wake_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006214 }
6215
6216 return NETDEV_TX_OK;
6217}
6218
6219/* Called with rtnl_lock */
6220static int
6221bnx2_close(struct net_device *dev)
6222{
Michael Chan972ec0d2006-01-23 16:12:43 -08006223 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006224
David S. Miller4bb073c2008-06-12 02:22:02 -07006225 cancel_work_sync(&bp->reset_task);
Michael Chanafdc08b2005-08-25 15:34:29 -07006226
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006227 bnx2_disable_int_sync(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08006228 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006229 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07006230 bnx2_shutdown_chip(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006231 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006232 bnx2_free_skbs(bp);
6233 bnx2_free_mem(bp);
6234 bp->link_up = 0;
6235 netif_carrier_off(bp->dev);
Pavel Machek829ca9a2005-09-03 15:56:56 -07006236 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07006237 return 0;
6238}
6239
6240#define GET_NET_STATS64(ctr) \
6241 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6242 (unsigned long) (ctr##_lo)
6243
6244#define GET_NET_STATS32(ctr) \
6245 (ctr##_lo)
6246
6247#if (BITS_PER_LONG == 64)
6248#define GET_NET_STATS GET_NET_STATS64
6249#else
6250#define GET_NET_STATS GET_NET_STATS32
6251#endif
6252
6253static struct net_device_stats *
6254bnx2_get_stats(struct net_device *dev)
6255{
Michael Chan972ec0d2006-01-23 16:12:43 -08006256 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006257 struct statistics_block *stats_blk = bp->stats_blk;
Ilpo Järvinend8e80342008-11-28 15:52:43 -08006258 struct net_device_stats *net_stats = &dev->stats;
Michael Chanb6016b72005-05-26 13:03:09 -07006259
6260 if (bp->stats_blk == NULL) {
6261 return net_stats;
6262 }
6263 net_stats->rx_packets =
6264 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6265 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6266 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6267
6268 net_stats->tx_packets =
6269 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6270 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6271 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6272
6273 net_stats->rx_bytes =
6274 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6275
6276 net_stats->tx_bytes =
6277 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6278
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006279 net_stats->multicast =
Michael Chanb6016b72005-05-26 13:03:09 -07006280 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6281
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006282 net_stats->collisions =
Michael Chanb6016b72005-05-26 13:03:09 -07006283 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6284
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006285 net_stats->rx_length_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006286 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6287 stats_blk->stat_EtherStatsOverrsizePkts);
6288
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006289 net_stats->rx_over_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006290 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6291
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006292 net_stats->rx_frame_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006293 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6294
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006295 net_stats->rx_crc_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006296 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6297
6298 net_stats->rx_errors = net_stats->rx_length_errors +
6299 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6300 net_stats->rx_crc_errors;
6301
6302 net_stats->tx_aborted_errors =
6303 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6304 stats_blk->stat_Dot3StatsLateCollisions);
6305
Michael Chan5b0c76a2005-11-04 08:45:49 -08006306 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6307 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07006308 net_stats->tx_carrier_errors = 0;
6309 else {
6310 net_stats->tx_carrier_errors =
6311 (unsigned long)
6312 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6313 }
6314
6315 net_stats->tx_errors =
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006316 (unsigned long)
Michael Chanb6016b72005-05-26 13:03:09 -07006317 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6318 +
6319 net_stats->tx_aborted_errors +
6320 net_stats->tx_carrier_errors;
6321
Michael Chancea94db2006-06-12 22:16:13 -07006322 net_stats->rx_missed_errors =
6323 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6324 stats_blk->stat_FwRxDrop);
6325
Michael Chanb6016b72005-05-26 13:03:09 -07006326 return net_stats;
6327}
6328
6329/* All ethtool functions called with rtnl_lock */
6330
6331static int
6332bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6333{
Michael Chan972ec0d2006-01-23 16:12:43 -08006334 struct bnx2 *bp = netdev_priv(dev);
Michael Chan7b6b8342007-07-07 22:50:15 -07006335 int support_serdes = 0, support_copper = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006336
6337 cmd->supported = SUPPORTED_Autoneg;
Michael Chan583c28e2008-01-21 19:51:35 -08006338 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006339 support_serdes = 1;
6340 support_copper = 1;
6341 } else if (bp->phy_port == PORT_FIBRE)
6342 support_serdes = 1;
6343 else
6344 support_copper = 1;
6345
6346 if (support_serdes) {
Michael Chanb6016b72005-05-26 13:03:09 -07006347 cmd->supported |= SUPPORTED_1000baseT_Full |
6348 SUPPORTED_FIBRE;
Michael Chan583c28e2008-01-21 19:51:35 -08006349 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan605a9e22007-05-03 13:23:13 -07006350 cmd->supported |= SUPPORTED_2500baseX_Full;
Michael Chanb6016b72005-05-26 13:03:09 -07006351
Michael Chanb6016b72005-05-26 13:03:09 -07006352 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006353 if (support_copper) {
Michael Chanb6016b72005-05-26 13:03:09 -07006354 cmd->supported |= SUPPORTED_10baseT_Half |
6355 SUPPORTED_10baseT_Full |
6356 SUPPORTED_100baseT_Half |
6357 SUPPORTED_100baseT_Full |
6358 SUPPORTED_1000baseT_Full |
6359 SUPPORTED_TP;
6360
Michael Chanb6016b72005-05-26 13:03:09 -07006361 }
6362
Michael Chan7b6b8342007-07-07 22:50:15 -07006363 spin_lock_bh(&bp->phy_lock);
6364 cmd->port = bp->phy_port;
Michael Chanb6016b72005-05-26 13:03:09 -07006365 cmd->advertising = bp->advertising;
6366
6367 if (bp->autoneg & AUTONEG_SPEED) {
6368 cmd->autoneg = AUTONEG_ENABLE;
6369 }
6370 else {
6371 cmd->autoneg = AUTONEG_DISABLE;
6372 }
6373
6374 if (netif_carrier_ok(dev)) {
6375 cmd->speed = bp->line_speed;
6376 cmd->duplex = bp->duplex;
6377 }
6378 else {
6379 cmd->speed = -1;
6380 cmd->duplex = -1;
6381 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006382 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006383
6384 cmd->transceiver = XCVR_INTERNAL;
6385 cmd->phy_address = bp->phy_addr;
6386
6387 return 0;
6388}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006389
Michael Chanb6016b72005-05-26 13:03:09 -07006390static int
6391bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6392{
Michael Chan972ec0d2006-01-23 16:12:43 -08006393 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006394 u8 autoneg = bp->autoneg;
6395 u8 req_duplex = bp->req_duplex;
6396 u16 req_line_speed = bp->req_line_speed;
6397 u32 advertising = bp->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006398 int err = -EINVAL;
6399
6400 spin_lock_bh(&bp->phy_lock);
6401
6402 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6403 goto err_out_unlock;
6404
Michael Chan583c28e2008-01-21 19:51:35 -08006405 if (cmd->port != bp->phy_port &&
6406 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
Michael Chan7b6b8342007-07-07 22:50:15 -07006407 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006408
Michael Chand6b14482008-07-14 22:37:21 -07006409 /* If device is down, we can store the settings only if the user
6410 * is setting the currently active port.
6411 */
6412 if (!netif_running(dev) && cmd->port != bp->phy_port)
6413 goto err_out_unlock;
6414
Michael Chanb6016b72005-05-26 13:03:09 -07006415 if (cmd->autoneg == AUTONEG_ENABLE) {
6416 autoneg |= AUTONEG_SPEED;
6417
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006418 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006419
6420 /* allow advertising 1 speed */
6421 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6422 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6423 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6424 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6425
Michael Chan7b6b8342007-07-07 22:50:15 -07006426 if (cmd->port == PORT_FIBRE)
6427 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006428
6429 advertising = cmd->advertising;
6430
Michael Chan27a005b2007-05-03 13:23:41 -07006431 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
Michael Chan583c28e2008-01-21 19:51:35 -08006432 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
Michael Chan7b6b8342007-07-07 22:50:15 -07006433 (cmd->port == PORT_TP))
6434 goto err_out_unlock;
6435 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07006436 advertising = cmd->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006437 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6438 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006439 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006440 if (cmd->port == PORT_FIBRE)
Michael Chanb6016b72005-05-26 13:03:09 -07006441 advertising = ETHTOOL_ALL_FIBRE_SPEED;
Michael Chan7b6b8342007-07-07 22:50:15 -07006442 else
Michael Chanb6016b72005-05-26 13:03:09 -07006443 advertising = ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006444 }
6445 advertising |= ADVERTISED_Autoneg;
6446 }
6447 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006448 if (cmd->port == PORT_FIBRE) {
Michael Chan80be4432006-11-19 14:07:28 -08006449 if ((cmd->speed != SPEED_1000 &&
6450 cmd->speed != SPEED_2500) ||
6451 (cmd->duplex != DUPLEX_FULL))
Michael Chan7b6b8342007-07-07 22:50:15 -07006452 goto err_out_unlock;
Michael Chan80be4432006-11-19 14:07:28 -08006453
6454 if (cmd->speed == SPEED_2500 &&
Michael Chan583c28e2008-01-21 19:51:35 -08006455 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan7b6b8342007-07-07 22:50:15 -07006456 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006457 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006458 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6459 goto err_out_unlock;
6460
Michael Chanb6016b72005-05-26 13:03:09 -07006461 autoneg &= ~AUTONEG_SPEED;
6462 req_line_speed = cmd->speed;
6463 req_duplex = cmd->duplex;
6464 advertising = 0;
6465 }
6466
6467 bp->autoneg = autoneg;
6468 bp->advertising = advertising;
6469 bp->req_line_speed = req_line_speed;
6470 bp->req_duplex = req_duplex;
6471
Michael Chand6b14482008-07-14 22:37:21 -07006472 err = 0;
6473 /* If device is down, the new settings will be picked up when it is
6474 * brought up.
6475 */
6476 if (netif_running(dev))
6477 err = bnx2_setup_phy(bp, cmd->port);
Michael Chanb6016b72005-05-26 13:03:09 -07006478
Michael Chan7b6b8342007-07-07 22:50:15 -07006479err_out_unlock:
Michael Chanc770a652005-08-25 15:38:39 -07006480 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006481
Michael Chan7b6b8342007-07-07 22:50:15 -07006482 return err;
Michael Chanb6016b72005-05-26 13:03:09 -07006483}
6484
6485static void
6486bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6487{
Michael Chan972ec0d2006-01-23 16:12:43 -08006488 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006489
6490 strcpy(info->driver, DRV_MODULE_NAME);
6491 strcpy(info->version, DRV_MODULE_VERSION);
6492 strcpy(info->bus_info, pci_name(bp->pdev));
Michael Chan58fc2ea2007-07-07 22:52:02 -07006493 strcpy(info->fw_version, bp->fw_version);
Michael Chanb6016b72005-05-26 13:03:09 -07006494}
6495
Michael Chan244ac4f2006-03-20 17:48:46 -08006496#define BNX2_REGDUMP_LEN (32 * 1024)
6497
6498static int
6499bnx2_get_regs_len(struct net_device *dev)
6500{
6501 return BNX2_REGDUMP_LEN;
6502}
6503
6504static void
6505bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6506{
6507 u32 *p = _p, i, offset;
6508 u8 *orig_p = _p;
6509 struct bnx2 *bp = netdev_priv(dev);
6510 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6511 0x0800, 0x0880, 0x0c00, 0x0c10,
6512 0x0c30, 0x0d08, 0x1000, 0x101c,
6513 0x1040, 0x1048, 0x1080, 0x10a4,
6514 0x1400, 0x1490, 0x1498, 0x14f0,
6515 0x1500, 0x155c, 0x1580, 0x15dc,
6516 0x1600, 0x1658, 0x1680, 0x16d8,
6517 0x1800, 0x1820, 0x1840, 0x1854,
6518 0x1880, 0x1894, 0x1900, 0x1984,
6519 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6520 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6521 0x2000, 0x2030, 0x23c0, 0x2400,
6522 0x2800, 0x2820, 0x2830, 0x2850,
6523 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6524 0x3c00, 0x3c94, 0x4000, 0x4010,
6525 0x4080, 0x4090, 0x43c0, 0x4458,
6526 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6527 0x4fc0, 0x5010, 0x53c0, 0x5444,
6528 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6529 0x5fc0, 0x6000, 0x6400, 0x6428,
6530 0x6800, 0x6848, 0x684c, 0x6860,
6531 0x6888, 0x6910, 0x8000 };
6532
6533 regs->version = 0;
6534
6535 memset(p, 0, BNX2_REGDUMP_LEN);
6536
6537 if (!netif_running(bp->dev))
6538 return;
6539
6540 i = 0;
6541 offset = reg_boundaries[0];
6542 p += offset;
6543 while (offset < BNX2_REGDUMP_LEN) {
6544 *p++ = REG_RD(bp, offset);
6545 offset += 4;
6546 if (offset == reg_boundaries[i + 1]) {
6547 offset = reg_boundaries[i + 2];
6548 p = (u32 *) (orig_p + offset);
6549 i += 2;
6550 }
6551 }
6552}
6553
Michael Chanb6016b72005-05-26 13:03:09 -07006554static void
6555bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6556{
Michael Chan972ec0d2006-01-23 16:12:43 -08006557 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006558
David S. Millerf86e82f2008-01-21 17:15:40 -08006559 if (bp->flags & BNX2_FLAG_NO_WOL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006560 wol->supported = 0;
6561 wol->wolopts = 0;
6562 }
6563 else {
6564 wol->supported = WAKE_MAGIC;
6565 if (bp->wol)
6566 wol->wolopts = WAKE_MAGIC;
6567 else
6568 wol->wolopts = 0;
6569 }
6570 memset(&wol->sopass, 0, sizeof(wol->sopass));
6571}
6572
6573static int
6574bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6575{
Michael Chan972ec0d2006-01-23 16:12:43 -08006576 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006577
6578 if (wol->wolopts & ~WAKE_MAGIC)
6579 return -EINVAL;
6580
6581 if (wol->wolopts & WAKE_MAGIC) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006582 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chanb6016b72005-05-26 13:03:09 -07006583 return -EINVAL;
6584
6585 bp->wol = 1;
6586 }
6587 else {
6588 bp->wol = 0;
6589 }
6590 return 0;
6591}
6592
6593static int
6594bnx2_nway_reset(struct net_device *dev)
6595{
Michael Chan972ec0d2006-01-23 16:12:43 -08006596 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006597 u32 bmcr;
6598
Michael Chan9f52b562008-10-09 12:21:46 -07006599 if (!netif_running(dev))
6600 return -EAGAIN;
6601
Michael Chanb6016b72005-05-26 13:03:09 -07006602 if (!(bp->autoneg & AUTONEG_SPEED)) {
6603 return -EINVAL;
6604 }
6605
Michael Chanc770a652005-08-25 15:38:39 -07006606 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006607
Michael Chan583c28e2008-01-21 19:51:35 -08006608 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006609 int rc;
6610
6611 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6612 spin_unlock_bh(&bp->phy_lock);
6613 return rc;
6614 }
6615
Michael Chanb6016b72005-05-26 13:03:09 -07006616 /* Force a link down visible on the other side */
Michael Chan583c28e2008-01-21 19:51:35 -08006617 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanca58c3a2007-05-03 13:22:52 -07006618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chanc770a652005-08-25 15:38:39 -07006619 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006620
6621 msleep(20);
6622
Michael Chanc770a652005-08-25 15:38:39 -07006623 spin_lock_bh(&bp->phy_lock);
Michael Chanf8dd0642006-11-19 14:08:29 -08006624
Michael Chan40105c02008-11-12 16:02:45 -08006625 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08006626 bp->serdes_an_pending = 1;
6627 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006628 }
6629
Michael Chanca58c3a2007-05-03 13:22:52 -07006630 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07006631 bmcr &= ~BMCR_LOOPBACK;
Michael Chanca58c3a2007-05-03 13:22:52 -07006632 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07006633
Michael Chanc770a652005-08-25 15:38:39 -07006634 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006635
6636 return 0;
6637}
6638
6639static int
6640bnx2_get_eeprom_len(struct net_device *dev)
6641{
Michael Chan972ec0d2006-01-23 16:12:43 -08006642 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006643
Michael Chan1122db72006-01-23 16:11:42 -08006644 if (bp->flash_info == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07006645 return 0;
6646
Michael Chan1122db72006-01-23 16:11:42 -08006647 return (int) bp->flash_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006648}
6649
6650static int
6651bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6652 u8 *eebuf)
6653{
Michael Chan972ec0d2006-01-23 16:12:43 -08006654 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006655 int rc;
6656
Michael Chan9f52b562008-10-09 12:21:46 -07006657 if (!netif_running(dev))
6658 return -EAGAIN;
6659
John W. Linville1064e942005-11-10 12:58:24 -08006660 /* parameters already validated in ethtool_get_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006661
6662 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6663
6664 return rc;
6665}
6666
6667static int
6668bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6669 u8 *eebuf)
6670{
Michael Chan972ec0d2006-01-23 16:12:43 -08006671 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006672 int rc;
6673
Michael Chan9f52b562008-10-09 12:21:46 -07006674 if (!netif_running(dev))
6675 return -EAGAIN;
6676
John W. Linville1064e942005-11-10 12:58:24 -08006677 /* parameters already validated in ethtool_set_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006678
6679 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6680
6681 return rc;
6682}
6683
6684static int
6685bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6686{
Michael Chan972ec0d2006-01-23 16:12:43 -08006687 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006688
6689 memset(coal, 0, sizeof(struct ethtool_coalesce));
6690
6691 coal->rx_coalesce_usecs = bp->rx_ticks;
6692 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6693 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6694 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6695
6696 coal->tx_coalesce_usecs = bp->tx_ticks;
6697 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6698 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6699 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6700
6701 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6702
6703 return 0;
6704}
6705
6706static int
6707bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6708{
Michael Chan972ec0d2006-01-23 16:12:43 -08006709 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006710
6711 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6712 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6713
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006714 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
Michael Chanb6016b72005-05-26 13:03:09 -07006715 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6716
6717 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6718 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6719
6720 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6721 if (bp->rx_quick_cons_trip_int > 0xff)
6722 bp->rx_quick_cons_trip_int = 0xff;
6723
6724 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6725 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6726
6727 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6728 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6729
6730 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6731 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6732
6733 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6734 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6735 0xff;
6736
6737 bp->stats_ticks = coal->stats_block_coalesce_usecs;
Michael Chan02537b062007-06-04 21:24:07 -07006738 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6739 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6740 bp->stats_ticks = USEC_PER_SEC;
6741 }
Michael Chan7ea69202007-07-16 18:27:10 -07006742 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6743 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6744 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07006745
6746 if (netif_running(bp->dev)) {
6747 bnx2_netif_stop(bp);
Michael Chan9a120bc2008-05-16 22:17:45 -07006748 bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006749 bnx2_netif_start(bp);
6750 }
6751
6752 return 0;
6753}
6754
6755static void
6756bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6757{
Michael Chan972ec0d2006-01-23 16:12:43 -08006758 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006759
Michael Chan13daffa2006-03-20 17:49:20 -08006760 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006761 ering->rx_mini_max_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006762 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006763
6764 ering->rx_pending = bp->rx_ring_size;
6765 ering->rx_mini_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006766 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006767
6768 ering->tx_max_pending = MAX_TX_DESC_CNT;
6769 ering->tx_pending = bp->tx_ring_size;
6770}
6771
6772static int
Michael Chan5d5d0012007-12-12 11:17:43 -08006773bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
Michael Chanb6016b72005-05-26 13:03:09 -07006774{
Michael Chan13daffa2006-03-20 17:49:20 -08006775 if (netif_running(bp->dev)) {
6776 bnx2_netif_stop(bp);
6777 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6778 bnx2_free_skbs(bp);
6779 bnx2_free_mem(bp);
6780 }
6781
Michael Chan5d5d0012007-12-12 11:17:43 -08006782 bnx2_set_rx_ring_size(bp, rx);
6783 bp->tx_ring_size = tx;
Michael Chanb6016b72005-05-26 13:03:09 -07006784
6785 if (netif_running(bp->dev)) {
Michael Chan13daffa2006-03-20 17:49:20 -08006786 int rc;
6787
6788 rc = bnx2_alloc_mem(bp);
6789 if (rc)
6790 return rc;
Michael Chan9a120bc2008-05-16 22:17:45 -07006791 bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006792 bnx2_netif_start(bp);
6793 }
Michael Chanb6016b72005-05-26 13:03:09 -07006794 return 0;
6795}
6796
Michael Chan5d5d0012007-12-12 11:17:43 -08006797static int
6798bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6799{
6800 struct bnx2 *bp = netdev_priv(dev);
6801 int rc;
6802
6803 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6804 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6805 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6806
6807 return -EINVAL;
6808 }
6809 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6810 return rc;
6811}
6812
Michael Chanb6016b72005-05-26 13:03:09 -07006813static void
6814bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6815{
Michael Chan972ec0d2006-01-23 16:12:43 -08006816 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006817
6818 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6819 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6820 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6821}
6822
6823static int
6824bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6825{
Michael Chan972ec0d2006-01-23 16:12:43 -08006826 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006827
6828 bp->req_flow_ctrl = 0;
6829 if (epause->rx_pause)
6830 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6831 if (epause->tx_pause)
6832 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6833
6834 if (epause->autoneg) {
6835 bp->autoneg |= AUTONEG_FLOW_CTRL;
6836 }
6837 else {
6838 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6839 }
6840
Michael Chan9f52b562008-10-09 12:21:46 -07006841 if (netif_running(dev)) {
6842 spin_lock_bh(&bp->phy_lock);
6843 bnx2_setup_phy(bp, bp->phy_port);
6844 spin_unlock_bh(&bp->phy_lock);
6845 }
Michael Chanb6016b72005-05-26 13:03:09 -07006846
6847 return 0;
6848}
6849
6850static u32
6851bnx2_get_rx_csum(struct net_device *dev)
6852{
Michael Chan972ec0d2006-01-23 16:12:43 -08006853 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006854
6855 return bp->rx_csum;
6856}
6857
6858static int
6859bnx2_set_rx_csum(struct net_device *dev, u32 data)
6860{
Michael Chan972ec0d2006-01-23 16:12:43 -08006861 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006862
6863 bp->rx_csum = data;
6864 return 0;
6865}
6866
Michael Chanb11d6212006-06-29 12:31:21 -07006867static int
6868bnx2_set_tso(struct net_device *dev, u32 data)
6869{
Michael Chan4666f872007-05-03 13:22:28 -07006870 struct bnx2 *bp = netdev_priv(dev);
6871
6872 if (data) {
Michael Chanb11d6212006-06-29 12:31:21 -07006873 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07006874 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6875 dev->features |= NETIF_F_TSO6;
6876 } else
6877 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6878 NETIF_F_TSO_ECN);
Michael Chanb11d6212006-06-29 12:31:21 -07006879 return 0;
6880}
6881
Michael Chancea94db2006-06-12 22:16:13 -07006882#define BNX2_NUM_STATS 46
Michael Chanb6016b72005-05-26 13:03:09 -07006883
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006884static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07006885 char string[ETH_GSTRING_LEN];
6886} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6887 { "rx_bytes" },
6888 { "rx_error_bytes" },
6889 { "tx_bytes" },
6890 { "tx_error_bytes" },
6891 { "rx_ucast_packets" },
6892 { "rx_mcast_packets" },
6893 { "rx_bcast_packets" },
6894 { "tx_ucast_packets" },
6895 { "tx_mcast_packets" },
6896 { "tx_bcast_packets" },
6897 { "tx_mac_errors" },
6898 { "tx_carrier_errors" },
6899 { "rx_crc_errors" },
6900 { "rx_align_errors" },
6901 { "tx_single_collisions" },
6902 { "tx_multi_collisions" },
6903 { "tx_deferred" },
6904 { "tx_excess_collisions" },
6905 { "tx_late_collisions" },
6906 { "tx_total_collisions" },
6907 { "rx_fragments" },
6908 { "rx_jabbers" },
6909 { "rx_undersize_packets" },
6910 { "rx_oversize_packets" },
6911 { "rx_64_byte_packets" },
6912 { "rx_65_to_127_byte_packets" },
6913 { "rx_128_to_255_byte_packets" },
6914 { "rx_256_to_511_byte_packets" },
6915 { "rx_512_to_1023_byte_packets" },
6916 { "rx_1024_to_1522_byte_packets" },
6917 { "rx_1523_to_9022_byte_packets" },
6918 { "tx_64_byte_packets" },
6919 { "tx_65_to_127_byte_packets" },
6920 { "tx_128_to_255_byte_packets" },
6921 { "tx_256_to_511_byte_packets" },
6922 { "tx_512_to_1023_byte_packets" },
6923 { "tx_1024_to_1522_byte_packets" },
6924 { "tx_1523_to_9022_byte_packets" },
6925 { "rx_xon_frames" },
6926 { "rx_xoff_frames" },
6927 { "tx_xon_frames" },
6928 { "tx_xoff_frames" },
6929 { "rx_mac_ctrl_frames" },
6930 { "rx_filtered_packets" },
6931 { "rx_discards" },
Michael Chancea94db2006-06-12 22:16:13 -07006932 { "rx_fw_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07006933};
6934
6935#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6936
Arjan van de Venf71e1302006-03-03 21:33:57 -05006937static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006938 STATS_OFFSET32(stat_IfHCInOctets_hi),
6939 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6940 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6941 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6942 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6943 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6944 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6945 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6946 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6947 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6948 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006949 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6950 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6951 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6952 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6953 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6954 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6955 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6956 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6957 STATS_OFFSET32(stat_EtherStatsCollisions),
6958 STATS_OFFSET32(stat_EtherStatsFragments),
6959 STATS_OFFSET32(stat_EtherStatsJabbers),
6960 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6961 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6962 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6963 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6964 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6965 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6966 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6967 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6968 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6969 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6970 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6971 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6972 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6973 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6974 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6975 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6976 STATS_OFFSET32(stat_XonPauseFramesReceived),
6977 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6978 STATS_OFFSET32(stat_OutXonSent),
6979 STATS_OFFSET32(stat_OutXoffSent),
6980 STATS_OFFSET32(stat_MacControlFramesReceived),
6981 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6982 STATS_OFFSET32(stat_IfInMBUFDiscards),
Michael Chancea94db2006-06-12 22:16:13 -07006983 STATS_OFFSET32(stat_FwRxDrop),
Michael Chanb6016b72005-05-26 13:03:09 -07006984};
6985
6986/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6987 * skipped because of errata.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006988 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006989static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006990 8,0,8,8,8,8,8,8,8,8,
6991 4,0,4,4,4,4,4,4,4,4,
6992 4,4,4,4,4,4,4,4,4,4,
6993 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07006994 4,4,4,4,4,4,
Michael Chanb6016b72005-05-26 13:03:09 -07006995};
6996
Michael Chan5b0c76a2005-11-04 08:45:49 -08006997static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6998 8,0,8,8,8,8,8,8,8,8,
6999 4,4,4,4,4,4,4,4,4,4,
7000 4,4,4,4,4,4,4,4,4,4,
7001 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07007002 4,4,4,4,4,4,
Michael Chan5b0c76a2005-11-04 08:45:49 -08007003};
7004
Michael Chanb6016b72005-05-26 13:03:09 -07007005#define BNX2_NUM_TESTS 6
7006
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007007static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07007008 char string[ETH_GSTRING_LEN];
7009} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7010 { "register_test (offline)" },
7011 { "memory_test (offline)" },
7012 { "loopback_test (offline)" },
7013 { "nvram_test (online)" },
7014 { "interrupt_test (online)" },
7015 { "link_test (online)" },
7016};
7017
7018static int
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007019bnx2_get_sset_count(struct net_device *dev, int sset)
Michael Chanb6016b72005-05-26 13:03:09 -07007020{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007021 switch (sset) {
7022 case ETH_SS_TEST:
7023 return BNX2_NUM_TESTS;
7024 case ETH_SS_STATS:
7025 return BNX2_NUM_STATS;
7026 default:
7027 return -EOPNOTSUPP;
7028 }
Michael Chanb6016b72005-05-26 13:03:09 -07007029}
7030
7031static void
7032bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7033{
Michael Chan972ec0d2006-01-23 16:12:43 -08007034 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007035
Michael Chan9f52b562008-10-09 12:21:46 -07007036 bnx2_set_power_state(bp, PCI_D0);
7037
Michael Chanb6016b72005-05-26 13:03:09 -07007038 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7039 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Michael Chan80be4432006-11-19 14:07:28 -08007040 int i;
7041
Michael Chanb6016b72005-05-26 13:03:09 -07007042 bnx2_netif_stop(bp);
7043 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7044 bnx2_free_skbs(bp);
7045
7046 if (bnx2_test_registers(bp) != 0) {
7047 buf[0] = 1;
7048 etest->flags |= ETH_TEST_FL_FAILED;
7049 }
7050 if (bnx2_test_memory(bp) != 0) {
7051 buf[1] = 1;
7052 etest->flags |= ETH_TEST_FL_FAILED;
7053 }
Michael Chanbc5a0692006-01-23 16:13:22 -08007054 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
Michael Chanb6016b72005-05-26 13:03:09 -07007055 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chanb6016b72005-05-26 13:03:09 -07007056
Michael Chan9f52b562008-10-09 12:21:46 -07007057 if (!netif_running(bp->dev))
7058 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007059 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07007060 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007061 bnx2_netif_start(bp);
7062 }
7063
7064 /* wait for link up */
Michael Chan80be4432006-11-19 14:07:28 -08007065 for (i = 0; i < 7; i++) {
7066 if (bp->link_up)
7067 break;
7068 msleep_interruptible(1000);
7069 }
Michael Chanb6016b72005-05-26 13:03:09 -07007070 }
7071
7072 if (bnx2_test_nvram(bp) != 0) {
7073 buf[3] = 1;
7074 etest->flags |= ETH_TEST_FL_FAILED;
7075 }
7076 if (bnx2_test_intr(bp) != 0) {
7077 buf[4] = 1;
7078 etest->flags |= ETH_TEST_FL_FAILED;
7079 }
7080
7081 if (bnx2_test_link(bp) != 0) {
7082 buf[5] = 1;
7083 etest->flags |= ETH_TEST_FL_FAILED;
7084
7085 }
Michael Chan9f52b562008-10-09 12:21:46 -07007086 if (!netif_running(bp->dev))
7087 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07007088}
7089
7090static void
7091bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7092{
7093 switch (stringset) {
7094 case ETH_SS_STATS:
7095 memcpy(buf, bnx2_stats_str_arr,
7096 sizeof(bnx2_stats_str_arr));
7097 break;
7098 case ETH_SS_TEST:
7099 memcpy(buf, bnx2_tests_str_arr,
7100 sizeof(bnx2_tests_str_arr));
7101 break;
7102 }
7103}
7104
Michael Chanb6016b72005-05-26 13:03:09 -07007105static void
7106bnx2_get_ethtool_stats(struct net_device *dev,
7107 struct ethtool_stats *stats, u64 *buf)
7108{
Michael Chan972ec0d2006-01-23 16:12:43 -08007109 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007110 int i;
7111 u32 *hw_stats = (u32 *) bp->stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007112 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007113
7114 if (hw_stats == NULL) {
7115 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7116 return;
7117 }
7118
Michael Chan5b0c76a2005-11-04 08:45:49 -08007119 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7120 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7121 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7122 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07007123 stats_len_arr = bnx2_5706_stats_len_arr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007124 else
7125 stats_len_arr = bnx2_5708_stats_len_arr;
Michael Chanb6016b72005-05-26 13:03:09 -07007126
7127 for (i = 0; i < BNX2_NUM_STATS; i++) {
7128 if (stats_len_arr[i] == 0) {
7129 /* skip this counter */
7130 buf[i] = 0;
7131 continue;
7132 }
7133 if (stats_len_arr[i] == 4) {
7134 /* 4-byte counter */
7135 buf[i] = (u64)
7136 *(hw_stats + bnx2_stats_offset_arr[i]);
7137 continue;
7138 }
7139 /* 8-byte counter */
7140 buf[i] = (((u64) *(hw_stats +
7141 bnx2_stats_offset_arr[i])) << 32) +
7142 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7143 }
7144}
7145
7146static int
7147bnx2_phys_id(struct net_device *dev, u32 data)
7148{
Michael Chan972ec0d2006-01-23 16:12:43 -08007149 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007150 int i;
7151 u32 save;
7152
Michael Chan9f52b562008-10-09 12:21:46 -07007153 bnx2_set_power_state(bp, PCI_D0);
7154
Michael Chanb6016b72005-05-26 13:03:09 -07007155 if (data == 0)
7156 data = 2;
7157
7158 save = REG_RD(bp, BNX2_MISC_CFG);
7159 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7160
7161 for (i = 0; i < (data * 2); i++) {
7162 if ((i % 2) == 0) {
7163 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7164 }
7165 else {
7166 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7167 BNX2_EMAC_LED_1000MB_OVERRIDE |
7168 BNX2_EMAC_LED_100MB_OVERRIDE |
7169 BNX2_EMAC_LED_10MB_OVERRIDE |
7170 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7171 BNX2_EMAC_LED_TRAFFIC);
7172 }
7173 msleep_interruptible(500);
7174 if (signal_pending(current))
7175 break;
7176 }
7177 REG_WR(bp, BNX2_EMAC_LED, 0);
7178 REG_WR(bp, BNX2_MISC_CFG, save);
Michael Chan9f52b562008-10-09 12:21:46 -07007179
7180 if (!netif_running(dev))
7181 bnx2_set_power_state(bp, PCI_D3hot);
7182
Michael Chanb6016b72005-05-26 13:03:09 -07007183 return 0;
7184}
7185
Michael Chan4666f872007-05-03 13:22:28 -07007186static int
7187bnx2_set_tx_csum(struct net_device *dev, u32 data)
7188{
7189 struct bnx2 *bp = netdev_priv(dev);
7190
7191 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan6460d942007-07-14 19:07:52 -07007192 return (ethtool_op_set_tx_ipv6_csum(dev, data));
Michael Chan4666f872007-05-03 13:22:28 -07007193 else
7194 return (ethtool_op_set_tx_csum(dev, data));
7195}
7196
Jeff Garzik7282d492006-09-13 14:30:00 -04007197static const struct ethtool_ops bnx2_ethtool_ops = {
Michael Chanb6016b72005-05-26 13:03:09 -07007198 .get_settings = bnx2_get_settings,
7199 .set_settings = bnx2_set_settings,
7200 .get_drvinfo = bnx2_get_drvinfo,
Michael Chan244ac4f2006-03-20 17:48:46 -08007201 .get_regs_len = bnx2_get_regs_len,
7202 .get_regs = bnx2_get_regs,
Michael Chanb6016b72005-05-26 13:03:09 -07007203 .get_wol = bnx2_get_wol,
7204 .set_wol = bnx2_set_wol,
7205 .nway_reset = bnx2_nway_reset,
7206 .get_link = ethtool_op_get_link,
7207 .get_eeprom_len = bnx2_get_eeprom_len,
7208 .get_eeprom = bnx2_get_eeprom,
7209 .set_eeprom = bnx2_set_eeprom,
7210 .get_coalesce = bnx2_get_coalesce,
7211 .set_coalesce = bnx2_set_coalesce,
7212 .get_ringparam = bnx2_get_ringparam,
7213 .set_ringparam = bnx2_set_ringparam,
7214 .get_pauseparam = bnx2_get_pauseparam,
7215 .set_pauseparam = bnx2_set_pauseparam,
7216 .get_rx_csum = bnx2_get_rx_csum,
7217 .set_rx_csum = bnx2_set_rx_csum,
Michael Chan4666f872007-05-03 13:22:28 -07007218 .set_tx_csum = bnx2_set_tx_csum,
Michael Chanb6016b72005-05-26 13:03:09 -07007219 .set_sg = ethtool_op_set_sg,
Michael Chanb11d6212006-06-29 12:31:21 -07007220 .set_tso = bnx2_set_tso,
Michael Chanb6016b72005-05-26 13:03:09 -07007221 .self_test = bnx2_self_test,
7222 .get_strings = bnx2_get_strings,
7223 .phys_id = bnx2_phys_id,
Michael Chanb6016b72005-05-26 13:03:09 -07007224 .get_ethtool_stats = bnx2_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007225 .get_sset_count = bnx2_get_sset_count,
Michael Chanb6016b72005-05-26 13:03:09 -07007226};
7227
7228/* Called with rtnl_lock */
7229static int
7230bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7231{
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007232 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chan972ec0d2006-01-23 16:12:43 -08007233 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007234 int err;
7235
7236 switch(cmd) {
7237 case SIOCGMIIPHY:
7238 data->phy_id = bp->phy_addr;
7239
7240 /* fallthru */
7241 case SIOCGMIIREG: {
7242 u32 mii_regval;
7243
Michael Chan583c28e2008-01-21 19:51:35 -08007244 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007245 return -EOPNOTSUPP;
7246
Michael Chandad3e452007-05-03 13:18:03 -07007247 if (!netif_running(dev))
7248 return -EAGAIN;
7249
Michael Chanc770a652005-08-25 15:38:39 -07007250 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007251 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
Michael Chanc770a652005-08-25 15:38:39 -07007252 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007253
7254 data->val_out = mii_regval;
7255
7256 return err;
7257 }
7258
7259 case SIOCSMIIREG:
7260 if (!capable(CAP_NET_ADMIN))
7261 return -EPERM;
7262
Michael Chan583c28e2008-01-21 19:51:35 -08007263 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007264 return -EOPNOTSUPP;
7265
Michael Chandad3e452007-05-03 13:18:03 -07007266 if (!netif_running(dev))
7267 return -EAGAIN;
7268
Michael Chanc770a652005-08-25 15:38:39 -07007269 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007270 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
Michael Chanc770a652005-08-25 15:38:39 -07007271 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007272
7273 return err;
7274
7275 default:
7276 /* do nothing */
7277 break;
7278 }
7279 return -EOPNOTSUPP;
7280}
7281
7282/* Called with rtnl_lock */
7283static int
7284bnx2_change_mac_addr(struct net_device *dev, void *p)
7285{
7286 struct sockaddr *addr = p;
Michael Chan972ec0d2006-01-23 16:12:43 -08007287 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007288
Michael Chan73eef4c2005-08-25 15:39:15 -07007289 if (!is_valid_ether_addr(addr->sa_data))
7290 return -EINVAL;
7291
Michael Chanb6016b72005-05-26 13:03:09 -07007292 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7293 if (netif_running(dev))
Benjamin Li5fcaed02008-07-14 22:39:52 -07007294 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07007295
7296 return 0;
7297}
7298
7299/* Called with rtnl_lock */
7300static int
7301bnx2_change_mtu(struct net_device *dev, int new_mtu)
7302{
Michael Chan972ec0d2006-01-23 16:12:43 -08007303 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007304
7305 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7306 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7307 return -EINVAL;
7308
7309 dev->mtu = new_mtu;
Michael Chan5d5d0012007-12-12 11:17:43 -08007310 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
Michael Chanb6016b72005-05-26 13:03:09 -07007311}
7312
7313#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7314static void
7315poll_bnx2(struct net_device *dev)
7316{
Michael Chan972ec0d2006-01-23 16:12:43 -08007317 struct bnx2 *bp = netdev_priv(dev);
Neil Hormanb2af2c12008-11-12 16:23:44 -08007318 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07007319
Neil Hormanb2af2c12008-11-12 16:23:44 -08007320 for (i = 0; i < bp->irq_nvecs; i++) {
7321 disable_irq(bp->irq_tbl[i].vector);
7322 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7323 enable_irq(bp->irq_tbl[i].vector);
7324 }
Michael Chanb6016b72005-05-26 13:03:09 -07007325}
7326#endif
7327
Michael Chan253c8b72007-01-08 19:56:01 -08007328static void __devinit
7329bnx2_get_5709_media(struct bnx2 *bp)
7330{
7331 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7332 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7333 u32 strap;
7334
7335 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7336 return;
7337 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
Michael Chan583c28e2008-01-21 19:51:35 -08007338 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007339 return;
7340 }
7341
7342 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7343 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7344 else
7345 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7346
7347 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7348 switch (strap) {
7349 case 0x4:
7350 case 0x5:
7351 case 0x6:
Michael Chan583c28e2008-01-21 19:51:35 -08007352 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007353 return;
7354 }
7355 } else {
7356 switch (strap) {
7357 case 0x1:
7358 case 0x2:
7359 case 0x4:
Michael Chan583c28e2008-01-21 19:51:35 -08007360 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007361 return;
7362 }
7363 }
7364}
7365
Michael Chan883e5152007-05-03 13:25:11 -07007366static void __devinit
7367bnx2_get_pci_speed(struct bnx2 *bp)
7368{
7369 u32 reg;
7370
7371 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7372 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7373 u32 clkreg;
7374
David S. Millerf86e82f2008-01-21 17:15:40 -08007375 bp->flags |= BNX2_FLAG_PCIX;
Michael Chan883e5152007-05-03 13:25:11 -07007376
7377 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7378
7379 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7380 switch (clkreg) {
7381 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7382 bp->bus_speed_mhz = 133;
7383 break;
7384
7385 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7386 bp->bus_speed_mhz = 100;
7387 break;
7388
7389 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7390 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7391 bp->bus_speed_mhz = 66;
7392 break;
7393
7394 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7395 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7396 bp->bus_speed_mhz = 50;
7397 break;
7398
7399 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7400 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7401 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7402 bp->bus_speed_mhz = 33;
7403 break;
7404 }
7405 }
7406 else {
7407 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7408 bp->bus_speed_mhz = 66;
7409 else
7410 bp->bus_speed_mhz = 33;
7411 }
7412
7413 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
David S. Millerf86e82f2008-01-21 17:15:40 -08007414 bp->flags |= BNX2_FLAG_PCI_32BIT;
Michael Chan883e5152007-05-03 13:25:11 -07007415
7416}
7417
Michael Chanb6016b72005-05-26 13:03:09 -07007418static int __devinit
7419bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7420{
7421 struct bnx2 *bp;
7422 unsigned long mem_len;
Michael Chan58fc2ea2007-07-07 22:52:02 -07007423 int rc, i, j;
Michael Chanb6016b72005-05-26 13:03:09 -07007424 u32 reg;
Michael Chan40453c82007-05-03 13:19:18 -07007425 u64 dma_mask, persist_dma_mask;
Michael Chanb6016b72005-05-26 13:03:09 -07007426
Michael Chanb6016b72005-05-26 13:03:09 -07007427 SET_NETDEV_DEV(dev, &pdev->dev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007428 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007429
7430 bp->flags = 0;
7431 bp->phy_flags = 0;
7432
7433 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7434 rc = pci_enable_device(pdev);
7435 if (rc) {
Joe Perches898eb712007-10-18 03:06:30 -07007436 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007437 goto err_out;
7438 }
7439
7440 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007441 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007442 "Cannot find PCI device base address, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007443 rc = -ENODEV;
7444 goto err_out_disable;
7445 }
7446
7447 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7448 if (rc) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007449 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007450 goto err_out_disable;
7451 }
7452
7453 pci_set_master(pdev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007454 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007455
7456 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7457 if (bp->pm_cap == 0) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007458 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007459 "Cannot find power management capability, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007460 rc = -EIO;
7461 goto err_out_release;
7462 }
7463
Michael Chanb6016b72005-05-26 13:03:09 -07007464 bp->dev = dev;
7465 bp->pdev = pdev;
7466
7467 spin_lock_init(&bp->phy_lock);
Michael Chan1b8227c2007-05-03 13:24:05 -07007468 spin_lock_init(&bp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +00007469 INIT_WORK(&bp->reset_task, bnx2_reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07007470
7471 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
Benjamin Li706bf242008-07-18 17:55:11 -07007472 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07007473 dev->mem_end = dev->mem_start + mem_len;
7474 dev->irq = pdev->irq;
7475
7476 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7477
7478 if (!bp->regview) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007479 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007480 rc = -ENOMEM;
7481 goto err_out_release;
7482 }
7483
7484 /* Configure byte swap and enable write to the reg_window registers.
7485 * Rely on CPU to do target byte swapping on big endian systems
7486 * The chip's target access swapping will not swap all accesses
7487 */
7488 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7489 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7490 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7491
Pavel Machek829ca9a2005-09-03 15:56:56 -07007492 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007493
7494 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7495
Michael Chan883e5152007-05-03 13:25:11 -07007496 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7497 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7498 dev_err(&pdev->dev,
7499 "Cannot find PCIE capability, aborting.\n");
7500 rc = -EIO;
7501 goto err_out_unmap;
7502 }
David S. Millerf86e82f2008-01-21 17:15:40 -08007503 bp->flags |= BNX2_FLAG_PCIE;
Michael Chan2dd201d2008-01-21 17:06:09 -08007504 if (CHIP_REV(bp) == CHIP_REV_Ax)
David S. Millerf86e82f2008-01-21 17:15:40 -08007505 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
Michael Chan883e5152007-05-03 13:25:11 -07007506 } else {
Michael Chan59b47d82006-11-19 14:10:45 -08007507 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7508 if (bp->pcix_cap == 0) {
7509 dev_err(&pdev->dev,
7510 "Cannot find PCIX capability, aborting.\n");
7511 rc = -EIO;
7512 goto err_out_unmap;
7513 }
7514 }
7515
Michael Chanb4b36042007-12-20 19:59:30 -08007516 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7517 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
David S. Millerf86e82f2008-01-21 17:15:40 -08007518 bp->flags |= BNX2_FLAG_MSIX_CAP;
Michael Chanb4b36042007-12-20 19:59:30 -08007519 }
7520
Michael Chan8e6a72c2007-05-03 13:24:48 -07007521 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7522 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
David S. Millerf86e82f2008-01-21 17:15:40 -08007523 bp->flags |= BNX2_FLAG_MSI_CAP;
Michael Chan8e6a72c2007-05-03 13:24:48 -07007524 }
7525
Michael Chan40453c82007-05-03 13:19:18 -07007526 /* 5708 cannot support DMA addresses > 40-bit. */
7527 if (CHIP_NUM(bp) == CHIP_NUM_5708)
Yang Hongyang50cf1562009-04-06 19:01:14 -07007528 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan40453c82007-05-03 13:19:18 -07007529 else
Yang Hongyang6a355282009-04-06 19:01:13 -07007530 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan40453c82007-05-03 13:19:18 -07007531
7532 /* Configure DMA attributes. */
7533 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7534 dev->features |= NETIF_F_HIGHDMA;
7535 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7536 if (rc) {
7537 dev_err(&pdev->dev,
7538 "pci_set_consistent_dma_mask failed, aborting.\n");
7539 goto err_out_unmap;
7540 }
7541 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7542 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7543 goto err_out_unmap;
7544 }
7545
David S. Millerf86e82f2008-01-21 17:15:40 -08007546 if (!(bp->flags & BNX2_FLAG_PCIE))
Michael Chan883e5152007-05-03 13:25:11 -07007547 bnx2_get_pci_speed(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007548
7549 /* 5706A0 may falsely detect SERR and PERR. */
7550 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7551 reg = REG_RD(bp, PCI_COMMAND);
7552 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7553 REG_WR(bp, PCI_COMMAND, reg);
7554 }
7555 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08007556 !(bp->flags & BNX2_FLAG_PCIX)) {
Michael Chanb6016b72005-05-26 13:03:09 -07007557
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007558 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007559 "5706 A1 can only be used in a PCIX bus, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007560 goto err_out_unmap;
7561 }
7562
7563 bnx2_init_nvram(bp);
7564
Michael Chan2726d6e2008-01-29 21:35:05 -08007565 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
Michael Chane3648b32005-11-04 08:51:21 -08007566
7567 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
Michael Chan24cb2302007-01-25 15:49:56 -08007568 BNX2_SHM_HDR_SIGNATURE_SIG) {
7569 u32 off = PCI_FUNC(pdev->devfn) << 2;
7570
Michael Chan2726d6e2008-01-29 21:35:05 -08007571 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
Michael Chan24cb2302007-01-25 15:49:56 -08007572 } else
Michael Chane3648b32005-11-04 08:51:21 -08007573 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7574
Michael Chanb6016b72005-05-26 13:03:09 -07007575 /* Get the permanent MAC address. First we need to make sure the
7576 * firmware is actually running.
7577 */
Michael Chan2726d6e2008-01-29 21:35:05 -08007578 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
Michael Chanb6016b72005-05-26 13:03:09 -07007579
7580 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7581 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007582 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007583 rc = -ENODEV;
7584 goto err_out_unmap;
7585 }
7586
Michael Chan2726d6e2008-01-29 21:35:05 -08007587 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007588 for (i = 0, j = 0; i < 3; i++) {
7589 u8 num, k, skip0;
7590
7591 num = (u8) (reg >> (24 - (i * 8)));
7592 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7593 if (num >= k || !skip0 || k == 1) {
7594 bp->fw_version[j++] = (num / k) + '0';
7595 skip0 = 0;
7596 }
7597 }
7598 if (i != 2)
7599 bp->fw_version[j++] = '.';
7600 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007601 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
Michael Chan846f5c62007-10-10 16:16:51 -07007602 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7603 bp->wol = 1;
7604
7605 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007606 bp->flags |= BNX2_FLAG_ASF_ENABLE;
Michael Chanc2d3db82007-07-16 18:26:43 -07007607
7608 for (i = 0; i < 30; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007609 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chanc2d3db82007-07-16 18:26:43 -07007610 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7611 break;
7612 msleep(10);
7613 }
7614 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007615 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007616 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7617 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7618 reg != BNX2_CONDITION_MFW_RUN_NONE) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007619 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007620
7621 bp->fw_version[j++] = ' ';
7622 for (i = 0; i < 3; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007623 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007624 reg = swab32(reg);
7625 memcpy(&bp->fw_version[j], &reg, 4);
7626 j += 4;
7627 }
7628 }
Michael Chanb6016b72005-05-26 13:03:09 -07007629
Michael Chan2726d6e2008-01-29 21:35:05 -08007630 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
Michael Chanb6016b72005-05-26 13:03:09 -07007631 bp->mac_addr[0] = (u8) (reg >> 8);
7632 bp->mac_addr[1] = (u8) reg;
7633
Michael Chan2726d6e2008-01-29 21:35:05 -08007634 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
Michael Chanb6016b72005-05-26 13:03:09 -07007635 bp->mac_addr[2] = (u8) (reg >> 24);
7636 bp->mac_addr[3] = (u8) (reg >> 16);
7637 bp->mac_addr[4] = (u8) (reg >> 8);
7638 bp->mac_addr[5] = (u8) reg;
7639
7640 bp->tx_ring_size = MAX_TX_DESC_CNT;
Michael Chan932f3772006-08-15 01:39:36 -07007641 bnx2_set_rx_ring_size(bp, 255);
Michael Chanb6016b72005-05-26 13:03:09 -07007642
7643 bp->rx_csum = 1;
7644
Michael Chanb6016b72005-05-26 13:03:09 -07007645 bp->tx_quick_cons_trip_int = 20;
7646 bp->tx_quick_cons_trip = 20;
7647 bp->tx_ticks_int = 80;
7648 bp->tx_ticks = 80;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007649
Michael Chanb6016b72005-05-26 13:03:09 -07007650 bp->rx_quick_cons_trip_int = 6;
7651 bp->rx_quick_cons_trip = 6;
7652 bp->rx_ticks_int = 18;
7653 bp->rx_ticks = 18;
7654
Michael Chan7ea69202007-07-16 18:27:10 -07007655 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007656
Benjamin Liac392ab2008-09-18 16:40:49 -07007657 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07007658
Michael Chan5b0c76a2005-11-04 08:45:49 -08007659 bp->phy_addr = 1;
7660
Michael Chanb6016b72005-05-26 13:03:09 -07007661 /* Disable WOL support if we are running on a SERDES chip. */
Michael Chan253c8b72007-01-08 19:56:01 -08007662 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7663 bnx2_get_5709_media(bp);
7664 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
Michael Chan583c28e2008-01-21 19:51:35 -08007665 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chanbac0dff2006-11-19 14:15:05 -08007666
Michael Chan0d8a6572007-07-07 22:49:43 -07007667 bp->phy_port = PORT_TP;
Michael Chan583c28e2008-01-21 19:51:35 -08007668 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07007669 bp->phy_port = PORT_FIBRE;
Michael Chan2726d6e2008-01-29 21:35:05 -08007670 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan846f5c62007-10-10 16:16:51 -07007671 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007672 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007673 bp->wol = 0;
7674 }
Michael Chan38ea3682008-02-23 19:48:57 -08007675 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7676 /* Don't do parallel detect on this board because of
7677 * some board problems. The link will not go down
7678 * if we do parallel detect.
7679 */
7680 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7681 pdev->subsystem_device == 0x310c)
7682 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7683 } else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08007684 bp->phy_addr = 2;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007685 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
Michael Chan583c28e2008-01-21 19:51:35 -08007686 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007687 }
Michael Chan261dd5c2007-01-08 19:55:46 -08007688 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7689 CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan583c28e2008-01-21 19:51:35 -08007690 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
Michael Chanfb0c18b2007-12-10 17:18:23 -08007691 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7692 (CHIP_REV(bp) == CHIP_REV_Ax ||
7693 CHIP_REV(bp) == CHIP_REV_Bx))
Michael Chan583c28e2008-01-21 19:51:35 -08007694 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
Michael Chanb6016b72005-05-26 13:03:09 -07007695
Michael Chan7c62e832008-07-14 22:39:03 -07007696 bnx2_init_fw_cap(bp);
7697
Michael Chan16088272006-06-12 22:16:43 -07007698 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7699 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
Michael Chan5ec6d7b2008-11-12 16:01:41 -08007700 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7701 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007702 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007703 bp->wol = 0;
7704 }
Michael Chandda1e392006-01-23 16:08:14 -08007705
Michael Chanb6016b72005-05-26 13:03:09 -07007706 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7707 bp->tx_quick_cons_trip_int =
7708 bp->tx_quick_cons_trip;
7709 bp->tx_ticks_int = bp->tx_ticks;
7710 bp->rx_quick_cons_trip_int =
7711 bp->rx_quick_cons_trip;
7712 bp->rx_ticks_int = bp->rx_ticks;
7713 bp->comp_prod_trip_int = bp->comp_prod_trip;
7714 bp->com_ticks_int = bp->com_ticks;
7715 bp->cmd_ticks_int = bp->cmd_ticks;
7716 }
7717
Michael Chanf9317a42006-09-29 17:06:23 -07007718 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7719 *
7720 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7721 * with byte enables disabled on the unused 32-bit word. This is legal
7722 * but causes problems on the AMD 8132 which will eventually stop
7723 * responding after a while.
7724 *
7725 * AMD believes this incompatibility is unique to the 5706, and
Michael Ellerman88187df2007-01-25 19:34:07 +11007726 * prefers to locally disable MSI rather than globally disabling it.
Michael Chanf9317a42006-09-29 17:06:23 -07007727 */
7728 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7729 struct pci_dev *amd_8132 = NULL;
7730
7731 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7732 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7733 amd_8132))) {
Michael Chanf9317a42006-09-29 17:06:23 -07007734
Auke Kok44c10132007-06-08 15:46:36 -07007735 if (amd_8132->revision >= 0x10 &&
7736 amd_8132->revision <= 0x13) {
Michael Chanf9317a42006-09-29 17:06:23 -07007737 disable_msi = 1;
7738 pci_dev_put(amd_8132);
7739 break;
7740 }
7741 }
7742 }
7743
Michael Chandeaf3912007-07-07 22:48:00 -07007744 bnx2_set_default_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007745 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7746
Michael Chancd339a02005-08-25 15:35:24 -07007747 init_timer(&bp->timer);
Benjamin Liac392ab2008-09-18 16:40:49 -07007748 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
Michael Chancd339a02005-08-25 15:35:24 -07007749 bp->timer.data = (unsigned long) bp;
7750 bp->timer.function = bnx2_timer;
7751
Michael Chanb6016b72005-05-26 13:03:09 -07007752 return 0;
7753
7754err_out_unmap:
7755 if (bp->regview) {
7756 iounmap(bp->regview);
Michael Chan73eef4c2005-08-25 15:39:15 -07007757 bp->regview = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007758 }
7759
7760err_out_release:
7761 pci_release_regions(pdev);
7762
7763err_out_disable:
7764 pci_disable_device(pdev);
7765 pci_set_drvdata(pdev, NULL);
7766
7767err_out:
7768 return rc;
7769}
7770
Michael Chan883e5152007-05-03 13:25:11 -07007771static char * __devinit
7772bnx2_bus_string(struct bnx2 *bp, char *str)
7773{
7774 char *s = str;
7775
David S. Millerf86e82f2008-01-21 17:15:40 -08007776 if (bp->flags & BNX2_FLAG_PCIE) {
Michael Chan883e5152007-05-03 13:25:11 -07007777 s += sprintf(s, "PCI Express");
7778 } else {
7779 s += sprintf(s, "PCI");
David S. Millerf86e82f2008-01-21 17:15:40 -08007780 if (bp->flags & BNX2_FLAG_PCIX)
Michael Chan883e5152007-05-03 13:25:11 -07007781 s += sprintf(s, "-X");
David S. Millerf86e82f2008-01-21 17:15:40 -08007782 if (bp->flags & BNX2_FLAG_PCI_32BIT)
Michael Chan883e5152007-05-03 13:25:11 -07007783 s += sprintf(s, " 32-bit");
7784 else
7785 s += sprintf(s, " 64-bit");
7786 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7787 }
7788 return str;
7789}
7790
Michael Chan2ba582b2007-12-21 15:04:49 -08007791static void __devinit
Michael Chan35efa7c2007-12-20 19:56:37 -08007792bnx2_init_napi(struct bnx2 *bp)
7793{
Michael Chanb4b36042007-12-20 19:59:30 -08007794 int i;
Michael Chan35efa7c2007-12-20 19:56:37 -08007795
Michael Chanb4b36042007-12-20 19:59:30 -08007796 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan35e90102008-06-19 16:37:42 -07007797 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7798 int (*poll)(struct napi_struct *, int);
7799
7800 if (i == 0)
7801 poll = bnx2_poll;
7802 else
Michael Chanf0ea2e62008-06-19 16:41:57 -07007803 poll = bnx2_poll_msix;
Michael Chan35e90102008-06-19 16:37:42 -07007804
7805 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
Michael Chanb4b36042007-12-20 19:59:30 -08007806 bnapi->bp = bp;
7807 }
Michael Chan35efa7c2007-12-20 19:56:37 -08007808}
7809
Stephen Hemminger0421eae2008-11-21 17:31:27 -08007810static const struct net_device_ops bnx2_netdev_ops = {
7811 .ndo_open = bnx2_open,
7812 .ndo_start_xmit = bnx2_start_xmit,
7813 .ndo_stop = bnx2_close,
7814 .ndo_get_stats = bnx2_get_stats,
7815 .ndo_set_rx_mode = bnx2_set_rx_mode,
7816 .ndo_do_ioctl = bnx2_ioctl,
7817 .ndo_validate_addr = eth_validate_addr,
7818 .ndo_set_mac_address = bnx2_change_mac_addr,
7819 .ndo_change_mtu = bnx2_change_mtu,
7820 .ndo_tx_timeout = bnx2_tx_timeout,
7821#ifdef BCM_VLAN
7822 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
7823#endif
7824#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7825 .ndo_poll_controller = poll_bnx2,
7826#endif
7827};
7828
Michael Chan35efa7c2007-12-20 19:56:37 -08007829static int __devinit
Michael Chanb6016b72005-05-26 13:03:09 -07007830bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7831{
7832 static int version_printed = 0;
7833 struct net_device *dev = NULL;
7834 struct bnx2 *bp;
Joe Perches0795af52007-10-03 17:59:30 -07007835 int rc;
Michael Chan883e5152007-05-03 13:25:11 -07007836 char str[40];
Michael Chanb6016b72005-05-26 13:03:09 -07007837
7838 if (version_printed++ == 0)
7839 printk(KERN_INFO "%s", version);
7840
7841 /* dev zeroed in init_etherdev */
Benjamin Li706bf242008-07-18 17:55:11 -07007842 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07007843
7844 if (!dev)
7845 return -ENOMEM;
7846
7847 rc = bnx2_init_board(pdev, dev);
7848 if (rc < 0) {
7849 free_netdev(dev);
7850 return rc;
7851 }
7852
Stephen Hemminger0421eae2008-11-21 17:31:27 -08007853 dev->netdev_ops = &bnx2_netdev_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07007854 dev->watchdog_timeo = TX_TIMEOUT;
Michael Chanb6016b72005-05-26 13:03:09 -07007855 dev->ethtool_ops = &bnx2_ethtool_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07007856
Michael Chan972ec0d2006-01-23 16:12:43 -08007857 bp = netdev_priv(dev);
Michael Chan35efa7c2007-12-20 19:56:37 -08007858 bnx2_init_napi(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007859
Michael Chan1b2f9222007-05-03 13:20:19 -07007860 pci_set_drvdata(pdev, dev);
7861
Michael Chan57579f72009-04-04 16:51:14 -07007862 rc = bnx2_request_firmware(bp);
7863 if (rc)
7864 goto error;
7865
Michael Chan1b2f9222007-05-03 13:20:19 -07007866 memcpy(dev->dev_addr, bp->mac_addr, 6);
7867 memcpy(dev->perm_addr, bp->mac_addr, 6);
Michael Chan1b2f9222007-05-03 13:20:19 -07007868
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007869 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Michael Chan4666f872007-05-03 13:22:28 -07007870 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007871 dev->features |= NETIF_F_IPV6_CSUM;
7872
Michael Chan1b2f9222007-05-03 13:20:19 -07007873#ifdef BCM_VLAN
7874 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7875#endif
7876 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07007877 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7878 dev->features |= NETIF_F_TSO6;
Michael Chan1b2f9222007-05-03 13:20:19 -07007879
Michael Chanb6016b72005-05-26 13:03:09 -07007880 if ((rc = register_netdev(dev))) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007881 dev_err(&pdev->dev, "Cannot register net device\n");
Michael Chan57579f72009-04-04 16:51:14 -07007882 goto error;
Michael Chanb6016b72005-05-26 13:03:09 -07007883 }
7884
Michael Chan883e5152007-05-03 13:25:11 -07007885 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
Johannes Berge1749612008-10-27 15:59:26 -07007886 "IRQ %d, node addr %pM\n",
Michael Chanb6016b72005-05-26 13:03:09 -07007887 dev->name,
Benjamin Lifbbf68b2008-09-18 16:40:03 -07007888 board_info[ent->driver_data].name,
Michael Chanb6016b72005-05-26 13:03:09 -07007889 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7890 ((CHIP_ID(bp) & 0x0ff0) >> 4),
Michael Chan883e5152007-05-03 13:25:11 -07007891 bnx2_bus_string(bp, str),
Michael Chanb6016b72005-05-26 13:03:09 -07007892 dev->base_addr,
Johannes Berge1749612008-10-27 15:59:26 -07007893 bp->pdev->irq, dev->dev_addr);
Michael Chanb6016b72005-05-26 13:03:09 -07007894
Michael Chanb6016b72005-05-26 13:03:09 -07007895 return 0;
Michael Chan57579f72009-04-04 16:51:14 -07007896
7897error:
7898 if (bp->mips_firmware)
7899 release_firmware(bp->mips_firmware);
7900 if (bp->rv2p_firmware)
7901 release_firmware(bp->rv2p_firmware);
7902
7903 if (bp->regview)
7904 iounmap(bp->regview);
7905 pci_release_regions(pdev);
7906 pci_disable_device(pdev);
7907 pci_set_drvdata(pdev, NULL);
7908 free_netdev(dev);
7909 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07007910}
7911
7912static void __devexit
7913bnx2_remove_one(struct pci_dev *pdev)
7914{
7915 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007916 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007917
Michael Chanafdc08b2005-08-25 15:34:29 -07007918 flush_scheduled_work();
7919
Michael Chanb6016b72005-05-26 13:03:09 -07007920 unregister_netdev(dev);
7921
Michael Chan57579f72009-04-04 16:51:14 -07007922 if (bp->mips_firmware)
7923 release_firmware(bp->mips_firmware);
7924 if (bp->rv2p_firmware)
7925 release_firmware(bp->rv2p_firmware);
7926
Michael Chanb6016b72005-05-26 13:03:09 -07007927 if (bp->regview)
7928 iounmap(bp->regview);
7929
7930 free_netdev(dev);
7931 pci_release_regions(pdev);
7932 pci_disable_device(pdev);
7933 pci_set_drvdata(pdev, NULL);
7934}
7935
7936static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07007937bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07007938{
7939 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007940 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007941
Michael Chan6caebb02007-08-03 20:57:25 -07007942 /* PCI register 4 needs to be saved whether netif_running() or not.
7943 * MSI address and data need to be saved if using MSI and
7944 * netif_running().
7945 */
7946 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007947 if (!netif_running(dev))
7948 return 0;
7949
Michael Chan1d60290f2006-03-20 17:50:08 -08007950 flush_scheduled_work();
Michael Chanb6016b72005-05-26 13:03:09 -07007951 bnx2_netif_stop(bp);
7952 netif_device_detach(dev);
7953 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07007954 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007955 bnx2_free_skbs(bp);
Pavel Machek829ca9a2005-09-03 15:56:56 -07007956 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
Michael Chanb6016b72005-05-26 13:03:09 -07007957 return 0;
7958}
7959
7960static int
7961bnx2_resume(struct pci_dev *pdev)
7962{
7963 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007964 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007965
Michael Chan6caebb02007-08-03 20:57:25 -07007966 pci_restore_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007967 if (!netif_running(dev))
7968 return 0;
7969
Pavel Machek829ca9a2005-09-03 15:56:56 -07007970 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007971 netif_device_attach(dev);
Michael Chan9a120bc2008-05-16 22:17:45 -07007972 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007973 bnx2_netif_start(bp);
7974 return 0;
7975}
7976
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007977/**
7978 * bnx2_io_error_detected - called when PCI error is detected
7979 * @pdev: Pointer to PCI device
7980 * @state: The current pci connection state
7981 *
7982 * This function is called after a PCI bus error affecting
7983 * this device has been detected.
7984 */
7985static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7986 pci_channel_state_t state)
7987{
7988 struct net_device *dev = pci_get_drvdata(pdev);
7989 struct bnx2 *bp = netdev_priv(dev);
7990
7991 rtnl_lock();
7992 netif_device_detach(dev);
7993
7994 if (netif_running(dev)) {
7995 bnx2_netif_stop(bp);
7996 del_timer_sync(&bp->timer);
7997 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7998 }
7999
8000 pci_disable_device(pdev);
8001 rtnl_unlock();
8002
8003 /* Request a slot slot reset. */
8004 return PCI_ERS_RESULT_NEED_RESET;
8005}
8006
8007/**
8008 * bnx2_io_slot_reset - called after the pci bus has been reset.
8009 * @pdev: Pointer to PCI device
8010 *
8011 * Restart the card from scratch, as if from a cold-boot.
8012 */
8013static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8014{
8015 struct net_device *dev = pci_get_drvdata(pdev);
8016 struct bnx2 *bp = netdev_priv(dev);
8017
8018 rtnl_lock();
8019 if (pci_enable_device(pdev)) {
8020 dev_err(&pdev->dev,
8021 "Cannot re-enable PCI device after reset.\n");
8022 rtnl_unlock();
8023 return PCI_ERS_RESULT_DISCONNECT;
8024 }
8025 pci_set_master(pdev);
8026 pci_restore_state(pdev);
8027
8028 if (netif_running(dev)) {
8029 bnx2_set_power_state(bp, PCI_D0);
8030 bnx2_init_nic(bp, 1);
8031 }
8032
8033 rtnl_unlock();
8034 return PCI_ERS_RESULT_RECOVERED;
8035}
8036
8037/**
8038 * bnx2_io_resume - called when traffic can start flowing again.
8039 * @pdev: Pointer to PCI device
8040 *
8041 * This callback is called when the error recovery driver tells us that
8042 * its OK to resume normal operation.
8043 */
8044static void bnx2_io_resume(struct pci_dev *pdev)
8045{
8046 struct net_device *dev = pci_get_drvdata(pdev);
8047 struct bnx2 *bp = netdev_priv(dev);
8048
8049 rtnl_lock();
8050 if (netif_running(dev))
8051 bnx2_netif_start(bp);
8052
8053 netif_device_attach(dev);
8054 rtnl_unlock();
8055}
8056
8057static struct pci_error_handlers bnx2_err_handler = {
8058 .error_detected = bnx2_io_error_detected,
8059 .slot_reset = bnx2_io_slot_reset,
8060 .resume = bnx2_io_resume,
8061};
8062
Michael Chanb6016b72005-05-26 13:03:09 -07008063static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -07008064 .name = DRV_MODULE_NAME,
8065 .id_table = bnx2_pci_tbl,
8066 .probe = bnx2_init_one,
8067 .remove = __devexit_p(bnx2_remove_one),
8068 .suspend = bnx2_suspend,
8069 .resume = bnx2_resume,
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008070 .err_handler = &bnx2_err_handler,
Michael Chanb6016b72005-05-26 13:03:09 -07008071};
8072
8073static int __init bnx2_init(void)
8074{
Jeff Garzik29917622006-08-19 17:48:59 -04008075 return pci_register_driver(&bnx2_pci_driver);
Michael Chanb6016b72005-05-26 13:03:09 -07008076}
8077
8078static void __exit bnx2_cleanup(void)
8079{
8080 pci_unregister_driver(&bnx2_pci_driver);
8081}
8082
8083module_init(bnx2_init);
8084module_exit(bnx2_cleanup);
8085
8086
8087