Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Paul Gortmaker | 355b200 | 2011-07-03 16:17:28 -0400 | [diff] [blame] | 30 | #include <linux/module.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 31 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 32 | #include <linux/seq_file.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 35 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 36 | #include <linux/workqueue.h> |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 37 | #include <linux/sched.h> |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 38 | #include <linux/slab.h> |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 39 | #include <linux/debugfs.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 40 | #include <linux/pm_runtime.h> |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 41 | #include <linux/of.h> |
| 42 | #include <linux/of_platform.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 43 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 44 | #include <video/omapdss.h> |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 45 | #include <video/mipi_display.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 46 | |
| 47 | #include "dss.h" |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 48 | #include "dss_features.h" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 49 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 50 | #define DSI_CATCH_MISSING_TE |
| 51 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 52 | struct dsi_reg { u16 module; u16 idx; }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 53 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 54 | #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 55 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 56 | /* DSI Protocol Engine */ |
| 57 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 58 | #define DSI_PROTO 0 |
| 59 | #define DSI_PROTO_SZ 0x200 |
| 60 | |
| 61 | #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) |
| 62 | #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) |
| 63 | #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) |
| 64 | #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) |
| 65 | #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) |
| 66 | #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) |
| 67 | #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) |
| 68 | #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) |
| 69 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) |
| 70 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) |
| 71 | #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) |
| 72 | #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) |
| 73 | #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) |
| 74 | #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) |
| 75 | #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) |
| 76 | #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) |
| 77 | #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) |
| 78 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) |
| 79 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) |
| 80 | #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) |
| 81 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) |
| 82 | #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) |
| 83 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) |
| 84 | #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) |
| 85 | #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) |
| 86 | #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) |
| 87 | #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) |
| 88 | #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) |
| 89 | #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) |
| 90 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) |
| 91 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) |
| 92 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) |
| 93 | #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) |
| 94 | #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 95 | |
| 96 | /* DSIPHY_SCP */ |
| 97 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 98 | #define DSI_PHY 1 |
| 99 | #define DSI_PHY_OFFSET 0x200 |
| 100 | #define DSI_PHY_SZ 0x40 |
| 101 | |
| 102 | #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) |
| 103 | #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) |
| 104 | #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) |
| 105 | #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) |
| 106 | #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 107 | |
| 108 | /* DSI_PLL_CTRL_SCP */ |
| 109 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 110 | #define DSI_PLL 2 |
| 111 | #define DSI_PLL_OFFSET 0x300 |
| 112 | #define DSI_PLL_SZ 0x20 |
| 113 | |
| 114 | #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) |
| 115 | #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) |
| 116 | #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) |
| 117 | #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) |
| 118 | #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 119 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 120 | #define REG_GET(dsidev, idx, start, end) \ |
| 121 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 122 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 123 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
| 124 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 125 | |
| 126 | /* Global interrupts */ |
| 127 | #define DSI_IRQ_VC0 (1 << 0) |
| 128 | #define DSI_IRQ_VC1 (1 << 1) |
| 129 | #define DSI_IRQ_VC2 (1 << 2) |
| 130 | #define DSI_IRQ_VC3 (1 << 3) |
| 131 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 132 | #define DSI_IRQ_RESYNC (1 << 5) |
| 133 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 134 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 135 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 136 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 137 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 138 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 139 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 140 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 141 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 142 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 143 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 144 | #define DSI_IRQ_ERROR_MASK \ |
| 145 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 146 | DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 147 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 148 | |
| 149 | /* Virtual channel interrupts */ |
| 150 | #define DSI_VC_IRQ_CS (1 << 0) |
| 151 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 152 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 153 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 154 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 155 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 156 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 157 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 158 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 159 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 160 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 161 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 162 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 163 | |
| 164 | /* ComplexIO interrupts */ |
| 165 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 166 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 167 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 168 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
| 169 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 170 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 171 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 172 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 173 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
| 174 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 175 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 176 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 177 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 178 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
| 179 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 180 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 181 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 182 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 183 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
| 184 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 185 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 186 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 187 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 188 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 189 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 190 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 191 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
| 192 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) |
| 193 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) |
| 194 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 195 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 196 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 197 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 198 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 199 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
| 200 | DSI_CIO_IRQ_ERRSYNCESC5 | \ |
| 201 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 202 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ |
| 203 | DSI_CIO_IRQ_ERRESC5 | \ |
| 204 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ |
| 205 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ |
| 206 | DSI_CIO_IRQ_ERRCONTROL5 | \ |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 207 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 208 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 209 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
| 210 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ |
| 211 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 212 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 213 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
| 214 | |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 215 | static int dsi_display_init_dispc(struct platform_device *dsidev, |
| 216 | struct omap_overlay_manager *mgr); |
| 217 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, |
| 218 | struct omap_overlay_manager *mgr); |
| 219 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 220 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); |
| 221 | |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 222 | /* DSI PLL HSDIV indices */ |
| 223 | #define HSDIV_DISPC 0 |
| 224 | #define HSDIV_DSI 1 |
| 225 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 226 | #define DSI_MAX_NR_ISRS 2 |
Tomi Valkeinen | 739a7f4 | 2011-10-13 11:22:06 +0300 | [diff] [blame] | 227 | #define DSI_MAX_NR_LANES 5 |
| 228 | |
| 229 | enum dsi_lane_function { |
| 230 | DSI_LANE_UNUSED = 0, |
| 231 | DSI_LANE_CLK, |
| 232 | DSI_LANE_DATA1, |
| 233 | DSI_LANE_DATA2, |
| 234 | DSI_LANE_DATA3, |
| 235 | DSI_LANE_DATA4, |
| 236 | }; |
| 237 | |
| 238 | struct dsi_lane_config { |
| 239 | enum dsi_lane_function function; |
| 240 | u8 polarity; |
| 241 | }; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 242 | |
| 243 | struct dsi_isr_data { |
| 244 | omap_dsi_isr_t isr; |
| 245 | void *arg; |
| 246 | u32 mask; |
| 247 | }; |
| 248 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 249 | enum fifo_size { |
| 250 | DSI_FIFO_SIZE_0 = 0, |
| 251 | DSI_FIFO_SIZE_32 = 1, |
| 252 | DSI_FIFO_SIZE_64 = 2, |
| 253 | DSI_FIFO_SIZE_96 = 3, |
| 254 | DSI_FIFO_SIZE_128 = 4, |
| 255 | }; |
| 256 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 257 | enum dsi_vc_source { |
| 258 | DSI_VC_SOURCE_L4 = 0, |
| 259 | DSI_VC_SOURCE_VP, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 260 | }; |
| 261 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 262 | struct dsi_irq_stats { |
| 263 | unsigned long last_reset; |
| 264 | unsigned irq_count; |
| 265 | unsigned dsi_irqs[32]; |
| 266 | unsigned vc_irqs[4][32]; |
| 267 | unsigned cio_irqs[32]; |
| 268 | }; |
| 269 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 270 | struct dsi_isr_tables { |
| 271 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; |
| 272 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; |
| 273 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; |
| 274 | }; |
| 275 | |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 276 | struct dsi_clk_calc_ctx { |
| 277 | struct platform_device *dsidev; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 278 | struct dss_pll *pll; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 279 | |
| 280 | /* inputs */ |
| 281 | |
| 282 | const struct omap_dss_dsi_config *config; |
| 283 | |
| 284 | unsigned long req_pck_min, req_pck_nom, req_pck_max; |
| 285 | |
| 286 | /* outputs */ |
| 287 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 288 | struct dss_pll_clock_info dsi_cinfo; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 289 | struct dispc_clock_info dispc_cinfo; |
| 290 | |
| 291 | struct omap_video_timings dispc_vm; |
| 292 | struct omap_dss_dsi_videomode_timings dsi_vm; |
| 293 | }; |
| 294 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 295 | struct dsi_lp_clock_info { |
| 296 | unsigned long lp_clk; |
| 297 | u16 lp_clk_div; |
| 298 | }; |
| 299 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 300 | struct dsi_data { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 301 | struct platform_device *pdev; |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 302 | void __iomem *proto_base; |
| 303 | void __iomem *phy_base; |
| 304 | void __iomem *pll_base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 305 | |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 306 | int module_id; |
| 307 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 308 | int irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 309 | |
Tomi Valkeinen | 0925afc | 2014-04-11 13:49:55 +0300 | [diff] [blame] | 310 | bool is_enabled; |
| 311 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 312 | struct clk *dss_clk; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 313 | |
Tomi Valkeinen | a0d269e | 2012-11-27 17:05:54 +0200 | [diff] [blame] | 314 | struct dispc_clock_info user_dispc_cinfo; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 315 | struct dss_pll_clock_info user_dsi_cinfo; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 316 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 317 | struct dsi_lp_clock_info user_lp_cinfo; |
| 318 | struct dsi_lp_clock_info current_lp_cinfo; |
| 319 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 320 | struct dss_pll pll; |
| 321 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 322 | bool vdds_dsi_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 323 | struct regulator *vdds_dsi_reg; |
| 324 | |
| 325 | struct { |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 326 | enum dsi_vc_source source; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 327 | struct omap_dss_device *dssdev; |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 328 | enum fifo_size tx_fifo_size; |
| 329 | enum fifo_size rx_fifo_size; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 330 | int vc_id; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 331 | } vc[4]; |
| 332 | |
| 333 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 334 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 335 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 336 | spinlock_t irq_lock; |
| 337 | struct dsi_isr_tables isr_tables; |
| 338 | /* space for a copy used by the interrupt handler */ |
| 339 | struct dsi_isr_tables isr_tables_copy; |
| 340 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 341 | int update_channel; |
Tomi Valkeinen | 477fed7 | 2013-10-02 14:41:24 +0300 | [diff] [blame] | 342 | #ifdef DSI_PERF_MEASURE |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 343 | unsigned update_bytes; |
| 344 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 345 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 346 | bool te_enabled; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 347 | bool ulps_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 348 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 349 | void (*framedone_callback)(int, void *); |
| 350 | void *framedone_data; |
| 351 | |
| 352 | struct delayed_work framedone_timeout_work; |
| 353 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 354 | #ifdef DSI_CATCH_MISSING_TE |
| 355 | struct timer_list te_timer; |
| 356 | #endif |
| 357 | |
| 358 | unsigned long cache_req_pck; |
| 359 | unsigned long cache_clk_freq; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 360 | struct dss_pll_clock_info cache_cinfo; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 361 | |
| 362 | u32 errors; |
| 363 | spinlock_t errors_lock; |
Tomi Valkeinen | 477fed7 | 2013-10-02 14:41:24 +0300 | [diff] [blame] | 364 | #ifdef DSI_PERF_MEASURE |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 365 | ktime_t perf_setup_time; |
| 366 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 367 | #endif |
| 368 | int debug_read; |
| 369 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 370 | |
| 371 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 372 | spinlock_t irq_stats_lock; |
| 373 | struct dsi_irq_stats irq_stats; |
| 374 | #endif |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 375 | |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 376 | unsigned num_lanes_supported; |
Tomi Valkeinen | 9932257 | 2013-03-05 10:37:02 +0200 | [diff] [blame] | 377 | unsigned line_buffer_size; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 378 | |
Tomi Valkeinen | 739a7f4 | 2011-10-13 11:22:06 +0300 | [diff] [blame] | 379 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
| 380 | unsigned num_lanes_used; |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 381 | |
| 382 | unsigned scp_clk_refcount; |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 383 | |
| 384 | struct dss_lcd_mgr_config mgr_config; |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 385 | struct omap_video_timings timings; |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 386 | enum omap_dss_dsi_pixel_format pix_fmt; |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 387 | enum omap_dss_dsi_mode mode; |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 388 | struct omap_dss_dsi_videomode_timings vm_timings; |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 389 | |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 390 | struct omap_dss_device output; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 391 | }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 392 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 393 | struct dsi_packet_sent_handler_data { |
| 394 | struct platform_device *dsidev; |
| 395 | struct completion *completion; |
| 396 | }; |
| 397 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 398 | struct dsi_module_id_data { |
| 399 | u32 address; |
| 400 | int id; |
| 401 | }; |
| 402 | |
| 403 | static const struct of_device_id dsi_of_match[]; |
| 404 | |
Tomi Valkeinen | 477fed7 | 2013-10-02 14:41:24 +0300 | [diff] [blame] | 405 | #ifdef DSI_PERF_MEASURE |
Rusty Russell | 90ab5ee | 2012-01-13 09:32:20 +1030 | [diff] [blame] | 406 | static bool dsi_perf; |
| 407 | module_param(dsi_perf, bool, 0644); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 408 | #endif |
| 409 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 410 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
| 411 | { |
| 412 | return dev_get_drvdata(&dsidev->dev); |
| 413 | } |
| 414 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 415 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
| 416 | { |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 417 | return to_platform_device(dssdev->dev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 418 | } |
| 419 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 420 | static struct platform_device *dsi_get_dsidev_from_id(int module) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 421 | { |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 422 | struct omap_dss_device *out; |
Archit Taneja | 400e65d | 2012-07-04 13:48:34 +0530 | [diff] [blame] | 423 | enum omap_dss_output_id id; |
| 424 | |
Tomi Valkeinen | 78e7f25 | 2012-10-15 12:48:11 +0300 | [diff] [blame] | 425 | switch (module) { |
| 426 | case 0: |
| 427 | id = OMAP_DSS_OUTPUT_DSI1; |
| 428 | break; |
| 429 | case 1: |
| 430 | id = OMAP_DSS_OUTPUT_DSI2; |
| 431 | break; |
| 432 | default: |
| 433 | return NULL; |
| 434 | } |
Archit Taneja | 400e65d | 2012-07-04 13:48:34 +0530 | [diff] [blame] | 435 | |
| 436 | out = omap_dss_get_output(id); |
| 437 | |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 438 | return out ? to_platform_device(out->dev) : NULL; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | static inline void dsi_write_reg(struct platform_device *dsidev, |
| 442 | const struct dsi_reg idx, u32 val) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 443 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 444 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 445 | void __iomem *base; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 446 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 447 | switch(idx.module) { |
| 448 | case DSI_PROTO: base = dsi->proto_base; break; |
| 449 | case DSI_PHY: base = dsi->phy_base; break; |
| 450 | case DSI_PLL: base = dsi->pll_base; break; |
| 451 | default: return; |
| 452 | } |
| 453 | |
| 454 | __raw_writel(val, base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 455 | } |
| 456 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 457 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
| 458 | const struct dsi_reg idx) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 459 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 460 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 461 | void __iomem *base; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 462 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 463 | switch(idx.module) { |
| 464 | case DSI_PROTO: base = dsi->proto_base; break; |
| 465 | case DSI_PHY: base = dsi->phy_base; break; |
| 466 | case DSI_PLL: base = dsi->pll_base; break; |
| 467 | default: return 0; |
| 468 | } |
| 469 | |
| 470 | return __raw_readl(base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 471 | } |
| 472 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 473 | static void dsi_bus_lock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 474 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 475 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 476 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 477 | |
| 478 | down(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 479 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 480 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 481 | static void dsi_bus_unlock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 482 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 483 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 484 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 485 | |
| 486 | up(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 487 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 488 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 489 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 490 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 491 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 492 | |
| 493 | return dsi->bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 494 | } |
| 495 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 496 | static void dsi_completion_handler(void *data, u32 mask) |
| 497 | { |
| 498 | complete((struct completion *)data); |
| 499 | } |
| 500 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 501 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
| 502 | const struct dsi_reg idx, int bitnum, int value) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 503 | { |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 504 | unsigned long timeout; |
| 505 | ktime_t wait; |
| 506 | int t; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 507 | |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 508 | /* first busyloop to see if the bit changes right away */ |
| 509 | t = 100; |
| 510 | while (t-- > 0) { |
| 511 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) |
| 512 | return value; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 513 | } |
| 514 | |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 515 | /* then loop for 500ms, sleeping for 1ms in between */ |
| 516 | timeout = jiffies + msecs_to_jiffies(500); |
| 517 | while (time_before(jiffies, timeout)) { |
| 518 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) |
| 519 | return value; |
| 520 | |
| 521 | wait = ns_to_ktime(1000 * 1000); |
| 522 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 523 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 524 | } |
| 525 | |
| 526 | return !value; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 527 | } |
| 528 | |
Archit Taneja | a3b3cc2 | 2011-09-08 18:42:16 +0530 | [diff] [blame] | 529 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
| 530 | { |
| 531 | switch (fmt) { |
| 532 | case OMAP_DSS_DSI_FMT_RGB888: |
| 533 | case OMAP_DSS_DSI_FMT_RGB666: |
| 534 | return 24; |
| 535 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: |
| 536 | return 18; |
| 537 | case OMAP_DSS_DSI_FMT_RGB565: |
| 538 | return 16; |
| 539 | default: |
| 540 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 541 | return 0; |
Archit Taneja | a3b3cc2 | 2011-09-08 18:42:16 +0530 | [diff] [blame] | 542 | } |
| 543 | } |
| 544 | |
Tomi Valkeinen | 477fed7 | 2013-10-02 14:41:24 +0300 | [diff] [blame] | 545 | #ifdef DSI_PERF_MEASURE |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 546 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 547 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 548 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 549 | dsi->perf_setup_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 550 | } |
| 551 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 552 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 553 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 554 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 555 | dsi->perf_start_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 556 | } |
| 557 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 558 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 559 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 560 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 561 | ktime_t t, setup_time, trans_time; |
| 562 | u32 total_bytes; |
| 563 | u32 setup_us, trans_us, total_us; |
| 564 | |
| 565 | if (!dsi_perf) |
| 566 | return; |
| 567 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 568 | t = ktime_get(); |
| 569 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 570 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 571 | setup_us = (u32)ktime_to_us(setup_time); |
| 572 | if (setup_us == 0) |
| 573 | setup_us = 1; |
| 574 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 575 | trans_time = ktime_sub(t, dsi->perf_start_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 576 | trans_us = (u32)ktime_to_us(trans_time); |
| 577 | if (trans_us == 0) |
| 578 | trans_us = 1; |
| 579 | |
| 580 | total_us = setup_us + trans_us; |
| 581 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 582 | total_bytes = dsi->update_bytes; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 583 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 584 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 585 | "%u bytes, %u kbytes/sec\n", |
| 586 | name, |
| 587 | setup_us, |
| 588 | trans_us, |
| 589 | total_us, |
| 590 | 1000*1000 / total_us, |
| 591 | total_bytes, |
| 592 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 593 | } |
| 594 | #else |
Tomi Valkeinen | 4a9a5e3 | 2011-05-23 16:36:09 +0300 | [diff] [blame] | 595 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
| 596 | { |
| 597 | } |
| 598 | |
| 599 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) |
| 600 | { |
| 601 | } |
| 602 | |
| 603 | static inline void dsi_perf_show(struct platform_device *dsidev, |
| 604 | const char *name) |
| 605 | { |
| 606 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 607 | #endif |
| 608 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 609 | static int verbose_irq; |
| 610 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 611 | static void print_irq_status(u32 status) |
| 612 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 613 | if (status == 0) |
| 614 | return; |
| 615 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 616 | if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 617 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 618 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 619 | #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" |
| 620 | |
| 621 | pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", |
| 622 | status, |
| 623 | verbose_irq ? PIS(VC0) : "", |
| 624 | verbose_irq ? PIS(VC1) : "", |
| 625 | verbose_irq ? PIS(VC2) : "", |
| 626 | verbose_irq ? PIS(VC3) : "", |
| 627 | PIS(WAKEUP), |
| 628 | PIS(RESYNC), |
| 629 | PIS(PLL_LOCK), |
| 630 | PIS(PLL_UNLOCK), |
| 631 | PIS(PLL_RECALL), |
| 632 | PIS(COMPLEXIO_ERR), |
| 633 | PIS(HS_TX_TIMEOUT), |
| 634 | PIS(LP_RX_TIMEOUT), |
| 635 | PIS(TE_TRIGGER), |
| 636 | PIS(ACK_TRIGGER), |
| 637 | PIS(SYNC_LOST), |
| 638 | PIS(LDO_POWER_GOOD), |
| 639 | PIS(TA_TIMEOUT)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 640 | #undef PIS |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | static void print_irq_status_vc(int channel, u32 status) |
| 644 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 645 | if (status == 0) |
| 646 | return; |
| 647 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 648 | if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 649 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 650 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 651 | #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" |
| 652 | |
| 653 | pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", |
| 654 | channel, |
| 655 | status, |
| 656 | PIS(CS), |
| 657 | PIS(ECC_CORR), |
| 658 | PIS(ECC_NO_CORR), |
| 659 | verbose_irq ? PIS(PACKET_SENT) : "", |
| 660 | PIS(BTA), |
| 661 | PIS(FIFO_TX_OVF), |
| 662 | PIS(FIFO_RX_OVF), |
| 663 | PIS(FIFO_TX_UDF), |
| 664 | PIS(PP_BUSY_CHANGE)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 665 | #undef PIS |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 666 | } |
| 667 | |
| 668 | static void print_irq_status_cio(u32 status) |
| 669 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 670 | if (status == 0) |
| 671 | return; |
| 672 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 673 | #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 674 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 675 | pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", |
| 676 | status, |
| 677 | PIS(ERRSYNCESC1), |
| 678 | PIS(ERRSYNCESC2), |
| 679 | PIS(ERRSYNCESC3), |
| 680 | PIS(ERRESC1), |
| 681 | PIS(ERRESC2), |
| 682 | PIS(ERRESC3), |
| 683 | PIS(ERRCONTROL1), |
| 684 | PIS(ERRCONTROL2), |
| 685 | PIS(ERRCONTROL3), |
| 686 | PIS(STATEULPS1), |
| 687 | PIS(STATEULPS2), |
| 688 | PIS(STATEULPS3), |
| 689 | PIS(ERRCONTENTIONLP0_1), |
| 690 | PIS(ERRCONTENTIONLP1_1), |
| 691 | PIS(ERRCONTENTIONLP0_2), |
| 692 | PIS(ERRCONTENTIONLP1_2), |
| 693 | PIS(ERRCONTENTIONLP0_3), |
| 694 | PIS(ERRCONTENTIONLP1_3), |
| 695 | PIS(ULPSACTIVENOT_ALL0), |
| 696 | PIS(ULPSACTIVENOT_ALL1)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 697 | #undef PIS |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 698 | } |
| 699 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 700 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 701 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
| 702 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 703 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 704 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 705 | int i; |
| 706 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 707 | spin_lock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 708 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 709 | dsi->irq_stats.irq_count++; |
| 710 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 711 | |
| 712 | for (i = 0; i < 4; ++i) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 713 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 714 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 715 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 716 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 717 | spin_unlock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 718 | } |
| 719 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 720 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 721 | #endif |
| 722 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 723 | static int debug_irq; |
| 724 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 725 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
| 726 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 727 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 728 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 729 | int i; |
| 730 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 731 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 732 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 733 | print_irq_status(irqstatus); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 734 | spin_lock(&dsi->errors_lock); |
| 735 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 736 | spin_unlock(&dsi->errors_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 737 | } else if (debug_irq) { |
| 738 | print_irq_status(irqstatus); |
| 739 | } |
| 740 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 741 | for (i = 0; i < 4; ++i) { |
| 742 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
| 743 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 744 | i, vcstatus[i]); |
| 745 | print_irq_status_vc(i, vcstatus[i]); |
| 746 | } else if (debug_irq) { |
| 747 | print_irq_status_vc(i, vcstatus[i]); |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 752 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 753 | print_irq_status_cio(ciostatus); |
| 754 | } else if (debug_irq) { |
| 755 | print_irq_status_cio(ciostatus); |
| 756 | } |
| 757 | } |
| 758 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 759 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
| 760 | unsigned isr_array_size, u32 irqstatus) |
| 761 | { |
| 762 | struct dsi_isr_data *isr_data; |
| 763 | int i; |
| 764 | |
| 765 | for (i = 0; i < isr_array_size; i++) { |
| 766 | isr_data = &isr_array[i]; |
| 767 | if (isr_data->isr && isr_data->mask & irqstatus) |
| 768 | isr_data->isr(isr_data->arg, irqstatus); |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, |
| 773 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
| 774 | { |
| 775 | int i; |
| 776 | |
| 777 | dsi_call_isrs(isr_tables->isr_table, |
| 778 | ARRAY_SIZE(isr_tables->isr_table), |
| 779 | irqstatus); |
| 780 | |
| 781 | for (i = 0; i < 4; ++i) { |
| 782 | if (vcstatus[i] == 0) |
| 783 | continue; |
| 784 | dsi_call_isrs(isr_tables->isr_table_vc[i], |
| 785 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), |
| 786 | vcstatus[i]); |
| 787 | } |
| 788 | |
| 789 | if (ciostatus != 0) |
| 790 | dsi_call_isrs(isr_tables->isr_table_cio, |
| 791 | ARRAY_SIZE(isr_tables->isr_table_cio), |
| 792 | ciostatus); |
| 793 | } |
| 794 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 795 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
| 796 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 797 | struct platform_device *dsidev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 798 | struct dsi_data *dsi; |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 799 | u32 irqstatus, vcstatus[4], ciostatus; |
| 800 | int i; |
| 801 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 802 | dsidev = (struct platform_device *) arg; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 803 | dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 804 | |
Tomi Valkeinen | 0925afc | 2014-04-11 13:49:55 +0300 | [diff] [blame] | 805 | if (!dsi->is_enabled) |
| 806 | return IRQ_NONE; |
| 807 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 808 | spin_lock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 809 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 810 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 811 | |
| 812 | /* IRQ is not for us */ |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 813 | if (!irqstatus) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 814 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 815 | return IRQ_NONE; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 816 | } |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 817 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 818 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 819 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 820 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 821 | |
| 822 | for (i = 0; i < 4; ++i) { |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 823 | if ((irqstatus & (1 << i)) == 0) { |
| 824 | vcstatus[i] = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 825 | continue; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 826 | } |
| 827 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 828 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 829 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 830 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 831 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 832 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 833 | } |
| 834 | |
| 835 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 836 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 837 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 838 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 839 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 840 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 841 | } else { |
| 842 | ciostatus = 0; |
| 843 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 844 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 845 | #ifdef DSI_CATCH_MISSING_TE |
| 846 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 847 | del_timer(&dsi->te_timer); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 848 | #endif |
| 849 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 850 | /* make a copy and unlock, so that isrs can unregister |
| 851 | * themselves */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 852 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
| 853 | sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 854 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 855 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 856 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 857 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 858 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 859 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 860 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 861 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 862 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 863 | return IRQ_HANDLED; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 864 | } |
| 865 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 866 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 867 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
| 868 | struct dsi_isr_data *isr_array, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 869 | unsigned isr_array_size, u32 default_mask, |
| 870 | const struct dsi_reg enable_reg, |
| 871 | const struct dsi_reg status_reg) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 872 | { |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 873 | struct dsi_isr_data *isr_data; |
| 874 | u32 mask; |
| 875 | u32 old_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 876 | int i; |
| 877 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 878 | mask = default_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 879 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 880 | for (i = 0; i < isr_array_size; i++) { |
| 881 | isr_data = &isr_array[i]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 882 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 883 | if (isr_data->isr == NULL) |
| 884 | continue; |
| 885 | |
| 886 | mask |= isr_data->mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 887 | } |
| 888 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 889 | old_mask = dsi_read_reg(dsidev, enable_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 890 | /* clear the irqstatus for newly enabled irqs */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 891 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
| 892 | dsi_write_reg(dsidev, enable_reg, mask); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 893 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 894 | /* flush posted writes */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 895 | dsi_read_reg(dsidev, enable_reg); |
| 896 | dsi_read_reg(dsidev, status_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 897 | } |
| 898 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 899 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 900 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 901 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 902 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 903 | u32 mask = DSI_IRQ_ERROR_MASK; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 904 | #ifdef DSI_CATCH_MISSING_TE |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 905 | mask |= DSI_IRQ_TE_TRIGGER; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 906 | #endif |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 907 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
| 908 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 909 | DSI_IRQENABLE, DSI_IRQSTATUS); |
| 910 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 911 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 912 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 913 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 914 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 915 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 916 | |
| 917 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], |
| 918 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 919 | DSI_VC_IRQ_ERROR_MASK, |
| 920 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); |
| 921 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 922 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 923 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 924 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 925 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 926 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 927 | |
| 928 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, |
| 929 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 930 | DSI_CIO_IRQ_ERROR_MASK, |
| 931 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); |
| 932 | } |
| 933 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 934 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 935 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 936 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 937 | unsigned long flags; |
| 938 | int vc; |
| 939 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 940 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 941 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 942 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 943 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 944 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 945 | for (vc = 0; vc < 4; ++vc) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 946 | _omap_dsi_set_irqs_vc(dsidev, vc); |
| 947 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 948 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 949 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 950 | } |
| 951 | |
| 952 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 953 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 954 | { |
| 955 | struct dsi_isr_data *isr_data; |
| 956 | int free_idx; |
| 957 | int i; |
| 958 | |
| 959 | BUG_ON(isr == NULL); |
| 960 | |
| 961 | /* check for duplicate entry and find a free slot */ |
| 962 | free_idx = -1; |
| 963 | for (i = 0; i < isr_array_size; i++) { |
| 964 | isr_data = &isr_array[i]; |
| 965 | |
| 966 | if (isr_data->isr == isr && isr_data->arg == arg && |
| 967 | isr_data->mask == mask) { |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | if (isr_data->isr == NULL && free_idx == -1) |
| 972 | free_idx = i; |
| 973 | } |
| 974 | |
| 975 | if (free_idx == -1) |
| 976 | return -EBUSY; |
| 977 | |
| 978 | isr_data = &isr_array[free_idx]; |
| 979 | isr_data->isr = isr; |
| 980 | isr_data->arg = arg; |
| 981 | isr_data->mask = mask; |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 987 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 988 | { |
| 989 | struct dsi_isr_data *isr_data; |
| 990 | int i; |
| 991 | |
| 992 | for (i = 0; i < isr_array_size; i++) { |
| 993 | isr_data = &isr_array[i]; |
| 994 | if (isr_data->isr != isr || isr_data->arg != arg || |
| 995 | isr_data->mask != mask) |
| 996 | continue; |
| 997 | |
| 998 | isr_data->isr = NULL; |
| 999 | isr_data->arg = NULL; |
| 1000 | isr_data->mask = 0; |
| 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
| 1005 | return -EINVAL; |
| 1006 | } |
| 1007 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1008 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
| 1009 | void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1010 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1011 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1012 | unsigned long flags; |
| 1013 | int r; |
| 1014 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1015 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1016 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1017 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 1018 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1019 | |
| 1020 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1021 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1022 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1023 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1024 | |
| 1025 | return r; |
| 1026 | } |
| 1027 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1028 | static int dsi_unregister_isr(struct platform_device *dsidev, |
| 1029 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1030 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1031 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1032 | unsigned long flags; |
| 1033 | int r; |
| 1034 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1035 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1036 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1037 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 1038 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1039 | |
| 1040 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1041 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1042 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1043 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1044 | |
| 1045 | return r; |
| 1046 | } |
| 1047 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1048 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
| 1049 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1050 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1051 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1052 | unsigned long flags; |
| 1053 | int r; |
| 1054 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1055 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1056 | |
| 1057 | r = _dsi_register_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1058 | dsi->isr_tables.isr_table_vc[channel], |
| 1059 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1060 | |
| 1061 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1062 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1063 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1064 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1065 | |
| 1066 | return r; |
| 1067 | } |
| 1068 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1069 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
| 1070 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1071 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1072 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1073 | unsigned long flags; |
| 1074 | int r; |
| 1075 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1076 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1077 | |
| 1078 | r = _dsi_unregister_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1079 | dsi->isr_tables.isr_table_vc[channel], |
| 1080 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1081 | |
| 1082 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1083 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1084 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1085 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1086 | |
| 1087 | return r; |
| 1088 | } |
| 1089 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1090 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
| 1091 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1092 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1093 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1094 | unsigned long flags; |
| 1095 | int r; |
| 1096 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1097 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1098 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1099 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 1100 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1101 | |
| 1102 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1103 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1104 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1105 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1106 | |
| 1107 | return r; |
| 1108 | } |
| 1109 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1110 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
| 1111 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1112 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1113 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1114 | unsigned long flags; |
| 1115 | int r; |
| 1116 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1117 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1118 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1119 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 1120 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1121 | |
| 1122 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1123 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1124 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1125 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1126 | |
| 1127 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1128 | } |
| 1129 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1130 | static u32 dsi_get_errors(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1131 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1132 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1133 | unsigned long flags; |
| 1134 | u32 e; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1135 | spin_lock_irqsave(&dsi->errors_lock, flags); |
| 1136 | e = dsi->errors; |
| 1137 | dsi->errors = 0; |
| 1138 | spin_unlock_irqrestore(&dsi->errors_lock, flags); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1139 | return e; |
| 1140 | } |
| 1141 | |
Tomi Valkeinen | f76b178 | 2014-08-08 10:04:31 +0300 | [diff] [blame] | 1142 | static int dsi_runtime_get(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1143 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1144 | int r; |
| 1145 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1146 | |
| 1147 | DSSDBG("dsi_runtime_get\n"); |
| 1148 | |
| 1149 | r = pm_runtime_get_sync(&dsi->pdev->dev); |
| 1150 | WARN_ON(r < 0); |
| 1151 | return r < 0 ? r : 0; |
| 1152 | } |
| 1153 | |
Tomi Valkeinen | f76b178 | 2014-08-08 10:04:31 +0300 | [diff] [blame] | 1154 | static void dsi_runtime_put(struct platform_device *dsidev) |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1155 | { |
| 1156 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1157 | int r; |
| 1158 | |
| 1159 | DSSDBG("dsi_runtime_put\n"); |
| 1160 | |
Tomi Valkeinen | 0eaf9f5 | 2012-01-23 13:23:08 +0200 | [diff] [blame] | 1161 | r = pm_runtime_put_sync(&dsi->pdev->dev); |
Tomi Valkeinen | 5be3aeb | 2012-06-27 16:37:18 +0300 | [diff] [blame] | 1162 | WARN_ON(r < 0 && r != -ENOSYS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1163 | } |
| 1164 | |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1165 | static int dsi_regulator_init(struct platform_device *dsidev) |
| 1166 | { |
| 1167 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1168 | struct regulator *vdds_dsi; |
Tomi Valkeinen | 02b7a32 | 2014-03-13 14:33:03 +0200 | [diff] [blame] | 1169 | int r; |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1170 | |
| 1171 | if (dsi->vdds_dsi_reg != NULL) |
| 1172 | return 0; |
| 1173 | |
Tomi Valkeinen | 931d4bd | 2013-06-10 14:05:10 +0300 | [diff] [blame] | 1174 | vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1175 | |
| 1176 | if (IS_ERR(vdds_dsi)) { |
Tomi Valkeinen | 40359a9 | 2013-12-19 16:15:34 +0200 | [diff] [blame] | 1177 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
Tomi Valkeinen | 931d4bd | 2013-06-10 14:05:10 +0300 | [diff] [blame] | 1178 | DSSERR("can't get DSI VDD regulator\n"); |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1179 | return PTR_ERR(vdds_dsi); |
| 1180 | } |
| 1181 | |
Tomi Valkeinen | 02b7a32 | 2014-03-13 14:33:03 +0200 | [diff] [blame] | 1182 | if (regulator_can_change_voltage(vdds_dsi)) { |
| 1183 | r = regulator_set_voltage(vdds_dsi, 1800000, 1800000); |
| 1184 | if (r) { |
| 1185 | devm_regulator_put(vdds_dsi); |
| 1186 | DSSERR("can't set the DSI regulator voltage\n"); |
| 1187 | return r; |
| 1188 | } |
| 1189 | } |
| 1190 | |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1191 | dsi->vdds_dsi_reg = vdds_dsi; |
| 1192 | |
| 1193 | return 0; |
| 1194 | } |
| 1195 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1196 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1197 | { |
| 1198 | u32 l; |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1199 | int b0, b1, b2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1200 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1201 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 1202 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 1203 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1204 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1205 | |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1206 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 1207 | b0 = 28; |
| 1208 | b1 = 27; |
| 1209 | b2 = 26; |
| 1210 | } else { |
| 1211 | b0 = 24; |
| 1212 | b1 = 25; |
| 1213 | b2 = 26; |
| 1214 | } |
| 1215 | |
Chandrabhanu Mahapatra | f30be7d | 2012-09-29 12:33:05 +0530 | [diff] [blame] | 1216 | #define DSI_FLD_GET(fld, start, end)\ |
| 1217 | FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) |
| 1218 | |
| 1219 | pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", |
| 1220 | DSI_FLD_GET(PLL_STATUS, 0, 0), |
| 1221 | DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), |
| 1222 | DSI_FLD_GET(DSIPHY_CFG5, b0, b0), |
| 1223 | DSI_FLD_GET(DSIPHY_CFG5, b1, b1), |
| 1224 | DSI_FLD_GET(DSIPHY_CFG5, b2, b2), |
| 1225 | DSI_FLD_GET(DSIPHY_CFG5, 29, 29), |
| 1226 | DSI_FLD_GET(DSIPHY_CFG5, 30, 30), |
| 1227 | DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); |
| 1228 | |
| 1229 | #undef DSI_FLD_GET |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1230 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1231 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1232 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1233 | { |
| 1234 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 1235 | |
| 1236 | enable = enable ? 1 : 0; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1237 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1238 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1239 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1240 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 1241 | return -EIO; |
| 1242 | } |
| 1243 | |
| 1244 | return 0; |
| 1245 | } |
| 1246 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1247 | static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1248 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1249 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1250 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1251 | return dsi->pll.cinfo.clkout[HSDIV_DISPC]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1252 | } |
| 1253 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1254 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1255 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1256 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1257 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1258 | return dsi->pll.cinfo.clkout[HSDIV_DSI]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1259 | } |
| 1260 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1261 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1262 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1263 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1264 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1265 | return dsi->pll.cinfo.clkdco / 16; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1266 | } |
| 1267 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1268 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1269 | { |
| 1270 | unsigned long r; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1271 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1272 | |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 1273 | if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1274 | /* DSI FCLK source is DSS_CLK_FCK */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1275 | r = clk_get_rate(dsi->dss_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1276 | } else { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1277 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1278 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1279 | } |
| 1280 | |
| 1281 | return r; |
| 1282 | } |
| 1283 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 1284 | static int dsi_lp_clock_calc(unsigned long dsi_fclk, |
| 1285 | unsigned long lp_clk_min, unsigned long lp_clk_max, |
| 1286 | struct dsi_lp_clock_info *lp_cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1287 | { |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 1288 | unsigned lp_clk_div; |
| 1289 | unsigned long lp_clk; |
| 1290 | |
| 1291 | lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); |
| 1292 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 1293 | |
| 1294 | if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) |
| 1295 | return -EINVAL; |
| 1296 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 1297 | lp_cinfo->lp_clk_div = lp_clk_div; |
| 1298 | lp_cinfo->lp_clk = lp_clk; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 1299 | |
| 1300 | return 0; |
| 1301 | } |
| 1302 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 1303 | static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1304 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1305 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1306 | unsigned long dsi_fclk; |
| 1307 | unsigned lp_clk_div; |
| 1308 | unsigned long lp_clk; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1309 | unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); |
| 1310 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1311 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 1312 | lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1313 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1314 | if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1315 | return -EINVAL; |
| 1316 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1317 | dsi_fclk = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1318 | |
| 1319 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 1320 | |
| 1321 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 1322 | dsi->current_lp_cinfo.lp_clk = lp_clk; |
| 1323 | dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1324 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1325 | /* LP_CLK_DIVISOR */ |
| 1326 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1327 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1328 | /* LP_RX_SYNCHRO_ENABLE */ |
| 1329 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1330 | |
| 1331 | return 0; |
| 1332 | } |
| 1333 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1334 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1335 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1336 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1337 | |
| 1338 | if (dsi->scp_clk_refcount++ == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1339 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1340 | } |
| 1341 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1342 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1343 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1344 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1345 | |
| 1346 | WARN_ON(dsi->scp_clk_refcount == 0); |
| 1347 | if (--dsi->scp_clk_refcount == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1348 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1349 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1350 | |
| 1351 | enum dsi_pll_power_state { |
| 1352 | DSI_PLL_POWER_OFF = 0x0, |
| 1353 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 1354 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 1355 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 1356 | }; |
| 1357 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1358 | static int dsi_pll_power(struct platform_device *dsidev, |
| 1359 | enum dsi_pll_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1360 | { |
| 1361 | int t = 0; |
| 1362 | |
Tomi Valkeinen | c94dfe0 | 2011-04-15 10:42:59 +0300 | [diff] [blame] | 1363 | /* DSI-PLL power command 0x3 is not working */ |
| 1364 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && |
| 1365 | state == DSI_PLL_POWER_ON_DIV) |
| 1366 | state = DSI_PLL_POWER_ON_ALL; |
| 1367 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1368 | /* PLL_PWR_CMD */ |
| 1369 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1370 | |
| 1371 | /* PLL_PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1372 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1373 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1374 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 1375 | state); |
| 1376 | return -ENODEV; |
| 1377 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1378 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1379 | } |
| 1380 | |
| 1381 | return 0; |
| 1382 | } |
| 1383 | |
Tomi Valkeinen | 72658f0 | 2013-03-05 16:39:00 +0200 | [diff] [blame] | 1384 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1385 | static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) |
Tomi Valkeinen | d66b158 | 2012-09-24 15:15:06 +0300 | [diff] [blame] | 1386 | { |
| 1387 | unsigned long max_dsi_fck; |
| 1388 | |
| 1389 | max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); |
| 1390 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1391 | cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); |
| 1392 | cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; |
Tomi Valkeinen | d66b158 | 2012-09-24 15:15:06 +0300 | [diff] [blame] | 1393 | } |
| 1394 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1395 | static int dsi_pll_enable(struct dss_pll *pll) |
Tomi Valkeinen | 544bfb6 | 2014-08-04 13:46:05 +0300 | [diff] [blame] | 1396 | { |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1397 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); |
| 1398 | struct platform_device *dsidev = dsi->pdev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1399 | int r = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1400 | |
| 1401 | DSSDBG("PLL init\n"); |
| 1402 | |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 1403 | r = dsi_regulator_init(dsidev); |
| 1404 | if (r) |
| 1405 | return r; |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1406 | |
Tomi Valkeinen | f76b178 | 2014-08-08 10:04:31 +0300 | [diff] [blame] | 1407 | r = dsi_runtime_get(dsidev); |
| 1408 | if (r) |
| 1409 | return r; |
| 1410 | |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1411 | /* |
| 1412 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. |
| 1413 | */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1414 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1415 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1416 | if (!dsi->vdds_dsi_enabled) { |
| 1417 | r = regulator_enable(dsi->vdds_dsi_reg); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1418 | if (r) |
| 1419 | goto err0; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1420 | dsi->vdds_dsi_enabled = true; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1421 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1422 | |
| 1423 | /* XXX PLL does not come out of reset without this... */ |
| 1424 | dispc_pck_free_enable(1); |
| 1425 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1426 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1427 | DSSERR("PLL not coming out of reset.\n"); |
| 1428 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1429 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1430 | goto err1; |
| 1431 | } |
| 1432 | |
| 1433 | /* XXX ... but if left on, we get problems when planes do not |
| 1434 | * fill the whole display. No idea about this */ |
| 1435 | dispc_pck_free_enable(0); |
| 1436 | |
Tomi Valkeinen | 1a7f4bf | 2014-08-06 13:31:47 +0300 | [diff] [blame] | 1437 | r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1438 | |
| 1439 | if (r) |
| 1440 | goto err1; |
| 1441 | |
| 1442 | DSSDBG("PLL init done\n"); |
| 1443 | |
| 1444 | return 0; |
| 1445 | err1: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1446 | if (dsi->vdds_dsi_enabled) { |
| 1447 | regulator_disable(dsi->vdds_dsi_reg); |
| 1448 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1449 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1450 | err0: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1451 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | f76b178 | 2014-08-08 10:04:31 +0300 | [diff] [blame] | 1452 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1453 | return r; |
| 1454 | } |
| 1455 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1456 | static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1457 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1458 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1459 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1460 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1461 | if (disconnect_lanes) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1462 | WARN_ON(!dsi->vdds_dsi_enabled); |
| 1463 | regulator_disable(dsi->vdds_dsi_reg); |
| 1464 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1465 | } |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1466 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1467 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | f76b178 | 2014-08-08 10:04:31 +0300 | [diff] [blame] | 1468 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1469 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1470 | DSSDBG("PLL uninit done\n"); |
| 1471 | } |
| 1472 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1473 | static void dsi_pll_disable(struct dss_pll *pll) |
| 1474 | { |
| 1475 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); |
| 1476 | struct platform_device *dsidev = dsi->pdev; |
| 1477 | |
| 1478 | dsi_pll_uninit(dsidev, true); |
| 1479 | } |
| 1480 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1481 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
| 1482 | struct seq_file *s) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1483 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1484 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1485 | struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1486 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 1487 | int dsi_module = dsi->module_id; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1488 | struct dss_pll *pll = &dsi->pll; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1489 | |
| 1490 | dispc_clk_src = dss_get_dispc_clk_source(); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1491 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1492 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1493 | if (dsi_runtime_get(dsidev)) |
| 1494 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1495 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1496 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1497 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1498 | seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1499 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1500 | seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1501 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1502 | seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", |
| 1503 | cinfo->clkdco, cinfo->m); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1504 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1505 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", |
Archit Taneja | 84309f1 | 2011-12-12 11:47:41 +0530 | [diff] [blame] | 1506 | dss_feat_get_clk_source_name(dsi_module == 0 ? |
| 1507 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : |
| 1508 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 1509 | cinfo->clkout[HSDIV_DISPC], |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1510 | cinfo->mX[HSDIV_DISPC], |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1511 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1512 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1513 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1514 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", |
Archit Taneja | 84309f1 | 2011-12-12 11:47:41 +0530 | [diff] [blame] | 1515 | dss_feat_get_clk_source_name(dsi_module == 0 ? |
| 1516 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : |
| 1517 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 1518 | cinfo->clkout[HSDIV_DSI], |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1519 | cinfo->mX[HSDIV_DSI], |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1520 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1521 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1522 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1523 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1524 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1525 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
| 1526 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1527 | dss_feat_get_clk_source_name(dsi_clk_src)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1528 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1529 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1530 | |
| 1531 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
Tomi Valkeinen | 4a38aed | 2014-11-07 13:08:16 +0200 | [diff] [blame] | 1532 | cinfo->clkdco / 4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1533 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1534 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1535 | |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 1536 | seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1537 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1538 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1539 | } |
| 1540 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1541 | void dsi_dump_clocks(struct seq_file *s) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1542 | { |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1543 | struct platform_device *dsidev; |
| 1544 | int i; |
| 1545 | |
| 1546 | for (i = 0; i < MAX_NUM_DSI; i++) { |
| 1547 | dsidev = dsi_get_dsidev_from_id(i); |
| 1548 | if (dsidev) |
| 1549 | dsi_dump_dsidev_clocks(dsidev, s); |
| 1550 | } |
| 1551 | } |
| 1552 | |
| 1553 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1554 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
| 1555 | struct seq_file *s) |
| 1556 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1557 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1558 | unsigned long flags; |
| 1559 | struct dsi_irq_stats stats; |
| 1560 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1561 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1562 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1563 | stats = dsi->irq_stats; |
| 1564 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); |
| 1565 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1566 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1567 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1568 | |
| 1569 | seq_printf(s, "period %u ms\n", |
| 1570 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1571 | |
| 1572 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1573 | #define PIS(x) \ |
| 1574 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1575 | |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 1576 | seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1577 | PIS(VC0); |
| 1578 | PIS(VC1); |
| 1579 | PIS(VC2); |
| 1580 | PIS(VC3); |
| 1581 | PIS(WAKEUP); |
| 1582 | PIS(RESYNC); |
| 1583 | PIS(PLL_LOCK); |
| 1584 | PIS(PLL_UNLOCK); |
| 1585 | PIS(PLL_RECALL); |
| 1586 | PIS(COMPLEXIO_ERR); |
| 1587 | PIS(HS_TX_TIMEOUT); |
| 1588 | PIS(LP_RX_TIMEOUT); |
| 1589 | PIS(TE_TRIGGER); |
| 1590 | PIS(ACK_TRIGGER); |
| 1591 | PIS(SYNC_LOST); |
| 1592 | PIS(LDO_POWER_GOOD); |
| 1593 | PIS(TA_TIMEOUT); |
| 1594 | #undef PIS |
| 1595 | |
| 1596 | #define PIS(x) \ |
| 1597 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1598 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1599 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1600 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1601 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1602 | |
| 1603 | seq_printf(s, "-- VC interrupts --\n"); |
| 1604 | PIS(CS); |
| 1605 | PIS(ECC_CORR); |
| 1606 | PIS(PACKET_SENT); |
| 1607 | PIS(FIFO_TX_OVF); |
| 1608 | PIS(FIFO_RX_OVF); |
| 1609 | PIS(BTA); |
| 1610 | PIS(ECC_NO_CORR); |
| 1611 | PIS(FIFO_TX_UDF); |
| 1612 | PIS(PP_BUSY_CHANGE); |
| 1613 | #undef PIS |
| 1614 | |
| 1615 | #define PIS(x) \ |
| 1616 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1617 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1618 | |
| 1619 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1620 | PIS(ERRSYNCESC1); |
| 1621 | PIS(ERRSYNCESC2); |
| 1622 | PIS(ERRSYNCESC3); |
| 1623 | PIS(ERRESC1); |
| 1624 | PIS(ERRESC2); |
| 1625 | PIS(ERRESC3); |
| 1626 | PIS(ERRCONTROL1); |
| 1627 | PIS(ERRCONTROL2); |
| 1628 | PIS(ERRCONTROL3); |
| 1629 | PIS(STATEULPS1); |
| 1630 | PIS(STATEULPS2); |
| 1631 | PIS(STATEULPS3); |
| 1632 | PIS(ERRCONTENTIONLP0_1); |
| 1633 | PIS(ERRCONTENTIONLP1_1); |
| 1634 | PIS(ERRCONTENTIONLP0_2); |
| 1635 | PIS(ERRCONTENTIONLP1_2); |
| 1636 | PIS(ERRCONTENTIONLP0_3); |
| 1637 | PIS(ERRCONTENTIONLP1_3); |
| 1638 | PIS(ULPSACTIVENOT_ALL0); |
| 1639 | PIS(ULPSACTIVENOT_ALL1); |
| 1640 | #undef PIS |
| 1641 | } |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1642 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1643 | static void dsi1_dump_irqs(struct seq_file *s) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1644 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1645 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1646 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1647 | dsi_dump_dsidev_irqs(dsidev, s); |
| 1648 | } |
| 1649 | |
| 1650 | static void dsi2_dump_irqs(struct seq_file *s) |
| 1651 | { |
| 1652 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); |
| 1653 | |
| 1654 | dsi_dump_dsidev_irqs(dsidev, s); |
| 1655 | } |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1656 | #endif |
| 1657 | |
| 1658 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, |
| 1659 | struct seq_file *s) |
| 1660 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1661 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1662 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1663 | if (dsi_runtime_get(dsidev)) |
| 1664 | return; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1665 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1666 | |
| 1667 | DUMPREG(DSI_REVISION); |
| 1668 | DUMPREG(DSI_SYSCONFIG); |
| 1669 | DUMPREG(DSI_SYSSTATUS); |
| 1670 | DUMPREG(DSI_IRQSTATUS); |
| 1671 | DUMPREG(DSI_IRQENABLE); |
| 1672 | DUMPREG(DSI_CTRL); |
| 1673 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1674 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1675 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1676 | DUMPREG(DSI_CLK_CTRL); |
| 1677 | DUMPREG(DSI_TIMING1); |
| 1678 | DUMPREG(DSI_TIMING2); |
| 1679 | DUMPREG(DSI_VM_TIMING1); |
| 1680 | DUMPREG(DSI_VM_TIMING2); |
| 1681 | DUMPREG(DSI_VM_TIMING3); |
| 1682 | DUMPREG(DSI_CLK_TIMING); |
| 1683 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1684 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1685 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1686 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1687 | DUMPREG(DSI_VM_TIMING4); |
| 1688 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1689 | DUMPREG(DSI_VM_TIMING5); |
| 1690 | DUMPREG(DSI_VM_TIMING6); |
| 1691 | DUMPREG(DSI_VM_TIMING7); |
| 1692 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1693 | |
| 1694 | DUMPREG(DSI_VC_CTRL(0)); |
| 1695 | DUMPREG(DSI_VC_TE(0)); |
| 1696 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1697 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1698 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1699 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1700 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1701 | |
| 1702 | DUMPREG(DSI_VC_CTRL(1)); |
| 1703 | DUMPREG(DSI_VC_TE(1)); |
| 1704 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1705 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1706 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1707 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1708 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1709 | |
| 1710 | DUMPREG(DSI_VC_CTRL(2)); |
| 1711 | DUMPREG(DSI_VC_TE(2)); |
| 1712 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1713 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1714 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1715 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1716 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1717 | |
| 1718 | DUMPREG(DSI_VC_CTRL(3)); |
| 1719 | DUMPREG(DSI_VC_TE(3)); |
| 1720 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1721 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1722 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1723 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1724 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1725 | |
| 1726 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1727 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1728 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1729 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1730 | |
| 1731 | DUMPREG(DSI_PLL_CONTROL); |
| 1732 | DUMPREG(DSI_PLL_STATUS); |
| 1733 | DUMPREG(DSI_PLL_GO); |
| 1734 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1735 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1736 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1737 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1738 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1739 | #undef DUMPREG |
| 1740 | } |
| 1741 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1742 | static void dsi1_dump_regs(struct seq_file *s) |
| 1743 | { |
| 1744 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1745 | |
| 1746 | dsi_dump_dsidev_regs(dsidev, s); |
| 1747 | } |
| 1748 | |
| 1749 | static void dsi2_dump_regs(struct seq_file *s) |
| 1750 | { |
| 1751 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); |
| 1752 | |
| 1753 | dsi_dump_dsidev_regs(dsidev, s); |
| 1754 | } |
| 1755 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1756 | enum dsi_cio_power_state { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1757 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1758 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1759 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1760 | }; |
| 1761 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1762 | static int dsi_cio_power(struct platform_device *dsidev, |
| 1763 | enum dsi_cio_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1764 | { |
| 1765 | int t = 0; |
| 1766 | |
| 1767 | /* PWR_CMD */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1768 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1769 | |
| 1770 | /* PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1771 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
| 1772 | 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1773 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1774 | DSSERR("failed to set complexio power state to " |
| 1775 | "%d\n", state); |
| 1776 | return -ENODEV; |
| 1777 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1778 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1779 | } |
| 1780 | |
| 1781 | return 0; |
| 1782 | } |
| 1783 | |
Archit Taneja | 0c65622 | 2011-05-16 15:17:09 +0530 | [diff] [blame] | 1784 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
| 1785 | { |
| 1786 | int val; |
| 1787 | |
| 1788 | /* line buffer on OMAP3 is 1024 x 24bits */ |
| 1789 | /* XXX: for some reason using full buffer size causes |
| 1790 | * considerable TX slowdown with update sizes that fill the |
| 1791 | * whole buffer */ |
| 1792 | if (!dss_has_feature(FEAT_DSI_GNQ)) |
| 1793 | return 1023 * 3; |
| 1794 | |
| 1795 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ |
| 1796 | |
| 1797 | switch (val) { |
| 1798 | case 1: |
| 1799 | return 512 * 3; /* 512x24 bits */ |
| 1800 | case 2: |
| 1801 | return 682 * 3; /* 682x24 bits */ |
| 1802 | case 3: |
| 1803 | return 853 * 3; /* 853x24 bits */ |
| 1804 | case 4: |
| 1805 | return 1024 * 3; /* 1024x24 bits */ |
| 1806 | case 5: |
| 1807 | return 1194 * 3; /* 1194x24 bits */ |
| 1808 | case 6: |
| 1809 | return 1365 * 3; /* 1365x24 bits */ |
Tomi Valkeinen | 2ac80fb | 2012-08-22 16:00:47 +0300 | [diff] [blame] | 1810 | case 7: |
| 1811 | return 1920 * 3; /* 1920x24 bits */ |
Archit Taneja | 0c65622 | 2011-05-16 15:17:09 +0530 | [diff] [blame] | 1812 | default: |
| 1813 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 1814 | return 0; |
Archit Taneja | 0c65622 | 2011-05-16 15:17:09 +0530 | [diff] [blame] | 1815 | } |
| 1816 | } |
| 1817 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 1818 | static int dsi_set_lane_config(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1819 | { |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1820 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1821 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; |
| 1822 | static const enum dsi_lane_function functions[] = { |
| 1823 | DSI_LANE_CLK, |
| 1824 | DSI_LANE_DATA1, |
| 1825 | DSI_LANE_DATA2, |
| 1826 | DSI_LANE_DATA3, |
| 1827 | DSI_LANE_DATA4, |
| 1828 | }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1829 | u32 r; |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1830 | int i; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1831 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1832 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1833 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1834 | for (i = 0; i < dsi->num_lanes_used; ++i) { |
| 1835 | unsigned offset = offsets[i]; |
| 1836 | unsigned polarity, lane_number; |
| 1837 | unsigned t; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1838 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1839 | for (t = 0; t < dsi->num_lanes_supported; ++t) |
| 1840 | if (dsi->lanes[t].function == functions[i]) |
| 1841 | break; |
| 1842 | |
| 1843 | if (t == dsi->num_lanes_supported) |
| 1844 | return -EINVAL; |
| 1845 | |
| 1846 | lane_number = t; |
| 1847 | polarity = dsi->lanes[t].polarity; |
| 1848 | |
| 1849 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); |
| 1850 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1851 | } |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1852 | |
| 1853 | /* clear the unused lanes */ |
| 1854 | for (; i < dsi->num_lanes_supported; ++i) { |
| 1855 | unsigned offset = offsets[i]; |
| 1856 | |
| 1857 | r = FLD_MOD(r, 0, offset + 2, offset); |
| 1858 | r = FLD_MOD(r, 0, offset + 3, offset + 3); |
| 1859 | } |
| 1860 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1861 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1862 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 1863 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1864 | } |
| 1865 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1866 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1867 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1868 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1869 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1870 | /* convert time in ns to ddr ticks, rounding up */ |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1871 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1872 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 1873 | } |
| 1874 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1875 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1876 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1877 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1878 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 1879 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1880 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 1881 | } |
| 1882 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1883 | static void dsi_cio_timings(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1884 | { |
| 1885 | u32 r; |
| 1886 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 1887 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 1888 | u32 tclk_prepare; |
| 1889 | |
| 1890 | /* calculate timings */ |
| 1891 | |
| 1892 | /* 1 * DDR_CLK = 2 * UI */ |
| 1893 | |
| 1894 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1895 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1896 | |
| 1897 | /* min 145ns + 10*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1898 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1899 | |
| 1900 | /* min max(8*UI, 60ns+4*UI) */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1901 | ths_trail = ns2ddr(dsidev, 60) + 5; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1902 | |
| 1903 | /* min 100ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1904 | ths_exit = ns2ddr(dsidev, 145); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1905 | |
| 1906 | /* tlpx min 50n */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1907 | tlpx_half = ns2ddr(dsidev, 25); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1908 | |
| 1909 | /* min 60ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1910 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1911 | |
| 1912 | /* min 38ns, max 95ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1913 | tclk_prepare = ns2ddr(dsidev, 65); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1914 | |
| 1915 | /* min tclk-prepare + tclk-zero = 300ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1916 | tclk_zero = ns2ddr(dsidev, 260); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1917 | |
| 1918 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1919 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
| 1920 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1921 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1922 | ths_trail, ddr2ns(dsidev, ths_trail), |
| 1923 | ths_exit, ddr2ns(dsidev, ths_exit)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1924 | |
| 1925 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 1926 | "tclk_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1927 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
| 1928 | tclk_trail, ddr2ns(dsidev, tclk_trail), |
| 1929 | tclk_zero, ddr2ns(dsidev, tclk_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1930 | DSSDBG("tclk_prepare %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1931 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1932 | |
| 1933 | /* program timings */ |
| 1934 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1935 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1936 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 1937 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 1938 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 1939 | r = FLD_MOD(r, ths_exit, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1940 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1941 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1942 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | e84dc1c | 2012-09-24 09:34:52 +0300 | [diff] [blame] | 1943 | r = FLD_MOD(r, tlpx_half, 20, 16); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1944 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 1945 | r = FLD_MOD(r, tclk_zero, 7, 0); |
Tomi Valkeinen | 77ccbfb | 2012-09-24 15:15:57 +0300 | [diff] [blame] | 1946 | |
| 1947 | if (dss_has_feature(FEAT_DSI_PHY_DCC)) { |
| 1948 | r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ |
| 1949 | r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ |
| 1950 | r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ |
| 1951 | } |
| 1952 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1953 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1954 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1955 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1956 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1957 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1958 | } |
| 1959 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1960 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 1961 | static void dsi_cio_enable_lane_override(struct platform_device *dsidev, |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1962 | unsigned mask_p, unsigned mask_n) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1963 | { |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1964 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1965 | int i; |
| 1966 | u32 l; |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 1967 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1968 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1969 | l = 0; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1970 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1971 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 1972 | unsigned p = dsi->lanes[i].polarity; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1973 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1974 | if (mask_p & (1 << i)) |
| 1975 | l |= 1 << (i * 2 + (p ? 0 : 1)); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1976 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 1977 | if (mask_n & (1 << i)) |
| 1978 | l |= 1 << (i * 2 + (p ? 1 : 0)); |
| 1979 | } |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1980 | |
| 1981 | /* |
| 1982 | * Bits in REGLPTXSCPDAT4TO0DXDY: |
| 1983 | * 17: DY0 18: DX0 |
| 1984 | * 19: DY1 20: DX1 |
| 1985 | * 21: DY2 22: DX2 |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1986 | * 23: DY3 24: DX3 |
| 1987 | * 25: DY4 26: DX4 |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1988 | */ |
| 1989 | |
| 1990 | /* Set the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1991 | |
| 1992 | /* REGLPTXSCPDAT4TO0DXDY */ |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 1993 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1994 | |
| 1995 | /* Enable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1996 | |
| 1997 | /* ENLPTXSCPDAT */ |
| 1998 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 1999 | } |
| 2000 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2001 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2002 | { |
| 2003 | /* Disable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2004 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2005 | /* Reset the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2006 | /* REGLPTXSCPDAT4TO0DXDY */ |
| 2007 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2008 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2009 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2010 | static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2011 | { |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2012 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2013 | int t, i; |
| 2014 | bool in_use[DSI_MAX_NR_LANES]; |
| 2015 | static const u8 offsets_old[] = { 28, 27, 26 }; |
| 2016 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; |
| 2017 | const u8 *offsets; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2018 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2019 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) |
| 2020 | offsets = offsets_old; |
| 2021 | else |
| 2022 | offsets = offsets_new; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2023 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2024 | for (i = 0; i < dsi->num_lanes_supported; ++i) |
| 2025 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2026 | |
| 2027 | t = 100000; |
| 2028 | while (true) { |
| 2029 | u32 l; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2030 | int ok; |
| 2031 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2032 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2033 | |
| 2034 | ok = 0; |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2035 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2036 | if (!in_use[i] || (l & (1 << offsets[i]))) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2037 | ok++; |
| 2038 | } |
| 2039 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2040 | if (ok == dsi->num_lanes_supported) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2041 | break; |
| 2042 | |
| 2043 | if (--t == 0) { |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2044 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2045 | if (!in_use[i] || (l & (1 << offsets[i]))) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2046 | continue; |
| 2047 | |
| 2048 | DSSERR("CIO TXCLKESC%d domain not coming " \ |
| 2049 | "out of reset\n", i); |
| 2050 | } |
| 2051 | return -EIO; |
| 2052 | } |
| 2053 | } |
| 2054 | |
| 2055 | return 0; |
| 2056 | } |
| 2057 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2058 | /* return bitmask of enabled lanes, lane0 being the lsb */ |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2059 | static unsigned dsi_get_lane_mask(struct platform_device *dsidev) |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2060 | { |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2061 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2062 | unsigned mask = 0; |
| 2063 | int i; |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2064 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2065 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2066 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) |
| 2067 | mask |= 1 << i; |
| 2068 | } |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2069 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2070 | return mask; |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2071 | } |
| 2072 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2073 | static int dsi_cio_init(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2074 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2075 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2076 | int r; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2077 | u32 l; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2078 | |
Chandrabhanu Mahapatra | 702d267 | 2012-09-24 17:12:58 +0530 | [diff] [blame] | 2079 | DSSDBG("DSI CIO init starts"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2080 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2081 | r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2082 | if (r) |
| 2083 | return r; |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2084 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2085 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2086 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2087 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 2088 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 2089 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2090 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2091 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2092 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2093 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
| 2094 | r = -EIO; |
| 2095 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2096 | } |
| 2097 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2098 | r = dsi_set_lane_config(dsidev); |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2099 | if (r) |
| 2100 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2101 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2102 | /* set TX STOP MODE timer to maximum for this operation */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2103 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2104 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 2105 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ |
| 2106 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ |
| 2107 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2108 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2109 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2110 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2111 | unsigned mask_p; |
| 2112 | int i; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2113 | |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2114 | DSSDBG("manual ulps exit\n"); |
| 2115 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2116 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
| 2117 | * stop state. DSS HW cannot do this via the normal |
| 2118 | * ULPS exit sequence, as after reset the DSS HW thinks |
| 2119 | * that we are not in ULPS mode, and refuses to send the |
| 2120 | * sequence. So we need to send the ULPS exit sequence |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2121 | * manually by setting positive lines high and negative lines |
| 2122 | * low for 1ms. |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2123 | */ |
| 2124 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2125 | mask_p = 0; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2126 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2127 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2128 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) |
| 2129 | continue; |
| 2130 | mask_p |= 1 << i; |
| 2131 | } |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2132 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2133 | dsi_cio_enable_lane_override(dsidev, mask_p, 0); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2134 | } |
| 2135 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2136 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2137 | if (r) |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2138 | goto err_cio_pwr; |
| 2139 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2140 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2141 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
| 2142 | r = -ENODEV; |
| 2143 | goto err_cio_pwr_dom; |
| 2144 | } |
| 2145 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2146 | dsi_if_enable(dsidev, true); |
| 2147 | dsi_if_enable(dsidev, false); |
| 2148 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2149 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2150 | r = dsi_cio_wait_tx_clk_esc_reset(dsidev); |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2151 | if (r) |
| 2152 | goto err_tx_clk_esc_rst; |
| 2153 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2154 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2155 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
| 2156 | ktime_t wait = ns_to_ktime(1000 * 1000); |
| 2157 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 2158 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 2159 | |
| 2160 | /* Disable the override. The lanes should be set to Mark-11 |
| 2161 | * state by the HW */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2162 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2163 | } |
| 2164 | |
| 2165 | /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2166 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2167 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2168 | dsi_cio_timings(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2169 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 2170 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2171 | /* DDR_CLK_ALWAYS_ON */ |
| 2172 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 2173 | dsi->vm_timings.ddr_clk_always_on, 13, 13); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2174 | } |
| 2175 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2176 | dsi->ulps_enabled = false; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2177 | |
| 2178 | DSSDBG("CIO init done\n"); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2179 | |
| 2180 | return 0; |
| 2181 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2182 | err_tx_clk_esc_rst: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2183 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2184 | err_cio_pwr_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2185 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2186 | err_cio_pwr: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2187 | if (dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2188 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2189 | err_scp_clk_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2190 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2191 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2192 | return r; |
| 2193 | } |
| 2194 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2195 | static void dsi_cio_uninit(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2196 | { |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 2197 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2198 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2199 | /* DDR_CLK_ALWAYS_ON */ |
| 2200 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); |
| 2201 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2202 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
| 2203 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2204 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2205 | } |
| 2206 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2207 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
| 2208 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2209 | enum fifo_size size3, enum fifo_size size4) |
| 2210 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2211 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2212 | u32 r = 0; |
| 2213 | int add = 0; |
| 2214 | int i; |
| 2215 | |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 2216 | dsi->vc[0].tx_fifo_size = size1; |
| 2217 | dsi->vc[1].tx_fifo_size = size2; |
| 2218 | dsi->vc[2].tx_fifo_size = size3; |
| 2219 | dsi->vc[3].tx_fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2220 | |
| 2221 | for (i = 0; i < 4; i++) { |
| 2222 | u8 v; |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 2223 | int size = dsi->vc[i].tx_fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2224 | |
| 2225 | if (add + size > 4) { |
| 2226 | DSSERR("Illegal FIFO configuration\n"); |
| 2227 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 2228 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2232 | r |= v << (8 * i); |
| 2233 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2234 | add += size; |
| 2235 | } |
| 2236 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2237 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2238 | } |
| 2239 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2240 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
| 2241 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2242 | enum fifo_size size3, enum fifo_size size4) |
| 2243 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2244 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2245 | u32 r = 0; |
| 2246 | int add = 0; |
| 2247 | int i; |
| 2248 | |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 2249 | dsi->vc[0].rx_fifo_size = size1; |
| 2250 | dsi->vc[1].rx_fifo_size = size2; |
| 2251 | dsi->vc[2].rx_fifo_size = size3; |
| 2252 | dsi->vc[3].rx_fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2253 | |
| 2254 | for (i = 0; i < 4; i++) { |
| 2255 | u8 v; |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 2256 | int size = dsi->vc[i].rx_fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2257 | |
| 2258 | if (add + size > 4) { |
| 2259 | DSSERR("Illegal FIFO configuration\n"); |
| 2260 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 2261 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2262 | } |
| 2263 | |
| 2264 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2265 | r |= v << (8 * i); |
| 2266 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2267 | add += size; |
| 2268 | } |
| 2269 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2270 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2271 | } |
| 2272 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2273 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2274 | { |
| 2275 | u32 r; |
| 2276 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2277 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2278 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2279 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2280 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2281 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2282 | DSSERR("TX_STOP bit not going down\n"); |
| 2283 | return -EIO; |
| 2284 | } |
| 2285 | |
| 2286 | return 0; |
| 2287 | } |
| 2288 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2289 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2290 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2291 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2292 | } |
| 2293 | |
| 2294 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) |
| 2295 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2296 | struct dsi_packet_sent_handler_data *vp_data = |
| 2297 | (struct dsi_packet_sent_handler_data *) data; |
| 2298 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2299 | const int channel = dsi->update_channel; |
| 2300 | u8 bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2301 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2302 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
| 2303 | complete(vp_data->completion); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2304 | } |
| 2305 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2306 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2307 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2308 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2309 | DECLARE_COMPLETION_ONSTACK(completion); |
Julia Lawall | 39917f0 | 2014-08-23 13:20:29 +0200 | [diff] [blame] | 2310 | struct dsi_packet_sent_handler_data vp_data = { |
| 2311 | .dsidev = dsidev, |
| 2312 | .completion = &completion |
| 2313 | }; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2314 | int r = 0; |
| 2315 | u8 bit; |
| 2316 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2317 | bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2318 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2319 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2320 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2321 | if (r) |
| 2322 | goto err0; |
| 2323 | |
| 2324 | /* Wait for completion only if TE_EN/TE_START is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2325 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2326 | if (wait_for_completion_timeout(&completion, |
| 2327 | msecs_to_jiffies(10)) == 0) { |
| 2328 | DSSERR("Failed to complete previous frame transfer\n"); |
| 2329 | r = -EIO; |
| 2330 | goto err1; |
| 2331 | } |
| 2332 | } |
| 2333 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2334 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2335 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2336 | |
| 2337 | return 0; |
| 2338 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2339 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2340 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2341 | err0: |
| 2342 | return r; |
| 2343 | } |
| 2344 | |
| 2345 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) |
| 2346 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2347 | struct dsi_packet_sent_handler_data *l4_data = |
| 2348 | (struct dsi_packet_sent_handler_data *) data; |
| 2349 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2350 | const int channel = dsi->update_channel; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2351 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2352 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
| 2353 | complete(l4_data->completion); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2354 | } |
| 2355 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2356 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2357 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2358 | DECLARE_COMPLETION_ONSTACK(completion); |
Julia Lawall | 39917f0 | 2014-08-23 13:20:29 +0200 | [diff] [blame] | 2359 | struct dsi_packet_sent_handler_data l4_data = { |
| 2360 | .dsidev = dsidev, |
| 2361 | .completion = &completion |
| 2362 | }; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2363 | int r = 0; |
| 2364 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2365 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2366 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2367 | if (r) |
| 2368 | goto err0; |
| 2369 | |
| 2370 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2371 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2372 | if (wait_for_completion_timeout(&completion, |
| 2373 | msecs_to_jiffies(10)) == 0) { |
| 2374 | DSSERR("Failed to complete previous l4 transfer\n"); |
| 2375 | r = -EIO; |
| 2376 | goto err1; |
| 2377 | } |
| 2378 | } |
| 2379 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2380 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2381 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2382 | |
| 2383 | return 0; |
| 2384 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2385 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2386 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2387 | err0: |
| 2388 | return r; |
| 2389 | } |
| 2390 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2391 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2392 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2393 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2394 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2395 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2396 | |
| 2397 | WARN_ON(in_interrupt()); |
| 2398 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2399 | if (!dsi_vc_is_enabled(dsidev, channel)) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2400 | return 0; |
| 2401 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2402 | switch (dsi->vc[channel].source) { |
| 2403 | case DSI_VC_SOURCE_VP: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2404 | return dsi_sync_vc_vp(dsidev, channel); |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2405 | case DSI_VC_SOURCE_L4: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2406 | return dsi_sync_vc_l4(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2407 | default: |
| 2408 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 2409 | return -EINVAL; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2410 | } |
| 2411 | } |
| 2412 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2413 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
| 2414 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2415 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2416 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 2417 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2418 | |
| 2419 | enable = enable ? 1 : 0; |
| 2420 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2421 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2422 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2423 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
| 2424 | 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2425 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 2426 | return -EIO; |
| 2427 | } |
| 2428 | |
| 2429 | return 0; |
| 2430 | } |
| 2431 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2432 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2433 | { |
Tomi Valkeinen | 2c1a3ea | 2013-02-22 13:42:59 +0200 | [diff] [blame] | 2434 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2435 | u32 r; |
| 2436 | |
Chandrabhanu Mahapatra | 702d267 | 2012-09-24 17:12:58 +0530 | [diff] [blame] | 2437 | DSSDBG("Initial config of virtual channel %d", channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2438 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2439 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2440 | |
| 2441 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 2442 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 2443 | channel); |
| 2444 | |
| 2445 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 2446 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 2447 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 2448 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 2449 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 2450 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 2451 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2452 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
| 2453 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2454 | |
| 2455 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 2456 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 2457 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2458 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
Tomi Valkeinen | 2c1a3ea | 2013-02-22 13:42:59 +0200 | [diff] [blame] | 2459 | |
| 2460 | dsi->vc[channel].source = DSI_VC_SOURCE_L4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2461 | } |
| 2462 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2463 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
| 2464 | enum dsi_vc_source source) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2465 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2466 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2467 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2468 | if (dsi->vc[channel].source == source) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2469 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2470 | |
Chandrabhanu Mahapatra | 702d267 | 2012-09-24 17:12:58 +0530 | [diff] [blame] | 2471 | DSSDBG("Source config of virtual channel %d", channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2472 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2473 | dsi_sync_vc(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2474 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2475 | dsi_vc_enable(dsidev, channel, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2476 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2477 | /* VC_BUSY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2478 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2479 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2480 | return -EIO; |
| 2481 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2482 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2483 | /* SOURCE, 0 = L4, 1 = video port */ |
| 2484 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2485 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2486 | /* DCS_CMD_ENABLE */ |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2487 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 2488 | bool enable = source == DSI_VC_SOURCE_VP; |
| 2489 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); |
| 2490 | } |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2491 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2492 | dsi_vc_enable(dsidev, channel, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2493 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2494 | dsi->vc[channel].source = source; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2495 | |
| 2496 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2497 | } |
| 2498 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2499 | static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2500 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2501 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2502 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 2503 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2504 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2505 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 2506 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2507 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2508 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2509 | dsi_vc_enable(dsidev, channel, 0); |
| 2510 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2511 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2512 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2513 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2514 | dsi_vc_enable(dsidev, channel, 1); |
| 2515 | dsi_if_enable(dsidev, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2516 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2517 | dsi_force_tx_stop_mode_io(dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2518 | |
| 2519 | /* start the DDR clock by sending a NULL packet */ |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 2520 | if (dsi->vm_timings.ddr_clk_always_on && enable) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2521 | dsi_vc_send_null(dssdev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2522 | } |
| 2523 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2524 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2525 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2526 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2527 | u32 val; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2528 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2529 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 2530 | (val >> 0) & 0xff, |
| 2531 | (val >> 8) & 0xff, |
| 2532 | (val >> 16) & 0xff, |
| 2533 | (val >> 24) & 0xff); |
| 2534 | } |
| 2535 | } |
| 2536 | |
| 2537 | static void dsi_show_rx_ack_with_err(u16 err) |
| 2538 | { |
| 2539 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 2540 | if (err & (1 << 0)) |
| 2541 | DSSERR("\t\tSoT Error\n"); |
| 2542 | if (err & (1 << 1)) |
| 2543 | DSSERR("\t\tSoT Sync Error\n"); |
| 2544 | if (err & (1 << 2)) |
| 2545 | DSSERR("\t\tEoT Sync Error\n"); |
| 2546 | if (err & (1 << 3)) |
| 2547 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 2548 | if (err & (1 << 4)) |
| 2549 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 2550 | if (err & (1 << 5)) |
| 2551 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 2552 | if (err & (1 << 6)) |
| 2553 | DSSERR("\t\tFalse Control Error\n"); |
| 2554 | if (err & (1 << 7)) |
| 2555 | DSSERR("\t\t(reserved7)\n"); |
| 2556 | if (err & (1 << 8)) |
| 2557 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 2558 | if (err & (1 << 9)) |
| 2559 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 2560 | if (err & (1 << 10)) |
| 2561 | DSSERR("\t\tChecksum Error\n"); |
| 2562 | if (err & (1 << 11)) |
| 2563 | DSSERR("\t\tData type not recognized\n"); |
| 2564 | if (err & (1 << 12)) |
| 2565 | DSSERR("\t\tInvalid VC ID\n"); |
| 2566 | if (err & (1 << 13)) |
| 2567 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 2568 | if (err & (1 << 14)) |
| 2569 | DSSERR("\t\t(reserved14)\n"); |
| 2570 | if (err & (1 << 15)) |
| 2571 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 2572 | } |
| 2573 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2574 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
| 2575 | int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2576 | { |
| 2577 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2578 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2579 | u32 val; |
| 2580 | u8 dt; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2581 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2582 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2583 | dt = FLD_GET(val, 5, 0); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2584 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2585 | u16 err = FLD_GET(val, 23, 8); |
| 2586 | dsi_show_rx_ack_with_err(err); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2587 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2588 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2589 | FLD_GET(val, 23, 8)); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2590 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2591 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2592 | FLD_GET(val, 23, 8)); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2593 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2594 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2595 | FLD_GET(val, 23, 8)); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2596 | dsi_vc_flush_long_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2597 | } else { |
| 2598 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 2599 | } |
| 2600 | } |
| 2601 | return 0; |
| 2602 | } |
| 2603 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2604 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2605 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2606 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2607 | |
| 2608 | if (dsi->debug_write || dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2609 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 2610 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2611 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2612 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2613 | /* RX_FIFO_NOT_EMPTY */ |
| 2614 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2615 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2616 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2617 | } |
| 2618 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2619 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2620 | |
Tomi Valkeinen | 968f8e9 | 2011-10-12 10:13:14 +0300 | [diff] [blame] | 2621 | /* flush posted write */ |
| 2622 | dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
| 2623 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2624 | return 0; |
| 2625 | } |
| 2626 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2627 | static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2628 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2629 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2630 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2631 | int r = 0; |
| 2632 | u32 err; |
| 2633 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2634 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2635 | &completion, DSI_VC_IRQ_BTA); |
| 2636 | if (r) |
| 2637 | goto err0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2638 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2639 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2640 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2641 | if (r) |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2642 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2643 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2644 | r = dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2645 | if (r) |
| 2646 | goto err2; |
| 2647 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2648 | if (wait_for_completion_timeout(&completion, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2649 | msecs_to_jiffies(500)) == 0) { |
| 2650 | DSSERR("Failed to receive BTA\n"); |
| 2651 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2652 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2653 | } |
| 2654 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2655 | err = dsi_get_errors(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2656 | if (err) { |
| 2657 | DSSERR("Error while sending BTA: %x\n", err); |
| 2658 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2659 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2660 | } |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2661 | err2: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2662 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2663 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2664 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2665 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2666 | &completion, DSI_VC_IRQ_BTA); |
| 2667 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2668 | return r; |
| 2669 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2670 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2671 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
| 2672 | int channel, u8 data_type, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2673 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2674 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2675 | u32 val; |
| 2676 | u8 data_id; |
| 2677 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2678 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2679 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2680 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2681 | |
| 2682 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 2683 | FLD_VAL(ecc, 31, 24); |
| 2684 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2685 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2686 | } |
| 2687 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2688 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
| 2689 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2690 | { |
| 2691 | u32 val; |
| 2692 | |
| 2693 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 2694 | |
| 2695 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 2696 | b1, b2, b3, b4, val); */ |
| 2697 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2698 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2699 | } |
| 2700 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2701 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
| 2702 | u8 data_type, u8 *data, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2703 | { |
| 2704 | /*u32 val; */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2705 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2706 | int i; |
| 2707 | u8 *p; |
| 2708 | int r = 0; |
| 2709 | u8 b1, b2, b3, b4; |
| 2710 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2711 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2712 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 2713 | |
| 2714 | /* len + header */ |
Tomi Valkeinen | 558c73e | 2013-09-25 14:40:06 +0300 | [diff] [blame] | 2715 | if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2716 | DSSERR("unable to send long packet: packet too long.\n"); |
| 2717 | return -EINVAL; |
| 2718 | } |
| 2719 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2720 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2721 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2722 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2723 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2724 | p = data; |
| 2725 | for (i = 0; i < len >> 2; i++) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2726 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2727 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2728 | |
| 2729 | b1 = *p++; |
| 2730 | b2 = *p++; |
| 2731 | b3 = *p++; |
| 2732 | b4 = *p++; |
| 2733 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2734 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2735 | } |
| 2736 | |
| 2737 | i = len % 4; |
| 2738 | if (i) { |
| 2739 | b1 = 0; b2 = 0; b3 = 0; |
| 2740 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2741 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2742 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2743 | |
| 2744 | switch (i) { |
| 2745 | case 3: |
| 2746 | b1 = *p++; |
| 2747 | b2 = *p++; |
| 2748 | b3 = *p++; |
| 2749 | break; |
| 2750 | case 2: |
| 2751 | b1 = *p++; |
| 2752 | b2 = *p++; |
| 2753 | break; |
| 2754 | case 1: |
| 2755 | b1 = *p++; |
| 2756 | break; |
| 2757 | } |
| 2758 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2759 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2760 | } |
| 2761 | |
| 2762 | return r; |
| 2763 | } |
| 2764 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2765 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
| 2766 | u8 data_type, u16 data, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2767 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2768 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2769 | u32 r; |
| 2770 | u8 data_id; |
| 2771 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2772 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2773 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2774 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2775 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2776 | channel, |
| 2777 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2778 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2779 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2780 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2781 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2782 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2783 | return -EINVAL; |
| 2784 | } |
| 2785 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2786 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2787 | |
| 2788 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2789 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2790 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2791 | |
| 2792 | return 0; |
| 2793 | } |
| 2794 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2795 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2796 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2797 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2798 | |
Archit Taneja | 18b7d09 | 2011-09-05 17:01:08 +0530 | [diff] [blame] | 2799 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, |
| 2800 | 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2801 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2802 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2803 | static int dsi_vc_write_nosync_common(struct platform_device *dsidev, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2804 | int channel, u8 *data, int len, enum dss_dsi_content_type type) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2805 | { |
| 2806 | int r; |
| 2807 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2808 | if (len == 0) { |
| 2809 | BUG_ON(type == DSS_DSI_CONTENT_DCS); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2810 | r = dsi_vc_send_short(dsidev, channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2811 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
| 2812 | } else if (len == 1) { |
| 2813 | r = dsi_vc_send_short(dsidev, channel, |
| 2814 | type == DSS_DSI_CONTENT_GENERIC ? |
| 2815 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2816 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2817 | } else if (len == 2) { |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2818 | r = dsi_vc_send_short(dsidev, channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2819 | type == DSS_DSI_CONTENT_GENERIC ? |
| 2820 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2821 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2822 | data[0] | (data[1] << 8), 0); |
| 2823 | } else { |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2824 | r = dsi_vc_send_long(dsidev, channel, |
| 2825 | type == DSS_DSI_CONTENT_GENERIC ? |
| 2826 | MIPI_DSI_GENERIC_LONG_WRITE : |
| 2827 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2828 | } |
| 2829 | |
| 2830 | return r; |
| 2831 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2832 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2833 | static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2834 | u8 *data, int len) |
| 2835 | { |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2836 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 2837 | |
| 2838 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2839 | DSS_DSI_CONTENT_DCS); |
| 2840 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2841 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2842 | static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2843 | u8 *data, int len) |
| 2844 | { |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2845 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 2846 | |
| 2847 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2848 | DSS_DSI_CONTENT_GENERIC); |
| 2849 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2850 | |
| 2851 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, |
| 2852 | u8 *data, int len, enum dss_dsi_content_type type) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2853 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2854 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2855 | int r; |
| 2856 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2857 | r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2858 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2859 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2860 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2861 | r = dsi_vc_send_bta_sync(dssdev, channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2862 | if (r) |
| 2863 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2864 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2865 | /* RX_FIFO_NOT_EMPTY */ |
| 2866 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2867 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2868 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 2869 | r = -EIO; |
| 2870 | goto err; |
| 2871 | } |
| 2872 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2873 | return 0; |
| 2874 | err: |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2875 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2876 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2877 | return r; |
| 2878 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2879 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2880 | static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2881 | int len) |
| 2882 | { |
| 2883 | return dsi_vc_write_common(dssdev, channel, data, len, |
| 2884 | DSS_DSI_CONTENT_DCS); |
| 2885 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2886 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 2887 | static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2888 | int len) |
| 2889 | { |
| 2890 | return dsi_vc_write_common(dssdev, channel, data, len, |
| 2891 | DSS_DSI_CONTENT_GENERIC); |
| 2892 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2893 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2894 | static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 2895 | int channel, u8 dcs_cmd) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2896 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2897 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 2898 | int r; |
| 2899 | |
| 2900 | if (dsi->debug_read) |
| 2901 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
| 2902 | channel, dcs_cmd); |
| 2903 | |
| 2904 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
| 2905 | if (r) { |
| 2906 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" |
| 2907 | " failed\n", channel, dcs_cmd); |
| 2908 | return r; |
| 2909 | } |
| 2910 | |
| 2911 | return 0; |
| 2912 | } |
| 2913 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 2914 | static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2915 | int channel, u8 *reqdata, int reqlen) |
| 2916 | { |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2917 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2918 | u16 data; |
| 2919 | u8 data_type; |
| 2920 | int r; |
| 2921 | |
| 2922 | if (dsi->debug_read) |
| 2923 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", |
| 2924 | channel, reqlen); |
| 2925 | |
| 2926 | if (reqlen == 0) { |
| 2927 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; |
| 2928 | data = 0; |
| 2929 | } else if (reqlen == 1) { |
| 2930 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; |
| 2931 | data = reqdata[0]; |
| 2932 | } else if (reqlen == 2) { |
| 2933 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; |
| 2934 | data = reqdata[0] | (reqdata[1] << 8); |
| 2935 | } else { |
| 2936 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 2937 | return -EINVAL; |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2938 | } |
| 2939 | |
| 2940 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); |
| 2941 | if (r) { |
| 2942 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" |
| 2943 | " failed\n", channel, reqlen); |
| 2944 | return r; |
| 2945 | } |
| 2946 | |
| 2947 | return 0; |
| 2948 | } |
| 2949 | |
| 2950 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, |
| 2951 | u8 *buf, int buflen, enum dss_dsi_content_type type) |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 2952 | { |
| 2953 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2954 | u32 val; |
| 2955 | u8 dt; |
| 2956 | int r; |
| 2957 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2958 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2959 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2960 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2961 | r = -EIO; |
| 2962 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2963 | } |
| 2964 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2965 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2966 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2967 | DSSDBG("\theader: %08x\n", val); |
| 2968 | dt = FLD_GET(val, 5, 0); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2969 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2970 | u16 err = FLD_GET(val, 23, 8); |
| 2971 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2972 | r = -EIO; |
| 2973 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2974 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2975 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 2976 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : |
| 2977 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2978 | u8 data = FLD_GET(val, 15, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2979 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2980 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
| 2981 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 2982 | "DCS", data); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2983 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 2984 | if (buflen < 1) { |
| 2985 | r = -EIO; |
| 2986 | goto err; |
| 2987 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2988 | |
| 2989 | buf[0] = data; |
| 2990 | |
| 2991 | return 1; |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2992 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 2993 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : |
| 2994 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2995 | u16 data = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2996 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 2997 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
| 2998 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 2999 | "DCS", data); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3000 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3001 | if (buflen < 2) { |
| 3002 | r = -EIO; |
| 3003 | goto err; |
| 3004 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3005 | |
| 3006 | buf[0] = data & 0xff; |
| 3007 | buf[1] = (data >> 8) & 0xff; |
| 3008 | |
| 3009 | return 2; |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3010 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 3011 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : |
| 3012 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3013 | int w; |
| 3014 | int len = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3015 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3016 | DSSDBG("\t%s long response, len %d\n", |
| 3017 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 3018 | "DCS", len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3019 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3020 | if (len > buflen) { |
| 3021 | r = -EIO; |
| 3022 | goto err; |
| 3023 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3024 | |
| 3025 | /* two byte checksum ends the packet, not included in len */ |
| 3026 | for (w = 0; w < len + 2;) { |
| 3027 | int b; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3028 | val = dsi_read_reg(dsidev, |
| 3029 | DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3030 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3031 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 3032 | (val >> 0) & 0xff, |
| 3033 | (val >> 8) & 0xff, |
| 3034 | (val >> 16) & 0xff, |
| 3035 | (val >> 24) & 0xff); |
| 3036 | |
| 3037 | for (b = 0; b < 4; ++b) { |
| 3038 | if (w < len) |
| 3039 | buf[w] = (val >> (b * 8)) & 0xff; |
| 3040 | /* we discard the 2 byte checksum */ |
| 3041 | ++w; |
| 3042 | } |
| 3043 | } |
| 3044 | |
| 3045 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3046 | } else { |
| 3047 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3048 | r = -EIO; |
| 3049 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3050 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3051 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3052 | err: |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3053 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
| 3054 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3055 | |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3056 | return r; |
| 3057 | } |
| 3058 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 3059 | static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3060 | u8 *buf, int buflen) |
| 3061 | { |
| 3062 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3063 | int r; |
| 3064 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3065 | r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3066 | if (r) |
| 3067 | goto err; |
| 3068 | |
| 3069 | r = dsi_vc_send_bta_sync(dssdev, channel); |
| 3070 | if (r) |
| 3071 | goto err; |
| 3072 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3073 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
| 3074 | DSS_DSI_CONTENT_DCS); |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3075 | if (r < 0) |
| 3076 | goto err; |
| 3077 | |
| 3078 | if (r != buflen) { |
| 3079 | r = -EIO; |
| 3080 | goto err; |
| 3081 | } |
| 3082 | |
| 3083 | return 0; |
| 3084 | err: |
| 3085 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); |
| 3086 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3087 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3088 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3089 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
| 3090 | u8 *reqdata, int reqlen, u8 *buf, int buflen) |
| 3091 | { |
| 3092 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3093 | int r; |
| 3094 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3095 | r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3096 | if (r) |
| 3097 | return r; |
| 3098 | |
| 3099 | r = dsi_vc_send_bta_sync(dssdev, channel); |
| 3100 | if (r) |
| 3101 | return r; |
| 3102 | |
| 3103 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
| 3104 | DSS_DSI_CONTENT_GENERIC); |
| 3105 | if (r < 0) |
| 3106 | return r; |
| 3107 | |
| 3108 | if (r != buflen) { |
| 3109 | r = -EIO; |
| 3110 | return r; |
| 3111 | } |
| 3112 | |
| 3113 | return 0; |
| 3114 | } |
| 3115 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 3116 | static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3117 | u16 len) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3118 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3119 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3120 | |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3121 | return dsi_vc_send_short(dsidev, channel, |
| 3122 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3123 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3124 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3125 | static int dsi_enter_ulps(struct platform_device *dsidev) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3126 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3127 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3128 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3129 | int r, i; |
| 3130 | unsigned mask; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3131 | |
Chandrabhanu Mahapatra | 702d267 | 2012-09-24 17:12:58 +0530 | [diff] [blame] | 3132 | DSSDBG("Entering ULPS"); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3133 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3134 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3135 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3136 | WARN_ON(dsi->ulps_enabled); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3137 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3138 | if (dsi->ulps_enabled) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3139 | return 0; |
| 3140 | |
Tomi Valkeinen | 6cc78aa | 2011-10-13 19:22:43 +0300 | [diff] [blame] | 3141 | /* DDR_CLK_ALWAYS_ON */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3142 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
Tomi Valkeinen | 6cc78aa | 2011-10-13 19:22:43 +0300 | [diff] [blame] | 3143 | dsi_if_enable(dsidev, 0); |
| 3144 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); |
| 3145 | dsi_if_enable(dsidev, 1); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3146 | } |
| 3147 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3148 | dsi_sync_vc(dsidev, 0); |
| 3149 | dsi_sync_vc(dsidev, 1); |
| 3150 | dsi_sync_vc(dsidev, 2); |
| 3151 | dsi_sync_vc(dsidev, 3); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3152 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3153 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3154 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3155 | dsi_vc_enable(dsidev, 0, false); |
| 3156 | dsi_vc_enable(dsidev, 1, false); |
| 3157 | dsi_vc_enable(dsidev, 2, false); |
| 3158 | dsi_vc_enable(dsidev, 3, false); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3159 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3160 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3161 | DSSERR("HS busy when enabling ULPS\n"); |
| 3162 | return -EIO; |
| 3163 | } |
| 3164 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3165 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3166 | DSSERR("LP busy when enabling ULPS\n"); |
| 3167 | return -EIO; |
| 3168 | } |
| 3169 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3170 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3171 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3172 | if (r) |
| 3173 | return r; |
| 3174 | |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3175 | mask = 0; |
| 3176 | |
| 3177 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 3178 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) |
| 3179 | continue; |
| 3180 | mask |= 1 << i; |
| 3181 | } |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3182 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
| 3183 | /* LANEx_ULPS_SIG2 */ |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3184 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3185 | |
Tomi Valkeinen | a702c85 | 2011-10-12 10:10:21 +0300 | [diff] [blame] | 3186 | /* flush posted write and wait for SCP interface to finish the write */ |
| 3187 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3188 | |
| 3189 | if (wait_for_completion_timeout(&completion, |
| 3190 | msecs_to_jiffies(1000)) == 0) { |
| 3191 | DSSERR("ULPS enable timeout\n"); |
| 3192 | r = -EIO; |
| 3193 | goto err; |
| 3194 | } |
| 3195 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3196 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3197 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3198 | |
Tomi Valkeinen | 8ef0e61 | 2011-05-31 16:55:47 +0300 | [diff] [blame] | 3199 | /* Reset LANEx_ULPS_SIG2 */ |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3200 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); |
Tomi Valkeinen | 8ef0e61 | 2011-05-31 16:55:47 +0300 | [diff] [blame] | 3201 | |
Tomi Valkeinen | a702c85 | 2011-10-12 10:10:21 +0300 | [diff] [blame] | 3202 | /* flush posted write and wait for SCP interface to finish the write */ |
| 3203 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3204 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3205 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3206 | |
| 3207 | dsi_if_enable(dsidev, false); |
| 3208 | |
| 3209 | dsi->ulps_enabled = true; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3210 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3211 | return 0; |
| 3212 | |
| 3213 | err: |
| 3214 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3215 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3216 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3217 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3218 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3219 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
| 3220 | unsigned ticks, bool x4, bool x16) |
| 3221 | { |
| 3222 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3223 | unsigned long total_ticks; |
| 3224 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3225 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3226 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3227 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3228 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3229 | fck = dsi_fclk_rate(dsidev); |
| 3230 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3231 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3232 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3233 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3234 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
| 3235 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
| 3236 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
| 3237 | |
| 3238 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3239 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3240 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3241 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3242 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3243 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3244 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3245 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3246 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
| 3247 | bool x8, bool x16) |
| 3248 | { |
| 3249 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3250 | unsigned long total_ticks; |
| 3251 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3252 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3253 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3254 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3255 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3256 | fck = dsi_fclk_rate(dsidev); |
| 3257 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3258 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3259 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3260 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3261 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
| 3262 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
| 3263 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
| 3264 | |
| 3265 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 3266 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3267 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3268 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3269 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 3270 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3271 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3272 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3273 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
| 3274 | unsigned ticks, bool x4, bool x16) |
| 3275 | { |
| 3276 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3277 | unsigned long total_ticks; |
| 3278 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3279 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3280 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3281 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3282 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3283 | fck = dsi_fclk_rate(dsidev); |
| 3284 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3285 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3286 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3287 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3288 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
| 3289 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 3290 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
| 3291 | |
| 3292 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3293 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3294 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 3295 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3296 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3297 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3298 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3299 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3300 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
| 3301 | unsigned ticks, bool x4, bool x16) |
| 3302 | { |
| 3303 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3304 | unsigned long total_ticks; |
| 3305 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3306 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3307 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3308 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3309 | /* ticks in TxByteClkHS */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3310 | fck = dsi_get_txbyteclkhs(dsidev); |
| 3311 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3312 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3313 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3314 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3315 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
| 3316 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
| 3317 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
| 3318 | |
| 3319 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3320 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3321 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3322 | total_ticks, |
| 3323 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3324 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3325 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3326 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3327 | static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3328 | { |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3329 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3330 | int num_line_buffers; |
| 3331 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3332 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3333 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 3334 | struct omap_video_timings *timings = &dsi->timings; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3335 | /* |
| 3336 | * Don't use line buffers if width is greater than the video |
| 3337 | * port's line buffer size |
| 3338 | */ |
Tomi Valkeinen | 9932257 | 2013-03-05 10:37:02 +0200 | [diff] [blame] | 3339 | if (dsi->line_buffer_size <= timings->x_res * bpp / 8) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3340 | num_line_buffers = 0; |
| 3341 | else |
| 3342 | num_line_buffers = 2; |
| 3343 | } else { |
| 3344 | /* Use maximum number of line buffers in command mode */ |
| 3345 | num_line_buffers = 2; |
| 3346 | } |
| 3347 | |
| 3348 | /* LINE_BUFFER */ |
| 3349 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); |
| 3350 | } |
| 3351 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3352 | static void dsi_config_vp_sync_events(struct platform_device *dsidev) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3353 | { |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 3354 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3355 | bool sync_end; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3356 | u32 r; |
| 3357 | |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3358 | if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) |
| 3359 | sync_end = true; |
| 3360 | else |
| 3361 | sync_end = false; |
| 3362 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3363 | r = dsi_read_reg(dsidev, DSI_CTRL); |
Archit Taneja | bd5a7b1 | 2012-06-26 12:38:31 +0530 | [diff] [blame] | 3364 | r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ |
| 3365 | r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ |
| 3366 | r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3367 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3368 | r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3369 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3370 | r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3371 | dsi_write_reg(dsidev, DSI_CTRL, r); |
| 3372 | } |
| 3373 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3374 | static void dsi_config_blanking_modes(struct platform_device *dsidev) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3375 | { |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 3376 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3377 | int blanking_mode = dsi->vm_timings.blanking_mode; |
| 3378 | int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; |
| 3379 | int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; |
| 3380 | int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3381 | u32 r; |
| 3382 | |
| 3383 | /* |
| 3384 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods |
| 3385 | * 1 = Long blanking packets are sent in corresponding blanking periods |
| 3386 | */ |
| 3387 | r = dsi_read_reg(dsidev, DSI_CTRL); |
| 3388 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ |
| 3389 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ |
| 3390 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ |
| 3391 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ |
| 3392 | dsi_write_reg(dsidev, DSI_CTRL, r); |
| 3393 | } |
| 3394 | |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3395 | /* |
| 3396 | * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 |
| 3397 | * results in maximum transition time for data and clock lanes to enter and |
| 3398 | * exit HS mode. Hence, this is the scenario where the least amount of command |
| 3399 | * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS |
| 3400 | * clock cycles that can be used to interleave command mode data in HS so that |
| 3401 | * all scenarios are satisfied. |
| 3402 | */ |
| 3403 | static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, |
| 3404 | int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) |
| 3405 | { |
| 3406 | int transition; |
| 3407 | |
| 3408 | /* |
| 3409 | * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition |
| 3410 | * time of data lanes only, if it isn't set, we need to consider HS |
| 3411 | * transition time of both data and clock lanes. HS transition time |
| 3412 | * of Scenario 3 is considered. |
| 3413 | */ |
| 3414 | if (ddr_alwon) { |
| 3415 | transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; |
| 3416 | } else { |
| 3417 | int trans1, trans2; |
| 3418 | trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; |
| 3419 | trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + |
| 3420 | enter_hs + 1; |
| 3421 | transition = max(trans1, trans2); |
| 3422 | } |
| 3423 | |
| 3424 | return blank > transition ? blank - transition : 0; |
| 3425 | } |
| 3426 | |
| 3427 | /* |
| 3428 | * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 |
| 3429 | * results in maximum transition time for data lanes to enter and exit LP mode. |
| 3430 | * Hence, this is the scenario where the least amount of command mode data can |
| 3431 | * be interleaved. We program the minimum amount of bytes that can be |
| 3432 | * interleaved in LP so that all scenarios are satisfied. |
| 3433 | */ |
| 3434 | static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, |
| 3435 | int lp_clk_div, int tdsi_fclk) |
| 3436 | { |
| 3437 | int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ |
| 3438 | int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ |
| 3439 | int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ |
| 3440 | int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ |
| 3441 | int lp_inter; /* cmd mode data that can be interleaved, in bytes */ |
| 3442 | |
| 3443 | /* maximum LP transition time according to Scenario 1 */ |
| 3444 | trans_lp = exit_hs + max(enter_hs, 2) + 1; |
| 3445 | |
| 3446 | /* CLKIN4DDR = 16 * TXBYTECLKHS */ |
| 3447 | tlp_avail = thsbyte_clk * (blank - trans_lp); |
| 3448 | |
Archit Taneja | 2e063c3 | 2012-06-04 13:36:34 +0530 | [diff] [blame] | 3449 | ttxclkesc = tdsi_fclk * lp_clk_div; |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3450 | |
| 3451 | lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - |
| 3452 | 26) / 16; |
| 3453 | |
| 3454 | return max(lp_inter, 0); |
| 3455 | } |
| 3456 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3457 | static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3458 | { |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3459 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3460 | int blanking_mode; |
| 3461 | int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; |
| 3462 | int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; |
| 3463 | int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; |
| 3464 | int tclk_trail, ths_exit, exiths_clk; |
| 3465 | bool ddr_alwon; |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 3466 | struct omap_video_timings *timings = &dsi->timings; |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3467 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3468 | int ndl = dsi->num_lanes_used - 1; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 3469 | int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; |
Archit Taneja | 6f28c29 | 2012-05-15 11:32:18 +0530 | [diff] [blame] | 3470 | int hsa_interleave_hs = 0, hsa_interleave_lp = 0; |
| 3471 | int hfp_interleave_hs = 0, hfp_interleave_lp = 0; |
| 3472 | int hbp_interleave_hs = 0, hbp_interleave_lp = 0; |
| 3473 | int bl_interleave_hs = 0, bl_interleave_lp = 0; |
| 3474 | u32 r; |
| 3475 | |
| 3476 | r = dsi_read_reg(dsidev, DSI_CTRL); |
| 3477 | blanking_mode = FLD_GET(r, 20, 20); |
| 3478 | hfp_blanking_mode = FLD_GET(r, 21, 21); |
| 3479 | hbp_blanking_mode = FLD_GET(r, 22, 22); |
| 3480 | hsa_blanking_mode = FLD_GET(r, 23, 23); |
| 3481 | |
| 3482 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); |
| 3483 | hbp = FLD_GET(r, 11, 0); |
| 3484 | hfp = FLD_GET(r, 23, 12); |
| 3485 | hsa = FLD_GET(r, 31, 24); |
| 3486 | |
| 3487 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
| 3488 | ddr_clk_post = FLD_GET(r, 7, 0); |
| 3489 | ddr_clk_pre = FLD_GET(r, 15, 8); |
| 3490 | |
| 3491 | r = dsi_read_reg(dsidev, DSI_VM_TIMING7); |
| 3492 | exit_hs_mode_lat = FLD_GET(r, 15, 0); |
| 3493 | enter_hs_mode_lat = FLD_GET(r, 31, 16); |
| 3494 | |
| 3495 | r = dsi_read_reg(dsidev, DSI_CLK_CTRL); |
| 3496 | lp_clk_div = FLD_GET(r, 12, 0); |
| 3497 | ddr_alwon = FLD_GET(r, 13, 13); |
| 3498 | |
| 3499 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
| 3500 | ths_exit = FLD_GET(r, 7, 0); |
| 3501 | |
| 3502 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
| 3503 | tclk_trail = FLD_GET(r, 15, 8); |
| 3504 | |
| 3505 | exiths_clk = ths_exit + tclk_trail; |
| 3506 | |
| 3507 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); |
| 3508 | bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); |
| 3509 | |
| 3510 | if (!hsa_blanking_mode) { |
| 3511 | hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, |
| 3512 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3513 | exiths_clk, ddr_clk_pre, ddr_clk_post); |
| 3514 | hsa_interleave_lp = dsi_compute_interleave_lp(hsa, |
| 3515 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3516 | lp_clk_div, dsi_fclk_hsdiv); |
| 3517 | } |
| 3518 | |
| 3519 | if (!hfp_blanking_mode) { |
| 3520 | hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, |
| 3521 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3522 | exiths_clk, ddr_clk_pre, ddr_clk_post); |
| 3523 | hfp_interleave_lp = dsi_compute_interleave_lp(hfp, |
| 3524 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3525 | lp_clk_div, dsi_fclk_hsdiv); |
| 3526 | } |
| 3527 | |
| 3528 | if (!hbp_blanking_mode) { |
| 3529 | hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, |
| 3530 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3531 | exiths_clk, ddr_clk_pre, ddr_clk_post); |
| 3532 | |
| 3533 | hbp_interleave_lp = dsi_compute_interleave_lp(hbp, |
| 3534 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3535 | lp_clk_div, dsi_fclk_hsdiv); |
| 3536 | } |
| 3537 | |
| 3538 | if (!blanking_mode) { |
| 3539 | bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, |
| 3540 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3541 | exiths_clk, ddr_clk_pre, ddr_clk_post); |
| 3542 | |
| 3543 | bl_interleave_lp = dsi_compute_interleave_lp(bllp, |
| 3544 | enter_hs_mode_lat, exit_hs_mode_lat, |
| 3545 | lp_clk_div, dsi_fclk_hsdiv); |
| 3546 | } |
| 3547 | |
| 3548 | DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", |
| 3549 | hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, |
| 3550 | bl_interleave_hs); |
| 3551 | |
| 3552 | DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", |
| 3553 | hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, |
| 3554 | bl_interleave_lp); |
| 3555 | |
| 3556 | r = dsi_read_reg(dsidev, DSI_VM_TIMING4); |
| 3557 | r = FLD_MOD(r, hsa_interleave_hs, 23, 16); |
| 3558 | r = FLD_MOD(r, hfp_interleave_hs, 15, 8); |
| 3559 | r = FLD_MOD(r, hbp_interleave_hs, 7, 0); |
| 3560 | dsi_write_reg(dsidev, DSI_VM_TIMING4, r); |
| 3561 | |
| 3562 | r = dsi_read_reg(dsidev, DSI_VM_TIMING5); |
| 3563 | r = FLD_MOD(r, hsa_interleave_lp, 23, 16); |
| 3564 | r = FLD_MOD(r, hfp_interleave_lp, 15, 8); |
| 3565 | r = FLD_MOD(r, hbp_interleave_lp, 7, 0); |
| 3566 | dsi_write_reg(dsidev, DSI_VM_TIMING5, r); |
| 3567 | |
| 3568 | r = dsi_read_reg(dsidev, DSI_VM_TIMING6); |
| 3569 | r = FLD_MOD(r, bl_interleave_hs, 31, 15); |
| 3570 | r = FLD_MOD(r, bl_interleave_lp, 16, 0); |
| 3571 | dsi_write_reg(dsidev, DSI_VM_TIMING6, r); |
| 3572 | } |
| 3573 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3574 | static int dsi_proto_config(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3575 | { |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3576 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3577 | u32 r; |
| 3578 | int buswidth = 0; |
| 3579 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3580 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3581 | DSI_FIFO_SIZE_32, |
| 3582 | DSI_FIFO_SIZE_32, |
| 3583 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3584 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3585 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3586 | DSI_FIFO_SIZE_32, |
| 3587 | DSI_FIFO_SIZE_32, |
| 3588 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3589 | |
| 3590 | /* XXX what values for the timeouts? */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3591 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
| 3592 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); |
| 3593 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); |
| 3594 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3595 | |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3596 | switch (dsi_get_pixel_size(dsi->pix_fmt)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3597 | case 16: |
| 3598 | buswidth = 0; |
| 3599 | break; |
| 3600 | case 18: |
| 3601 | buswidth = 1; |
| 3602 | break; |
| 3603 | case 24: |
| 3604 | buswidth = 2; |
| 3605 | break; |
| 3606 | default: |
| 3607 | BUG(); |
Tomi Valkeinen | c6eee96 | 2012-05-18 11:47:02 +0300 | [diff] [blame] | 3608 | return -EINVAL; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3609 | } |
| 3610 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3611 | r = dsi_read_reg(dsidev, DSI_CTRL); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3612 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 3613 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 3614 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 3615 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 3616 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 3617 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3618 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 3619 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3620 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 3621 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 3622 | /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 3623 | r = FLD_MOD(r, 0, 25, 25); |
| 3624 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3625 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3626 | dsi_write_reg(dsidev, DSI_CTRL, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3627 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3628 | dsi_config_vp_num_line_buffers(dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3629 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3630 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3631 | dsi_config_vp_sync_events(dsidev); |
| 3632 | dsi_config_blanking_modes(dsidev); |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3633 | dsi_config_cmd_mode_interleaving(dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3634 | } |
| 3635 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3636 | dsi_vc_initial_config(dsidev, 0); |
| 3637 | dsi_vc_initial_config(dsidev, 1); |
| 3638 | dsi_vc_initial_config(dsidev, 2); |
| 3639 | dsi_vc_initial_config(dsidev, 3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3640 | |
| 3641 | return 0; |
| 3642 | } |
| 3643 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 3644 | static void dsi_proto_timings(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3645 | { |
Tomi Valkeinen | db18644 | 2011-10-13 16:12:29 +0300 | [diff] [blame] | 3646 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3647 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 3648 | unsigned tclk_pre, tclk_post; |
| 3649 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 3650 | unsigned ths_trail, ths_exit; |
| 3651 | unsigned ddr_clk_pre, ddr_clk_post; |
| 3652 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 3653 | unsigned ths_eot; |
Tomi Valkeinen | db18644 | 2011-10-13 16:12:29 +0300 | [diff] [blame] | 3654 | int ndl = dsi->num_lanes_used - 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3655 | u32 r; |
| 3656 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3657 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3658 | ths_prepare = FLD_GET(r, 31, 24); |
| 3659 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 3660 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 3661 | ths_trail = FLD_GET(r, 15, 8); |
| 3662 | ths_exit = FLD_GET(r, 7, 0); |
| 3663 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3664 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | e84dc1c | 2012-09-24 09:34:52 +0300 | [diff] [blame] | 3665 | tlpx = FLD_GET(r, 20, 16) * 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3666 | tclk_trail = FLD_GET(r, 15, 8); |
| 3667 | tclk_zero = FLD_GET(r, 7, 0); |
| 3668 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3669 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3670 | tclk_prepare = FLD_GET(r, 7, 0); |
| 3671 | |
| 3672 | /* min 8*UI */ |
| 3673 | tclk_pre = 20; |
| 3674 | /* min 60ns + 52*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3675 | tclk_post = ns2ddr(dsidev, 60) + 26; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3676 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3677 | ths_eot = DIV_ROUND_UP(4, ndl); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3678 | |
| 3679 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 3680 | 4); |
| 3681 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 3682 | |
| 3683 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 3684 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 3685 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3686 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3687 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 3688 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3689 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3690 | |
| 3691 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 3692 | ddr_clk_pre, |
| 3693 | ddr_clk_post); |
| 3694 | |
| 3695 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 3696 | DIV_ROUND_UP(ths_prepare, 4) + |
| 3697 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 3698 | |
| 3699 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 3700 | |
| 3701 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 3702 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3703 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3704 | |
| 3705 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 3706 | enter_hs_mode_lat, exit_hs_mode_lat); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3707 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3708 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3709 | /* TODO: Implement a video mode check_timings function */ |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 3710 | int hsa = dsi->vm_timings.hsa; |
| 3711 | int hfp = dsi->vm_timings.hfp; |
| 3712 | int hbp = dsi->vm_timings.hbp; |
| 3713 | int vsa = dsi->vm_timings.vsa; |
| 3714 | int vfp = dsi->vm_timings.vfp; |
| 3715 | int vbp = dsi->vm_timings.vbp; |
| 3716 | int window_sync = dsi->vm_timings.window_sync; |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3717 | bool hsync_end; |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 3718 | struct omap_video_timings *timings = &dsi->timings; |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3719 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3720 | int tl, t_he, width_bytes; |
| 3721 | |
Tomi Valkeinen | 478d7df | 2013-03-05 16:29:36 +0200 | [diff] [blame] | 3722 | hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3723 | t_he = hsync_end ? |
| 3724 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; |
| 3725 | |
| 3726 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); |
| 3727 | |
| 3728 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ |
| 3729 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + |
| 3730 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; |
| 3731 | |
| 3732 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, |
| 3733 | hfp, hsync_end ? hsa : 0, tl); |
| 3734 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, |
| 3735 | vsa, timings->y_res); |
| 3736 | |
| 3737 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); |
| 3738 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ |
| 3739 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ |
| 3740 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ |
| 3741 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); |
| 3742 | |
| 3743 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); |
| 3744 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ |
| 3745 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ |
| 3746 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ |
| 3747 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ |
| 3748 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); |
| 3749 | |
| 3750 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); |
| 3751 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ |
| 3752 | r = FLD_MOD(r, tl, 31, 16); /* TL */ |
| 3753 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); |
| 3754 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3755 | } |
| 3756 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 3757 | static int dsi_configure_pins(struct omap_dss_device *dssdev, |
Tomi Valkeinen | e4a9e94 | 2012-03-28 15:58:56 +0300 | [diff] [blame] | 3758 | const struct omap_dsi_pin_config *pin_cfg) |
| 3759 | { |
| 3760 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3761 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3762 | int num_pins; |
| 3763 | const int *pins; |
| 3764 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
| 3765 | int num_lanes; |
| 3766 | int i; |
| 3767 | |
| 3768 | static const enum dsi_lane_function functions[] = { |
| 3769 | DSI_LANE_CLK, |
| 3770 | DSI_LANE_DATA1, |
| 3771 | DSI_LANE_DATA2, |
| 3772 | DSI_LANE_DATA3, |
| 3773 | DSI_LANE_DATA4, |
| 3774 | }; |
| 3775 | |
| 3776 | num_pins = pin_cfg->num_pins; |
| 3777 | pins = pin_cfg->pins; |
| 3778 | |
| 3779 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 |
| 3780 | || num_pins % 2 != 0) |
| 3781 | return -EINVAL; |
| 3782 | |
| 3783 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) |
| 3784 | lanes[i].function = DSI_LANE_UNUSED; |
| 3785 | |
| 3786 | num_lanes = 0; |
| 3787 | |
| 3788 | for (i = 0; i < num_pins; i += 2) { |
| 3789 | u8 lane, pol; |
| 3790 | int dx, dy; |
| 3791 | |
| 3792 | dx = pins[i]; |
| 3793 | dy = pins[i + 1]; |
| 3794 | |
| 3795 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) |
| 3796 | return -EINVAL; |
| 3797 | |
| 3798 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) |
| 3799 | return -EINVAL; |
| 3800 | |
| 3801 | if (dx & 1) { |
| 3802 | if (dy != dx - 1) |
| 3803 | return -EINVAL; |
| 3804 | pol = 1; |
| 3805 | } else { |
| 3806 | if (dy != dx + 1) |
| 3807 | return -EINVAL; |
| 3808 | pol = 0; |
| 3809 | } |
| 3810 | |
| 3811 | lane = dx / 2; |
| 3812 | |
| 3813 | lanes[lane].function = functions[i / 2]; |
| 3814 | lanes[lane].polarity = pol; |
| 3815 | num_lanes++; |
| 3816 | } |
| 3817 | |
| 3818 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); |
| 3819 | dsi->num_lanes_used = num_lanes; |
| 3820 | |
| 3821 | return 0; |
| 3822 | } |
Tomi Valkeinen | e4a9e94 | 2012-03-28 15:58:56 +0300 | [diff] [blame] | 3823 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 3824 | static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3825 | { |
| 3826 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 3827 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3828 | struct omap_overlay_manager *mgr = dsi->output.manager; |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3829 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 3830 | struct omap_dss_device *out = &dsi->output; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3831 | u8 data_type; |
| 3832 | u16 word_count; |
Tomi Valkeinen | 33ca237 | 2011-11-21 13:42:58 +0200 | [diff] [blame] | 3833 | int r; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3834 | |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 3835 | if (out == NULL || out->manager == NULL) { |
| 3836 | DSSERR("failed to enable display: no output/manager\n"); |
| 3837 | return -ENODEV; |
| 3838 | } |
| 3839 | |
| 3840 | r = dsi_display_init_dispc(dsidev, mgr); |
| 3841 | if (r) |
| 3842 | goto err_init_dispc; |
| 3843 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3844 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3845 | switch (dsi->pix_fmt) { |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3846 | case OMAP_DSS_DSI_FMT_RGB888: |
| 3847 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; |
| 3848 | break; |
| 3849 | case OMAP_DSS_DSI_FMT_RGB666: |
| 3850 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; |
| 3851 | break; |
| 3852 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: |
| 3853 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; |
| 3854 | break; |
| 3855 | case OMAP_DSS_DSI_FMT_RGB565: |
| 3856 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; |
| 3857 | break; |
| 3858 | default: |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 3859 | r = -EINVAL; |
| 3860 | goto err_pix_fmt; |
Joe Perches | cf6ac4ce | 2013-10-08 16:23:24 -0700 | [diff] [blame] | 3861 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3862 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3863 | dsi_if_enable(dsidev, false); |
| 3864 | dsi_vc_enable(dsidev, channel, false); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3865 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3866 | /* MODE, 1 = video mode */ |
| 3867 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3868 | |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 3869 | word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3870 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3871 | dsi_vc_write_long_header(dsidev, channel, data_type, |
| 3872 | word_count, 0); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3873 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3874 | dsi_vc_enable(dsidev, channel, true); |
| 3875 | dsi_if_enable(dsidev, true); |
| 3876 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3877 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 3878 | r = dss_mgr_enable(mgr); |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 3879 | if (r) |
| 3880 | goto err_mgr_enable; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3881 | |
| 3882 | return 0; |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 3883 | |
| 3884 | err_mgr_enable: |
| 3885 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3886 | dsi_if_enable(dsidev, false); |
| 3887 | dsi_vc_enable(dsidev, channel, false); |
| 3888 | } |
| 3889 | err_pix_fmt: |
| 3890 | dsi_display_uninit_dispc(dsidev, mgr); |
| 3891 | err_init_dispc: |
| 3892 | return r; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3893 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3894 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 3895 | static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3896 | { |
| 3897 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3898 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3899 | struct omap_overlay_manager *mgr = dsi->output.manager; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3900 | |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 3901 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3902 | dsi_if_enable(dsidev, false); |
| 3903 | dsi_vc_enable(dsidev, channel, false); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3904 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3905 | /* MODE, 0 = command mode */ |
| 3906 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3907 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3908 | dsi_vc_enable(dsidev, channel, true); |
| 3909 | dsi_if_enable(dsidev, true); |
| 3910 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3911 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 3912 | dss_mgr_disable(mgr); |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 3913 | |
| 3914 | dsi_display_uninit_dispc(dsidev, mgr); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3915 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3916 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3917 | static void dsi_update_screen_dispc(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3918 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3919 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 3920 | struct omap_overlay_manager *mgr = dsi->output.manager; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3921 | unsigned bytespp; |
| 3922 | unsigned bytespl; |
| 3923 | unsigned bytespf; |
| 3924 | unsigned total_len; |
| 3925 | unsigned packet_payload; |
| 3926 | unsigned packet_len; |
| 3927 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3928 | int r; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3929 | const unsigned channel = dsi->update_channel; |
Tomi Valkeinen | 9932257 | 2013-03-05 10:37:02 +0200 | [diff] [blame] | 3930 | const unsigned line_buf_size = dsi->line_buffer_size; |
Archit Taneja | 55cd63a | 2012-08-09 15:41:13 +0530 | [diff] [blame] | 3931 | u16 w = dsi->timings.x_res; |
| 3932 | u16 h = dsi->timings.y_res; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3933 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 3934 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3935 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 3936 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3937 | |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 3938 | bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3939 | bytespl = w * bytespp; |
| 3940 | bytespf = bytespl * h; |
| 3941 | |
| 3942 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 3943 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 3944 | |
| 3945 | if (bytespf < line_buf_size) |
| 3946 | packet_payload = bytespf; |
| 3947 | else |
| 3948 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 3949 | |
| 3950 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 3951 | total_len = (bytespf / packet_payload) * packet_len; |
| 3952 | |
| 3953 | if (bytespf % packet_payload) |
| 3954 | total_len += (bytespf % packet_payload) + 1; |
| 3955 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3956 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3957 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3958 | |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3959 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3960 | packet_len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3961 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3962 | if (dsi->te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3963 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 3964 | else |
| 3965 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3966 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3967 | |
| 3968 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 3969 | * because DSS interrupts are not capable of waking up the CPU and the |
| 3970 | * framedone interrupt could be delayed for quite a long time. I think |
| 3971 | * the same goes for any DSS interrupts, but for some reason I have not |
| 3972 | * seen the problem anywhere else than here. |
| 3973 | */ |
| 3974 | dispc_disable_sidle(); |
| 3975 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3976 | dsi_perf_mark_start(dsidev); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3977 | |
Archit Taneja | 49dbf58 | 2011-05-16 15:17:07 +0530 | [diff] [blame] | 3978 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
| 3979 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 3980 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 3981 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 3982 | dss_mgr_set_timings(mgr, &dsi->timings); |
Archit Taneja | 55cd63a | 2012-08-09 15:41:13 +0530 | [diff] [blame] | 3983 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 3984 | dss_mgr_start_update(mgr); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3985 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3986 | if (dsi->te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3987 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 3988 | * for TE is longer than the timer allows */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3989 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3990 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3991 | dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3992 | |
| 3993 | #ifdef DSI_CATCH_MISSING_TE |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3994 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3995 | #endif |
| 3996 | } |
| 3997 | } |
| 3998 | |
| 3999 | #ifdef DSI_CATCH_MISSING_TE |
| 4000 | static void dsi_te_timeout(unsigned long arg) |
| 4001 | { |
| 4002 | DSSERR("TE not received for 250ms!\n"); |
| 4003 | } |
| 4004 | #endif |
| 4005 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4006 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4007 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4008 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4009 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4010 | /* SIDLEMODE back to smart-idle */ |
| 4011 | dispc_enable_sidle(); |
| 4012 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4013 | if (dsi->te_enabled) { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4014 | /* enable LP_RX_TO again after the TE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4015 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4016 | } |
| 4017 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4018 | dsi->framedone_callback(error, dsi->framedone_data); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4019 | |
| 4020 | if (!error) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4021 | dsi_perf_show(dsidev, "DISPC"); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4022 | } |
| 4023 | |
| 4024 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 4025 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4026 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
| 4027 | framedone_timeout_work.work); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4028 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 4029 | * 250ms which would conflict with this timeout work. What should be |
| 4030 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4031 | * possibly scheduled framedone work. However, cancelling the transfer |
| 4032 | * on the HW is buggy, and would probably require resetting the whole |
| 4033 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4034 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4035 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4036 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4037 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4038 | } |
| 4039 | |
Tomi Valkeinen | 1550202 | 2012-10-10 13:59:07 +0300 | [diff] [blame] | 4040 | static void dsi_framedone_irq_callback(void *data) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4041 | { |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 4042 | struct platform_device *dsidev = (struct platform_device *) data; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4043 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4044 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4045 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 4046 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 4047 | * and is sending the data. |
| 4048 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4049 | |
Tejun Heo | 136b572 | 2012-08-21 13:18:24 -0700 | [diff] [blame] | 4050 | cancel_delayed_work(&dsi->framedone_timeout_work); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4051 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4052 | dsi_handle_framedone(dsidev, 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4053 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4054 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4055 | static int dsi_update(struct omap_dss_device *dssdev, int channel, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4056 | void (*callback)(int, void *), void *data) |
| 4057 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4058 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4059 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4060 | u16 dw, dh; |
| 4061 | |
| 4062 | dsi_perf_mark_setup(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4063 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4064 | dsi->update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4065 | |
Tomi Valkeinen | 4a9e78a | 2011-08-15 11:22:21 +0300 | [diff] [blame] | 4066 | dsi->framedone_callback = callback; |
| 4067 | dsi->framedone_data = data; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4068 | |
Archit Taneja | e352574 | 2012-08-09 15:23:43 +0530 | [diff] [blame] | 4069 | dw = dsi->timings.x_res; |
| 4070 | dh = dsi->timings.y_res; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4071 | |
Tomi Valkeinen | 477fed7 | 2013-10-02 14:41:24 +0300 | [diff] [blame] | 4072 | #ifdef DSI_PERF_MEASURE |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4073 | dsi->update_bytes = dw * dh * |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 4074 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4075 | #endif |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4076 | dsi_update_screen_dispc(dsidev); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4077 | |
| 4078 | return 0; |
| 4079 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4080 | |
| 4081 | /* Display funcs */ |
| 4082 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4083 | static int dsi_configure_dispc_clocks(struct platform_device *dsidev) |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4084 | { |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4085 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4086 | struct dispc_clock_info dispc_cinfo; |
| 4087 | int r; |
Tomi Valkeinen | 1751818 | 2013-03-07 11:21:45 +0200 | [diff] [blame] | 4088 | unsigned long fck; |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4089 | |
| 4090 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
| 4091 | |
Tomi Valkeinen | a0d269e | 2012-11-27 17:05:54 +0200 | [diff] [blame] | 4092 | dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; |
| 4093 | dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4094 | |
| 4095 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 4096 | if (r) { |
| 4097 | DSSERR("Failed to calc dispc clocks\n"); |
| 4098 | return r; |
| 4099 | } |
| 4100 | |
| 4101 | dsi->mgr_config.clock_info = dispc_cinfo; |
| 4102 | |
| 4103 | return 0; |
| 4104 | } |
| 4105 | |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 4106 | static int dsi_display_init_dispc(struct platform_device *dsidev, |
| 4107 | struct omap_overlay_manager *mgr) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4108 | { |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4109 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4110 | int r; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4111 | |
Tomi Valkeinen | 4ce9e33 | 2013-03-05 17:11:16 +0200 | [diff] [blame] | 4112 | dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? |
| 4113 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : |
| 4114 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4115 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4116 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { |
Tomi Valkeinen | 1550202 | 2012-10-10 13:59:07 +0300 | [diff] [blame] | 4117 | r = dss_mgr_register_framedone_handler(mgr, |
| 4118 | dsi_framedone_irq_callback, dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4119 | if (r) { |
Tomi Valkeinen | 1550202 | 2012-10-10 13:59:07 +0300 | [diff] [blame] | 4120 | DSSERR("can't register FRAMEDONE handler\n"); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4121 | goto err; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4122 | } |
| 4123 | |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4124 | dsi->mgr_config.stallmode = true; |
| 4125 | dsi->mgr_config.fifohandcheck = true; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4126 | } else { |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4127 | dsi->mgr_config.stallmode = false; |
| 4128 | dsi->mgr_config.fifohandcheck = false; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4129 | } |
| 4130 | |
Archit Taneja | bd5a7b1 | 2012-06-26 12:38:31 +0530 | [diff] [blame] | 4131 | /* |
| 4132 | * override interlace, logic level and edge related parameters in |
| 4133 | * omap_video_timings with default values |
| 4134 | */ |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 4135 | dsi->timings.interlace = false; |
| 4136 | dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; |
| 4137 | dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; |
| 4138 | dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; |
| 4139 | dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; |
Tomi Valkeinen | 7a16360 | 2014-10-02 17:58:48 +0000 | [diff] [blame^] | 4140 | dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; |
Archit Taneja | bd5a7b1 | 2012-06-26 12:38:31 +0530 | [diff] [blame] | 4141 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 4142 | dss_mgr_set_timings(mgr, &dsi->timings); |
Archit Taneja | bd5a7b1 | 2012-06-26 12:38:31 +0530 | [diff] [blame] | 4143 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4144 | r = dsi_configure_dispc_clocks(dsidev); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4145 | if (r) |
| 4146 | goto err1; |
| 4147 | |
| 4148 | dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; |
| 4149 | dsi->mgr_config.video_port_width = |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 4150 | dsi_get_pixel_size(dsi->pix_fmt); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4151 | dsi->mgr_config.lcden_sig_polarity = 0; |
| 4152 | |
Archit Taneja | eea8340 | 2012-09-04 11:42:36 +0530 | [diff] [blame] | 4153 | dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); |
Archit Taneja | d21f43b | 2012-06-21 09:45:11 +0530 | [diff] [blame] | 4154 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4155 | return 0; |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4156 | err1: |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 4157 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
Tomi Valkeinen | 1550202 | 2012-10-10 13:59:07 +0300 | [diff] [blame] | 4158 | dss_mgr_unregister_framedone_handler(mgr, |
| 4159 | dsi_framedone_irq_callback, dsidev); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4160 | err: |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 4161 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); |
Archit Taneja | 7d2572f | 2012-06-29 14:31:07 +0530 | [diff] [blame] | 4162 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4163 | } |
| 4164 | |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 4165 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, |
| 4166 | struct omap_overlay_manager *mgr) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4167 | { |
Archit Taneja | dca2b15 | 2012-08-16 18:02:00 +0530 | [diff] [blame] | 4168 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4169 | |
Tomi Valkeinen | 1550202 | 2012-10-10 13:59:07 +0300 | [diff] [blame] | 4170 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
| 4171 | dss_mgr_unregister_framedone_handler(mgr, |
| 4172 | dsi_framedone_irq_callback, dsidev); |
Tomi Valkeinen | b7dec9b | 2013-02-22 12:58:35 +0200 | [diff] [blame] | 4173 | |
| 4174 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4175 | } |
| 4176 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4177 | static int dsi_configure_dsi_clocks(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4178 | { |
Tomi Valkeinen | a0d269e | 2012-11-27 17:05:54 +0200 | [diff] [blame] | 4179 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4180 | struct dss_pll_clock_info cinfo; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4181 | int r; |
| 4182 | |
Tomi Valkeinen | a0d269e | 2012-11-27 17:05:54 +0200 | [diff] [blame] | 4183 | cinfo = dsi->user_dsi_cinfo; |
| 4184 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4185 | r = dss_pll_set_config(&dsi->pll, &cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4186 | if (r) { |
| 4187 | DSSERR("Failed to set dsi clocks\n"); |
| 4188 | return r; |
| 4189 | } |
| 4190 | |
| 4191 | return 0; |
| 4192 | } |
| 4193 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4194 | static int dsi_display_init_dsi(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4195 | { |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 4196 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4197 | int r; |
| 4198 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4199 | r = dss_pll_enable(&dsi->pll); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4200 | if (r) |
| 4201 | goto err0; |
| 4202 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4203 | r = dsi_configure_dsi_clocks(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4204 | if (r) |
| 4205 | goto err1; |
| 4206 | |
Tomi Valkeinen | 4ce9e33 | 2013-03-05 17:11:16 +0200 | [diff] [blame] | 4207 | dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? |
| 4208 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : |
| 4209 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4210 | |
| 4211 | DSSDBG("PLL OK\n"); |
| 4212 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 4213 | r = dsi_cio_init(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4214 | if (r) |
| 4215 | goto err2; |
| 4216 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4217 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4218 | |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 4219 | dsi_proto_timings(dsidev); |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4220 | dsi_set_lp_clk_divisor(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4221 | |
| 4222 | if (1) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4223 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4224 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4225 | r = dsi_proto_config(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4226 | if (r) |
| 4227 | goto err3; |
| 4228 | |
| 4229 | /* enable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4230 | dsi_vc_enable(dsidev, 0, 1); |
| 4231 | dsi_vc_enable(dsidev, 1, 1); |
| 4232 | dsi_vc_enable(dsidev, 2, 1); |
| 4233 | dsi_vc_enable(dsidev, 3, 1); |
| 4234 | dsi_if_enable(dsidev, 1); |
| 4235 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4236 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4237 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4238 | err3: |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 4239 | dsi_cio_uninit(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4240 | err2: |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 4241 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4242 | err1: |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4243 | dss_pll_disable(&dsi->pll); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4244 | err0: |
| 4245 | return r; |
| 4246 | } |
| 4247 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4248 | static void dsi_display_uninit_dsi(struct platform_device *dsidev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4249 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4250 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4251 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4252 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4253 | if (enter_ulps && !dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4254 | dsi_enter_ulps(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 4255 | |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4256 | /* disable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4257 | dsi_if_enable(dsidev, 0); |
| 4258 | dsi_vc_enable(dsidev, 0, 0); |
| 4259 | dsi_vc_enable(dsidev, 1, 0); |
| 4260 | dsi_vc_enable(dsidev, 2, 0); |
| 4261 | dsi_vc_enable(dsidev, 3, 0); |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4262 | |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 4263 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
Archit Taneja | 9e7e937 | 2012-08-14 12:29:22 +0530 | [diff] [blame] | 4264 | dsi_cio_uninit(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4265 | dsi_pll_uninit(dsidev, disconnect_lanes); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4266 | } |
| 4267 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4268 | static int dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4269 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4270 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4271 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4272 | int r = 0; |
| 4273 | |
| 4274 | DSSDBG("dsi_display_enable\n"); |
| 4275 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4276 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4277 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4278 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4279 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4280 | r = dsi_runtime_get(dsidev); |
| 4281 | if (r) |
| 4282 | goto err_get_dsi; |
| 4283 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4284 | _dsi_initialize_irq(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4285 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4286 | r = dsi_display_init_dsi(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4287 | if (r) |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4288 | goto err_init_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4289 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4290 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4291 | |
| 4292 | return 0; |
| 4293 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4294 | err_init_dsi: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4295 | dsi_runtime_put(dsidev); |
| 4296 | err_get_dsi: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4297 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4298 | DSSDBG("dsi_display_enable FAILED\n"); |
| 4299 | return r; |
| 4300 | } |
| 4301 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4302 | static void dsi_display_disable(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4303 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4304 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4305 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4306 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4307 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4308 | DSSDBG("dsi_display_disable\n"); |
| 4309 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4310 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4311 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4312 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4313 | |
Tomi Valkeinen | 15ffa1d | 2011-06-16 14:34:06 +0300 | [diff] [blame] | 4314 | dsi_sync_vc(dsidev, 0); |
| 4315 | dsi_sync_vc(dsidev, 1); |
| 4316 | dsi_sync_vc(dsidev, 2); |
| 4317 | dsi_sync_vc(dsidev, 3); |
| 4318 | |
Tomi Valkeinen | 5761217 | 2012-11-27 17:32:36 +0200 | [diff] [blame] | 4319 | dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4320 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4321 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4322 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4323 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4324 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4325 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4326 | static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4327 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4328 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4329 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4330 | |
| 4331 | dsi->te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4332 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4333 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4334 | |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4335 | #ifdef PRINT_VERBOSE_VM_TIMINGS |
| 4336 | static void print_dsi_vm(const char *str, |
| 4337 | const struct omap_dss_dsi_videomode_timings *t) |
| 4338 | { |
| 4339 | unsigned long byteclk = t->hsclk / 4; |
| 4340 | int bl, wc, pps, tot; |
| 4341 | |
| 4342 | wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); |
| 4343 | pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ |
| 4344 | bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; |
| 4345 | tot = bl + pps; |
| 4346 | |
| 4347 | #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) |
| 4348 | |
| 4349 | pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " |
| 4350 | "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", |
| 4351 | str, |
| 4352 | byteclk, |
| 4353 | t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, |
| 4354 | bl, pps, tot, |
| 4355 | TO_DSI_T(t->hss), |
| 4356 | TO_DSI_T(t->hsa), |
| 4357 | TO_DSI_T(t->hse), |
| 4358 | TO_DSI_T(t->hbp), |
| 4359 | TO_DSI_T(pps), |
| 4360 | TO_DSI_T(t->hfp), |
| 4361 | |
| 4362 | TO_DSI_T(bl), |
| 4363 | TO_DSI_T(pps), |
| 4364 | |
| 4365 | TO_DSI_T(tot)); |
| 4366 | #undef TO_DSI_T |
| 4367 | } |
| 4368 | |
| 4369 | static void print_dispc_vm(const char *str, const struct omap_video_timings *t) |
| 4370 | { |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4371 | unsigned long pck = t->pixelclock; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4372 | int hact, bl, tot; |
| 4373 | |
| 4374 | hact = t->x_res; |
| 4375 | bl = t->hsw + t->hbp + t->hfp; |
| 4376 | tot = hact + bl; |
| 4377 | |
| 4378 | #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) |
| 4379 | |
| 4380 | pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " |
| 4381 | "%u/%u/%u/%u = %u + %u = %u\n", |
| 4382 | str, |
| 4383 | pck, |
| 4384 | t->hsw, t->hbp, hact, t->hfp, |
| 4385 | bl, hact, tot, |
| 4386 | TO_DISPC_T(t->hsw), |
| 4387 | TO_DISPC_T(t->hbp), |
| 4388 | TO_DISPC_T(hact), |
| 4389 | TO_DISPC_T(t->hfp), |
| 4390 | TO_DISPC_T(bl), |
| 4391 | TO_DISPC_T(hact), |
| 4392 | TO_DISPC_T(tot)); |
| 4393 | #undef TO_DISPC_T |
| 4394 | } |
| 4395 | |
| 4396 | /* note: this is not quite accurate */ |
| 4397 | static void print_dsi_dispc_vm(const char *str, |
| 4398 | const struct omap_dss_dsi_videomode_timings *t) |
| 4399 | { |
| 4400 | struct omap_video_timings vm = { 0 }; |
| 4401 | unsigned long byteclk = t->hsclk / 4; |
| 4402 | unsigned long pck; |
| 4403 | u64 dsi_tput; |
| 4404 | int dsi_hact, dsi_htot; |
| 4405 | |
| 4406 | dsi_tput = (u64)byteclk * t->ndl * 8; |
| 4407 | pck = (u32)div64_u64(dsi_tput, t->bitspp); |
| 4408 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); |
| 4409 | dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; |
| 4410 | |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4411 | vm.pixelclock = pck; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4412 | vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); |
| 4413 | vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); |
| 4414 | vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); |
| 4415 | vm.x_res = t->hact; |
| 4416 | |
| 4417 | print_dispc_vm(str, &vm); |
| 4418 | } |
| 4419 | #endif /* PRINT_VERBOSE_VM_TIMINGS */ |
| 4420 | |
| 4421 | static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, |
| 4422 | unsigned long pck, void *data) |
| 4423 | { |
| 4424 | struct dsi_clk_calc_ctx *ctx = data; |
| 4425 | struct omap_video_timings *t = &ctx->dispc_vm; |
| 4426 | |
| 4427 | ctx->dispc_cinfo.lck_div = lckd; |
| 4428 | ctx->dispc_cinfo.pck_div = pckd; |
| 4429 | ctx->dispc_cinfo.lck = lck; |
| 4430 | ctx->dispc_cinfo.pck = pck; |
| 4431 | |
| 4432 | *t = *ctx->config->timings; |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4433 | t->pixelclock = pck; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4434 | t->x_res = ctx->config->timings->x_res; |
| 4435 | t->y_res = ctx->config->timings->y_res; |
| 4436 | t->hsw = t->hfp = t->hbp = t->vsw = 1; |
| 4437 | t->vfp = t->vbp = 0; |
| 4438 | |
| 4439 | return true; |
| 4440 | } |
| 4441 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4442 | static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4443 | void *data) |
| 4444 | { |
| 4445 | struct dsi_clk_calc_ctx *ctx = data; |
| 4446 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4447 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 4448 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4449 | |
| 4450 | return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, |
| 4451 | dsi_cm_calc_dispc_cb, ctx); |
| 4452 | } |
| 4453 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4454 | static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, |
| 4455 | unsigned long clkdco, void *data) |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4456 | { |
| 4457 | struct dsi_clk_calc_ctx *ctx = data; |
| 4458 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4459 | ctx->dsi_cinfo.n = n; |
| 4460 | ctx->dsi_cinfo.m = m; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4461 | ctx->dsi_cinfo.fint = fint; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4462 | ctx->dsi_cinfo.clkdco = clkdco; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4463 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4464 | return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, |
| 4465 | dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4466 | dsi_cm_calc_hsdiv_cb, ctx); |
| 4467 | } |
| 4468 | |
| 4469 | static bool dsi_cm_calc(struct dsi_data *dsi, |
| 4470 | const struct omap_dss_dsi_config *cfg, |
| 4471 | struct dsi_clk_calc_ctx *ctx) |
| 4472 | { |
| 4473 | unsigned long clkin; |
| 4474 | int bitspp, ndl; |
| 4475 | unsigned long pll_min, pll_max; |
| 4476 | unsigned long pck, txbyteclk; |
| 4477 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4478 | clkin = clk_get_rate(dsi->pll.clkin); |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4479 | bitspp = dsi_get_pixel_size(cfg->pixel_format); |
| 4480 | ndl = dsi->num_lanes_used - 1; |
| 4481 | |
| 4482 | /* |
| 4483 | * Here we should calculate minimum txbyteclk to be able to send the |
| 4484 | * frame in time, and also to handle TE. That's not very simple, though, |
| 4485 | * especially as we go to LP between each pixel packet due to HW |
| 4486 | * "feature". So let's just estimate very roughly and multiply by 1.5. |
| 4487 | */ |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4488 | pck = cfg->timings->pixelclock; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4489 | pck = pck * 3 / 2; |
| 4490 | txbyteclk = pck * bitspp / 8 / ndl; |
| 4491 | |
| 4492 | memset(ctx, 0, sizeof(*ctx)); |
| 4493 | ctx->dsidev = dsi->pdev; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4494 | ctx->pll = &dsi->pll; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4495 | ctx->config = cfg; |
| 4496 | ctx->req_pck_min = pck; |
| 4497 | ctx->req_pck_nom = pck; |
| 4498 | ctx->req_pck_max = pck * 3 / 2; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4499 | |
| 4500 | pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); |
| 4501 | pll_max = cfg->hs_clk_max * 4; |
| 4502 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4503 | return dss_pll_calc(ctx->pll, clkin, |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4504 | pll_min, pll_max, |
| 4505 | dsi_cm_calc_pll_cb, ctx); |
| 4506 | } |
| 4507 | |
| 4508 | static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) |
| 4509 | { |
| 4510 | struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); |
| 4511 | const struct omap_dss_dsi_config *cfg = ctx->config; |
| 4512 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); |
| 4513 | int ndl = dsi->num_lanes_used - 1; |
Tomi Valkeinen | 4a38aed | 2014-11-07 13:08:16 +0200 | [diff] [blame] | 4514 | unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4515 | unsigned long byteclk = hsclk / 4; |
| 4516 | |
| 4517 | unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; |
| 4518 | int xres; |
| 4519 | int panel_htot, panel_hbl; /* pixels */ |
| 4520 | int dispc_htot, dispc_hbl; /* pixels */ |
| 4521 | int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ |
| 4522 | int hfp, hsa, hbp; |
| 4523 | const struct omap_video_timings *req_vm; |
| 4524 | struct omap_video_timings *dispc_vm; |
| 4525 | struct omap_dss_dsi_videomode_timings *dsi_vm; |
| 4526 | u64 dsi_tput, dispc_tput; |
| 4527 | |
| 4528 | dsi_tput = (u64)byteclk * ndl * 8; |
| 4529 | |
| 4530 | req_vm = cfg->timings; |
| 4531 | req_pck_min = ctx->req_pck_min; |
| 4532 | req_pck_max = ctx->req_pck_max; |
| 4533 | req_pck_nom = ctx->req_pck_nom; |
| 4534 | |
| 4535 | dispc_pck = ctx->dispc_cinfo.pck; |
| 4536 | dispc_tput = (u64)dispc_pck * bitspp; |
| 4537 | |
| 4538 | xres = req_vm->x_res; |
| 4539 | |
| 4540 | panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; |
| 4541 | panel_htot = xres + panel_hbl; |
| 4542 | |
| 4543 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); |
| 4544 | |
| 4545 | /* |
| 4546 | * When there are no line buffers, DISPC and DSI must have the |
| 4547 | * same tput. Otherwise DISPC tput needs to be higher than DSI's. |
| 4548 | */ |
| 4549 | if (dsi->line_buffer_size < xres * bitspp / 8) { |
| 4550 | if (dispc_tput != dsi_tput) |
| 4551 | return false; |
| 4552 | } else { |
| 4553 | if (dispc_tput < dsi_tput) |
| 4554 | return false; |
| 4555 | } |
| 4556 | |
| 4557 | /* DSI tput must be over the min requirement */ |
| 4558 | if (dsi_tput < (u64)bitspp * req_pck_min) |
| 4559 | return false; |
| 4560 | |
| 4561 | /* When non-burst mode, DSI tput must be below max requirement. */ |
| 4562 | if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { |
| 4563 | if (dsi_tput > (u64)bitspp * req_pck_max) |
| 4564 | return false; |
| 4565 | } |
| 4566 | |
| 4567 | hss = DIV_ROUND_UP(4, ndl); |
| 4568 | |
| 4569 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { |
| 4570 | if (ndl == 3 && req_vm->hsw == 0) |
| 4571 | hse = 1; |
| 4572 | else |
| 4573 | hse = DIV_ROUND_UP(4, ndl); |
| 4574 | } else { |
| 4575 | hse = 0; |
| 4576 | } |
| 4577 | |
| 4578 | /* DSI htot to match the panel's nominal pck */ |
| 4579 | dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); |
| 4580 | |
| 4581 | /* fail if there would be no time for blanking */ |
| 4582 | if (dsi_htot < hss + hse + dsi_hact) |
| 4583 | return false; |
| 4584 | |
| 4585 | /* total DSI blanking needed to achieve panel's TL */ |
| 4586 | dsi_hbl = dsi_htot - dsi_hact; |
| 4587 | |
| 4588 | /* DISPC htot to match the DSI TL */ |
| 4589 | dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); |
| 4590 | |
| 4591 | /* verify that the DSI and DISPC TLs are the same */ |
| 4592 | if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) |
| 4593 | return false; |
| 4594 | |
| 4595 | dispc_hbl = dispc_htot - xres; |
| 4596 | |
| 4597 | /* setup DSI videomode */ |
| 4598 | |
| 4599 | dsi_vm = &ctx->dsi_vm; |
| 4600 | memset(dsi_vm, 0, sizeof(*dsi_vm)); |
| 4601 | |
| 4602 | dsi_vm->hsclk = hsclk; |
| 4603 | |
| 4604 | dsi_vm->ndl = ndl; |
| 4605 | dsi_vm->bitspp = bitspp; |
| 4606 | |
| 4607 | if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { |
| 4608 | hsa = 0; |
| 4609 | } else if (ndl == 3 && req_vm->hsw == 0) { |
| 4610 | hsa = 0; |
| 4611 | } else { |
| 4612 | hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); |
| 4613 | hsa = max(hsa - hse, 1); |
| 4614 | } |
| 4615 | |
| 4616 | hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); |
| 4617 | hbp = max(hbp, 1); |
| 4618 | |
| 4619 | hfp = dsi_hbl - (hss + hsa + hse + hbp); |
| 4620 | if (hfp < 1) { |
| 4621 | int t; |
| 4622 | /* we need to take cycles from hbp */ |
| 4623 | |
| 4624 | t = 1 - hfp; |
| 4625 | hbp = max(hbp - t, 1); |
| 4626 | hfp = dsi_hbl - (hss + hsa + hse + hbp); |
| 4627 | |
| 4628 | if (hfp < 1 && hsa > 0) { |
| 4629 | /* we need to take cycles from hsa */ |
| 4630 | t = 1 - hfp; |
| 4631 | hsa = max(hsa - t, 1); |
| 4632 | hfp = dsi_hbl - (hss + hsa + hse + hbp); |
| 4633 | } |
| 4634 | } |
| 4635 | |
| 4636 | if (hfp < 1) |
| 4637 | return false; |
| 4638 | |
| 4639 | dsi_vm->hss = hss; |
| 4640 | dsi_vm->hsa = hsa; |
| 4641 | dsi_vm->hse = hse; |
| 4642 | dsi_vm->hbp = hbp; |
| 4643 | dsi_vm->hact = xres; |
| 4644 | dsi_vm->hfp = hfp; |
| 4645 | |
| 4646 | dsi_vm->vsa = req_vm->vsw; |
| 4647 | dsi_vm->vbp = req_vm->vbp; |
| 4648 | dsi_vm->vact = req_vm->y_res; |
| 4649 | dsi_vm->vfp = req_vm->vfp; |
| 4650 | |
| 4651 | dsi_vm->trans_mode = cfg->trans_mode; |
| 4652 | |
| 4653 | dsi_vm->blanking_mode = 0; |
| 4654 | dsi_vm->hsa_blanking_mode = 1; |
| 4655 | dsi_vm->hfp_blanking_mode = 1; |
| 4656 | dsi_vm->hbp_blanking_mode = 1; |
| 4657 | |
| 4658 | dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; |
| 4659 | dsi_vm->window_sync = 4; |
| 4660 | |
| 4661 | /* setup DISPC videomode */ |
| 4662 | |
| 4663 | dispc_vm = &ctx->dispc_vm; |
| 4664 | *dispc_vm = *req_vm; |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4665 | dispc_vm->pixelclock = dispc_pck; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4666 | |
| 4667 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { |
| 4668 | hsa = div64_u64((u64)req_vm->hsw * dispc_pck, |
| 4669 | req_pck_nom); |
| 4670 | hsa = max(hsa, 1); |
| 4671 | } else { |
| 4672 | hsa = 1; |
| 4673 | } |
| 4674 | |
| 4675 | hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); |
| 4676 | hbp = max(hbp, 1); |
| 4677 | |
| 4678 | hfp = dispc_hbl - hsa - hbp; |
| 4679 | if (hfp < 1) { |
| 4680 | int t; |
| 4681 | /* we need to take cycles from hbp */ |
| 4682 | |
| 4683 | t = 1 - hfp; |
| 4684 | hbp = max(hbp - t, 1); |
| 4685 | hfp = dispc_hbl - hsa - hbp; |
| 4686 | |
| 4687 | if (hfp < 1) { |
| 4688 | /* we need to take cycles from hsa */ |
| 4689 | t = 1 - hfp; |
| 4690 | hsa = max(hsa - t, 1); |
| 4691 | hfp = dispc_hbl - hsa - hbp; |
| 4692 | } |
| 4693 | } |
| 4694 | |
| 4695 | if (hfp < 1) |
| 4696 | return false; |
| 4697 | |
| 4698 | dispc_vm->hfp = hfp; |
| 4699 | dispc_vm->hsw = hsa; |
| 4700 | dispc_vm->hbp = hbp; |
| 4701 | |
| 4702 | return true; |
| 4703 | } |
| 4704 | |
| 4705 | |
| 4706 | static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, |
| 4707 | unsigned long pck, void *data) |
| 4708 | { |
| 4709 | struct dsi_clk_calc_ctx *ctx = data; |
| 4710 | |
| 4711 | ctx->dispc_cinfo.lck_div = lckd; |
| 4712 | ctx->dispc_cinfo.pck_div = pckd; |
| 4713 | ctx->dispc_cinfo.lck = lck; |
| 4714 | ctx->dispc_cinfo.pck = pck; |
| 4715 | |
| 4716 | if (dsi_vm_calc_blanking(ctx) == false) |
| 4717 | return false; |
| 4718 | |
| 4719 | #ifdef PRINT_VERBOSE_VM_TIMINGS |
| 4720 | print_dispc_vm("dispc", &ctx->dispc_vm); |
| 4721 | print_dsi_vm("dsi ", &ctx->dsi_vm); |
| 4722 | print_dispc_vm("req ", ctx->config->timings); |
| 4723 | print_dsi_dispc_vm("act ", &ctx->dsi_vm); |
| 4724 | #endif |
| 4725 | |
| 4726 | return true; |
| 4727 | } |
| 4728 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4729 | static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4730 | void *data) |
| 4731 | { |
| 4732 | struct dsi_clk_calc_ctx *ctx = data; |
| 4733 | unsigned long pck_max; |
| 4734 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4735 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 4736 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4737 | |
| 4738 | /* |
| 4739 | * In burst mode we can let the dispc pck be arbitrarily high, but it |
| 4740 | * limits our scaling abilities. So for now, don't aim too high. |
| 4741 | */ |
| 4742 | |
| 4743 | if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) |
| 4744 | pck_max = ctx->req_pck_max + 10000000; |
| 4745 | else |
| 4746 | pck_max = ctx->req_pck_max; |
| 4747 | |
| 4748 | return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, |
| 4749 | dsi_vm_calc_dispc_cb, ctx); |
| 4750 | } |
| 4751 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4752 | static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, |
| 4753 | unsigned long clkdco, void *data) |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4754 | { |
| 4755 | struct dsi_clk_calc_ctx *ctx = data; |
| 4756 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4757 | ctx->dsi_cinfo.n = n; |
| 4758 | ctx->dsi_cinfo.m = m; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4759 | ctx->dsi_cinfo.fint = fint; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4760 | ctx->dsi_cinfo.clkdco = clkdco; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4761 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4762 | return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, |
| 4763 | dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4764 | dsi_vm_calc_hsdiv_cb, ctx); |
| 4765 | } |
| 4766 | |
| 4767 | static bool dsi_vm_calc(struct dsi_data *dsi, |
| 4768 | const struct omap_dss_dsi_config *cfg, |
| 4769 | struct dsi_clk_calc_ctx *ctx) |
| 4770 | { |
| 4771 | const struct omap_video_timings *t = cfg->timings; |
| 4772 | unsigned long clkin; |
| 4773 | unsigned long pll_min; |
| 4774 | unsigned long pll_max; |
| 4775 | int ndl = dsi->num_lanes_used - 1; |
| 4776 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); |
| 4777 | unsigned long byteclk_min; |
| 4778 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4779 | clkin = clk_get_rate(dsi->pll.clkin); |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4780 | |
| 4781 | memset(ctx, 0, sizeof(*ctx)); |
| 4782 | ctx->dsidev = dsi->pdev; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4783 | ctx->pll = &dsi->pll; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4784 | ctx->config = cfg; |
| 4785 | |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4786 | /* these limits should come from the panel driver */ |
Tomi Valkeinen | d8d78941 | 2013-04-10 14:12:14 +0300 | [diff] [blame] | 4787 | ctx->req_pck_min = t->pixelclock - 1000; |
| 4788 | ctx->req_pck_nom = t->pixelclock; |
| 4789 | ctx->req_pck_max = t->pixelclock + 1000; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4790 | |
| 4791 | byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); |
| 4792 | pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); |
| 4793 | |
| 4794 | if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { |
| 4795 | pll_max = cfg->hs_clk_max * 4; |
| 4796 | } else { |
| 4797 | unsigned long byteclk_max; |
| 4798 | byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, |
| 4799 | ndl * 8); |
| 4800 | |
| 4801 | pll_max = byteclk_max * 4 * 4; |
| 4802 | } |
| 4803 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 4804 | return dss_pll_calc(ctx->pll, clkin, |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4805 | pll_min, pll_max, |
| 4806 | dsi_vm_calc_pll_cb, ctx); |
| 4807 | } |
| 4808 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4809 | static int dsi_set_config(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 777f05c | 2013-03-06 11:10:29 +0200 | [diff] [blame] | 4810 | const struct omap_dss_dsi_config *config) |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 4811 | { |
| 4812 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4813 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4814 | struct dsi_clk_calc_ctx ctx; |
| 4815 | bool ok; |
| 4816 | int r; |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 4817 | |
| 4818 | mutex_lock(&dsi->lock); |
| 4819 | |
Tomi Valkeinen | 777f05c | 2013-03-06 11:10:29 +0200 | [diff] [blame] | 4820 | dsi->pix_fmt = config->pixel_format; |
| 4821 | dsi->mode = config->mode; |
| 4822 | |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4823 | if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) |
| 4824 | ok = dsi_vm_calc(dsi, config, &ctx); |
| 4825 | else |
| 4826 | ok = dsi_cm_calc(dsi, config, &ctx); |
| 4827 | |
| 4828 | if (!ok) { |
| 4829 | DSSERR("failed to find suitable DSI clock settings\n"); |
| 4830 | r = -EINVAL; |
| 4831 | goto err; |
| 4832 | } |
| 4833 | |
| 4834 | dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); |
| 4835 | |
Tomi Valkeinen | acf604b | 2014-11-07 13:13:24 +0200 | [diff] [blame] | 4836 | r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], |
Tomi Valkeinen | 7b71c41 | 2014-08-06 15:45:26 +0300 | [diff] [blame] | 4837 | config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4838 | if (r) { |
| 4839 | DSSERR("failed to find suitable DSI LP clock settings\n"); |
| 4840 | goto err; |
| 4841 | } |
| 4842 | |
| 4843 | dsi->user_dsi_cinfo = ctx.dsi_cinfo; |
| 4844 | dsi->user_dispc_cinfo = ctx.dispc_cinfo; |
| 4845 | |
| 4846 | dsi->timings = ctx.dispc_vm; |
| 4847 | dsi->vm_timings = ctx.dsi_vm; |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 4848 | |
| 4849 | mutex_unlock(&dsi->lock); |
Archit Taneja | e67458a | 2012-08-13 14:17:30 +0530 | [diff] [blame] | 4850 | |
Tomi Valkeinen | 777f05c | 2013-03-06 11:10:29 +0200 | [diff] [blame] | 4851 | return 0; |
Tomi Valkeinen | f1e0001 | 2013-03-05 17:21:35 +0200 | [diff] [blame] | 4852 | err: |
| 4853 | mutex_unlock(&dsi->lock); |
| 4854 | |
| 4855 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4856 | } |
Archit Taneja | 0b3ffe3 | 2012-08-13 22:13:39 +0530 | [diff] [blame] | 4857 | |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4858 | /* |
| 4859 | * Return a hardcoded channel for the DSI output. This should work for |
| 4860 | * current use cases, but this can be later expanded to either resolve |
| 4861 | * the channel in some more dynamic manner, or get the channel as a user |
| 4862 | * parameter. |
| 4863 | */ |
| 4864 | static enum omap_channel dsi_get_channel(int module_id) |
Archit Taneja | e352574 | 2012-08-09 15:23:43 +0530 | [diff] [blame] | 4865 | { |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4866 | switch (omapdss_get_version()) { |
| 4867 | case OMAPDSS_VER_OMAP24xx: |
Sathya Prakash M R | d6279d4 | 2014-03-24 16:31:51 +0530 | [diff] [blame] | 4868 | case OMAPDSS_VER_AM43xx: |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4869 | DSSWARN("DSI not supported\n"); |
| 4870 | return OMAP_DSS_CHANNEL_LCD; |
Archit Taneja | e352574 | 2012-08-09 15:23:43 +0530 | [diff] [blame] | 4871 | |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4872 | case OMAPDSS_VER_OMAP34xx_ES1: |
| 4873 | case OMAPDSS_VER_OMAP34xx_ES3: |
| 4874 | case OMAPDSS_VER_OMAP3630: |
| 4875 | case OMAPDSS_VER_AM35xx: |
| 4876 | return OMAP_DSS_CHANNEL_LCD; |
Archit Taneja | e352574 | 2012-08-09 15:23:43 +0530 | [diff] [blame] | 4877 | |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4878 | case OMAPDSS_VER_OMAP4430_ES1: |
| 4879 | case OMAPDSS_VER_OMAP4430_ES2: |
| 4880 | case OMAPDSS_VER_OMAP4: |
| 4881 | switch (module_id) { |
| 4882 | case 0: |
| 4883 | return OMAP_DSS_CHANNEL_LCD; |
| 4884 | case 1: |
| 4885 | return OMAP_DSS_CHANNEL_LCD2; |
| 4886 | default: |
| 4887 | DSSWARN("unsupported module id\n"); |
| 4888 | return OMAP_DSS_CHANNEL_LCD; |
| 4889 | } |
Archit Taneja | e352574 | 2012-08-09 15:23:43 +0530 | [diff] [blame] | 4890 | |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 4891 | case OMAPDSS_VER_OMAP5: |
| 4892 | switch (module_id) { |
| 4893 | case 0: |
| 4894 | return OMAP_DSS_CHANNEL_LCD; |
| 4895 | case 1: |
| 4896 | return OMAP_DSS_CHANNEL_LCD3; |
| 4897 | default: |
| 4898 | DSSWARN("unsupported module id\n"); |
| 4899 | return OMAP_DSS_CHANNEL_LCD; |
| 4900 | } |
| 4901 | |
| 4902 | default: |
| 4903 | DSSWARN("unsupported DSS version\n"); |
| 4904 | return OMAP_DSS_CHANNEL_LCD; |
| 4905 | } |
Archit Taneja | 02c3960 | 2012-08-10 15:01:33 +0530 | [diff] [blame] | 4906 | } |
Tomi Valkeinen | 5f42f2c | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4907 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4908 | static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4909 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4910 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4911 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4912 | int i; |
| 4913 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4914 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
| 4915 | if (!dsi->vc[i].dssdev) { |
| 4916 | dsi->vc[i].dssdev = dssdev; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4917 | *channel = i; |
| 4918 | return 0; |
| 4919 | } |
| 4920 | } |
| 4921 | |
| 4922 | DSSERR("cannot get VC for display %s", dssdev->name); |
| 4923 | return -ENOSPC; |
| 4924 | } |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4925 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4926 | static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4927 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4928 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4929 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4930 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4931 | if (vc_id < 0 || vc_id > 3) { |
| 4932 | DSSERR("VC ID out of range\n"); |
| 4933 | return -EINVAL; |
| 4934 | } |
| 4935 | |
| 4936 | if (channel < 0 || channel > 3) { |
| 4937 | DSSERR("Virtual Channel out of range\n"); |
| 4938 | return -EINVAL; |
| 4939 | } |
| 4940 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4941 | if (dsi->vc[channel].dssdev != dssdev) { |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4942 | DSSERR("Virtual Channel not allocated to display %s\n", |
| 4943 | dssdev->name); |
| 4944 | return -EINVAL; |
| 4945 | } |
| 4946 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4947 | dsi->vc[channel].vc_id = vc_id; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4948 | |
| 4949 | return 0; |
| 4950 | } |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4951 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 4952 | static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4953 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4954 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4955 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4956 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4957 | if ((channel >= 0 && channel <= 3) && |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4958 | dsi->vc[channel].dssdev == dssdev) { |
| 4959 | dsi->vc[channel].dssdev = NULL; |
| 4960 | dsi->vc[channel].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4961 | } |
| 4962 | } |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4963 | |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4964 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4965 | static int dsi_get_clocks(struct platform_device *dsidev) |
| 4966 | { |
| 4967 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4968 | struct clk *clk; |
| 4969 | |
Sachin Kamat | 5303b3a | 2013-04-02 14:33:00 +0300 | [diff] [blame] | 4970 | clk = devm_clk_get(&dsidev->dev, "fck"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4971 | if (IS_ERR(clk)) { |
| 4972 | DSSERR("can't get fck\n"); |
| 4973 | return PTR_ERR(clk); |
| 4974 | } |
| 4975 | |
| 4976 | dsi->dss_clk = clk; |
| 4977 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4978 | return 0; |
| 4979 | } |
| 4980 | |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 4981 | static int dsi_connect(struct omap_dss_device *dssdev, |
| 4982 | struct omap_dss_device *dst) |
| 4983 | { |
| 4984 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4985 | struct omap_overlay_manager *mgr; |
| 4986 | int r; |
| 4987 | |
| 4988 | r = dsi_regulator_init(dsidev); |
| 4989 | if (r) |
| 4990 | return r; |
| 4991 | |
| 4992 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); |
| 4993 | if (!mgr) |
| 4994 | return -ENODEV; |
| 4995 | |
| 4996 | r = dss_mgr_connect(mgr, dssdev); |
| 4997 | if (r) |
| 4998 | return r; |
| 4999 | |
| 5000 | r = omapdss_output_set_device(dssdev, dst); |
| 5001 | if (r) { |
| 5002 | DSSERR("failed to connect output to new device: %s\n", |
| 5003 | dssdev->name); |
| 5004 | dss_mgr_disconnect(mgr, dssdev); |
| 5005 | return r; |
| 5006 | } |
| 5007 | |
| 5008 | return 0; |
| 5009 | } |
| 5010 | |
| 5011 | static void dsi_disconnect(struct omap_dss_device *dssdev, |
| 5012 | struct omap_dss_device *dst) |
| 5013 | { |
Tomi Valkeinen | 9560dc10 | 2013-07-24 13:06:54 +0300 | [diff] [blame] | 5014 | WARN_ON(dst != dssdev->dst); |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5015 | |
Tomi Valkeinen | 9560dc10 | 2013-07-24 13:06:54 +0300 | [diff] [blame] | 5016 | if (dst != dssdev->dst) |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5017 | return; |
| 5018 | |
| 5019 | omapdss_output_unset_device(dssdev); |
| 5020 | |
| 5021 | if (dssdev->manager) |
| 5022 | dss_mgr_disconnect(dssdev->manager, dssdev); |
| 5023 | } |
| 5024 | |
| 5025 | static const struct omapdss_dsi_ops dsi_ops = { |
| 5026 | .connect = dsi_connect, |
| 5027 | .disconnect = dsi_disconnect, |
| 5028 | |
| 5029 | .bus_lock = dsi_bus_lock, |
| 5030 | .bus_unlock = dsi_bus_unlock, |
| 5031 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5032 | .enable = dsi_display_enable, |
| 5033 | .disable = dsi_display_disable, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5034 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5035 | .enable_hs = dsi_vc_enable_hs, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5036 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5037 | .configure_pins = dsi_configure_pins, |
| 5038 | .set_config = dsi_set_config, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5039 | |
| 5040 | .enable_video_output = dsi_enable_video_output, |
| 5041 | .disable_video_output = dsi_disable_video_output, |
| 5042 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5043 | .update = dsi_update, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5044 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5045 | .enable_te = dsi_enable_te, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5046 | |
Tomi Valkeinen | 5cfc1c3 | 2013-05-15 11:24:30 +0300 | [diff] [blame] | 5047 | .request_vc = dsi_request_vc, |
| 5048 | .set_vc_id = dsi_set_vc_id, |
| 5049 | .release_vc = dsi_release_vc, |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5050 | |
| 5051 | .dcs_write = dsi_vc_dcs_write, |
| 5052 | .dcs_write_nosync = dsi_vc_dcs_write_nosync, |
| 5053 | .dcs_read = dsi_vc_dcs_read, |
| 5054 | |
| 5055 | .gen_write = dsi_vc_generic_write, |
| 5056 | .gen_write_nosync = dsi_vc_generic_write_nosync, |
| 5057 | .gen_read = dsi_vc_generic_read, |
| 5058 | |
| 5059 | .bta_sync = dsi_vc_send_bta_sync, |
| 5060 | |
| 5061 | .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, |
| 5062 | }; |
| 5063 | |
Tomi Valkeinen | ee4a24e | 2013-04-26 13:47:06 +0300 | [diff] [blame] | 5064 | static void dsi_init_output(struct platform_device *dsidev) |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5065 | { |
| 5066 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 5067 | struct omap_dss_device *out = &dsi->output; |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5068 | |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 5069 | out->dev = &dsidev->dev; |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5070 | out->id = dsi->module_id == 0 ? |
| 5071 | OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; |
| 5072 | |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 5073 | out->output_type = OMAP_DISPLAY_TYPE_DSI; |
Tomi Valkeinen | 7286a08 | 2013-02-18 13:06:01 +0200 | [diff] [blame] | 5074 | out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; |
Tomi Valkeinen | 2eea5ae | 2013-02-13 11:23:54 +0200 | [diff] [blame] | 5075 | out->dispc_channel = dsi_get_channel(dsi->module_id); |
Tomi Valkeinen | deb16df | 2013-05-24 13:20:27 +0300 | [diff] [blame] | 5076 | out->ops.dsi = &dsi_ops; |
Tomi Valkeinen | b7328e1 | 2013-05-03 11:42:18 +0300 | [diff] [blame] | 5077 | out->owner = THIS_MODULE; |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5078 | |
Tomi Valkeinen | 5d47dbc | 2013-04-24 13:32:51 +0300 | [diff] [blame] | 5079 | omapdss_register_output(out); |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5080 | } |
| 5081 | |
Tomi Valkeinen | d1890a6 | 2013-04-26 13:47:41 +0300 | [diff] [blame] | 5082 | static void dsi_uninit_output(struct platform_device *dsidev) |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5083 | { |
| 5084 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 1f68d9c | 2013-04-19 15:09:34 +0300 | [diff] [blame] | 5085 | struct omap_dss_device *out = &dsi->output; |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5086 | |
Tomi Valkeinen | 5d47dbc | 2013-04-24 13:32:51 +0300 | [diff] [blame] | 5087 | omapdss_unregister_output(out); |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5088 | } |
| 5089 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5090 | static int dsi_probe_of(struct platform_device *pdev) |
| 5091 | { |
| 5092 | struct device_node *node = pdev->dev.of_node; |
| 5093 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); |
| 5094 | struct property *prop; |
| 5095 | u32 lane_arr[10]; |
| 5096 | int len, num_pins; |
| 5097 | int r, i; |
| 5098 | struct device_node *ep; |
| 5099 | struct omap_dsi_pin_config pin_cfg; |
| 5100 | |
| 5101 | ep = omapdss_of_get_first_endpoint(node); |
| 5102 | if (!ep) |
| 5103 | return 0; |
| 5104 | |
| 5105 | prop = of_find_property(ep, "lanes", &len); |
| 5106 | if (prop == NULL) { |
| 5107 | dev_err(&pdev->dev, "failed to find lane data\n"); |
| 5108 | r = -EINVAL; |
| 5109 | goto err; |
| 5110 | } |
| 5111 | |
| 5112 | num_pins = len / sizeof(u32); |
| 5113 | |
| 5114 | if (num_pins < 4 || num_pins % 2 != 0 || |
| 5115 | num_pins > dsi->num_lanes_supported * 2) { |
| 5116 | dev_err(&pdev->dev, "bad number of lanes\n"); |
| 5117 | r = -EINVAL; |
| 5118 | goto err; |
| 5119 | } |
| 5120 | |
| 5121 | r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); |
| 5122 | if (r) { |
| 5123 | dev_err(&pdev->dev, "failed to read lane data\n"); |
| 5124 | goto err; |
| 5125 | } |
| 5126 | |
| 5127 | pin_cfg.num_pins = num_pins; |
| 5128 | for (i = 0; i < num_pins; ++i) |
| 5129 | pin_cfg.pins[i] = (int)lane_arr[i]; |
| 5130 | |
| 5131 | r = dsi_configure_pins(&dsi->output, &pin_cfg); |
| 5132 | if (r) { |
| 5133 | dev_err(&pdev->dev, "failed to configure pins"); |
| 5134 | goto err; |
| 5135 | } |
| 5136 | |
| 5137 | of_node_put(ep); |
| 5138 | |
| 5139 | return 0; |
| 5140 | |
| 5141 | err: |
| 5142 | of_node_put(ep); |
| 5143 | return r; |
| 5144 | } |
| 5145 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 5146 | static const struct dss_pll_ops dsi_pll_ops = { |
| 5147 | .enable = dsi_pll_enable, |
| 5148 | .disable = dsi_pll_disable, |
| 5149 | .set_config = dss_pll_write_config_type_a, |
| 5150 | }; |
| 5151 | |
| 5152 | static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { |
| 5153 | .n_max = (1 << 7) - 1, |
| 5154 | .m_max = (1 << 11) - 1, |
| 5155 | .mX_max = (1 << 4) - 1, |
| 5156 | .fint_min = 750000, |
| 5157 | .fint_max = 2100000, |
| 5158 | .clkdco_low = 1000000000, |
| 5159 | .clkdco_max = 1800000000, |
| 5160 | |
| 5161 | .n_msb = 7, |
| 5162 | .n_lsb = 1, |
| 5163 | .m_msb = 18, |
| 5164 | .m_lsb = 8, |
| 5165 | |
| 5166 | .mX_msb[0] = 22, |
| 5167 | .mX_lsb[0] = 19, |
| 5168 | .mX_msb[1] = 26, |
| 5169 | .mX_lsb[1] = 23, |
| 5170 | |
| 5171 | .has_stopmode = true, |
| 5172 | .has_freqsel = true, |
| 5173 | .has_selfreqdco = false, |
| 5174 | .has_refsel = false, |
| 5175 | }; |
| 5176 | |
| 5177 | static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { |
| 5178 | .n_max = (1 << 8) - 1, |
| 5179 | .m_max = (1 << 12) - 1, |
| 5180 | .mX_max = (1 << 5) - 1, |
| 5181 | .fint_min = 500000, |
| 5182 | .fint_max = 2500000, |
| 5183 | .clkdco_low = 1000000000, |
| 5184 | .clkdco_max = 1800000000, |
| 5185 | |
| 5186 | .n_msb = 8, |
| 5187 | .n_lsb = 1, |
| 5188 | .m_msb = 20, |
| 5189 | .m_lsb = 9, |
| 5190 | |
| 5191 | .mX_msb[0] = 25, |
| 5192 | .mX_lsb[0] = 21, |
| 5193 | .mX_msb[1] = 30, |
| 5194 | .mX_lsb[1] = 26, |
| 5195 | |
| 5196 | .has_stopmode = true, |
| 5197 | .has_freqsel = false, |
| 5198 | .has_selfreqdco = false, |
| 5199 | .has_refsel = false, |
| 5200 | }; |
| 5201 | |
| 5202 | static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { |
| 5203 | .n_max = (1 << 8) - 1, |
| 5204 | .m_max = (1 << 12) - 1, |
| 5205 | .mX_max = (1 << 5) - 1, |
| 5206 | .fint_min = 150000, |
| 5207 | .fint_max = 52000000, |
| 5208 | .clkdco_low = 1000000000, |
| 5209 | .clkdco_max = 1800000000, |
| 5210 | |
| 5211 | .n_msb = 8, |
| 5212 | .n_lsb = 1, |
| 5213 | .m_msb = 20, |
| 5214 | .m_lsb = 9, |
| 5215 | |
| 5216 | .mX_msb[0] = 25, |
| 5217 | .mX_lsb[0] = 21, |
| 5218 | .mX_msb[1] = 30, |
| 5219 | .mX_lsb[1] = 26, |
| 5220 | |
| 5221 | .has_stopmode = true, |
| 5222 | .has_freqsel = false, |
| 5223 | .has_selfreqdco = true, |
| 5224 | .has_refsel = true, |
| 5225 | }; |
| 5226 | |
| 5227 | static int dsi_init_pll_data(struct platform_device *dsidev) |
| 5228 | { |
| 5229 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 5230 | struct dss_pll *pll = &dsi->pll; |
| 5231 | struct clk *clk; |
| 5232 | int r; |
| 5233 | |
| 5234 | clk = devm_clk_get(&dsidev->dev, "sys_clk"); |
| 5235 | if (IS_ERR(clk)) { |
| 5236 | DSSERR("can't get sys_clk\n"); |
| 5237 | return PTR_ERR(clk); |
| 5238 | } |
| 5239 | |
| 5240 | pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; |
Tomi Valkeinen | 64e22ff | 2015-01-02 10:05:33 +0200 | [diff] [blame] | 5241 | pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 5242 | pll->clkin = clk; |
| 5243 | pll->base = dsi->pll_base; |
| 5244 | |
| 5245 | switch (omapdss_get_version()) { |
| 5246 | case OMAPDSS_VER_OMAP34xx_ES1: |
| 5247 | case OMAPDSS_VER_OMAP34xx_ES3: |
| 5248 | case OMAPDSS_VER_OMAP3630: |
| 5249 | case OMAPDSS_VER_AM35xx: |
| 5250 | pll->hw = &dss_omap3_dsi_pll_hw; |
| 5251 | break; |
| 5252 | |
| 5253 | case OMAPDSS_VER_OMAP4430_ES1: |
| 5254 | case OMAPDSS_VER_OMAP4430_ES2: |
| 5255 | case OMAPDSS_VER_OMAP4: |
| 5256 | pll->hw = &dss_omap4_dsi_pll_hw; |
| 5257 | break; |
| 5258 | |
| 5259 | case OMAPDSS_VER_OMAP5: |
| 5260 | pll->hw = &dss_omap5_dsi_pll_hw; |
| 5261 | break; |
| 5262 | |
| 5263 | default: |
| 5264 | return -ENODEV; |
| 5265 | } |
| 5266 | |
| 5267 | pll->ops = &dsi_pll_ops; |
| 5268 | |
| 5269 | r = dss_pll_register(pll); |
| 5270 | if (r) |
| 5271 | return r; |
| 5272 | |
| 5273 | return 0; |
| 5274 | } |
| 5275 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 5276 | /* DSI1 HW IP initialisation */ |
Tomi Valkeinen | ee4a24e | 2013-04-26 13:47:06 +0300 | [diff] [blame] | 5277 | static int omap_dsihw_probe(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5278 | { |
| 5279 | u32 rev; |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 5280 | int r, i; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5281 | struct dsi_data *dsi; |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5282 | struct resource *dsi_mem; |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 5283 | struct resource *res; |
| 5284 | struct resource temp_res; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5285 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 5286 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5287 | if (!dsi) |
| 5288 | return -ENOMEM; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5289 | |
| 5290 | dsi->pdev = dsidev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5291 | dev_set_drvdata(&dsidev->dev, dsi); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 5292 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5293 | spin_lock_init(&dsi->irq_lock); |
| 5294 | spin_lock_init(&dsi->errors_lock); |
| 5295 | dsi->errors = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5296 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 5297 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5298 | spin_lock_init(&dsi->irq_stats_lock); |
| 5299 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 5300 | #endif |
| 5301 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5302 | mutex_init(&dsi->lock); |
| 5303 | sema_init(&dsi->bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5304 | |
Tejun Heo | 203b42f | 2012-08-21 13:18:23 -0700 | [diff] [blame] | 5305 | INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, |
| 5306 | dsi_framedone_timeout_work_callback); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5307 | |
| 5308 | #ifdef DSI_CATCH_MISSING_TE |
| 5309 | init_timer(&dsi->te_timer); |
| 5310 | dsi->te_timer.function = dsi_te_timeout; |
| 5311 | dsi->te_timer.data = 0; |
| 5312 | #endif |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 5313 | |
| 5314 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); |
| 5315 | if (!res) { |
| 5316 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); |
| 5317 | if (!res) { |
| 5318 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 5319 | return -EINVAL; |
| 5320 | } |
| 5321 | |
| 5322 | temp_res.start = res->start; |
| 5323 | temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; |
| 5324 | res = &temp_res; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 5325 | } |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5326 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5327 | dsi_mem = res; |
| 5328 | |
Tomi Valkeinen | 6810446 | 2013-12-17 13:53:28 +0200 | [diff] [blame] | 5329 | dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, |
| 5330 | resource_size(res)); |
| 5331 | if (!dsi->proto_base) { |
| 5332 | DSSERR("can't ioremap DSI protocol engine\n"); |
| 5333 | return -ENOMEM; |
| 5334 | } |
| 5335 | |
| 5336 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); |
| 5337 | if (!res) { |
| 5338 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); |
| 5339 | if (!res) { |
| 5340 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 5341 | return -EINVAL; |
| 5342 | } |
| 5343 | |
| 5344 | temp_res.start = res->start + DSI_PHY_OFFSET; |
| 5345 | temp_res.end = temp_res.start + DSI_PHY_SZ - 1; |
| 5346 | res = &temp_res; |
| 5347 | } |
| 5348 | |
| 5349 | dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, |
| 5350 | resource_size(res)); |
| 5351 | if (!dsi->proto_base) { |
| 5352 | DSSERR("can't ioremap DSI PHY\n"); |
| 5353 | return -ENOMEM; |
| 5354 | } |
| 5355 | |
| 5356 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); |
| 5357 | if (!res) { |
| 5358 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); |
| 5359 | if (!res) { |
| 5360 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
| 5361 | return -EINVAL; |
| 5362 | } |
| 5363 | |
| 5364 | temp_res.start = res->start + DSI_PLL_OFFSET; |
| 5365 | temp_res.end = temp_res.start + DSI_PLL_SZ - 1; |
| 5366 | res = &temp_res; |
| 5367 | } |
| 5368 | |
| 5369 | dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, |
| 5370 | resource_size(res)); |
| 5371 | if (!dsi->proto_base) { |
| 5372 | DSSERR("can't ioremap DSI PLL\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5373 | return -ENOMEM; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5374 | } |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5375 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5376 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
| 5377 | if (dsi->irq < 0) { |
| 5378 | DSSERR("platform_get_irq failed\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5379 | return -ENODEV; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5380 | } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 5381 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 5382 | r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, |
| 5383 | IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 5384 | if (r < 0) { |
| 5385 | DSSERR("request_irq failed\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5386 | return r; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 5387 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5388 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5389 | if (dsidev->dev.of_node) { |
| 5390 | const struct of_device_id *match; |
| 5391 | const struct dsi_module_id_data *d; |
| 5392 | |
| 5393 | match = of_match_node(dsi_of_match, dsidev->dev.of_node); |
| 5394 | if (!match) { |
| 5395 | DSSERR("unsupported DSI module\n"); |
| 5396 | return -ENODEV; |
| 5397 | } |
| 5398 | |
| 5399 | d = match->data; |
| 5400 | |
| 5401 | while (d->address != 0 && d->address != dsi_mem->start) |
| 5402 | d++; |
| 5403 | |
| 5404 | if (d->address == 0) { |
| 5405 | DSSERR("unsupported DSI module\n"); |
| 5406 | return -ENODEV; |
| 5407 | } |
| 5408 | |
| 5409 | dsi->module_id = d->id; |
| 5410 | } else { |
| 5411 | dsi->module_id = dsidev->id; |
| 5412 | } |
| 5413 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 5414 | /* DSI VCs initialization */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5415 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 5416 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5417 | dsi->vc[i].dssdev = NULL; |
| 5418 | dsi->vc[i].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 5419 | } |
| 5420 | |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5421 | r = dsi_get_clocks(dsidev); |
| 5422 | if (r) |
| 5423 | return r; |
| 5424 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 5425 | dsi_init_pll_data(dsidev); |
| 5426 | |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5427 | pm_runtime_enable(&dsidev->dev); |
| 5428 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5429 | r = dsi_runtime_get(dsidev); |
| 5430 | if (r) |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5431 | goto err_runtime_get; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5432 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 5433 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
| 5434 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5435 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 5436 | |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 5437 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number |
| 5438 | * of data to 3 by default */ |
| 5439 | if (dss_has_feature(FEAT_DSI_GNQ)) |
| 5440 | /* NB_DATA_LANES */ |
| 5441 | dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); |
| 5442 | else |
| 5443 | dsi->num_lanes_supported = 3; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 5444 | |
Tomi Valkeinen | 9932257 | 2013-03-05 10:37:02 +0200 | [diff] [blame] | 5445 | dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); |
| 5446 | |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5447 | dsi_init_output(dsidev); |
| 5448 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5449 | if (dsidev->dev.of_node) { |
| 5450 | r = dsi_probe_of(dsidev); |
| 5451 | if (r) { |
| 5452 | DSSERR("Invalid DSI DT data\n"); |
| 5453 | goto err_probe_of; |
| 5454 | } |
| 5455 | |
| 5456 | r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, |
| 5457 | &dsidev->dev); |
| 5458 | if (r) |
| 5459 | DSSERR("Failed to populate DSI child devices: %d\n", r); |
| 5460 | } |
| 5461 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5462 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5463 | |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 5464 | if (dsi->module_id == 0) |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 5465 | dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 5466 | else if (dsi->module_id == 1) |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 5467 | dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); |
| 5468 | |
| 5469 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 5470 | if (dsi->module_id == 0) |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 5471 | dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); |
Tomi Valkeinen | 11ee960 | 2012-03-09 16:07:39 +0200 | [diff] [blame] | 5472 | else if (dsi->module_id == 1) |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 5473 | dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); |
| 5474 | #endif |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5475 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5476 | return 0; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5477 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5478 | err_probe_of: |
| 5479 | dsi_uninit_output(dsidev); |
| 5480 | dsi_runtime_put(dsidev); |
| 5481 | |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 5482 | err_runtime_get: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5483 | pm_runtime_disable(&dsidev->dev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5484 | return r; |
| 5485 | } |
| 5486 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 5487 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 5488 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 5489 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 5490 | |
Tomi Valkeinen | e4e42b8 | 2014-07-31 16:15:39 +0300 | [diff] [blame] | 5491 | of_platform_depopulate(&dsidev->dev); |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5492 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 5493 | WARN_ON(dsi->scp_clk_refcount > 0); |
| 5494 | |
Tomi Valkeinen | 2daea7a | 2014-10-22 14:49:14 +0300 | [diff] [blame] | 5495 | dss_pll_unregister(&dsi->pll); |
| 5496 | |
Archit Taneja | 81b87f5 | 2012-09-26 16:30:49 +0530 | [diff] [blame] | 5497 | dsi_uninit_output(dsidev); |
| 5498 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5499 | pm_runtime_disable(&dsidev->dev); |
| 5500 | |
Tomi Valkeinen | b2541c4 | 2013-05-03 13:42:24 +0300 | [diff] [blame] | 5501 | if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { |
| 5502 | regulator_disable(dsi->vdds_dsi_reg); |
| 5503 | dsi->vdds_dsi_enabled = false; |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5504 | } |
| 5505 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5506 | return 0; |
| 5507 | } |
| 5508 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5509 | static int dsi_runtime_suspend(struct device *dev) |
| 5510 | { |
Tomi Valkeinen | 0925afc | 2014-04-11 13:49:55 +0300 | [diff] [blame] | 5511 | struct platform_device *pdev = to_platform_device(dev); |
| 5512 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); |
| 5513 | |
| 5514 | dsi->is_enabled = false; |
| 5515 | /* ensure the irq handler sees the is_enabled value */ |
| 5516 | smp_wmb(); |
| 5517 | /* wait for current handler to finish before turning the DSI off */ |
| 5518 | synchronize_irq(dsi->irq); |
| 5519 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5520 | dispc_runtime_put(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5521 | |
| 5522 | return 0; |
| 5523 | } |
| 5524 | |
| 5525 | static int dsi_runtime_resume(struct device *dev) |
| 5526 | { |
Tomi Valkeinen | 0925afc | 2014-04-11 13:49:55 +0300 | [diff] [blame] | 5527 | struct platform_device *pdev = to_platform_device(dev); |
| 5528 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5529 | int r; |
| 5530 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5531 | r = dispc_runtime_get(); |
| 5532 | if (r) |
Tomi Valkeinen | 852f083 | 2012-02-17 17:58:04 +0200 | [diff] [blame] | 5533 | return r; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5534 | |
Tomi Valkeinen | 0925afc | 2014-04-11 13:49:55 +0300 | [diff] [blame] | 5535 | dsi->is_enabled = true; |
| 5536 | /* ensure the irq handler sees the is_enabled value */ |
| 5537 | smp_wmb(); |
| 5538 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5539 | return 0; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5540 | } |
| 5541 | |
| 5542 | static const struct dev_pm_ops dsi_pm_ops = { |
| 5543 | .runtime_suspend = dsi_runtime_suspend, |
| 5544 | .runtime_resume = dsi_runtime_resume, |
| 5545 | }; |
| 5546 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5547 | static const struct dsi_module_id_data dsi_of_data_omap3[] = { |
| 5548 | { .address = 0x4804fc00, .id = 0, }, |
| 5549 | { }, |
| 5550 | }; |
| 5551 | |
| 5552 | static const struct dsi_module_id_data dsi_of_data_omap4[] = { |
| 5553 | { .address = 0x58004000, .id = 0, }, |
| 5554 | { .address = 0x58005000, .id = 1, }, |
| 5555 | { }, |
| 5556 | }; |
| 5557 | |
Tomi Valkeinen | bd3ad6a | 2014-03-07 12:44:24 +0200 | [diff] [blame] | 5558 | static const struct dsi_module_id_data dsi_of_data_omap5[] = { |
| 5559 | { .address = 0x58004000, .id = 0, }, |
| 5560 | { .address = 0x58009000, .id = 1, }, |
| 5561 | { }, |
| 5562 | }; |
| 5563 | |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5564 | static const struct of_device_id dsi_of_match[] = { |
| 5565 | { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, |
| 5566 | { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, |
Tomi Valkeinen | bd3ad6a | 2014-03-07 12:44:24 +0200 | [diff] [blame] | 5567 | { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5568 | {}, |
| 5569 | }; |
| 5570 | |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 5571 | static struct platform_driver omap_dsihw_driver = { |
Tomi Valkeinen | ee4a24e | 2013-04-26 13:47:06 +0300 | [diff] [blame] | 5572 | .probe = omap_dsihw_probe, |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 5573 | .remove = __exit_p(omap_dsihw_remove), |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5574 | .driver = { |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 5575 | .name = "omapdss_dsi", |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 5576 | .pm = &dsi_pm_ops, |
Tomi Valkeinen | 6274a61 | 2012-08-21 15:35:42 +0300 | [diff] [blame] | 5577 | .of_match_table = dsi_of_match, |
Tomi Valkeinen | 422ccbd | 2014-10-16 09:54:25 +0300 | [diff] [blame] | 5578 | .suppress_bind_attrs = true, |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5579 | }, |
| 5580 | }; |
| 5581 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 5582 | int __init dsi_init_platform_driver(void) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5583 | { |
Tomi Valkeinen | ee4a24e | 2013-04-26 13:47:06 +0300 | [diff] [blame] | 5584 | return platform_driver_register(&omap_dsihw_driver); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5585 | } |
| 5586 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 5587 | void __exit dsi_uninit_platform_driver(void) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5588 | { |
Tomi Valkeinen | 04c742c | 2012-02-23 15:32:37 +0200 | [diff] [blame] | 5589 | platform_driver_unregister(&omap_dsihw_driver); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 5590 | } |