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gerrit-public.fairphone.software / kernel / msm-4.9 / 7c143465dbf6986602f9bf1caf9c2576b85ea369 / . / arch / arm64 / boot / dts / qcom / sdm670.dtsi
blob: 021549cf5cacbe3dc8f20711794f9e6fe257fb2d [file] [log] [blame]
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]1/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "skeleton64.dtsi"
14#include <dt-bindings/interrupt-controller/arm-gic.h>
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]15#include <dt-bindings/clock/qcom,gcc-sdm845.h>
16#include <dt-bindings/clock/qcom,camcc-sdm845.h>
17#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
18#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
19#include <dt-bindings/clock/qcom,videocc-sdm845.h>
20#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
21#include <dt-bindings/clock/qcom,rpmh.h>
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]22#include <dt-bindings/soc/qcom,tcs-mbox.h>
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]23#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]24#include <dt-bindings/clock/qcom,aop-qmp.h>
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]25
Santosh Mardi903c95d2017-09-25 10:36:29 +0530[diff] [blame]26#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
27
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]28/ {
29 model = "Qualcomm Technologies, Inc. SDM670";
30 compatible = "qcom,sdm670";
31 qcom,msm-id = <336 0x0>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]32 interrupt-parent = <&pdc>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]33
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]34 aliases {
35 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]36 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]37 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
Mukesh Kumar Savaliya7b272542017-07-10 19:35:29 +0530[diff] [blame]38 serial0 = &qupv3_se12_2uart;
39 spi0 = &qupv3_se8_spi;
40 i2c0 = &qupv3_se10_i2c;
41 i2c1 = &qupv3_se3_i2c;
42 hsuart0 = &qupv3_se6_4uart;
43 };
44
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]45 chosen {
Pavankumar Kondeti2c218d72017-10-03 19:31:31 +0530[diff] [blame]46 bootargs = "rcupdate.rcu_expedited=1 core_ctl_disable_cpumask=6-7";
Lingutla Chandrasekhard9eb37a2017-10-03 19:53:36 +0530[diff] [blame]47 };
48
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]49 cpus {
50 #address-cells = <2>;
51 #size-cells = <0>;
52
53 CPU0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,armv8";
56 reg = <0x0 0x0>;
57 enable-method = "psci";
58 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]59 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]60 cpu-release-addr = <0x0 0x90000000>;
61 next-level-cache = <&L2_0>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]62 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]63 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]64 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]65 L2_0: l2-cache {
66 compatible = "arm,arch-cache";
67 cache-size = <0x20000>;
68 cache-level = <2>;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "arm,arch-cache";
72 cache-size = <0x100000>;
73 cache-level = <3>;
74 };
75 };
76 L1_I_0: l1-icache {
77 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]78 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]79 };
80 L1_D_0: l1-dcache {
81 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]82 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]83 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]84 L1_TLB_0: l1-tlb {
85 qcom,dump-size = <0x3000>;
86 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]87 };
88
89 CPU1: cpu@100 {
90 device_type = "cpu";
91 compatible = "arm,armv8";
92 reg = <0x0 0x100>;
93 enable-method = "psci";
94 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]95 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]96 cpu-release-addr = <0x0 0x90000000>;
97 next-level-cache = <&L2_100>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]98 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]99 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]100 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]101 L2_100: l2-cache {
102 compatible = "arm,arch-cache";
103 cache-size = <0x20000>;
104 cache-level = <2>;
105 next-level-cache = <&L3_0>;
106 };
107 L1_I_100: l1-icache {
108 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]109 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]110 };
111 L1_D_100: l1-dcache {
112 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]113 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]114 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]115 L1_TLB_100: l1-tlb {
116 qcom,dump-size = <0x3000>;
117 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]118 };
119
120 CPU2: cpu@200 {
121 device_type = "cpu";
122 compatible = "arm,armv8";
123 reg = <0x0 0x200>;
124 enable-method = "psci";
125 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]126 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]127 cpu-release-addr = <0x0 0x90000000>;
128 next-level-cache = <&L2_200>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]129 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]130 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]131 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]132 L2_200: l2-cache {
133 compatible = "arm,arch-cache";
134 cache-size = <0x20000>;
135 cache-level = <2>;
136 next-level-cache = <&L3_0>;
137 };
138 L1_I_200: l1-icache {
139 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]140 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]141 };
142 L1_D_200: l1-dcache {
143 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]144 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]145 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]146 L1_TLB_200: l1-tlb {
147 qcom,dump-size = <0x3000>;
148 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]149 };
150
151 CPU3: cpu@300 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x0 0x300>;
155 enable-method = "psci";
156 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]157 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]158 cpu-release-addr = <0x0 0x90000000>;
159 next-level-cache = <&L2_300>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]160 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]161 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]162 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]163 L2_300: l2-cache {
164 compatible = "arm,arch-cache";
165 cache-size = <0x20000>;
166 cache-level = <2>;
167 next-level-cache = <&L3_0>;
168 };
169 L1_I_300: l1-icache {
170 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]171 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]172 };
173 L1_D_300: l1-dcache {
174 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]175 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]176 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]177 L1_TLB_300: l1-tlb {
178 qcom,dump-size = <0x3000>;
179 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]180 };
181
182 CPU4: cpu@400 {
183 device_type = "cpu";
184 compatible = "arm,armv8";
185 reg = <0x0 0x400>;
186 enable-method = "psci";
187 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]188 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]189 cpu-release-addr = <0x0 0x90000000>;
190 next-level-cache = <&L2_400>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]191 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]192 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]193 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]194 L2_400: l2-cache {
195 compatible = "arm,arch-cache";
196 cache-size = <0x20000>;
197 cache-level = <2>;
198 next-level-cache = <&L3_0>;
199 };
200 L1_I_400: l1-icache {
201 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]202 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]203 };
204 L1_D_400: l1-dcache {
205 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]206 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]207 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]208 L1_TLB_400: l1-tlb {
209 qcom,dump-size = <0x3000>;
210 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]211 };
212
213 CPU5: cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x0 0x500>;
217 enable-method = "psci";
218 efficiency = <1024>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]219 cache-size = <0x10000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]220 cpu-release-addr = <0x0 0x90000000>;
221 next-level-cache = <&L2_500>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]222 sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]223 qcom,lmh-dcvs = <&lmh_dcvs0>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]224 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]225 L2_500: l2-cache {
226 compatible = "arm,arch-cache";
227 cache-size = <0x20000>;
228 cache-level = <2>;
229 next-level-cache = <&L3_0>;
230 };
231 L1_I_500: l1-icache {
232 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]233 qcom,dump-size = <0x12000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]234 };
235 L1_D_500: l1-dcache {
236 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]237 qcom,dump-size = <0xa000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]238 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]239 L1_TLB_500: l1-tlb {
240 qcom,dump-size = <0x3000>;
241 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]242 };
243
244 CPU6: cpu@600 {
245 device_type = "cpu";
246 compatible = "arm,armv8";
247 reg = <0x0 0x600>;
248 enable-method = "psci";
249 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]250 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]251 cpu-release-addr = <0x0 0x90000000>;
252 next-level-cache = <&L2_600>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]253 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]254 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]255 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]256 L2_600: l2-cache {
257 compatible = "arm,arch-cache";
258 cache-size = <0x40000>;
259 cache-level = <2>;
260 next-level-cache = <&L3_0>;
261 };
262 L1_I_600: l1-icache {
263 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]264 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]265 };
266 L1_D_600: l1-dcache {
267 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]268 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]269 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]270 L1_TLB_600: l1-tlb {
271 qcom,dump-size = <0x3c000>;
272 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]273 };
274
275 CPU7: cpu@700 {
276 device_type = "cpu";
277 compatible = "arm,armv8";
278 reg = <0x0 0x700>;
279 enable-method = "psci";
280 efficiency = <1740>;
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]281 cache-size = <0x20000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]282 cpu-release-addr = <0x0 0x90000000>;
283 next-level-cache = <&L2_700>;
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]284 sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
Manaf Meethalavalappu Pallikunhiae5420e2017-09-07 01:01:08 +0530[diff] [blame]285 qcom,lmh-dcvs = <&lmh_dcvs1>;
Manaf Meethalavalappu Pallikunhi07ee0812017-09-07 01:09:06 +0530[diff] [blame]286 #cooling-cells = <2>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]287 L2_700: l2-cache {
288 compatible = "arm,arch-cache";
289 cache-size = <0x40000>;
290 cache-level = <2>;
291 next-level-cache = <&L3_0>;
292 };
293 L1_I_700: l1-icache {
294 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]295 qcom,dump-size = <0x24000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]296 };
297 L1_D_700: l1-dcache {
298 compatible = "arm,arch-cache";
Lingutla Chandrasekharc4b762a2017-10-12 12:12:44 +0530[diff] [blame]299 qcom,dump-size = <0x14000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]300 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]301 L1_TLB_700: l1-tlb {
302 qcom,dump-size = <0x3c000>;
303 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]304 };
305
306 cpu-map {
307 cluster0 {
308 core0 {
309 cpu = <&CPU0>;
310 };
311
312 core1 {
313 cpu = <&CPU1>;
314 };
315
316 core2 {
317 cpu = <&CPU2>;
318 };
319
320 core3 {
321 cpu = <&CPU3>;
322 };
323
324 core4 {
325 cpu = <&CPU4>;
326 };
327
328 core5 {
329 cpu = <&CPU5>;
330 };
331 };
332 cluster1 {
333 core0 {
334 cpu = <&CPU6>;
335 };
336
337 core1 {
338 cpu = <&CPU7>;
339 };
340 };
341 };
342 };
343
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]344 energy_costs: energy-costs {
345 compatible = "sched-energy";
346
347 CPU_COST_0: core-cost0 {
348 busy-cost-data = <
349 300000 14
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]350 576000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]351 748800 31
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]352 998400 46
353 1209600 57
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]354 1324800 84
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]355 1516800 96
356 1612800 114
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]357 1708800 139
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]358 >;
359 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]360 12 10 8 6 4
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]361 >;
362 };
363 CPU_COST_1: core-cost1 {
364 busy-cost-data = <
365 300000 256
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]366 652800 307
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]367 825600 332
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]368 979200 382
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]369 1132800 408
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]370 1363200 448
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]371 1536000 586
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]372 1747200 641
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]373 1843200 659
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]374 1996800 696
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]375 2016000 865
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]376 2054400 876
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]377 2169600 900
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]378 2208000 924
Pavankumar Kondeti0011ca12018-12-04 10:06:40 +0530[diff] [blame]379 2304000 940
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]380 2361600 948
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]381 2400000 1170
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]382 2457600 1200
383 2515200 1300
384 2611200 1400
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]385 >;
386 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]387 100 80 60 40 20
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]388 >;
389 };
390 CLUSTER_COST_0: cluster-cost0 {
391 busy-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]392 300000 6
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]393 576000 7
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]394 748800 8
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]395 998400 9
396 1209600 10
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]397 1324800 13
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]398 1516800 15
399 1612800 16
Pavankumar Kondeti80872462017-11-06 08:57:45 +0530[diff] [blame]400 1708800 19
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]401 >;
402 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]403 5 4 3 2 1
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]404 >;
405 };
406 CLUSTER_COST_1: cluster-cost1 {
407 busy-cost-data = <
408 300000 25
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]409 652800 30
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]410 825600 33
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]411 979200 38
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]412 1132800 40
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]413 1363200 44
Pavankumar Kondeti865e7562017-11-06 08:57:45 +0530[diff] [blame]414 1536000 58
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]415 1747200 64
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]416 1843200 65
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]417 1996800 69
Pavankumar Kondetid019a602017-11-06 08:57:45 +0530[diff] [blame]418 2016000 85
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]419 2054400 87
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]420 2169600 90
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]421 2208000 92
Pavankumar Kondeti0011ca12018-12-04 10:06:40 +0530[diff] [blame]422 2304000 93
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]423 2361600 94
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]424 2400000 117
Pavankumar Kondeti5c494942017-10-26 12:09:18 +0530[diff] [blame]425 2457600 120
426 2515200 130
427 2611200 140
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]428 >;
429 idle-cost-data = <
Lingutla Chandrasekharf9eeb282018-10-30 14:24:55 +0530[diff] [blame]430 5 4 3 2 1
Pavankumar Kondetie4231242017-09-12 12:19:57 +0530[diff] [blame]431 >;
432 };
433 };
434
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]435 psci {
436 compatible = "arm,psci-1.0";
437 method = "smc";
438 };
439
440 soc: soc { };
441
Imran Khanb1066fa2017-08-01 17:20:22 +0530[diff] [blame]442 vendor: vendor {
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges = <0 0 0 0xffffffff>;
446 compatible = "simple-bus";
447 };
448
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]449 firmware: firmware {
450 android {
451 compatible = "android,firmware";
452
monisingfb2cb762017-12-19 14:40:49 +0530[diff] [blame]453 vbmeta {
454 compatible = "android,vbmeta";
455 parts = "vbmeta,boot,system,vendor,dtbo";
456 };
457
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]458 fstab {
459 compatible = "android,fstab";
460 vendor {
461 compatible = "android,vendor";
462 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
463 type = "ext4";
464 mnt_flags = "ro,barrier=1,discard";
AnilKumar Chimata0d646ab2017-10-25 22:09:03 +0530[diff] [blame]465 fsmgr_flags = "wait,slotselect,avb";
Rahul Shahare902e6732019-05-30 10:06:51 +0530[diff] [blame]466 status = "ok";
Imran Khan5381c932017-08-02 11:27:07 +0530[diff] [blame]467 };
468 };
469 };
470 };
471
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]472 reserved-memory {
473 #address-cells = <2>;
474 #size-cells = <2>;
475 ranges;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]476
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]477 hyp_region: hyp_region@85700000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]478 compatible = "removed-dma-pool";
479 no-map;
Vijayanand Jitta0ef73982017-12-11 11:19:29 +0530[diff] [blame]480 reg = <0 0x85700000 0 0x600000>;
481 };
482
483 xbl_region: xbl_region@85e00000 {
484 compatible = "removed-dma-pool";
485 no-map;
486 reg = <0 0x85e00000 0 0x100000>;
487 };
488
489 removed_region: removed_region@85fc0000 {
490 compatible = "removed-dma-pool";
491 no-map;
492 reg = <0 0x85fc0000 0 0x2f40000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]493 };
494
495 pil_camera_mem: camera_region@8ab00000 {
496 compatible = "removed-dma-pool";
497 no-map;
498 reg = <0 0x8ab00000 0 0x500000>;
499 };
500
501 pil_modem_mem: modem_region@8b000000 {
502 compatible = "removed-dma-pool";
503 no-map;
504 reg = <0 0x8b000000 0 0x7e00000>;
505 };
506
507 pil_video_mem: pil_video_region@92e00000 {
508 compatible = "removed-dma-pool";
509 no-map;
510 reg = <0 0x92e00000 0 0x500000>;
511 };
512
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]513 wlan_msa_mem: wlan_msa_region@93300000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]514 compatible = "removed-dma-pool";
515 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]516 reg = <0 0x93300000 0 0x100000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]517 };
518
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]519 pil_cdsp_mem: cdsp_regions@93400000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]520 compatible = "removed-dma-pool";
521 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]522 reg = <0 0x93400000 0 0x800000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]523 };
524
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]525 pil_mba_mem: pil_mba_region@0x93c00000 {
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]526 compatible = "removed-dma-pool";
527 no-map;
Prakash Guptac97a6a32017-11-21 17:46:55 +0530[diff] [blame]528 reg = <0 0x93c00000 0 0x200000>;
529 };
530
531 pil_adsp_mem: pil_adsp_region@93e00000 {
532 compatible = "removed-dma-pool";
533 no-map;
534 reg = <0 0x93e00000 0 0x1e00000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]535 };
536
Prakash Gupta7c571ef2018-01-19 17:57:47 +0530[diff] [blame]537 pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
538 compatible = "removed-dma-pool";
539 no-map;
540 reg = <0 0x95c00000 0 0x10000>;
541 };
542
543 pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
544 compatible = "removed-dma-pool";
545 no-map;
546 reg = <0 0x95c10000 0 0x5000>;
547 };
548
549 pil_gpu_mem: gpu_region@0x95c15000 {
550 compatible = "removed-dma-pool";
551 no-map;
552 reg = <0 0x95c15000 0 0x2000>;
553 };
554
555 qseecom_mem: qseecom_region@0x9e400000 {
556 compatible = "shared-dma-pool";
557 no-map;
558 reg = <0 0x9e400000 0 0x1400000>;
559 };
560
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]561 adsp_mem: adsp_region {
562 compatible = "shared-dma-pool";
563 alloc-ranges = <0 0x00000000 0 0xffffffff>;
564 reusable;
565 alignment = <0 0x400000>;
Tharun Kumar Meruguf0bb40e2018-06-25 16:02:04 +0530[diff] [blame]566 size = <0 0x800000>;
567 };
568
569 sdsp_mem: sdsp_region {
570 compatible = "shared-dma-pool";
571 alloc-ranges = <0 0x00000000 0 0xffffffff>;
572 reusable;
573 alignment = <0 0x400000>;
574 size = <0 0x400000>;
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]575 };
576
Zhen Kong0ebe1bc32018-01-02 14:53:51 -0800[diff] [blame]577 qseecom_ta_mem: qseecom_ta_region {
578 compatible = "shared-dma-pool";
579 alloc-ranges = <0 0x00000000 0 0xffffffff>;
580 reusable;
581 alignment = <0 0x400000>;
582 size = <0 0x1000000>;
583 };
584
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]585 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
586 compatible = "shared-dma-pool";
587 alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
588 reusable;
589 alignment = <0 0x400000>;
590 size = <0 0x800000>;
591 };
592
593 secure_display_memory: secure_display_region {
594 compatible = "shared-dma-pool";
595 alloc-ranges = <0 0x00000000 0 0xffffffff>;
596 reusable;
597 alignment = <0 0x400000>;
598 size = <0 0x5c00000>;
599 };
600
Jayant Shekhare3191272018-01-30 16:49:08 +0530[diff] [blame]601 cont_splash_memory: cont_splash_region@9c000000 {
Sandeep Pandaf5ed08d2018-11-08 23:16:46 +0530[diff] [blame]602 reg = <0x0 0x9c000000 0x0 0x2300000>;
Jayant Shekharb59d1692017-11-10 14:21:40 +0530[diff] [blame]603 label = "cont_splash_region";
604 };
605
Sandeep Pandaf5ed08d2018-11-08 23:16:46 +0530[diff] [blame]606 dfps_data_memory: dfps_data_region@9e300000 {
607 reg = <0x0 0x9e300000 0x0 0x0100000>;
608 label = "dfps_data_region";
609 };
610
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]611 dump_mem: mem_dump_region {
612 compatible = "shared-dma-pool";
613 reusable;
614 size = <0 0x2400000>;
615 };
616
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]617 /* global autoconfigured region for contiguous allocations */
618 linux,cma {
619 compatible = "shared-dma-pool";
620 alloc-ranges = <0 0x00000000 0 0xffffffff>;
621 reusable;
622 alignment = <0 0x400000>;
623 size = <0 0x2000000>;
624 linux,cma-default;
625 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]626 };
627};
628
Vijayanand Jittaa1ee7862017-06-07 12:06:39 +0530[diff] [blame]629#include "sdm670-ion.dtsi"
630
Dhoat Harpal92d63dea2017-06-06 21:20:26 +0530[diff] [blame]631#include "sdm670-smp2p.dtsi"
632
c_mtharuce962e42017-12-05 22:41:17 +0530[diff] [blame]633#include "msm-rdbg.dtsi"
634
Mukesh Kumar Savaliya065ca482017-06-06 14:44:45 +0530[diff] [blame]635#include "sdm670-qupv3.dtsi"
636
Saranya Chiduraf49fee12017-06-19 10:52:37 +0530[diff] [blame]637#include "sdm670-coresight.dtsi"
Manikanta Kanamarlapudid4abc602017-08-28 19:23:41 +0530[diff] [blame]638
639#include "sdm670-vidc.dtsi"
640
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]641#include "sdm670-sde-pll.dtsi"
642
643#include "sdm670-sde.dtsi"
644
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]645&soc {
646 #address-cells = <1>;
647 #size-cells = <1>;
648 ranges = <0 0 0 0xffffffff>;
649 compatible = "simple-bus";
650
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]651 jtag_mm0: jtagmm@7040000 {
652 compatible = "qcom,jtagv8-mm";
653 reg = <0x7040000 0x1000>;
654 reg-names = "etm-base";
655
656 clocks = <&clock_aop QDSS_CLK>;
657 clock-names = "core_clk";
658
659 qcom,coresight-jtagmm-cpu = <&CPU0>;
660 };
661
662 jtag_mm1: jtagmm@7140000 {
663 compatible = "qcom,jtagv8-mm";
664 reg = <0x7140000 0x1000>;
665 reg-names = "etm-base";
666
667 clocks = <&clock_aop QDSS_CLK>;
668 clock-names = "core_clk";
669
Mao Jinlong7da84d72018-11-13 21:03:30 +0800[diff] [blame]670 qcom,coresight-jtagmm-cpu = <&CPU1>;
Saranya Chidura0e8b4262017-10-04 13:06:26 +0530[diff] [blame]671 };
672
673 jtag_mm2: jtagmm@7240000 {
674 compatible = "qcom,jtagv8-mm";
675 reg = <0x7240000 0x1000>;
676 reg-names = "etm-base";
677
678 clocks = <&clock_aop QDSS_CLK>;
679 clock-names = "core_clk";
680
681 qcom,coresight-jtagmm-cpu = <&CPU2>;
682 };
683
684 jtag_mm3: jtagmm@7340000 {
685 compatible = "qcom,jtagv8-mm";
686 reg = <0x7340000 0x1000>;
687 reg-names = "etm-base";
688
689 clocks = <&clock_aop QDSS_CLK>;
690 clock-names = "core_clk";
691
692 qcom,coresight-jtagmm-cpu = <&CPU3>;
693 };
694
695 jtag_mm4: jtagmm@7440000 {
696 compatible = "qcom,jtagv8-mm";
697 reg = <0x7440000 0x1000>;
698 reg-names = "etm-base";
699
700 clocks = <&clock_aop QDSS_CLK>;
701 clock-names = "core_clk";
702
703 qcom,coresight-jtagmm-cpu = <&CPU4>;
704 };
705
706 jtag_mm5: jtagmm@7540000 {
707 compatible = "qcom,jtagv8-mm";
708 reg = <0x7540000 0x1000>;
709 reg-names = "etm-base";
710
711 clocks = <&clock_aop QDSS_CLK>;
712 clock-names = "core_clk";
713
714 qcom,coresight-jtagmm-cpu = <&CPU5>;
715 };
716
717 jtag_mm6: jtagmm@7640000 {
718 compatible = "qcom,jtagv8-mm";
719 reg = <0x7640000 0x1000>;
720 reg-names = "etm-base";
721
722 clocks = <&clock_aop QDSS_CLK>;
723 clock-names = "core_clk";
724
725 qcom,coresight-jtagmm-cpu = <&CPU6>;
726 };
727
728 jtag_mm7: jtagmm@7740000 {
729 compatible = "qcom,jtagv8-mm";
730 reg = <0x7740000 0x1000>;
731 reg-names = "etm-base";
732
733 clocks = <&clock_aop QDSS_CLK>;
734 clock-names = "core_clk";
735
736 qcom,coresight-jtagmm-cpu = <&CPU7>;
737 };
738
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]739 intc: interrupt-controller@17a00000 {
740 compatible = "arm,gic-v3";
741 #interrupt-cells = <3>;
742 interrupt-controller;
743 #redistributor-regions = <1>;
744 redistributor-stride = <0x0 0x20000>;
745 reg = <0x17a00000 0x10000>, /* GICD */
746 <0x17a60000 0x100000>; /* GICR * 8 */
747 interrupts = <1 9 4>;
Maulik Shah30ebbde2017-06-15 10:02:54 +0530[diff] [blame]748 interrupt-parent = <&intc>;
Gaurav Kohli34f87562018-05-11 12:26:16 +0530[diff] [blame]749 ignored-save-restore-irqs = <38>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]750 };
751
Raghavendra Kakarla04f032162017-12-08 19:11:54 +0530[diff] [blame]752 pdc: interrupt-controller@b220000{
753 compatible = "qcom,pdc-sdm670";
754 reg = <0xb220000 0x400>;
755 #interrupt-cells = <3>;
756 interrupt-parent = <&intc>;
757 interrupt-controller;
758 };
759
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]760 timer {
761 compatible = "arm,armv8-timer";
762 interrupts = <1 1 0xf08>,
763 <1 2 0xf08>,
764 <1 3 0xf08>,
765 <1 0 0xf08>;
766 clock-frequency = <19200000>;
767 };
768
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]769 qcom,memshare {
770 compatible = "qcom,memshare";
771
772 qcom,client_1 {
773 compatible = "qcom,memshare-peripheral";
774 qcom,peripheral-size = <0x0>;
775 qcom,client-id = <0>;
776 qcom,allocate-boot-time;
777 label = "modem";
778 };
779
780 qcom,client_2 {
781 compatible = "qcom,memshare-peripheral";
782 qcom,peripheral-size = <0x0>;
783 qcom,client-id = <2>;
784 label = "modem";
785 };
786
787 mem_client_3_size: qcom,client_3 {
788 compatible = "qcom,memshare-peripheral";
789 qcom,peripheral-size = <0x500000>;
790 qcom,client-id = <1>;
Manoj Prabhu B991f9222018-01-03 19:13:56 +0530[diff] [blame]791 qcom,allocate-boot-time;
Manoj Prabhu B95b1bc72017-11-17 15:09:29 +0530[diff] [blame]792 label = "modem";
793 };
794 };
795
Lakshmi Sunkarabbd69892017-06-09 13:17:10 +0530[diff] [blame]796 qcom,sps {
797 compatible = "qcom,msm_sps_4k";
798 qcom,pipe-attr-ee;
799 };
800
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]801 qcom_cedev: qcedev@1de0000 {
802 compatible = "qcom,qcedev";
803 reg = <0x1de0000 0x20000>,
804 <0x1dc4000 0x24000>;
805 reg-names = "crypto-base","crypto-bam-base";
806 interrupts = <0 272 0>;
807 qcom,bam-pipe-pair = <3>;
808 qcom,ce-hw-instance = <0>;
809 qcom,ce-device = <0>;
810 qcom,ce-hw-shared;
811 qcom,bam-ee = <0>;
812 qcom,msm-bus,name = "qcedev-noc";
813 qcom,msm-bus,num-cases = <2>;
814 qcom,msm-bus,num-paths = <1>;
815 qcom,msm-bus,vectors-KBps =
816 <125 512 0 0>,
817 <125 512 393600 393600>;
818 clock-names = "core_clk_src", "core_clk",
819 "iface_clk", "bus_clk";
820 clocks = <&clock_gcc GCC_CE1_CLK>,
821 <&clock_gcc GCC_CE1_CLK>,
822 <&clock_gcc GCC_CE1_AHB_CLK>,
823 <&clock_gcc GCC_CE1_AXI_CLK>;
824 qcom,ce-opp-freq = <171430000>;
825 qcom,request-bw-before-clk;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]826 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]827 iommus = <&apps_smmu 0x706 0x1>,
828 <&apps_smmu 0x716 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]829 };
830
Tatenda Chipeperekwa8a77c8a2018-01-30 14:50:11 -0800[diff] [blame]831 qcom_msmhdcp: qcom,msm_hdcp {
832 compatible = "qcom,msm-hdcp";
833 };
834
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]835 qcom_crypto: qcrypto@1de0000 {
836 compatible = "qcom,qcrypto";
837 reg = <0x1de0000 0x20000>,
838 <0x1dc4000 0x24000>;
839 reg-names = "crypto-base","crypto-bam-base";
840 interrupts = <0 272 0>;
841 qcom,bam-pipe-pair = <2>;
842 qcom,ce-hw-instance = <0>;
843 qcom,ce-device = <0>;
844 qcom,bam-ee = <0>;
845 qcom,ce-hw-shared;
846 qcom,clk-mgmt-sus-res;
847 qcom,msm-bus,name = "qcrypto-noc";
848 qcom,msm-bus,num-cases = <2>;
849 qcom,msm-bus,num-paths = <1>;
850 qcom,msm-bus,vectors-KBps =
851 <125 512 0 0>,
852 <125 512 393600 393600>;
853 clock-names = "core_clk_src", "core_clk",
854 "iface_clk", "bus_clk";
855 clocks = <&clock_gcc GCC_CE1_CLK>,
856 <&clock_gcc GCC_CE1_CLK>,
857 <&clock_gcc GCC_CE1_AHB_CLK>,
858 <&clock_gcc GCC_CE1_AXI_CLK>;
859 qcom,ce-opp-freq = <171430000>;
860 qcom,request-bw-before-clk;
861 qcom,use-sw-aes-cbc-ecb-ctr-algo;
862 qcom,use-sw-aes-xts-algo;
863 qcom,use-sw-aes-ccm-algo;
864 qcom,use-sw-aead-algo;
865 qcom,use-sw-ahash-algo;
866 qcom,use-sw-hmac-algo;
mohamed sunfeer4b2ca442017-11-07 14:46:45 +0530[diff] [blame]867 qcom,smmu-s1-enable;
mohamed sunfeerdce9b922017-11-11 22:14:58 +0530[diff] [blame]868 iommus = <&apps_smmu 0x704 0x1>,
869 <&apps_smmu 0x714 0x1>;
mohamed sunfeer7462bc82017-10-11 22:50:13 +0530[diff] [blame]870 };
871
Abir Ghoshb849ab22017-09-19 13:03:11 +0530[diff] [blame]872 qcom,qbt1000 {
873 compatible = "qcom,qbt1000";
874 clock-names = "core", "iface";
875 clock-frequency = <25000000>;
876 qcom,ipc-gpio = <&tlmm 121 0>;
877 qcom,finger-detect-gpio = <&tlmm 122 0>;
878 };
879
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]880 qcom_seecom: qseecom@86d00000 {
881 compatible = "qcom,qseecom";
882 reg = <0x86d00000 0x2200000>;
883 reg-names = "secapp-region";
884 qcom,hlos-num-ce-hw-instances = <1>;
885 qcom,hlos-ce-hw-instance = <0>;
886 qcom,qsee-ce-hw-instance = <0>;
887 qcom,disk-encrypt-pipe-pair = <2>;
888 qcom,support-fde;
889 qcom,no-clock-support;
Neeraj Soni7c4254c2017-11-15 11:13:14 +0530[diff] [blame]890 qcom,fde-key-size;
mohamed sunfeer71b31322017-09-20 00:46:46 +0530[diff] [blame]891 qcom,appsbl-qseecom-support;
892 qcom,msm-bus,name = "qseecom-noc";
893 qcom,msm-bus,num-cases = <4>;
894 qcom,msm-bus,num-paths = <1>;
895 qcom,msm-bus,vectors-KBps =
896 <125 512 0 0>,
897 <125 512 200000 400000>,
898 <125 512 300000 800000>,
899 <125 512 400000 1000000>;
900 clock-names = "core_clk_src", "core_clk",
901 "iface_clk", "bus_clk";
902 clocks = <&clock_gcc GCC_CE1_CLK>,
903 <&clock_gcc GCC_CE1_CLK>,
904 <&clock_gcc GCC_CE1_AHB_CLK>,
905 <&clock_gcc GCC_CE1_AXI_CLK>;
906 qcom,ce-opp-freq = <171430000>;
907 qcom,qsee-reentrancy-support = <2>;
908 };
909
mohamed sunfeer732f7572017-09-19 19:51:11 +0530[diff] [blame]910 qcom_tzlog: tz-log@146bf720 {
911 compatible = "qcom,tz-log";
912 reg = <0x146bf720 0x3000>;
913 qcom,hyplog-enabled;
914 hyplog-address-offset = <0x410>;
915 hyplog-size-offset = <0x414>;
916 };
917
mohamed sunfeer2228b242017-09-19 19:10:08 +0530[diff] [blame]918 qcom_rng: qrng@793000{
919 compatible = "qcom,msm-rng";
920 reg = <0x793000 0x1000>;
921 qcom,msm-rng-iface-clk;
922 qcom,no-qrng-config;
923 qcom,msm-bus,name = "msm-rng-noc";
924 qcom,msm-bus,num-cases = <2>;
925 qcom,msm-bus,num-paths = <1>;
926 qcom,msm-bus,vectors-KBps =
927 <1 618 0 0>, /* No vote */
928 <1 618 0 800>; /* 100 KHz */
929 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
930 clock-names = "iface_clk";
931 };
932
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]933 thermal_zones: thermal-zones {};
Rama Krishna Phani Aa3c0e782017-07-17 20:09:15 +0530[diff] [blame]934
935 tsens0: tsens@c222000 {
936 compatible = "qcom,tsens24xx";
937 reg = <0xc222000 0x4>,
938 <0xc263000 0x1ff>;
939 reg-names = "tsens_srot_physical",
940 "tsens_tm_physical";
941 interrupts = <0 506 0>, <0 508 0>;
942 interrupt-names = "tsens-upper-lower", "tsens-critical";
943 #thermal-sensor-cells = <1>;
944 };
945
946 tsens1: tsens@c223000 {
947 compatible = "qcom,tsens24xx";
948 reg = <0xc223000 0x4>,
949 <0xc265000 0x1ff>;
950 reg-names = "tsens_srot_physical",
951 "tsens_tm_physical";
952 interrupts = <0 507 0>, <0 509 0>;
953 interrupt-names = "tsens-upper-lower", "tsens-critical";
954 #thermal-sensor-cells = <1>;
955 };
956
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]957 timer@0x17c90000{
958 #address-cells = <1>;
959 #size-cells = <1>;
960 ranges;
961 compatible = "arm,armv7-timer-mem";
962 reg = <0x17c90000 0x1000>;
963 clock-frequency = <19200000>;
964
965 frame@0x17ca0000 {
966 frame-number = <0>;
967 interrupts = <0 7 0x4>,
968 <0 6 0x4>;
969 reg = <0x17ca0000 0x1000>,
970 <0x17cb0000 0x1000>;
971 };
972
973 frame@17cc0000 {
974 frame-number = <1>;
975 interrupts = <0 8 0x4>;
976 reg = <0x17cc0000 0x1000>;
977 status = "disabled";
978 };
979
980 frame@17cd0000 {
981 frame-number = <2>;
982 interrupts = <0 9 0x4>;
983 reg = <0x17cd0000 0x1000>;
984 status = "disabled";
985 };
986
987 frame@17ce0000 {
988 frame-number = <3>;
989 interrupts = <0 10 0x4>;
990 reg = <0x17ce0000 0x1000>;
991 status = "disabled";
992 };
993
994 frame@17cf0000 {
995 frame-number = <4>;
996 interrupts = <0 11 0x4>;
997 reg = <0x17cf0000 0x1000>;
998 status = "disabled";
999 };
1000
1001 frame@17d00000 {
1002 frame-number = <5>;
1003 interrupts = <0 12 0x4>;
1004 reg = <0x17d00000 0x1000>;
1005 status = "disabled";
1006 };
1007
1008 frame@17d10000 {
1009 frame-number = <6>;
1010 interrupts = <0 13 0x4>;
1011 reg = <0x17d10000 0x1000>;
1012 status = "disabled";
1013 };
1014 };
1015
1016 restart@10ac000 {
1017 compatible = "qcom,pshold";
1018 reg = <0xC264000 0x4>,
1019 <0x1fd3000 0x4>;
1020 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1021 };
1022
Maulik Shah6bf7d5d2017-07-27 09:48:42 +0530[diff] [blame]1023 aop-msg-client {
1024 compatible = "qcom,debugfs-qmp-client";
1025 mboxes = <&qmp_aop 0>;
1026 mbox-names = "aop";
1027 };
1028
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1029 clock_rpmh: qcom,rpmhclk {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1030 compatible = "qcom,rpmh-clk-sdm670";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1031 #clock-cells = <1>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1032 mboxes = <&apps_rsc 0>;
1033 mbox-names = "apps";
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1034 };
1035
1036 clock_gcc: qcom,gcc@100000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1037 compatible = "qcom,gcc-sdm670", "syscon";
1038 reg = <0x100000 0x1f0000>;
1039 reg-names = "cc_base";
1040 vdd_cx-supply = <&pm660l_s3_level>;
1041 vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1042 #clock-cells = <1>;
1043 #reset-cells = <1>;
1044 };
1045
1046 clock_videocc: qcom,videocc@ab00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1047 compatible = "qcom,video_cc-sdm670", "syscon";
1048 reg = <0xab00000 0x10000>;
1049 reg-names = "cc_base";
1050 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1051 #clock-cells = <1>;
1052 #reset-cells = <1>;
1053 };
1054
1055 clock_camcc: qcom,camcc@ad00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1056 compatible = "qcom,cam_cc-sdm670", "syscon";
1057 reg = <0xad00000 0x10000>;
1058 reg-names = "cc_base";
1059 vdd_cx-supply = <&pm660l_s3_level>;
1060 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1061 #clock-cells = <1>;
1062 #reset-cells = <1>;
Alok Pandey499587b2018-02-08 22:14:59 +0530[diff] [blame]1063 qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;
1064 qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;
1065 qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;
1066 qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;
1067 qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;
1068 qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;
1069 qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;
1070 qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;
1071 qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;
1072 qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;
1073 qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;
1074 qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;
1075 qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;
1076 qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1077 };
1078
1079 clock_dispcc: qcom,dispcc@af00000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1080 compatible = "qcom,dispcc-sdm670", "syscon";
1081 reg = <0xaf00000 0x10000>;
1082 reg-names = "cc_base";
1083 vdd_cx-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1084 #clock-cells = <1>;
1085 #reset-cells = <1>;
1086 };
1087
1088 clock_gpucc: qcom,gpucc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1089 compatible = "qcom,gpucc-sdm670", "syscon";
1090 reg = <0x5090000 0x9000>;
1091 reg-names = "cc_base";
1092 vdd_cx-supply = <&pm660l_s3_level>;
1093 vdd_mx-supply = <&pm660l_s1_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1094 qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1095 #clock-cells = <1>;
1096 #reset-cells = <1>;
1097 };
1098
1099 clock_gfx: qcom,gfxcc@5090000 {
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1100 compatible = "qcom,gfxcc-sdm670";
1101 reg = <0x5090000 0x9000>;
1102 reg-names = "cc_base";
1103 vdd_gfx-supply = <&pm660l_s2_level>;
Odelu Kukatladc7ac7d2017-09-27 11:05:53 +0530[diff] [blame]1104 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]1105 #clock-cells = <1>;
1106 #reset-cells = <1>;
1107 };
1108
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1109 cpucc_debug: syscon@17970018 {
1110 compatible = "syscon";
1111 reg = <0x17970018 0x4>;
1112 };
1113
1114 clock_debug: qcom,cc-debug {
1115 compatible = "qcom,debugcc-sdm845";
Shefali Jain582eb3b2018-04-24 11:46:58 +0530[diff] [blame]1116 qcom,cc-count = <6>;
Odelu Kukatlad7e457b2017-08-07 22:08:09 +0530[diff] [blame]1117 qcom,gcc = <&clock_gcc>;
1118 qcom,videocc = <&clock_videocc>;
1119 qcom,camcc = <&clock_camcc>;
1120 qcom,dispcc = <&clock_dispcc>;
1121 qcom,gpucc = <&clock_gpucc>;
1122 qcom,cpucc = <&cpucc_debug>;
1123 clock-names = "xo_clk_src";
1124 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1125 #clock-cells = <1>;
1126 };
1127
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1128 clock_cpucc: qcom,cpucc@0x17d41000 {
1129 compatible = "qcom,clk-cpu-osm-sdm670";
1130 reg = <0x17d41000 0x1400>,
1131 <0x17d43000 0x1400>,
David Collins1e048402017-11-29 15:43:09 -0800[diff] [blame]1132 <0x17d45800 0x1400>;
1133 reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
Deepak Katragadda02617bd2017-11-10 16:03:43 -0800[diff] [blame]1134 vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
1135 vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1136
Odelu Kukatla86c179e2017-12-12 19:10:23 +0530[diff] [blame]1137 qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]1138 l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
Odelu Kukatlaffce30a2017-09-23 17:20:48 +0530[diff] [blame]1139
1140 clock-names = "xo_ao";
1141 clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1142 #clock-cells = <1>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1143 };
1144
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1145 clock_aop: qcom,aopclk {
Odelu Kukatla80f617f2017-09-15 19:30:25 +0530[diff] [blame]1146 compatible = "qcom,aop-qmp-clk-v1";
Odelu Kukatla6f3ffa12017-08-10 12:31:06 +0530[diff] [blame]1147 #clock-cells = <1>;
1148 mboxes = <&qmp_aop 0>;
1149 mbox-names = "qdss_clk";
1150 };
1151
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1152 slim_aud: slim@62dc0000 {
1153 cell-index = <1>;
1154 compatible = "qcom,slim-ngd";
1155 reg = <0x62dc0000 0x2c000>,
1156 <0x62d84000 0x2a000>;
1157 reg-names = "slimbus_physical", "slimbus_bam_physical";
1158 interrupts = <0 163 0>, <0 164 0>;
1159 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
1160 qcom,apps-ch-pipes = <0x780000>;
1161 qcom,ea-pc = <0x290>;
1162 status = "disabled";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1163 qcom,iommu-s1-bypass;
1164
1165 iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1166 compatible = "qcom,iommu-slim-ctrl-cb";
1167 iommus = <&apps_smmu 0x1826 0x0>,
1168 <&apps_smmu 0x182d 0x0>,
1169 <&apps_smmu 0x182e 0x1>,
1170 <&apps_smmu 0x1830 0x1>;
1171 };
1172
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1173 };
1174
1175 slim_qca: slim@62e40000 {
1176 cell-index = <3>;
1177 compatible = "qcom,slim-ngd";
1178 reg = <0x62e40000 0x2c000>,
1179 <0x62e04000 0x20000>;
1180 reg-names = "slimbus_physical", "slimbus_bam_physical";
1181 interrupts = <0 291 0>, <0 292 0>;
1182 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1183 status = "ok";
Dilip Kota0f5974d2017-08-17 15:13:08 +0530[diff] [blame]1184 qcom,iommu-s1-bypass;
1185
1186 iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
1187 compatible = "qcom,iommu-slim-ctrl-cb";
1188 iommus = <&apps_smmu 0x1833 0x0>;
1189 };
1190
Rupesh Tatiya7615f682017-10-11 12:30:20 +0530[diff] [blame]1191 /* Slimbus Slave DT for WCN3990 */
1192 btfmslim_codec: wcn3990 {
1193 compatible = "qcom,btfmslim_slave";
1194 elemental-addr = [00 01 20 02 17 02];
1195 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
1196 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
1197 };
Shrey Vijay6b6b3a52017-06-21 15:06:03 +0530[diff] [blame]1198 };
1199
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1200 wdog: qcom,wdt@17980000{
1201 compatible = "qcom,msm-watchdog";
1202 reg = <0x17980000 0x1000>;
1203 reg-names = "wdt-base";
Lingutla Chandrasekhar9fb9ba92017-10-08 21:59:19 +0530[diff] [blame]1204 interrupts = <0 0 0>, <0 1 0>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1205 qcom,bark-time = <11000>;
Neeraj Upadhyaydbc184d2017-12-07 16:05:39 +0530[diff] [blame]1206 qcom,pet-time = <9360>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1207 qcom,ipi-ping;
1208 qcom,wakeup-enable;
1209 };
1210
1211 qcom,msm-rtb {
1212 compatible = "qcom,msm-rtb";
1213 qcom,rtb-size = <0x100000>;
1214 };
1215
Lingutla Chandrasekhar4d78d722017-11-10 16:03:44 +0530[diff] [blame]1216 qcom,mpm2-sleep-counter@c221000 {
1217 compatible = "qcom,mpm2-sleep-counter";
1218 reg = <0x0c221000 0x1000>;
1219 clock-frequency = <32768>;
1220 };
1221
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1222 qcom,msm-imem@146bf000 {
1223 compatible = "qcom,msm-imem";
1224 reg = <0x146bf000 0x1000>;
1225 ranges = <0x0 0x146bf000 0x1000>;
1226 #address-cells = <1>;
1227 #size-cells = <1>;
1228
1229 mem_dump_table@10 {
1230 compatible = "qcom,msm-imem-mem_dump_table";
1231 reg = <0x10 8>;
1232 };
1233
Lingutla Chandrasekharfa5c13f2017-09-25 11:01:58 +0530[diff] [blame]1234 dload_type@1c {
1235 compatible = "qcom,msm-imem-dload-type";
1236 reg = <0x1c 0x4>;
1237 };
1238
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1239 restart_reason@65c {
1240 compatible = "qcom,msm-imem-restart_reason";
1241 reg = <0x65c 4>;
1242 };
1243
1244 pil@94c {
1245 compatible = "qcom,msm-imem-pil";
1246 reg = <0x94c 200>;
1247 };
1248
1249 kaslr_offset@6d0 {
1250 compatible = "qcom,msm-imem-kaslr_offset";
1251 reg = <0x6d0 12>;
1252 };
Lingutla Chandrasekhar3c51f0b2017-09-12 14:21:21 +0530[diff] [blame]1253
1254 boot_stats@6b0 {
1255 compatible = "qcom,msm-imem-boot_stats";
1256 reg = <0x6b0 0x20>;
1257 };
1258
1259 diag_dload@c8 {
1260 compatible = "qcom,msm-imem-diag-dload";
1261 reg = <0xc8 0xc8>;
1262 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1263 };
1264
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1265 gpi_dma0: qcom,gpi-dma@0x800000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1266 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1267 compatible = "qcom,gpi-dma";
1268 reg = <0x800000 0x60000>;
1269 reg-names = "gpi-top";
1270 interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
1271 <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
1272 <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
1273 <0 256 0>;
1274 qcom,max-num-gpii = <13>;
1275 qcom,gpii-mask = <0xfa>;
1276 qcom,ev-factor = <2>;
1277 iommus = <&apps_smmu 0x0016 0x0>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1278 qcom,smmu-cfg = <0x1>;
1279 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1280 status = "ok";
1281 };
1282
1283 gpi_dma1: qcom,gpi-dma@0xa00000 {
Jishnu Prakashfb619282017-11-06 11:07:53 +0530[diff] [blame]1284 #dma-cells = <5>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1285 compatible = "qcom,gpi-dma";
1286 reg = <0xa00000 0x60000>;
1287 reg-names = "gpi-top";
1288 interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,
1289 <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,
1290 <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>,
1291 <0 299 0>;
1292 qcom,max-num-gpii = <13>;
1293 qcom,gpii-mask = <0xfa>;
1294 qcom,ev-factor = <2>;
Jishnu Prakash71f42792017-11-02 16:04:21 +0530[diff] [blame]1295 qcom,smmu-cfg = <0x1>;
1296 qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
Rama Krishna Phani A2acd96a2017-07-03 17:12:46 +0530[diff] [blame]1297 iommus = <&apps_smmu 0x06d6 0x0>;
1298 status = "ok";
1299 };
1300
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1301 cpuss_dump {
1302 compatible = "qcom,cpuss-dump";
1303 qcom,l1_i_cache0 {
1304 qcom,dump-node = <&L1_I_0>;
1305 qcom,dump-id = <0x60>;
1306 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1307 qcom,l1_i_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1308 qcom,dump-node = <&L1_I_100>;
1309 qcom,dump-id = <0x61>;
1310 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1311 qcom,l1_i_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1312 qcom,dump-node = <&L1_I_200>;
1313 qcom,dump-id = <0x62>;
1314 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1315 qcom,l1_i_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1316 qcom,dump-node = <&L1_I_300>;
1317 qcom,dump-id = <0x63>;
1318 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1319 qcom,l1_i_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1320 qcom,dump-node = <&L1_I_400>;
1321 qcom,dump-id = <0x64>;
1322 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1323 qcom,l1_i_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1324 qcom,dump-node = <&L1_I_500>;
1325 qcom,dump-id = <0x65>;
1326 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1327 qcom,l1_i_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1328 qcom,dump-node = <&L1_I_600>;
1329 qcom,dump-id = <0x66>;
1330 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1331 qcom,l1_i_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1332 qcom,dump-node = <&L1_I_700>;
1333 qcom,dump-id = <0x67>;
1334 };
1335 qcom,l1_d_cache0 {
1336 qcom,dump-node = <&L1_D_0>;
1337 qcom,dump-id = <0x80>;
1338 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1339 qcom,l1_d_cache100 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1340 qcom,dump-node = <&L1_D_100>;
1341 qcom,dump-id = <0x81>;
1342 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1343 qcom,l1_d_cache200 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1344 qcom,dump-node = <&L1_D_200>;
1345 qcom,dump-id = <0x82>;
1346 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1347 qcom,l1_d_cache300 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1348 qcom,dump-node = <&L1_D_300>;
1349 qcom,dump-id = <0x83>;
1350 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1351 qcom,l1_d_cache400 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1352 qcom,dump-node = <&L1_D_400>;
1353 qcom,dump-id = <0x84>;
1354 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1355 qcom,l1_d_cache500 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1356 qcom,dump-node = <&L1_D_500>;
1357 qcom,dump-id = <0x85>;
1358 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1359 qcom,l1_d_cache600 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1360 qcom,dump-node = <&L1_D_600>;
1361 qcom,dump-id = <0x86>;
1362 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1363 qcom,l1_d_cache700 {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1364 qcom,dump-node = <&L1_D_700>;
1365 qcom,dump-id = <0x87>;
1366 };
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1367 qcom,llcc1_d_cache {
1368 qcom,dump-node = <&LLCC_1>;
1369 qcom,dump-id = <0x140>;
1370 };
1371 qcom,llcc2_d_cache {
1372 qcom,dump-node = <&LLCC_2>;
1373 qcom,dump-id = <0x141>;
1374 };
Lingutla Chandrasekhar22792282017-09-01 16:38:20 +0530[diff] [blame]1375 qcom,l1_tlb_dump0 {
1376 qcom,dump-node = <&L1_TLB_0>;
1377 qcom,dump-id = <0x20>;
1378 };
1379 qcom,l1_tlb_dump100 {
1380 qcom,dump-node = <&L1_TLB_100>;
1381 qcom,dump-id = <0x21>;
1382 };
1383 qcom,l1_tlb_dump200 {
1384 qcom,dump-node = <&L1_TLB_200>;
1385 qcom,dump-id = <0x22>;
1386 };
1387 qcom,l1_tlb_dump300 {
1388 qcom,dump-node = <&L1_TLB_300>;
1389 qcom,dump-id = <0x23>;
1390 };
1391 qcom,l1_tlb_dump400 {
1392 qcom,dump-node = <&L1_TLB_400>;
1393 qcom,dump-id = <0x24>;
1394 };
1395 qcom,l1_tlb_dump500 {
1396 qcom,dump-node = <&L1_TLB_500>;
1397 qcom,dump-id = <0x25>;
1398 };
1399 qcom,l1_tlb_dump600 {
1400 qcom,dump-node = <&L1_TLB_600>;
1401 qcom,dump-id = <0x26>;
1402 };
1403 qcom,l1_tlb_dump700 {
1404 qcom,dump-node = <&L1_TLB_700>;
1405 qcom,dump-id = <0x27>;
1406 };
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1407 };
1408
Vishwanath Raju Kb6e9cb22018-05-02 11:56:34 +0530[diff] [blame]1409 mem_dump: mem_dump {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1410 compatible = "qcom,mem-dump";
1411 memory-region = <&dump_mem>;
1412
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1413 rpmh {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1414 qcom,dump-size = <0x2000000>;
1415 qcom,dump-id = <0xec>;
1416 };
1417
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1418 rpm_sw {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1419 qcom,dump-size = <0x28000>;
1420 qcom,dump-id = <0xea>;
1421 };
1422
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1423 pmic {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1424 qcom,dump-size = <0x10000>;
1425 qcom,dump-id = <0xe4>;
1426 };
1427
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1428 tmc_etf {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1429 qcom,dump-size = <0x10000>;
1430 qcom,dump-id = <0xf0>;
1431 };
1432
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1433 tmc_etfswao {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1434 qcom,dump-size = <0x8400>;
1435 qcom,dump-id = <0xf1>;
1436 };
1437
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1438 tmc_etr_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1439 qcom,dump-size = <0x1000>;
1440 qcom,dump-id = <0x100>;
1441 };
1442
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1443 tmc_etf_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1444 qcom,dump-size = <0x1000>;
1445 qcom,dump-id = <0x101>;
1446 };
1447
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1448 etfswao_reg {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1449 qcom,dump-size = <0x1000>;
1450 qcom,dump-id = <0x102>;
1451 };
1452
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1453 misc_data {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1454 qcom,dump-size = <0x1000>;
1455 qcom,dump-id = <0xe8>;
1456 };
1457
Lingutla Chandrasekhar408ca1d2017-11-06 21:48:09 +0530[diff] [blame]1458 power_regs {
Lingutla Chandrasekhar96fd39c2017-09-12 10:34:33 +0530[diff] [blame]1459 qcom,dump-size = <0x100000>;
1460 qcom,dump-id = <0xed>;
1461 };
1462 };
1463
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1464 kryo3xx-erp {
1465 compatible = "arm,arm64-kryo3xx-cpu-erp";
1466 interrupts = <1 6 4>,
1467 <1 7 4>,
1468 <0 34 4>,
1469 <0 35 4>;
1470
1471 interrupt-names = "l1-l2-faultirq",
1472 "l1-l2-errirq",
1473 "l3-scu-errirq",
1474 "l3-scu-faultirq";
1475 };
1476
Dhoat Harpala24cb2c2017-06-06 20:39:54 +0530[diff] [blame]1477 qcom,ipc-spinlock@1f40000 {
1478 compatible = "qcom,ipc-spinlock-sfpb";
1479 reg = <0x1f40000 0x8000>;
1480 qcom,num-locks = <8>;
1481 };
1482
Dhoat Harpaldd9bfaf2017-06-06 20:43:16 +0530[diff] [blame]1483 qcom,smem@86000000 {
1484 compatible = "qcom,smem";
1485 reg = <0x86000000 0x200000>,
1486 <0x17911008 0x4>,
1487 <0x778000 0x7000>,
1488 <0x1fd4000 0x8>;
1489 reg-names = "smem", "irq-reg-base", "aux-mem1",
1490 "smem_targ_info_reg";
1491 qcom,mpu-enabled;
1492 };
1493
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1494 qmp_aop: qcom,qmp-aop@c300000 {
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1495 compatible = "qcom,qmp-mbox";
1496 label = "aop";
1497 reg = <0xc300000 0x100000>,
1498 <0x1799000c 0x4>;
1499 reg-names = "msgram", "irq-reg-base";
1500 qcom,irq-mask = <0x1>;
1501 interrupts = <0 389 1>;
Dhoat Harpalebc9e562017-07-30 20:53:03 +0530[diff] [blame]1502 priority = <0>;
Dhoat Harpal5f909ef2017-06-09 21:18:00 +0530[diff] [blame]1503 mbox-desc-offset = <0x0>;
1504 #mbox-cells = <1>;
1505 };
1506
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1507 qcom,glink-smem-native-xprt-modem@86000000 {
1508 compatible = "qcom,glink-smem-native-xprt";
1509 reg = <0x86000000 0x200000>,
1510 <0x1799000c 0x4>;
1511 reg-names = "smem", "irq-reg-base";
1512 qcom,irq-mask = <0x1000>;
1513 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1514 label = "mpss";
1515 };
1516
1517 qcom,glink-smem-native-xprt-adsp@86000000 {
1518 compatible = "qcom,glink-smem-native-xprt";
1519 reg = <0x86000000 0x200000>,
1520 <0x1799000c 0x4>;
1521 reg-names = "smem", "irq-reg-base";
Dhoat Harpal3adebbe2017-07-06 15:59:13 +0530[diff] [blame]1522 qcom,irq-mask = <0x1000000>;
1523 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
Dhoat Harpal466ffcc2017-06-06 20:54:51 +0530[diff] [blame]1524 label = "lpass";
1525 qcom,qos-config = <&glink_qos_adsp>;
1526 qcom,ramp-time = <0xaf>;
1527 };
1528
1529 glink_qos_adsp: qcom,glink-qos-config-adsp {
1530 compatible = "qcom,glink-qos-config";
1531 qcom,flow-info = <0x3c 0x0>,
1532 <0x3c 0x0>,
1533 <0x3c 0x0>,
1534 <0x3c 0x0>;
1535 qcom,mtu-size = <0x800>;
1536 qcom,tput-stats-cycle = <0xa>;
1537 };
1538
1539 glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1540 compatible = "qcom,glink-spi-xprt";
1541 label = "wdsp";
1542 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1543 qcom,qos-config = <&glink_qos_wdsp>;
1544 qcom,ramp-time = <0x10>,
1545 <0x20>,
1546 <0x30>,
1547 <0x40>;
1548 };
1549
1550 glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1551 compatible = "qcom,glink-fifo-config";
1552 qcom,out-read-idx-reg = <0x12000>;
1553 qcom,out-write-idx-reg = <0x12004>;
1554 qcom,in-read-idx-reg = <0x1200C>;
1555 qcom,in-write-idx-reg = <0x12010>;
1556 };
1557
1558 glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1559 compatible = "qcom,glink-qos-config";
1560 qcom,flow-info = <0x80 0x0>,
1561 <0x70 0x1>,
1562 <0x60 0x2>,
1563 <0x50 0x3>;
1564 qcom,mtu-size = <0x800>;
1565 qcom,tput-stats-cycle = <0xa>;
1566 };
1567
1568 qcom,glink-smem-native-xprt-cdsp@86000000 {
1569 compatible = "qcom,glink-smem-native-xprt";
1570 reg = <0x86000000 0x200000>,
1571 <0x1799000c 0x4>;
1572 reg-names = "smem", "irq-reg-base";
1573 qcom,irq-mask = <0x10>;
1574 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1575 label = "cdsp";
1576 };
1577
Dhoat Harpal9cb73cc2017-06-06 20:58:14 +0530[diff] [blame]1578 glink_mpss: qcom,glink-ssr-modem {
1579 compatible = "qcom,glink_ssr";
1580 label = "modem";
1581 qcom,edge = "mpss";
1582 qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>;
1583 qcom,xprt = "smem";
1584 };
1585
1586 glink_lpass: qcom,glink-ssr-adsp {
1587 compatible = "qcom,glink_ssr";
1588 label = "adsp";
1589 qcom,edge = "lpass";
1590 qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>;
1591 qcom,xprt = "smem";
1592 };
1593
1594 glink_cdsp: qcom,glink-ssr-cdsp {
1595 compatible = "qcom,glink_ssr";
1596 label = "cdsp";
1597 qcom,edge = "cdsp";
1598 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>;
1599 qcom,xprt = "smem";
1600 };
1601
Dhoat Harpal22dafa92017-06-06 21:03:34 +0530[diff] [blame]1602 qcom,ipc_router {
1603 compatible = "qcom,ipc_router";
1604 qcom,node-id = <1>;
1605 };
1606
1607 qcom,ipc_router_modem_xprt {
1608 compatible = "qcom,ipc_router_glink_xprt";
1609 qcom,ch-name = "IPCRTR";
1610 qcom,xprt-remote = "mpss";
1611 qcom,glink-xprt = "smem";
1612 qcom,xprt-linkid = <1>;
1613 qcom,xprt-version = <1>;
1614 qcom,fragmented-data;
1615 };
1616
1617 qcom,ipc_router_q6_xprt {
1618 compatible = "qcom,ipc_router_glink_xprt";
1619 qcom,ch-name = "IPCRTR";
1620 qcom,xprt-remote = "lpass";
1621 qcom,glink-xprt = "smem";
1622 qcom,xprt-linkid = <1>;
1623 qcom,xprt-version = <1>;
1624 qcom,fragmented-data;
1625 };
1626
1627 qcom,ipc_router_cdsp_xprt {
1628 compatible = "qcom,ipc_router_glink_xprt";
1629 qcom,ch-name = "IPCRTR";
1630 qcom,xprt-remote = "cdsp";
1631 qcom,glink-xprt = "smem";
1632 qcom,xprt-linkid = <1>;
1633 qcom,xprt-version = <1>;
1634 qcom,fragmented-data;
1635 };
1636
Dhoat Harpal11d34482017-06-06 21:00:14 +0530[diff] [blame]1637 qcom,glink_pkt {
1638 compatible = "qcom,glinkpkt";
1639
1640 qcom,glinkpkt-at-mdm0 {
1641 qcom,glinkpkt-transport = "smem";
1642 qcom,glinkpkt-edge = "mpss";
1643 qcom,glinkpkt-ch-name = "DS";
1644 qcom,glinkpkt-dev-name = "at_mdm0";
1645 };
1646
1647 qcom,glinkpkt-loopback_cntl {
1648 qcom,glinkpkt-transport = "lloop";
1649 qcom,glinkpkt-edge = "local";
1650 qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1651 qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1652 };
1653
1654 qcom,glinkpkt-loopback_data {
1655 qcom,glinkpkt-transport = "lloop";
1656 qcom,glinkpkt-edge = "local";
1657 qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1658 qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1659 };
1660
1661 qcom,glinkpkt-apr-apps2 {
1662 qcom,glinkpkt-transport = "smem";
1663 qcom,glinkpkt-edge = "adsp";
1664 qcom,glinkpkt-ch-name = "apr_apps2";
1665 qcom,glinkpkt-dev-name = "apr_apps2";
1666 };
1667
1668 qcom,glinkpkt-data40-cntl {
1669 qcom,glinkpkt-transport = "smem";
1670 qcom,glinkpkt-edge = "mpss";
1671 qcom,glinkpkt-ch-name = "DATA40_CNTL";
1672 qcom,glinkpkt-dev-name = "smdcntl8";
1673 };
1674
1675 qcom,glinkpkt-data1 {
1676 qcom,glinkpkt-transport = "smem";
1677 qcom,glinkpkt-edge = "mpss";
1678 qcom,glinkpkt-ch-name = "DATA1";
1679 qcom,glinkpkt-dev-name = "smd7";
1680 };
1681
1682 qcom,glinkpkt-data4 {
1683 qcom,glinkpkt-transport = "smem";
1684 qcom,glinkpkt-edge = "mpss";
1685 qcom,glinkpkt-ch-name = "DATA4";
1686 qcom,glinkpkt-dev-name = "smd8";
1687 };
1688
1689 qcom,glinkpkt-data11 {
1690 qcom,glinkpkt-transport = "smem";
1691 qcom,glinkpkt-edge = "mpss";
1692 qcom,glinkpkt-ch-name = "DATA11";
1693 qcom,glinkpkt-dev-name = "smd11";
1694 };
1695 };
1696
Gaurav Kohlid1131902018-02-21 13:21:25 +0530[diff] [blame]1697 qcom,chd_silver {
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1698 compatible = "qcom,core-hang-detect";
1699 label = "silver";
1700 qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
1701 0x17e30058 0x17e40058 0x17e50058>;
1702 qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
1703 0x17e30060 0x17e40060 0x17e50060>;
1704 };
1705
1706 qcom,chd_gold {
1707 compatible = "qcom,core-hang-detect";
1708 label = "gold";
1709 qcom,threshold-arr = <0x17e60058 0x17e70058>;
1710 qcom,config-arr = <0x17e60060 0x17e70060>;
1711 };
1712
1713 qcom,ghd {
1714 compatible = "qcom,gladiator-hang-detect-v2";
1715 qcom,threshold-arr = <0x1799041c 0x17990420>;
1716 qcom,config-reg = <0x17990434>;
1717 };
1718
1719 qcom,msm-gladiator-v3@17900000 {
1720 compatible = "qcom,msm-gladiator-v3";
1721 reg = <0x17900000 0xd080>;
1722 reg-names = "gladiator_base";
1723 interrupts = <0 17 0>;
1724 };
1725
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1726 eud: qcom,msm-eud@88e0000 {
1727 compatible = "qcom,msm-eud";
1728 interrupt-names = "eud_irq";
1729 interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
1730 reg = <0x88e0000 0x2000>;
1731 reg-names = "eud_base";
Lingutla Chandrasekhar5422daf2017-10-26 11:27:32 +0530[diff] [blame]1732 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1733 clock-names = "cfg_ahb_clk";
Lingutla Chandrasekhar88f9e7b2017-09-15 18:29:25 +0530[diff] [blame]1734 };
1735
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1736 qcom,llcc@1100000 {
1737 compatible = "qcom,llcc-core", "syscon", "simple-mfd";
1738 reg = <0x1100000 0x250000>;
1739 reg-names = "llcc_base";
1740 qcom,llcc-banks-off = <0x0 0x80000 >;
1741 qcom,llcc-broadcast-off = <0x200000>;
1742
1743 llcc: qcom,sdm670-llcc {
1744 compatible = "qcom,sdm670-llcc";
1745 #cache-cells = <1>;
1746 max-slices = <32>;
1747 qcom,dump-size = <0x80000>;
1748 };
1749
Sankaran Nampoothiri0c5dac02017-11-06 11:53:52 +0530[diff] [blame]1750 qcom,llcc-perfmon {
1751 compatible = "qcom,llcc-perfmon";
1752 };
1753
Lingutla Chandrasekharee4f1872017-06-07 13:50:53 +0530[diff] [blame]1754 qcom,llcc-erp {
1755 compatible = "qcom,llcc-erp";
1756 interrupt-names = "ecc_irq";
1757 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1758 };
1759
1760 qcom,llcc-amon {
1761 compatible = "qcom,llcc-amon";
1762 };
1763
1764 LLCC_1: llcc_1_dcache {
1765 qcom,dump-size = <0xd8000>;
1766 };
1767
1768 LLCC_2: llcc_2_dcache {
1769 qcom,dump-size = <0xd8000>;
1770 };
1771 };
1772
Maulik Shah210773d2017-06-15 09:49:12 +0530[diff] [blame]1773 cmd_db: qcom,cmd-db@c3f000c {
1774 compatible = "qcom,cmd-db";
1775 reg = <0xc3f000c 0x8>;
1776 };
1777
Maulik Shahc77d1d22017-06-15 14:04:50 +0530[diff] [blame]1778 apps_rsc: mailbox@179e0000 {
1779 compatible = "qcom,tcs-drv";
1780 label = "apps_rsc";
1781 reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
1782 interrupts = <0 5 0>;
1783 #mbox-cells = <1>;
1784 qcom,drv-id = <2>;
1785 qcom,tcs-config = <ACTIVE_TCS 2>,
1786 <SLEEP_TCS 3>,
1787 <WAKE_TCS 3>,
1788 <CONTROL_TCS 1>;
1789 };
1790
Maulik Shahda3941f2017-06-15 09:41:38 +0530[diff] [blame]1791 disp_rsc: mailbox@af20000 {
1792 compatible = "qcom,tcs-drv";
1793 label = "display_rsc";
1794 reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
1795 interrupts = <0 129 0>;
1796 #mbox-cells = <1>;
1797 qcom,drv-id = <0>;
1798 qcom,tcs-config = <SLEEP_TCS 1>,
1799 <WAKE_TCS 1>,
1800 <ACTIVE_TCS 0>,
1801 <CONTROL_TCS 1>;
1802 };
1803
Maulik Shah0dd203f2017-06-15 09:44:59 +0530[diff] [blame]1804 system_pm {
1805 compatible = "qcom,system-pm";
1806 mboxes = <&apps_rsc 0>;
1807 };
1808
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1809 dcc: dcc_v2@10a2000 {
Mao Jinlong1d656f92018-04-09 16:09:44 +0800[diff] [blame]1810 compatible = "qcom,dcc-v2";
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1811 reg = <0x10a2000 0x1000>,
1812 <0x10ae000 0x2000>;
1813 reg-names = "dcc-base", "dcc-ram-base";
Saranya Chidurac0a161c2017-08-28 13:06:10 +0530[diff] [blame]1814
1815 dcc-ram-offset = <0x6000>;
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]1816 };
1817
Tirupathi Reddy9ae4c892017-06-09 12:30:31 +0530[diff] [blame]1818 spmi_bus: qcom,spmi@c440000 {
1819 compatible = "qcom,spmi-pmic-arb";
1820 reg = <0xc440000 0x1100>,
1821 <0xc600000 0x2000000>,
1822 <0xe600000 0x100000>,
1823 <0xe700000 0xa0000>,
1824 <0xc40a000 0x26000>;
1825 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1826 interrupt-names = "periph_irq";
1827 interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
1828 qcom,ee = <0>;
1829 qcom,channel = <0>;
1830 #address-cells = <2>;
1831 #size-cells = <0>;
1832 interrupt-controller;
1833 #interrupt-cells = <4>;
1834 cell-index = <0>;
1835 };
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1836
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1837 ufs_ice: ufsice@1d90000 {
1838 compatible = "qcom,ice";
1839 reg = <0x1d90000 0x8000>;
1840 qcom,enable-ice-clk;
1841 clock-names = "ufs_core_clk", "bus_clk",
1842 "iface_clk", "ice_core_clk";
1843 clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
1844 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1845 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1846 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1847 qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
1848 vdd-hba-supply = <&ufs_phy_gdsc>;
1849 qcom,msm-bus,name = "ufs_ice_noc";
1850 qcom,msm-bus,num-cases = <2>;
1851 qcom,msm-bus,num-paths = <1>;
1852 qcom,msm-bus,vectors-KBps =
1853 <1 650 0 0>, /* No vote */
1854 <1 650 1000 0>; /* Max. bandwidth */
1855 qcom,bus-vector-names = "MIN",
1856 "MAX";
1857 qcom,instance-type = "ufs";
1858 };
1859
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1860 ufsphy_mem: ufsphy_mem@1d87000 {
1861 reg = <0x1d87000 0xe00>; /* PHY regs */
1862 reg-names = "phy_mem";
1863 #phy-cells = <0>;
1864
1865 lanes-per-direction = <1>;
1866
1867 clock-names = "ref_clk_src",
1868 "ref_clk",
1869 "ref_aux_clk";
1870 clocks = <&clock_rpmh RPMH_CXO_CLK>,
1871 <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
1872 <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
1873
1874 status = "disabled";
1875 };
1876
1877 ufshc_mem: ufshc@1d84000 {
1878 compatible = "qcom,ufshc";
1879 reg = <0x1d84000 0x3000>;
1880 interrupts = <0 265 0>;
1881 phys = <&ufsphy_mem>;
1882 phy-names = "ufsphy";
Neeraj Soni3c041f12018-01-19 16:45:44 +0530[diff] [blame]1883 ufs-qcom-crypto = <&ufs_ice>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1884
1885 lanes-per-direction = <1>;
Sayali Lokhande1e49f022018-09-07 12:24:43 +0530[diff] [blame]1886 spm-level = <5>;
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1887 dev-ref-clk-freq = <0>; /* 19.2 MHz */
1888
1889 clock-names =
1890 "core_clk",
1891 "bus_aggr_clk",
1892 "iface_clk",
1893 "core_clk_unipro",
1894 "core_clk_ice",
1895 "ref_clk",
1896 "tx_lane0_sync_clk",
1897 "rx_lane0_sync_clk";
1898 clocks =
1899 <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]1900 <&clock_gcc UFS_PHY_AXI_UFS_VOTE_CLK>,
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1901 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
1902 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
1903 <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
1904 <&clock_rpmh RPMH_CXO_CLK>,
1905 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1906 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1907 freq-table-hz =
1908 <50000000 200000000>,
1909 <0 0>,
1910 <0 0>,
1911 <37500000 150000000>,
1912 <75000000 300000000>,
1913 <0 0>,
1914 <0 0>,
1915 <0 0>;
1916
Sayali Lokhandeaa3db742017-10-09 15:13:01 +0530[diff] [blame]1917 non-removable;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1918 qcom,msm-bus,name = "ufshc_mem";
1919 qcom,msm-bus,num-cases = <12>;
1920 qcom,msm-bus,num-paths = <2>;
1921 qcom,msm-bus,vectors-KBps =
1922 /*
1923 * During HS G3 UFS runs at nominal voltage corner, vote
1924 * higher bandwidth to push other buses in the data path
1925 * to run at nominal to achieve max throughput.
1926 * 4GBps pushes BIMC to run at nominal.
1927 * 200MBps pushes CNOC to run at nominal.
1928 * Vote for half of this bandwidth for HS G3 1-lane.
1929 * For max bandwidth, vote high enough to push the buses
1930 * to run in turbo voltage corner.
1931 */
1932 <123 512 0 0>, <1 757 0 0>, /* No vote */
1933 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
1934 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
1935 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
1936 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
1937 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
1938 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
1939 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
1940 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
1941 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
1942 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
1943 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
1944
1945 qcom,bus-vector-names = "MIN",
1946 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1947 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1948 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1949 "MAX";
1950
1951 /* PM QoS */
1952 qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]1953 qcom,pm-qos-cpu-group-latency-us = <67 67>;
Sayali Lokhande9ad47f02017-08-02 12:44:31 +0530[diff] [blame]1954 qcom,pm-qos-default-cpu = <0>;
1955
Sayali Lokhandebd53f6a2018-04-05 16:32:08 +0530[diff] [blame]1956 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
1957 pinctrl-0 = <&ufs_dev_reset_assert>;
1958 pinctrl-1 = <&ufs_dev_reset_deassert>;
1959
Sayali Lokhande099af9c2017-06-08 10:18:29 +0530[diff] [blame]1960 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
1961 reset-names = "core_reset";
1962
1963 status = "disabled";
1964 };
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1965
1966 qcom,lpass@62400000 {
1967 compatible = "qcom,pil-tz-generic";
1968 reg = <0x62400000 0x00100>;
1969 interrupts = <0 162 1>;
1970
1971 vdd_cx-supply = <&pm660l_l9_level>;
1972 qcom,proxy-reg-names = "vdd_cx";
1973 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
1974
1975 clocks = <&clock_rpmh RPMH_CXO_CLK>;
1976 clock-names = "xo";
1977 qcom,proxy-clock-names = "xo";
1978
1979 qcom,pas-id = <1>;
1980 qcom,proxy-timeout-ms = <10000>;
1981 qcom,smem-id = <423>;
1982 qcom,sysmon-id = <1>;
1983 qcom,ssctl-instance-id = <0x14>;
1984 qcom,firmware-name = "adsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1985 qcom,signal-aop;
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1986 memory-region = <&pil_adsp_mem>;
1987
1988 /* GPIO inputs from lpass */
1989 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
1990 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
1991 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
1992 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
1993
1994 /* GPIO output to lpass */
1995 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]1996
1997 mboxes = <&qmp_aop 0>;
1998 mbox-names = "adsp-pil";
Gaurav Kohlib28d5562017-06-12 11:26:27 +0530[diff] [blame]1999 status = "ok";
2000 };
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2001
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]2002 qcom,rmtfs_sharedmem@0 {
2003 compatible = "qcom,sharedmem-uio";
2004 reg = <0x0 0x200000>;
2005 reg-names = "rmtfs";
2006 qcom,client-id = <0x00000001>;
Sahitya Tummala57f7b572017-10-23 10:29:03 +0530[diff] [blame]2007 qcom,guard-memory;
Sahitya Tummala02e49182017-09-19 10:54:42 +0530[diff] [blame]2008 };
2009
Mohammed Javidf97a10e2017-10-08 13:11:26 +0530[diff] [blame]2010 qcom,msm_gsi {
2011 compatible = "qcom,msm_gsi";
2012 };
2013
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2014 qcom,rmnet-ipa {
2015 compatible = "qcom,rmnet-ipa3";
2016 qcom,rmnet-ipa-ssr;
2017 qcom,ipa-loaduC;
2018 qcom,ipa-advertise-sg-support;
2019 qcom,ipa-napi-enable;
2020 };
2021
2022 ipa_hw: qcom,ipa@01e00000 {
2023 compatible = "qcom,ipa";
2024 reg = <0x1e00000 0x34000>,
2025 <0x1e04000 0x2c000>;
2026 reg-names = "ipa-base", "gsi-base";
2027 interrupts =
2028 <0 311 0>,
2029 <0 432 0>;
2030 interrupt-names = "ipa-irq", "gsi-irq";
2031 qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
Mohammed Javiddcefa282018-04-10 17:22:30 +0530[diff] [blame]2032 qcom,ipa-hw-mode = <0>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2033 qcom,ee = <0>;
2034 qcom,use-ipa-tethering-bridge;
2035 qcom,modem-cfg-emb-pipe-flt;
2036 qcom,ipa-wdi2;
2037 qcom,use-64-bit-dma-mask;
2038 qcom,arm-smmu;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2039 qcom,bandwidth-vote-for-ipa;
2040 qcom,msm-bus,name = "ipa";
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2041 qcom,msm-bus,num-cases = <5>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2042 qcom,msm-bus,num-paths = <4>;
2043 qcom,msm-bus,vectors-KBps =
2044 /* No vote */
2045 <90 512 0 0>,
2046 <90 585 0 0>,
2047 <1 676 0 0>,
2048 <143 777 0 0>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2049 /* SVS2 */
2050 <90 512 80000 600000>,
2051 <90 585 80000 350000>,
2052 <1 676 40000 40000>, /*gcc_config_noc_clk_src */
2053 <143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2054 /* SVS */
2055 <90 512 80000 640000>,
2056 <90 585 80000 640000>,
2057 <1 676 80000 80000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2058 <143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2059 /* NOMINAL */
2060 <90 512 206000 960000>,
2061 <90 585 206000 960000>,
2062 <1 676 206000 160000>,
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2063 <143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2064 /* TURBO */
2065 <90 512 206000 3600000>,
2066 <90 585 206000 3600000>,
2067 <1 676 206000 300000>,
Mohammed Javid6c065482017-09-19 19:19:27 +0530[diff] [blame]2068 <143 777 0 355>; /* IB defined for IPA clk in MHz*/
Mohammed Javid963acd02018-01-17 12:59:40 +0530[diff] [blame]2069 qcom,bus-vector-names =
2070 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2071
2072 /* IPA RAM mmap */
2073 qcom,ipa-ram-mmap = <
2074 0x280 /* ofst_start; */
2075 0x0 /* nat_ofst; */
2076 0x0 /* nat_size; */
2077 0x288 /* v4_flt_hash_ofst; */
2078 0x78 /* v4_flt_hash_size; */
2079 0x4000 /* v4_flt_hash_size_ddr; */
2080 0x308 /* v4_flt_nhash_ofst; */
2081 0x78 /* v4_flt_nhash_size; */
2082 0x4000 /* v4_flt_nhash_size_ddr; */
2083 0x388 /* v6_flt_hash_ofst; */
2084 0x78 /* v6_flt_hash_size; */
2085 0x4000 /* v6_flt_hash_size_ddr; */
2086 0x408 /* v6_flt_nhash_ofst; */
2087 0x78 /* v6_flt_nhash_size; */
2088 0x4000 /* v6_flt_nhash_size_ddr; */
2089 0xf /* v4_rt_num_index; */
2090 0x0 /* v4_modem_rt_index_lo; */
2091 0x7 /* v4_modem_rt_index_hi; */
2092 0x8 /* v4_apps_rt_index_lo; */
2093 0xe /* v4_apps_rt_index_hi; */
2094 0x488 /* v4_rt_hash_ofst; */
2095 0x78 /* v4_rt_hash_size; */
2096 0x4000 /* v4_rt_hash_size_ddr; */
2097 0x508 /* v4_rt_nhash_ofst; */
2098 0x78 /* v4_rt_nhash_size; */
2099 0x4000 /* v4_rt_nhash_size_ddr; */
2100 0xf /* v6_rt_num_index; */
2101 0x0 /* v6_modem_rt_index_lo; */
2102 0x7 /* v6_modem_rt_index_hi; */
2103 0x8 /* v6_apps_rt_index_lo; */
2104 0xe /* v6_apps_rt_index_hi; */
2105 0x588 /* v6_rt_hash_ofst; */
2106 0x78 /* v6_rt_hash_size; */
2107 0x4000 /* v6_rt_hash_size_ddr; */
2108 0x608 /* v6_rt_nhash_ofst; */
2109 0x78 /* v6_rt_nhash_size; */
2110 0x4000 /* v6_rt_nhash_size_ddr; */
2111 0x688 /* modem_hdr_ofst; */
2112 0x140 /* modem_hdr_size; */
2113 0x7c8 /* apps_hdr_ofst; */
2114 0x0 /* apps_hdr_size; */
2115 0x800 /* apps_hdr_size_ddr; */
2116 0x7d0 /* modem_hdr_proc_ctx_ofst; */
2117 0x200 /* modem_hdr_proc_ctx_size; */
2118 0x9d0 /* apps_hdr_proc_ctx_ofst; */
2119 0x200 /* apps_hdr_proc_ctx_size; */
2120 0x0 /* apps_hdr_proc_ctx_size_ddr; */
2121 0x0 /* modem_comp_decomp_ofst; diff */
2122 0x0 /* modem_comp_decomp_size; diff */
2123 0xbd8 /* modem_ofst; */
2124 0x1024 /* modem_size; */
2125 0x2000 /* apps_v4_flt_hash_ofst; */
2126 0x0 /* apps_v4_flt_hash_size; */
2127 0x2000 /* apps_v4_flt_nhash_ofst; */
2128 0x0 /* apps_v4_flt_nhash_size; */
2129 0x2000 /* apps_v6_flt_hash_ofst; */
2130 0x0 /* apps_v6_flt_hash_size; */
2131 0x2000 /* apps_v6_flt_nhash_ofst; */
2132 0x0 /* apps_v6_flt_nhash_size; */
2133 0x80 /* uc_info_ofst; */
2134 0x200 /* uc_info_size; */
2135 0x2000 /* end_ofst; */
2136 0x2000 /* apps_v4_rt_hash_ofst; */
2137 0x0 /* apps_v4_rt_hash_size; */
2138 0x2000 /* apps_v4_rt_nhash_ofst; */
2139 0x0 /* apps_v4_rt_nhash_size; */
2140 0x2000 /* apps_v6_rt_hash_ofst; */
2141 0x0 /* apps_v6_rt_hash_size; */
2142 0x2000 /* apps_v6_rt_nhash_ofst; */
2143 0x0 /* apps_v6_rt_nhash_size; */
2144 0x1c00 /* uc_event_ring_ofst; */
2145 0x400 /* uc_event_ring_size; */
2146 >;
2147
2148 /* smp2p gpio information */
2149 qcom,smp2pgpio_map_ipa_1_out {
2150 compatible = "qcom,smp2pgpio-map-ipa-1-out";
2151 gpios = <&smp2pgpio_ipa_1_out 0 0>;
2152 };
2153
2154 qcom,smp2pgpio_map_ipa_1_in {
2155 compatible = "qcom,smp2pgpio-map-ipa-1-in";
2156 gpios = <&smp2pgpio_ipa_1_in 0 0>;
2157 };
2158
2159 ipa_smmu_ap: ipa_smmu_ap {
2160 compatible = "qcom,ipa-smmu-ap-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2161 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2162 iommus = <&apps_smmu 0x720 0x0>;
2163 qcom,iova-mapping = <0x20000000 0x40000000>;
2164 };
2165
2166 ipa_smmu_wlan: ipa_smmu_wlan {
2167 compatible = "qcom,ipa-smmu-wlan-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2168 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2169 iommus = <&apps_smmu 0x721 0x0>;
2170 };
2171
2172 ipa_smmu_uc: ipa_smmu_uc {
2173 compatible = "qcom,ipa-smmu-uc-cb";
Mohammed Javidcc505a62017-10-25 11:36:02 +0530[diff] [blame]2174 qcom,smmu-s1-bypass;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2175 iommus = <&apps_smmu 0x722 0x0>;
2176 qcom,iova-mapping = <0x40000000 0x20000000>;
2177 };
2178 };
2179
2180 qcom,ipa_fws {
2181 compatible = "qcom,pil-tz-generic";
2182 qcom,pas-id = <0xf>;
2183 qcom,firmware-name = "ipa_fws";
Mohammed Javid42445cb2018-02-01 18:22:17 +0530[diff] [blame]2184 qcom,pil-force-shutdown;
Mohammed Javide0dd2a32018-01-25 14:18:56 +0530[diff] [blame]2185 memory-region = <&pil_ipa_fw_mem>;
Mohammed Javid736c25c2017-06-19 13:23:18 +0530[diff] [blame]2186 };
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2187
2188 pil_modem: qcom,mss@4080000 {
2189 compatible = "qcom,pil-q6v55-mss";
2190 reg = <0x4080000 0x100>,
2191 <0x1f63000 0x008>,
2192 <0x1f65000 0x008>,
2193 <0x1f64000 0x008>,
2194 <0x4180000 0x020>,
2195 <0xc2b0000 0x004>,
2196 <0xb2e0100 0x004>,
2197 <0x4180044 0x004>;
2198 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2199 "halt_nc", "rmb_base", "restart_reg",
2200 "pdc_sync", "alt_reset";
2201
2202 clocks = <&clock_rpmh RPMH_CXO_CLK>,
2203 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2204 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2205 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2206 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2207 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2208 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
2209 <&clock_gcc GCC_PRNG_AHB_CLK>;
2210 clock-names = "xo", "iface_clk", "bus_clk",
2211 "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2212 "mnoc_axi_clk", "prng_clk";
2213 qcom,proxy-clock-names = "xo", "prng_clk";
2214 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2215 "gpll0_mss_clk", "snoc_axi_clk",
2216 "mnoc_axi_clk";
2217
2218 interrupts = <0 266 1>;
2219 vdd_cx-supply = <&pm660l_s3_level>;
2220 vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
2221 vdd_mx-supply = <&pm660l_s1_level>;
2222 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Jitendra Sharma2e981ef2017-10-30 12:16:23 +0530[diff] [blame]2223 vdd_mss-supply = <&pm660_s5_level>;
2224 vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2225 qcom,firmware-name = "modem";
2226 qcom,pil-self-auth;
2227 qcom,sysmon-id = <0>;
Avaneesh Kumar Dwivedi8d336612017-11-09 16:48:25 +0530[diff] [blame]2228 qcom,minidump-id = <3>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2229 qcom,ssctl-instance-id = <0x12>;
2230 qcom,override-acc;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2231 qcom,signal-aop;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2232 qcom,qdsp6v65-1-0;
Jitendra Sharma93dd7fc2017-10-14 17:38:55 +0530[diff] [blame]2233 qcom,mss_pdc_offset = <9>;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2234 status = "ok";
2235 memory-region = <&pil_modem_mem>;
2236 qcom,mem-protect-id = <0xF>;
Shadab Naseem60b870a2018-05-11 14:31:03 +0530[diff] [blame]2237 qcom,complete-ramdump;
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2238
2239 /* GPIO inputs from mss */
2240 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2241 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2242 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2243 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2244 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2245
2246 /* GPIO output to mss */
2247 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2248
2249 mboxes = <&qmp_aop 0>;
2250 mbox-names = "mss-pil";
Gaurav Kohli04a55af2017-07-19 17:25:30 +0530[diff] [blame]2251 qcom,mba-mem@0 {
2252 compatible = "qcom,pil-mba-mem";
2253 memory-region = <&pil_mba_mem>;
2254 };
2255 };
Gaurav Kohli985a99d2017-07-25 18:46:45 +0530[diff] [blame]2256
2257 qcom,venus@aae0000 {
2258 compatible = "qcom,pil-tz-generic";
2259 reg = <0xaae0000 0x4000>;
2260
2261 vdd-supply = <&venus_gdsc>;
2262 qcom,proxy-reg-names = "vdd";
2263
2264 clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2265 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
2266 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2267 clock-names = "core_clk", "iface_clk", "bus_clk";
2268 qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";
2269
2270 qcom,pas-id = <9>;
2271 qcom,msm-bus,name = "pil-venus";
2272 qcom,msm-bus,num-cases = <2>;
2273 qcom,msm-bus,num-paths = <1>;
2274 qcom,msm-bus,vectors-KBps =
2275 <63 512 0 0>,
2276 <63 512 0 304000>;
2277 qcom,proxy-timeout-ms = <100>;
2278 qcom,firmware-name = "venus";
2279 memory-region = <&pil_video_mem>;
2280 status = "ok";
2281 };
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2282
2283 qcom,turing@8300000 {
2284 compatible = "qcom,pil-tz-generic";
2285 reg = <0x8300000 0x100000>;
2286 interrupts = <0 578 1>;
2287
2288 vdd_cx-supply = <&pm660l_s3_level>;
2289 qcom,proxy-reg-names = "vdd_cx";
2290 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2291
2292 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2293 clock-names = "xo";
2294 qcom,proxy-clock-names = "xo";
2295
2296 qcom,pas-id = <18>;
2297 qcom,proxy-timeout-ms = <10000>;
2298 qcom,smem-id = <601>;
2299 qcom,sysmon-id = <7>;
2300 qcom,ssctl-instance-id = <0x17>;
2301 qcom,firmware-name = "cdsp";
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2302 qcom,signal-aop;
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2303 memory-region = <&pil_cdsp_mem>;
2304
2305 /* GPIO inputs from turing */
2306 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2307 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2308 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2309 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2310
2311 /* GPIO output to turing*/
2312 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
Gaurav Kohlif11f7cc2017-10-03 14:37:48 +0530[diff] [blame]2313
2314 mboxes = <&qmp_aop 0>;
2315 mbox-names = "cdsp-pil";
Gaurav Kohli106f4882017-06-29 12:29:12 +0530[diff] [blame]2316 status = "ok";
2317 };
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2318
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2319 sdcc1_ice: sdcc1ice@7c8000 {
2320 compatible = "qcom,ice";
2321 reg = <0x7c8000 0x8000>;
2322 qcom,enable-ice-clk;
2323 clock-names = "ice_core_clk_src", "ice_core_clk",
2324 "bus_clk", "iface_clk";
2325 clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
2326 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
2327 <&clock_gcc GCC_SDCC1_APPS_CLK>,
2328 <&clock_gcc GCC_SDCC1_AHB_CLK>;
2329 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
2330 qcom,msm-bus,name = "sdcc_ice_noc";
2331 qcom,msm-bus,num-cases = <2>;
2332 qcom,msm-bus,num-paths = <1>;
2333 qcom,msm-bus,vectors-KBps =
2334 <150 512 0 0>, /* No vote */
2335 <150 512 1000 0>; /* Max. bandwidth */
2336 qcom,bus-vector-names = "MIN",
2337 "MAX";
2338 qcom,instance-type = "sdcc";
2339 };
2340
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2341 sdhc_1: sdhci@7c4000 {
2342 compatible = "qcom,sdhci-msm-v5";
2343 reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
2344 reg-names = "hc_mem", "cmdq_mem";
2345
2346 interrupts = <0 641 0>, <0 644 0>;
2347 interrupt-names = "hc_irq", "pwr_irq";
2348
2349 qcom,bus-width = <8>;
2350 qcom,large-address-bus;
Neeraj Soni27efd652017-11-01 18:17:58 +0530[diff] [blame]2351 sdhc-msm-crypto = <&sdcc1_ice>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2352
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2353 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2354 192000000 384000000>;
Vijay Viswanath01db23a2017-11-09 15:46:22 +0530[diff] [blame]2355 qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
2356 100000000 200000000 200000000>;
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2357 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2358
2359 qcom,devfreq,freq-table = <50000000 200000000>;
2360
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2361 qcom,msm-bus,name = "sdhc1";
2362 qcom,msm-bus,num-cases = <9>;
2363 qcom,msm-bus,num-paths = <2>;
2364 qcom,msm-bus,vectors-KBps =
2365 /* No vote */
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2366 <150 512 0 0>, <1 782 0 0>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2367 /* 400 KB/s*/
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2368 <150 512 1046 1600>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2369 <1 782 1600 1600>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2370 /* 20 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2371 <150 512 52286 80000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2372 <1 782 80000 80000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2373 /* 25 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2374 <150 512 65360 100000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2375 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2376 /* 50 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2377 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2378 <1 782 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2379 /* 100 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2380 <150 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2381 <1 782 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2382 /* 200 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2383 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2384 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2385 /* 400 MB/s */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2386 <150 512 261438 400000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2387 <1 782 300000 300000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2388 /* Max. bandwidth */
Vijay Viswanath413e5f42017-10-09 10:50:46 +0530[diff] [blame]2389 <150 512 1338562 4096000>,
Vijay Viswanath49024c22017-10-17 12:42:06 +0530[diff] [blame]2390 <1 782 1338562 4096000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2391 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2392 100000000 200000000 400000000 4294967295>;
2393
2394 /* PM QoS */
2395 qcom,pm-qos-irq-type = "affine_irq";
Vijay Viswanathcac6f862018-03-20 11:40:54 +0530[diff] [blame]2396 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2397 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2398 qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
2399 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2400
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2401 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2402 <&clock_gcc GCC_SDCC1_APPS_CLK>,
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2403 <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
Veerabhadrarao Badiganti0161cd72018-05-14 15:02:02 +0530[diff] [blame]2404 <&clock_gcc UFS_PHY_AXI_EMMC_VOTE_CLK>;
Vijay Viswanath7e20ddc2017-10-07 14:23:38 +0530[diff] [blame]2405 clock-names = "iface_clk", "core_clk", "ice_core_clk",
2406 "bus_aggr_clk";
Vijay Viswanathcebae3a2017-10-05 14:33:17 +0530[diff] [blame]2407
2408 qcom,ice-clk-rates = <300000000 75000000>;
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2409
Vijay Viswanathd4dcf5f2017-10-17 15:42:00 +0530[diff] [blame]2410 qcom,ddr-config = <0xC3040873>;
2411
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2412 qcom,nonremovable;
Asutosh Das3d37f972018-01-12 15:48:25 +0530[diff] [blame]2413 nvmem-cells = <&minor_rev>;
2414 nvmem-cell-names = "minor_rev";
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2415
Vijay Viswanatheac72722017-06-05 11:01:38 +0530[diff] [blame]2416 status = "disabled";
2417 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2418
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2419 sdhc_2: sdhci@8804000 {
2420 compatible = "qcom,sdhci-msm-v5";
2421 reg = <0x8804000 0x1000>;
2422 reg-names = "hc_mem";
2423
2424 interrupts = <0 204 0>, <0 222 0>;
2425 interrupt-names = "hc_irq", "pwr_irq";
2426
2427 qcom,bus-width = <4>;
2428 qcom,large-address-bus;
2429
Vijay Viswanath6f83cbf2017-08-30 16:41:48 +0530[diff] [blame]2430 qcom,clk-rates = <400000 20000000 25000000
2431 50000000 100000000 201500000>;
2432 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2433 "SDR104";
2434
2435 qcom,devfreq,freq-table = <50000000 201500000>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2436
2437 qcom,msm-bus,name = "sdhc2";
2438 qcom,msm-bus,num-cases = <8>;
2439 qcom,msm-bus,num-paths = <2>;
2440 qcom,msm-bus,vectors-KBps =
2441 /* No vote */
2442 <81 512 0 0>, <1 608 0 0>,
2443 /* 400 KB/s*/
2444 <81 512 1046 1600>,
2445 <1 608 1600 1600>,
2446 /* 20 MB/s */
2447 <81 512 52286 80000>,
2448 <1 608 80000 80000>,
2449 /* 25 MB/s */
2450 <81 512 65360 100000>,
2451 <1 608 100000 100000>,
2452 /* 50 MB/s */
2453 <81 512 130718 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2454 <1 608 100000 100000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2455 /* 100 MB/s */
2456 <81 512 261438 200000>,
Vijay Viswanath655407f2017-11-09 12:37:34 +0530[diff] [blame]2457 <1 608 130000 130000>,
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2458 /* 200 MB/s */
2459 <81 512 261438 400000>,
2460 <1 608 300000 300000>,
2461 /* Max. bandwidth */
2462 <81 512 1338562 4096000>,
2463 <1 608 1338562 4096000>;
2464 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2465 100000000 200000000 4294967295>;
2466
2467 /* PM QoS */
2468 qcom,pm-qos-irq-type = "affine_irq";
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2469 qcom,pm-qos-irq-latency = <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2470 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
Maulik Shah0223afc2018-02-09 12:47:28 +0530[diff] [blame]2471 qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
Vijay Viswanath6ef06c12017-09-20 16:06:18 +0530[diff] [blame]2472
Vijay Viswanathee4340d2017-08-28 09:50:18 +0530[diff] [blame]2473 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
2474 <&clock_gcc GCC_SDCC2_APPS_CLK>;
2475 clock-names = "iface_clk", "core_clk";
2476
2477 status = "disabled";
2478 };
2479
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2480 qcom,msm-cdsp-loader {
2481 compatible = "qcom,cdsp-loader";
2482 qcom,proc-img-to-load = "cdsp";
2483 };
2484
2485 qcom,msm-adsprpc-mem {
2486 compatible = "qcom,msm-adsprpc-mem-region";
2487 memory-region = <&adsp_mem>;
Tharun Kumar Merugu8bb71292018-01-17 15:55:05 +0530[diff] [blame]2488 restrict-access;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2489 };
2490
2491 qcom,msm_fastrpc {
2492 compatible = "qcom,msm-fastrpc-compute";
Tharun Kumar Merugubbebad12017-12-21 16:33:03 +0530[diff] [blame]2493 qcom,adsp-remoteheap-vmid = <22 37>;
Tharun Kumar Merugu1cb19c62018-01-18 12:20:16 +0530[diff] [blame]2494 qcom,fastrpc-adsp-audio-pdr;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2495 qcom,fastrpc-adsp-sensors-pdr;
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2496
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2497 msm_fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2498 compatible = "qcom,msm-fastrpc-compute-cb";
2499 label = "cdsprpc-smd";
2500 iommus = <&apps_smmu 0x1421 0x30>;
2501 dma-coherent;
2502 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2503 msm_fastrpc_compute_cb2: qcom,msm_fastrpc_compute_cb2 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2504 compatible = "qcom,msm-fastrpc-compute-cb";
2505 label = "cdsprpc-smd";
2506 iommus = <&apps_smmu 0x1422 0x30>;
2507 dma-coherent;
2508 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2509 msm_fastrpc_compute_cb3: qcom,msm_fastrpc_compute_cb3 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2510 compatible = "qcom,msm-fastrpc-compute-cb";
2511 label = "cdsprpc-smd";
2512 iommus = <&apps_smmu 0x1423 0x30>;
2513 dma-coherent;
2514 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2515 msm_fastrpc_compute_cb4: qcom,msm_fastrpc_compute_cb4 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2516 compatible = "qcom,msm-fastrpc-compute-cb";
2517 label = "cdsprpc-smd";
2518 iommus = <&apps_smmu 0x1424 0x30>;
2519 dma-coherent;
2520 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2521 msm_fastrpc_compute_cb5: qcom,msm_fastrpc_compute_cb5 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2522 compatible = "qcom,msm-fastrpc-compute-cb";
2523 label = "cdsprpc-smd";
2524 iommus = <&apps_smmu 0x1425 0x30>;
2525 dma-coherent;
2526 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2527 msm_fastrpc_compute_cb6: qcom,msm_fastrpc_compute_cb6 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2528 compatible = "qcom,msm-fastrpc-compute-cb";
2529 label = "cdsprpc-smd";
2530 iommus = <&apps_smmu 0x1426 0x30>;
2531 dma-coherent;
2532 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2533 msm_fastrpc_compute_cb7: qcom,msm_fastrpc_compute_cb7 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2534 compatible = "qcom,msm-fastrpc-compute-cb";
2535 label = "cdsprpc-smd";
2536 qcom,secure-context-bank;
2537 iommus = <&apps_smmu 0x1429 0x30>;
2538 dma-coherent;
2539 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2540 msm_fastrpc_compute_cb8: qcom,msm_fastrpc_compute_cb8 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2541 compatible = "qcom,msm-fastrpc-compute-cb";
2542 label = "cdsprpc-smd";
2543 qcom,secure-context-bank;
2544 iommus = <&apps_smmu 0x142A 0x30>;
2545 dma-coherent;
2546 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2547 msm_fastrpc_compute_cb9: qcom,msm_fastrpc_compute_cb9 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2548 compatible = "qcom,msm-fastrpc-compute-cb";
2549 label = "adsprpc-smd";
2550 iommus = <&apps_smmu 0x1803 0x0>;
2551 dma-coherent;
2552 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2553 msm_fastrpc_compute_cb10: qcom,msm_fastrpc_compute_cb10 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2554 compatible = "qcom,msm-fastrpc-compute-cb";
2555 label = "adsprpc-smd";
2556 iommus = <&apps_smmu 0x1804 0x0>;
2557 dma-coherent;
2558 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2559 msm_fastrpc_compute_cb11: qcom,msm_fastrpc_compute_cb11 {
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2560 compatible = "qcom,msm-fastrpc-compute-cb";
2561 label = "adsprpc-smd";
2562 iommus = <&apps_smmu 0x1805 0x0>;
2563 dma-coherent;
2564 };
Vishwanath Raju K922111f2019-03-11 22:20:55 +0530[diff] [blame]2565 msm_fastrpc_compute_cb12: qcom,msm_fastrpc_compute_cb12 {
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2566 compatible = "qcom,msm-fastrpc-compute-cb";
2567 label = "adsprpc-smd";
2568 iommus = <&apps_smmu 0x1806 0x0>;
2569 dma-coherent;
Tharun Kumar Merugub67b0ef2018-02-07 21:30:39 +0530[diff] [blame]2570 shared-cb;
c_mtharu92125922017-10-16 14:06:39 +0530[diff] [blame]2571 };
Tharun Kumar Merugu03380d82017-08-08 13:04:36 +0530[diff] [blame]2572 };
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2573
Rupesh Tatiyaf2072952017-10-08 19:57:12 +0530[diff] [blame]2574 bluetooth: bt_wcn3990 {
2575 compatible = "qca,wcn3990";
2576 qca,bt-vdd-core-supply = <&pm660_l9>;
2577 qca,bt-vdd-pa-supply = <&pm660_l6>;
2578 qca,bt-vdd-ldo-supply = <&pm660_l19>;
2579
2580 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
2581 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
2582 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
2583
2584 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
2585 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
2586 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
2587 };
2588
Sarada Prasanna Garnayakd5ccc902018-02-22 15:54:50 +0530[diff] [blame]2589 icnss: qcom,icnss@18800000 {
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2590 compatible = "qcom,icnss";
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2591 reg = <0x18800000 0x800000>,
2592 <0xa0000000 0x10000000>,
2593 <0xb0000000 0x10000>;
2594 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
2595 iommus = <&apps_smmu 0x0040 0x1>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2596 interrupts = <0 414 0 /* CE0 */ >,
2597 <0 415 0 /* CE1 */ >,
2598 <0 416 0 /* CE2 */ >,
2599 <0 417 0 /* CE3 */ >,
2600 <0 418 0 /* CE4 */ >,
2601 <0 419 0 /* CE5 */ >,
2602 <0 420 0 /* CE6 */ >,
2603 <0 421 0 /* CE7 */ >,
2604 <0 422 0 /* CE8 */ >,
2605 <0 423 0 /* CE9 */ >,
2606 <0 424 0 /* CE10 */ >,
2607 <0 425 0 /* CE11 */ >;
Anurag Chouhand22b18a2017-10-08 15:16:08 +0530[diff] [blame]2608 vdd-0.8-cx-mx-supply = <&pm660_l5>;
2609 vdd-1.8-xo-supply = <&pm660_l9>;
2610 vdd-1.3-rfa-supply = <&pm660_l6>;
2611 vdd-3.3-ch0-supply = <&pm660_l19>;
Hardik Kantilal Patel25c05b42017-12-08 11:10:27 +0530[diff] [blame]2612 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2613 qcom,wlan-msa-memory = <0x100000>;
Anurag Chouhana4f55db2017-11-22 16:35:27 +0530[diff] [blame]2614 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
Hardik Kantilal Patel1697bd12018-03-05 14:46:29 +0530[diff] [blame]2615 qcom,gpio-force-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
2616 qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2617 qcom,smmu-s1-bypass;
Naman Padhiar7c143462019-07-01 12:10:47 +0530[diff] [blame^]2618 #cooling-cells = <2>;
Anurag Chouhan7563b532017-09-12 15:49:16 +0530[diff] [blame]2619 };
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2620
2621 cpubw: qcom,cpubw {
2622 compatible = "qcom,devbw";
2623 governor = "performance";
2624 qcom,src-dst-ports =
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2625 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2626 qcom,active-only;
2627 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2628 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2629 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2630 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2631 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2632 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2633 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2634 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2635 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2636 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2637 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2638 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2639 };
2640
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2641 bwmon: qcom,cpu-bwmon {
2642 compatible = "qcom,bimc-bwmon4";
2643 reg = <0x1436400 0x300>, <0x1436300 0x200>;
2644 reg-names = "base", "global_base";
2645 interrupts = <0 581 4>;
2646 qcom,mport = <0>;
Santosh Mardida0b0f82017-10-13 23:30:22 +0530[diff] [blame]2647 qcom,count-unit = <0x10000>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2648 qcom,hw-timer-hz = <19200000>;
Santosh Mardidfc78812017-10-05 13:15:20 +0530[diff] [blame]2649 qcom,target-dev = <&cpubw>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2650 };
2651
2652 memlat_cpu0: qcom,memlat-cpu0 {
2653 compatible = "qcom,devbw";
2654 governor = "powersave";
2655 qcom,src-dst-ports = <1 512>;
2656 qcom,active-only;
2657 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2658 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2659 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2660 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2661 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2662 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2663 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2664 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2665 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2666 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2667 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2668 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2669 };
2670
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2671 memlat_cpu6: qcom,memlat-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2672 compatible = "qcom,devbw";
2673 governor = "powersave";
2674 qcom,src-dst-ports = <1 512>;
2675 qcom,active-only;
2676 status = "ok";
2677 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2678 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2679 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2680 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2681 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2682 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2683 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2684 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2685 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2686 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2687 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2688 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2689 };
2690
Odelu Kukatlafe8d3302017-11-17 10:54:32 +0530[diff] [blame]2691 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
2692 compatible = "qcom,devbw";
2693 governor = "powersave";
2694 qcom,src-dst-ports = <139 627>;
2695 qcom,active-only;
2696 status = "ok";
2697 qcom,bw-tbl =
2698 < 1 >;
2699 };
2700
Odelu Kukatla95e7aea2018-02-27 15:46:39 +0530[diff] [blame]2701 bus_proxy_client: qcom,bus_proxy_client {
2702 compatible = "qcom,bus-proxy-client";
2703 qcom,msm-bus,name = "bus-proxy-client";
2704 qcom,msm-bus,num-cases = <2>;
2705 qcom,msm-bus,num-paths = <2>;
2706 qcom,msm-bus,vectors-KBps =
2707 <22 512 0 0>, <23 512 0 0>,
2708 <22 512 0 5000000>, <23 512 0 5000000>;
2709 qcom,msm-bus,active-only;
2710 status = "ok";
2711 };
2712
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2713 devfreq_memlat_0: qcom,cpu0-memlat-mon {
2714 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2715 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2716 qcom,target-dev = <&memlat_cpu0>;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2717 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2718 qcom,core-dev-table =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2719 < 748800 MHZ_TO_MBPS( 300, 4) >,
2720 < 998400 MHZ_TO_MBPS( 451, 4) >,
2721 < 1209600 MHZ_TO_MBPS( 547, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2722 < 1516800 MHZ_TO_MBPS( 768, 4) >,
2723 < 1708000 MHZ_TO_MBPS(1017, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2724 };
2725
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2726 devfreq_memlat_6: qcom,cpu6-memlat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2727 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2728 qcom,cpulist = <&CPU6 &CPU7>;
2729 qcom,target-dev = <&memlat_cpu6>;
2730 qcom,cachemiss-ev = <0x2a>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2731 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2732 < 825600 MHZ_TO_MBPS( 300, 4) >,
2733 < 1132800 MHZ_TO_MBPS( 547, 4) >,
2734 < 1363200 MHZ_TO_MBPS(1017, 4) >,
2735 < 1996800 MHZ_TO_MBPS(1555, 4) >,
2736 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2737 };
2738
2739 l3_cpu0: qcom,l3-cpu0 {
2740 compatible = "devfreq-simple-dev";
2741 clock-names = "devfreq_clk";
2742 clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
2743 governor = "performance";
2744 };
2745
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2746 l3_cpu6: qcom,l3-cpu6 {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2747 compatible = "devfreq-simple-dev";
2748 clock-names = "devfreq_clk";
2749 clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
2750 governor = "performance";
2751 };
2752
2753 devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
2754 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2755 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2756 qcom,target-dev = <&l3_cpu0>;
2757 qcom,cachemiss-ev = <0x17>;
2758 qcom,core-dev-table =
Santosh Mardi10d45032017-11-02 17:25:54 +0530[diff] [blame]2759 < 576000 300000000 >,
Santosh Mardi831cc872018-01-11 14:52:32 +0530[diff] [blame]2760 < 998400 556800000 >,
2761 < 1209660 844800000 >,
2762 < 1516800 940800000 >,
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2763 < 1612800 1382400000 >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2764 < 1708000 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2765 };
2766
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2767 devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2768 compatible = "qcom,arm-memlat-mon";
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2769 qcom,cpulist = <&CPU6 &CPU7>;
2770 qcom,target-dev = <&l3_cpu6>;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2771 qcom,cachemiss-ev = <0x17>;
2772 qcom,core-dev-table =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2773 < 1132800 556800000 >,
2774 < 1363200 806400000 >,
2775 < 1747200 940800000 >,
2776 < 1996800 1190400000 >,
2777 < 2457600 1440000000 >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2778 };
2779
2780 mincpubw: qcom,mincpubw {
2781 compatible = "qcom,devbw";
2782 governor = "powersave";
2783 qcom,src-dst-ports = <1 512>;
2784 qcom,active-only;
2785 qcom,bw-tbl =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2786 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2787 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2788 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2789 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2790 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2791 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2792 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2793 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2794 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2795 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2796 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2797 };
2798
2799 devfreq-cpufreq {
2800 mincpubw-cpufreq {
2801 target-dev = <&mincpubw>;
2802 cpu-to-dev-map-0 =
Santosh Mardi9d208ff2017-09-25 11:16:17 +0530[diff] [blame]2803 < 748800 MHZ_TO_MBPS( 300, 4) >,
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2804 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2805 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2806 < 1708000 MHZ_TO_MBPS( 768, 4) >;
Santosh Mardi37a28af2017-10-12 13:03:31 +0530[diff] [blame]2807 cpu-to-dev-map-6 =
Santosh Mardie49578c2017-10-27 11:24:45 +0530[diff] [blame]2808 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2809 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2810 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2811 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2812 < 2457600 MHZ_TO_MBPS(1804, 4) >;
Santosh Mardi077e7eb2017-09-11 18:53:47 +0530[diff] [blame]2813 };
2814 };
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2815
Jonathan Avilac7a6fd52017-10-12 15:24:05 -0700[diff] [blame]2816 mincpu0bw: qcom,mincpu0bw {
2817 compatible = "qcom,devbw";
2818 governor = "powersave";
2819 qcom,src-dst-ports = <1 512>;
2820 qcom,active-only;
2821 qcom,bw-tbl =
2822 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2823 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2824 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2825 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2826 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2827 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2828 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2829 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2830 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2831 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2832 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2833 };
2834
2835 mincpu6bw: qcom,mincpu6bw {
2836 compatible = "qcom,devbw";
2837 governor = "powersave";
2838 qcom,src-dst-ports = <1 512>;
2839 qcom,active-only;
2840 qcom,bw-tbl =
2841 < MHZ_TO_MBPS( 100, 4) >, /* 381 MB/s */
2842 < MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
2843 < MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
2844 < MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
2845 < MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
2846 < MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
2847 < MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
2848 < MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
2849 < MHZ_TO_MBPS(1353, 4) >, /* 5161 MB/s */
2850 < MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
2851 < MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
2852 };
2853
2854 devfreq_compute0: qcom,devfreq-compute0 {
2855 compatible = "qcom,arm-cpu-mon";
2856 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
2857 qcom,target-dev = <&mincpu0bw>;
2858 qcom,core-dev-table =
2859 < 748800 MHZ_TO_MBPS( 300, 4) >,
2860 < 1209660 MHZ_TO_MBPS( 451, 4) >,
2861 < 1612800 MHZ_TO_MBPS( 547, 4) >,
2862 < 1708000 MHZ_TO_MBPS( 768, 4) >;
2863 };
2864
2865 devfreq_compute6: qcom,devfreq-compute6 {
2866 compatible = "qcom,arm-cpu-mon";
2867 qcom,cpulist = <&CPU6 &CPU7>;
2868 qcom,target-dev = <&mincpu6bw>;
2869 qcom,core-dev-table =
2870 < 1132800 MHZ_TO_MBPS( 300, 4) >,
2871 < 1363200 MHZ_TO_MBPS( 547, 4) >,
2872 < 1747200 MHZ_TO_MBPS( 768, 4) >,
2873 < 1996800 MHZ_TO_MBPS(1017, 4) >,
2874 < 2457600 MHZ_TO_MBPS(1804, 4) >;
2875 };
2876
Santosh Mardi7790a432018-01-09 23:01:56 +0530[diff] [blame]2877 l3_cdsp: qcom,l3-cdsp {
2878 compatible = "devfreq-simple-dev";
2879 clock-names = "devfreq_clk";
2880 clocks = <&clock_cpucc L3_MISC_VOTE_CLK>;
2881 governor = "powersave";
2882 };
2883
Raghavendra Rao Ananta28dd4502017-10-18 10:28:31 -0700[diff] [blame]2884 cpu_pmu: cpu-pmu {
2885 compatible = "arm,armv8-pmuv3";
2886 qcom,irq-is-percpu;
2887 interrupts = <1 5 4>;
2888 };
2889
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2890 gpu_gx_domain_addr: syscon@0x5091508 {
2891 compatible = "syscon";
2892 reg = <0x5091508 0x4>;
2893 };
2894
2895 gpu_gx_sw_reset: syscon@0x5091008 {
2896 compatible = "syscon";
2897 reg = <0x5091008 0x4>;
2898 };
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2899
2900 qfprom: qfprom@0x780000 {
2901 compatible = "qcom,qfprom";
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2902 reg = <0x00784000 0x1000>;
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2903 #address-cells = <1>;
2904 #size-cells = <1>;
2905 ranges;
2906
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2907 minor_rev: minor_rev@0x78414c {
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2908 reg = <0x14c 0x4>;
Prakash Gupta50a47e52018-01-29 16:11:19 +0530[diff] [blame]2909 bits = <0 30>; /* Access 30 bits from bit offset 0 */
Prakash Gupta325dff62018-01-09 15:38:09 +0530[diff] [blame]2910 };
2911 };
2912
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2913};
2914
Ashay Jaiswal81940302017-09-20 15:17:58 +0530[diff] [blame]2915#include "pm660.dtsi"
2916#include "pm660l.dtsi"
2917#include "sdm670-regulator.dtsi"
Imran Khan04f08312017-03-30 15:07:43 +0530[diff] [blame]2918#include "sdm670-pinctrl.dtsi"
Vijayanand Jittad48c4082017-06-07 15:07:51 +0530[diff] [blame]2919#include "msm-arm-smmu-sdm670.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2920#include "msm-gdsc-sdm845.dtsi"
Maulik Shahd313ea82017-06-14 13:10:52 +0530[diff] [blame]2921#include "sdm670-pm.dtsi"
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2922
2923&usb30_prim_gdsc {
2924 status = "ok";
2925};
2926
2927&ufs_phy_gdsc {
2928 status = "ok";
2929};
2930
2931&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
2932 status = "ok";
2933};
2934
2935&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
2936 status = "ok";
2937};
2938
2939&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
2940 status = "ok";
2941};
2942
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2943&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
2944 status = "ok";
2945};
2946
2947&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
2948 status = "ok";
2949};
2950
2951&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
2952 status = "ok";
2953};
2954
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2955&bps_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2956 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2957 status = "ok";
2958};
2959
2960&ife_0_gdsc {
2961 status = "ok";
2962};
2963
2964&ife_1_gdsc {
2965 status = "ok";
2966};
2967
2968&ipe_0_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2969 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2970 status = "ok";
2971};
2972
2973&ipe_1_gdsc {
Odelu Kukatla4328a432017-12-06 18:16:59 +0530[diff] [blame]2974 qcom,support-hw-trigger;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2975 status = "ok";
2976};
2977
2978&titan_top_gdsc {
2979 status = "ok";
2980};
2981
2982&mdss_core_gdsc {
2983 status = "ok";
Sandeep Pandaae888352017-11-15 13:15:31 +0530[diff] [blame]2984 proxy-supply = <&mdss_core_gdsc>;
2985 qcom,proxy-consumer-enable;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2986};
2987
2988&gpu_cx_gdsc {
Odelu Kukatla4abca302018-06-19 12:46:47 +0530[diff] [blame]2989 parent-supply = <&pm660l_s3_level>;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]2990 status = "ok";
2991};
2992
2993&gpu_gx_gdsc {
2994 clock-names = "core_root_clk";
2995 clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
2996 qcom,force-enable-root-clk;
Odelu Kukatla1186d2e2017-08-04 17:28:46 +0530[diff] [blame]2997 parent-supply = <&pm660l_s2_level>;
Amit Nischal199f15d2017-09-12 10:58:51 +0530[diff] [blame]2998 domain-addr = <&gpu_gx_domain_addr>;
2999 sw-reset = <&gpu_gx_sw_reset>;
3000 qcom,reset-aon-logic;
Odelu Kukatla1fe3a222017-06-01 16:24:59 +0530[diff] [blame]3001 status = "ok";
3002};
3003
3004&vcodec0_gdsc {
3005 qcom,support-hw-trigger;
3006 status = "ok";
3007};
3008
3009&vcodec1_gdsc {
3010 qcom,support-hw-trigger;
3011 status = "ok";
3012};
3013
3014&venus_gdsc {
3015 status = "ok";
3016};
Tirupathi Reddy0cfe2082017-06-08 14:24:13 +0530[diff] [blame]3017
Sandeep Panda229db242017-10-03 11:32:29 +0530[diff] [blame]3018&mdss_dsi0 {
3019 qcom,core-supply-entries {
3020 #address-cells = <1>;
3021 #size-cells = <0>;
3022
3023 qcom,core-supply-entry@0 {
3024 reg = <0>;
3025 qcom,supply-name = "refgen";
3026 qcom,supply-min-voltage = <0>;
3027 qcom,supply-max-voltage = <0>;
3028 qcom,supply-enable-load = <0>;
3029 qcom,supply-disable-load = <0>;
3030 };
3031 };
3032};
3033
3034&mdss_dsi1 {
3035 qcom,core-supply-entries {
3036 #address-cells = <1>;
3037 #size-cells = <0>;
3038
3039 qcom,core-supply-entry@0 {
3040 reg = <0>;
3041 qcom,supply-name = "refgen";
3042 qcom,supply-min-voltage = <0>;
3043 qcom,supply-max-voltage = <0>;
3044 qcom,supply-enable-load = <0>;
3045 qcom,supply-disable-load = <0>;
3046 };
3047 };
3048};
3049
Padmanabhan Komanduru07137332017-10-20 12:53:23 +0530[diff] [blame]3050&sde_dp {
3051 qcom,core-supply-entries {
3052 #address-cells = <1>;
3053 #size-cells = <0>;
3054
3055 qcom,core-supply-entry@0 {
3056 reg = <0>;
3057 qcom,supply-name = "refgen";
3058 qcom,supply-min-voltage = <0>;
3059 qcom,supply-max-voltage = <0>;
3060 qcom,supply-enable-load = <0>;
3061 qcom,supply-disable-load = <0>;
3062 };
3063 };
3064};
3065
Rohit Kumar14051282017-07-12 11:18:48 +0530[diff] [blame]3066#include "sdm670-audio.dtsi"
Pratham Pratap9e420a32017-09-05 11:26:57 +0530[diff] [blame]3067#include "sdm670-usb.dtsi"
Rajesh Kemisettiba56c482017-08-31 18:12:35 +0530[diff] [blame]3068#include "sdm670-gpu.dtsi"
Suresh Vankadara402d0ca2017-10-26 22:54:54 +0530[diff] [blame]3069#include "sdm670-camera.dtsi"
Manaf Meethalavalappu Pallikunhi52c7ba12017-09-07 01:41:43 +0530[diff] [blame]3070#include "sdm670-thermal.dtsi"
Odelu Kukatlaf197e382017-07-04 19:47:35 +0530[diff] [blame]3071#include "sdm670-bus.dtsi"
Tirupathi Reddyf805ac72017-10-12 14:22:17 +0530[diff] [blame]3072
3073&pm660_div_clk {
3074 status = "ok";
3075};
Tirupathi Reddy53b92a62017-10-26 13:57:42 +0530[diff] [blame]3076
3077&qupv3_se10_i2c {
3078 nx30p6093: nx30p6093@36 {
3079 status = "disabled";
3080 compatible = "nxp,nx30p6093";
3081 reg = <0x36>;
3082 interrupt-parent = <&tlmm>;
3083 interrupts = <5 IRQ_TYPE_NONE>;
3084 nxp,long-wakeup-sec = <28800>; /* 8 hours */
3085 nxp,short-wakeup-ms = <180000>; /* 3 mins */
3086 pinctrl-names = "default";
3087 pinctrl-0 = <&nx30p6093_intr_default>;
3088 };
3089};