Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 43 | #if defined(CONFIG_DEBUG_FS) |
| 44 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 46 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 48 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 49 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 50 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 51 | static const char *yesno(int v) |
| 52 | { |
| 53 | return v ? "yes" : "no"; |
| 54 | } |
| 55 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 56 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 57 | * allocated we need to hook into the minor for release. */ |
| 58 | static int |
| 59 | drm_add_fake_info_node(struct drm_minor *minor, |
| 60 | struct dentry *ent, |
| 61 | const void *key) |
| 62 | { |
| 63 | struct drm_info_node *node; |
| 64 | |
| 65 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 66 | if (node == NULL) { |
| 67 | debugfs_remove(ent); |
| 68 | return -ENOMEM; |
| 69 | } |
| 70 | |
| 71 | node->minor = minor; |
| 72 | node->dent = ent; |
| 73 | node->info_ent = (void *) key; |
| 74 | |
| 75 | mutex_lock(&minor->debugfs_lock); |
| 76 | list_add(&node->list, &minor->debugfs_list); |
| 77 | mutex_unlock(&minor->debugfs_lock); |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 82 | static int i915_capabilities(struct seq_file *m, void *data) |
| 83 | { |
| 84 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 85 | struct drm_device *dev = node->minor->dev; |
| 86 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 87 | |
| 88 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 89 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 90 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 91 | #define SEP_SEMICOLON ; |
| 92 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 93 | #undef PRINT_FLAG |
| 94 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 95 | |
| 96 | return 0; |
| 97 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 98 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 99 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 100 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 101 | if (obj->user_pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 102 | return "P"; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 103 | else if (obj->pin_count > 0) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 104 | return "p"; |
| 105 | else |
| 106 | return " "; |
| 107 | } |
| 108 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 109 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 110 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 111 | switch (obj->tiling_mode) { |
| 112 | default: |
| 113 | case I915_TILING_NONE: return " "; |
| 114 | case I915_TILING_X: return "X"; |
| 115 | case I915_TILING_Y: return "Y"; |
| 116 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 117 | } |
| 118 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 119 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 120 | { |
| 121 | return obj->has_global_gtt_mapping ? "g" : " "; |
| 122 | } |
| 123 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 124 | static void |
| 125 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 126 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 127 | struct i915_vma *vma; |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 129 | &obj->base, |
| 130 | get_pin_flag(obj), |
| 131 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 132 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 133 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 134 | obj->base.read_domains, |
| 135 | obj->base.write_domain, |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 136 | obj->last_read_seqno, |
| 137 | obj->last_write_seqno, |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 138 | obj->last_fenced_seqno, |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 139 | i915_cache_level_str(obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 140 | obj->dirty ? " dirty" : "", |
| 141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 142 | if (obj->base.name) |
| 143 | seq_printf(m, " (name: %d)", obj->base.name); |
Chris Wilson | c110a6d | 2012-08-11 15:41:02 +0100 | [diff] [blame] | 144 | if (obj->pin_count) |
| 145 | seq_printf(m, " (pinned x %d)", obj->pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 146 | if (obj->pin_display) |
| 147 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 149 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 151 | if (!i915_is_ggtt(vma->vm)) |
| 152 | seq_puts(m, " (pp"); |
| 153 | else |
| 154 | seq_puts(m, " (g"); |
| 155 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", |
| 156 | vma->node.start, vma->node.size); |
| 157 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 158 | if (obj->stolen) |
| 159 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 160 | if (obj->pin_mappable || obj->fault_mappable) { |
| 161 | char s[3], *t = s; |
| 162 | if (obj->pin_mappable) |
| 163 | *t++ = 'p'; |
| 164 | if (obj->fault_mappable) |
| 165 | *t++ = 'f'; |
| 166 | *t = '\0'; |
| 167 | seq_printf(m, " (%s mappable)", s); |
| 168 | } |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 169 | if (obj->ring != NULL) |
| 170 | seq_printf(m, " (%s)", obj->ring->name); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 171 | } |
| 172 | |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 173 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
| 174 | { |
| 175 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); |
| 176 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 177 | seq_putc(m, ' '); |
| 178 | } |
| 179 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 180 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 181 | { |
| 182 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 183 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 184 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 185 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 186 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 187 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 188 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 189 | size_t total_obj_size, total_gtt_size; |
| 190 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 191 | |
| 192 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 193 | if (ret) |
| 194 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 195 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 196 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 197 | switch (list) { |
| 198 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 199 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 200 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 201 | break; |
| 202 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 203 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 204 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 205 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 206 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 207 | mutex_unlock(&dev->struct_mutex); |
| 208 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 209 | } |
| 210 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 211 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 212 | list_for_each_entry(vma, head, mm_list) { |
| 213 | seq_printf(m, " "); |
| 214 | describe_obj(m, vma->obj); |
| 215 | seq_printf(m, "\n"); |
| 216 | total_obj_size += vma->obj->base.size; |
| 217 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 218 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 219 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 220 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 221 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 222 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 223 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 224 | return 0; |
| 225 | } |
| 226 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 227 | static int obj_rank_by_stolen(void *priv, |
| 228 | struct list_head *A, struct list_head *B) |
| 229 | { |
| 230 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 231 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 232 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 233 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 234 | |
| 235 | return a->stolen->start - b->stolen->start; |
| 236 | } |
| 237 | |
| 238 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 239 | { |
| 240 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 241 | struct drm_device *dev = node->minor->dev; |
| 242 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 243 | struct drm_i915_gem_object *obj; |
| 244 | size_t total_obj_size, total_gtt_size; |
| 245 | LIST_HEAD(stolen); |
| 246 | int count, ret; |
| 247 | |
| 248 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 249 | if (ret) |
| 250 | return ret; |
| 251 | |
| 252 | total_obj_size = total_gtt_size = count = 0; |
| 253 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 254 | if (obj->stolen == NULL) |
| 255 | continue; |
| 256 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 257 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 258 | |
| 259 | total_obj_size += obj->base.size; |
| 260 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 261 | count++; |
| 262 | } |
| 263 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 264 | if (obj->stolen == NULL) |
| 265 | continue; |
| 266 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 267 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 268 | |
| 269 | total_obj_size += obj->base.size; |
| 270 | count++; |
| 271 | } |
| 272 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 273 | seq_puts(m, "Stolen:\n"); |
| 274 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 275 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 276 | seq_puts(m, " "); |
| 277 | describe_obj(m, obj); |
| 278 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 279 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 280 | } |
| 281 | mutex_unlock(&dev->struct_mutex); |
| 282 | |
| 283 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 284 | count, total_obj_size, total_gtt_size); |
| 285 | return 0; |
| 286 | } |
| 287 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 288 | #define count_objects(list, member) do { \ |
| 289 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 290 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 291 | ++count; \ |
| 292 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 293 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 294 | ++mappable_count; \ |
| 295 | } \ |
| 296 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 297 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 298 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 299 | struct file_stats { |
| 300 | int count; |
| 301 | size_t total, active, inactive, unbound; |
| 302 | }; |
| 303 | |
| 304 | static int per_file_stats(int id, void *ptr, void *data) |
| 305 | { |
| 306 | struct drm_i915_gem_object *obj = ptr; |
| 307 | struct file_stats *stats = data; |
| 308 | |
| 309 | stats->count++; |
| 310 | stats->total += obj->base.size; |
| 311 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 312 | if (i915_gem_obj_ggtt_bound(obj)) { |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 313 | if (!list_empty(&obj->ring_list)) |
| 314 | stats->active += obj->base.size; |
| 315 | else |
| 316 | stats->inactive += obj->base.size; |
| 317 | } else { |
| 318 | if (!list_empty(&obj->global_list)) |
| 319 | stats->unbound += obj->base.size; |
| 320 | } |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 325 | #define count_vmas(list, member) do { \ |
| 326 | list_for_each_entry(vma, list, member) { \ |
| 327 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 328 | ++count; \ |
| 329 | if (vma->obj->map_and_fenceable) { \ |
| 330 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 331 | ++mappable_count; \ |
| 332 | } \ |
| 333 | } \ |
| 334 | } while (0) |
| 335 | |
| 336 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 337 | { |
| 338 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 339 | struct drm_device *dev = node->minor->dev; |
| 340 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 341 | u32 count, mappable_count, purgeable_count; |
| 342 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 343 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 344 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 345 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 346 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 347 | int ret; |
| 348 | |
| 349 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 350 | if (ret) |
| 351 | return ret; |
| 352 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 353 | seq_printf(m, "%u objects, %zu bytes\n", |
| 354 | dev_priv->mm.object_count, |
| 355 | dev_priv->mm.object_memory); |
| 356 | |
| 357 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 358 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 359 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 360 | count, mappable_count, size, mappable_size); |
| 361 | |
| 362 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 363 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 364 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 365 | count, mappable_count, size, mappable_size); |
| 366 | |
| 367 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 368 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 369 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 370 | count, mappable_count, size, mappable_size); |
| 371 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 372 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 373 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 374 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 375 | if (obj->madv == I915_MADV_DONTNEED) |
| 376 | purgeable_size += obj->base.size, ++purgeable_count; |
| 377 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 378 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 379 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 380 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 381 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 382 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 383 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 384 | ++count; |
| 385 | } |
| 386 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 387 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 388 | ++mappable_count; |
| 389 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 390 | if (obj->madv == I915_MADV_DONTNEED) { |
| 391 | purgeable_size += obj->base.size; |
| 392 | ++purgeable_count; |
| 393 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 394 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 395 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 396 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 397 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 398 | mappable_count, mappable_size); |
| 399 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 400 | count, size); |
| 401 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 402 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 403 | dev_priv->gtt.base.total, |
| 404 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 405 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 406 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 407 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 408 | struct file_stats stats; |
| 409 | |
| 410 | memset(&stats, 0, sizeof(stats)); |
| 411 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
| 412 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", |
| 413 | get_pid_task(file->pid, PIDTYPE_PID)->comm, |
| 414 | stats.count, |
| 415 | stats.total, |
| 416 | stats.active, |
| 417 | stats.inactive, |
| 418 | stats.unbound); |
| 419 | } |
| 420 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 421 | mutex_unlock(&dev->struct_mutex); |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 426 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 427 | { |
| 428 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 429 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 430 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 431 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 432 | struct drm_i915_gem_object *obj; |
| 433 | size_t total_obj_size, total_gtt_size; |
| 434 | int count, ret; |
| 435 | |
| 436 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 437 | if (ret) |
| 438 | return ret; |
| 439 | |
| 440 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 441 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 442 | if (list == PINNED_LIST && obj->pin_count == 0) |
| 443 | continue; |
| 444 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 445 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 446 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 447 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 448 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 449 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 450 | count++; |
| 451 | } |
| 452 | |
| 453 | mutex_unlock(&dev->struct_mutex); |
| 454 | |
| 455 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 456 | count, total_obj_size, total_gtt_size); |
| 457 | |
| 458 | return 0; |
| 459 | } |
| 460 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 461 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 462 | { |
| 463 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 464 | struct drm_device *dev = node->minor->dev; |
| 465 | unsigned long flags; |
| 466 | struct intel_crtc *crtc; |
| 467 | |
| 468 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 469 | const char pipe = pipe_name(crtc->pipe); |
| 470 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 471 | struct intel_unpin_work *work; |
| 472 | |
| 473 | spin_lock_irqsave(&dev->event_lock, flags); |
| 474 | work = crtc->unpin_work; |
| 475 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 476 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 477 | pipe, plane); |
| 478 | } else { |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 479 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 480 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 481 | pipe, plane); |
| 482 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 483 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 484 | pipe, plane); |
| 485 | } |
| 486 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 487 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 488 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 489 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 490 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 491 | |
| 492 | if (work->old_fb_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 493 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
| 494 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 495 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
| 496 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 497 | } |
| 498 | if (work->pending_flip_obj) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 499 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
| 500 | if (obj) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 501 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
| 502 | i915_gem_obj_ggtt_offset(obj)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 503 | } |
| 504 | } |
| 505 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 506 | } |
| 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 511 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 512 | { |
| 513 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 514 | struct drm_device *dev = node->minor->dev; |
| 515 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 516 | struct intel_ring_buffer *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 517 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 518 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 519 | |
| 520 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 521 | if (ret) |
| 522 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 523 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 524 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 525 | for_each_ring(ring, dev_priv, i) { |
| 526 | if (list_empty(&ring->request_list)) |
| 527 | continue; |
| 528 | |
| 529 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 530 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 531 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 532 | list) { |
| 533 | seq_printf(m, " %d @ %d\n", |
| 534 | gem_request->seqno, |
| 535 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 536 | } |
| 537 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 538 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 539 | mutex_unlock(&dev->struct_mutex); |
| 540 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 541 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 542 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 543 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 544 | return 0; |
| 545 | } |
| 546 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 547 | static void i915_ring_seqno_info(struct seq_file *m, |
| 548 | struct intel_ring_buffer *ring) |
| 549 | { |
| 550 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 551 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 552 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 553 | } |
| 554 | } |
| 555 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 556 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 557 | { |
| 558 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 559 | struct drm_device *dev = node->minor->dev; |
| 560 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 561 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 562 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 563 | |
| 564 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 565 | if (ret) |
| 566 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 567 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 568 | for_each_ring(ring, dev_priv, i) |
| 569 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 570 | |
| 571 | mutex_unlock(&dev->struct_mutex); |
| 572 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | |
| 577 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 578 | { |
| 579 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 580 | struct drm_device *dev = node->minor->dev; |
| 581 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 582 | struct intel_ring_buffer *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 583 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 584 | |
| 585 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 586 | if (ret) |
| 587 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 588 | |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame^] | 589 | if (INTEL_INFO(dev)->gen >= 8) { |
| 590 | int i; |
| 591 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 592 | I915_READ(GEN8_MASTER_IRQ)); |
| 593 | |
| 594 | for (i = 0; i < 4; i++) { |
| 595 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 596 | i, I915_READ(GEN8_GT_IMR(i))); |
| 597 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 598 | i, I915_READ(GEN8_GT_IIR(i))); |
| 599 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 600 | i, I915_READ(GEN8_GT_IER(i))); |
| 601 | } |
| 602 | |
| 603 | for_each_pipe(i) { |
| 604 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
| 605 | pipe_name(i), |
| 606 | I915_READ(GEN8_DE_PIPE_IMR(i))); |
| 607 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
| 608 | pipe_name(i), |
| 609 | I915_READ(GEN8_DE_PIPE_IIR(i))); |
| 610 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
| 611 | pipe_name(i), |
| 612 | I915_READ(GEN8_DE_PIPE_IER(i))); |
| 613 | } |
| 614 | |
| 615 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 616 | I915_READ(GEN8_DE_PORT_IMR)); |
| 617 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 618 | I915_READ(GEN8_DE_PORT_IIR)); |
| 619 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 620 | I915_READ(GEN8_DE_PORT_IER)); |
| 621 | |
| 622 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 623 | I915_READ(GEN8_DE_MISC_IMR)); |
| 624 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 625 | I915_READ(GEN8_DE_MISC_IIR)); |
| 626 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 627 | I915_READ(GEN8_DE_MISC_IER)); |
| 628 | |
| 629 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 630 | I915_READ(GEN8_PCU_IMR)); |
| 631 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 632 | I915_READ(GEN8_PCU_IIR)); |
| 633 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 634 | I915_READ(GEN8_PCU_IER)); |
| 635 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 636 | seq_printf(m, "Display IER:\t%08x\n", |
| 637 | I915_READ(VLV_IER)); |
| 638 | seq_printf(m, "Display IIR:\t%08x\n", |
| 639 | I915_READ(VLV_IIR)); |
| 640 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 641 | I915_READ(VLV_IIR_RW)); |
| 642 | seq_printf(m, "Display IMR:\t%08x\n", |
| 643 | I915_READ(VLV_IMR)); |
| 644 | for_each_pipe(pipe) |
| 645 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 646 | pipe_name(pipe), |
| 647 | I915_READ(PIPESTAT(pipe))); |
| 648 | |
| 649 | seq_printf(m, "Master IER:\t%08x\n", |
| 650 | I915_READ(VLV_MASTER_IER)); |
| 651 | |
| 652 | seq_printf(m, "Render IER:\t%08x\n", |
| 653 | I915_READ(GTIER)); |
| 654 | seq_printf(m, "Render IIR:\t%08x\n", |
| 655 | I915_READ(GTIIR)); |
| 656 | seq_printf(m, "Render IMR:\t%08x\n", |
| 657 | I915_READ(GTIMR)); |
| 658 | |
| 659 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 660 | I915_READ(GEN6_PMIER)); |
| 661 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 662 | I915_READ(GEN6_PMIIR)); |
| 663 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 664 | I915_READ(GEN6_PMIMR)); |
| 665 | |
| 666 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 667 | I915_READ(PORT_HOTPLUG_EN)); |
| 668 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 669 | I915_READ(VLV_DPFLIPSTAT)); |
| 670 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 671 | I915_READ(DPINVGTT)); |
| 672 | |
| 673 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 674 | seq_printf(m, "Interrupt enable: %08x\n", |
| 675 | I915_READ(IER)); |
| 676 | seq_printf(m, "Interrupt identity: %08x\n", |
| 677 | I915_READ(IIR)); |
| 678 | seq_printf(m, "Interrupt mask: %08x\n", |
| 679 | I915_READ(IMR)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 680 | for_each_pipe(pipe) |
| 681 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 682 | pipe_name(pipe), |
| 683 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 684 | } else { |
| 685 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 686 | I915_READ(DEIER)); |
| 687 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 688 | I915_READ(DEIIR)); |
| 689 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 690 | I915_READ(DEIMR)); |
| 691 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 692 | I915_READ(SDEIER)); |
| 693 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 694 | I915_READ(SDEIIR)); |
| 695 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 696 | I915_READ(SDEIMR)); |
| 697 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 698 | I915_READ(GTIER)); |
| 699 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 700 | I915_READ(GTIIR)); |
| 701 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 702 | I915_READ(GTIMR)); |
| 703 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 704 | seq_printf(m, "Interrupts received: %d\n", |
| 705 | atomic_read(&dev_priv->irq_received)); |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 706 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame^] | 707 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 708 | seq_printf(m, |
| 709 | "Graphics Interrupt mask (%s): %08x\n", |
| 710 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 711 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 712 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 713 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 714 | mutex_unlock(&dev->struct_mutex); |
| 715 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 716 | return 0; |
| 717 | } |
| 718 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 719 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 720 | { |
| 721 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 722 | struct drm_device *dev = node->minor->dev; |
| 723 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 724 | int i, ret; |
| 725 | |
| 726 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 727 | if (ret) |
| 728 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 729 | |
| 730 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 731 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 732 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 733 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 734 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 735 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 736 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 737 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 738 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 739 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 740 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 741 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 742 | } |
| 743 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 744 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 745 | return 0; |
| 746 | } |
| 747 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 748 | static int i915_hws_info(struct seq_file *m, void *data) |
| 749 | { |
| 750 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 751 | struct drm_device *dev = node->minor->dev; |
| 752 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 753 | struct intel_ring_buffer *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 754 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 755 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 756 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 757 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 758 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 759 | if (hws == NULL) |
| 760 | return 0; |
| 761 | |
| 762 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 763 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 764 | i * 4, |
| 765 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 766 | } |
| 767 | return 0; |
| 768 | } |
| 769 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 770 | static ssize_t |
| 771 | i915_error_state_write(struct file *filp, |
| 772 | const char __user *ubuf, |
| 773 | size_t cnt, |
| 774 | loff_t *ppos) |
| 775 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 776 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 777 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 778 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 779 | |
| 780 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 781 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 782 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 783 | if (ret) |
| 784 | return ret; |
| 785 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 786 | i915_destroy_error_state(dev); |
| 787 | mutex_unlock(&dev->struct_mutex); |
| 788 | |
| 789 | return cnt; |
| 790 | } |
| 791 | |
| 792 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 793 | { |
| 794 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 795 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 796 | |
| 797 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 798 | if (!error_priv) |
| 799 | return -ENOMEM; |
| 800 | |
| 801 | error_priv->dev = dev; |
| 802 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 803 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 804 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 805 | file->private_data = error_priv; |
| 806 | |
| 807 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 808 | } |
| 809 | |
| 810 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 811 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 812 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 813 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 814 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 815 | kfree(error_priv); |
| 816 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 821 | size_t count, loff_t *pos) |
| 822 | { |
| 823 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 824 | struct drm_i915_error_state_buf error_str; |
| 825 | loff_t tmp_pos = 0; |
| 826 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 827 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 828 | |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 829 | ret = i915_error_state_buf_init(&error_str, count, *pos); |
| 830 | if (ret) |
| 831 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 832 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 833 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 834 | if (ret) |
| 835 | goto out; |
| 836 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 837 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 838 | error_str.buf, |
| 839 | error_str.bytes); |
| 840 | |
| 841 | if (ret_count < 0) |
| 842 | ret = ret_count; |
| 843 | else |
| 844 | *pos = error_str.start + ret_count; |
| 845 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 846 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 847 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 848 | } |
| 849 | |
| 850 | static const struct file_operations i915_error_state_fops = { |
| 851 | .owner = THIS_MODULE, |
| 852 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 853 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 854 | .write = i915_error_state_write, |
| 855 | .llseek = default_llseek, |
| 856 | .release = i915_error_state_release, |
| 857 | }; |
| 858 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 859 | static int |
| 860 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 861 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 862 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 863 | drm_i915_private_t *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 864 | int ret; |
| 865 | |
| 866 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 867 | if (ret) |
| 868 | return ret; |
| 869 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 870 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 871 | mutex_unlock(&dev->struct_mutex); |
| 872 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 873 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 874 | } |
| 875 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 876 | static int |
| 877 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 878 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 879 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 880 | int ret; |
| 881 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 882 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 883 | if (ret) |
| 884 | return ret; |
| 885 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 886 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 887 | mutex_unlock(&dev->struct_mutex); |
| 888 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 889 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 890 | } |
| 891 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 892 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 893 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 894 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 895 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 896 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
| 897 | { |
| 898 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 899 | struct drm_device *dev = node->minor->dev; |
| 900 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 901 | u16 crstanddelay; |
| 902 | int ret; |
| 903 | |
| 904 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 905 | if (ret) |
| 906 | return ret; |
| 907 | |
| 908 | crstanddelay = I915_READ16(CRSTANDVID); |
| 909 | |
| 910 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 911 | |
| 912 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) |
| 918 | { |
| 919 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 920 | struct drm_device *dev = node->minor->dev; |
| 921 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 922 | int ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 923 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 924 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 925 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 926 | if (IS_GEN5(dev)) { |
| 927 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 928 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 929 | |
| 930 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 931 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 932 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 933 | MEMSTAT_VID_SHIFT); |
| 934 | seq_printf(m, "Current P-state: %d\n", |
| 935 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 936 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 937 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 938 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 939 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 940 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 941 | u32 rpupei, rpcurup, rpprevup; |
| 942 | u32 rpdownei, rpcurdown, rpprevdown; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 943 | int max_freq; |
| 944 | |
| 945 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 947 | if (ret) |
| 948 | return ret; |
| 949 | |
Ben Widawsky | fcca792 | 2011-04-25 11:23:07 -0700 | [diff] [blame] | 950 | gen6_gt_force_wake_get(dev_priv); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 951 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 952 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 953 | reqf &= ~GEN6_TURBO_DISABLE; |
| 954 | if (IS_HASWELL(dev)) |
| 955 | reqf >>= 24; |
| 956 | else |
| 957 | reqf >>= 25; |
| 958 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 959 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 960 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 961 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 962 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 963 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 964 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 965 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 966 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 967 | if (IS_HASWELL(dev)) |
| 968 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 969 | else |
| 970 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 971 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 972 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 973 | gen6_gt_force_wake_put(dev_priv); |
| 974 | mutex_unlock(&dev->struct_mutex); |
| 975 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 976 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 977 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 978 | seq_printf(m, "Render p-state ratio: %d\n", |
| 979 | (gt_perf_status & 0xff00) >> 8); |
| 980 | seq_printf(m, "Render p-state VID: %d\n", |
| 981 | gt_perf_status & 0xff); |
| 982 | seq_printf(m, "Render p-state limit: %d\n", |
| 983 | rp_state_limits & 0xff); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 984 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 985 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 986 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 987 | GEN6_CURICONT_MASK); |
| 988 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 989 | GEN6_CURBSYTAVG_MASK); |
| 990 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 991 | GEN6_CURBSYTAVG_MASK); |
| 992 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 993 | GEN6_CURIAVG_MASK); |
| 994 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 995 | GEN6_CURBSYTAVG_MASK); |
| 996 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 997 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 998 | |
| 999 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1000 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1001 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1002 | |
| 1003 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1004 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1005 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1006 | |
| 1007 | max_freq = rp_state_cap & 0xff; |
| 1008 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1009 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1010 | |
| 1011 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
| 1012 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1013 | } else if (IS_VALLEYVIEW(dev)) { |
| 1014 | u32 freq_sts, val; |
| 1015 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1016 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1017 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1018 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1019 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1020 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1021 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1022 | seq_printf(m, "max GPU freq: %d MHz\n", |
| 1023 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 1024 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1025 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1026 | seq_printf(m, "min GPU freq: %d MHz\n", |
| 1027 | vlv_gpu_freq(dev_priv->mem_freq, val)); |
| 1028 | |
| 1029 | seq_printf(m, "current GPU freq: %d MHz\n", |
| 1030 | vlv_gpu_freq(dev_priv->mem_freq, |
| 1031 | (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1032 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1033 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1034 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1035 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1036 | |
| 1037 | return 0; |
| 1038 | } |
| 1039 | |
| 1040 | static int i915_delayfreq_table(struct seq_file *m, void *unused) |
| 1041 | { |
| 1042 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1043 | struct drm_device *dev = node->minor->dev; |
| 1044 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1045 | u32 delayfreq; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1046 | int ret, i; |
| 1047 | |
| 1048 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1049 | if (ret) |
| 1050 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1051 | |
| 1052 | for (i = 0; i < 16; i++) { |
| 1053 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1054 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
| 1055 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1056 | } |
| 1057 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1058 | mutex_unlock(&dev->struct_mutex); |
| 1059 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1060 | return 0; |
| 1061 | } |
| 1062 | |
| 1063 | static inline int MAP_TO_MV(int map) |
| 1064 | { |
| 1065 | return 1250 - (map * 25); |
| 1066 | } |
| 1067 | |
| 1068 | static int i915_inttoext_table(struct seq_file *m, void *unused) |
| 1069 | { |
| 1070 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1071 | struct drm_device *dev = node->minor->dev; |
| 1072 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1073 | u32 inttoext; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1074 | int ret, i; |
| 1075 | |
| 1076 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1077 | if (ret) |
| 1078 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1079 | |
| 1080 | for (i = 1; i <= 32; i++) { |
| 1081 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); |
| 1082 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); |
| 1083 | } |
| 1084 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1085 | mutex_unlock(&dev->struct_mutex); |
| 1086 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1087 | return 0; |
| 1088 | } |
| 1089 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1090 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1091 | { |
| 1092 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1093 | struct drm_device *dev = node->minor->dev; |
| 1094 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1095 | u32 rgvmodectl, rstdbyctl; |
| 1096 | u16 crstandvid; |
| 1097 | int ret; |
| 1098 | |
| 1099 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1100 | if (ret) |
| 1101 | return ret; |
| 1102 | |
| 1103 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1104 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1105 | crstandvid = I915_READ16(CRSTANDVID); |
| 1106 | |
| 1107 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1108 | |
| 1109 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1110 | "yes" : "no"); |
| 1111 | seq_printf(m, "Boost freq: %d\n", |
| 1112 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1113 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1114 | seq_printf(m, "HW control enabled: %s\n", |
| 1115 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1116 | seq_printf(m, "SW control enabled: %s\n", |
| 1117 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1118 | seq_printf(m, "Gated voltage change: %s\n", |
| 1119 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1120 | seq_printf(m, "Starting frequency: P%d\n", |
| 1121 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1122 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1123 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1124 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1125 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1126 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1127 | seq_printf(m, "Render standby enabled: %s\n", |
| 1128 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1129 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1130 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1131 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1132 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1133 | break; |
| 1134 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1135 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1136 | break; |
| 1137 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1138 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1139 | break; |
| 1140 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1141 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1142 | break; |
| 1143 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1144 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1145 | break; |
| 1146 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1147 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1148 | break; |
| 1149 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1150 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1151 | break; |
| 1152 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1153 | |
| 1154 | return 0; |
| 1155 | } |
| 1156 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1157 | static int gen6_drpc_info(struct seq_file *m) |
| 1158 | { |
| 1159 | |
| 1160 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1161 | struct drm_device *dev = node->minor->dev; |
| 1162 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1163 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1164 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1165 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1166 | |
| 1167 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1168 | if (ret) |
| 1169 | return ret; |
| 1170 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1171 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1172 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1173 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1174 | |
| 1175 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1176 | seq_puts(m, "RC information inaccurate because somebody " |
| 1177 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1178 | } else { |
| 1179 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1180 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1181 | udelay(10); |
| 1182 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1183 | } |
| 1184 | |
| 1185 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1186 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1187 | |
| 1188 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1189 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1190 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1191 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1192 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1193 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1194 | |
| 1195 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1196 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1197 | seq_printf(m, "HW control enabled: %s\n", |
| 1198 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1199 | seq_printf(m, "SW control enabled: %s\n", |
| 1200 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1201 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1202 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1203 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1204 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1205 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1206 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1207 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1208 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1209 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1210 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1211 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1212 | case GEN6_RC0: |
| 1213 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1214 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1215 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1216 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1217 | break; |
| 1218 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1219 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1220 | break; |
| 1221 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1222 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1223 | break; |
| 1224 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1225 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1226 | break; |
| 1227 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1228 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1229 | break; |
| 1230 | } |
| 1231 | |
| 1232 | seq_printf(m, "Core Power Down: %s\n", |
| 1233 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1234 | |
| 1235 | /* Not exactly sure what this is */ |
| 1236 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1237 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1238 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1239 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1240 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1241 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1242 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1243 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1244 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1245 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1246 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1247 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1248 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1249 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1250 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1251 | return 0; |
| 1252 | } |
| 1253 | |
| 1254 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1255 | { |
| 1256 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1257 | struct drm_device *dev = node->minor->dev; |
| 1258 | |
| 1259 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 1260 | return gen6_drpc_info(m); |
| 1261 | else |
| 1262 | return ironlake_drpc_info(m); |
| 1263 | } |
| 1264 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1265 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1266 | { |
| 1267 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1268 | struct drm_device *dev = node->minor->dev; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1269 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1270 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1271 | if (!I915_HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1272 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1273 | return 0; |
| 1274 | } |
| 1275 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1276 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1277 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1278 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1279 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1280 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1281 | case FBC_OK: |
| 1282 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1283 | break; |
| 1284 | case FBC_UNSUPPORTED: |
| 1285 | seq_puts(m, "unsupported by this chipset"); |
| 1286 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1287 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1288 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1289 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1290 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1291 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1292 | break; |
| 1293 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1294 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1295 | break; |
| 1296 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1297 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1298 | break; |
| 1299 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1300 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1301 | break; |
| 1302 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1303 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1304 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1305 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1306 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1307 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1308 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1309 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1310 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1311 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1312 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1313 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1314 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1315 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1316 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1317 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1318 | } |
| 1319 | return 0; |
| 1320 | } |
| 1321 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1322 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1323 | { |
| 1324 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1325 | struct drm_device *dev = node->minor->dev; |
| 1326 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1327 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1328 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1329 | seq_puts(m, "not supported\n"); |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
| 1333 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1334 | seq_puts(m, "enabled\n"); |
| 1335 | else |
| 1336 | seq_puts(m, "disabled\n"); |
| 1337 | |
| 1338 | return 0; |
| 1339 | } |
| 1340 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1341 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1342 | { |
| 1343 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1344 | struct drm_device *dev = node->minor->dev; |
| 1345 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1346 | bool sr_enabled = false; |
| 1347 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1348 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1349 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1350 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1351 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1352 | else if (IS_I915GM(dev)) |
| 1353 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1354 | else if (IS_PINEVIEW(dev)) |
| 1355 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1356 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1357 | seq_printf(m, "self-refresh: %s\n", |
| 1358 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1359 | |
| 1360 | return 0; |
| 1361 | } |
| 1362 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1363 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1364 | { |
| 1365 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1366 | struct drm_device *dev = node->minor->dev; |
| 1367 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1368 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1369 | int ret; |
| 1370 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1371 | if (!IS_GEN5(dev)) |
| 1372 | return -ENODEV; |
| 1373 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1374 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1375 | if (ret) |
| 1376 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1377 | |
| 1378 | temp = i915_mch_val(dev_priv); |
| 1379 | chipset = i915_chipset_val(dev_priv); |
| 1380 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1381 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1382 | |
| 1383 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1384 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1385 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1386 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1387 | |
| 1388 | return 0; |
| 1389 | } |
| 1390 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1391 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1392 | { |
| 1393 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1394 | struct drm_device *dev = node->minor->dev; |
| 1395 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1396 | int ret; |
| 1397 | int gpu_freq, ia_freq; |
| 1398 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1399 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1400 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1401 | return 0; |
| 1402 | } |
| 1403 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1404 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1405 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1406 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1407 | if (ret) |
| 1408 | return ret; |
| 1409 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1410 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1411 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1412 | for (gpu_freq = dev_priv->rps.min_delay; |
| 1413 | gpu_freq <= dev_priv->rps.max_delay; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1414 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1415 | ia_freq = gpu_freq; |
| 1416 | sandybridge_pcode_read(dev_priv, |
| 1417 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1418 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1419 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1420 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1421 | ((ia_freq >> 0) & 0xff) * 100, |
| 1422 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1423 | } |
| 1424 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1425 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1426 | |
| 1427 | return 0; |
| 1428 | } |
| 1429 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1430 | static int i915_gfxec(struct seq_file *m, void *unused) |
| 1431 | { |
| 1432 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1433 | struct drm_device *dev = node->minor->dev; |
| 1434 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1435 | int ret; |
| 1436 | |
| 1437 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1438 | if (ret) |
| 1439 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1440 | |
| 1441 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); |
| 1442 | |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1443 | mutex_unlock(&dev->struct_mutex); |
| 1444 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1445 | return 0; |
| 1446 | } |
| 1447 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1448 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1449 | { |
| 1450 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1451 | struct drm_device *dev = node->minor->dev; |
| 1452 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1453 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1454 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1455 | int ret; |
| 1456 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1457 | if (data == NULL) |
| 1458 | return -ENOMEM; |
| 1459 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1460 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1461 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1462 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1463 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1464 | if (opregion->header) { |
| 1465 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1466 | seq_write(m, data, OPREGION_SIZE); |
| 1467 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1468 | |
| 1469 | mutex_unlock(&dev->struct_mutex); |
| 1470 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1471 | out: |
| 1472 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1473 | return 0; |
| 1474 | } |
| 1475 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1476 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1477 | { |
| 1478 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1479 | struct drm_device *dev = node->minor->dev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1480 | struct intel_fbdev *ifbdev = NULL; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1481 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1482 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1483 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1484 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1485 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1486 | if (ret) |
| 1487 | return ret; |
| 1488 | |
| 1489 | ifbdev = dev_priv->fbdev; |
| 1490 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1491 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1492 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1493 | fb->base.width, |
| 1494 | fb->base.height, |
| 1495 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1496 | fb->base.bits_per_pixel, |
| 1497 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1498 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1499 | seq_putc(m, '\n'); |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1500 | mutex_unlock(&dev->mode_config.mutex); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1501 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1502 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1503 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1504 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
Daniel Vetter | 131a56d | 2013-10-17 14:35:31 +0200 | [diff] [blame] | 1505 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1506 | continue; |
| 1507 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1508 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1509 | fb->base.width, |
| 1510 | fb->base.height, |
| 1511 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1512 | fb->base.bits_per_pixel, |
| 1513 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1514 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1515 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1516 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1517 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1518 | |
| 1519 | return 0; |
| 1520 | } |
| 1521 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1522 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1523 | { |
| 1524 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1525 | struct drm_device *dev = node->minor->dev; |
| 1526 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1527 | struct intel_ring_buffer *ring; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1528 | struct i915_hw_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1529 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1530 | |
| 1531 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); |
| 1532 | if (ret) |
| 1533 | return ret; |
| 1534 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1535 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1536 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1537 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1538 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1539 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1540 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1541 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1542 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1543 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1544 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1545 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1546 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1547 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
| 1548 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1549 | describe_ctx(m, ctx); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1550 | for_each_ring(ring, dev_priv, i) |
| 1551 | if (ring->default_context == ctx) |
| 1552 | seq_printf(m, "(default context %s) ", ring->name); |
| 1553 | |
| 1554 | describe_obj(m, ctx->obj); |
| 1555 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1556 | } |
| 1557 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1558 | mutex_unlock(&dev->mode_config.mutex); |
| 1559 | |
| 1560 | return 0; |
| 1561 | } |
| 1562 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1563 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1564 | { |
| 1565 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1566 | struct drm_device *dev = node->minor->dev; |
| 1567 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1568 | unsigned forcewake_count; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1569 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1570 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1571 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1572 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1573 | |
| 1574 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1575 | |
| 1576 | return 0; |
| 1577 | } |
| 1578 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1579 | static const char *swizzle_string(unsigned swizzle) |
| 1580 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1581 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1582 | case I915_BIT_6_SWIZZLE_NONE: |
| 1583 | return "none"; |
| 1584 | case I915_BIT_6_SWIZZLE_9: |
| 1585 | return "bit9"; |
| 1586 | case I915_BIT_6_SWIZZLE_9_10: |
| 1587 | return "bit9/bit10"; |
| 1588 | case I915_BIT_6_SWIZZLE_9_11: |
| 1589 | return "bit9/bit11"; |
| 1590 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1591 | return "bit9/bit10/bit11"; |
| 1592 | case I915_BIT_6_SWIZZLE_9_17: |
| 1593 | return "bit9/bit17"; |
| 1594 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1595 | return "bit9/bit10/bit17"; |
| 1596 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1597 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1598 | } |
| 1599 | |
| 1600 | return "bug"; |
| 1601 | } |
| 1602 | |
| 1603 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1604 | { |
| 1605 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1606 | struct drm_device *dev = node->minor->dev; |
| 1607 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1608 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1609 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1610 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1611 | if (ret) |
| 1612 | return ret; |
| 1613 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1614 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1615 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1616 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1617 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1618 | |
| 1619 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 1620 | seq_printf(m, "DDC = 0x%08x\n", |
| 1621 | I915_READ(DCC)); |
| 1622 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 1623 | I915_READ16(C0DRB3)); |
| 1624 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 1625 | I915_READ16(C1DRB3)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 1626 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1627 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 1628 | I915_READ(MAD_DIMM_C0)); |
| 1629 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 1630 | I915_READ(MAD_DIMM_C1)); |
| 1631 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 1632 | I915_READ(MAD_DIMM_C2)); |
| 1633 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 1634 | I915_READ(TILECTL)); |
| 1635 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 1636 | I915_READ(ARB_MODE)); |
| 1637 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 1638 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1639 | } |
| 1640 | mutex_unlock(&dev->struct_mutex); |
| 1641 | |
| 1642 | return 0; |
| 1643 | } |
| 1644 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1645 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 1646 | { |
| 1647 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1648 | struct drm_device *dev = node->minor->dev; |
| 1649 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1650 | struct intel_ring_buffer *ring; |
| 1651 | int i, ret; |
| 1652 | |
| 1653 | |
| 1654 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1655 | if (ret) |
| 1656 | return ret; |
| 1657 | if (INTEL_INFO(dev)->gen == 6) |
| 1658 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 1659 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 1660 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1661 | seq_printf(m, "%s\n", ring->name); |
| 1662 | if (INTEL_INFO(dev)->gen == 7) |
| 1663 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 1664 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 1665 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 1666 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 1667 | } |
| 1668 | if (dev_priv->mm.aliasing_ppgtt) { |
| 1669 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1670 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1671 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 1672 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
| 1673 | } |
| 1674 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
| 1675 | mutex_unlock(&dev->struct_mutex); |
| 1676 | |
| 1677 | return 0; |
| 1678 | } |
| 1679 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1680 | static int i915_dpio_info(struct seq_file *m, void *data) |
| 1681 | { |
| 1682 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1683 | struct drm_device *dev = node->minor->dev; |
| 1684 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1685 | int ret; |
| 1686 | |
| 1687 | |
| 1688 | if (!IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1689 | seq_puts(m, "unsupported\n"); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1690 | return 0; |
| 1691 | } |
| 1692 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1693 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1694 | if (ret) |
| 1695 | return ret; |
| 1696 | |
| 1697 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); |
| 1698 | |
| 1699 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1700 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1701 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1702 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1703 | |
| 1704 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1705 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1706 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1707 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1708 | |
| 1709 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1710 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1711 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1712 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1713 | |
Ville Syrjälä | 4abb2c3 | 2013-06-14 14:02:53 +0300 | [diff] [blame] | 1714 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1715 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
Ville Syrjälä | 4abb2c3 | 2013-06-14 14:02:53 +0300 | [diff] [blame] | 1716 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1717 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1718 | |
| 1719 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1720 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1721 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1722 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 1723 | |
| 1724 | return 0; |
| 1725 | } |
| 1726 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 1727 | static int i915_llc(struct seq_file *m, void *data) |
| 1728 | { |
| 1729 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1730 | struct drm_device *dev = node->minor->dev; |
| 1731 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1732 | |
| 1733 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 1734 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 1735 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 1736 | |
| 1737 | return 0; |
| 1738 | } |
| 1739 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1740 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 1741 | { |
| 1742 | struct drm_info_node *node = m->private; |
| 1743 | struct drm_device *dev = node->minor->dev; |
| 1744 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1745 | u32 psrperf = 0; |
| 1746 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1747 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1748 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 1749 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1750 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1751 | enabled = HAS_PSR(dev) && |
| 1752 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
| 1753 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1754 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1755 | if (HAS_PSR(dev)) |
| 1756 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
| 1757 | EDP_PSR_PERF_CNT_MASK; |
| 1758 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 1759 | |
| 1760 | return 0; |
| 1761 | } |
| 1762 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1763 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 1764 | { |
| 1765 | struct drm_info_node *node = m->private; |
| 1766 | struct drm_device *dev = node->minor->dev; |
| 1767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1768 | u64 power; |
| 1769 | u32 units; |
| 1770 | |
| 1771 | if (INTEL_INFO(dev)->gen < 6) |
| 1772 | return -ENODEV; |
| 1773 | |
| 1774 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 1775 | power = (power & 0x1f00) >> 8; |
| 1776 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 1777 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 1778 | power *= units; |
| 1779 | |
| 1780 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 1781 | |
| 1782 | return 0; |
| 1783 | } |
| 1784 | |
| 1785 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 1786 | { |
| 1787 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1788 | struct drm_device *dev = node->minor->dev; |
| 1789 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1790 | |
| 1791 | if (!IS_HASWELL(dev)) { |
| 1792 | seq_puts(m, "not supported\n"); |
| 1793 | return 0; |
| 1794 | } |
| 1795 | |
| 1796 | mutex_lock(&dev_priv->pc8.lock); |
| 1797 | seq_printf(m, "Requirements met: %s\n", |
| 1798 | yesno(dev_priv->pc8.requirements_met)); |
| 1799 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); |
| 1800 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); |
| 1801 | seq_printf(m, "IRQs disabled: %s\n", |
| 1802 | yesno(dev_priv->pc8.irqs_disabled)); |
| 1803 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); |
| 1804 | mutex_unlock(&dev_priv->pc8.lock); |
| 1805 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 1806 | return 0; |
| 1807 | } |
| 1808 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1809 | struct pipe_crc_info { |
| 1810 | const char *name; |
| 1811 | struct drm_device *dev; |
| 1812 | enum pipe pipe; |
| 1813 | }; |
| 1814 | |
| 1815 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1816 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 1817 | struct pipe_crc_info *info = inode->i_private; |
| 1818 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 1819 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 1820 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1821 | spin_lock_irq(&pipe_crc->lock); |
| 1822 | |
| 1823 | if (pipe_crc->opened) { |
| 1824 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 1825 | return -EBUSY; /* already open */ |
| 1826 | } |
| 1827 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1828 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1829 | filep->private_data = inode->i_private; |
| 1830 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1831 | spin_unlock_irq(&pipe_crc->lock); |
| 1832 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1833 | return 0; |
| 1834 | } |
| 1835 | |
| 1836 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 1837 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 1838 | struct pipe_crc_info *info = inode->i_private; |
| 1839 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 1840 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 1841 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1842 | spin_lock_irq(&pipe_crc->lock); |
| 1843 | pipe_crc->opened = false; |
| 1844 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 1845 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1846 | return 0; |
| 1847 | } |
| 1848 | |
| 1849 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 1850 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 1851 | /* account for \'0' */ |
| 1852 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 1853 | |
| 1854 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 1855 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1856 | assert_spin_locked(&pipe_crc->lock); |
| 1857 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 1858 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1859 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1860 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1861 | static ssize_t |
| 1862 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 1863 | loff_t *pos) |
| 1864 | { |
| 1865 | struct pipe_crc_info *info = filep->private_data; |
| 1866 | struct drm_device *dev = info->dev; |
| 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1868 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 1869 | char buf[PIPE_CRC_BUFFER_LEN]; |
| 1870 | int head, tail, n_entries, n; |
| 1871 | ssize_t bytes_read; |
| 1872 | |
| 1873 | /* |
| 1874 | * Don't allow user space to provide buffers not big enough to hold |
| 1875 | * a line of data. |
| 1876 | */ |
| 1877 | if (count < PIPE_CRC_LINE_LEN) |
| 1878 | return -EINVAL; |
| 1879 | |
| 1880 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 1881 | return 0; |
| 1882 | |
| 1883 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1884 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1885 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1886 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1887 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1888 | if (filep->f_flags & O_NONBLOCK) { |
| 1889 | spin_unlock_irq(&pipe_crc->lock); |
| 1890 | return -EAGAIN; |
| 1891 | } |
| 1892 | |
| 1893 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 1894 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 1895 | if (ret) { |
| 1896 | spin_unlock_irq(&pipe_crc->lock); |
| 1897 | return ret; |
| 1898 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1899 | } |
| 1900 | |
| 1901 | /* We now have one or more entries to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1902 | head = pipe_crc->head; |
| 1903 | tail = pipe_crc->tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1904 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
| 1905 | count / PIPE_CRC_LINE_LEN); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1906 | spin_unlock_irq(&pipe_crc->lock); |
| 1907 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1908 | bytes_read = 0; |
| 1909 | n = 0; |
| 1910 | do { |
| 1911 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
| 1912 | int ret; |
| 1913 | |
| 1914 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 1915 | "%8u %8x %8x %8x %8x %8x\n", |
| 1916 | entry->frame, entry->crc[0], |
| 1917 | entry->crc[1], entry->crc[2], |
| 1918 | entry->crc[3], entry->crc[4]); |
| 1919 | |
| 1920 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, |
| 1921 | buf, PIPE_CRC_LINE_LEN); |
| 1922 | if (ret == PIPE_CRC_LINE_LEN) |
| 1923 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1924 | |
| 1925 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 1926 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1927 | n++; |
| 1928 | } while (--n_entries); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1929 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1930 | spin_lock_irq(&pipe_crc->lock); |
| 1931 | pipe_crc->tail = tail; |
| 1932 | spin_unlock_irq(&pipe_crc->lock); |
| 1933 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1934 | return bytes_read; |
| 1935 | } |
| 1936 | |
| 1937 | static const struct file_operations i915_pipe_crc_fops = { |
| 1938 | .owner = THIS_MODULE, |
| 1939 | .open = i915_pipe_crc_open, |
| 1940 | .read = i915_pipe_crc_read, |
| 1941 | .release = i915_pipe_crc_release, |
| 1942 | }; |
| 1943 | |
| 1944 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 1945 | { |
| 1946 | .name = "i915_pipe_A_crc", |
| 1947 | .pipe = PIPE_A, |
| 1948 | }, |
| 1949 | { |
| 1950 | .name = "i915_pipe_B_crc", |
| 1951 | .pipe = PIPE_B, |
| 1952 | }, |
| 1953 | { |
| 1954 | .name = "i915_pipe_C_crc", |
| 1955 | .pipe = PIPE_C, |
| 1956 | }, |
| 1957 | }; |
| 1958 | |
| 1959 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 1960 | enum pipe pipe) |
| 1961 | { |
| 1962 | struct drm_device *dev = minor->dev; |
| 1963 | struct dentry *ent; |
| 1964 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 1965 | |
| 1966 | info->dev = dev; |
| 1967 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 1968 | &i915_pipe_crc_fops); |
| 1969 | if (IS_ERR(ent)) |
| 1970 | return PTR_ERR(ent); |
| 1971 | |
| 1972 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1973 | } |
| 1974 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 1975 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1976 | "none", |
| 1977 | "plane1", |
| 1978 | "plane2", |
| 1979 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1980 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 1981 | "TV", |
| 1982 | "DP-B", |
| 1983 | "DP-C", |
| 1984 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 1985 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1986 | }; |
| 1987 | |
| 1988 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 1989 | { |
| 1990 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 1991 | return pipe_crc_sources[source]; |
| 1992 | } |
| 1993 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 1994 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1995 | { |
| 1996 | struct drm_device *dev = m->private; |
| 1997 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1998 | int i; |
| 1999 | |
| 2000 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 2001 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 2002 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 2003 | |
| 2004 | return 0; |
| 2005 | } |
| 2006 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2007 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2008 | { |
| 2009 | struct drm_device *dev = inode->i_private; |
| 2010 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2011 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2012 | } |
| 2013 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2014 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2015 | uint32_t *val) |
| 2016 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2017 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2018 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2019 | |
| 2020 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2021 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2022 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 2023 | break; |
| 2024 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2025 | *val = 0; |
| 2026 | break; |
| 2027 | default: |
| 2028 | return -EINVAL; |
| 2029 | } |
| 2030 | |
| 2031 | return 0; |
| 2032 | } |
| 2033 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2034 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 2035 | enum intel_pipe_crc_source *source) |
| 2036 | { |
| 2037 | struct intel_encoder *encoder; |
| 2038 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2039 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2040 | int ret = 0; |
| 2041 | |
| 2042 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2043 | |
| 2044 | mutex_lock(&dev->mode_config.mutex); |
| 2045 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 2046 | base.head) { |
| 2047 | if (!encoder->base.crtc) |
| 2048 | continue; |
| 2049 | |
| 2050 | crtc = to_intel_crtc(encoder->base.crtc); |
| 2051 | |
| 2052 | if (crtc->pipe != pipe) |
| 2053 | continue; |
| 2054 | |
| 2055 | switch (encoder->type) { |
| 2056 | case INTEL_OUTPUT_TVOUT: |
| 2057 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 2058 | break; |
| 2059 | case INTEL_OUTPUT_DISPLAYPORT: |
| 2060 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 2061 | dig_port = enc_to_dig_port(&encoder->base); |
| 2062 | switch (dig_port->port) { |
| 2063 | case PORT_B: |
| 2064 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 2065 | break; |
| 2066 | case PORT_C: |
| 2067 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 2068 | break; |
| 2069 | case PORT_D: |
| 2070 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 2071 | break; |
| 2072 | default: |
| 2073 | WARN(1, "nonexisting DP port %c\n", |
| 2074 | port_name(dig_port->port)); |
| 2075 | break; |
| 2076 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2077 | break; |
| 2078 | } |
| 2079 | } |
| 2080 | mutex_unlock(&dev->mode_config.mutex); |
| 2081 | |
| 2082 | return ret; |
| 2083 | } |
| 2084 | |
| 2085 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 2086 | enum pipe pipe, |
| 2087 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2088 | uint32_t *val) |
| 2089 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2090 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2091 | bool need_stable_symbols = false; |
| 2092 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2093 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 2094 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 2095 | if (ret) |
| 2096 | return ret; |
| 2097 | } |
| 2098 | |
| 2099 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2100 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2101 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 2102 | break; |
| 2103 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 2104 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2105 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2106 | break; |
| 2107 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 2108 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2109 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2110 | break; |
| 2111 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2112 | *val = 0; |
| 2113 | break; |
| 2114 | default: |
| 2115 | return -EINVAL; |
| 2116 | } |
| 2117 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2118 | /* |
| 2119 | * When the pipe CRC tap point is after the transcoders we need |
| 2120 | * to tweak symbol-level features to produce a deterministic series of |
| 2121 | * symbols for a given frame. We need to reset those features only once |
| 2122 | * a frame (instead of every nth symbol): |
| 2123 | * - DC-balance: used to ensure a better clock recovery from the data |
| 2124 | * link (SDVO) |
| 2125 | * - DisplayPort scrambling: used for EMI reduction |
| 2126 | */ |
| 2127 | if (need_stable_symbols) { |
| 2128 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2129 | |
| 2130 | WARN_ON(!IS_G4X(dev)); |
| 2131 | |
| 2132 | tmp |= DC_BALANCE_RESET_VLV; |
| 2133 | if (pipe == PIPE_A) |
| 2134 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 2135 | else |
| 2136 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 2137 | |
| 2138 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2139 | } |
| 2140 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2141 | return 0; |
| 2142 | } |
| 2143 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2144 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2145 | enum pipe pipe, |
| 2146 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2147 | uint32_t *val) |
| 2148 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2150 | bool need_stable_symbols = false; |
| 2151 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2152 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 2153 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 2154 | if (ret) |
| 2155 | return ret; |
| 2156 | } |
| 2157 | |
| 2158 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2159 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2160 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 2161 | break; |
| 2162 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 2163 | if (!SUPPORTS_TV(dev)) |
| 2164 | return -EINVAL; |
| 2165 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 2166 | break; |
| 2167 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 2168 | if (!IS_G4X(dev)) |
| 2169 | return -EINVAL; |
| 2170 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2171 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2172 | break; |
| 2173 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 2174 | if (!IS_G4X(dev)) |
| 2175 | return -EINVAL; |
| 2176 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2177 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2178 | break; |
| 2179 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 2180 | if (!IS_G4X(dev)) |
| 2181 | return -EINVAL; |
| 2182 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2183 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2184 | break; |
| 2185 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 2186 | *val = 0; |
| 2187 | break; |
| 2188 | default: |
| 2189 | return -EINVAL; |
| 2190 | } |
| 2191 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2192 | /* |
| 2193 | * When the pipe CRC tap point is after the transcoders we need |
| 2194 | * to tweak symbol-level features to produce a deterministic series of |
| 2195 | * symbols for a given frame. We need to reset those features only once |
| 2196 | * a frame (instead of every nth symbol): |
| 2197 | * - DC-balance: used to ensure a better clock recovery from the data |
| 2198 | * link (SDVO) |
| 2199 | * - DisplayPort scrambling: used for EMI reduction |
| 2200 | */ |
| 2201 | if (need_stable_symbols) { |
| 2202 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2203 | |
| 2204 | WARN_ON(!IS_G4X(dev)); |
| 2205 | |
| 2206 | I915_WRITE(PORT_DFT_I9XX, |
| 2207 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 2208 | |
| 2209 | if (pipe == PIPE_A) |
| 2210 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 2211 | else |
| 2212 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 2213 | |
| 2214 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2215 | } |
| 2216 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2217 | return 0; |
| 2218 | } |
| 2219 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2220 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 2221 | enum pipe pipe) |
| 2222 | { |
| 2223 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2224 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2225 | |
| 2226 | if (pipe == PIPE_A) |
| 2227 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 2228 | else |
| 2229 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 2230 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 2231 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 2232 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2233 | |
| 2234 | } |
| 2235 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2236 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 2237 | enum pipe pipe) |
| 2238 | { |
| 2239 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2240 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 2241 | |
| 2242 | if (pipe == PIPE_A) |
| 2243 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 2244 | else |
| 2245 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 2246 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 2247 | |
| 2248 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 2249 | I915_WRITE(PORT_DFT_I9XX, |
| 2250 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 2251 | } |
| 2252 | } |
| 2253 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2254 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2255 | uint32_t *val) |
| 2256 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2257 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2258 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 2259 | |
| 2260 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2261 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 2262 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 2263 | break; |
| 2264 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 2265 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 2266 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2267 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 2268 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 2269 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2270 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2271 | *val = 0; |
| 2272 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2273 | default: |
| 2274 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2275 | } |
| 2276 | |
| 2277 | return 0; |
| 2278 | } |
| 2279 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2280 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2281 | uint32_t *val) |
| 2282 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2283 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 2284 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 2285 | |
| 2286 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2287 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 2288 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 2289 | break; |
| 2290 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 2291 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 2292 | break; |
| 2293 | case INTEL_PIPE_CRC_SOURCE_PF: |
| 2294 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 2295 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2296 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2297 | *val = 0; |
| 2298 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2299 | default: |
| 2300 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2301 | } |
| 2302 | |
| 2303 | return 0; |
| 2304 | } |
| 2305 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2306 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 2307 | enum intel_pipe_crc_source source) |
| 2308 | { |
| 2309 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2310 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2311 | u32 val; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2312 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2313 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2314 | if (pipe_crc->source == source) |
| 2315 | return 0; |
| 2316 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 2317 | /* forbid changing the source without going back to 'none' */ |
| 2318 | if (pipe_crc->source && source) |
| 2319 | return -EINVAL; |
| 2320 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2321 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2322 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 2323 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2324 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 2325 | else if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2326 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 2327 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2328 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2329 | else |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2330 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2331 | |
| 2332 | if (ret != 0) |
| 2333 | return ret; |
| 2334 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 2335 | /* none -> real source transition */ |
| 2336 | if (source) { |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 2337 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 2338 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 2339 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 2340 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
| 2341 | INTEL_PIPE_CRC_ENTRIES_NR, |
| 2342 | GFP_KERNEL); |
| 2343 | if (!pipe_crc->entries) |
| 2344 | return -ENOMEM; |
| 2345 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2346 | spin_lock_irq(&pipe_crc->lock); |
| 2347 | pipe_crc->head = 0; |
| 2348 | pipe_crc->tail = 0; |
| 2349 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 2350 | } |
| 2351 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 2352 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2353 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2354 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 2355 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 2356 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 2357 | /* real source -> none transition */ |
| 2358 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2359 | struct intel_pipe_crc_entry *entries; |
| 2360 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 2361 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 2362 | pipe_name(pipe)); |
| 2363 | |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 2364 | intel_wait_for_vblank(dev, pipe); |
| 2365 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2366 | spin_lock_irq(&pipe_crc->lock); |
| 2367 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 2368 | pipe_crc->entries = NULL; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2369 | spin_unlock_irq(&pipe_crc->lock); |
| 2370 | |
| 2371 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 2372 | |
| 2373 | if (IS_G4X(dev)) |
| 2374 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 2375 | else if (IS_VALLEYVIEW(dev)) |
| 2376 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 2377 | } |
| 2378 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2379 | return 0; |
| 2380 | } |
| 2381 | |
| 2382 | /* |
| 2383 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2384 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 2385 | * object: 'pipe' |
| 2386 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2387 | * source: (none | plane1 | plane2 | pf) |
| 2388 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 2389 | * |
| 2390 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2391 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 2392 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2393 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2394 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2395 | { |
| 2396 | int n_words = 0; |
| 2397 | |
| 2398 | while (*buf) { |
| 2399 | char *end; |
| 2400 | |
| 2401 | /* skip leading white space */ |
| 2402 | buf = skip_spaces(buf); |
| 2403 | if (!*buf) |
| 2404 | break; /* end of buffer */ |
| 2405 | |
| 2406 | /* find end of word */ |
| 2407 | for (end = buf; *end && !isspace(*end); end++) |
| 2408 | ; |
| 2409 | |
| 2410 | if (n_words == max_words) { |
| 2411 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 2412 | max_words); |
| 2413 | return -EINVAL; /* ran out of words[] before bytes */ |
| 2414 | } |
| 2415 | |
| 2416 | if (*end) |
| 2417 | *end++ = '\0'; |
| 2418 | words[n_words++] = buf; |
| 2419 | buf = end; |
| 2420 | } |
| 2421 | |
| 2422 | return n_words; |
| 2423 | } |
| 2424 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2425 | enum intel_pipe_crc_object { |
| 2426 | PIPE_CRC_OBJECT_PIPE, |
| 2427 | }; |
| 2428 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 2429 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2430 | "pipe", |
| 2431 | }; |
| 2432 | |
| 2433 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2434 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2435 | { |
| 2436 | int i; |
| 2437 | |
| 2438 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 2439 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2440 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2441 | return 0; |
| 2442 | } |
| 2443 | |
| 2444 | return -EINVAL; |
| 2445 | } |
| 2446 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2447 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2448 | { |
| 2449 | const char name = buf[0]; |
| 2450 | |
| 2451 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 2452 | return -EINVAL; |
| 2453 | |
| 2454 | *pipe = name - 'A'; |
| 2455 | |
| 2456 | return 0; |
| 2457 | } |
| 2458 | |
| 2459 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2460 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2461 | { |
| 2462 | int i; |
| 2463 | |
| 2464 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 2465 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2466 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2467 | return 0; |
| 2468 | } |
| 2469 | |
| 2470 | return -EINVAL; |
| 2471 | } |
| 2472 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2473 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2474 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2475 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2476 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2477 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2478 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2479 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2480 | enum intel_pipe_crc_source source; |
| 2481 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2482 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2483 | if (n_words != N_WORDS) { |
| 2484 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 2485 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2486 | return -EINVAL; |
| 2487 | } |
| 2488 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2489 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2490 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2491 | return -EINVAL; |
| 2492 | } |
| 2493 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2494 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2495 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 2496 | return -EINVAL; |
| 2497 | } |
| 2498 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2499 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 2500 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2501 | return -EINVAL; |
| 2502 | } |
| 2503 | |
| 2504 | return pipe_crc_set_source(dev, pipe, source); |
| 2505 | } |
| 2506 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2507 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 2508 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2509 | { |
| 2510 | struct seq_file *m = file->private_data; |
| 2511 | struct drm_device *dev = m->private; |
| 2512 | char *tmpbuf; |
| 2513 | int ret; |
| 2514 | |
| 2515 | if (len == 0) |
| 2516 | return 0; |
| 2517 | |
| 2518 | if (len > PAGE_SIZE - 1) { |
| 2519 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 2520 | PAGE_SIZE); |
| 2521 | return -E2BIG; |
| 2522 | } |
| 2523 | |
| 2524 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 2525 | if (!tmpbuf) |
| 2526 | return -ENOMEM; |
| 2527 | |
| 2528 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 2529 | ret = -EFAULT; |
| 2530 | goto out; |
| 2531 | } |
| 2532 | tmpbuf[len] = '\0'; |
| 2533 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2534 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2535 | |
| 2536 | out: |
| 2537 | kfree(tmpbuf); |
| 2538 | if (ret < 0) |
| 2539 | return ret; |
| 2540 | |
| 2541 | *offp += len; |
| 2542 | return len; |
| 2543 | } |
| 2544 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2545 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2546 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2547 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2548 | .read = seq_read, |
| 2549 | .llseek = seq_lseek, |
| 2550 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2551 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2552 | }; |
| 2553 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2554 | static int |
| 2555 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2556 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2557 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2558 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2559 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2560 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2561 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2562 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2563 | } |
| 2564 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2565 | static int |
| 2566 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2567 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2568 | struct drm_device *dev = data; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2569 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2570 | DRM_INFO("Manually setting wedged to %llu\n", val); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 2571 | i915_handle_error(dev, val); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2572 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2573 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2574 | } |
| 2575 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2576 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 2577 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2578 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 2579 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2580 | static int |
| 2581 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2582 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2583 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2584 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2585 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2586 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2587 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2588 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2589 | } |
| 2590 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2591 | static int |
| 2592 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2593 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2594 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2595 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2596 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2597 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2598 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2599 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2600 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2601 | if (ret) |
| 2602 | return ret; |
| 2603 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 2604 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2605 | mutex_unlock(&dev->struct_mutex); |
| 2606 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2607 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 2608 | } |
| 2609 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2610 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 2611 | i915_ring_stop_get, i915_ring_stop_set, |
| 2612 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 2613 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 2614 | static int |
| 2615 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 2616 | { |
| 2617 | struct drm_device *dev = data; |
| 2618 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2619 | |
| 2620 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 2621 | return 0; |
| 2622 | } |
| 2623 | |
| 2624 | static int |
| 2625 | i915_ring_missed_irq_set(void *data, u64 val) |
| 2626 | { |
| 2627 | struct drm_device *dev = data; |
| 2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2629 | int ret; |
| 2630 | |
| 2631 | /* Lock against concurrent debugfs callers */ |
| 2632 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2633 | if (ret) |
| 2634 | return ret; |
| 2635 | dev_priv->gpu_error.missed_irq_rings = val; |
| 2636 | mutex_unlock(&dev->struct_mutex); |
| 2637 | |
| 2638 | return 0; |
| 2639 | } |
| 2640 | |
| 2641 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 2642 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 2643 | "0x%08llx\n"); |
| 2644 | |
| 2645 | static int |
| 2646 | i915_ring_test_irq_get(void *data, u64 *val) |
| 2647 | { |
| 2648 | struct drm_device *dev = data; |
| 2649 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2650 | |
| 2651 | *val = dev_priv->gpu_error.test_irq_rings; |
| 2652 | |
| 2653 | return 0; |
| 2654 | } |
| 2655 | |
| 2656 | static int |
| 2657 | i915_ring_test_irq_set(void *data, u64 val) |
| 2658 | { |
| 2659 | struct drm_device *dev = data; |
| 2660 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2661 | int ret; |
| 2662 | |
| 2663 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 2664 | |
| 2665 | /* Lock against concurrent debugfs callers */ |
| 2666 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2667 | if (ret) |
| 2668 | return ret; |
| 2669 | |
| 2670 | dev_priv->gpu_error.test_irq_rings = val; |
| 2671 | mutex_unlock(&dev->struct_mutex); |
| 2672 | |
| 2673 | return 0; |
| 2674 | } |
| 2675 | |
| 2676 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 2677 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 2678 | "0x%08llx\n"); |
| 2679 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2680 | #define DROP_UNBOUND 0x1 |
| 2681 | #define DROP_BOUND 0x2 |
| 2682 | #define DROP_RETIRE 0x4 |
| 2683 | #define DROP_ACTIVE 0x8 |
| 2684 | #define DROP_ALL (DROP_UNBOUND | \ |
| 2685 | DROP_BOUND | \ |
| 2686 | DROP_RETIRE | \ |
| 2687 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2688 | static int |
| 2689 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2690 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2691 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2692 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2693 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2694 | } |
| 2695 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2696 | static int |
| 2697 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2698 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2699 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2700 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2701 | struct drm_i915_gem_object *obj, *next; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2702 | struct i915_address_space *vm; |
| 2703 | struct i915_vma *vma, *x; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2704 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2705 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2706 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2707 | |
| 2708 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 2709 | * on ioctls on -EAGAIN. */ |
| 2710 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2711 | if (ret) |
| 2712 | return ret; |
| 2713 | |
| 2714 | if (val & DROP_ACTIVE) { |
| 2715 | ret = i915_gpu_idle(dev); |
| 2716 | if (ret) |
| 2717 | goto unlock; |
| 2718 | } |
| 2719 | |
| 2720 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 2721 | i915_gem_retire_requests(dev); |
| 2722 | |
| 2723 | if (val & DROP_BOUND) { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2724 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2725 | list_for_each_entry_safe(vma, x, &vm->inactive_list, |
| 2726 | mm_list) { |
| 2727 | if (vma->obj->pin_count) |
| 2728 | continue; |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 2729 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2730 | ret = i915_vma_unbind(vma); |
| 2731 | if (ret) |
| 2732 | goto unlock; |
| 2733 | } |
Ben Widawsky | 31a46c9 | 2013-07-31 16:59:55 -0700 | [diff] [blame] | 2734 | } |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2735 | } |
| 2736 | |
| 2737 | if (val & DROP_UNBOUND) { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2738 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
| 2739 | global_list) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2740 | if (obj->pages_pin_count == 0) { |
| 2741 | ret = i915_gem_object_put_pages(obj); |
| 2742 | if (ret) |
| 2743 | goto unlock; |
| 2744 | } |
| 2745 | } |
| 2746 | |
| 2747 | unlock: |
| 2748 | mutex_unlock(&dev->struct_mutex); |
| 2749 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2750 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2751 | } |
| 2752 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2753 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 2754 | i915_drop_caches_get, i915_drop_caches_set, |
| 2755 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2756 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2757 | static int |
| 2758 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2759 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2760 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2761 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2762 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2763 | |
| 2764 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2765 | return -ENODEV; |
| 2766 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 2767 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 2768 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2769 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2770 | if (ret) |
| 2771 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2772 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2773 | if (IS_VALLEYVIEW(dev)) |
| 2774 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 2775 | dev_priv->rps.max_delay); |
| 2776 | else |
| 2777 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2778 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2779 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2780 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2781 | } |
| 2782 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2783 | static int |
| 2784 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2785 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2786 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2788 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2789 | |
| 2790 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2791 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2792 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 2793 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 2794 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2795 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2796 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2797 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2798 | if (ret) |
| 2799 | return ret; |
| 2800 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2801 | /* |
| 2802 | * Turbo will still be enabled, but won't go above the set value. |
| 2803 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2804 | if (IS_VALLEYVIEW(dev)) { |
| 2805 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 2806 | dev_priv->rps.max_delay = val; |
| 2807 | gen6_set_rps(dev, val); |
| 2808 | } else { |
| 2809 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 2810 | dev_priv->rps.max_delay = val; |
| 2811 | gen6_set_rps(dev, val); |
| 2812 | } |
| 2813 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2814 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2815 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2816 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2817 | } |
| 2818 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2819 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 2820 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2821 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2822 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2823 | static int |
| 2824 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2825 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2826 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2827 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2828 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2829 | |
| 2830 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2831 | return -ENODEV; |
| 2832 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 2833 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 2834 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2835 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2836 | if (ret) |
| 2837 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2838 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2839 | if (IS_VALLEYVIEW(dev)) |
| 2840 | *val = vlv_gpu_freq(dev_priv->mem_freq, |
| 2841 | dev_priv->rps.min_delay); |
| 2842 | else |
| 2843 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2844 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2845 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2846 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2847 | } |
| 2848 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2849 | static int |
| 2850 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2851 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2852 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2853 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2854 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2855 | |
| 2856 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2857 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2858 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 2859 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 2860 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2861 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2862 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2863 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2864 | if (ret) |
| 2865 | return ret; |
| 2866 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2867 | /* |
| 2868 | * Turbo will still be enabled, but won't go below the set value. |
| 2869 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2870 | if (IS_VALLEYVIEW(dev)) { |
| 2871 | val = vlv_freq_opcode(dev_priv->mem_freq, val); |
| 2872 | dev_priv->rps.min_delay = val; |
| 2873 | valleyview_set_rps(dev, val); |
| 2874 | } else { |
| 2875 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
| 2876 | dev_priv->rps.min_delay = val; |
| 2877 | gen6_set_rps(dev, val); |
| 2878 | } |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 2879 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2880 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2881 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2882 | } |
| 2883 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2884 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 2885 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 2886 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 2887 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2888 | static int |
| 2889 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2890 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2891 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2892 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2893 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2894 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2895 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2896 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2897 | return -ENODEV; |
| 2898 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 2899 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2900 | if (ret) |
| 2901 | return ret; |
| 2902 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2903 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2904 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 2905 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2906 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2907 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2908 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2909 | } |
| 2910 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2911 | static int |
| 2912 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2913 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2914 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2915 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2916 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2917 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 2918 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 2919 | return -ENODEV; |
| 2920 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2921 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2922 | return -EINVAL; |
| 2923 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2924 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2925 | |
| 2926 | /* Update the cache sharing policy here as well */ |
| 2927 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 2928 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 2929 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 2930 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 2931 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2932 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2933 | } |
| 2934 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 2935 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 2936 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 2937 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 2938 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2939 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 2940 | { |
| 2941 | struct drm_device *dev = inode->i_private; |
| 2942 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2943 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2944 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2945 | return 0; |
| 2946 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2947 | gen6_gt_force_wake_get(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2948 | |
| 2949 | return 0; |
| 2950 | } |
| 2951 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2952 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2953 | { |
| 2954 | struct drm_device *dev = inode->i_private; |
| 2955 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2956 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 2957 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2958 | return 0; |
| 2959 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2960 | gen6_gt_force_wake_put(dev_priv); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2961 | |
| 2962 | return 0; |
| 2963 | } |
| 2964 | |
| 2965 | static const struct file_operations i915_forcewake_fops = { |
| 2966 | .owner = THIS_MODULE, |
| 2967 | .open = i915_forcewake_open, |
| 2968 | .release = i915_forcewake_release, |
| 2969 | }; |
| 2970 | |
| 2971 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 2972 | { |
| 2973 | struct drm_device *dev = minor->dev; |
| 2974 | struct dentry *ent; |
| 2975 | |
| 2976 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2977 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2978 | root, dev, |
| 2979 | &i915_forcewake_fops); |
| 2980 | if (IS_ERR(ent)) |
| 2981 | return PTR_ERR(ent); |
| 2982 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 2983 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 2984 | } |
| 2985 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2986 | static int i915_debugfs_create(struct dentry *root, |
| 2987 | struct drm_minor *minor, |
| 2988 | const char *name, |
| 2989 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2990 | { |
| 2991 | struct drm_device *dev = minor->dev; |
| 2992 | struct dentry *ent; |
| 2993 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2994 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2995 | S_IRUGO | S_IWUSR, |
| 2996 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 2997 | fops); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 2998 | if (IS_ERR(ent)) |
| 2999 | return PTR_ERR(ent); |
| 3000 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3001 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 3002 | } |
| 3003 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3004 | static struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 3005 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3006 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 3007 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3008 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 3009 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 3010 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 3011 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 3012 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3013 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 3014 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 3015 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3016 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3017 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 3018 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 3019 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 3020 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3021 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
| 3022 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, |
| 3023 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
| 3024 | {"i915_inttoext_table", i915_inttoext_table, 0}, |
| 3025 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 3026 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 3027 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 3028 | {"i915_gfxec", i915_gfxec, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 3029 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 3030 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 3031 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 3032 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 3033 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 3034 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3035 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 3036 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 3037 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 3038 | {"i915_dpio", i915_dpio_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 3039 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 3040 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 3041 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 3042 | {"i915_pc8_status", i915_pc8_status, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3043 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3044 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3045 | |
Ville Syrjälä | 2b4bd0e | 2013-08-07 15:11:52 +0300 | [diff] [blame] | 3046 | static struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3047 | const char *name; |
| 3048 | const struct file_operations *fops; |
| 3049 | } i915_debugfs_files[] = { |
| 3050 | {"i915_wedged", &i915_wedged_fops}, |
| 3051 | {"i915_max_freq", &i915_max_freq_fops}, |
| 3052 | {"i915_min_freq", &i915_min_freq_fops}, |
| 3053 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 3054 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3055 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 3056 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3057 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 3058 | {"i915_error_state", &i915_error_state_fops}, |
| 3059 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3060 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3061 | }; |
| 3062 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3063 | void intel_display_crc_init(struct drm_device *dev) |
| 3064 | { |
| 3065 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3066 | int i; |
| 3067 | |
| 3068 | for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { |
| 3069 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i]; |
| 3070 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3071 | pipe_crc->opened = false; |
| 3072 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3073 | init_waitqueue_head(&pipe_crc->wq); |
| 3074 | } |
| 3075 | } |
| 3076 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3077 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3078 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3079 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3080 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3081 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 3082 | if (ret) |
| 3083 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 3084 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3085 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 3086 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 3087 | if (ret) |
| 3088 | return ret; |
| 3089 | } |
| 3090 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3091 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 3092 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 3093 | i915_debugfs_files[i].name, |
| 3094 | i915_debugfs_files[i].fops); |
| 3095 | if (ret) |
| 3096 | return ret; |
| 3097 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 3098 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3099 | return drm_debugfs_create_files(i915_debugfs_list, |
| 3100 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3101 | minor->debugfs_root, minor); |
| 3102 | } |
| 3103 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3104 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3105 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3106 | int i; |
| 3107 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 3108 | drm_debugfs_remove_files(i915_debugfs_list, |
| 3109 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3110 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 3111 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 3112 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3113 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 3114 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 3115 | struct drm_info_list *info_list = |
| 3116 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 3117 | |
| 3118 | drm_debugfs_remove_files(info_list, 1, minor); |
| 3119 | } |
| 3120 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 3121 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 3122 | struct drm_info_list *info_list = |
| 3123 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 3124 | |
| 3125 | drm_debugfs_remove_files(info_list, 1, minor); |
| 3126 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 3127 | } |
| 3128 | |
| 3129 | #endif /* CONFIG_DEBUG_FS */ |