Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 40 | |
| 41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 42 | bool pipelined); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 52 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 54 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 57 | struct drm_i915_gem_pwrite *args, |
| 58 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 60 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 61 | static int |
| 62 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 63 | gfp_t gfpmask); |
| 64 | |
| 65 | static void |
| 66 | i915_gem_object_put_pages(struct drm_gem_object *obj); |
| 67 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 68 | static LIST_HEAD(shrink_list); |
| 69 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
| 87 | size_t size) |
| 88 | { |
| 89 | dev_priv->mm.gtt_count++; |
| 90 | dev_priv->mm.gtt_memory += size; |
| 91 | } |
| 92 | |
| 93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
| 94 | size_t size) |
| 95 | { |
| 96 | dev_priv->mm.gtt_count--; |
| 97 | dev_priv->mm.gtt_memory -= size; |
| 98 | } |
| 99 | |
| 100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
| 101 | size_t size) |
| 102 | { |
| 103 | dev_priv->mm.pin_count++; |
| 104 | dev_priv->mm.pin_memory += size; |
| 105 | } |
| 106 | |
| 107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
| 108 | size_t size) |
| 109 | { |
| 110 | dev_priv->mm.pin_count--; |
| 111 | dev_priv->mm.pin_memory -= size; |
| 112 | } |
| 113 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | int |
| 115 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 116 | { |
| 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 118 | struct completion *x = &dev_priv->error_completion; |
| 119 | unsigned long flags; |
| 120 | int ret; |
| 121 | |
| 122 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 123 | return 0; |
| 124 | |
| 125 | ret = wait_for_completion_interruptible(x); |
| 126 | if (ret) |
| 127 | return ret; |
| 128 | |
| 129 | /* Success, we reset the GPU! */ |
| 130 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 131 | return 0; |
| 132 | |
| 133 | /* GPU is hung, bump the completion count to account for |
| 134 | * the token we just consumed so that we never hit zero and |
| 135 | * end up waiting upon a subsequent completion event that |
| 136 | * will never happen. |
| 137 | */ |
| 138 | spin_lock_irqsave(&x->wait.lock, flags); |
| 139 | x->done++; |
| 140 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 141 | return -EIO; |
| 142 | } |
| 143 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 145 | { |
| 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 147 | int ret; |
| 148 | |
| 149 | ret = i915_gem_check_is_wedged(dev); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 154 | if (ret) |
| 155 | return ret; |
| 156 | |
| 157 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 158 | mutex_unlock(&dev->struct_mutex); |
| 159 | return -EAGAIN; |
| 160 | } |
| 161 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 162 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 163 | return 0; |
| 164 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 165 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 166 | static inline bool |
| 167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 168 | { |
| 169 | return obj_priv->gtt_space && |
| 170 | !obj_priv->active && |
| 171 | obj_priv->pin_count == 0; |
| 172 | } |
| 173 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 174 | int i915_gem_do_init(struct drm_device *dev, |
| 175 | unsigned long start, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 176 | unsigned long end) |
| 177 | { |
| 178 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 179 | |
| 180 | if (start >= end || |
| 181 | (start & (PAGE_SIZE - 1)) != 0 || |
| 182 | (end & (PAGE_SIZE - 1)) != 0) { |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | |
| 186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 187 | end - start); |
| 188 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 189 | dev_priv->mm.gtt_total = end - start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 190 | |
| 191 | return 0; |
| 192 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 194 | int |
| 195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 196 | struct drm_file *file_priv) |
| 197 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 198 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 199 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 200 | |
| 201 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 203 | mutex_unlock(&dev->struct_mutex); |
| 204 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 205 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 206 | } |
| 207 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 208 | int |
| 209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 210 | struct drm_file *file_priv) |
| 211 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 213 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 214 | |
| 215 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 216 | return -ENODEV; |
| 217 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 218 | mutex_lock(&dev->struct_mutex); |
| 219 | args->aper_size = dev_priv->mm.gtt_total; |
| 220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 221 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 226 | |
| 227 | /** |
| 228 | * Creates a new mm object and returns a handle to it. |
| 229 | */ |
| 230 | int |
| 231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 232 | struct drm_file *file_priv) |
| 233 | { |
| 234 | struct drm_i915_gem_create *args = data; |
| 235 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 236 | int ret; |
| 237 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 238 | |
| 239 | args->size = roundup(args->size, PAGE_SIZE); |
| 240 | |
| 241 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 242 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 243 | if (obj == NULL) |
| 244 | return -ENOMEM; |
| 245 | |
| 246 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 247 | if (ret) { |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 248 | drm_gem_object_release(obj); |
| 249 | i915_gem_info_remove_obj(dev->dev_private, obj->size); |
| 250 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 251 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 252 | } |
| 253 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 254 | /* drop reference from allocate - handle holds it now */ |
| 255 | drm_gem_object_unreference(obj); |
| 256 | trace_i915_gem_object_create(obj); |
| 257 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 259 | return 0; |
| 260 | } |
| 261 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 262 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 263 | fast_shmem_read(struct page **pages, |
| 264 | loff_t page_base, int page_offset, |
| 265 | char __user *data, |
| 266 | int length) |
| 267 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 268 | char *vaddr; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 269 | int ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 270 | |
| 271 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 272 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 273 | kunmap_atomic(vaddr, KM_USER0); |
| 274 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 275 | return ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 276 | } |
| 277 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 279 | { |
| 280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 282 | |
| 283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 284 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 285 | } |
| 286 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 287 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 288 | slow_shmem_copy(struct page *dst_page, |
| 289 | int dst_offset, |
| 290 | struct page *src_page, |
| 291 | int src_offset, |
| 292 | int length) |
| 293 | { |
| 294 | char *dst_vaddr, *src_vaddr; |
| 295 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 296 | dst_vaddr = kmap(dst_page); |
| 297 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 298 | |
| 299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 300 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 301 | kunmap(src_page); |
| 302 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 303 | } |
| 304 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 305 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 306 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 307 | int gpu_offset, |
| 308 | struct page *cpu_page, |
| 309 | int cpu_offset, |
| 310 | int length, |
| 311 | int is_read) |
| 312 | { |
| 313 | char *gpu_vaddr, *cpu_vaddr; |
| 314 | |
| 315 | /* Use the unswizzled path if this page isn't affected. */ |
| 316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 317 | if (is_read) |
| 318 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 319 | gpu_page, gpu_offset, length); |
| 320 | else |
| 321 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 322 | cpu_page, cpu_offset, length); |
| 323 | } |
| 324 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 325 | gpu_vaddr = kmap(gpu_page); |
| 326 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 327 | |
| 328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 330 | */ |
| 331 | while (length > 0) { |
| 332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 333 | int this_length = min(cacheline_end - gpu_offset, length); |
| 334 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 335 | |
| 336 | if (is_read) { |
| 337 | memcpy(cpu_vaddr + cpu_offset, |
| 338 | gpu_vaddr + swizzled_gpu_offset, |
| 339 | this_length); |
| 340 | } else { |
| 341 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 342 | cpu_vaddr + cpu_offset, |
| 343 | this_length); |
| 344 | } |
| 345 | cpu_offset += this_length; |
| 346 | gpu_offset += this_length; |
| 347 | length -= this_length; |
| 348 | } |
| 349 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 350 | kunmap(cpu_page); |
| 351 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 352 | } |
| 353 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 354 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 355 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 356 | * from the backing pages of the object to the user's address space. On a |
| 357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 358 | */ |
| 359 | static int |
| 360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 361 | struct drm_i915_gem_pread *args, |
| 362 | struct drm_file *file_priv) |
| 363 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 365 | ssize_t remain; |
| 366 | loff_t offset, page_base; |
| 367 | char __user *user_data; |
| 368 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 369 | |
| 370 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 371 | remain = args->size; |
| 372 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 373 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 374 | offset = args->offset; |
| 375 | |
| 376 | while (remain > 0) { |
| 377 | /* Operation in this page |
| 378 | * |
| 379 | * page_base = page offset within aperture |
| 380 | * page_offset = offset within page |
| 381 | * page_length = bytes to copy for this page |
| 382 | */ |
| 383 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 384 | page_offset = offset & (PAGE_SIZE-1); |
| 385 | page_length = remain; |
| 386 | if ((page_offset + remain) > PAGE_SIZE) |
| 387 | page_length = PAGE_SIZE - page_offset; |
| 388 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 389 | if (fast_shmem_read(obj_priv->pages, |
| 390 | page_base, page_offset, |
| 391 | user_data, page_length)) |
| 392 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 393 | |
| 394 | remain -= page_length; |
| 395 | user_data += page_length; |
| 396 | offset += page_length; |
| 397 | } |
| 398 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 399 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | } |
| 401 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 402 | static int |
| 403 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 404 | { |
| 405 | int ret; |
| 406 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 407 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 408 | |
| 409 | /* If we've insufficient memory to map in the pages, attempt |
| 410 | * to make some space by throwing out some old buffers. |
| 411 | */ |
| 412 | if (ret == -ENOMEM) { |
| 413 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 414 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 415 | ret = i915_gem_evict_something(dev, obj->size, |
| 416 | i915_gem_get_gtt_alignment(obj)); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 417 | if (ret) |
| 418 | return ret; |
| 419 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 420 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | return ret; |
| 424 | } |
| 425 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | /** |
| 427 | * This is the fallback shmem pread path, which allocates temporary storage |
| 428 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 429 | * can copy out of the object's backing pages while holding the struct mutex |
| 430 | * and not take page faults. |
| 431 | */ |
| 432 | static int |
| 433 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 434 | struct drm_i915_gem_pread *args, |
| 435 | struct drm_file *file_priv) |
| 436 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 437 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 438 | struct mm_struct *mm = current->mm; |
| 439 | struct page **user_pages; |
| 440 | ssize_t remain; |
| 441 | loff_t offset, pinned_pages, i; |
| 442 | loff_t first_data_page, last_data_page, num_pages; |
| 443 | int shmem_page_index, shmem_page_offset; |
| 444 | int data_page_index, data_page_offset; |
| 445 | int page_length; |
| 446 | int ret; |
| 447 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 448 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 449 | |
| 450 | remain = args->size; |
| 451 | |
| 452 | /* Pin the user pages containing the data. We can't fault while |
| 453 | * holding the struct mutex, yet we want to hold it while |
| 454 | * dereferencing the user data. |
| 455 | */ |
| 456 | first_data_page = data_ptr / PAGE_SIZE; |
| 457 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 458 | num_pages = last_data_page - first_data_page + 1; |
| 459 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 460 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 461 | if (user_pages == NULL) |
| 462 | return -ENOMEM; |
| 463 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 464 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | down_read(&mm->mmap_sem); |
| 466 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 467 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 468 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 469 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 470 | if (pinned_pages < num_pages) { |
| 471 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 472 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 473 | } |
| 474 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 475 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 476 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 477 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 478 | if (ret) |
| 479 | goto out; |
| 480 | |
| 481 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 482 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 483 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 484 | offset = args->offset; |
| 485 | |
| 486 | while (remain > 0) { |
| 487 | /* Operation in this page |
| 488 | * |
| 489 | * shmem_page_index = page number within shmem file |
| 490 | * shmem_page_offset = offset within page in shmem file |
| 491 | * data_page_index = page number in get_user_pages return |
| 492 | * data_page_offset = offset with data_page_index page. |
| 493 | * page_length = bytes to copy for this page |
| 494 | */ |
| 495 | shmem_page_index = offset / PAGE_SIZE; |
| 496 | shmem_page_offset = offset & ~PAGE_MASK; |
| 497 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 498 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 499 | |
| 500 | page_length = remain; |
| 501 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 502 | page_length = PAGE_SIZE - shmem_page_offset; |
| 503 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 504 | page_length = PAGE_SIZE - data_page_offset; |
| 505 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 506 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 507 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 508 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 509 | user_pages[data_page_index], |
| 510 | data_page_offset, |
| 511 | page_length, |
| 512 | 1); |
| 513 | } else { |
| 514 | slow_shmem_copy(user_pages[data_page_index], |
| 515 | data_page_offset, |
| 516 | obj_priv->pages[shmem_page_index], |
| 517 | shmem_page_offset, |
| 518 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 519 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 520 | |
| 521 | remain -= page_length; |
| 522 | data_ptr += page_length; |
| 523 | offset += page_length; |
| 524 | } |
| 525 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 526 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 527 | for (i = 0; i < pinned_pages; i++) { |
| 528 | SetPageDirty(user_pages[i]); |
| 529 | page_cache_release(user_pages[i]); |
| 530 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 531 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 532 | |
| 533 | return ret; |
| 534 | } |
| 535 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 536 | /** |
| 537 | * Reads data from the object referenced by handle. |
| 538 | * |
| 539 | * On error, the contents of *data are undefined. |
| 540 | */ |
| 541 | int |
| 542 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 543 | struct drm_file *file_priv) |
| 544 | { |
| 545 | struct drm_i915_gem_pread *args = data; |
| 546 | struct drm_gem_object *obj; |
| 547 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 548 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 549 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 550 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 551 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 552 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 553 | |
| 554 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 555 | if (obj == NULL) { |
| 556 | ret = -ENOENT; |
| 557 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 558 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 559 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 560 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 561 | /* Bounds check source. */ |
| 562 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 563 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 564 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 565 | } |
| 566 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 567 | if (args->size == 0) |
| 568 | goto out; |
| 569 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 570 | if (!access_ok(VERIFY_WRITE, |
| 571 | (char __user *)(uintptr_t)args->data_ptr, |
| 572 | args->size)) { |
| 573 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 574 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 575 | } |
| 576 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 577 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 578 | args->size); |
| 579 | if (ret) { |
| 580 | ret = -EFAULT; |
| 581 | goto out; |
| 582 | } |
| 583 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 584 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 585 | if (ret) |
| 586 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 588 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 589 | args->offset, |
| 590 | args->size); |
| 591 | if (ret) |
| 592 | goto out_put; |
| 593 | |
| 594 | ret = -EFAULT; |
| 595 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 596 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 597 | if (ret == -EFAULT) |
| 598 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
| 599 | |
| 600 | out_put: |
| 601 | i915_gem_object_put_pages(obj); |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 602 | out: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 603 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 604 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 605 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 606 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 607 | } |
| 608 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 609 | /* This is the fast write path which cannot handle |
| 610 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 611 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 612 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 613 | static inline int |
| 614 | fast_user_write(struct io_mapping *mapping, |
| 615 | loff_t page_base, int page_offset, |
| 616 | char __user *user_data, |
| 617 | int length) |
| 618 | { |
| 619 | char *vaddr_atomic; |
| 620 | unsigned long unwritten; |
| 621 | |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 622 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 623 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 624 | user_data, length); |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 625 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 626 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | /* Here's the write path which can sleep for |
| 630 | * page faults |
| 631 | */ |
| 632 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 633 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 634 | slow_kernel_write(struct io_mapping *mapping, |
| 635 | loff_t gtt_base, int gtt_offset, |
| 636 | struct page *user_page, int user_offset, |
| 637 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 638 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 639 | char __iomem *dst_vaddr; |
| 640 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 641 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 642 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 643 | src_vaddr = kmap(user_page); |
| 644 | |
| 645 | memcpy_toio(dst_vaddr + gtt_offset, |
| 646 | src_vaddr + user_offset, |
| 647 | length); |
| 648 | |
| 649 | kunmap(user_page); |
| 650 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 651 | } |
| 652 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 653 | static inline int |
| 654 | fast_shmem_write(struct page **pages, |
| 655 | loff_t page_base, int page_offset, |
| 656 | char __user *data, |
| 657 | int length) |
| 658 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 659 | char *vaddr; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 660 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 661 | |
| 662 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 663 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 664 | kunmap_atomic(vaddr, KM_USER0); |
| 665 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 666 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 667 | } |
| 668 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 669 | /** |
| 670 | * This is the fast pwrite path, where we copy the data directly from the |
| 671 | * user into the GTT, uncached. |
| 672 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 673 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 674 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 675 | struct drm_i915_gem_pwrite *args, |
| 676 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 677 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 678 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 679 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 680 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 681 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 682 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 683 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 684 | |
| 685 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 686 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 687 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 688 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 689 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 690 | |
| 691 | while (remain > 0) { |
| 692 | /* Operation in this page |
| 693 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 694 | * page_base = page offset within aperture |
| 695 | * page_offset = offset within page |
| 696 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 698 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 699 | page_offset = offset & (PAGE_SIZE-1); |
| 700 | page_length = remain; |
| 701 | if ((page_offset + remain) > PAGE_SIZE) |
| 702 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 704 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 705 | * source page isn't available. Return the error and we'll |
| 706 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 707 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 709 | page_offset, user_data, page_length)) |
| 710 | |
| 711 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 713 | remain -= page_length; |
| 714 | user_data += page_length; |
| 715 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 716 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 717 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 718 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 721 | /** |
| 722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 723 | * the memory and maps it using kmap_atomic for copying. |
| 724 | * |
| 725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 727 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 728 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 730 | struct drm_i915_gem_pwrite *args, |
| 731 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 732 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 733 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 735 | ssize_t remain; |
| 736 | loff_t gtt_page_base, offset; |
| 737 | loff_t first_data_page, last_data_page, num_pages; |
| 738 | loff_t pinned_pages, i; |
| 739 | struct page **user_pages; |
| 740 | struct mm_struct *mm = current->mm; |
| 741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 743 | uint64_t data_ptr = args->data_ptr; |
| 744 | |
| 745 | remain = args->size; |
| 746 | |
| 747 | /* Pin the user pages containing the data. We can't fault while |
| 748 | * holding the struct mutex, and all of the pwrite implementations |
| 749 | * want to hold it while dereferencing the user data. |
| 750 | */ |
| 751 | first_data_page = data_ptr / PAGE_SIZE; |
| 752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 753 | num_pages = last_data_page - first_data_page + 1; |
| 754 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 756 | if (user_pages == NULL) |
| 757 | return -ENOMEM; |
| 758 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 759 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 760 | down_read(&mm->mmap_sem); |
| 761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 762 | num_pages, 0, 0, user_pages, NULL); |
| 763 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 764 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 765 | if (pinned_pages < num_pages) { |
| 766 | ret = -EFAULT; |
| 767 | goto out_unpin_pages; |
| 768 | } |
| 769 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 771 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 772 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 773 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 774 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 775 | offset = obj_priv->gtt_offset + args->offset; |
| 776 | |
| 777 | while (remain > 0) { |
| 778 | /* Operation in this page |
| 779 | * |
| 780 | * gtt_page_base = page offset within aperture |
| 781 | * gtt_page_offset = offset within page in aperture |
| 782 | * data_page_index = page number in get_user_pages return |
| 783 | * data_page_offset = offset with data_page_index page. |
| 784 | * page_length = bytes to copy for this page |
| 785 | */ |
| 786 | gtt_page_base = offset & PAGE_MASK; |
| 787 | gtt_page_offset = offset & ~PAGE_MASK; |
| 788 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 789 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 790 | |
| 791 | page_length = remain; |
| 792 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 793 | page_length = PAGE_SIZE - gtt_page_offset; |
| 794 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 795 | page_length = PAGE_SIZE - data_page_offset; |
| 796 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 797 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 798 | gtt_page_base, gtt_page_offset, |
| 799 | user_pages[data_page_index], |
| 800 | data_page_offset, |
| 801 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 802 | |
| 803 | remain -= page_length; |
| 804 | offset += page_length; |
| 805 | data_ptr += page_length; |
| 806 | } |
| 807 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 808 | out_unpin_pages: |
| 809 | for (i = 0; i < pinned_pages; i++) |
| 810 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 811 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 812 | |
| 813 | return ret; |
| 814 | } |
| 815 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | /** |
| 817 | * This is the fast shmem pwrite path, which attempts to directly |
| 818 | * copy_from_user into the kmapped pages backing the object. |
| 819 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 820 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 821 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 822 | struct drm_i915_gem_pwrite *args, |
| 823 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 824 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 825 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | ssize_t remain; |
| 827 | loff_t offset, page_base; |
| 828 | char __user *user_data; |
| 829 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 830 | |
| 831 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 832 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 834 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 835 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 836 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 837 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 838 | while (remain > 0) { |
| 839 | /* Operation in this page |
| 840 | * |
| 841 | * page_base = page offset within aperture |
| 842 | * page_offset = offset within page |
| 843 | * page_length = bytes to copy for this page |
| 844 | */ |
| 845 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 846 | page_offset = offset & (PAGE_SIZE-1); |
| 847 | page_length = remain; |
| 848 | if ((page_offset + remain) > PAGE_SIZE) |
| 849 | page_length = PAGE_SIZE - page_offset; |
| 850 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 851 | if (fast_shmem_write(obj_priv->pages, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 852 | page_base, page_offset, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 853 | user_data, page_length)) |
| 854 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 855 | |
| 856 | remain -= page_length; |
| 857 | user_data += page_length; |
| 858 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 859 | } |
| 860 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 861 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | /** |
| 865 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 866 | * the memory and maps it using kmap_atomic for copying. |
| 867 | * |
| 868 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 869 | * struct_mutex is held. |
| 870 | */ |
| 871 | static int |
| 872 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 873 | struct drm_i915_gem_pwrite *args, |
| 874 | struct drm_file *file_priv) |
| 875 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 876 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 877 | struct mm_struct *mm = current->mm; |
| 878 | struct page **user_pages; |
| 879 | ssize_t remain; |
| 880 | loff_t offset, pinned_pages, i; |
| 881 | loff_t first_data_page, last_data_page, num_pages; |
| 882 | int shmem_page_index, shmem_page_offset; |
| 883 | int data_page_index, data_page_offset; |
| 884 | int page_length; |
| 885 | int ret; |
| 886 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 887 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 888 | |
| 889 | remain = args->size; |
| 890 | |
| 891 | /* Pin the user pages containing the data. We can't fault while |
| 892 | * holding the struct mutex, and all of the pwrite implementations |
| 893 | * want to hold it while dereferencing the user data. |
| 894 | */ |
| 895 | first_data_page = data_ptr / PAGE_SIZE; |
| 896 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 897 | num_pages = last_data_page - first_data_page + 1; |
| 898 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 899 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 900 | if (user_pages == NULL) |
| 901 | return -ENOMEM; |
| 902 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 903 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 904 | down_read(&mm->mmap_sem); |
| 905 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 906 | num_pages, 0, 0, user_pages, NULL); |
| 907 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 908 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 909 | if (pinned_pages < num_pages) { |
| 910 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 911 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 912 | } |
| 913 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 914 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 915 | if (ret) |
| 916 | goto out; |
| 917 | |
| 918 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 919 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 920 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 921 | offset = args->offset; |
| 922 | obj_priv->dirty = 1; |
| 923 | |
| 924 | while (remain > 0) { |
| 925 | /* Operation in this page |
| 926 | * |
| 927 | * shmem_page_index = page number within shmem file |
| 928 | * shmem_page_offset = offset within page in shmem file |
| 929 | * data_page_index = page number in get_user_pages return |
| 930 | * data_page_offset = offset with data_page_index page. |
| 931 | * page_length = bytes to copy for this page |
| 932 | */ |
| 933 | shmem_page_index = offset / PAGE_SIZE; |
| 934 | shmem_page_offset = offset & ~PAGE_MASK; |
| 935 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 936 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 937 | |
| 938 | page_length = remain; |
| 939 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 940 | page_length = PAGE_SIZE - shmem_page_offset; |
| 941 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 942 | page_length = PAGE_SIZE - data_page_offset; |
| 943 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 944 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 945 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 946 | shmem_page_offset, |
| 947 | user_pages[data_page_index], |
| 948 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 949 | page_length, |
| 950 | 0); |
| 951 | } else { |
| 952 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 953 | shmem_page_offset, |
| 954 | user_pages[data_page_index], |
| 955 | data_page_offset, |
| 956 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 957 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 958 | |
| 959 | remain -= page_length; |
| 960 | data_ptr += page_length; |
| 961 | offset += page_length; |
| 962 | } |
| 963 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 964 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 965 | for (i = 0; i < pinned_pages; i++) |
| 966 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 967 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 968 | |
| 969 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 970 | } |
| 971 | |
| 972 | /** |
| 973 | * Writes data to the object referenced by handle. |
| 974 | * |
| 975 | * On error, the contents of the buffer that were to be modified are undefined. |
| 976 | */ |
| 977 | int |
| 978 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 979 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | { |
| 981 | struct drm_i915_gem_pwrite *args = data; |
| 982 | struct drm_gem_object *obj; |
| 983 | struct drm_i915_gem_object *obj_priv; |
| 984 | int ret = 0; |
| 985 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 986 | ret = i915_mutex_lock_interruptible(dev); |
| 987 | if (ret) |
| 988 | return ret; |
| 989 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 990 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 991 | if (obj == NULL) { |
| 992 | ret = -ENOENT; |
| 993 | goto unlock; |
| 994 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 995 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 996 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 997 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 998 | /* Bounds check destination. */ |
| 999 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1000 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1001 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1002 | } |
| 1003 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1004 | if (args->size == 0) |
| 1005 | goto out; |
| 1006 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1007 | if (!access_ok(VERIFY_READ, |
| 1008 | (char __user *)(uintptr_t)args->data_ptr, |
| 1009 | args->size)) { |
| 1010 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1011 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | } |
| 1013 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 1014 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1015 | args->size); |
| 1016 | if (ret) { |
| 1017 | ret = -EFAULT; |
| 1018 | goto out; |
| 1019 | } |
| 1020 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1021 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1022 | * it would end up going through the fenced access, and we'll get |
| 1023 | * different detiling behavior between reading and writing. |
| 1024 | * pread/pwrite currently are reading and writing from the CPU |
| 1025 | * perspective, requiring manual detiling by the client. |
| 1026 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1027 | if (obj_priv->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1028 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1029 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1030 | obj_priv->gtt_space && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 1031 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1032 | ret = i915_gem_object_pin(obj, 0); |
| 1033 | if (ret) |
| 1034 | goto out; |
| 1035 | |
| 1036 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1037 | if (ret) |
| 1038 | goto out_unpin; |
| 1039 | |
| 1040 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1041 | if (ret == -EFAULT) |
| 1042 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1043 | |
| 1044 | out_unpin: |
| 1045 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1046 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1047 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 1048 | if (ret) |
| 1049 | goto out; |
| 1050 | |
| 1051 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1052 | if (ret) |
| 1053 | goto out_put; |
| 1054 | |
| 1055 | ret = -EFAULT; |
| 1056 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1057 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1058 | if (ret == -EFAULT) |
| 1059 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
| 1060 | |
| 1061 | out_put: |
| 1062 | i915_gem_object_put_pages(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1063 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1064 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1065 | out: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1066 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1067 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1068 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1069 | return ret; |
| 1070 | } |
| 1071 | |
| 1072 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1073 | * Called when user space prepares to use an object with the CPU, either |
| 1074 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1075 | */ |
| 1076 | int |
| 1077 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1078 | struct drm_file *file_priv) |
| 1079 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1080 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1081 | struct drm_i915_gem_set_domain *args = data; |
| 1082 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1083 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1084 | uint32_t read_domains = args->read_domains; |
| 1085 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1086 | int ret; |
| 1087 | |
| 1088 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1089 | return -ENODEV; |
| 1090 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1091 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1092 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1093 | return -EINVAL; |
| 1094 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1095 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1096 | return -EINVAL; |
| 1097 | |
| 1098 | /* Having something in the write domain implies it's in the read |
| 1099 | * domain, and only that read domain. Enforce that in the request. |
| 1100 | */ |
| 1101 | if (write_domain != 0 && read_domains != write_domain) |
| 1102 | return -EINVAL; |
| 1103 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1104 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1105 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1106 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1107 | |
| 1108 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1109 | if (obj == NULL) { |
| 1110 | ret = -ENOENT; |
| 1111 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1112 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1113 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1114 | |
| 1115 | intel_mark_busy(dev, obj); |
| 1116 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1117 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1118 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1119 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1120 | /* Update the LRU on the fence for the CPU access that's |
| 1121 | * about to occur. |
| 1122 | */ |
| 1123 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1124 | struct drm_i915_fence_reg *reg = |
| 1125 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1126 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1127 | &dev_priv->mm.fence_list); |
| 1128 | } |
| 1129 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1130 | /* Silently promote "you're not bound, there was nothing to do" |
| 1131 | * to success, since the client was just asking us to |
| 1132 | * make sure everything was done. |
| 1133 | */ |
| 1134 | if (ret == -EINVAL) |
| 1135 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1136 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1137 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1138 | } |
| 1139 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1140 | /* Maintain LRU order of "inactive" objects */ |
| 1141 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1142 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1144 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1145 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1146 | mutex_unlock(&dev->struct_mutex); |
| 1147 | return ret; |
| 1148 | } |
| 1149 | |
| 1150 | /** |
| 1151 | * Called when user space has done writes to this buffer |
| 1152 | */ |
| 1153 | int |
| 1154 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1155 | struct drm_file *file_priv) |
| 1156 | { |
| 1157 | struct drm_i915_gem_sw_finish *args = data; |
| 1158 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1159 | int ret = 0; |
| 1160 | |
| 1161 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1162 | return -ENODEV; |
| 1163 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1164 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1165 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1166 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1167 | |
| 1168 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1169 | if (obj == NULL) { |
| 1170 | ret = -ENOENT; |
| 1171 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1172 | } |
| 1173 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1174 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 1175 | if (to_intel_bo(obj)->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1176 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1177 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1178 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1179 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1180 | mutex_unlock(&dev->struct_mutex); |
| 1181 | return ret; |
| 1182 | } |
| 1183 | |
| 1184 | /** |
| 1185 | * Maps the contents of an object, returning the address it is mapped |
| 1186 | * into. |
| 1187 | * |
| 1188 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1189 | * imply a ref on the object itself. |
| 1190 | */ |
| 1191 | int |
| 1192 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1193 | struct drm_file *file_priv) |
| 1194 | { |
| 1195 | struct drm_i915_gem_mmap *args = data; |
| 1196 | struct drm_gem_object *obj; |
| 1197 | loff_t offset; |
| 1198 | unsigned long addr; |
| 1199 | |
| 1200 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1201 | return -ENODEV; |
| 1202 | |
| 1203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1204 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1205 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1206 | |
| 1207 | offset = args->offset; |
| 1208 | |
| 1209 | down_write(¤t->mm->mmap_sem); |
| 1210 | addr = do_mmap(obj->filp, 0, args->size, |
| 1211 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1212 | args->offset); |
| 1213 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1214 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1215 | if (IS_ERR((void *)addr)) |
| 1216 | return addr; |
| 1217 | |
| 1218 | args->addr_ptr = (uint64_t) addr; |
| 1219 | |
| 1220 | return 0; |
| 1221 | } |
| 1222 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1223 | /** |
| 1224 | * i915_gem_fault - fault a page into the GTT |
| 1225 | * vma: VMA in question |
| 1226 | * vmf: fault info |
| 1227 | * |
| 1228 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1229 | * from userspace. The fault handler takes care of binding the object to |
| 1230 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1231 | * only if needed based on whether the old reg is still valid or the object |
| 1232 | * is tiled) and inserting a new PTE into the faulting process. |
| 1233 | * |
| 1234 | * Note that the faulting process may involve evicting existing objects |
| 1235 | * from the GTT and/or fence registers to make room. So performance may |
| 1236 | * suffer if the GTT working set is large or there are few fence registers |
| 1237 | * left. |
| 1238 | */ |
| 1239 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1240 | { |
| 1241 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1242 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1243 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1244 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1245 | pgoff_t page_offset; |
| 1246 | unsigned long pfn; |
| 1247 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1248 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1249 | |
| 1250 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1251 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1252 | PAGE_SHIFT; |
| 1253 | |
| 1254 | /* Now bind it into the GTT if needed */ |
| 1255 | mutex_lock(&dev->struct_mutex); |
| 1256 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1257 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1258 | if (ret) |
| 1259 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1260 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1261 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1262 | if (ret) |
| 1263 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | } |
| 1265 | |
| 1266 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1267 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1268 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1269 | if (ret) |
| 1270 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1271 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1272 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1273 | if (i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1274 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1275 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1277 | page_offset; |
| 1278 | |
| 1279 | /* Finally, remap it using the new GTT offset */ |
| 1280 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1281 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1282 | mutex_unlock(&dev->struct_mutex); |
| 1283 | |
| 1284 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1285 | case 0: |
| 1286 | case -ERESTARTSYS: |
| 1287 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1288 | case -ENOMEM: |
| 1289 | case -EAGAIN: |
| 1290 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1291 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1292 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1293 | } |
| 1294 | } |
| 1295 | |
| 1296 | /** |
| 1297 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1298 | * @obj: obj in question |
| 1299 | * |
| 1300 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1301 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1302 | * up the object based on the offset and sets up the various memory mapping |
| 1303 | * structures. |
| 1304 | * |
| 1305 | * This routine allocates and attaches a fake offset for @obj. |
| 1306 | */ |
| 1307 | static int |
| 1308 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1309 | { |
| 1310 | struct drm_device *dev = obj->dev; |
| 1311 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1312 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1313 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1314 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1315 | int ret = 0; |
| 1316 | |
| 1317 | /* Set the object up for mmap'ing */ |
| 1318 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1319 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1320 | if (!list->map) |
| 1321 | return -ENOMEM; |
| 1322 | |
| 1323 | map = list->map; |
| 1324 | map->type = _DRM_GEM; |
| 1325 | map->size = obj->size; |
| 1326 | map->handle = obj; |
| 1327 | |
| 1328 | /* Get a DRM GEM mmap offset allocated... */ |
| 1329 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1330 | obj->size / PAGE_SIZE, 0, 0); |
| 1331 | if (!list->file_offset_node) { |
| 1332 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1333 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1334 | goto out_free_list; |
| 1335 | } |
| 1336 | |
| 1337 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1338 | obj->size / PAGE_SIZE, 0); |
| 1339 | if (!list->file_offset_node) { |
| 1340 | ret = -ENOMEM; |
| 1341 | goto out_free_list; |
| 1342 | } |
| 1343 | |
| 1344 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1345 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1346 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1347 | DRM_ERROR("failed to add to map hash\n"); |
| 1348 | goto out_free_mm; |
| 1349 | } |
| 1350 | |
| 1351 | /* By now we should be all set, any drm_mmap request on the offset |
| 1352 | * below will get to our mmap & fault handler */ |
| 1353 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1354 | |
| 1355 | return 0; |
| 1356 | |
| 1357 | out_free_mm: |
| 1358 | drm_mm_put_block(list->file_offset_node); |
| 1359 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1360 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1361 | |
| 1362 | return ret; |
| 1363 | } |
| 1364 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1365 | /** |
| 1366 | * i915_gem_release_mmap - remove physical page mappings |
| 1367 | * @obj: obj in question |
| 1368 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1369 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1370 | * relinquish ownership of the pages back to the system. |
| 1371 | * |
| 1372 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1373 | * object through the GTT and then lose the fence register due to |
| 1374 | * resource pressure. Similarly if the object has been moved out of the |
| 1375 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1376 | * mapping will then trigger a page fault on the next user access, allowing |
| 1377 | * fixup by i915_gem_fault(). |
| 1378 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1379 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1380 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1381 | { |
| 1382 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1383 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1384 | |
| 1385 | if (dev->dev_mapping) |
| 1386 | unmap_mapping_range(dev->dev_mapping, |
| 1387 | obj_priv->mmap_offset, obj->size, 1); |
| 1388 | } |
| 1389 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1390 | static void |
| 1391 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1392 | { |
| 1393 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1394 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1395 | struct drm_gem_mm *mm = dev->mm_private; |
| 1396 | struct drm_map_list *list; |
| 1397 | |
| 1398 | list = &obj->map_list; |
| 1399 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1400 | |
| 1401 | if (list->file_offset_node) { |
| 1402 | drm_mm_put_block(list->file_offset_node); |
| 1403 | list->file_offset_node = NULL; |
| 1404 | } |
| 1405 | |
| 1406 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1407 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1408 | list->map = NULL; |
| 1409 | } |
| 1410 | |
| 1411 | obj_priv->mmap_offset = 0; |
| 1412 | } |
| 1413 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1414 | /** |
| 1415 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1416 | * @obj: object to check |
| 1417 | * |
| 1418 | * Return the required GTT alignment for an object, taking into account |
| 1419 | * potential fence register mapping if needed. |
| 1420 | */ |
| 1421 | static uint32_t |
| 1422 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1423 | { |
| 1424 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1425 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1426 | int start, i; |
| 1427 | |
| 1428 | /* |
| 1429 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1430 | * if a fence register is needed for the object. |
| 1431 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1432 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1433 | return 4096; |
| 1434 | |
| 1435 | /* |
| 1436 | * Previous chips need to be aligned to the size of the smallest |
| 1437 | * fence register that can contain the object. |
| 1438 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1439 | if (INTEL_INFO(dev)->gen == 3) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1440 | start = 1024*1024; |
| 1441 | else |
| 1442 | start = 512*1024; |
| 1443 | |
| 1444 | for (i = start; i < obj->size; i <<= 1) |
| 1445 | ; |
| 1446 | |
| 1447 | return i; |
| 1448 | } |
| 1449 | |
| 1450 | /** |
| 1451 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1452 | * @dev: DRM device |
| 1453 | * @data: GTT mapping ioctl data |
| 1454 | * @file_priv: GEM object info |
| 1455 | * |
| 1456 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1457 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1458 | * up so we can get faults in the handler above. |
| 1459 | * |
| 1460 | * The fault handler will take care of binding the object into the GTT |
| 1461 | * (since it may have been evicted to make room for something), allocating |
| 1462 | * a fence register, and mapping the appropriate aperture address into |
| 1463 | * userspace. |
| 1464 | */ |
| 1465 | int |
| 1466 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1467 | struct drm_file *file_priv) |
| 1468 | { |
| 1469 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1470 | struct drm_gem_object *obj; |
| 1471 | struct drm_i915_gem_object *obj_priv; |
| 1472 | int ret; |
| 1473 | |
| 1474 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1475 | return -ENODEV; |
| 1476 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1477 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1478 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1479 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1480 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1481 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1482 | if (obj == NULL) { |
| 1483 | ret = -ENOENT; |
| 1484 | goto unlock; |
| 1485 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1486 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1487 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1488 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1489 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1490 | ret = -EINVAL; |
| 1491 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1492 | } |
| 1493 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1494 | if (!obj_priv->mmap_offset) { |
| 1495 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1496 | if (ret) |
| 1497 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1498 | } |
| 1499 | |
| 1500 | args->offset = obj_priv->mmap_offset; |
| 1501 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1502 | /* |
| 1503 | * Pull it into the GTT so that we have a page list (makes the |
| 1504 | * initial fault faster and any subsequent flushing possible). |
| 1505 | */ |
| 1506 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1507 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1508 | if (ret) |
| 1509 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1510 | } |
| 1511 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1512 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1513 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1514 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1515 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1516 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1517 | } |
| 1518 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1519 | static void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1520 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1521 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1523 | int page_count = obj->size / PAGE_SIZE; |
| 1524 | int i; |
| 1525 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1526 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1527 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1528 | |
| 1529 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1530 | return; |
| 1531 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1532 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1533 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1534 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1535 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1536 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1537 | |
| 1538 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1539 | if (obj_priv->dirty) |
| 1540 | set_page_dirty(obj_priv->pages[i]); |
| 1541 | |
| 1542 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1543 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1544 | |
| 1545 | page_cache_release(obj_priv->pages[i]); |
| 1546 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1547 | obj_priv->dirty = 0; |
| 1548 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1549 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1550 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1551 | } |
| 1552 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1553 | static uint32_t |
| 1554 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1555 | struct intel_ring_buffer *ring) |
| 1556 | { |
| 1557 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1558 | |
| 1559 | ring->outstanding_lazy_request = true; |
| 1560 | return dev_priv->next_seqno; |
| 1561 | } |
| 1562 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1563 | static void |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1564 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1565 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | { |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1567 | struct drm_device *dev = obj->dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1569 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1570 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1571 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1572 | BUG_ON(ring == NULL); |
| 1573 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1574 | |
| 1575 | /* Add a reference if we're newly entering the active list. */ |
| 1576 | if (!obj_priv->active) { |
| 1577 | drm_gem_object_reference(obj); |
| 1578 | obj_priv->active = 1; |
| 1579 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1580 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1581 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1582 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
| 1583 | list_move_tail(&obj_priv->ring_list, &ring->active_list); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1584 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1585 | } |
| 1586 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1587 | static void |
| 1588 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1589 | { |
| 1590 | struct drm_device *dev = obj->dev; |
| 1591 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1592 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1593 | |
| 1594 | BUG_ON(!obj_priv->active); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1595 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
| 1596 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1597 | obj_priv->last_rendering_seqno = 0; |
| 1598 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1599 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1600 | /* Immediately discard the backing storage */ |
| 1601 | static void |
| 1602 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1603 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1604 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1605 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1606 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1607 | /* Our goal here is to return as much of the memory as |
| 1608 | * is possible back to the system as we are called from OOM. |
| 1609 | * To do this we must instruct the shmfs to drop all of its |
| 1610 | * backing pages, *now*. Here we mirror the actions taken |
| 1611 | * when by shmem_delete_inode() to release the backing store. |
| 1612 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1613 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1614 | truncate_inode_pages(inode->i_mapping, 0); |
| 1615 | if (inode->i_op->truncate_range) |
| 1616 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1617 | |
| 1618 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1619 | } |
| 1620 | |
| 1621 | static inline int |
| 1622 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1623 | { |
| 1624 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1625 | } |
| 1626 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1627 | static void |
| 1628 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1629 | { |
| 1630 | struct drm_device *dev = obj->dev; |
| 1631 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1632 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1633 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1634 | if (obj_priv->pin_count != 0) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1635 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1636 | else |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1637 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
| 1638 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1639 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1640 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1641 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1642 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1643 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | if (obj_priv->active) { |
| 1645 | obj_priv->active = 0; |
| 1646 | drm_gem_object_unreference(obj); |
| 1647 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1648 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1649 | } |
| 1650 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 1651 | static void |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1652 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1653 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1654 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1655 | { |
| 1656 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1657 | struct drm_i915_gem_object *obj_priv, *next; |
| 1658 | |
| 1659 | list_for_each_entry_safe(obj_priv, next, |
| 1660 | &dev_priv->mm.gpu_write_list, |
| 1661 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1662 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1663 | |
Chris Wilson | 2b6efaa | 2010-09-14 17:04:02 +0100 | [diff] [blame] | 1664 | if (obj->write_domain & flush_domains && |
| 1665 | obj_priv->ring == ring) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1666 | uint32_t old_write_domain = obj->write_domain; |
| 1667 | |
| 1668 | obj->write_domain = 0; |
| 1669 | list_del_init(&obj_priv->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1670 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1671 | |
| 1672 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1673 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1674 | struct drm_i915_fence_reg *reg = |
| 1675 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1676 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1677 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1678 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1679 | |
| 1680 | trace_i915_gem_object_change_domain(obj, |
| 1681 | obj->read_domains, |
| 1682 | old_write_domain); |
| 1683 | } |
| 1684 | } |
| 1685 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1686 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1687 | uint32_t |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1688 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1689 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1690 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1691 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1692 | { |
| 1693 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1694 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1695 | uint32_t seqno; |
| 1696 | int was_empty; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1698 | if (file != NULL) |
| 1699 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1700 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1701 | if (request == NULL) { |
| 1702 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1703 | if (request == NULL) |
| 1704 | return 0; |
| 1705 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1706 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1707 | seqno = ring->add_request(dev, ring, 0); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1708 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1709 | |
| 1710 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1711 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1712 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1713 | was_empty = list_empty(&ring->request_list); |
| 1714 | list_add_tail(&request->list, &ring->request_list); |
| 1715 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1716 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1717 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1718 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1719 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1720 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1721 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1722 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1723 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1724 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1725 | mod_timer(&dev_priv->hangcheck_timer, |
| 1726 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1727 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1728 | queue_delayed_work(dev_priv->wq, |
| 1729 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1730 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1731 | return seqno; |
| 1732 | } |
| 1733 | |
| 1734 | /** |
| 1735 | * Command execution barrier |
| 1736 | * |
| 1737 | * Ensures that all commands in the ring are finished |
| 1738 | * before signalling the CPU |
| 1739 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1740 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1741 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1743 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1744 | |
| 1745 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1746 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1747 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1748 | |
| 1749 | ring->flush(dev, ring, |
| 1750 | I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1751 | } |
| 1752 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1753 | static inline void |
| 1754 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1755 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1756 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1757 | |
| 1758 | if (!file_priv) |
| 1759 | return; |
| 1760 | |
| 1761 | spin_lock(&file_priv->mm.lock); |
| 1762 | list_del(&request->client_list); |
| 1763 | request->file_priv = NULL; |
| 1764 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1765 | } |
| 1766 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1767 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1768 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1769 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1770 | while (!list_empty(&ring->request_list)) { |
| 1771 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1772 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1773 | request = list_first_entry(&ring->request_list, |
| 1774 | struct drm_i915_gem_request, |
| 1775 | list); |
| 1776 | |
| 1777 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1778 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1779 | kfree(request); |
| 1780 | } |
| 1781 | |
| 1782 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1783 | struct drm_i915_gem_object *obj_priv; |
| 1784 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1785 | obj_priv = list_first_entry(&ring->active_list, |
| 1786 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1787 | ring_list); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1788 | |
| 1789 | obj_priv->base.write_domain = 0; |
| 1790 | list_del_init(&obj_priv->gpu_write_list); |
| 1791 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1792 | } |
| 1793 | } |
| 1794 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1795 | void i915_gem_reset(struct drm_device *dev) |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1796 | { |
| 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1798 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1799 | int i; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1800 | |
| 1801 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1802 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1803 | |
| 1804 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1805 | * to be lost on reset along with the data, so simply move the |
| 1806 | * lost bo to the inactive list. |
| 1807 | */ |
| 1808 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1809 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1810 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1811 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1812 | |
| 1813 | obj_priv->base.write_domain = 0; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1814 | list_del_init(&obj_priv->gpu_write_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1815 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1816 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1817 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1818 | /* Move everything out of the GPU domains to ensure we do any |
| 1819 | * necessary invalidation upon reuse. |
| 1820 | */ |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1821 | list_for_each_entry(obj_priv, |
| 1822 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1823 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1824 | { |
| 1825 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 1826 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1827 | |
| 1828 | /* The fence registers are invalidated so clear them out */ |
| 1829 | for (i = 0; i < 16; i++) { |
| 1830 | struct drm_i915_fence_reg *reg; |
| 1831 | |
| 1832 | reg = &dev_priv->fence_regs[i]; |
| 1833 | if (!reg->obj) |
| 1834 | continue; |
| 1835 | |
| 1836 | i915_gem_clear_fence_reg(reg->obj); |
| 1837 | } |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1838 | } |
| 1839 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1840 | /** |
| 1841 | * This function clears the request list as sequence numbers are passed. |
| 1842 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1843 | static void |
| 1844 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1845 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | { |
| 1847 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1848 | uint32_t seqno; |
| 1849 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1850 | if (!ring->status_page.page_addr || |
| 1851 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1852 | return; |
| 1853 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1854 | WARN_ON(i915_verify_lists(dev)); |
| 1855 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1856 | seqno = ring->get_seqno(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1857 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1858 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1859 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1860 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1861 | struct drm_i915_gem_request, |
| 1862 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1863 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1864 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1865 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1866 | |
| 1867 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1868 | |
| 1869 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1870 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1871 | kfree(request); |
| 1872 | } |
| 1873 | |
| 1874 | /* Move any buffers on the active list that are no longer referenced |
| 1875 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1876 | */ |
| 1877 | while (!list_empty(&ring->active_list)) { |
| 1878 | struct drm_gem_object *obj; |
| 1879 | struct drm_i915_gem_object *obj_priv; |
| 1880 | |
| 1881 | obj_priv = list_first_entry(&ring->active_list, |
| 1882 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1883 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1884 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1885 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1886 | break; |
| 1887 | |
| 1888 | obj = &obj_priv->base; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1889 | if (obj->write_domain != 0) |
| 1890 | i915_gem_object_move_to_flushing(obj); |
| 1891 | else |
| 1892 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1893 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1894 | |
| 1895 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1896 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1897 | ring->user_irq_put(dev, ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1898 | dev_priv->trace_irq_seqno = 0; |
| 1899 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1900 | |
| 1901 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1902 | } |
| 1903 | |
| 1904 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1905 | i915_gem_retire_requests(struct drm_device *dev) |
| 1906 | { |
| 1907 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1908 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1909 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 1910 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 1911 | |
| 1912 | /* We must be careful that during unbind() we do not |
| 1913 | * accidentally infinitely recurse into retire requests. |
| 1914 | * Currently: |
| 1915 | * retire -> free -> unbind -> wait -> retire_ring |
| 1916 | */ |
| 1917 | list_for_each_entry_safe(obj_priv, tmp, |
| 1918 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1919 | mm_list) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1920 | i915_gem_free_object_tail(&obj_priv->base); |
| 1921 | } |
| 1922 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1923 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1924 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1925 | } |
| 1926 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1927 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1928 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1929 | { |
| 1930 | drm_i915_private_t *dev_priv; |
| 1931 | struct drm_device *dev; |
| 1932 | |
| 1933 | dev_priv = container_of(work, drm_i915_private_t, |
| 1934 | mm.retire_work.work); |
| 1935 | dev = dev_priv->dev; |
| 1936 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1937 | /* Come back later if the device is busy... */ |
| 1938 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1939 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1940 | return; |
| 1941 | } |
| 1942 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1943 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1944 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1945 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1946 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1947 | !list_empty(&dev_priv->bsd_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1948 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1949 | mutex_unlock(&dev->struct_mutex); |
| 1950 | } |
| 1951 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1952 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1953 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1954 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | { |
| 1956 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1957 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1958 | int ret = 0; |
| 1959 | |
| 1960 | BUG_ON(seqno == 0); |
| 1961 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1962 | if (atomic_read(&dev_priv->mm.wedged)) |
| 1963 | return -EAGAIN; |
| 1964 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1965 | if (ring->outstanding_lazy_request) { |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1966 | seqno = i915_add_request(dev, NULL, NULL, ring); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1967 | if (seqno == 0) |
| 1968 | return -ENOMEM; |
| 1969 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1970 | BUG_ON(seqno == dev_priv->next_seqno); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1971 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1972 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1973 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1974 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1975 | else |
| 1976 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1977 | if (!ier) { |
| 1978 | DRM_ERROR("something (likely vbetool) disabled " |
| 1979 | "interrupts, re-enabling\n"); |
| 1980 | i915_driver_irq_preinstall(dev); |
| 1981 | i915_driver_irq_postinstall(dev); |
| 1982 | } |
| 1983 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1984 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1985 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1986 | ring->waiting_gem_seqno = seqno; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1987 | ring->user_irq_get(dev, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1988 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1989 | ret = wait_event_interruptible(ring->irq_queue, |
| 1990 | i915_seqno_passed( |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1991 | ring->get_seqno(dev, ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1992 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1993 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1994 | wait_event(ring->irq_queue, |
| 1995 | i915_seqno_passed( |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1996 | ring->get_seqno(dev, ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1997 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1998 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1999 | ring->user_irq_put(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2000 | ring->waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2001 | |
| 2002 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2003 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2004 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2005 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2006 | |
| 2007 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2008 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2009 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2010 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2011 | |
| 2012 | /* Directly dispatch request retiring. While we have the work queue |
| 2013 | * to handle this, the waiter on a request often wants an associated |
| 2014 | * buffer to have made it to the inactive list, and we would need |
| 2015 | * a separate wait queue to handle that. |
| 2016 | */ |
| 2017 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2018 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2019 | |
| 2020 | return ret; |
| 2021 | } |
| 2022 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2023 | /** |
| 2024 | * Waits for a sequence number to be signaled, and cleans up the |
| 2025 | * request and object lists appropriately for that event. |
| 2026 | */ |
| 2027 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2028 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2029 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2030 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2031 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2032 | } |
| 2033 | |
Chris Wilson | 20f0cd5 | 2010-09-23 11:00:38 +0100 | [diff] [blame] | 2034 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2035 | i915_gem_flush_ring(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2036 | struct drm_file *file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2037 | struct intel_ring_buffer *ring, |
| 2038 | uint32_t invalidate_domains, |
| 2039 | uint32_t flush_domains) |
| 2040 | { |
| 2041 | ring->flush(dev, ring, invalidate_domains, flush_domains); |
| 2042 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2043 | } |
| 2044 | |
| 2045 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2046 | i915_gem_flush(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2047 | struct drm_file *file_priv, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2048 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2049 | uint32_t flush_domains, |
| 2050 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2051 | { |
| 2052 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2053 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2054 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 2055 | drm_agp_chipset_flush(dev); |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2056 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2057 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2058 | if (flush_rings & RING_RENDER) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2059 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2060 | &dev_priv->render_ring, |
| 2061 | invalidate_domains, flush_domains); |
| 2062 | if (flush_rings & RING_BSD) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2063 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2064 | &dev_priv->bsd_ring, |
| 2065 | invalidate_domains, flush_domains); |
| 2066 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2067 | } |
| 2068 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2069 | /** |
| 2070 | * Ensures that all rendering to the object has completed and the object is |
| 2071 | * safe to unbind from the GTT or access from the CPU. |
| 2072 | */ |
| 2073 | static int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2074 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 2075 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2076 | { |
| 2077 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2078 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2079 | int ret; |
| 2080 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2081 | /* This function only exists to support waiting for existing rendering, |
| 2082 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2083 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2084 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2085 | |
| 2086 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2087 | * it. |
| 2088 | */ |
| 2089 | if (obj_priv->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2090 | ret = i915_do_wait_request(dev, |
| 2091 | obj_priv->last_rendering_seqno, |
| 2092 | interruptible, |
| 2093 | obj_priv->ring); |
| 2094 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2095 | return ret; |
| 2096 | } |
| 2097 | |
| 2098 | return 0; |
| 2099 | } |
| 2100 | |
| 2101 | /** |
| 2102 | * Unbinds an object from the GTT aperture. |
| 2103 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2104 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2105 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 2106 | { |
| 2107 | struct drm_device *dev = obj->dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2108 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2109 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2110 | int ret = 0; |
| 2111 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2112 | if (obj_priv->gtt_space == NULL) |
| 2113 | return 0; |
| 2114 | |
| 2115 | if (obj_priv->pin_count != 0) { |
| 2116 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2117 | return -EINVAL; |
| 2118 | } |
| 2119 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2120 | /* blow away mappings if mapped through GTT */ |
| 2121 | i915_gem_release_mmap(obj); |
| 2122 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2123 | /* Move the object to the CPU domain to ensure that |
| 2124 | * any possible CPU writes while it's not in the GTT |
| 2125 | * are flushed when we go to remap it. This will |
| 2126 | * also ensure that all pending GPU writes are finished |
| 2127 | * before we unbind. |
| 2128 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2129 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2130 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2131 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2132 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2133 | * should be safe and we need to cleanup or else we might |
| 2134 | * cause memory corruption through use-after-free. |
| 2135 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2136 | if (ret) { |
| 2137 | i915_gem_clflush_object(obj); |
| 2138 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2139 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2140 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2141 | /* release the fence reg _after_ flushing */ |
| 2142 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2143 | i915_gem_clear_fence_reg(obj); |
| 2144 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2145 | drm_unbind_agp(obj_priv->agp_mem); |
| 2146 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2147 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2148 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2149 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2150 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2151 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2152 | list_del_init(&obj_priv->mm_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2153 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2154 | drm_mm_put_block(obj_priv->gtt_space); |
| 2155 | obj_priv->gtt_space = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2156 | obj_priv->gtt_offset = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2157 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2158 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2159 | i915_gem_object_truncate(obj); |
| 2160 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2161 | trace_i915_gem_object_unbind(obj); |
| 2162 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2163 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2164 | } |
| 2165 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2166 | static int i915_ring_idle(struct drm_device *dev, |
| 2167 | struct intel_ring_buffer *ring) |
| 2168 | { |
| 2169 | i915_gem_flush_ring(dev, NULL, ring, |
| 2170 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2171 | return i915_wait_request(dev, |
| 2172 | i915_gem_next_request_seqno(dev, ring), |
| 2173 | ring); |
| 2174 | } |
| 2175 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2176 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2177 | i915_gpu_idle(struct drm_device *dev) |
| 2178 | { |
| 2179 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2180 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2181 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2182 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2183 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2184 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2185 | list_empty(&dev_priv->bsd_ring.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2186 | if (lists_empty) |
| 2187 | return 0; |
| 2188 | |
| 2189 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2190 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2191 | if (ret) |
| 2192 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2193 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2194 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2195 | if (ret) |
| 2196 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2197 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2198 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2199 | } |
| 2200 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2201 | static int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2202 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2203 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2204 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2205 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2206 | int page_count, i; |
| 2207 | struct address_space *mapping; |
| 2208 | struct inode *inode; |
| 2209 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2210 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2211 | BUG_ON(obj_priv->pages_refcount |
| 2212 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2213 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2214 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2215 | return 0; |
| 2216 | |
| 2217 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2218 | * at this point until we release them. |
| 2219 | */ |
| 2220 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2221 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2222 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2223 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2224 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2225 | return -ENOMEM; |
| 2226 | } |
| 2227 | |
| 2228 | inode = obj->filp->f_path.dentry->d_inode; |
| 2229 | mapping = inode->i_mapping; |
| 2230 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2231 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2232 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2233 | __GFP_COLD | |
Linus Torvalds | cd9f040 | 2010-07-18 09:44:37 -0700 | [diff] [blame] | 2234 | __GFP_RECLAIMABLE | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2235 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2236 | if (IS_ERR(page)) |
| 2237 | goto err_pages; |
| 2238 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2239 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2240 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2241 | |
| 2242 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2243 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2244 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2245 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2246 | |
| 2247 | err_pages: |
| 2248 | while (i--) |
| 2249 | page_cache_release(obj_priv->pages[i]); |
| 2250 | |
| 2251 | drm_free_large(obj_priv->pages); |
| 2252 | obj_priv->pages = NULL; |
| 2253 | obj_priv->pages_refcount--; |
| 2254 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2255 | } |
| 2256 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2257 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2258 | { |
| 2259 | struct drm_gem_object *obj = reg->obj; |
| 2260 | struct drm_device *dev = obj->dev; |
| 2261 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2262 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2263 | int regnum = obj_priv->fence_reg; |
| 2264 | uint64_t val; |
| 2265 | |
| 2266 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2267 | 0xfffff000) << 32; |
| 2268 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2269 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2270 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2271 | |
| 2272 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2273 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2274 | val |= I965_FENCE_REG_VALID; |
| 2275 | |
| 2276 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2277 | } |
| 2278 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2279 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2280 | { |
| 2281 | struct drm_gem_object *obj = reg->obj; |
| 2282 | struct drm_device *dev = obj->dev; |
| 2283 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2284 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2285 | int regnum = obj_priv->fence_reg; |
| 2286 | uint64_t val; |
| 2287 | |
| 2288 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2289 | 0xfffff000) << 32; |
| 2290 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2291 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2292 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2293 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2294 | val |= I965_FENCE_REG_VALID; |
| 2295 | |
| 2296 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2297 | } |
| 2298 | |
| 2299 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2300 | { |
| 2301 | struct drm_gem_object *obj = reg->obj; |
| 2302 | struct drm_device *dev = obj->dev; |
| 2303 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2304 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2305 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2306 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2307 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2308 | uint32_t pitch_val; |
| 2309 | |
| 2310 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2311 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2312 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2313 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2314 | return; |
| 2315 | } |
| 2316 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2317 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2318 | HAS_128_BYTE_Y_TILING(dev)) |
| 2319 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2320 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2321 | tile_width = 512; |
| 2322 | |
| 2323 | /* Note: pitch better be a power of two tile widths */ |
| 2324 | pitch_val = obj_priv->stride / tile_width; |
| 2325 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2326 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2327 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2328 | HAS_128_BYTE_Y_TILING(dev)) |
| 2329 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2330 | else |
| 2331 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2332 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2333 | val = obj_priv->gtt_offset; |
| 2334 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2335 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2336 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2337 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2338 | val |= I830_FENCE_REG_VALID; |
| 2339 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2340 | if (regnum < 8) |
| 2341 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2342 | else |
| 2343 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2344 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2345 | } |
| 2346 | |
| 2347 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2348 | { |
| 2349 | struct drm_gem_object *obj = reg->obj; |
| 2350 | struct drm_device *dev = obj->dev; |
| 2351 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2352 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2353 | int regnum = obj_priv->fence_reg; |
| 2354 | uint32_t val; |
| 2355 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2356 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2357 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2358 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2359 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2360 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2361 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2362 | return; |
| 2363 | } |
| 2364 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2365 | pitch_val = obj_priv->stride / 128; |
| 2366 | pitch_val = ffs(pitch_val) - 1; |
| 2367 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2368 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2369 | val = obj_priv->gtt_offset; |
| 2370 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2371 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2372 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2373 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2374 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2375 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2376 | val |= I830_FENCE_REG_VALID; |
| 2377 | |
| 2378 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2379 | } |
| 2380 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2381 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2382 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2383 | { |
| 2384 | struct drm_i915_fence_reg *reg = NULL; |
| 2385 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2386 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2387 | struct drm_gem_object *obj = NULL; |
| 2388 | int i, avail, ret; |
| 2389 | |
| 2390 | /* First try to find a free reg */ |
| 2391 | avail = 0; |
| 2392 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2393 | reg = &dev_priv->fence_regs[i]; |
| 2394 | if (!reg->obj) |
| 2395 | return i; |
| 2396 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2397 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2398 | if (!obj_priv->pin_count) |
| 2399 | avail++; |
| 2400 | } |
| 2401 | |
| 2402 | if (avail == 0) |
| 2403 | return -ENOSPC; |
| 2404 | |
| 2405 | /* None available, try to steal one or wait for a user to finish */ |
| 2406 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2407 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2408 | lru_list) { |
| 2409 | obj = reg->obj; |
| 2410 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2411 | |
| 2412 | if (obj_priv->pin_count) |
| 2413 | continue; |
| 2414 | |
| 2415 | /* found one! */ |
| 2416 | i = obj_priv->fence_reg; |
| 2417 | break; |
| 2418 | } |
| 2419 | |
| 2420 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2421 | |
| 2422 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2423 | * might drop that one, causing a use-after-free in it. So hold a |
| 2424 | * private reference to obj like the other callers of put_fence_reg |
| 2425 | * (set_tiling ioctl) do. */ |
| 2426 | drm_gem_object_reference(obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2427 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2428 | drm_gem_object_unreference(obj); |
| 2429 | if (ret != 0) |
| 2430 | return ret; |
| 2431 | |
| 2432 | return i; |
| 2433 | } |
| 2434 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2435 | /** |
| 2436 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2437 | * @obj: object to map through a fence reg |
| 2438 | * |
| 2439 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2440 | * to them without having to worry about swizzling if the object is tiled. |
| 2441 | * |
| 2442 | * This function walks the fence regs looking for a free one for @obj, |
| 2443 | * stealing one if it can't find any. |
| 2444 | * |
| 2445 | * It then sets up the reg based on the object's properties: address, pitch |
| 2446 | * and tiling format. |
| 2447 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2448 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2449 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
| 2450 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2451 | { |
| 2452 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2453 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2454 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2455 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2456 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2457 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2458 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2459 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2460 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2461 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2462 | return 0; |
| 2463 | } |
| 2464 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2465 | switch (obj_priv->tiling_mode) { |
| 2466 | case I915_TILING_NONE: |
| 2467 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2468 | break; |
| 2469 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2470 | if (!obj_priv->stride) |
| 2471 | return -EINVAL; |
| 2472 | WARN((obj_priv->stride & (512 - 1)), |
| 2473 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2474 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2475 | break; |
| 2476 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2477 | if (!obj_priv->stride) |
| 2478 | return -EINVAL; |
| 2479 | WARN((obj_priv->stride & (128 - 1)), |
| 2480 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2481 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2482 | break; |
| 2483 | } |
| 2484 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2485 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2486 | if (ret < 0) |
| 2487 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2488 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2489 | obj_priv->fence_reg = ret; |
| 2490 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2491 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2492 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2493 | reg->obj = obj; |
| 2494 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2495 | switch (INTEL_INFO(dev)->gen) { |
| 2496 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2497 | sandybridge_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2498 | break; |
| 2499 | case 5: |
| 2500 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2501 | i965_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2502 | break; |
| 2503 | case 3: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2504 | i915_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2505 | break; |
| 2506 | case 2: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2507 | i830_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2508 | break; |
| 2509 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2510 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2511 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2512 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2513 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2514 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2515 | } |
| 2516 | |
| 2517 | /** |
| 2518 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2519 | * @obj: object to clear |
| 2520 | * |
| 2521 | * Zeroes out the fence register itself and clears out the associated |
| 2522 | * data structures in dev_priv and obj_priv. |
| 2523 | */ |
| 2524 | static void |
| 2525 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2526 | { |
| 2527 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2528 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2529 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2530 | struct drm_i915_fence_reg *reg = |
| 2531 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2532 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2533 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2534 | switch (INTEL_INFO(dev)->gen) { |
| 2535 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2536 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2537 | (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2538 | break; |
| 2539 | case 5: |
| 2540 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2541 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2542 | break; |
| 2543 | case 3: |
Chris Wilson | 9b74f73 | 2010-09-22 19:10:44 +0100 | [diff] [blame] | 2544 | if (obj_priv->fence_reg >= 8) |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2545 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2546 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2547 | case 2: |
| 2548 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2549 | |
| 2550 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2551 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2552 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2553 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2554 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2555 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2556 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2557 | } |
| 2558 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2559 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2560 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2561 | * to the buffer to finish, and then resets the fence register. |
| 2562 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2563 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2564 | * |
| 2565 | * Zeroes out the fence register itself and clears out the associated |
| 2566 | * data structures in dev_priv and obj_priv. |
| 2567 | */ |
| 2568 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2569 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
| 2570 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2571 | { |
| 2572 | struct drm_device *dev = obj->dev; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2573 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2574 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2575 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2576 | |
| 2577 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2578 | return 0; |
| 2579 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2580 | /* If we've changed tiling, GTT-mappings of the object |
| 2581 | * need to re-fault to ensure that the correct fence register |
| 2582 | * setup is in place. |
| 2583 | */ |
| 2584 | i915_gem_release_mmap(obj); |
| 2585 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2586 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2587 | * therefore we must wait for any outstanding access to complete |
| 2588 | * before clearing the fence. |
| 2589 | */ |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2590 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2591 | if (reg->gpu) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2592 | int ret; |
| 2593 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2594 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2595 | if (ret) |
| 2596 | return ret; |
| 2597 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2598 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2599 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2600 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2601 | |
| 2602 | reg->gpu = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2603 | } |
| 2604 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2605 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2606 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2607 | |
| 2608 | return 0; |
| 2609 | } |
| 2610 | |
| 2611 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2612 | * Finds free space in the GTT aperture and binds the object there. |
| 2613 | */ |
| 2614 | static int |
| 2615 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2616 | { |
| 2617 | struct drm_device *dev = obj->dev; |
| 2618 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2619 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2620 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2621 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2622 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2623 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2624 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2625 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2626 | return -EINVAL; |
| 2627 | } |
| 2628 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2629 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2630 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2631 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2632 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2633 | return -EINVAL; |
| 2634 | } |
| 2635 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2636 | /* If the object is bigger than the entire aperture, reject it early |
| 2637 | * before evicting everything in a vain attempt to find space. |
| 2638 | */ |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2639 | if (obj->size > dev_priv->mm.gtt_total) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2640 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2641 | return -E2BIG; |
| 2642 | } |
| 2643 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2644 | search_free: |
| 2645 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2646 | obj->size, alignment, 0); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2647 | if (free_space != NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2648 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2649 | alignment); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2650 | if (obj_priv->gtt_space == NULL) { |
| 2651 | /* If the gtt is empty and we're still having trouble |
| 2652 | * fitting our object in, we're out of memory. |
| 2653 | */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2654 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2655 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2656 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2657 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2658 | goto search_free; |
| 2659 | } |
| 2660 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2661 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2662 | if (ret) { |
| 2663 | drm_mm_put_block(obj_priv->gtt_space); |
| 2664 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2665 | |
| 2666 | if (ret == -ENOMEM) { |
| 2667 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2668 | ret = i915_gem_evict_something(dev, obj->size, |
| 2669 | alignment); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2670 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2671 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2672 | if (gfpmask) { |
| 2673 | gfpmask = 0; |
| 2674 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2675 | } |
| 2676 | |
| 2677 | return ret; |
| 2678 | } |
| 2679 | |
| 2680 | goto search_free; |
| 2681 | } |
| 2682 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2683 | return ret; |
| 2684 | } |
| 2685 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2686 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2687 | * into the GTT. |
| 2688 | */ |
| 2689 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2690 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2691 | obj->size >> PAGE_SHIFT, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2692 | obj_priv->gtt_space->start, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2693 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2695 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2696 | drm_mm_put_block(obj_priv->gtt_space); |
| 2697 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2698 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2699 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2700 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2701 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2702 | |
| 2703 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2704 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2705 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2706 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2707 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2708 | i915_gem_info_add_gtt(dev_priv, obj->size); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2709 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2710 | /* Assert that the object is not currently in any GPU domain. As it |
| 2711 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2712 | * a GPU cache |
| 2713 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2714 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2715 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2716 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2717 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2718 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2719 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2720 | return 0; |
| 2721 | } |
| 2722 | |
| 2723 | void |
| 2724 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2725 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2726 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | |
| 2728 | /* If we don't have a page list set up, then we're not pinned |
| 2729 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2730 | * again at bind time. |
| 2731 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2732 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | return; |
| 2734 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2735 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2736 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2737 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2738 | } |
| 2739 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2740 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2741 | static int |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2742 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 2743 | bool pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2744 | { |
| 2745 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2746 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2747 | |
| 2748 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2749 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2750 | |
| 2751 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2752 | old_write_domain = obj->write_domain; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2753 | i915_gem_flush_ring(dev, NULL, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2754 | to_intel_bo(obj)->ring, |
| 2755 | 0, obj->write_domain); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2756 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2757 | |
| 2758 | trace_i915_gem_object_change_domain(obj, |
| 2759 | obj->read_domains, |
| 2760 | old_write_domain); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2761 | |
| 2762 | if (pipelined) |
| 2763 | return 0; |
| 2764 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2765 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2766 | } |
| 2767 | |
| 2768 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2769 | static void |
| 2770 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2771 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2772 | uint32_t old_write_domain; |
| 2773 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2774 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2775 | return; |
| 2776 | |
| 2777 | /* No actual flushing is required for the GTT write domain. Writes |
| 2778 | * to it immediately go to main memory as far as we know, so there's |
| 2779 | * no chipset flush. It also doesn't land in render cache. |
| 2780 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2781 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2782 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2783 | |
| 2784 | trace_i915_gem_object_change_domain(obj, |
| 2785 | obj->read_domains, |
| 2786 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2787 | } |
| 2788 | |
| 2789 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2790 | static void |
| 2791 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2792 | { |
| 2793 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2794 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2795 | |
| 2796 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2797 | return; |
| 2798 | |
| 2799 | i915_gem_clflush_object(obj); |
| 2800 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2801 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2802 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2803 | |
| 2804 | trace_i915_gem_object_change_domain(obj, |
| 2805 | obj->read_domains, |
| 2806 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2807 | } |
| 2808 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2809 | /** |
| 2810 | * Moves a single object to the GTT read, and possibly write domain. |
| 2811 | * |
| 2812 | * This function returns when the move is complete, including waiting on |
| 2813 | * flushes to occur. |
| 2814 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2815 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2816 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2817 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2818 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2819 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2820 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2821 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2822 | /* Not valid to be called on unbound objects. */ |
| 2823 | if (obj_priv->gtt_space == NULL) |
| 2824 | return -EINVAL; |
| 2825 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2826 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2827 | if (ret != 0) |
| 2828 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2829 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2830 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2831 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2832 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2833 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2834 | if (ret) |
| 2835 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2836 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2837 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2838 | old_write_domain = obj->write_domain; |
| 2839 | old_read_domains = obj->read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2840 | |
| 2841 | /* It should now be out of any other write domains, and we can update |
| 2842 | * the domain values for our changes. |
| 2843 | */ |
| 2844 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2845 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2846 | if (write) { |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2847 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2848 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2849 | obj_priv->dirty = 1; |
| 2850 | } |
| 2851 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2852 | trace_i915_gem_object_change_domain(obj, |
| 2853 | old_read_domains, |
| 2854 | old_write_domain); |
| 2855 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2856 | return 0; |
| 2857 | } |
| 2858 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2859 | /* |
| 2860 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2861 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2862 | */ |
| 2863 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2864 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
| 2865 | bool pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2866 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2867 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2868 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2869 | int ret; |
| 2870 | |
| 2871 | /* Not valid to be called on unbound objects. */ |
| 2872 | if (obj_priv->gtt_space == NULL) |
| 2873 | return -EINVAL; |
| 2874 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2875 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2876 | if (ret) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2877 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2878 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2879 | /* Currently, we are always called from an non-interruptible context. */ |
| 2880 | if (!pipelined) { |
| 2881 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2882 | if (ret) |
| 2883 | return ret; |
| 2884 | } |
| 2885 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2886 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2887 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2888 | old_read_domains = obj->read_domains; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2889 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2890 | |
| 2891 | trace_i915_gem_object_change_domain(obj, |
| 2892 | old_read_domains, |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2893 | obj->write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2894 | |
| 2895 | return 0; |
| 2896 | } |
| 2897 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2898 | /** |
| 2899 | * Moves a single object to the CPU read, and possibly write domain. |
| 2900 | * |
| 2901 | * This function returns when the move is complete, including waiting on |
| 2902 | * flushes to occur. |
| 2903 | */ |
| 2904 | static int |
| 2905 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2906 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2907 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2908 | int ret; |
| 2909 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2910 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2911 | if (ret != 0) |
| 2912 | return ret; |
| 2913 | |
| 2914 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2915 | |
| 2916 | /* If we have a partially-valid cache of the object in the CPU, |
| 2917 | * finish invalidating it and free the per-page flags. |
| 2918 | */ |
| 2919 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2920 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2921 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2922 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2923 | if (ret) |
| 2924 | return ret; |
| 2925 | } |
| 2926 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2927 | old_write_domain = obj->write_domain; |
| 2928 | old_read_domains = obj->read_domains; |
| 2929 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2930 | /* Flush the CPU cache if it's still invalid. */ |
| 2931 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2932 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2933 | |
| 2934 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2935 | } |
| 2936 | |
| 2937 | /* It should now be out of any other write domains, and we can update |
| 2938 | * the domain values for our changes. |
| 2939 | */ |
| 2940 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2941 | |
| 2942 | /* If we're writing through the CPU, then the GPU read domains will |
| 2943 | * need to be invalidated at next use. |
| 2944 | */ |
| 2945 | if (write) { |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2946 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2947 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2948 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2949 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2950 | trace_i915_gem_object_change_domain(obj, |
| 2951 | old_read_domains, |
| 2952 | old_write_domain); |
| 2953 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2954 | return 0; |
| 2955 | } |
| 2956 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2957 | /* |
| 2958 | * Set the next domain for the specified object. This |
| 2959 | * may not actually perform the necessary flushing/invaliding though, |
| 2960 | * as that may want to be batched with other set_domain operations |
| 2961 | * |
| 2962 | * This is (we hope) the only really tricky part of gem. The goal |
| 2963 | * is fairly simple -- track which caches hold bits of the object |
| 2964 | * and make sure they remain coherent. A few concrete examples may |
| 2965 | * help to explain how it works. For shorthand, we use the notation |
| 2966 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2967 | * a pair of read and write domain masks. |
| 2968 | * |
| 2969 | * Case 1: the batch buffer |
| 2970 | * |
| 2971 | * 1. Allocated |
| 2972 | * 2. Written by CPU |
| 2973 | * 3. Mapped to GTT |
| 2974 | * 4. Read by GPU |
| 2975 | * 5. Unmapped from GTT |
| 2976 | * 6. Freed |
| 2977 | * |
| 2978 | * Let's take these a step at a time |
| 2979 | * |
| 2980 | * 1. Allocated |
| 2981 | * Pages allocated from the kernel may still have |
| 2982 | * cache contents, so we set them to (CPU, CPU) always. |
| 2983 | * 2. Written by CPU (using pwrite) |
| 2984 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2985 | * this function does nothing (as nothing changes) |
| 2986 | * 3. Mapped by GTT |
| 2987 | * This function asserts that the object is not |
| 2988 | * currently in any GPU-based read or write domains |
| 2989 | * 4. Read by GPU |
| 2990 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 2991 | * As write_domain is zero, this function adds in the |
| 2992 | * current read domains (CPU+COMMAND, 0). |
| 2993 | * flush_domains is set to CPU. |
| 2994 | * invalidate_domains is set to COMMAND |
| 2995 | * clflush is run to get data out of the CPU caches |
| 2996 | * then i915_dev_set_domain calls i915_gem_flush to |
| 2997 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 2998 | * 5. Unmapped from GTT |
| 2999 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3000 | * flush_domains and invalidate_domains end up both zero |
| 3001 | * so no flushing/invalidating happens |
| 3002 | * 6. Freed |
| 3003 | * yay, done |
| 3004 | * |
| 3005 | * Case 2: The shared render buffer |
| 3006 | * |
| 3007 | * 1. Allocated |
| 3008 | * 2. Mapped to GTT |
| 3009 | * 3. Read/written by GPU |
| 3010 | * 4. set_domain to (CPU,CPU) |
| 3011 | * 5. Read/written by CPU |
| 3012 | * 6. Read/written by GPU |
| 3013 | * |
| 3014 | * 1. Allocated |
| 3015 | * Same as last example, (CPU, CPU) |
| 3016 | * 2. Mapped to GTT |
| 3017 | * Nothing changes (assertions find that it is not in the GPU) |
| 3018 | * 3. Read/written by GPU |
| 3019 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3020 | * flush_domains gets CPU |
| 3021 | * invalidate_domains gets GPU |
| 3022 | * clflush (obj) |
| 3023 | * MI_FLUSH and drm_agp_chipset_flush |
| 3024 | * 4. set_domain (CPU, CPU) |
| 3025 | * flush_domains gets GPU |
| 3026 | * invalidate_domains gets CPU |
| 3027 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3028 | * This will include an MI_FLUSH to get the data from GPU |
| 3029 | * to memory |
| 3030 | * clflush (obj) to invalidate the CPU cache |
| 3031 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3032 | * 5. Read/written by CPU |
| 3033 | * cache lines are loaded and dirtied |
| 3034 | * 6. Read written by GPU |
| 3035 | * Same as last GPU access |
| 3036 | * |
| 3037 | * Case 3: The constant buffer |
| 3038 | * |
| 3039 | * 1. Allocated |
| 3040 | * 2. Written by CPU |
| 3041 | * 3. Read by GPU |
| 3042 | * 4. Updated (written) by CPU again |
| 3043 | * 5. Read by GPU |
| 3044 | * |
| 3045 | * 1. Allocated |
| 3046 | * (CPU, CPU) |
| 3047 | * 2. Written by CPU |
| 3048 | * (CPU, CPU) |
| 3049 | * 3. Read by GPU |
| 3050 | * (CPU+RENDER, 0) |
| 3051 | * flush_domains = CPU |
| 3052 | * invalidate_domains = RENDER |
| 3053 | * clflush (obj) |
| 3054 | * MI_FLUSH |
| 3055 | * drm_agp_chipset_flush |
| 3056 | * 4. Updated (written) by CPU again |
| 3057 | * (CPU, CPU) |
| 3058 | * flush_domains = 0 (no previous write domain) |
| 3059 | * invalidate_domains = 0 (no new read domains) |
| 3060 | * 5. Read by GPU |
| 3061 | * (CPU+RENDER, 0) |
| 3062 | * flush_domains = CPU |
| 3063 | * invalidate_domains = RENDER |
| 3064 | * clflush (obj) |
| 3065 | * MI_FLUSH |
| 3066 | * drm_agp_chipset_flush |
| 3067 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3068 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3069 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3070 | { |
| 3071 | struct drm_device *dev = obj->dev; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3072 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3073 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3074 | uint32_t invalidate_domains = 0; |
| 3075 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3076 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3077 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3078 | intel_mark_busy(dev, obj); |
| 3079 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3080 | /* |
| 3081 | * If the object isn't moving to a new write domain, |
| 3082 | * let the object stay in multiple read domains |
| 3083 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3084 | if (obj->pending_write_domain == 0) |
| 3085 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3086 | else |
| 3087 | obj_priv->dirty = 1; |
| 3088 | |
| 3089 | /* |
| 3090 | * Flush the current write domain if |
| 3091 | * the new read domains don't match. Invalidate |
| 3092 | * any read domains which differ from the old |
| 3093 | * write domain |
| 3094 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3095 | if (obj->write_domain && |
| 3096 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3097 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3098 | invalidate_domains |= |
| 3099 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3100 | } |
| 3101 | /* |
| 3102 | * Invalidate any read caches which may have |
| 3103 | * stale data. That is, any new read domains. |
| 3104 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3105 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3106 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3107 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3108 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3109 | old_read_domains = obj->read_domains; |
| 3110 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3111 | /* The actual obj->write_domain will be updated with |
| 3112 | * pending_write_domain after we emit the accumulated flush for all |
| 3113 | * of our domain changes in execbuffers (which clears objects' |
| 3114 | * write_domains). So if we have a current write domain that we |
| 3115 | * aren't changing, set pending_write_domain to that. |
| 3116 | */ |
| 3117 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3118 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3119 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3120 | |
| 3121 | dev->invalidate_domains |= invalidate_domains; |
| 3122 | dev->flush_domains |= flush_domains; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3123 | if (obj_priv->ring) |
| 3124 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3125 | |
| 3126 | trace_i915_gem_object_change_domain(obj, |
| 3127 | old_read_domains, |
| 3128 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3129 | } |
| 3130 | |
| 3131 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3132 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3133 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3134 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3135 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3136 | */ |
| 3137 | static void |
| 3138 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3139 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3140 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3141 | |
| 3142 | if (!obj_priv->page_cpu_valid) |
| 3143 | return; |
| 3144 | |
| 3145 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3146 | */ |
| 3147 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3148 | int i; |
| 3149 | |
| 3150 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3151 | if (obj_priv->page_cpu_valid[i]) |
| 3152 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3153 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3154 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3155 | } |
| 3156 | |
| 3157 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3158 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3159 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3160 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3161 | obj_priv->page_cpu_valid = NULL; |
| 3162 | } |
| 3163 | |
| 3164 | /** |
| 3165 | * Set the CPU read domain on a range of the object. |
| 3166 | * |
| 3167 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3168 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3169 | * pages have been flushed, and will be respected by |
| 3170 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3171 | * of the whole object. |
| 3172 | * |
| 3173 | * This function returns when the move is complete, including waiting on |
| 3174 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3175 | */ |
| 3176 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3177 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3178 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3179 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3180 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3181 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3182 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3183 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3184 | if (offset == 0 && size == obj->size) |
| 3185 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3186 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3187 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3188 | if (ret != 0) |
| 3189 | return ret; |
| 3190 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3191 | |
| 3192 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3193 | if (obj_priv->page_cpu_valid == NULL && |
| 3194 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3195 | return 0; |
| 3196 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3197 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3198 | * newly adding I915_GEM_DOMAIN_CPU |
| 3199 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3200 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3201 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3202 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3203 | if (obj_priv->page_cpu_valid == NULL) |
| 3204 | return -ENOMEM; |
| 3205 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3206 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3207 | |
| 3208 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3209 | * perspective. |
| 3210 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3211 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3212 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3213 | if (obj_priv->page_cpu_valid[i]) |
| 3214 | continue; |
| 3215 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3216 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | |
| 3218 | obj_priv->page_cpu_valid[i] = 1; |
| 3219 | } |
| 3220 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3221 | /* It should now be out of any other write domains, and we can update |
| 3222 | * the domain values for our changes. |
| 3223 | */ |
| 3224 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3225 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3226 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3227 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3228 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3229 | trace_i915_gem_object_change_domain(obj, |
| 3230 | old_read_domains, |
| 3231 | obj->write_domain); |
| 3232 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3233 | return 0; |
| 3234 | } |
| 3235 | |
| 3236 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3237 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3238 | */ |
| 3239 | static int |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3240 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
| 3241 | struct drm_file *file_priv, |
| 3242 | struct drm_i915_gem_exec_object2 *entry) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3244 | struct drm_device *dev = obj->base.dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3245 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3246 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3247 | struct drm_gem_object *target_obj = NULL; |
| 3248 | uint32_t target_handle = 0; |
| 3249 | int i, ret = 0; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3250 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3251 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3252 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3253 | struct drm_i915_gem_relocation_entry reloc; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3254 | uint32_t target_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3255 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3256 | if (__copy_from_user_inatomic(&reloc, |
| 3257 | user_relocs+i, |
| 3258 | sizeof(reloc))) { |
| 3259 | ret = -EFAULT; |
| 3260 | break; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3261 | } |
| 3262 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3263 | if (reloc.target_handle != target_handle) { |
| 3264 | drm_gem_object_unreference(target_obj); |
| 3265 | |
| 3266 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3267 | reloc.target_handle); |
| 3268 | if (target_obj == NULL) { |
| 3269 | ret = -ENOENT; |
| 3270 | break; |
| 3271 | } |
| 3272 | |
| 3273 | target_handle = reloc.target_handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3274 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3275 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3276 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3277 | #if WATCH_RELOC |
| 3278 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3279 | "read %08x write %08x gtt %08x " |
| 3280 | "presumed %08x delta %08x\n", |
| 3281 | __func__, |
| 3282 | obj, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3283 | (int) reloc.offset, |
| 3284 | (int) reloc.target_handle, |
| 3285 | (int) reloc.read_domains, |
| 3286 | (int) reloc.write_domain, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3287 | (int) target_offset, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3288 | (int) reloc.presumed_offset, |
| 3289 | reloc.delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3290 | #endif |
| 3291 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3292 | /* The target buffer should have appeared before us in the |
| 3293 | * exec_object list, so it should have a GTT space bound by now. |
| 3294 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3295 | if (target_offset == 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3296 | DRM_ERROR("No GTT space found for object %d\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3297 | reloc.target_handle); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3298 | ret = -EINVAL; |
| 3299 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3300 | } |
| 3301 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3302 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3303 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3304 | DRM_ERROR("reloc with multiple write domains: " |
| 3305 | "obj %p target %d offset %d " |
| 3306 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3307 | obj, reloc.target_handle, |
| 3308 | (int) reloc.offset, |
| 3309 | reloc.read_domains, |
| 3310 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3311 | ret = -EINVAL; |
| 3312 | break; |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3313 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3314 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 3315 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3316 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3317 | "obj %p target %d offset %d " |
| 3318 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3319 | obj, reloc.target_handle, |
| 3320 | (int) reloc.offset, |
| 3321 | reloc.read_domains, |
| 3322 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3323 | ret = -EINVAL; |
| 3324 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3325 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3326 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 3327 | reloc.write_domain != target_obj->pending_write_domain) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3328 | DRM_ERROR("Write domain conflict: " |
| 3329 | "obj %p target %d offset %d " |
| 3330 | "new %08x old %08x\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3331 | obj, reloc.target_handle, |
| 3332 | (int) reloc.offset, |
| 3333 | reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3334 | target_obj->pending_write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3335 | ret = -EINVAL; |
| 3336 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3337 | } |
| 3338 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3339 | target_obj->pending_read_domains |= reloc.read_domains; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3340 | target_obj->pending_write_domain = reloc.write_domain; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3341 | |
| 3342 | /* If the relocation already has the right value in it, no |
| 3343 | * more work needs to be done. |
| 3344 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3345 | if (target_offset == reloc.presumed_offset) |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3346 | continue; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3347 | |
| 3348 | /* Check that the relocation address is valid... */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3349 | if (reloc.offset > obj->base.size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3350 | DRM_ERROR("Relocation beyond object bounds: " |
| 3351 | "obj %p target %d offset %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3352 | obj, reloc.target_handle, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3353 | (int) reloc.offset, (int) obj->base.size); |
| 3354 | ret = -EINVAL; |
| 3355 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3356 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3357 | if (reloc.offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3358 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3359 | "obj %p target %d offset %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3360 | obj, reloc.target_handle, |
| 3361 | (int) reloc.offset); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3362 | ret = -EINVAL; |
| 3363 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3364 | } |
| 3365 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3366 | /* and points to somewhere within the target object. */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3367 | if (reloc.delta >= target_obj->size) { |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3368 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3369 | "obj %p target %d delta %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3370 | obj, reloc.target_handle, |
| 3371 | (int) reloc.delta, (int) target_obj->size); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3372 | ret = -EINVAL; |
| 3373 | break; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3374 | } |
| 3375 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3376 | reloc.delta += target_offset; |
| 3377 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3378 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
| 3379 | char *vaddr; |
| 3380 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3381 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT], KM_USER0); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3382 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
| 3383 | kunmap_atomic(vaddr, KM_USER0); |
| 3384 | } else { |
| 3385 | uint32_t __iomem *reloc_entry; |
| 3386 | void __iomem *reloc_page; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3387 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3388 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
| 3389 | if (ret) |
| 3390 | break; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3391 | |
| 3392 | /* Map the page containing the relocation we're going to perform. */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3393 | reloc.offset += obj->gtt_offset; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3394 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3395 | reloc.offset & PAGE_MASK, |
| 3396 | KM_USER0); |
| 3397 | reloc_entry = (uint32_t __iomem *) |
| 3398 | (reloc_page + (reloc.offset & ~PAGE_MASK)); |
| 3399 | iowrite32(reloc.delta, reloc_entry); |
| 3400 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3401 | } |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame^] | 3402 | |
| 3403 | /* and update the user's relocation entry */ |
| 3404 | reloc.presumed_offset = target_offset; |
| 3405 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3406 | &reloc.presumed_offset, |
| 3407 | sizeof(reloc.presumed_offset))) { |
| 3408 | ret = -EFAULT; |
| 3409 | break; |
| 3410 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3411 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3412 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3413 | drm_gem_object_unreference(target_obj); |
| 3414 | return ret; |
| 3415 | } |
| 3416 | |
| 3417 | static int |
| 3418 | i915_gem_execbuffer_pin(struct drm_device *dev, |
| 3419 | struct drm_file *file, |
| 3420 | struct drm_gem_object **object_list, |
| 3421 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3422 | int count) |
| 3423 | { |
| 3424 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3425 | int ret, i, retry; |
| 3426 | |
| 3427 | /* attempt to pin all of the buffers into the GTT */ |
| 3428 | for (retry = 0; retry < 2; retry++) { |
| 3429 | ret = 0; |
| 3430 | for (i = 0; i < count; i++) { |
| 3431 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
| 3432 | struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]); |
| 3433 | bool need_fence = |
| 3434 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3435 | obj->tiling_mode != I915_TILING_NONE; |
| 3436 | |
| 3437 | /* Check fence reg constraints and rebind if necessary */ |
| 3438 | if (need_fence && |
| 3439 | !i915_gem_object_fence_offset_ok(&obj->base, |
| 3440 | obj->tiling_mode)) { |
| 3441 | ret = i915_gem_object_unbind(&obj->base); |
| 3442 | if (ret) |
| 3443 | break; |
| 3444 | } |
| 3445 | |
| 3446 | ret = i915_gem_object_pin(&obj->base, entry->alignment); |
| 3447 | if (ret) |
| 3448 | break; |
| 3449 | |
| 3450 | /* |
| 3451 | * Pre-965 chips need a fence register set up in order |
| 3452 | * to properly handle blits to/from tiled surfaces. |
| 3453 | */ |
| 3454 | if (need_fence) { |
| 3455 | ret = i915_gem_object_get_fence_reg(&obj->base, true); |
| 3456 | if (ret) { |
| 3457 | i915_gem_object_unpin(&obj->base); |
| 3458 | break; |
| 3459 | } |
| 3460 | |
| 3461 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
| 3462 | } |
| 3463 | |
| 3464 | entry->offset = obj->gtt_offset; |
| 3465 | } |
| 3466 | |
| 3467 | while (i--) |
| 3468 | i915_gem_object_unpin(object_list[i]); |
| 3469 | |
| 3470 | if (ret == 0) |
| 3471 | break; |
| 3472 | |
| 3473 | if (ret != -ENOSPC || retry) |
| 3474 | return ret; |
| 3475 | |
| 3476 | ret = i915_gem_evict_everything(dev); |
| 3477 | if (ret) |
| 3478 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3479 | } |
| 3480 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3481 | return 0; |
| 3482 | } |
| 3483 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3484 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3485 | * emitted over 20 msec ago. |
| 3486 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3487 | * Note that if we were to use the current jiffies each time around the loop, |
| 3488 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3489 | * render a frame was over 20ms. |
| 3490 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3491 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3492 | * relatively low latency when blocking on a particular request to finish. |
| 3493 | */ |
| 3494 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3495 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3496 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3497 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3498 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3499 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3500 | struct drm_i915_gem_request *request; |
| 3501 | struct intel_ring_buffer *ring = NULL; |
| 3502 | u32 seqno = 0; |
| 3503 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3504 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3505 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3506 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3507 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3508 | break; |
| 3509 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3510 | ring = request->ring; |
| 3511 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3512 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3513 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3514 | |
| 3515 | if (seqno == 0) |
| 3516 | return 0; |
| 3517 | |
| 3518 | ret = 0; |
| 3519 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
| 3520 | /* And wait for the seqno passing without holding any locks and |
| 3521 | * causing extra latency for others. This is safe as the irq |
| 3522 | * generation is designed to be run atomically and so is |
| 3523 | * lockless. |
| 3524 | */ |
| 3525 | ring->user_irq_get(dev, ring); |
| 3526 | ret = wait_event_interruptible(ring->irq_queue, |
| 3527 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) |
| 3528 | || atomic_read(&dev_priv->mm.wedged)); |
| 3529 | ring->user_irq_put(dev, ring); |
| 3530 | |
| 3531 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3532 | ret = -EIO; |
| 3533 | } |
| 3534 | |
| 3535 | if (ret == 0) |
| 3536 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3537 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3538 | return ret; |
| 3539 | } |
| 3540 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3541 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3542 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3543 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3544 | { |
| 3545 | uint32_t exec_start, exec_len; |
| 3546 | |
| 3547 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3548 | exec_len = (uint32_t) exec->batch_len; |
| 3549 | |
| 3550 | if ((exec_start | exec_len) & 0x7) |
| 3551 | return -EINVAL; |
| 3552 | |
| 3553 | if (!exec_start) |
| 3554 | return -EINVAL; |
| 3555 | |
| 3556 | return 0; |
| 3557 | } |
| 3558 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3559 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3560 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3561 | int count) |
| 3562 | { |
| 3563 | int i; |
| 3564 | |
| 3565 | for (i = 0; i < count; i++) { |
| 3566 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 3567 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); |
| 3568 | |
| 3569 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3570 | return -EFAULT; |
| 3571 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame^] | 3572 | /* we may also need to update the presumed offsets */ |
| 3573 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3574 | return -EFAULT; |
| 3575 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3576 | if (fault_in_pages_readable(ptr, length)) |
| 3577 | return -EFAULT; |
| 3578 | } |
| 3579 | |
| 3580 | return 0; |
| 3581 | } |
| 3582 | |
| 3583 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3584 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3585 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3586 | struct drm_i915_gem_execbuffer2 *args, |
| 3587 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3588 | { |
| 3589 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3590 | struct drm_gem_object **object_list = NULL; |
| 3591 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3592 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3593 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3594 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3595 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3596 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3597 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3598 | struct intel_ring_buffer *ring = NULL; |
| 3599 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3600 | ret = i915_gem_check_is_wedged(dev); |
| 3601 | if (ret) |
| 3602 | return ret; |
| 3603 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3604 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3605 | if (ret) |
| 3606 | return ret; |
| 3607 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3608 | #if WATCH_EXEC |
| 3609 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3610 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3611 | #endif |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3612 | if (args->flags & I915_EXEC_BSD) { |
| 3613 | if (!HAS_BSD(dev)) { |
| 3614 | DRM_ERROR("execbuf with wrong flag\n"); |
| 3615 | return -EINVAL; |
| 3616 | } |
| 3617 | ring = &dev_priv->bsd_ring; |
| 3618 | } else { |
| 3619 | ring = &dev_priv->render_ring; |
| 3620 | } |
| 3621 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3622 | if (args->buffer_count < 1) { |
| 3623 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3624 | return -EINVAL; |
| 3625 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3626 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3627 | if (object_list == NULL) { |
| 3628 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3629 | args->buffer_count); |
| 3630 | ret = -ENOMEM; |
| 3631 | goto pre_mutex_err; |
| 3632 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3633 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3634 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3635 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3636 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3637 | if (cliprects == NULL) { |
| 3638 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3639 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3640 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3641 | |
| 3642 | ret = copy_from_user(cliprects, |
| 3643 | (struct drm_clip_rect __user *) |
| 3644 | (uintptr_t) args->cliprects_ptr, |
| 3645 | sizeof(*cliprects) * args->num_cliprects); |
| 3646 | if (ret != 0) { |
| 3647 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3648 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3649 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3650 | goto pre_mutex_err; |
| 3651 | } |
| 3652 | } |
| 3653 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3654 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3655 | if (request == NULL) { |
| 3656 | ret = -ENOMEM; |
| 3657 | goto pre_mutex_err; |
| 3658 | } |
| 3659 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3660 | ret = i915_mutex_lock_interruptible(dev); |
| 3661 | if (ret) |
| 3662 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3663 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3664 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3665 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3666 | ret = -EBUSY; |
| 3667 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3668 | } |
| 3669 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3670 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3671 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3672 | object_list[i] = drm_gem_object_lookup(dev, file, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3673 | exec_list[i].handle); |
| 3674 | if (object_list[i] == NULL) { |
| 3675 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3676 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3677 | /* prevent error path from reading uninitialized data */ |
| 3678 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3679 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3680 | goto err; |
| 3681 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3682 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3683 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3684 | if (obj_priv->in_execbuffer) { |
| 3685 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3686 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3687 | /* prevent error path from reading uninitialized data */ |
| 3688 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3689 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3690 | goto err; |
| 3691 | } |
| 3692 | obj_priv->in_execbuffer = true; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3693 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3695 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
| 3696 | ret = i915_gem_execbuffer_pin(dev, file, |
| 3697 | object_list, exec_list, |
| 3698 | args->buffer_count); |
| 3699 | if (ret) |
| 3700 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3701 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3702 | /* The objects are in their final locations, apply the relocations. */ |
| 3703 | for (i = 0; i < args->buffer_count; i++) { |
| 3704 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
| 3705 | obj->base.pending_read_domains = 0; |
| 3706 | obj->base.pending_write_domain = 0; |
| 3707 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); |
| 3708 | if (ret) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3709 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3710 | } |
| 3711 | |
| 3712 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3713 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3714 | if (batch_obj->pending_write_domain) { |
| 3715 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3716 | ret = -EINVAL; |
| 3717 | goto err; |
| 3718 | } |
| 3719 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3720 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3721 | /* Sanity check the batch buffer */ |
| 3722 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; |
| 3723 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3724 | if (ret != 0) { |
| 3725 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3726 | goto err; |
| 3727 | } |
| 3728 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3729 | /* Zero the global flush/invalidate flags. These |
| 3730 | * will be modified as new domains are computed |
| 3731 | * for each object |
| 3732 | */ |
| 3733 | dev->invalidate_domains = 0; |
| 3734 | dev->flush_domains = 0; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3735 | dev_priv->mm.flush_rings = 0; |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3736 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3737 | for (i = 0; i < args->buffer_count; i++) { |
| 3738 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3739 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3740 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3741 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3742 | } |
| 3743 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3744 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3745 | #if WATCH_EXEC |
| 3746 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3747 | __func__, |
| 3748 | dev->invalidate_domains, |
| 3749 | dev->flush_domains); |
| 3750 | #endif |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3751 | i915_gem_flush(dev, file, |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3752 | dev->invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3753 | dev->flush_domains, |
| 3754 | dev_priv->mm.flush_rings); |
Daniel Vetter | a691043 | 2010-02-02 17:08:37 +0100 | [diff] [blame] | 3755 | } |
| 3756 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3757 | for (i = 0; i < args->buffer_count; i++) { |
| 3758 | struct drm_gem_object *obj = object_list[i]; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3759 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3760 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3761 | |
| 3762 | obj->write_domain = obj->pending_write_domain; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3763 | if (obj->write_domain) |
| 3764 | list_move_tail(&obj_priv->gpu_write_list, |
| 3765 | &dev_priv->mm.gpu_write_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3766 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3767 | trace_i915_gem_object_change_domain(obj, |
| 3768 | obj->read_domains, |
| 3769 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3770 | } |
| 3771 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3772 | #if WATCH_COHERENCY |
| 3773 | for (i = 0; i < args->buffer_count; i++) { |
| 3774 | i915_gem_object_check_coherency(object_list[i], |
| 3775 | exec_list[i].handle); |
| 3776 | } |
| 3777 | #endif |
| 3778 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3779 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3780 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3781 | args->batch_len, |
| 3782 | __func__, |
| 3783 | ~0); |
| 3784 | #endif |
| 3785 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3786 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 3787 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 3788 | * to executing the batch and avoid stalling the CPU. |
| 3789 | */ |
| 3790 | flips = 0; |
| 3791 | for (i = 0; i < args->buffer_count; i++) { |
| 3792 | if (object_list[i]->write_domain) |
| 3793 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); |
| 3794 | } |
| 3795 | if (flips) { |
| 3796 | int plane, flip_mask; |
| 3797 | |
| 3798 | for (plane = 0; flips >> plane; plane++) { |
| 3799 | if (((flips >> plane) & 1) == 0) |
| 3800 | continue; |
| 3801 | |
| 3802 | if (plane) |
| 3803 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 3804 | else |
| 3805 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 3806 | |
| 3807 | intel_ring_begin(dev, ring, 2); |
| 3808 | intel_ring_emit(dev, ring, |
| 3809 | MI_WAIT_FOR_EVENT | flip_mask); |
| 3810 | intel_ring_emit(dev, ring, MI_NOOP); |
| 3811 | intel_ring_advance(dev, ring); |
| 3812 | } |
| 3813 | } |
| 3814 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3815 | /* Exec the batchbuffer */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3816 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3817 | cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3818 | if (ret) { |
| 3819 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3820 | goto err; |
| 3821 | } |
| 3822 | |
| 3823 | /* |
| 3824 | * Ensure that the commands in the batch buffer are |
| 3825 | * finished before the interrupt fires |
| 3826 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3827 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3828 | |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 3829 | for (i = 0; i < args->buffer_count; i++) { |
| 3830 | struct drm_gem_object *obj = object_list[i]; |
| 3831 | obj_priv = to_intel_bo(obj); |
| 3832 | |
| 3833 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 3834 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 3835 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3836 | i915_add_request(dev, file, request, ring); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3837 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3838 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3839 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3840 | for (i = 0; i < args->buffer_count; i++) { |
| 3841 | if (object_list[i]) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3842 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3843 | obj_priv->in_execbuffer = false; |
| 3844 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3845 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3846 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3847 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3848 | mutex_unlock(&dev->struct_mutex); |
| 3849 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3850 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3851 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3852 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3853 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3854 | |
| 3855 | return ret; |
| 3856 | } |
| 3857 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3858 | /* |
| 3859 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3860 | * list array and passes it to the real function. |
| 3861 | */ |
| 3862 | int |
| 3863 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3864 | struct drm_file *file_priv) |
| 3865 | { |
| 3866 | struct drm_i915_gem_execbuffer *args = data; |
| 3867 | struct drm_i915_gem_execbuffer2 exec2; |
| 3868 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3869 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3870 | int ret, i; |
| 3871 | |
| 3872 | #if WATCH_EXEC |
| 3873 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3874 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3875 | #endif |
| 3876 | |
| 3877 | if (args->buffer_count < 1) { |
| 3878 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3879 | return -EINVAL; |
| 3880 | } |
| 3881 | |
| 3882 | /* Copy in the exec list from userland */ |
| 3883 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 3884 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3885 | if (exec_list == NULL || exec2_list == NULL) { |
| 3886 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3887 | args->buffer_count); |
| 3888 | drm_free_large(exec_list); |
| 3889 | drm_free_large(exec2_list); |
| 3890 | return -ENOMEM; |
| 3891 | } |
| 3892 | ret = copy_from_user(exec_list, |
| 3893 | (struct drm_i915_relocation_entry __user *) |
| 3894 | (uintptr_t) args->buffers_ptr, |
| 3895 | sizeof(*exec_list) * args->buffer_count); |
| 3896 | if (ret != 0) { |
| 3897 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3898 | args->buffer_count, ret); |
| 3899 | drm_free_large(exec_list); |
| 3900 | drm_free_large(exec2_list); |
| 3901 | return -EFAULT; |
| 3902 | } |
| 3903 | |
| 3904 | for (i = 0; i < args->buffer_count; i++) { |
| 3905 | exec2_list[i].handle = exec_list[i].handle; |
| 3906 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 3907 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 3908 | exec2_list[i].alignment = exec_list[i].alignment; |
| 3909 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3910 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3911 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 3912 | else |
| 3913 | exec2_list[i].flags = 0; |
| 3914 | } |
| 3915 | |
| 3916 | exec2.buffers_ptr = args->buffers_ptr; |
| 3917 | exec2.buffer_count = args->buffer_count; |
| 3918 | exec2.batch_start_offset = args->batch_start_offset; |
| 3919 | exec2.batch_len = args->batch_len; |
| 3920 | exec2.DR1 = args->DR1; |
| 3921 | exec2.DR4 = args->DR4; |
| 3922 | exec2.num_cliprects = args->num_cliprects; |
| 3923 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3924 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3925 | |
| 3926 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 3927 | if (!ret) { |
| 3928 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3929 | for (i = 0; i < args->buffer_count; i++) |
| 3930 | exec_list[i].offset = exec2_list[i].offset; |
| 3931 | /* ... and back out to userspace */ |
| 3932 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3933 | (uintptr_t) args->buffers_ptr, |
| 3934 | exec_list, |
| 3935 | sizeof(*exec_list) * args->buffer_count); |
| 3936 | if (ret) { |
| 3937 | ret = -EFAULT; |
| 3938 | DRM_ERROR("failed to copy %d exec entries " |
| 3939 | "back to user (%d)\n", |
| 3940 | args->buffer_count, ret); |
| 3941 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3942 | } |
| 3943 | |
| 3944 | drm_free_large(exec_list); |
| 3945 | drm_free_large(exec2_list); |
| 3946 | return ret; |
| 3947 | } |
| 3948 | |
| 3949 | int |
| 3950 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 3951 | struct drm_file *file_priv) |
| 3952 | { |
| 3953 | struct drm_i915_gem_execbuffer2 *args = data; |
| 3954 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3955 | int ret; |
| 3956 | |
| 3957 | #if WATCH_EXEC |
| 3958 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3959 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3960 | #endif |
| 3961 | |
| 3962 | if (args->buffer_count < 1) { |
| 3963 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 3964 | return -EINVAL; |
| 3965 | } |
| 3966 | |
| 3967 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3968 | if (exec2_list == NULL) { |
| 3969 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3970 | args->buffer_count); |
| 3971 | return -ENOMEM; |
| 3972 | } |
| 3973 | ret = copy_from_user(exec2_list, |
| 3974 | (struct drm_i915_relocation_entry __user *) |
| 3975 | (uintptr_t) args->buffers_ptr, |
| 3976 | sizeof(*exec2_list) * args->buffer_count); |
| 3977 | if (ret != 0) { |
| 3978 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3979 | args->buffer_count, ret); |
| 3980 | drm_free_large(exec2_list); |
| 3981 | return -EFAULT; |
| 3982 | } |
| 3983 | |
| 3984 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 3985 | if (!ret) { |
| 3986 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3987 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3988 | (uintptr_t) args->buffers_ptr, |
| 3989 | exec2_list, |
| 3990 | sizeof(*exec2_list) * args->buffer_count); |
| 3991 | if (ret) { |
| 3992 | ret = -EFAULT; |
| 3993 | DRM_ERROR("failed to copy %d exec entries " |
| 3994 | "back to user (%d)\n", |
| 3995 | args->buffer_count, ret); |
| 3996 | } |
| 3997 | } |
| 3998 | |
| 3999 | drm_free_large(exec2_list); |
| 4000 | return ret; |
| 4001 | } |
| 4002 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4003 | int |
| 4004 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4005 | { |
| 4006 | struct drm_device *dev = obj->dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4007 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4008 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4009 | int ret; |
| 4010 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4011 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4012 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4013 | |
| 4014 | if (obj_priv->gtt_space != NULL) { |
| 4015 | if (alignment == 0) |
| 4016 | alignment = i915_gem_get_gtt_alignment(obj); |
| 4017 | if (obj_priv->gtt_offset & (alignment - 1)) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4018 | WARN(obj_priv->pin_count, |
| 4019 | "bo is already pinned with incorrect alignment:" |
| 4020 | " offset=%x, req.alignment=%x\n", |
| 4021 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4022 | ret = i915_gem_object_unbind(obj); |
| 4023 | if (ret) |
| 4024 | return ret; |
| 4025 | } |
| 4026 | } |
| 4027 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4028 | if (obj_priv->gtt_space == NULL) { |
| 4029 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4030 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4031 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4032 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4033 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4034 | obj_priv->pin_count++; |
| 4035 | |
| 4036 | /* If the object is not active and not pending a flush, |
| 4037 | * remove it from the inactive list |
| 4038 | */ |
| 4039 | if (obj_priv->pin_count == 1) { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4040 | i915_gem_info_add_pin(dev_priv, obj->size); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4041 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4042 | list_move_tail(&obj_priv->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4043 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4044 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4045 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4046 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4047 | return 0; |
| 4048 | } |
| 4049 | |
| 4050 | void |
| 4051 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4052 | { |
| 4053 | struct drm_device *dev = obj->dev; |
| 4054 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4055 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4056 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4057 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4058 | obj_priv->pin_count--; |
| 4059 | BUG_ON(obj_priv->pin_count < 0); |
| 4060 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4061 | |
| 4062 | /* If the object is no longer pinned, and is |
| 4063 | * neither active nor being flushed, then stick it on |
| 4064 | * the inactive list |
| 4065 | */ |
| 4066 | if (obj_priv->pin_count == 0) { |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4067 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4068 | list_move_tail(&obj_priv->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4069 | &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4070 | i915_gem_info_remove_pin(dev_priv, obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4071 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4072 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4073 | } |
| 4074 | |
| 4075 | int |
| 4076 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4077 | struct drm_file *file_priv) |
| 4078 | { |
| 4079 | struct drm_i915_gem_pin *args = data; |
| 4080 | struct drm_gem_object *obj; |
| 4081 | struct drm_i915_gem_object *obj_priv; |
| 4082 | int ret; |
| 4083 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4084 | ret = i915_mutex_lock_interruptible(dev); |
| 4085 | if (ret) |
| 4086 | return ret; |
| 4087 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4088 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4089 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4090 | ret = -ENOENT; |
| 4091 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4092 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4093 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4094 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4095 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4096 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4097 | ret = -EINVAL; |
| 4098 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4099 | } |
| 4100 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4101 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4102 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4103 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4104 | ret = -EINVAL; |
| 4105 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4106 | } |
| 4107 | |
| 4108 | obj_priv->user_pin_count++; |
| 4109 | obj_priv->pin_filp = file_priv; |
| 4110 | if (obj_priv->user_pin_count == 1) { |
| 4111 | ret = i915_gem_object_pin(obj, args->alignment); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4112 | if (ret) |
| 4113 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4114 | } |
| 4115 | |
| 4116 | /* XXX - flush the CPU caches for pinned objects |
| 4117 | * as the X server doesn't manage domains yet |
| 4118 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4119 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4120 | args->offset = obj_priv->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4121 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4122 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4123 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4124 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4125 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4126 | } |
| 4127 | |
| 4128 | int |
| 4129 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4130 | struct drm_file *file_priv) |
| 4131 | { |
| 4132 | struct drm_i915_gem_pin *args = data; |
| 4133 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4134 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4135 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4136 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4137 | ret = i915_mutex_lock_interruptible(dev); |
| 4138 | if (ret) |
| 4139 | return ret; |
| 4140 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4141 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4142 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4143 | ret = -ENOENT; |
| 4144 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4145 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4146 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4147 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4148 | if (obj_priv->pin_filp != file_priv) { |
| 4149 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4150 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4151 | ret = -EINVAL; |
| 4152 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4153 | } |
| 4154 | obj_priv->user_pin_count--; |
| 4155 | if (obj_priv->user_pin_count == 0) { |
| 4156 | obj_priv->pin_filp = NULL; |
| 4157 | i915_gem_object_unpin(obj); |
| 4158 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4159 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4160 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4161 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4162 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4163 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4164 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4165 | } |
| 4166 | |
| 4167 | int |
| 4168 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4169 | struct drm_file *file_priv) |
| 4170 | { |
| 4171 | struct drm_i915_gem_busy *args = data; |
| 4172 | struct drm_gem_object *obj; |
| 4173 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4174 | int ret; |
| 4175 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4176 | ret = i915_mutex_lock_interruptible(dev); |
| 4177 | if (ret) |
| 4178 | return ret; |
| 4179 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4180 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4181 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4182 | ret = -ENOENT; |
| 4183 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4184 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4185 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4186 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4187 | /* Count all active objects as busy, even if they are currently not used |
| 4188 | * by the gpu. Users of this interface expect objects to eventually |
| 4189 | * become non-busy without any further actions, therefore emit any |
| 4190 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4191 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4192 | args->busy = obj_priv->active; |
| 4193 | if (args->busy) { |
| 4194 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4195 | * object. Userspace calling this function indicates that it wants to |
| 4196 | * use this buffer rather sooner than later, so issuing the required |
| 4197 | * flush earlier is beneficial. |
| 4198 | */ |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 4199 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
| 4200 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 4201 | obj_priv->ring, |
| 4202 | 0, obj->write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4203 | |
| 4204 | /* Update the active list for the hardware's current position. |
| 4205 | * Otherwise this only updates on a delayed timer or when irqs |
| 4206 | * are actually unmasked, and our working set ends up being |
| 4207 | * larger than required. |
| 4208 | */ |
| 4209 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4210 | |
| 4211 | args->busy = obj_priv->active; |
| 4212 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4213 | |
| 4214 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4215 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4216 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4217 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4218 | } |
| 4219 | |
| 4220 | int |
| 4221 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4222 | struct drm_file *file_priv) |
| 4223 | { |
| 4224 | return i915_gem_ring_throttle(dev, file_priv); |
| 4225 | } |
| 4226 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4227 | int |
| 4228 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4229 | struct drm_file *file_priv) |
| 4230 | { |
| 4231 | struct drm_i915_gem_madvise *args = data; |
| 4232 | struct drm_gem_object *obj; |
| 4233 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4234 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4235 | |
| 4236 | switch (args->madv) { |
| 4237 | case I915_MADV_DONTNEED: |
| 4238 | case I915_MADV_WILLNEED: |
| 4239 | break; |
| 4240 | default: |
| 4241 | return -EINVAL; |
| 4242 | } |
| 4243 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4244 | ret = i915_mutex_lock_interruptible(dev); |
| 4245 | if (ret) |
| 4246 | return ret; |
| 4247 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4248 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4249 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4250 | ret = -ENOENT; |
| 4251 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4252 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4253 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4254 | |
| 4255 | if (obj_priv->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4256 | ret = -EINVAL; |
| 4257 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4258 | } |
| 4259 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4260 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4261 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4262 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4263 | /* if the object is no longer bound, discard its backing storage */ |
| 4264 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4265 | obj_priv->gtt_space == NULL) |
| 4266 | i915_gem_object_truncate(obj); |
| 4267 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4268 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4269 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4270 | out: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4271 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4272 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4273 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4274 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4275 | } |
| 4276 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4277 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4278 | size_t size) |
| 4279 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4280 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4281 | struct drm_i915_gem_object *obj; |
| 4282 | |
| 4283 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4284 | if (obj == NULL) |
| 4285 | return NULL; |
| 4286 | |
| 4287 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4288 | kfree(obj); |
| 4289 | return NULL; |
| 4290 | } |
| 4291 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4292 | i915_gem_info_add_obj(dev_priv, size); |
| 4293 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4294 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4295 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4296 | |
| 4297 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4298 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4299 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4300 | INIT_LIST_HEAD(&obj->mm_list); |
| 4301 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4302 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4303 | obj->madv = I915_MADV_WILLNEED; |
| 4304 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4305 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4306 | } |
| 4307 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4308 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4309 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4310 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4311 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4312 | return 0; |
| 4313 | } |
| 4314 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4315 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4316 | { |
| 4317 | struct drm_device *dev = obj->dev; |
| 4318 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4319 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4320 | int ret; |
| 4321 | |
| 4322 | ret = i915_gem_object_unbind(obj); |
| 4323 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4324 | list_move(&obj_priv->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4325 | &dev_priv->mm.deferred_free_list); |
| 4326 | return; |
| 4327 | } |
| 4328 | |
| 4329 | if (obj_priv->mmap_offset) |
| 4330 | i915_gem_free_mmap_offset(obj); |
| 4331 | |
| 4332 | drm_gem_object_release(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4333 | i915_gem_info_remove_obj(dev_priv, obj->size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4334 | |
| 4335 | kfree(obj_priv->page_cpu_valid); |
| 4336 | kfree(obj_priv->bit_17); |
| 4337 | kfree(obj_priv); |
| 4338 | } |
| 4339 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4340 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4341 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4342 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4343 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4344 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4345 | trace_i915_gem_object_destroy(obj); |
| 4346 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4347 | while (obj_priv->pin_count > 0) |
| 4348 | i915_gem_object_unpin(obj); |
| 4349 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4350 | if (obj_priv->phys_obj) |
| 4351 | i915_gem_detach_phys_object(dev, obj); |
| 4352 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4353 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4354 | } |
| 4355 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4356 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4357 | i915_gem_idle(struct drm_device *dev) |
| 4358 | { |
| 4359 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4360 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4361 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4362 | mutex_lock(&dev->struct_mutex); |
| 4363 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4364 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4365 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4366 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4367 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4368 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4369 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4370 | if (ret) { |
| 4371 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4372 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4373 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4374 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4375 | /* Under UMS, be paranoid and evict. */ |
| 4376 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4377 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4378 | if (ret) { |
| 4379 | mutex_unlock(&dev->struct_mutex); |
| 4380 | return ret; |
| 4381 | } |
| 4382 | } |
| 4383 | |
| 4384 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4385 | * We need to replace this with a semaphore, or something. |
| 4386 | * And not confound mm.suspended! |
| 4387 | */ |
| 4388 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4389 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4390 | |
| 4391 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4392 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4393 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4394 | mutex_unlock(&dev->struct_mutex); |
| 4395 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4396 | /* Cancel the retire work handler, which should be idle now. */ |
| 4397 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4398 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4399 | return 0; |
| 4400 | } |
| 4401 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4402 | /* |
| 4403 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4404 | * over cache flushing. |
| 4405 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4406 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4407 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4408 | { |
| 4409 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4410 | struct drm_gem_object *obj; |
| 4411 | struct drm_i915_gem_object *obj_priv; |
| 4412 | int ret; |
| 4413 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4414 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4415 | if (obj == NULL) { |
| 4416 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4417 | ret = -ENOMEM; |
| 4418 | goto err; |
| 4419 | } |
| 4420 | obj_priv = to_intel_bo(obj); |
| 4421 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4422 | |
| 4423 | ret = i915_gem_object_pin(obj, 4096); |
| 4424 | if (ret) |
| 4425 | goto err_unref; |
| 4426 | |
| 4427 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4428 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4429 | if (dev_priv->seqno_page == NULL) |
| 4430 | goto err_unpin; |
| 4431 | |
| 4432 | dev_priv->seqno_obj = obj; |
| 4433 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4434 | |
| 4435 | return 0; |
| 4436 | |
| 4437 | err_unpin: |
| 4438 | i915_gem_object_unpin(obj); |
| 4439 | err_unref: |
| 4440 | drm_gem_object_unreference(obj); |
| 4441 | err: |
| 4442 | return ret; |
| 4443 | } |
| 4444 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4445 | |
| 4446 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4447 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4448 | { |
| 4449 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4450 | struct drm_gem_object *obj; |
| 4451 | struct drm_i915_gem_object *obj_priv; |
| 4452 | |
| 4453 | obj = dev_priv->seqno_obj; |
| 4454 | obj_priv = to_intel_bo(obj); |
| 4455 | kunmap(obj_priv->pages[0]); |
| 4456 | i915_gem_object_unpin(obj); |
| 4457 | drm_gem_object_unreference(obj); |
| 4458 | dev_priv->seqno_obj = NULL; |
| 4459 | |
| 4460 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4461 | } |
| 4462 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4463 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4464 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4465 | { |
| 4466 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4467 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4468 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4469 | if (HAS_PIPE_CONTROL(dev)) { |
| 4470 | ret = i915_gem_init_pipe_control(dev); |
| 4471 | if (ret) |
| 4472 | return ret; |
| 4473 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4474 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4475 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4476 | if (ret) |
| 4477 | goto cleanup_pipe_control; |
| 4478 | |
| 4479 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4480 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4481 | if (ret) |
| 4482 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4483 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4484 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4485 | dev_priv->next_seqno = 1; |
| 4486 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4487 | return 0; |
| 4488 | |
| 4489 | cleanup_render_ring: |
| 4490 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
| 4491 | cleanup_pipe_control: |
| 4492 | if (HAS_PIPE_CONTROL(dev)) |
| 4493 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4494 | return ret; |
| 4495 | } |
| 4496 | |
| 4497 | void |
| 4498 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4499 | { |
| 4500 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4501 | |
| 4502 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4503 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4504 | if (HAS_PIPE_CONTROL(dev)) |
| 4505 | i915_gem_cleanup_pipe_control(dev); |
| 4506 | } |
| 4507 | |
| 4508 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4509 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4510 | struct drm_file *file_priv) |
| 4511 | { |
| 4512 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4513 | int ret; |
| 4514 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4515 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4516 | return 0; |
| 4517 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4518 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4519 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4520 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4521 | } |
| 4522 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4523 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4524 | dev_priv->mm.suspended = 0; |
| 4525 | |
| 4526 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4527 | if (ret != 0) { |
| 4528 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4529 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4530 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4531 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4532 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4533 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4534 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4535 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4536 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4537 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4538 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4539 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4540 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4541 | ret = drm_irq_install(dev); |
| 4542 | if (ret) |
| 4543 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4544 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4545 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4546 | |
| 4547 | cleanup_ringbuffer: |
| 4548 | mutex_lock(&dev->struct_mutex); |
| 4549 | i915_gem_cleanup_ringbuffer(dev); |
| 4550 | dev_priv->mm.suspended = 1; |
| 4551 | mutex_unlock(&dev->struct_mutex); |
| 4552 | |
| 4553 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4554 | } |
| 4555 | |
| 4556 | int |
| 4557 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4558 | struct drm_file *file_priv) |
| 4559 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4560 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4561 | return 0; |
| 4562 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4563 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4564 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4565 | } |
| 4566 | |
| 4567 | void |
| 4568 | i915_gem_lastclose(struct drm_device *dev) |
| 4569 | { |
| 4570 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4571 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4572 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4573 | return; |
| 4574 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4575 | ret = i915_gem_idle(dev); |
| 4576 | if (ret) |
| 4577 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4578 | } |
| 4579 | |
| 4580 | void |
| 4581 | i915_gem_load(struct drm_device *dev) |
| 4582 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4583 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4584 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4585 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4586 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4587 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4588 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4589 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4590 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4591 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4592 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4593 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
| 4594 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4595 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); |
| 4596 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4597 | for (i = 0; i < 16; i++) |
| 4598 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4599 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4600 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4601 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4602 | spin_lock(&shrink_list_lock); |
| 4603 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4604 | spin_unlock(&shrink_list_lock); |
| 4605 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4606 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4607 | if (IS_GEN3(dev)) { |
| 4608 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4609 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4610 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4611 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4612 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4613 | } |
| 4614 | } |
| 4615 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4616 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4617 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4618 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4619 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4620 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4621 | dev_priv->num_fence_regs = 16; |
| 4622 | else |
| 4623 | dev_priv->num_fence_regs = 8; |
| 4624 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4625 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4626 | switch (INTEL_INFO(dev)->gen) { |
| 4627 | case 6: |
| 4628 | for (i = 0; i < 16; i++) |
| 4629 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4630 | break; |
| 4631 | case 5: |
| 4632 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4633 | for (i = 0; i < 16; i++) |
| 4634 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4635 | break; |
| 4636 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4637 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4638 | for (i = 0; i < 8; i++) |
| 4639 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4640 | case 2: |
| 4641 | for (i = 0; i < 8; i++) |
| 4642 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4643 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4644 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4645 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4646 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4647 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4648 | |
| 4649 | /* |
| 4650 | * Create a physically contiguous memory object for this object |
| 4651 | * e.g. for cursor + overlay regs |
| 4652 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4653 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4654 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4655 | { |
| 4656 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4657 | struct drm_i915_gem_phys_object *phys_obj; |
| 4658 | int ret; |
| 4659 | |
| 4660 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4661 | return 0; |
| 4662 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4663 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4664 | if (!phys_obj) |
| 4665 | return -ENOMEM; |
| 4666 | |
| 4667 | phys_obj->id = id; |
| 4668 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4669 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4670 | if (!phys_obj->handle) { |
| 4671 | ret = -ENOMEM; |
| 4672 | goto kfree_obj; |
| 4673 | } |
| 4674 | #ifdef CONFIG_X86 |
| 4675 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4676 | #endif |
| 4677 | |
| 4678 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4679 | |
| 4680 | return 0; |
| 4681 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4682 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4683 | return ret; |
| 4684 | } |
| 4685 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4686 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4687 | { |
| 4688 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4689 | struct drm_i915_gem_phys_object *phys_obj; |
| 4690 | |
| 4691 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4692 | return; |
| 4693 | |
| 4694 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4695 | if (phys_obj->cur_obj) { |
| 4696 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4697 | } |
| 4698 | |
| 4699 | #ifdef CONFIG_X86 |
| 4700 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4701 | #endif |
| 4702 | drm_pci_free(dev, phys_obj->handle); |
| 4703 | kfree(phys_obj); |
| 4704 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4705 | } |
| 4706 | |
| 4707 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4708 | { |
| 4709 | int i; |
| 4710 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4711 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4712 | i915_gem_free_phys_object(dev, i); |
| 4713 | } |
| 4714 | |
| 4715 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4716 | struct drm_gem_object *obj) |
| 4717 | { |
| 4718 | struct drm_i915_gem_object *obj_priv; |
| 4719 | int i; |
| 4720 | int ret; |
| 4721 | int page_count; |
| 4722 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4723 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4724 | if (!obj_priv->phys_obj) |
| 4725 | return; |
| 4726 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4727 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4728 | if (ret) |
| 4729 | goto out; |
| 4730 | |
| 4731 | page_count = obj->size / PAGE_SIZE; |
| 4732 | |
| 4733 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4734 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4735 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4736 | |
| 4737 | memcpy(dst, src, PAGE_SIZE); |
| 4738 | kunmap_atomic(dst, KM_USER0); |
| 4739 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4740 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4741 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4742 | |
| 4743 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4744 | out: |
| 4745 | obj_priv->phys_obj->cur_obj = NULL; |
| 4746 | obj_priv->phys_obj = NULL; |
| 4747 | } |
| 4748 | |
| 4749 | int |
| 4750 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4751 | struct drm_gem_object *obj, |
| 4752 | int id, |
| 4753 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4754 | { |
| 4755 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4756 | struct drm_i915_gem_object *obj_priv; |
| 4757 | int ret = 0; |
| 4758 | int page_count; |
| 4759 | int i; |
| 4760 | |
| 4761 | if (id > I915_MAX_PHYS_OBJECT) |
| 4762 | return -EINVAL; |
| 4763 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4764 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4765 | |
| 4766 | if (obj_priv->phys_obj) { |
| 4767 | if (obj_priv->phys_obj->id == id) |
| 4768 | return 0; |
| 4769 | i915_gem_detach_phys_object(dev, obj); |
| 4770 | } |
| 4771 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4772 | /* create a new object */ |
| 4773 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4774 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4775 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4776 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4777 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4778 | goto out; |
| 4779 | } |
| 4780 | } |
| 4781 | |
| 4782 | /* bind to the object */ |
| 4783 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4784 | obj_priv->phys_obj->cur_obj = obj; |
| 4785 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4786 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4787 | if (ret) { |
| 4788 | DRM_ERROR("failed to get page list\n"); |
| 4789 | goto out; |
| 4790 | } |
| 4791 | |
| 4792 | page_count = obj->size / PAGE_SIZE; |
| 4793 | |
| 4794 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4795 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4796 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4797 | |
| 4798 | memcpy(dst, src, PAGE_SIZE); |
| 4799 | kunmap_atomic(src, KM_USER0); |
| 4800 | } |
| 4801 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4802 | i915_gem_object_put_pages(obj); |
| 4803 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4804 | return 0; |
| 4805 | out: |
| 4806 | return ret; |
| 4807 | } |
| 4808 | |
| 4809 | static int |
| 4810 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4811 | struct drm_i915_gem_pwrite *args, |
| 4812 | struct drm_file *file_priv) |
| 4813 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4814 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4815 | void *obj_addr; |
| 4816 | int ret; |
| 4817 | char __user *user_data; |
| 4818 | |
| 4819 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4820 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4821 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4822 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4823 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4824 | if (ret) |
| 4825 | return -EFAULT; |
| 4826 | |
| 4827 | drm_agp_chipset_flush(dev); |
| 4828 | return 0; |
| 4829 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4830 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4831 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4832 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4833 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4834 | |
| 4835 | /* Clean up our request list when the client is going away, so that |
| 4836 | * later retire_requests won't dereference our soon-to-be-gone |
| 4837 | * file_priv. |
| 4838 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4839 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4840 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4841 | struct drm_i915_gem_request *request; |
| 4842 | |
| 4843 | request = list_first_entry(&file_priv->mm.request_list, |
| 4844 | struct drm_i915_gem_request, |
| 4845 | client_list); |
| 4846 | list_del(&request->client_list); |
| 4847 | request->file_priv = NULL; |
| 4848 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4849 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4850 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4851 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4852 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4853 | i915_gpu_is_active(struct drm_device *dev) |
| 4854 | { |
| 4855 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4856 | int lists_empty; |
| 4857 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4858 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4859 | list_empty(&dev_priv->render_ring.active_list) && |
| 4860 | list_empty(&dev_priv->bsd_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4861 | |
| 4862 | return !lists_empty; |
| 4863 | } |
| 4864 | |
| 4865 | static int |
Dave Chinner | 7f8275d | 2010-07-19 14:56:17 +1000 | [diff] [blame] | 4866 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4867 | { |
| 4868 | drm_i915_private_t *dev_priv, *next_dev; |
| 4869 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4870 | int cnt = 0; |
| 4871 | int would_deadlock = 1; |
| 4872 | |
| 4873 | /* "fast-path" to count number of available objects */ |
| 4874 | if (nr_to_scan == 0) { |
| 4875 | spin_lock(&shrink_list_lock); |
| 4876 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4877 | struct drm_device *dev = dev_priv->dev; |
| 4878 | |
| 4879 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4880 | list_for_each_entry(obj_priv, |
| 4881 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4882 | mm_list) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4883 | cnt++; |
| 4884 | mutex_unlock(&dev->struct_mutex); |
| 4885 | } |
| 4886 | } |
| 4887 | spin_unlock(&shrink_list_lock); |
| 4888 | |
| 4889 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4890 | } |
| 4891 | |
| 4892 | spin_lock(&shrink_list_lock); |
| 4893 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4894 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4895 | /* first scan for clean buffers */ |
| 4896 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4897 | &shrink_list, mm.shrink_list) { |
| 4898 | struct drm_device *dev = dev_priv->dev; |
| 4899 | |
| 4900 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4901 | continue; |
| 4902 | |
| 4903 | spin_unlock(&shrink_list_lock); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 4904 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4905 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4906 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4907 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4908 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4909 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4910 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4911 | if (--nr_to_scan <= 0) |
| 4912 | break; |
| 4913 | } |
| 4914 | } |
| 4915 | |
| 4916 | spin_lock(&shrink_list_lock); |
| 4917 | mutex_unlock(&dev->struct_mutex); |
| 4918 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4919 | would_deadlock = 0; |
| 4920 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4921 | if (nr_to_scan <= 0) |
| 4922 | break; |
| 4923 | } |
| 4924 | |
| 4925 | /* second pass, evict/count anything still on the inactive list */ |
| 4926 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4927 | &shrink_list, mm.shrink_list) { |
| 4928 | struct drm_device *dev = dev_priv->dev; |
| 4929 | |
| 4930 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4931 | continue; |
| 4932 | |
| 4933 | spin_unlock(&shrink_list_lock); |
| 4934 | |
| 4935 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4936 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4937 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4938 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4939 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4940 | nr_to_scan--; |
| 4941 | } else |
| 4942 | cnt++; |
| 4943 | } |
| 4944 | |
| 4945 | spin_lock(&shrink_list_lock); |
| 4946 | mutex_unlock(&dev->struct_mutex); |
| 4947 | |
| 4948 | would_deadlock = 0; |
| 4949 | } |
| 4950 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4951 | if (nr_to_scan) { |
| 4952 | int active = 0; |
| 4953 | |
| 4954 | /* |
| 4955 | * We are desperate for pages, so as a last resort, wait |
| 4956 | * for the GPU to finish and discard whatever we can. |
| 4957 | * This has a dramatic impact to reduce the number of |
| 4958 | * OOM-killer events whilst running the GPU aggressively. |
| 4959 | */ |
| 4960 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4961 | struct drm_device *dev = dev_priv->dev; |
| 4962 | |
| 4963 | if (!mutex_trylock(&dev->struct_mutex)) |
| 4964 | continue; |
| 4965 | |
| 4966 | spin_unlock(&shrink_list_lock); |
| 4967 | |
| 4968 | if (i915_gpu_is_active(dev)) { |
| 4969 | i915_gpu_idle(dev); |
| 4970 | active++; |
| 4971 | } |
| 4972 | |
| 4973 | spin_lock(&shrink_list_lock); |
| 4974 | mutex_unlock(&dev->struct_mutex); |
| 4975 | } |
| 4976 | |
| 4977 | if (active) |
| 4978 | goto rescan; |
| 4979 | } |
| 4980 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4981 | spin_unlock(&shrink_list_lock); |
| 4982 | |
| 4983 | if (would_deadlock) |
| 4984 | return -1; |
| 4985 | else if (cnt > 0) |
| 4986 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4987 | else |
| 4988 | return 0; |
| 4989 | } |
| 4990 | |
| 4991 | static struct shrinker shrinker = { |
| 4992 | .shrink = i915_gem_shrink, |
| 4993 | .seeks = DEFAULT_SEEKS, |
| 4994 | }; |
| 4995 | |
| 4996 | __init void |
| 4997 | i915_gem_shrinker_init(void) |
| 4998 | { |
| 4999 | register_shrinker(&shrinker); |
| 5000 | } |
| 5001 | |
| 5002 | __exit void |
| 5003 | i915_gem_shrinker_exit(void) |
| 5004 | { |
| 5005 | unregister_shrinker(&shrinker); |
| 5006 | } |