blob: 80dc679c0f0169098b096c164dba2333584b7069 [file] [log] [blame]
Ben Gamari20172632009-02-17 20:08:50 -05001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
Chris Wilsonf3cd4742009-10-13 22:20:20 +010029#include <linux/debugfs.h>
Chris Wilsone637d2c2017-03-16 13:19:57 +000030#include <linux/sort.h>
Peter Zijlstrad92a8cf2017-03-03 10:13:38 +010031#include <linux/sched/mm.h>
Simon Farnsworth4e5359c2010-09-01 17:47:52 +010032#include "intel_drv.h"
Sagar Arun Kamblea2695742017-11-16 19:02:41 +053033#include "intel_guc_submission.h"
Ben Gamari20172632009-02-17 20:08:50 -050034
David Weinehall36cdd012016-08-22 13:59:31 +030035static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
36{
37 return to_i915(node->minor->dev);
38}
39
Chris Wilson70d39fe2010-08-25 16:03:34 +010040static int i915_capabilities(struct seq_file *m, void *data)
41{
David Weinehall36cdd012016-08-22 13:59:31 +030042 struct drm_i915_private *dev_priv = node_to_i915(m->private);
43 const struct intel_device_info *info = INTEL_INFO(dev_priv);
Michal Wajdeczkoa8c9b842017-12-19 11:43:44 +000044 struct drm_printer p = drm_seq_file_printer(m);
Chris Wilson70d39fe2010-08-25 16:03:34 +010045
David Weinehall36cdd012016-08-22 13:59:31 +030046 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
Jani Nikula2e0d26f2016-12-01 14:49:55 +020047 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
David Weinehall36cdd012016-08-22 13:59:31 +030048 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
Chris Wilson418e3cd2017-02-06 21:36:08 +000049
Michal Wajdeczkoa8c9b842017-12-19 11:43:44 +000050 intel_device_info_dump_flags(info, &p);
Michal Wajdeczko5fbbe8d2017-12-21 21:57:34 +000051 intel_device_info_dump_runtime(info, &p);
Chris Wilson70d39fe2010-08-25 16:03:34 +010052
Chris Wilson418e3cd2017-02-06 21:36:08 +000053 kernel_param_lock(THIS_MODULE);
Michal Wajdeczkoacfb9972017-12-19 11:43:46 +000054 i915_params_dump(&i915_modparams, &p);
Chris Wilson418e3cd2017-02-06 21:36:08 +000055 kernel_param_unlock(THIS_MODULE);
56
Chris Wilson70d39fe2010-08-25 16:03:34 +010057 return 0;
58}
Ben Gamari433e12f2009-02-17 20:08:51 -050059
Imre Deaka7363de2016-05-12 16:18:52 +030060static char get_active_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000061{
Chris Wilson573adb32016-08-04 16:32:39 +010062 return i915_gem_object_is_active(obj) ? '*' : ' ';
Chris Wilsona6172a82009-02-11 14:26:38 +000063}
64
Imre Deaka7363de2016-05-12 16:18:52 +030065static char get_pin_flag(struct drm_i915_gem_object *obj)
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +010066{
Chris Wilsonbd3d2252017-10-13 21:26:14 +010067 return obj->pin_global ? 'p' : ' ';
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +010068}
69
Imre Deaka7363de2016-05-12 16:18:52 +030070static char get_tiling_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000071{
Chris Wilson3e510a82016-08-05 10:14:23 +010072 switch (i915_gem_object_get_tiling(obj)) {
Akshay Joshi0206e352011-08-16 15:34:10 -040073 default:
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +010074 case I915_TILING_NONE: return ' ';
75 case I915_TILING_X: return 'X';
76 case I915_TILING_Y: return 'Y';
Akshay Joshi0206e352011-08-16 15:34:10 -040077 }
Chris Wilsona6172a82009-02-11 14:26:38 +000078}
79
Imre Deaka7363de2016-05-12 16:18:52 +030080static char get_global_flag(struct drm_i915_gem_object *obj)
Ben Widawsky1d693bc2013-07-31 17:00:00 -070081{
Chris Wilsona65adaf2017-10-09 09:43:57 +010082 return obj->userfault_count ? 'g' : ' ';
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +010083}
84
Imre Deaka7363de2016-05-12 16:18:52 +030085static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +010086{
Chris Wilsona4f5ea62016-10-28 13:58:35 +010087 return obj->mm.mapping ? 'M' : ' ';
Ben Widawsky1d693bc2013-07-31 17:00:00 -070088}
89
Tvrtko Ursulinca1543b2015-07-01 11:51:10 +010090static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
91{
92 u64 size = 0;
93 struct i915_vma *vma;
94
Chris Wilsone2189dd2017-12-07 21:14:07 +000095 for_each_ggtt_vma(vma, obj) {
96 if (drm_mm_node_allocated(&vma->node))
Tvrtko Ursulinca1543b2015-07-01 11:51:10 +010097 size += vma->node.size;
98 }
99
100 return size;
101}
102
Matthew Auld7393b7e2017-10-06 23:18:28 +0100103static const char *
104stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
105{
106 size_t x = 0;
107
108 switch (page_sizes) {
109 case 0:
110 return "";
111 case I915_GTT_PAGE_SIZE_4K:
112 return "4K";
113 case I915_GTT_PAGE_SIZE_64K:
114 return "64K";
115 case I915_GTT_PAGE_SIZE_2M:
116 return "2M";
117 default:
118 if (!buf)
119 return "M";
120
121 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
122 x += snprintf(buf + x, len - x, "2M, ");
123 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
124 x += snprintf(buf + x, len - x, "64K, ");
125 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
126 x += snprintf(buf + x, len - x, "4K, ");
127 buf[x-2] = '\0';
128
129 return buf;
130 }
131}
132
Chris Wilson37811fc2010-08-25 22:45:57 +0100133static void
134describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
135{
Chris Wilsonb4716182015-04-27 13:41:17 +0100136 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000137 struct intel_engine_cs *engine;
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700138 struct i915_vma *vma;
Chris Wilsonfaf5bf02016-08-04 16:32:37 +0100139 unsigned int frontbuffer_bits;
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800140 int pin_count = 0;
141
Chris Wilson188c1ab2016-04-03 14:14:20 +0100142 lockdep_assert_held(&obj->base.dev->struct_mutex);
143
Chris Wilsond07f0e52016-10-28 13:58:44 +0100144 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
Chris Wilson37811fc2010-08-25 22:45:57 +0100145 &obj->base,
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +0100146 get_active_flag(obj),
Chris Wilson37811fc2010-08-25 22:45:57 +0100147 get_pin_flag(obj),
148 get_tiling_flag(obj),
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700149 get_global_flag(obj),
Tvrtko Ursulinbe12a862016-04-15 11:34:52 +0100150 get_pin_mapped_flag(obj),
Eric Anholta05a5862011-12-20 08:54:15 -0800151 obj->base.size / 1024,
Chris Wilson37811fc2010-08-25 22:45:57 +0100152 obj->base.read_domains,
Chris Wilsond07f0e52016-10-28 13:58:44 +0100153 obj->base.write_domain,
David Weinehall36cdd012016-08-22 13:59:31 +0300154 i915_cache_level_str(dev_priv, obj->cache_level),
Chris Wilsona4f5ea62016-10-28 13:58:35 +0100155 obj->mm.dirty ? " dirty" : "",
156 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
Chris Wilson37811fc2010-08-25 22:45:57 +0100157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
Chris Wilson1c7f4bc2016-02-26 11:03:19 +0000159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
Chris Wilson20dfbde2016-08-04 16:32:30 +0100160 if (i915_vma_is_pinned(vma))
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800161 pin_count++;
Dan Carpenterba0635ff2015-02-25 16:17:48 +0300162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
Chris Wilsonbd3d2252017-10-13 21:26:14 +0100164 if (obj->pin_global)
165 seq_printf(m, " (global)");
Chris Wilson1c7f4bc2016-02-26 11:03:19 +0000166 list_for_each_entry(vma, &obj->vma_list, obj_link) {
Chris Wilson15717de2016-08-04 07:52:26 +0100167 if (!drm_mm_node_allocated(&vma->node))
168 continue;
169
Matthew Auld7393b7e2017-10-06 23:18:28 +0100170 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
Chris Wilson3272db52016-08-04 16:32:32 +0100171 i915_vma_is_ggtt(vma) ? "g" : "pp",
Matthew Auld7393b7e2017-10-06 23:18:28 +0100172 vma->node.start, vma->node.size,
173 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
Chris Wilson21976852017-01-12 11:21:08 +0000174 if (i915_vma_is_ggtt(vma)) {
175 switch (vma->ggtt_view.type) {
176 case I915_GGTT_VIEW_NORMAL:
177 seq_puts(m, ", normal");
178 break;
179
180 case I915_GGTT_VIEW_PARTIAL:
181 seq_printf(m, ", partial [%08llx+%x]",
Chris Wilson8bab11932017-01-14 00:28:25 +0000182 vma->ggtt_view.partial.offset << PAGE_SHIFT,
183 vma->ggtt_view.partial.size << PAGE_SHIFT);
Chris Wilson21976852017-01-12 11:21:08 +0000184 break;
185
186 case I915_GGTT_VIEW_ROTATED:
187 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
Chris Wilson8bab11932017-01-14 00:28:25 +0000188 vma->ggtt_view.rotated.plane[0].width,
189 vma->ggtt_view.rotated.plane[0].height,
190 vma->ggtt_view.rotated.plane[0].stride,
191 vma->ggtt_view.rotated.plane[0].offset,
192 vma->ggtt_view.rotated.plane[1].width,
193 vma->ggtt_view.rotated.plane[1].height,
194 vma->ggtt_view.rotated.plane[1].stride,
195 vma->ggtt_view.rotated.plane[1].offset);
Chris Wilson21976852017-01-12 11:21:08 +0000196 break;
197
198 default:
199 MISSING_CASE(vma->ggtt_view.type);
200 break;
201 }
202 }
Chris Wilson49ef5292016-08-18 17:17:00 +0100203 if (vma->fence)
204 seq_printf(m, " , fence: %d%s",
205 vma->fence->id,
206 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
Chris Wilson596c5922016-02-26 11:03:20 +0000207 seq_puts(m, ")");
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700208 }
Chris Wilsonc1ad11f2012-11-15 11:32:21 +0000209 if (obj->stolen)
Thierry Reding440fd522015-01-23 09:05:06 +0100210 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
Chris Wilson27c01aa2016-08-04 07:52:30 +0100211
Chris Wilsond07f0e52016-10-28 13:58:44 +0100212 engine = i915_gem_object_last_write_engine(obj);
Chris Wilson27c01aa2016-08-04 07:52:30 +0100213 if (engine)
214 seq_printf(m, " (%s)", engine->name);
215
Chris Wilsonfaf5bf02016-08-04 16:32:37 +0100216 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
217 if (frontbuffer_bits)
218 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
Chris Wilson37811fc2010-08-25 22:45:57 +0100219}
220
Chris Wilsone637d2c2017-03-16 13:19:57 +0000221static int obj_rank_by_stolen(const void *A, const void *B)
Chris Wilson6d2b88852013-08-07 18:30:54 +0100222{
Chris Wilsone637d2c2017-03-16 13:19:57 +0000223 const struct drm_i915_gem_object *a =
224 *(const struct drm_i915_gem_object **)A;
225 const struct drm_i915_gem_object *b =
226 *(const struct drm_i915_gem_object **)B;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100227
Rasmus Villemoes2d05fa12015-09-28 23:08:50 +0200228 if (a->stolen->start < b->stolen->start)
229 return -1;
230 if (a->stolen->start > b->stolen->start)
231 return 1;
232 return 0;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100233}
234
235static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
236{
David Weinehall36cdd012016-08-22 13:59:31 +0300237 struct drm_i915_private *dev_priv = node_to_i915(m->private);
238 struct drm_device *dev = &dev_priv->drm;
Chris Wilsone637d2c2017-03-16 13:19:57 +0000239 struct drm_i915_gem_object **objects;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100240 struct drm_i915_gem_object *obj;
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300241 u64 total_obj_size, total_gtt_size;
Chris Wilsone637d2c2017-03-16 13:19:57 +0000242 unsigned long total, count, n;
243 int ret;
244
245 total = READ_ONCE(dev_priv->mm.object_count);
Michal Hocko20981052017-05-17 14:23:12 +0200246 objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
Chris Wilsone637d2c2017-03-16 13:19:57 +0000247 if (!objects)
248 return -ENOMEM;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
Chris Wilsone637d2c2017-03-16 13:19:57 +0000252 goto out;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100253
254 total_obj_size = total_gtt_size = count = 0;
Chris Wilsonf2123812017-10-16 12:40:37 +0100255
256 spin_lock(&dev_priv->mm.obj_lock);
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
Chris Wilsone637d2c2017-03-16 13:19:57 +0000258 if (count == total)
259 break;
260
Chris Wilson6d2b88852013-08-07 18:30:54 +0100261 if (obj->stolen == NULL)
262 continue;
263
Chris Wilsone637d2c2017-03-16 13:19:57 +0000264 objects[count++] = obj;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100265 total_obj_size += obj->base.size;
Tvrtko Ursulinca1543b2015-07-01 11:51:10 +0100266 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
Chris Wilsone637d2c2017-03-16 13:19:57 +0000267
Chris Wilson6d2b88852013-08-07 18:30:54 +0100268 }
Chris Wilsonf2123812017-10-16 12:40:37 +0100269 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
Chris Wilsone637d2c2017-03-16 13:19:57 +0000270 if (count == total)
271 break;
272
Chris Wilson6d2b88852013-08-07 18:30:54 +0100273 if (obj->stolen == NULL)
274 continue;
275
Chris Wilsone637d2c2017-03-16 13:19:57 +0000276 objects[count++] = obj;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100277 total_obj_size += obj->base.size;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100278 }
Chris Wilsonf2123812017-10-16 12:40:37 +0100279 spin_unlock(&dev_priv->mm.obj_lock);
Chris Wilson6d2b88852013-08-07 18:30:54 +0100280
Chris Wilsone637d2c2017-03-16 13:19:57 +0000281 sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
282
283 seq_puts(m, "Stolen:\n");
284 for (n = 0; n < count; n++) {
285 seq_puts(m, " ");
286 describe_obj(m, objects[n]);
287 seq_putc(m, '\n');
288 }
289 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
Chris Wilson6d2b88852013-08-07 18:30:54 +0100290 count, total_obj_size, total_gtt_size);
Chris Wilsone637d2c2017-03-16 13:19:57 +0000291
292 mutex_unlock(&dev->struct_mutex);
293out:
Michal Hocko20981052017-05-17 14:23:12 +0200294 kvfree(objects);
Chris Wilsone637d2c2017-03-16 13:19:57 +0000295 return ret;
Chris Wilson6d2b88852013-08-07 18:30:54 +0100296}
297
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100298struct file_stats {
Chris Wilson6313c202014-03-19 13:45:45 +0000299 struct drm_i915_file_private *file_priv;
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300300 unsigned long count;
301 u64 total, unbound;
302 u64 global, shared;
303 u64 active, inactive;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100304};
305
306static int per_file_stats(int id, void *ptr, void *data)
307{
308 struct drm_i915_gem_object *obj = ptr;
309 struct file_stats *stats = data;
Chris Wilson6313c202014-03-19 13:45:45 +0000310 struct i915_vma *vma;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100311
Chris Wilson0caf81b2017-06-17 12:57:44 +0100312 lockdep_assert_held(&obj->base.dev->struct_mutex);
313
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100314 stats->count++;
315 stats->total += obj->base.size;
Chris Wilson15717de2016-08-04 07:52:26 +0100316 if (!obj->bind_count)
317 stats->unbound += obj->base.size;
Chris Wilsonc67a17e2014-03-19 13:45:46 +0000318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
320
Chris Wilson894eeec2016-08-04 07:52:20 +0100321 list_for_each_entry(vma, &obj->vma_list, obj_link) {
322 if (!drm_mm_node_allocated(&vma->node))
323 continue;
Chris Wilson6313c202014-03-19 13:45:45 +0000324
Chris Wilson3272db52016-08-04 16:32:32 +0100325 if (i915_vma_is_ggtt(vma)) {
Chris Wilson894eeec2016-08-04 07:52:20 +0100326 stats->global += vma->node.size;
327 } else {
328 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
Chris Wilson6313c202014-03-19 13:45:45 +0000329
Chris Wilson2bfa9962016-08-04 07:52:25 +0100330 if (ppgtt->base.file != stats->file_priv)
Chris Wilson6313c202014-03-19 13:45:45 +0000331 continue;
Chris Wilson6313c202014-03-19 13:45:45 +0000332 }
Chris Wilson894eeec2016-08-04 07:52:20 +0100333
Chris Wilsonb0decaf2016-08-04 07:52:44 +0100334 if (i915_vma_is_active(vma))
Chris Wilson894eeec2016-08-04 07:52:20 +0100335 stats->active += vma->node.size;
336 else
337 stats->inactive += vma->node.size;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100338 }
339
340 return 0;
341}
342
Chris Wilsonb0da1b72015-04-07 16:20:40 +0100343#define print_file_stats(m, name, stats) do { \
344 if (stats.count) \
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300345 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
Chris Wilsonb0da1b72015-04-07 16:20:40 +0100346 name, \
347 stats.count, \
348 stats.total, \
349 stats.active, \
350 stats.inactive, \
351 stats.global, \
352 stats.shared, \
353 stats.unbound); \
354} while (0)
Brad Volkin493018d2014-12-11 12:13:08 -0800355
356static void print_batch_pool_stats(struct seq_file *m,
357 struct drm_i915_private *dev_priv)
358{
359 struct drm_i915_gem_object *obj;
360 struct file_stats stats;
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000361 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +0530362 enum intel_engine_id id;
Dave Gordonb4ac5af2016-03-24 11:20:38 +0000363 int j;
Brad Volkin493018d2014-12-11 12:13:08 -0800364
365 memset(&stats, 0, sizeof(stats));
366
Akash Goel3b3f1652016-10-13 22:44:48 +0530367 for_each_engine(engine, dev_priv, id) {
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000368 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
Chris Wilson8d9d5742015-04-07 16:20:38 +0100369 list_for_each_entry(obj,
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000370 &engine->batch_pool.cache_list[j],
Chris Wilson8d9d5742015-04-07 16:20:38 +0100371 batch_pool_link)
372 per_file_stats(0, obj, &stats);
373 }
Chris Wilson06fbca72015-04-07 16:20:36 +0100374 }
Brad Volkin493018d2014-12-11 12:13:08 -0800375
Chris Wilsonb0da1b72015-04-07 16:20:40 +0100376 print_file_stats(m, "[k]batch pool", stats);
Brad Volkin493018d2014-12-11 12:13:08 -0800377}
378
Chris Wilson15da9562016-05-24 14:53:43 +0100379static int per_file_ctx_stats(int id, void *ptr, void *data)
380{
381 struct i915_gem_context *ctx = ptr;
382 int n;
383
384 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
385 if (ctx->engine[n].state)
Chris Wilsonbf3783e2016-08-15 10:48:54 +0100386 per_file_stats(0, ctx->engine[n].state->obj, data);
Chris Wilsondca33ec2016-08-02 22:50:20 +0100387 if (ctx->engine[n].ring)
Chris Wilson57e88532016-08-15 10:48:57 +0100388 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
Chris Wilson15da9562016-05-24 14:53:43 +0100389 }
390
391 return 0;
392}
393
394static void print_context_stats(struct seq_file *m,
395 struct drm_i915_private *dev_priv)
396{
David Weinehall36cdd012016-08-22 13:59:31 +0300397 struct drm_device *dev = &dev_priv->drm;
Chris Wilson15da9562016-05-24 14:53:43 +0100398 struct file_stats stats;
399 struct drm_file *file;
400
401 memset(&stats, 0, sizeof(stats));
402
David Weinehall36cdd012016-08-22 13:59:31 +0300403 mutex_lock(&dev->struct_mutex);
Chris Wilson15da9562016-05-24 14:53:43 +0100404 if (dev_priv->kernel_context)
405 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
406
David Weinehall36cdd012016-08-22 13:59:31 +0300407 list_for_each_entry(file, &dev->filelist, lhead) {
Chris Wilson15da9562016-05-24 14:53:43 +0100408 struct drm_i915_file_private *fpriv = file->driver_priv;
409 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
410 }
David Weinehall36cdd012016-08-22 13:59:31 +0300411 mutex_unlock(&dev->struct_mutex);
Chris Wilson15da9562016-05-24 14:53:43 +0100412
413 print_file_stats(m, "[k]contexts", stats);
414}
415
David Weinehall36cdd012016-08-22 13:59:31 +0300416static int i915_gem_object_info(struct seq_file *m, void *data)
Chris Wilson73aa8082010-09-30 11:46:12 +0100417{
David Weinehall36cdd012016-08-22 13:59:31 +0300418 struct drm_i915_private *dev_priv = node_to_i915(m->private);
419 struct drm_device *dev = &dev_priv->drm;
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300420 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Matthew Auld7393b7e2017-10-06 23:18:28 +0100421 u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
422 u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
Chris Wilson6299f992010-11-24 12:23:44 +0000423 struct drm_i915_gem_object *obj;
Matthew Auld7393b7e2017-10-06 23:18:28 +0100424 unsigned int page_sizes = 0;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100425 struct drm_file *file;
Matthew Auld7393b7e2017-10-06 23:18:28 +0100426 char buf[80];
Chris Wilson73aa8082010-09-30 11:46:12 +0100427 int ret;
428
429 ret = mutex_lock_interruptible(&dev->struct_mutex);
430 if (ret)
431 return ret;
432
Chris Wilson3ef7f222016-10-18 13:02:48 +0100433 seq_printf(m, "%u objects, %llu bytes\n",
Chris Wilson6299f992010-11-24 12:23:44 +0000434 dev_priv->mm.object_count,
435 dev_priv->mm.object_memory);
436
Chris Wilson1544c422016-08-15 13:18:16 +0100437 size = count = 0;
438 mapped_size = mapped_count = 0;
439 purgeable_size = purgeable_count = 0;
Matthew Auld7393b7e2017-10-06 23:18:28 +0100440 huge_size = huge_count = 0;
Chris Wilsonf2123812017-10-16 12:40:37 +0100441
442 spin_lock(&dev_priv->mm.obj_lock);
443 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100444 size += obj->base.size;
445 ++count;
Chris Wilson6c085a72012-08-20 11:40:46 +0200446
Chris Wilsona4f5ea62016-10-28 13:58:35 +0100447 if (obj->mm.madv == I915_MADV_DONTNEED) {
Chris Wilsonb7abb712012-08-20 11:33:30 +0200448 purgeable_size += obj->base.size;
449 ++purgeable_count;
450 }
Chris Wilson2bd160a2016-08-15 10:48:45 +0100451
Chris Wilsona4f5ea62016-10-28 13:58:35 +0100452 if (obj->mm.mapping) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100453 mapped_count++;
454 mapped_size += obj->base.size;
Tvrtko Ursulinbe19b102016-04-15 11:34:53 +0100455 }
Matthew Auld7393b7e2017-10-06 23:18:28 +0100456
457 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
458 huge_count++;
459 huge_size += obj->base.size;
460 page_sizes |= obj->mm.page_sizes.sg;
461 }
Chris Wilson6299f992010-11-24 12:23:44 +0000462 }
Chris Wilson2bd160a2016-08-15 10:48:45 +0100463 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
464
465 size = count = dpy_size = dpy_count = 0;
Chris Wilsonf2123812017-10-16 12:40:37 +0100466 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100467 size += obj->base.size;
468 ++count;
469
Chris Wilsonbd3d2252017-10-13 21:26:14 +0100470 if (obj->pin_global) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100471 dpy_size += obj->base.size;
472 ++dpy_count;
473 }
474
Chris Wilsona4f5ea62016-10-28 13:58:35 +0100475 if (obj->mm.madv == I915_MADV_DONTNEED) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100476 purgeable_size += obj->base.size;
477 ++purgeable_count;
478 }
479
Chris Wilsona4f5ea62016-10-28 13:58:35 +0100480 if (obj->mm.mapping) {
Chris Wilson2bd160a2016-08-15 10:48:45 +0100481 mapped_count++;
482 mapped_size += obj->base.size;
483 }
Matthew Auld7393b7e2017-10-06 23:18:28 +0100484
485 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
486 huge_count++;
487 huge_size += obj->base.size;
488 page_sizes |= obj->mm.page_sizes.sg;
489 }
Chris Wilson2bd160a2016-08-15 10:48:45 +0100490 }
Chris Wilsonf2123812017-10-16 12:40:37 +0100491 spin_unlock(&dev_priv->mm.obj_lock);
492
Chris Wilson2bd160a2016-08-15 10:48:45 +0100493 seq_printf(m, "%u bound objects, %llu bytes\n",
494 count, size);
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300495 seq_printf(m, "%u purgeable objects, %llu bytes\n",
Chris Wilsonb7abb712012-08-20 11:33:30 +0200496 purgeable_count, purgeable_size);
Chris Wilson2bd160a2016-08-15 10:48:45 +0100497 seq_printf(m, "%u mapped objects, %llu bytes\n",
498 mapped_count, mapped_size);
Matthew Auld7393b7e2017-10-06 23:18:28 +0100499 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
500 huge_count,
501 stringify_page_sizes(page_sizes, buf, sizeof(buf)),
502 huge_size);
Chris Wilsonbd3d2252017-10-13 21:26:14 +0100503 seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
Chris Wilson2bd160a2016-08-15 10:48:45 +0100504 dpy_count, dpy_size);
Chris Wilson6299f992010-11-24 12:23:44 +0000505
Matthew Auldb7128ef2017-12-11 15:18:22 +0000506 seq_printf(m, "%llu [%pa] gtt total\n",
507 ggtt->base.total, &ggtt->mappable_end);
Matthew Auld7393b7e2017-10-06 23:18:28 +0100508 seq_printf(m, "Supported page sizes: %s\n",
509 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
510 buf, sizeof(buf)));
Chris Wilson73aa8082010-09-30 11:46:12 +0100511
Damien Lespiau267f0c92013-06-24 22:59:48 +0100512 seq_putc(m, '\n');
Brad Volkin493018d2014-12-11 12:13:08 -0800513 print_batch_pool_stats(m, dev_priv);
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200514 mutex_unlock(&dev->struct_mutex);
515
516 mutex_lock(&dev->filelist_mutex);
Chris Wilson15da9562016-05-24 14:53:43 +0100517 print_context_stats(m, dev_priv);
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100518 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
519 struct file_stats stats;
Chris Wilsonc84455b2016-08-15 10:49:08 +0100520 struct drm_i915_file_private *file_priv = file->driver_priv;
521 struct drm_i915_gem_request *request;
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900522 struct task_struct *task;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100523
Chris Wilson0caf81b2017-06-17 12:57:44 +0100524 mutex_lock(&dev->struct_mutex);
525
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100526 memset(&stats, 0, sizeof(stats));
Chris Wilson6313c202014-03-19 13:45:45 +0000527 stats.file_priv = file->driver_priv;
Chris Wilson5b5ffff2014-06-17 09:56:24 +0100528 spin_lock(&file->table_lock);
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100529 idr_for_each(&file->object_idr, per_file_stats, &stats);
Chris Wilson5b5ffff2014-06-17 09:56:24 +0100530 spin_unlock(&file->table_lock);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900531 /*
532 * Although we have a valid reference on file->pid, that does
533 * not guarantee that the task_struct who called get_pid() is
534 * still alive (e.g. get_pid(current) => fork() => exit()).
535 * Therefore, we need to protect this ->comm access using RCU.
536 */
Chris Wilsonc84455b2016-08-15 10:49:08 +0100537 request = list_first_entry_or_null(&file_priv->mm.request_list,
538 struct drm_i915_gem_request,
Chris Wilsonc8659ef2017-03-02 12:25:25 +0000539 client_link);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900540 rcu_read_lock();
Chris Wilsonc84455b2016-08-15 10:49:08 +0100541 task = pid_task(request && request->ctx->pid ?
542 request->ctx->pid : file->pid,
543 PIDTYPE_PID);
Brad Volkin493018d2014-12-11 12:13:08 -0800544 print_file_stats(m, task ? task->comm : "<unknown>", stats);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900545 rcu_read_unlock();
Chris Wilson0caf81b2017-06-17 12:57:44 +0100546
Chris Wilsonc84455b2016-08-15 10:49:08 +0100547 mutex_unlock(&dev->struct_mutex);
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100548 }
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200549 mutex_unlock(&dev->filelist_mutex);
Chris Wilson73aa8082010-09-30 11:46:12 +0100550
551 return 0;
552}
553
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100554static int i915_gem_gtt_info(struct seq_file *m, void *data)
Chris Wilson08c18322011-01-10 00:00:24 +0000555{
Damien Lespiau9f25d002014-05-13 15:30:28 +0100556 struct drm_info_node *node = m->private;
David Weinehall36cdd012016-08-22 13:59:31 +0300557 struct drm_i915_private *dev_priv = node_to_i915(node);
558 struct drm_device *dev = &dev_priv->drm;
Chris Wilsonf2123812017-10-16 12:40:37 +0100559 struct drm_i915_gem_object **objects;
Chris Wilson08c18322011-01-10 00:00:24 +0000560 struct drm_i915_gem_object *obj;
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300561 u64 total_obj_size, total_gtt_size;
Chris Wilsonf2123812017-10-16 12:40:37 +0100562 unsigned long nobject, n;
Chris Wilson08c18322011-01-10 00:00:24 +0000563 int count, ret;
564
Chris Wilsonf2123812017-10-16 12:40:37 +0100565 nobject = READ_ONCE(dev_priv->mm.object_count);
566 objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
567 if (!objects)
568 return -ENOMEM;
569
Chris Wilson08c18322011-01-10 00:00:24 +0000570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
Chris Wilsonf2123812017-10-16 12:40:37 +0100574 count = 0;
575 spin_lock(&dev_priv->mm.obj_lock);
576 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
577 objects[count++] = obj;
578 if (count == nobject)
579 break;
580 }
581 spin_unlock(&dev_priv->mm.obj_lock);
582
583 total_obj_size = total_gtt_size = 0;
584 for (n = 0; n < count; n++) {
585 obj = objects[n];
586
Damien Lespiau267f0c92013-06-24 22:59:48 +0100587 seq_puts(m, " ");
Chris Wilson08c18322011-01-10 00:00:24 +0000588 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100589 seq_putc(m, '\n');
Chris Wilson08c18322011-01-10 00:00:24 +0000590 total_obj_size += obj->base.size;
Tvrtko Ursulinca1543b2015-07-01 11:51:10 +0100591 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
Chris Wilson08c18322011-01-10 00:00:24 +0000592 }
593
594 mutex_unlock(&dev->struct_mutex);
595
Mika Kuoppalac44ef602015-06-25 18:35:05 +0300596 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
Chris Wilson08c18322011-01-10 00:00:24 +0000597 count, total_obj_size, total_gtt_size);
Chris Wilsonf2123812017-10-16 12:40:37 +0100598 kvfree(objects);
Chris Wilson08c18322011-01-10 00:00:24 +0000599
600 return 0;
601}
602
Brad Volkin493018d2014-12-11 12:13:08 -0800603static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
604{
David Weinehall36cdd012016-08-22 13:59:31 +0300605 struct drm_i915_private *dev_priv = node_to_i915(m->private);
606 struct drm_device *dev = &dev_priv->drm;
Brad Volkin493018d2014-12-11 12:13:08 -0800607 struct drm_i915_gem_object *obj;
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000608 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +0530609 enum intel_engine_id id;
Chris Wilson8d9d5742015-04-07 16:20:38 +0100610 int total = 0;
Dave Gordonb4ac5af2016-03-24 11:20:38 +0000611 int ret, j;
Brad Volkin493018d2014-12-11 12:13:08 -0800612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
616
Akash Goel3b3f1652016-10-13 22:44:48 +0530617 for_each_engine(engine, dev_priv, id) {
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000618 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
Chris Wilson8d9d5742015-04-07 16:20:38 +0100619 int count;
620
621 count = 0;
622 list_for_each_entry(obj,
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000623 &engine->batch_pool.cache_list[j],
Chris Wilson8d9d5742015-04-07 16:20:38 +0100624 batch_pool_link)
625 count++;
626 seq_printf(m, "%s cache[%d]: %d objects\n",
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000627 engine->name, j, count);
Chris Wilson8d9d5742015-04-07 16:20:38 +0100628
629 list_for_each_entry(obj,
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000630 &engine->batch_pool.cache_list[j],
Chris Wilson8d9d5742015-04-07 16:20:38 +0100631 batch_pool_link) {
632 seq_puts(m, " ");
633 describe_obj(m, obj);
634 seq_putc(m, '\n');
635 }
636
637 total += count;
Chris Wilson06fbca72015-04-07 16:20:36 +0100638 }
Brad Volkin493018d2014-12-11 12:13:08 -0800639 }
640
Chris Wilson8d9d5742015-04-07 16:20:38 +0100641 seq_printf(m, "total: %d\n", total);
Brad Volkin493018d2014-12-11 12:13:08 -0800642
643 mutex_unlock(&dev->struct_mutex);
644
645 return 0;
646}
647
Ben Gamari20172632009-02-17 20:08:50 -0500648static int i915_interrupt_info(struct seq_file *m, void *data)
649{
David Weinehall36cdd012016-08-22 13:59:31 +0300650 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000651 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +0530652 enum intel_engine_id id;
Chris Wilson4bb05042016-09-03 07:53:43 +0100653 int i, pipe;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100654
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200655 intel_runtime_pm_get(dev_priv);
Ben Gamari20172632009-02-17 20:08:50 -0500656
David Weinehall36cdd012016-08-22 13:59:31 +0300657 if (IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300658 seq_printf(m, "Master Interrupt Control:\t%08x\n",
659 I915_READ(GEN8_MASTER_IRQ));
660
661 seq_printf(m, "Display IER:\t%08x\n",
662 I915_READ(VLV_IER));
663 seq_printf(m, "Display IIR:\t%08x\n",
664 I915_READ(VLV_IIR));
665 seq_printf(m, "Display IIR_RW:\t%08x\n",
666 I915_READ(VLV_IIR_RW));
667 seq_printf(m, "Display IMR:\t%08x\n",
668 I915_READ(VLV_IMR));
Chris Wilson9c870d02016-10-24 13:42:15 +0100669 for_each_pipe(dev_priv, pipe) {
670 enum intel_display_power_domain power_domain;
671
672 power_domain = POWER_DOMAIN_PIPE(pipe);
673 if (!intel_display_power_get_if_enabled(dev_priv,
674 power_domain)) {
675 seq_printf(m, "Pipe %c power disabled\n",
676 pipe_name(pipe));
677 continue;
678 }
679
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300680 seq_printf(m, "Pipe %c stat:\t%08x\n",
681 pipe_name(pipe),
682 I915_READ(PIPESTAT(pipe)));
683
Chris Wilson9c870d02016-10-24 13:42:15 +0100684 intel_display_power_put(dev_priv, power_domain);
685 }
686
687 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300688 seq_printf(m, "Port hotplug:\t%08x\n",
689 I915_READ(PORT_HOTPLUG_EN));
690 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
691 I915_READ(VLV_DPFLIPSTAT));
692 seq_printf(m, "DPINVGTT:\t%08x\n",
693 I915_READ(DPINVGTT));
Chris Wilson9c870d02016-10-24 13:42:15 +0100694 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
Ville Syrjälä74e1ca82014-04-09 13:28:09 +0300695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
705 seq_printf(m, "PCU interrupt mask:\t%08x\n",
706 I915_READ(GEN8_PCU_IMR));
707 seq_printf(m, "PCU interrupt identity:\t%08x\n",
708 I915_READ(GEN8_PCU_IIR));
709 seq_printf(m, "PCU interrupt enable:\t%08x\n",
710 I915_READ(GEN8_PCU_IER));
David Weinehall36cdd012016-08-22 13:59:31 +0300711 } else if (INTEL_GEN(dev_priv) >= 8) {
Ben Widawskya123f152013-11-02 21:07:10 -0700712 seq_printf(m, "Master Interrupt Control:\t%08x\n",
713 I915_READ(GEN8_MASTER_IRQ));
714
715 for (i = 0; i < 4; i++) {
716 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
717 i, I915_READ(GEN8_GT_IMR(i)));
718 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
719 i, I915_READ(GEN8_GT_IIR(i)));
720 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
721 i, I915_READ(GEN8_GT_IER(i)));
722 }
723
Damien Lespiau055e3932014-08-18 13:49:10 +0100724 for_each_pipe(dev_priv, pipe) {
Imre Deake1296492016-02-12 18:55:17 +0200725 enum intel_display_power_domain power_domain;
726
727 power_domain = POWER_DOMAIN_PIPE(pipe);
728 if (!intel_display_power_get_if_enabled(dev_priv,
729 power_domain)) {
Paulo Zanoni22c59962014-08-08 17:45:32 -0300730 seq_printf(m, "Pipe %c power disabled\n",
731 pipe_name(pipe));
732 continue;
733 }
Ben Widawskya123f152013-11-02 21:07:10 -0700734 seq_printf(m, "Pipe %c IMR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000735 pipe_name(pipe),
736 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700737 seq_printf(m, "Pipe %c IIR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000738 pipe_name(pipe),
739 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700740 seq_printf(m, "Pipe %c IER:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000741 pipe_name(pipe),
742 I915_READ(GEN8_DE_PIPE_IER(pipe)));
Imre Deake1296492016-02-12 18:55:17 +0200743
744 intel_display_power_put(dev_priv, power_domain);
Ben Widawskya123f152013-11-02 21:07:10 -0700745 }
746
747 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
748 I915_READ(GEN8_DE_PORT_IMR));
749 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
750 I915_READ(GEN8_DE_PORT_IIR));
751 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
752 I915_READ(GEN8_DE_PORT_IER));
753
754 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
755 I915_READ(GEN8_DE_MISC_IMR));
756 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
757 I915_READ(GEN8_DE_MISC_IIR));
758 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
759 I915_READ(GEN8_DE_MISC_IER));
760
761 seq_printf(m, "PCU interrupt mask:\t%08x\n",
762 I915_READ(GEN8_PCU_IMR));
763 seq_printf(m, "PCU interrupt identity:\t%08x\n",
764 I915_READ(GEN8_PCU_IIR));
765 seq_printf(m, "PCU interrupt enable:\t%08x\n",
766 I915_READ(GEN8_PCU_IER));
David Weinehall36cdd012016-08-22 13:59:31 +0300767 } else if (IS_VALLEYVIEW(dev_priv)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700768 seq_printf(m, "Display IER:\t%08x\n",
769 I915_READ(VLV_IER));
770 seq_printf(m, "Display IIR:\t%08x\n",
771 I915_READ(VLV_IIR));
772 seq_printf(m, "Display IIR_RW:\t%08x\n",
773 I915_READ(VLV_IIR_RW));
774 seq_printf(m, "Display IMR:\t%08x\n",
775 I915_READ(VLV_IMR));
Chris Wilson4f4631a2017-02-10 13:36:32 +0000776 for_each_pipe(dev_priv, pipe) {
777 enum intel_display_power_domain power_domain;
778
779 power_domain = POWER_DOMAIN_PIPE(pipe);
780 if (!intel_display_power_get_if_enabled(dev_priv,
781 power_domain)) {
782 seq_printf(m, "Pipe %c power disabled\n",
783 pipe_name(pipe));
784 continue;
785 }
786
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700787 seq_printf(m, "Pipe %c stat:\t%08x\n",
788 pipe_name(pipe),
789 I915_READ(PIPESTAT(pipe)));
Chris Wilson4f4631a2017-02-10 13:36:32 +0000790 intel_display_power_put(dev_priv, power_domain);
791 }
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700792
793 seq_printf(m, "Master IER:\t%08x\n",
794 I915_READ(VLV_MASTER_IER));
795
796 seq_printf(m, "Render IER:\t%08x\n",
797 I915_READ(GTIER));
798 seq_printf(m, "Render IIR:\t%08x\n",
799 I915_READ(GTIIR));
800 seq_printf(m, "Render IMR:\t%08x\n",
801 I915_READ(GTIMR));
802
803 seq_printf(m, "PM IER:\t\t%08x\n",
804 I915_READ(GEN6_PMIER));
805 seq_printf(m, "PM IIR:\t\t%08x\n",
806 I915_READ(GEN6_PMIIR));
807 seq_printf(m, "PM IMR:\t\t%08x\n",
808 I915_READ(GEN6_PMIMR));
809
810 seq_printf(m, "Port hotplug:\t%08x\n",
811 I915_READ(PORT_HOTPLUG_EN));
812 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
813 I915_READ(VLV_DPFLIPSTAT));
814 seq_printf(m, "DPINVGTT:\t%08x\n",
815 I915_READ(DPINVGTT));
816
David Weinehall36cdd012016-08-22 13:59:31 +0300817 } else if (!HAS_PCH_SPLIT(dev_priv)) {
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800818 seq_printf(m, "Interrupt enable: %08x\n",
819 I915_READ(IER));
820 seq_printf(m, "Interrupt identity: %08x\n",
821 I915_READ(IIR));
822 seq_printf(m, "Interrupt mask: %08x\n",
823 I915_READ(IMR));
Damien Lespiau055e3932014-08-18 13:49:10 +0100824 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800825 seq_printf(m, "Pipe %c stat: %08x\n",
826 pipe_name(pipe),
827 I915_READ(PIPESTAT(pipe)));
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800828 } else {
829 seq_printf(m, "North Display Interrupt enable: %08x\n",
830 I915_READ(DEIER));
831 seq_printf(m, "North Display Interrupt identity: %08x\n",
832 I915_READ(DEIIR));
833 seq_printf(m, "North Display Interrupt mask: %08x\n",
834 I915_READ(DEIMR));
835 seq_printf(m, "South Display Interrupt enable: %08x\n",
836 I915_READ(SDEIER));
837 seq_printf(m, "South Display Interrupt identity: %08x\n",
838 I915_READ(SDEIIR));
839 seq_printf(m, "South Display Interrupt mask: %08x\n",
840 I915_READ(SDEIMR));
841 seq_printf(m, "Graphics Interrupt enable: %08x\n",
842 I915_READ(GTIER));
843 seq_printf(m, "Graphics Interrupt identity: %08x\n",
844 I915_READ(GTIIR));
845 seq_printf(m, "Graphics Interrupt mask: %08x\n",
846 I915_READ(GTIMR));
847 }
Chris Wilsond5acadf2017-12-09 10:44:18 +0000848 if (INTEL_GEN(dev_priv) >= 6) {
849 for_each_engine(engine, dev_priv, id) {
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100850 seq_printf(m,
851 "Graphics Interrupt mask (%s): %08x\n",
Tvrtko Ursuline2f80392016-03-16 11:00:36 +0000852 engine->name, I915_READ_IMR(engine));
Chris Wilson9862e602011-01-04 22:22:17 +0000853 }
Chris Wilson9862e602011-01-04 22:22:17 +0000854 }
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200855 intel_runtime_pm_put(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100856
Ben Gamari20172632009-02-17 20:08:50 -0500857 return 0;
858}
859
Chris Wilsona6172a82009-02-11 14:26:38 +0000860static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
861{
David Weinehall36cdd012016-08-22 13:59:31 +0300862 struct drm_i915_private *dev_priv = node_to_i915(m->private);
863 struct drm_device *dev = &dev_priv->drm;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100864 int i, ret;
865
866 ret = mutex_lock_interruptible(&dev->struct_mutex);
867 if (ret)
868 return ret;
Chris Wilsona6172a82009-02-11 14:26:38 +0000869
Chris Wilsona6172a82009-02-11 14:26:38 +0000870 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
871 for (i = 0; i < dev_priv->num_fence_regs; i++) {
Chris Wilson49ef5292016-08-18 17:17:00 +0100872 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
Chris Wilsona6172a82009-02-11 14:26:38 +0000873
Chris Wilson6c085a72012-08-20 11:40:46 +0200874 seq_printf(m, "Fence %d, pin count = %d, object = ",
875 i, dev_priv->fence_regs[i].pin_count);
Chris Wilson49ef5292016-08-18 17:17:00 +0100876 if (!vma)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100877 seq_puts(m, "unused");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100878 else
Chris Wilson49ef5292016-08-18 17:17:00 +0100879 describe_obj(m, vma->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100880 seq_putc(m, '\n');
Chris Wilsona6172a82009-02-11 14:26:38 +0000881 }
882
Chris Wilson05394f32010-11-08 19:18:58 +0000883 mutex_unlock(&dev->struct_mutex);
Chris Wilsona6172a82009-02-11 14:26:38 +0000884 return 0;
885}
886
Chris Wilson98a2f412016-10-12 10:05:18 +0100887#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000888static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
889 size_t count, loff_t *pos)
890{
891 struct i915_gpu_state *error = file->private_data;
892 struct drm_i915_error_state_buf str;
893 ssize_t ret;
894 loff_t tmp;
895
896 if (!error)
897 return 0;
898
899 ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
900 if (ret)
901 return ret;
902
903 ret = i915_error_state_to_str(&str, error);
904 if (ret)
905 goto out;
906
907 tmp = 0;
908 ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
909 if (ret < 0)
910 goto out;
911
912 *pos = str.start + ret;
913out:
914 i915_error_state_buf_release(&str);
915 return ret;
916}
917
918static int gpu_state_release(struct inode *inode, struct file *file)
919{
920 i915_gpu_state_put(file->private_data);
921 return 0;
922}
923
924static int i915_gpu_info_open(struct inode *inode, struct file *file)
925{
Chris Wilson090e5fe2017-03-28 14:14:07 +0100926 struct drm_i915_private *i915 = inode->i_private;
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000927 struct i915_gpu_state *gpu;
928
Chris Wilson090e5fe2017-03-28 14:14:07 +0100929 intel_runtime_pm_get(i915);
930 gpu = i915_capture_gpu_state(i915);
931 intel_runtime_pm_put(i915);
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000932 if (!gpu)
933 return -ENOMEM;
934
935 file->private_data = gpu;
936 return 0;
937}
938
939static const struct file_operations i915_gpu_info_fops = {
940 .owner = THIS_MODULE,
941 .open = i915_gpu_info_open,
942 .read = gpu_state_read,
943 .llseek = default_llseek,
944 .release = gpu_state_release,
945};
Chris Wilson98a2f412016-10-12 10:05:18 +0100946
Daniel Vetterd5442302012-04-27 15:17:40 +0200947static ssize_t
948i915_error_state_write(struct file *filp,
949 const char __user *ubuf,
950 size_t cnt,
951 loff_t *ppos)
952{
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000953 struct i915_gpu_state *error = filp->private_data;
954
955 if (!error)
956 return 0;
Daniel Vetterd5442302012-04-27 15:17:40 +0200957
958 DRM_DEBUG_DRIVER("Resetting error state\n");
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000959 i915_reset_error_state(error->i915);
Daniel Vetterd5442302012-04-27 15:17:40 +0200960
961 return cnt;
962}
963
964static int i915_error_state_open(struct inode *inode, struct file *file)
965{
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000966 file->private_data = i915_first_error_state(inode->i_private);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300967 return 0;
Daniel Vetterd5442302012-04-27 15:17:40 +0200968}
969
Daniel Vetterd5442302012-04-27 15:17:40 +0200970static const struct file_operations i915_error_state_fops = {
971 .owner = THIS_MODULE,
972 .open = i915_error_state_open,
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000973 .read = gpu_state_read,
Daniel Vetterd5442302012-04-27 15:17:40 +0200974 .write = i915_error_state_write,
975 .llseek = default_llseek,
Chris Wilson5a4c6f12017-02-14 16:46:11 +0000976 .release = gpu_state_release,
Daniel Vetterd5442302012-04-27 15:17:40 +0200977};
Chris Wilson98a2f412016-10-12 10:05:18 +0100978#endif
979
Kees Cook647416f2013-03-10 14:10:06 -0700980static int
Kees Cook647416f2013-03-10 14:10:06 -0700981i915_next_seqno_set(void *data, u64 val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200982{
David Weinehall36cdd012016-08-22 13:59:31 +0300983 struct drm_i915_private *dev_priv = data;
984 struct drm_device *dev = &dev_priv->drm;
Mika Kuoppala40633212012-12-04 15:12:00 +0200985 int ret;
986
Mika Kuoppala40633212012-12-04 15:12:00 +0200987 ret = mutex_lock_interruptible(&dev->struct_mutex);
988 if (ret)
989 return ret;
990
Chris Wilson65c475c2018-01-02 15:12:31 +0000991 intel_runtime_pm_get(dev_priv);
Chris Wilson73cb9702016-10-28 13:58:46 +0100992 ret = i915_gem_set_global_seqno(dev, val);
Chris Wilson65c475c2018-01-02 15:12:31 +0000993 intel_runtime_pm_put(dev_priv);
994
Mika Kuoppala40633212012-12-04 15:12:00 +0200995 mutex_unlock(&dev->struct_mutex);
996
Kees Cook647416f2013-03-10 14:10:06 -0700997 return ret;
Mika Kuoppala40633212012-12-04 15:12:00 +0200998}
999
Kees Cook647416f2013-03-10 14:10:06 -07001000DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
Chris Wilson9b6586a2017-02-23 07:44:08 +00001001 NULL, i915_next_seqno_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03001002 "0x%llx\n");
Mika Kuoppala40633212012-12-04 15:12:00 +02001003
Deepak Sadb4bd12014-03-31 11:30:02 +05301004static int i915_frequency_info(struct seq_file *m, void *unused)
Jesse Barnesf97108d2010-01-29 11:27:07 -08001005{
David Weinehall36cdd012016-08-22 13:59:31 +03001006 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001007 struct intel_rps *rps = &dev_priv->gt_pm.rps;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001008 int ret = 0;
1009
1010 intel_runtime_pm_get(dev_priv);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001011
David Weinehall36cdd012016-08-22 13:59:31 +03001012 if (IS_GEN5(dev_priv)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001013 u16 rgvswctl = I915_READ16(MEMSWCTL);
1014 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1015
1016 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1017 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1018 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1019 MEMSTAT_VID_SHIFT);
1020 seq_printf(m, "Current P-state: %d\n",
1021 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
David Weinehall36cdd012016-08-22 13:59:31 +03001022 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Sagar Arun Kamble0d6fc922017-10-10 22:30:02 +01001023 u32 rpmodectl, freq_sts;
Wayne Boyer666a4532015-12-09 12:29:35 -08001024
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001025 mutex_lock(&dev_priv->pcu_lock);
Sagar Arun Kamble0d6fc922017-10-10 22:30:02 +01001026
1027 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1028 seq_printf(m, "Video Turbo Mode: %s\n",
1029 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1030 seq_printf(m, "HW control enabled: %s\n",
1031 yesno(rpmodectl & GEN6_RP_ENABLE));
1032 seq_printf(m, "SW control enabled: %s\n",
1033 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1034 GEN6_RP_MEDIA_SW_MODE));
1035
Wayne Boyer666a4532015-12-09 12:29:35 -08001036 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1037 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1038 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1039
1040 seq_printf(m, "actual GPU freq: %d MHz\n",
1041 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1042
1043 seq_printf(m, "current GPU freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001044 intel_gpu_freq(dev_priv, rps->cur_freq));
Wayne Boyer666a4532015-12-09 12:29:35 -08001045
1046 seq_printf(m, "max GPU freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001047 intel_gpu_freq(dev_priv, rps->max_freq));
Wayne Boyer666a4532015-12-09 12:29:35 -08001048
1049 seq_printf(m, "min GPU freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001050 intel_gpu_freq(dev_priv, rps->min_freq));
Wayne Boyer666a4532015-12-09 12:29:35 -08001051
1052 seq_printf(m, "idle GPU freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001053 intel_gpu_freq(dev_priv, rps->idle_freq));
Wayne Boyer666a4532015-12-09 12:29:35 -08001054
1055 seq_printf(m,
1056 "efficient (RPe) frequency: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001057 intel_gpu_freq(dev_priv, rps->efficient_freq));
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001058 mutex_unlock(&dev_priv->pcu_lock);
David Weinehall36cdd012016-08-22 13:59:31 +03001059 } else if (INTEL_GEN(dev_priv) >= 6) {
Bob Paauwe35040562015-06-25 14:54:07 -07001060 u32 rp_state_limits;
1061 u32 gt_perf_status;
1062 u32 rp_state_cap;
Chris Wilson0d8f9492014-03-27 09:06:14 +00001063 u32 rpmodectl, rpinclimit, rpdeclimit;
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001064 u32 rpstat, cagf, reqf;
Jesse Barnesccab5c82011-01-18 15:49:25 -08001065 u32 rpupei, rpcurup, rpprevup;
1066 u32 rpdownei, rpcurdown, rpprevdown;
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001067 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001068 int max_freq;
1069
Bob Paauwe35040562015-06-25 14:54:07 -07001070 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001071 if (IS_GEN9_LP(dev_priv)) {
Bob Paauwe35040562015-06-25 14:54:07 -07001072 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1073 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1074 } else {
1075 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1076 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1077 }
1078
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001079 /* RPSTAT1 is in the GT power well */
Mika Kuoppala59bad942015-01-16 11:34:40 +02001080 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001081
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001082 reqf = I915_READ(GEN6_RPNSWREQ);
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001083 if (INTEL_GEN(dev_priv) >= 9)
Akash Goel60260a52015-03-06 11:07:21 +05301084 reqf >>= 23;
1085 else {
1086 reqf &= ~GEN6_TURBO_DISABLE;
David Weinehall36cdd012016-08-22 13:59:31 +03001087 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Akash Goel60260a52015-03-06 11:07:21 +05301088 reqf >>= 24;
1089 else
1090 reqf >>= 25;
1091 }
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02001092 reqf = intel_gpu_freq(dev_priv, reqf);
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001093
Chris Wilson0d8f9492014-03-27 09:06:14 +00001094 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1095 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1096 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1097
Jesse Barnesccab5c82011-01-18 15:49:25 -08001098 rpstat = I915_READ(GEN6_RPSTAT1);
Akash Goeld6cda9c2016-04-23 00:05:46 +05301099 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1100 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1101 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1102 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1103 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1104 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
Tvrtko Ursulinc84b2702017-11-21 18:18:44 +00001105 cagf = intel_gpu_freq(dev_priv,
1106 intel_get_cagf(dev_priv, rpstat));
Jesse Barnesccab5c82011-01-18 15:49:25 -08001107
Mika Kuoppala59bad942015-01-16 11:34:40 +02001108 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01001109
David Weinehall36cdd012016-08-22 13:59:31 +03001110 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001111 pm_ier = I915_READ(GEN6_PMIER);
1112 pm_imr = I915_READ(GEN6_PMIMR);
1113 pm_isr = I915_READ(GEN6_PMISR);
1114 pm_iir = I915_READ(GEN6_PMIIR);
1115 pm_mask = I915_READ(GEN6_PMINTRMSK);
1116 } else {
1117 pm_ier = I915_READ(GEN8_GT_IER(2));
1118 pm_imr = I915_READ(GEN8_GT_IMR(2));
1119 pm_isr = I915_READ(GEN8_GT_ISR(2));
1120 pm_iir = I915_READ(GEN8_GT_IIR(2));
1121 pm_mask = I915_READ(GEN6_PMINTRMSK);
1122 }
Sagar Arun Kamble960e5462017-10-10 22:29:59 +01001123 seq_printf(m, "Video Turbo Mode: %s\n",
1124 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1125 seq_printf(m, "HW control enabled: %s\n",
1126 yesno(rpmodectl & GEN6_RP_ENABLE));
1127 seq_printf(m, "SW control enabled: %s\n",
1128 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1129 GEN6_RP_MEDIA_SW_MODE));
Chris Wilson0d8f9492014-03-27 09:06:14 +00001130 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
Paulo Zanoni9dd3c602014-08-01 18:14:48 -03001131 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
Sagar Arun Kamble5dd04552017-03-11 08:07:00 +05301132 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001133 rps->pm_intrmsk_mbz);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001134 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001135 seq_printf(m, "Render p-state ratio: %d\n",
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001136 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001137 seq_printf(m, "Render p-state VID: %d\n",
1138 gt_perf_status & 0xff);
1139 seq_printf(m, "Render p-state limit: %d\n",
1140 rp_state_limits & 0xff);
Chris Wilson0d8f9492014-03-27 09:06:14 +00001141 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1142 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1143 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1144 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001145 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
Ben Widawskyf82855d2013-01-29 12:00:15 -08001146 seq_printf(m, "CAGF: %dMHz\n", cagf);
Akash Goeld6cda9c2016-04-23 00:05:46 +05301147 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1148 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1149 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1150 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1151 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1152 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001153 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
Chris Wilsond86ed342015-04-27 13:41:19 +01001154
Akash Goeld6cda9c2016-04-23 00:05:46 +05301155 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1156 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1157 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1158 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1159 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1160 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001161 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001162
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001163 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
Bob Paauwe35040562015-06-25 14:54:07 -07001164 rp_state_cap >> 16) & 0xff;
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001165 max_freq *= (IS_GEN9_BC(dev_priv) ||
1166 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001167 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02001168 intel_gpu_freq(dev_priv, max_freq));
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001169
1170 max_freq = (rp_state_cap & 0xff00) >> 8;
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001171 max_freq *= (IS_GEN9_BC(dev_priv) ||
1172 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001173 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02001174 intel_gpu_freq(dev_priv, max_freq));
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001175
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02001176 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
Bob Paauwe35040562015-06-25 14:54:07 -07001177 rp_state_cap >> 0) & 0xff;
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001178 max_freq *= (IS_GEN9_BC(dev_priv) ||
1179 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001180 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
Ville Syrjälä7c59a9c12015-01-23 21:04:26 +02001181 intel_gpu_freq(dev_priv, max_freq));
Ben Widawsky31c77382013-04-05 14:29:22 -07001182 seq_printf(m, "Max overclocked frequency: %dMHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001183 intel_gpu_freq(dev_priv, rps->max_freq));
Chris Wilsonaed242f2015-03-18 09:48:21 +00001184
Chris Wilsond86ed342015-04-27 13:41:19 +01001185 seq_printf(m, "Current freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001186 intel_gpu_freq(dev_priv, rps->cur_freq));
Chris Wilsond86ed342015-04-27 13:41:19 +01001187 seq_printf(m, "Actual freq: %d MHz\n", cagf);
Chris Wilsonaed242f2015-03-18 09:48:21 +00001188 seq_printf(m, "Idle freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001189 intel_gpu_freq(dev_priv, rps->idle_freq));
Chris Wilsond86ed342015-04-27 13:41:19 +01001190 seq_printf(m, "Min freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001191 intel_gpu_freq(dev_priv, rps->min_freq));
Chris Wilson29ecd78d2016-07-13 09:10:35 +01001192 seq_printf(m, "Boost freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001193 intel_gpu_freq(dev_priv, rps->boost_freq));
Chris Wilsond86ed342015-04-27 13:41:19 +01001194 seq_printf(m, "Max freq: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001195 intel_gpu_freq(dev_priv, rps->max_freq));
Chris Wilsond86ed342015-04-27 13:41:19 +01001196 seq_printf(m,
1197 "efficient (RPe) frequency: %d MHz\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001198 intel_gpu_freq(dev_priv, rps->efficient_freq));
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001199 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001200 seq_puts(m, "no P-state info available\n");
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001201 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001202
Ville Syrjälä49cd97a2017-02-07 20:33:45 +02001203 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
Mika Kahola1170f282015-09-25 14:00:32 +03001204 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1205 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1206
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001207 intel_runtime_pm_put(dev_priv);
1208 return ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001209}
1210
Ben Widawskyd6369512016-09-20 16:54:32 +03001211static void i915_instdone_info(struct drm_i915_private *dev_priv,
1212 struct seq_file *m,
1213 struct intel_instdone *instdone)
1214{
Ben Widawskyf9e61372016-09-20 16:54:33 +03001215 int slice;
1216 int subslice;
1217
Ben Widawskyd6369512016-09-20 16:54:32 +03001218 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1219 instdone->instdone);
1220
1221 if (INTEL_GEN(dev_priv) <= 3)
1222 return;
1223
1224 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1225 instdone->slice_common);
1226
1227 if (INTEL_GEN(dev_priv) <= 6)
1228 return;
1229
Ben Widawskyf9e61372016-09-20 16:54:33 +03001230 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1231 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1232 slice, subslice, instdone->sampler[slice][subslice]);
1233
1234 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1235 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1236 slice, subslice, instdone->row[slice][subslice]);
Ben Widawskyd6369512016-09-20 16:54:32 +03001237}
1238
Chris Wilsonf6544492015-01-26 18:03:04 +02001239static int i915_hangcheck_info(struct seq_file *m, void *unused)
1240{
David Weinehall36cdd012016-08-22 13:59:31 +03001241 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00001242 struct intel_engine_cs *engine;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001243 u64 acthd[I915_NUM_ENGINES];
1244 u32 seqno[I915_NUM_ENGINES];
Ben Widawskyd6369512016-09-20 16:54:32 +03001245 struct intel_instdone instdone;
Dave Gordonc3232b12016-03-23 18:19:53 +00001246 enum intel_engine_id id;
Chris Wilsonf6544492015-01-26 18:03:04 +02001247
Chris Wilson8af29b02016-09-09 14:11:47 +01001248 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
Chris Wilson8c185ec2017-03-16 17:13:02 +00001249 seq_puts(m, "Wedged\n");
1250 if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1251 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1252 if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1253 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
Chris Wilson8af29b02016-09-09 14:11:47 +01001254 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
Chris Wilson8c185ec2017-03-16 17:13:02 +00001255 seq_puts(m, "Waiter holding struct mutex\n");
Chris Wilson8af29b02016-09-09 14:11:47 +01001256 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
Chris Wilson8c185ec2017-03-16 17:13:02 +00001257 seq_puts(m, "struct_mutex blocked for reset\n");
Chris Wilson8af29b02016-09-09 14:11:47 +01001258
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001259 if (!i915_modparams.enable_hangcheck) {
Chris Wilson8c185ec2017-03-16 17:13:02 +00001260 seq_puts(m, "Hangcheck disabled\n");
Chris Wilsonf6544492015-01-26 18:03:04 +02001261 return 0;
1262 }
1263
Mika Kuoppalaebbc7542015-02-05 18:41:48 +02001264 intel_runtime_pm_get(dev_priv);
1265
Akash Goel3b3f1652016-10-13 22:44:48 +05301266 for_each_engine(engine, dev_priv, id) {
Chris Wilson7e37f882016-08-02 22:50:21 +01001267 acthd[id] = intel_engine_get_active_head(engine);
Chris Wilson1b7744e2016-07-01 17:23:17 +01001268 seqno[id] = intel_engine_get_seqno(engine);
Mika Kuoppalaebbc7542015-02-05 18:41:48 +02001269 }
1270
Akash Goel3b3f1652016-10-13 22:44:48 +05301271 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001272
Mika Kuoppalaebbc7542015-02-05 18:41:48 +02001273 intel_runtime_pm_put(dev_priv);
1274
Chris Wilson8352aea2017-03-03 09:00:56 +00001275 if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1276 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
Chris Wilsonf6544492015-01-26 18:03:04 +02001277 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1278 jiffies));
Chris Wilson8352aea2017-03-03 09:00:56 +00001279 else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1280 seq_puts(m, "Hangcheck active, work pending\n");
1281 else
1282 seq_puts(m, "Hangcheck inactive\n");
Chris Wilsonf6544492015-01-26 18:03:04 +02001283
Chris Wilsonf73b5672017-03-02 15:03:56 +00001284 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1285
Akash Goel3b3f1652016-10-13 22:44:48 +05301286 for_each_engine(engine, dev_priv, id) {
Chris Wilson33f53712016-10-04 21:11:32 +01001287 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1288 struct rb_node *rb;
1289
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00001290 seq_printf(m, "%s:\n", engine->name);
Chris Wilsonf73b5672017-03-02 15:03:56 +00001291 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
Chris Wilsoncb399ea2016-11-01 10:03:16 +00001292 engine->hangcheck.seqno, seqno[id],
Chris Wilsonf73b5672017-03-02 15:03:56 +00001293 intel_engine_last_submit(engine),
1294 engine->timeline->inflight_seqnos);
Mika Kuoppala3fe3b032016-11-18 15:09:04 +02001295 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
Chris Wilson83348ba2016-08-09 17:47:51 +01001296 yesno(intel_engine_has_waiter(engine)),
1297 yesno(test_bit(engine->id,
Mika Kuoppala3fe3b032016-11-18 15:09:04 +02001298 &dev_priv->gpu_error.missed_irq_rings)),
1299 yesno(engine->hangcheck.stalled));
1300
Chris Wilson61d3dc72017-03-03 19:08:24 +00001301 spin_lock_irq(&b->rb_lock);
Chris Wilson33f53712016-10-04 21:11:32 +01001302 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
Geliang Tangf802cf72016-12-19 22:43:49 +08001303 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
Chris Wilson33f53712016-10-04 21:11:32 +01001304
1305 seq_printf(m, "\t%s [%d] waiting for %x\n",
1306 w->tsk->comm, w->tsk->pid, w->seqno);
1307 }
Chris Wilson61d3dc72017-03-03 19:08:24 +00001308 spin_unlock_irq(&b->rb_lock);
Chris Wilson33f53712016-10-04 21:11:32 +01001309
Chris Wilsonf6544492015-01-26 18:03:04 +02001310 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00001311 (long long)engine->hangcheck.acthd,
Dave Gordonc3232b12016-03-23 18:19:53 +00001312 (long long)acthd[id]);
Mika Kuoppala3fe3b032016-11-18 15:09:04 +02001313 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1314 hangcheck_action_to_str(engine->hangcheck.action),
1315 engine->hangcheck.action,
1316 jiffies_to_msecs(jiffies -
1317 engine->hangcheck.action_timestamp));
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001318
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00001319 if (engine->id == RCS) {
Ben Widawskyd6369512016-09-20 16:54:32 +03001320 seq_puts(m, "\tinstdone read =\n");
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001321
Ben Widawskyd6369512016-09-20 16:54:32 +03001322 i915_instdone_info(dev_priv, m, &instdone);
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001323
Ben Widawskyd6369512016-09-20 16:54:32 +03001324 seq_puts(m, "\tinstdone accu =\n");
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001325
Ben Widawskyd6369512016-09-20 16:54:32 +03001326 i915_instdone_info(dev_priv, m,
1327 &engine->hangcheck.instdone);
Mika Kuoppala61642ff2015-12-01 17:56:12 +02001328 }
Chris Wilsonf6544492015-01-26 18:03:04 +02001329 }
1330
1331 return 0;
1332}
1333
Michel Thierry061d06a2017-06-20 10:57:49 +01001334static int i915_reset_info(struct seq_file *m, void *unused)
1335{
1336 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1337 struct i915_gpu_error *error = &dev_priv->gpu_error;
1338 struct intel_engine_cs *engine;
1339 enum intel_engine_id id;
1340
1341 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1342
1343 for_each_engine(engine, dev_priv, id) {
1344 seq_printf(m, "%s = %u\n", engine->name,
1345 i915_reset_engine_count(error, engine));
1346 }
1347
1348 return 0;
1349}
1350
Ben Widawsky4d855292011-12-12 19:34:16 -08001351static int ironlake_drpc_info(struct seq_file *m)
Jesse Barnesf97108d2010-01-29 11:27:07 -08001352{
David Weinehall36cdd012016-08-22 13:59:31 +03001353 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001354 u32 rgvmodectl, rstdbyctl;
1355 u16 crstandvid;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001356
Ben Widawsky616fdb52011-10-05 11:44:54 -07001357 rgvmodectl = I915_READ(MEMMODECTL);
1358 rstdbyctl = I915_READ(RSTDBYCTL);
1359 crstandvid = I915_READ16(CRSTANDVID);
1360
Jani Nikula742f4912015-09-03 11:16:09 +03001361 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
Jesse Barnesf97108d2010-01-29 11:27:07 -08001362 seq_printf(m, "Boost freq: %d\n",
1363 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1364 MEMMODE_BOOST_FREQ_SHIFT);
1365 seq_printf(m, "HW control enabled: %s\n",
Jani Nikula742f4912015-09-03 11:16:09 +03001366 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
Jesse Barnesf97108d2010-01-29 11:27:07 -08001367 seq_printf(m, "SW control enabled: %s\n",
Jani Nikula742f4912015-09-03 11:16:09 +03001368 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
Jesse Barnesf97108d2010-01-29 11:27:07 -08001369 seq_printf(m, "Gated voltage change: %s\n",
Jani Nikula742f4912015-09-03 11:16:09 +03001370 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
Jesse Barnesf97108d2010-01-29 11:27:07 -08001371 seq_printf(m, "Starting frequency: P%d\n",
1372 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001373 seq_printf(m, "Max P-state: P%d\n",
Jesse Barnesf97108d2010-01-29 11:27:07 -08001374 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001375 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1376 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1377 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1378 seq_printf(m, "Render standby enabled: %s\n",
Jani Nikula742f4912015-09-03 11:16:09 +03001379 yesno(!(rstdbyctl & RCX_SW_EXIT)));
Damien Lespiau267f0c92013-06-24 22:59:48 +01001380 seq_puts(m, "Current RS state: ");
Jesse Barnes88271da2011-01-05 12:01:24 -08001381 switch (rstdbyctl & RSX_STATUS_MASK) {
1382 case RSX_STATUS_ON:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001383 seq_puts(m, "on\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001384 break;
1385 case RSX_STATUS_RC1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001386 seq_puts(m, "RC1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001387 break;
1388 case RSX_STATUS_RC1E:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001389 seq_puts(m, "RC1E\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001390 break;
1391 case RSX_STATUS_RS1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001392 seq_puts(m, "RS1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001393 break;
1394 case RSX_STATUS_RS2:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001395 seq_puts(m, "RS2 (RC6)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001396 break;
1397 case RSX_STATUS_RS3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001398 seq_puts(m, "RC3 (RC6+)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001399 break;
1400 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001401 seq_puts(m, "unknown\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001402 break;
1403 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001404
1405 return 0;
1406}
1407
Mika Kuoppalaf65367b2015-01-16 11:34:42 +02001408static int i915_forcewake_domains(struct seq_file *m, void *data)
Chris Wilsonb2cff0d2015-01-16 11:34:37 +02001409{
Chris Wilson233ebf52017-03-23 10:19:44 +00001410 struct drm_i915_private *i915 = node_to_i915(m->private);
Chris Wilsonb2cff0d2015-01-16 11:34:37 +02001411 struct intel_uncore_forcewake_domain *fw_domain;
Chris Wilsond2dc94b2017-03-23 10:19:41 +00001412 unsigned int tmp;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +02001413
Chris Wilsond7a133d2017-09-07 14:44:41 +01001414 seq_printf(m, "user.bypass_count = %u\n",
1415 i915->uncore.user_forcewake.count);
1416
Chris Wilson233ebf52017-03-23 10:19:44 +00001417 for_each_fw_domain(fw_domain, i915, tmp)
Chris Wilsonb2cff0d2015-01-16 11:34:37 +02001418 seq_printf(m, "%s.wake_count = %u\n",
Tvrtko Ursulin33c582c2016-04-07 17:04:33 +01001419 intel_uncore_forcewake_domain_to_str(fw_domain->id),
Chris Wilson233ebf52017-03-23 10:19:44 +00001420 READ_ONCE(fw_domain->wake_count));
Chris Wilsonb2cff0d2015-01-16 11:34:37 +02001421
1422 return 0;
1423}
1424
Mika Kuoppala13628772017-03-15 17:43:02 +02001425static void print_rc6_res(struct seq_file *m,
1426 const char *title,
1427 const i915_reg_t reg)
1428{
1429 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1430
1431 seq_printf(m, "%s %u (%llu us)\n",
1432 title, I915_READ(reg),
1433 intel_rc6_residency_us(dev_priv, reg));
1434}
1435
Deepak S669ab5a2014-01-10 15:18:26 +05301436static int vlv_drpc_info(struct seq_file *m)
1437{
David Weinehall36cdd012016-08-22 13:59:31 +03001438 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Sagar Arun Kamble0d6fc922017-10-10 22:30:02 +01001439 u32 rcctl1, pw_status;
Deepak S669ab5a2014-01-10 15:18:26 +05301440
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001441 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
Deepak S669ab5a2014-01-10 15:18:26 +05301442 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1443
Deepak S669ab5a2014-01-10 15:18:26 +05301444 seq_printf(m, "RC6 Enabled: %s\n",
1445 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1446 GEN6_RC_CTL_EI_MODE(1))));
1447 seq_printf(m, "Render Power Well: %s\n",
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001448 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
Deepak S669ab5a2014-01-10 15:18:26 +05301449 seq_printf(m, "Media Power Well: %s\n",
Ville Syrjälä6b312cd2014-11-19 20:07:42 +02001450 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
Deepak S669ab5a2014-01-10 15:18:26 +05301451
Mika Kuoppala13628772017-03-15 17:43:02 +02001452 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1453 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
Imre Deak9cc19be2014-04-14 20:24:24 +03001454
Mika Kuoppalaf65367b2015-01-16 11:34:42 +02001455 return i915_forcewake_domains(m, NULL);
Deepak S669ab5a2014-01-10 15:18:26 +05301456}
1457
Ben Widawsky4d855292011-12-12 19:34:16 -08001458static int gen6_drpc_info(struct seq_file *m)
1459{
David Weinehall36cdd012016-08-22 13:59:31 +03001460 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Sagar Arun Kamble960e5462017-10-10 22:29:59 +01001461 u32 gt_core_status, rcctl1, rc6vids = 0;
Akash Goelf2dd7572016-06-27 20:10:01 +05301462 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
Daniel Vetter93b525d2012-01-25 13:52:43 +01001463 unsigned forcewake_count;
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001464 int count = 0;
Ben Widawsky4d855292011-12-12 19:34:16 -08001465
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001466 forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
Daniel Vetter93b525d2012-01-25 13:52:43 +01001467 if (forcewake_count) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001468 seq_puts(m, "RC information inaccurate because somebody "
1469 "holds a forcewake reference \n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001470 } else {
1471 /* NB: we cannot use forcewake, else we read the wrong values */
1472 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1473 udelay(10);
1474 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1475 }
1476
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03001477 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
Chris Wilsoned71f1b2013-07-19 20:36:56 +01001478 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
Ben Widawsky4d855292011-12-12 19:34:16 -08001479
Ben Widawsky4d855292011-12-12 19:34:16 -08001480 rcctl1 = I915_READ(GEN6_RC_CONTROL);
David Weinehall36cdd012016-08-22 13:59:31 +03001481 if (INTEL_GEN(dev_priv) >= 9) {
Akash Goelf2dd7572016-06-27 20:10:01 +05301482 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1483 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1484 }
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001485
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001486 mutex_lock(&dev_priv->pcu_lock);
Ben Widawsky44cbd332012-11-06 14:36:36 +00001487 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001488 mutex_unlock(&dev_priv->pcu_lock);
Ben Widawsky4d855292011-12-12 19:34:16 -08001489
Eric Anholtfff24e22012-01-23 16:14:05 -08001490 seq_printf(m, "RC1e Enabled: %s\n",
Ben Widawsky4d855292011-12-12 19:34:16 -08001491 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1492 seq_printf(m, "RC6 Enabled: %s\n",
1493 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
David Weinehall36cdd012016-08-22 13:59:31 +03001494 if (INTEL_GEN(dev_priv) >= 9) {
Akash Goelf2dd7572016-06-27 20:10:01 +05301495 seq_printf(m, "Render Well Gating Enabled: %s\n",
1496 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1497 seq_printf(m, "Media Well Gating Enabled: %s\n",
1498 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1499 }
Ben Widawsky4d855292011-12-12 19:34:16 -08001500 seq_printf(m, "Deep RC6 Enabled: %s\n",
1501 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1502 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1503 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
Damien Lespiau267f0c92013-06-24 22:59:48 +01001504 seq_puts(m, "Current RC state: ");
Ben Widawsky4d855292011-12-12 19:34:16 -08001505 switch (gt_core_status & GEN6_RCn_MASK) {
1506 case GEN6_RC0:
1507 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
Damien Lespiau267f0c92013-06-24 22:59:48 +01001508 seq_puts(m, "Core Power Down\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001509 else
Damien Lespiau267f0c92013-06-24 22:59:48 +01001510 seq_puts(m, "on\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001511 break;
1512 case GEN6_RC3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001513 seq_puts(m, "RC3\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001514 break;
1515 case GEN6_RC6:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001516 seq_puts(m, "RC6\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001517 break;
1518 case GEN6_RC7:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001519 seq_puts(m, "RC7\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001520 break;
1521 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001522 seq_puts(m, "Unknown\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001523 break;
1524 }
1525
1526 seq_printf(m, "Core Power Down: %s\n",
1527 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
David Weinehall36cdd012016-08-22 13:59:31 +03001528 if (INTEL_GEN(dev_priv) >= 9) {
Akash Goelf2dd7572016-06-27 20:10:01 +05301529 seq_printf(m, "Render Power Well: %s\n",
1530 (gen9_powergate_status &
1531 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1532 seq_printf(m, "Media Power Well: %s\n",
1533 (gen9_powergate_status &
1534 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1535 }
Ben Widawskycce66a22012-03-27 18:59:38 -07001536
1537 /* Not exactly sure what this is */
Mika Kuoppala13628772017-03-15 17:43:02 +02001538 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1539 GEN6_GT_GFX_RC6_LOCKED);
1540 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1541 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1542 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
Ben Widawskycce66a22012-03-27 18:59:38 -07001543
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001544 seq_printf(m, "RC6 voltage: %dmV\n",
1545 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1546 seq_printf(m, "RC6+ voltage: %dmV\n",
1547 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1548 seq_printf(m, "RC6++ voltage: %dmV\n",
1549 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
Akash Goelf2dd7572016-06-27 20:10:01 +05301550 return i915_forcewake_domains(m, NULL);
Ben Widawsky4d855292011-12-12 19:34:16 -08001551}
1552
1553static int i915_drpc_info(struct seq_file *m, void *unused)
1554{
David Weinehall36cdd012016-08-22 13:59:31 +03001555 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001556 int err;
1557
1558 intel_runtime_pm_get(dev_priv);
Ben Widawsky4d855292011-12-12 19:34:16 -08001559
David Weinehall36cdd012016-08-22 13:59:31 +03001560 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001561 err = vlv_drpc_info(m);
David Weinehall36cdd012016-08-22 13:59:31 +03001562 else if (INTEL_GEN(dev_priv) >= 6)
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001563 err = gen6_drpc_info(m);
Ben Widawsky4d855292011-12-12 19:34:16 -08001564 else
Chris Wilsoncf632bd2017-03-13 09:56:17 +00001565 err = ironlake_drpc_info(m);
1566
1567 intel_runtime_pm_put(dev_priv);
1568
1569 return err;
Ben Widawsky4d855292011-12-12 19:34:16 -08001570}
1571
Daniel Vetter9a851782015-06-18 10:30:22 +02001572static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1573{
David Weinehall36cdd012016-08-22 13:59:31 +03001574 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Daniel Vetter9a851782015-06-18 10:30:22 +02001575
1576 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1577 dev_priv->fb_tracking.busy_bits);
1578
1579 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1580 dev_priv->fb_tracking.flip_bits);
1581
1582 return 0;
1583}
1584
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001585static int i915_fbc_status(struct seq_file *m, void *unused)
1586{
David Weinehall36cdd012016-08-22 13:59:31 +03001587 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Chris Wilson31388722017-12-20 20:58:48 +00001588 struct intel_fbc *fbc = &dev_priv->fbc;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001589
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00001590 if (!HAS_FBC(dev_priv))
1591 return -ENODEV;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001592
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001593 intel_runtime_pm_get(dev_priv);
Chris Wilson31388722017-12-20 20:58:48 +00001594 mutex_lock(&fbc->lock);
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001595
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03001596 if (intel_fbc_is_active(dev_priv))
Damien Lespiau267f0c92013-06-24 22:59:48 +01001597 seq_puts(m, "FBC enabled\n");
Paulo Zanoni2e8144a2015-06-12 14:36:20 -03001598 else
Chris Wilson31388722017-12-20 20:58:48 +00001599 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1600
1601 if (fbc->work.scheduled)
1602 seq_printf(m, "FBC worker scheduled on vblank %u, now %llu\n",
1603 fbc->work.scheduled_vblank,
1604 drm_crtc_vblank_count(&fbc->crtc->base));
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001605
Ville Syrjälä3fd5d1e2017-06-06 15:43:18 +03001606 if (intel_fbc_is_active(dev_priv)) {
1607 u32 mask;
1608
1609 if (INTEL_GEN(dev_priv) >= 8)
1610 mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1611 else if (INTEL_GEN(dev_priv) >= 7)
1612 mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1613 else if (INTEL_GEN(dev_priv) >= 5)
1614 mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1615 else if (IS_G4X(dev_priv))
1616 mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1617 else
1618 mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1619 FBC_STAT_COMPRESSED);
1620
1621 seq_printf(m, "Compressing: %s\n", yesno(mask));
Paulo Zanoni0fc6a9d2016-10-21 13:55:46 -02001622 }
Paulo Zanoni31b9df12015-06-12 14:36:18 -03001623
Chris Wilson31388722017-12-20 20:58:48 +00001624 mutex_unlock(&fbc->lock);
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001625 intel_runtime_pm_put(dev_priv);
1626
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001627 return 0;
1628}
1629
Ville Syrjälä4127dc42017-06-06 15:44:12 +03001630static int i915_fbc_false_color_get(void *data, u64 *val)
Rodrigo Vivida46f932014-08-01 02:04:45 -07001631{
David Weinehall36cdd012016-08-22 13:59:31 +03001632 struct drm_i915_private *dev_priv = data;
Rodrigo Vivida46f932014-08-01 02:04:45 -07001633
David Weinehall36cdd012016-08-22 13:59:31 +03001634 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
Rodrigo Vivida46f932014-08-01 02:04:45 -07001635 return -ENODEV;
1636
Rodrigo Vivida46f932014-08-01 02:04:45 -07001637 *val = dev_priv->fbc.false_color;
Rodrigo Vivida46f932014-08-01 02:04:45 -07001638
1639 return 0;
1640}
1641
Ville Syrjälä4127dc42017-06-06 15:44:12 +03001642static int i915_fbc_false_color_set(void *data, u64 val)
Rodrigo Vivida46f932014-08-01 02:04:45 -07001643{
David Weinehall36cdd012016-08-22 13:59:31 +03001644 struct drm_i915_private *dev_priv = data;
Rodrigo Vivida46f932014-08-01 02:04:45 -07001645 u32 reg;
1646
David Weinehall36cdd012016-08-22 13:59:31 +03001647 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
Rodrigo Vivida46f932014-08-01 02:04:45 -07001648 return -ENODEV;
1649
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001650 mutex_lock(&dev_priv->fbc.lock);
Rodrigo Vivida46f932014-08-01 02:04:45 -07001651
1652 reg = I915_READ(ILK_DPFC_CONTROL);
1653 dev_priv->fbc.false_color = val;
1654
1655 I915_WRITE(ILK_DPFC_CONTROL, val ?
1656 (reg | FBC_CTL_FALSE_COLOR) :
1657 (reg & ~FBC_CTL_FALSE_COLOR));
1658
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001659 mutex_unlock(&dev_priv->fbc.lock);
Rodrigo Vivida46f932014-08-01 02:04:45 -07001660 return 0;
1661}
1662
Ville Syrjälä4127dc42017-06-06 15:44:12 +03001663DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1664 i915_fbc_false_color_get, i915_fbc_false_color_set,
Rodrigo Vivida46f932014-08-01 02:04:45 -07001665 "%llu\n");
1666
Paulo Zanoni92d44622013-05-31 16:33:24 -03001667static int i915_ips_status(struct seq_file *m, void *unused)
1668{
David Weinehall36cdd012016-08-22 13:59:31 +03001669 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Paulo Zanoni92d44622013-05-31 16:33:24 -03001670
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00001671 if (!HAS_IPS(dev_priv))
1672 return -ENODEV;
Paulo Zanoni92d44622013-05-31 16:33:24 -03001673
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001674 intel_runtime_pm_get(dev_priv);
1675
Rodrigo Vivi0eaa53f2014-06-30 04:45:01 -07001676 seq_printf(m, "Enabled by kernel parameter: %s\n",
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00001677 yesno(i915_modparams.enable_ips));
Rodrigo Vivi0eaa53f2014-06-30 04:45:01 -07001678
David Weinehall36cdd012016-08-22 13:59:31 +03001679 if (INTEL_GEN(dev_priv) >= 8) {
Rodrigo Vivi0eaa53f2014-06-30 04:45:01 -07001680 seq_puts(m, "Currently: unknown\n");
1681 } else {
1682 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1683 seq_puts(m, "Currently: enabled\n");
1684 else
1685 seq_puts(m, "Currently: disabled\n");
1686 }
Paulo Zanoni92d44622013-05-31 16:33:24 -03001687
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001688 intel_runtime_pm_put(dev_priv);
1689
Paulo Zanoni92d44622013-05-31 16:33:24 -03001690 return 0;
1691}
1692
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001693static int i915_sr_status(struct seq_file *m, void *unused)
1694{
David Weinehall36cdd012016-08-22 13:59:31 +03001695 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001696 bool sr_enabled = false;
1697
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001698 intel_runtime_pm_get(dev_priv);
Chris Wilson9c870d02016-10-24 13:42:15 +01001699 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001700
Chris Wilson7342a722017-03-09 14:20:49 +00001701 if (INTEL_GEN(dev_priv) >= 9)
1702 /* no global SR status; inspect per-plane WM */;
1703 else if (HAS_PCH_SPLIT(dev_priv))
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001704 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
Jani Nikulac0f86832016-12-07 12:13:04 +02001705 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
David Weinehall36cdd012016-08-22 13:59:31 +03001706 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001707 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
David Weinehall36cdd012016-08-22 13:59:31 +03001708 else if (IS_I915GM(dev_priv))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001709 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
David Weinehall36cdd012016-08-22 13:59:31 +03001710 else if (IS_PINEVIEW(dev_priv))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001711 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
David Weinehall36cdd012016-08-22 13:59:31 +03001712 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ander Conselvan de Oliveira77b64552015-06-02 14:17:47 +03001713 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001714
Chris Wilson9c870d02016-10-24 13:42:15 +01001715 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001716 intel_runtime_pm_put(dev_priv);
1717
Tvrtko Ursulin08c4d7f2016-11-17 12:30:14 +00001718 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001719
1720 return 0;
1721}
1722
Jesse Barnes7648fa92010-05-20 14:28:11 -07001723static int i915_emon_status(struct seq_file *m, void *unused)
1724{
David Weinehall36cdd012016-08-22 13:59:31 +03001725 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1726 struct drm_device *dev = &dev_priv->drm;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001727 unsigned long temp, chipset, gfx;
Chris Wilsonde227ef2010-07-03 07:58:38 +01001728 int ret;
1729
David Weinehall36cdd012016-08-22 13:59:31 +03001730 if (!IS_GEN5(dev_priv))
Chris Wilson582be6b2012-04-30 19:35:02 +01001731 return -ENODEV;
1732
Chris Wilsonde227ef2010-07-03 07:58:38 +01001733 ret = mutex_lock_interruptible(&dev->struct_mutex);
1734 if (ret)
1735 return ret;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001736
1737 temp = i915_mch_val(dev_priv);
1738 chipset = i915_chipset_val(dev_priv);
1739 gfx = i915_gfx_val(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +01001740 mutex_unlock(&dev->struct_mutex);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001741
1742 seq_printf(m, "GMCH temp: %ld\n", temp);
1743 seq_printf(m, "Chipset power: %ld\n", chipset);
1744 seq_printf(m, "GFX power: %ld\n", gfx);
1745 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1746
1747 return 0;
1748}
1749
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001750static int i915_ring_freq_table(struct seq_file *m, void *unused)
1751{
David Weinehall36cdd012016-08-22 13:59:31 +03001752 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001753 struct intel_rps *rps = &dev_priv->gt_pm.rps;
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001754 int ret = 0;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001755 int gpu_freq, ia_freq;
Akash Goelf936ec32015-06-29 14:50:22 +05301756 unsigned int max_gpu_freq, min_gpu_freq;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001757
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00001758 if (!HAS_LLC(dev_priv))
1759 return -ENODEV;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001760
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001761 intel_runtime_pm_get(dev_priv);
1762
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001763 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001764 if (ret)
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001765 goto out;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001766
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001767 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
Akash Goelf936ec32015-06-29 14:50:22 +05301768 /* Convert GT frequency to 50 HZ units */
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001769 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1770 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
Akash Goelf936ec32015-06-29 14:50:22 +05301771 } else {
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01001772 min_gpu_freq = rps->min_freq_softlimit;
1773 max_gpu_freq = rps->max_freq_softlimit;
Akash Goelf936ec32015-06-29 14:50:22 +05301774 }
1775
Damien Lespiau267f0c92013-06-24 22:59:48 +01001776 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001777
Akash Goelf936ec32015-06-29 14:50:22 +05301778 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
Ben Widawsky42c05262012-09-26 10:34:00 -07001779 ia_freq = gpu_freq;
1780 sandybridge_pcode_read(dev_priv,
1781 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1782 &ia_freq);
Chris Wilson3ebecd02013-04-12 19:10:13 +01001783 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
Akash Goelf936ec32015-06-29 14:50:22 +05301784 intel_gpu_freq(dev_priv, (gpu_freq *
Rodrigo Vivi35ceabf2017-07-06 13:41:13 -07001785 (IS_GEN9_BC(dev_priv) ||
1786 IS_CANNONLAKE(dev_priv) ?
Rodrigo Vivib976dc52017-01-23 10:32:37 -08001787 GEN9_FREQ_SCALER : 1))),
Chris Wilson3ebecd02013-04-12 19:10:13 +01001788 ((ia_freq >> 0) & 0xff) * 100,
1789 ((ia_freq >> 8) & 0xff) * 100);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001790 }
1791
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01001792 mutex_unlock(&dev_priv->pcu_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001793
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001794out:
1795 intel_runtime_pm_put(dev_priv);
1796 return ret;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001797}
1798
Chris Wilson44834a62010-08-19 16:09:23 +01001799static int i915_opregion(struct seq_file *m, void *unused)
1800{
David Weinehall36cdd012016-08-22 13:59:31 +03001801 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1802 struct drm_device *dev = &dev_priv->drm;
Chris Wilson44834a62010-08-19 16:09:23 +01001803 struct intel_opregion *opregion = &dev_priv->opregion;
1804 int ret;
1805
1806 ret = mutex_lock_interruptible(&dev->struct_mutex);
1807 if (ret)
Daniel Vetter0d38f002012-04-21 22:49:10 +02001808 goto out;
Chris Wilson44834a62010-08-19 16:09:23 +01001809
Jani Nikula2455a8e2015-12-14 12:50:53 +02001810 if (opregion->header)
1811 seq_write(m, opregion->header, OPREGION_SIZE);
Chris Wilson44834a62010-08-19 16:09:23 +01001812
1813 mutex_unlock(&dev->struct_mutex);
1814
Daniel Vetter0d38f002012-04-21 22:49:10 +02001815out:
Chris Wilson44834a62010-08-19 16:09:23 +01001816 return 0;
1817}
1818
Jani Nikulaada8f952015-12-15 13:17:12 +02001819static int i915_vbt(struct seq_file *m, void *unused)
1820{
David Weinehall36cdd012016-08-22 13:59:31 +03001821 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
Jani Nikulaada8f952015-12-15 13:17:12 +02001822
1823 if (opregion->vbt)
1824 seq_write(m, opregion->vbt, opregion->vbt_size);
1825
1826 return 0;
1827}
1828
Chris Wilson37811fc2010-08-25 22:45:57 +01001829static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1830{
David Weinehall36cdd012016-08-22 13:59:31 +03001831 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1832 struct drm_device *dev = &dev_priv->drm;
Namrta Salonieb13b8402015-11-27 13:43:11 +05301833 struct intel_framebuffer *fbdev_fb = NULL;
Daniel Vetter3a58ee12015-07-10 19:02:51 +02001834 struct drm_framebuffer *drm_fb;
Chris Wilson188c1ab2016-04-03 14:14:20 +01001835 int ret;
1836
1837 ret = mutex_lock_interruptible(&dev->struct_mutex);
1838 if (ret)
1839 return ret;
Chris Wilson37811fc2010-08-25 22:45:57 +01001840
Daniel Vetter06957262015-08-10 13:34:08 +02001841#ifdef CONFIG_DRM_FBDEV_EMULATION
Daniel Vetter346fb4e2017-07-06 15:00:20 +02001842 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
David Weinehall36cdd012016-08-22 13:59:31 +03001843 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
Chris Wilson37811fc2010-08-25 22:45:57 +01001844
Chris Wilson25bcce92016-07-02 15:36:00 +01001845 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1846 fbdev_fb->base.width,
1847 fbdev_fb->base.height,
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001848 fbdev_fb->base.format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001849 fbdev_fb->base.format->cpp[0] * 8,
Ville Syrjäläbae781b2016-11-16 13:33:16 +02001850 fbdev_fb->base.modifier,
Chris Wilson25bcce92016-07-02 15:36:00 +01001851 drm_framebuffer_read_refcount(&fbdev_fb->base));
1852 describe_obj(m, fbdev_fb->obj);
1853 seq_putc(m, '\n');
1854 }
Daniel Vetter4520f532013-10-09 09:18:51 +02001855#endif
Chris Wilson37811fc2010-08-25 22:45:57 +01001856
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001857 mutex_lock(&dev->mode_config.fb_lock);
Daniel Vetter3a58ee12015-07-10 19:02:51 +02001858 drm_for_each_fb(drm_fb, dev) {
Namrta Salonieb13b8402015-11-27 13:43:11 +05301859 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1860 if (fb == fbdev_fb)
Chris Wilson37811fc2010-08-25 22:45:57 +01001861 continue;
1862
Tvrtko Ursulinc1ca506d2015-02-10 17:16:07 +00001863 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001864 fb->base.width,
1865 fb->base.height,
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001866 fb->base.format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001867 fb->base.format->cpp[0] * 8,
Ville Syrjäläbae781b2016-11-16 13:33:16 +02001868 fb->base.modifier,
Dave Airlie747a5982016-04-15 15:10:35 +10001869 drm_framebuffer_read_refcount(&fb->base));
Chris Wilson05394f32010-11-08 19:18:58 +00001870 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001871 seq_putc(m, '\n');
Chris Wilson37811fc2010-08-25 22:45:57 +01001872 }
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001873 mutex_unlock(&dev->mode_config.fb_lock);
Chris Wilson188c1ab2016-04-03 14:14:20 +01001874 mutex_unlock(&dev->struct_mutex);
Chris Wilson37811fc2010-08-25 22:45:57 +01001875
1876 return 0;
1877}
1878
Chris Wilson7e37f882016-08-02 22:50:21 +01001879static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001880{
Chris Wilsonfe085f12017-03-21 10:25:52 +00001881 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1882 ring->space, ring->head, ring->tail);
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001883}
1884
Ben Widawskye76d3632011-03-19 18:14:29 -07001885static int i915_context_status(struct seq_file *m, void *unused)
1886{
David Weinehall36cdd012016-08-22 13:59:31 +03001887 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1888 struct drm_device *dev = &dev_priv->drm;
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00001889 struct intel_engine_cs *engine;
Chris Wilsone2efd132016-05-24 14:53:34 +01001890 struct i915_gem_context *ctx;
Akash Goel3b3f1652016-10-13 22:44:48 +05301891 enum intel_engine_id id;
Dave Gordonc3232b12016-03-23 18:19:53 +00001892 int ret;
Ben Widawskye76d3632011-03-19 18:14:29 -07001893
Daniel Vetterf3d28872014-05-29 23:23:08 +02001894 ret = mutex_lock_interruptible(&dev->struct_mutex);
Ben Widawskye76d3632011-03-19 18:14:29 -07001895 if (ret)
1896 return ret;
1897
Chris Wilson829a0af2017-06-20 12:05:45 +01001898 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
Chris Wilson5d1808e2016-04-28 09:56:51 +01001899 seq_printf(m, "HW context %u ", ctx->hw_id);
Chris Wilsonc84455b2016-08-15 10:49:08 +01001900 if (ctx->pid) {
Chris Wilsond28b99a2016-05-24 14:53:39 +01001901 struct task_struct *task;
1902
Chris Wilsonc84455b2016-08-15 10:49:08 +01001903 task = get_pid_task(ctx->pid, PIDTYPE_PID);
Chris Wilsond28b99a2016-05-24 14:53:39 +01001904 if (task) {
1905 seq_printf(m, "(%s [%d]) ",
1906 task->comm, task->pid);
1907 put_task_struct(task);
1908 }
Chris Wilsonc84455b2016-08-15 10:49:08 +01001909 } else if (IS_ERR(ctx->file_priv)) {
1910 seq_puts(m, "(deleted) ");
Chris Wilsond28b99a2016-05-24 14:53:39 +01001911 } else {
1912 seq_puts(m, "(kernel) ");
1913 }
1914
Chris Wilsonbca44d82016-05-24 14:53:41 +01001915 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1916 seq_putc(m, '\n');
Ben Widawskya33afea2013-09-17 21:12:45 -07001917
Akash Goel3b3f1652016-10-13 22:44:48 +05301918 for_each_engine(engine, dev_priv, id) {
Chris Wilsonbca44d82016-05-24 14:53:41 +01001919 struct intel_context *ce = &ctx->engine[engine->id];
1920
1921 seq_printf(m, "%s: ", engine->name);
Chris Wilsonbca44d82016-05-24 14:53:41 +01001922 if (ce->state)
Chris Wilsonbf3783e2016-08-15 10:48:54 +01001923 describe_obj(m, ce->state->obj);
Chris Wilsondca33ec2016-08-02 22:50:20 +01001924 if (ce->ring)
Chris Wilson7e37f882016-08-02 22:50:21 +01001925 describe_ctx_ring(m, ce->ring);
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001926 seq_putc(m, '\n');
Oscar Mateoc9fe99b2014-07-24 17:04:46 +01001927 }
1928
Ben Widawskya33afea2013-09-17 21:12:45 -07001929 seq_putc(m, '\n');
Ben Widawskya168c292013-02-14 15:05:12 -08001930 }
1931
Daniel Vetterf3d28872014-05-29 23:23:08 +02001932 mutex_unlock(&dev->struct_mutex);
Ben Widawskye76d3632011-03-19 18:14:29 -07001933
1934 return 0;
1935}
1936
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001937static const char *swizzle_string(unsigned swizzle)
1938{
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001939 switch (swizzle) {
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001940 case I915_BIT_6_SWIZZLE_NONE:
1941 return "none";
1942 case I915_BIT_6_SWIZZLE_9:
1943 return "bit9";
1944 case I915_BIT_6_SWIZZLE_9_10:
1945 return "bit9/bit10";
1946 case I915_BIT_6_SWIZZLE_9_11:
1947 return "bit9/bit11";
1948 case I915_BIT_6_SWIZZLE_9_10_11:
1949 return "bit9/bit10/bit11";
1950 case I915_BIT_6_SWIZZLE_9_17:
1951 return "bit9/bit17";
1952 case I915_BIT_6_SWIZZLE_9_10_17:
1953 return "bit9/bit10/bit17";
1954 case I915_BIT_6_SWIZZLE_UNKNOWN:
Masanari Iida8a168ca2012-12-29 02:00:09 +09001955 return "unknown";
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001956 }
1957
1958 return "bug";
1959}
1960
1961static int i915_swizzle_info(struct seq_file *m, void *data)
1962{
David Weinehall36cdd012016-08-22 13:59:31 +03001963 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001964
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001965 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001966
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001967 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1968 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1969 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1970 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1971
David Weinehall36cdd012016-08-22 13:59:31 +03001972 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001973 seq_printf(m, "DDC = 0x%08x\n",
1974 I915_READ(DCC));
Daniel Vetter656bfa32014-11-20 09:26:30 +01001975 seq_printf(m, "DDC2 = 0x%08x\n",
1976 I915_READ(DCC2));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001977 seq_printf(m, "C0DRB3 = 0x%04x\n",
1978 I915_READ16(C0DRB3));
1979 seq_printf(m, "C1DRB3 = 0x%04x\n",
1980 I915_READ16(C1DRB3));
David Weinehall36cdd012016-08-22 13:59:31 +03001981 } else if (INTEL_GEN(dev_priv) >= 6) {
Daniel Vetter3fa7d232012-01-31 16:47:56 +01001982 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1983 I915_READ(MAD_DIMM_C0));
1984 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1985 I915_READ(MAD_DIMM_C1));
1986 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1987 I915_READ(MAD_DIMM_C2));
1988 seq_printf(m, "TILECTL = 0x%08x\n",
1989 I915_READ(TILECTL));
David Weinehall36cdd012016-08-22 13:59:31 +03001990 if (INTEL_GEN(dev_priv) >= 8)
Ben Widawsky9d3203e2013-11-02 21:07:14 -07001991 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1992 I915_READ(GAMTARBMODE));
1993 else
1994 seq_printf(m, "ARB_MODE = 0x%08x\n",
1995 I915_READ(ARB_MODE));
Daniel Vetter3fa7d232012-01-31 16:47:56 +01001996 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1997 I915_READ(DISP_ARB_CTL));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001998 }
Daniel Vetter656bfa32014-11-20 09:26:30 +01001999
2000 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2001 seq_puts(m, "L-shaped memory detected\n");
2002
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002003 intel_runtime_pm_put(dev_priv);
Daniel Vetterea16a3c2011-12-14 13:57:16 +01002004
2005 return 0;
2006}
2007
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002008static int per_file_ctx(int id, void *ptr, void *data)
2009{
Chris Wilsone2efd132016-05-24 14:53:34 +01002010 struct i915_gem_context *ctx = ptr;
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002011 struct seq_file *m = data;
Daniel Vetterae6c4802014-08-06 15:04:53 +02002012 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2013
2014 if (!ppgtt) {
2015 seq_printf(m, " no ppgtt for context %d\n",
2016 ctx->user_handle);
2017 return 0;
2018 }
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002019
Oscar Mateof83d6512014-05-22 14:13:38 +01002020 if (i915_gem_context_is_default(ctx))
2021 seq_puts(m, " default context:\n");
2022 else
Oscar Mateo821d66d2014-07-03 16:28:00 +01002023 seq_printf(m, " context %d:\n", ctx->user_handle);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002024 ppgtt->debug_dump(ppgtt, m);
2025
2026 return 0;
2027}
2028
David Weinehall36cdd012016-08-22 13:59:31 +03002029static void gen8_ppgtt_info(struct seq_file *m,
2030 struct drm_i915_private *dev_priv)
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002031{
Ben Widawsky77df6772013-11-02 21:07:30 -07002032 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
Akash Goel3b3f1652016-10-13 22:44:48 +05302033 struct intel_engine_cs *engine;
2034 enum intel_engine_id id;
Dave Gordonb4ac5af2016-03-24 11:20:38 +00002035 int i;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002036
Ben Widawsky77df6772013-11-02 21:07:30 -07002037 if (!ppgtt)
2038 return;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002039
Akash Goel3b3f1652016-10-13 22:44:48 +05302040 for_each_engine(engine, dev_priv, id) {
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002041 seq_printf(m, "%s\n", engine->name);
Ben Widawsky77df6772013-11-02 21:07:30 -07002042 for (i = 0; i < 4; i++) {
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002043 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
Ben Widawsky77df6772013-11-02 21:07:30 -07002044 pdp <<= 32;
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002045 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
Ville Syrjäläa2a5b152014-03-31 18:17:16 +03002046 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
Ben Widawsky77df6772013-11-02 21:07:30 -07002047 }
2048 }
2049}
2050
David Weinehall36cdd012016-08-22 13:59:31 +03002051static void gen6_ppgtt_info(struct seq_file *m,
2052 struct drm_i915_private *dev_priv)
Ben Widawsky77df6772013-11-02 21:07:30 -07002053{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002054 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +05302055 enum intel_engine_id id;
Ben Widawsky77df6772013-11-02 21:07:30 -07002056
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01002057 if (IS_GEN6(dev_priv))
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002058 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2059
Akash Goel3b3f1652016-10-13 22:44:48 +05302060 for_each_engine(engine, dev_priv, id) {
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002061 seq_printf(m, "%s\n", engine->name);
Tvrtko Ursulin7e22dbb2016-05-10 10:57:06 +01002062 if (IS_GEN7(dev_priv))
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002063 seq_printf(m, "GFX_MODE: 0x%08x\n",
2064 I915_READ(RING_MODE_GEN7(engine)));
2065 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2066 I915_READ(RING_PP_DIR_BASE(engine)));
2067 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2068 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2069 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2070 I915_READ(RING_PP_DIR_DCLV(engine)));
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002071 }
2072 if (dev_priv->mm.aliasing_ppgtt) {
2073 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2074
Damien Lespiau267f0c92013-06-24 22:59:48 +01002075 seq_puts(m, "aliasing PPGTT:\n");
Mika Kuoppala44159dd2015-06-25 18:35:07 +03002076 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002077
Ben Widawsky87d60b62013-12-06 14:11:29 -08002078 ppgtt->debug_dump(ppgtt, m);
Daniel Vetterae6c4802014-08-06 15:04:53 +02002079 }
Ben Widawsky1c60fef2013-12-06 14:11:30 -08002080
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002081 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
Ben Widawsky77df6772013-11-02 21:07:30 -07002082}
2083
2084static int i915_ppgtt_info(struct seq_file *m, void *data)
2085{
David Weinehall36cdd012016-08-22 13:59:31 +03002086 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2087 struct drm_device *dev = &dev_priv->drm;
Michel Thierryea91e402015-07-29 17:23:57 +01002088 struct drm_file *file;
Chris Wilson637ee292016-08-22 14:28:20 +01002089 int ret;
Ben Widawsky77df6772013-11-02 21:07:30 -07002090
Chris Wilson637ee292016-08-22 14:28:20 +01002091 mutex_lock(&dev->filelist_mutex);
2092 ret = mutex_lock_interruptible(&dev->struct_mutex);
Ben Widawsky77df6772013-11-02 21:07:30 -07002093 if (ret)
Chris Wilson637ee292016-08-22 14:28:20 +01002094 goto out_unlock;
2095
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002096 intel_runtime_pm_get(dev_priv);
Ben Widawsky77df6772013-11-02 21:07:30 -07002097
David Weinehall36cdd012016-08-22 13:59:31 +03002098 if (INTEL_GEN(dev_priv) >= 8)
2099 gen8_ppgtt_info(m, dev_priv);
2100 else if (INTEL_GEN(dev_priv) >= 6)
2101 gen6_ppgtt_info(m, dev_priv);
Ben Widawsky77df6772013-11-02 21:07:30 -07002102
Michel Thierryea91e402015-07-29 17:23:57 +01002103 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2104 struct drm_i915_file_private *file_priv = file->driver_priv;
Geliang Tang7cb5dff2015-09-25 03:58:11 -07002105 struct task_struct *task;
Michel Thierryea91e402015-07-29 17:23:57 +01002106
Geliang Tang7cb5dff2015-09-25 03:58:11 -07002107 task = get_pid_task(file->pid, PIDTYPE_PID);
Dan Carpenter06812762015-10-02 18:14:22 +03002108 if (!task) {
2109 ret = -ESRCH;
Chris Wilson637ee292016-08-22 14:28:20 +01002110 goto out_rpm;
Dan Carpenter06812762015-10-02 18:14:22 +03002111 }
Geliang Tang7cb5dff2015-09-25 03:58:11 -07002112 seq_printf(m, "\nproc: %s\n", task->comm);
2113 put_task_struct(task);
Michel Thierryea91e402015-07-29 17:23:57 +01002114 idr_for_each(&file_priv->context_idr, per_file_ctx,
2115 (void *)(unsigned long)m);
2116 }
2117
Chris Wilson637ee292016-08-22 14:28:20 +01002118out_rpm:
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002119 intel_runtime_pm_put(dev_priv);
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002120 mutex_unlock(&dev->struct_mutex);
Chris Wilson637ee292016-08-22 14:28:20 +01002121out_unlock:
2122 mutex_unlock(&dev->filelist_mutex);
Dan Carpenter06812762015-10-02 18:14:22 +03002123 return ret;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01002124}
2125
Chris Wilsonf5a4c672015-04-27 13:41:23 +01002126static int count_irq_waiters(struct drm_i915_private *i915)
2127{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002128 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +05302129 enum intel_engine_id id;
Chris Wilsonf5a4c672015-04-27 13:41:23 +01002130 int count = 0;
Chris Wilsonf5a4c672015-04-27 13:41:23 +01002131
Akash Goel3b3f1652016-10-13 22:44:48 +05302132 for_each_engine(engine, i915, id)
Chris Wilson688e6c72016-07-01 17:23:15 +01002133 count += intel_engine_has_waiter(engine);
Chris Wilsonf5a4c672015-04-27 13:41:23 +01002134
2135 return count;
2136}
2137
Chris Wilson7466c292016-08-15 09:49:33 +01002138static const char *rps_power_to_str(unsigned int power)
2139{
2140 static const char * const strings[] = {
2141 [LOW_POWER] = "low power",
2142 [BETWEEN] = "mixed",
2143 [HIGH_POWER] = "high power",
2144 };
2145
2146 if (power >= ARRAY_SIZE(strings) || !strings[power])
2147 return "unknown";
2148
2149 return strings[power];
2150}
2151
Chris Wilson1854d5c2015-04-07 16:20:32 +01002152static int i915_rps_boost_info(struct seq_file *m, void *data)
2153{
David Weinehall36cdd012016-08-22 13:59:31 +03002154 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2155 struct drm_device *dev = &dev_priv->drm;
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002156 struct intel_rps *rps = &dev_priv->gt_pm.rps;
Chris Wilson1854d5c2015-04-07 16:20:32 +01002157 struct drm_file *file;
Chris Wilson1854d5c2015-04-07 16:20:32 +01002158
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002159 seq_printf(m, "RPS enabled? %d\n", rps->enabled);
Chris Wilson28176ef2016-10-28 13:58:56 +01002160 seq_printf(m, "GPU busy? %s [%d requests]\n",
2161 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
Chris Wilsonf5a4c672015-04-27 13:41:23 +01002162 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
Chris Wilson7b92c1b2017-06-28 13:35:48 +01002163 seq_printf(m, "Boosts outstanding? %d\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002164 atomic_read(&rps->num_waiters));
Chris Wilson7466c292016-08-15 09:49:33 +01002165 seq_printf(m, "Frequency requested %d\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002166 intel_gpu_freq(dev_priv, rps->cur_freq));
Chris Wilson7466c292016-08-15 09:49:33 +01002167 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002168 intel_gpu_freq(dev_priv, rps->min_freq),
2169 intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2170 intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2171 intel_gpu_freq(dev_priv, rps->max_freq));
Chris Wilson7466c292016-08-15 09:49:33 +01002172 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002173 intel_gpu_freq(dev_priv, rps->idle_freq),
2174 intel_gpu_freq(dev_priv, rps->efficient_freq),
2175 intel_gpu_freq(dev_priv, rps->boost_freq));
Daniel Vetter1d2ac402016-04-26 19:29:41 +02002176
2177 mutex_lock(&dev->filelist_mutex);
Chris Wilson1854d5c2015-04-07 16:20:32 +01002178 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2179 struct drm_i915_file_private *file_priv = file->driver_priv;
2180 struct task_struct *task;
2181
2182 rcu_read_lock();
2183 task = pid_task(file->pid, PIDTYPE_PID);
Chris Wilson7b92c1b2017-06-28 13:35:48 +01002184 seq_printf(m, "%s [%d]: %d boosts\n",
Chris Wilson1854d5c2015-04-07 16:20:32 +01002185 task ? task->comm : "<unknown>",
2186 task ? task->pid : -1,
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002187 atomic_read(&file_priv->rps_client.boosts));
Chris Wilson1854d5c2015-04-07 16:20:32 +01002188 rcu_read_unlock();
2189 }
Chris Wilson7b92c1b2017-06-28 13:35:48 +01002190 seq_printf(m, "Kernel (anonymous) boosts: %d\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002191 atomic_read(&rps->boosts));
Daniel Vetter1d2ac402016-04-26 19:29:41 +02002192 mutex_unlock(&dev->filelist_mutex);
Chris Wilson1854d5c2015-04-07 16:20:32 +01002193
Chris Wilson7466c292016-08-15 09:49:33 +01002194 if (INTEL_GEN(dev_priv) >= 6 &&
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002195 rps->enabled &&
Chris Wilson28176ef2016-10-28 13:58:56 +01002196 dev_priv->gt.active_requests) {
Chris Wilson7466c292016-08-15 09:49:33 +01002197 u32 rpup, rpupei;
2198 u32 rpdown, rpdownei;
2199
2200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2201 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2202 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2203 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2204 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2205 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2206
2207 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002208 rps_power_to_str(rps->power));
Chris Wilson7466c292016-08-15 09:49:33 +01002209 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
Chris Wilson23f4a282017-02-18 11:27:08 +00002210 rpup && rpupei ? 100 * rpup / rpupei : 0,
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002211 rps->up_threshold);
Chris Wilson7466c292016-08-15 09:49:33 +01002212 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
Chris Wilson23f4a282017-02-18 11:27:08 +00002213 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01002214 rps->down_threshold);
Chris Wilson7466c292016-08-15 09:49:33 +01002215 } else {
2216 seq_puts(m, "\nRPS Autotuning inactive\n");
2217 }
2218
Chris Wilson8d3afd72015-05-21 21:01:47 +01002219 return 0;
Chris Wilson1854d5c2015-04-07 16:20:32 +01002220}
2221
Ben Widawsky63573eb2013-07-04 11:02:07 -07002222static int i915_llc(struct seq_file *m, void *data)
2223{
David Weinehall36cdd012016-08-22 13:59:31 +03002224 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Mika Kuoppala3accaf72016-04-13 17:26:43 +03002225 const bool edram = INTEL_GEN(dev_priv) > 8;
Ben Widawsky63573eb2013-07-04 11:02:07 -07002226
David Weinehall36cdd012016-08-22 13:59:31 +03002227 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
Mika Kuoppala3accaf72016-04-13 17:26:43 +03002228 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2229 intel_uncore_edram_size(dev_priv)/1024/1024);
Ben Widawsky63573eb2013-07-04 11:02:07 -07002230
2231 return 0;
2232}
2233
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002234static int i915_huc_load_status_info(struct seq_file *m, void *data)
2235{
2236 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Michal Wajdeczko56ffc742017-10-17 09:44:49 +00002237 struct drm_printer p;
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002238
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002239 if (!HAS_HUC(dev_priv))
2240 return -ENODEV;
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002241
Michal Wajdeczko56ffc742017-10-17 09:44:49 +00002242 p = drm_seq_file_printer(m);
2243 intel_uc_fw_dump(&dev_priv->huc.fw, &p);
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002244
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +05302245 intel_runtime_pm_get(dev_priv);
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002246 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +05302247 intel_runtime_pm_put(dev_priv);
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08002248
2249 return 0;
2250}
2251
Alex Daifdf5d352015-08-12 15:43:37 +01002252static int i915_guc_load_status_info(struct seq_file *m, void *data)
2253{
David Weinehall36cdd012016-08-22 13:59:31 +03002254 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Michal Wajdeczko56ffc742017-10-17 09:44:49 +00002255 struct drm_printer p;
Alex Daifdf5d352015-08-12 15:43:37 +01002256 u32 tmp, i;
2257
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002258 if (!HAS_GUC(dev_priv))
2259 return -ENODEV;
Alex Daifdf5d352015-08-12 15:43:37 +01002260
Michal Wajdeczko56ffc742017-10-17 09:44:49 +00002261 p = drm_seq_file_printer(m);
2262 intel_uc_fw_dump(&dev_priv->guc.fw, &p);
Alex Daifdf5d352015-08-12 15:43:37 +01002263
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +05302264 intel_runtime_pm_get(dev_priv);
2265
Alex Daifdf5d352015-08-12 15:43:37 +01002266 tmp = I915_READ(GUC_STATUS);
2267
2268 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2269 seq_printf(m, "\tBootrom status = 0x%x\n",
2270 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2271 seq_printf(m, "\tuKernel status = 0x%x\n",
2272 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2273 seq_printf(m, "\tMIA Core status = 0x%x\n",
2274 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2275 seq_puts(m, "\nScratch registers:\n");
2276 for (i = 0; i < 16; i++)
2277 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2278
sagar.a.kamble@intel.com3582ad12017-02-03 13:58:33 +05302279 intel_runtime_pm_put(dev_priv);
2280
Alex Daifdf5d352015-08-12 15:43:37 +01002281 return 0;
2282}
2283
Akash Goel5aa1ee42016-10-12 21:54:36 +05302284static void i915_guc_log_info(struct seq_file *m,
2285 struct drm_i915_private *dev_priv)
2286{
2287 struct intel_guc *guc = &dev_priv->guc;
2288
2289 seq_puts(m, "\nGuC logging stats:\n");
2290
2291 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2292 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2293 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2294
2295 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2296 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2297 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2298
2299 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2300 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2301 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2302
2303 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2304 guc->log.flush_interrupt_count);
2305
2306 seq_printf(m, "\tCapture miss count: %u\n",
2307 guc->log.capture_miss_count);
2308}
2309
Dave Gordon8b417c22015-08-12 15:43:44 +01002310static void i915_guc_client_info(struct seq_file *m,
2311 struct drm_i915_private *dev_priv,
Sagar Arun Kamble5afc8b42017-11-16 19:02:40 +05302312 struct intel_guc_client *client)
Dave Gordon8b417c22015-08-12 15:43:44 +01002313{
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00002314 struct intel_engine_cs *engine;
Dave Gordonc18468c2016-08-09 15:19:22 +01002315 enum intel_engine_id id;
Dave Gordon8b417c22015-08-12 15:43:44 +01002316 uint64_t tot = 0;
Dave Gordon8b417c22015-08-12 15:43:44 +01002317
Oscar Mateob09935a2017-03-22 10:39:53 -07002318 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2319 client->priority, client->stage_id, client->proc_desc_offset);
Michał Winiarski59db36c2017-09-14 12:51:23 +02002320 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2321 client->doorbell_id, client->doorbell_offset);
Dave Gordon8b417c22015-08-12 15:43:44 +01002322
Akash Goel3b3f1652016-10-13 22:44:48 +05302323 for_each_engine(engine, dev_priv, id) {
Dave Gordonc18468c2016-08-09 15:19:22 +01002324 u64 submissions = client->submissions[id];
2325 tot += submissions;
Dave Gordon8b417c22015-08-12 15:43:44 +01002326 seq_printf(m, "\tSubmissions: %llu %s\n",
Dave Gordonc18468c2016-08-09 15:19:22 +01002327 submissions, engine->name);
Dave Gordon8b417c22015-08-12 15:43:44 +01002328 }
2329 seq_printf(m, "\tTotal: %llu\n", tot);
2330}
2331
2332static int i915_guc_info(struct seq_file *m, void *data)
2333{
David Weinehall36cdd012016-08-22 13:59:31 +03002334 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Chris Wilson334636c2016-11-29 12:10:20 +00002335 const struct intel_guc *guc = &dev_priv->guc;
Dave Gordon8b417c22015-08-12 15:43:44 +01002336
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002337 if (!USES_GUC_SUBMISSION(dev_priv))
2338 return -ENODEV;
2339
2340 GEM_BUG_ON(!guc->execbuf_client);
2341 GEM_BUG_ON(!guc->preempt_client);
Dave Gordon8b417c22015-08-12 15:43:44 +01002342
Dave Gordon9636f6d2016-06-13 17:57:28 +01002343 seq_printf(m, "Doorbell map:\n");
Joonas Lahtinenabddffd2017-03-22 10:39:44 -07002344 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
Chris Wilson334636c2016-11-29 12:10:20 +00002345 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
Dave Gordon9636f6d2016-06-13 17:57:28 +01002346
Chris Wilson334636c2016-11-29 12:10:20 +00002347 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2348 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
Dave Gordone12ab162017-10-26 16:17:37 +02002349 seq_printf(m, "\nGuC preempt client @ %p:\n", guc->preempt_client);
2350 i915_guc_client_info(m, dev_priv, guc->preempt_client);
Dave Gordon8b417c22015-08-12 15:43:44 +01002351
Akash Goel5aa1ee42016-10-12 21:54:36 +05302352 i915_guc_log_info(m, dev_priv);
2353
Dave Gordon8b417c22015-08-12 15:43:44 +01002354 /* Add more as required ... */
2355
2356 return 0;
2357}
2358
Oscar Mateoa8b93702017-05-10 15:04:51 +00002359static int i915_guc_stage_pool(struct seq_file *m, void *data)
Alex Dai4c7e77f2015-08-12 15:43:40 +01002360{
David Weinehall36cdd012016-08-22 13:59:31 +03002361 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Oscar Mateoa8b93702017-05-10 15:04:51 +00002362 const struct intel_guc *guc = &dev_priv->guc;
2363 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
Sagar Arun Kamble5afc8b42017-11-16 19:02:40 +05302364 struct intel_guc_client *client = guc->execbuf_client;
Oscar Mateoa8b93702017-05-10 15:04:51 +00002365 unsigned int tmp;
2366 int index;
Alex Dai4c7e77f2015-08-12 15:43:40 +01002367
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002368 if (!USES_GUC_SUBMISSION(dev_priv))
2369 return -ENODEV;
Alex Dai4c7e77f2015-08-12 15:43:40 +01002370
Oscar Mateoa8b93702017-05-10 15:04:51 +00002371 for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2372 struct intel_engine_cs *engine;
Alex Dai4c7e77f2015-08-12 15:43:40 +01002373
Oscar Mateoa8b93702017-05-10 15:04:51 +00002374 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2375 continue;
Alex Dai4c7e77f2015-08-12 15:43:40 +01002376
Oscar Mateoa8b93702017-05-10 15:04:51 +00002377 seq_printf(m, "GuC stage descriptor %u:\n", index);
2378 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2379 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2380 seq_printf(m, "\tPriority: %d\n", desc->priority);
2381 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2382 seq_printf(m, "\tEngines used: 0x%x\n",
2383 desc->engines_used);
2384 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2385 desc->db_trigger_phy,
2386 desc->db_trigger_cpu,
2387 desc->db_trigger_uk);
2388 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2389 desc->process_desc);
Colin Ian King9a094852017-05-16 10:22:35 +01002390 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
Oscar Mateoa8b93702017-05-10 15:04:51 +00002391 desc->wq_addr, desc->wq_size);
2392 seq_putc(m, '\n');
2393
2394 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2395 u32 guc_engine_id = engine->guc_id;
2396 struct guc_execlist_context *lrc =
2397 &desc->lrc[guc_engine_id];
2398
2399 seq_printf(m, "\t%s LRC:\n", engine->name);
2400 seq_printf(m, "\t\tContext desc: 0x%x\n",
2401 lrc->context_desc);
2402 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2403 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2404 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2405 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2406 seq_putc(m, '\n');
2407 }
Alex Dai4c7e77f2015-08-12 15:43:40 +01002408 }
2409
Oscar Mateoa8b93702017-05-10 15:04:51 +00002410 return 0;
2411}
2412
Alex Dai4c7e77f2015-08-12 15:43:40 +01002413static int i915_guc_log_dump(struct seq_file *m, void *data)
2414{
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07002415 struct drm_info_node *node = m->private;
2416 struct drm_i915_private *dev_priv = node_to_i915(node);
2417 bool dump_load_err = !!node->info_ent->data;
2418 struct drm_i915_gem_object *obj = NULL;
2419 u32 *log;
2420 int i = 0;
Alex Dai4c7e77f2015-08-12 15:43:40 +01002421
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002422 if (!HAS_GUC(dev_priv))
2423 return -ENODEV;
2424
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07002425 if (dump_load_err)
2426 obj = dev_priv->guc.load_err_log;
2427 else if (dev_priv->guc.log.vma)
2428 obj = dev_priv->guc.log.vma->obj;
2429
2430 if (!obj)
Alex Dai4c7e77f2015-08-12 15:43:40 +01002431 return 0;
2432
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07002433 log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2434 if (IS_ERR(log)) {
2435 DRM_DEBUG("Failed to pin object\n");
2436 seq_puts(m, "(log data unaccessible)\n");
2437 return PTR_ERR(log);
Alex Dai4c7e77f2015-08-12 15:43:40 +01002438 }
2439
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07002440 for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2441 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2442 *(log + i), *(log + i + 1),
2443 *(log + i + 2), *(log + i + 3));
2444
Alex Dai4c7e77f2015-08-12 15:43:40 +01002445 seq_putc(m, '\n');
2446
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07002447 i915_gem_object_unpin_map(obj);
2448
Alex Dai4c7e77f2015-08-12 15:43:40 +01002449 return 0;
2450}
2451
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302452static int i915_guc_log_control_get(void *data, u64 *val)
2453{
Chris Wilsonbcc36d82017-04-07 20:42:20 +01002454 struct drm_i915_private *dev_priv = data;
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302455
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002456 if (!HAS_GUC(dev_priv))
2457 return -ENODEV;
2458
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302459 if (!dev_priv->guc.log.vma)
2460 return -EINVAL;
2461
Michal Wajdeczko4f044a82017-09-19 19:38:44 +00002462 *val = i915_modparams.guc_log_level;
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302463
2464 return 0;
2465}
2466
2467static int i915_guc_log_control_set(void *data, u64 val)
2468{
Chris Wilsonbcc36d82017-04-07 20:42:20 +01002469 struct drm_i915_private *dev_priv = data;
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302470 int ret;
2471
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002472 if (!HAS_GUC(dev_priv))
2473 return -ENODEV;
2474
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302475 if (!dev_priv->guc.log.vma)
2476 return -EINVAL;
2477
Chris Wilsonbcc36d82017-04-07 20:42:20 +01002478 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302479 if (ret)
2480 return ret;
2481
2482 intel_runtime_pm_get(dev_priv);
2483 ret = i915_guc_log_control(dev_priv, val);
2484 intel_runtime_pm_put(dev_priv);
2485
Chris Wilsonbcc36d82017-04-07 20:42:20 +01002486 mutex_unlock(&dev_priv->drm.struct_mutex);
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05302487 return ret;
2488}
2489
2490DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2491 i915_guc_log_control_get, i915_guc_log_control_set,
2492 "%lld\n");
2493
Chris Wilsonb86bef202017-01-16 13:06:21 +00002494static const char *psr2_live_status(u32 val)
2495{
2496 static const char * const live_status[] = {
2497 "IDLE",
2498 "CAPTURE",
2499 "CAPTURE_FS",
2500 "SLEEP",
2501 "BUFON_FW",
2502 "ML_UP",
2503 "SU_STANDBY",
2504 "FAST_SLEEP",
2505 "DEEP_SLEEP",
2506 "BUF_ON",
2507 "TG_ON"
2508 };
2509
2510 val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2511 if (val < ARRAY_SIZE(live_status))
2512 return live_status[val];
2513
2514 return "unknown";
2515}
2516
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002517static int i915_edp_psr_status(struct seq_file *m, void *data)
2518{
David Weinehall36cdd012016-08-22 13:59:31 +03002519 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Rodrigo Vivia031d702013-10-03 16:15:06 -03002520 u32 psrperf = 0;
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002521 u32 stat[3];
2522 enum pipe pipe;
Rodrigo Vivia031d702013-10-03 16:15:06 -03002523 bool enabled = false;
Dhinakaran Pandiyanc9ef2912018-01-03 13:38:24 -08002524 bool sink_support;
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002525
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002526 if (!HAS_PSR(dev_priv))
2527 return -ENODEV;
Damien Lespiau3553a8e2015-03-09 14:17:58 +00002528
Dhinakaran Pandiyanc9ef2912018-01-03 13:38:24 -08002529 sink_support = dev_priv->psr.sink_support;
2530 seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
2531 if (!sink_support)
2532 return 0;
2533
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002534 intel_runtime_pm_get(dev_priv);
2535
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002536 mutex_lock(&dev_priv->psr.lock);
Daniel Vetter2807cf62014-07-11 10:30:11 -07002537 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
Rodrigo Vivi5755c782014-06-12 10:16:45 -07002538 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002539 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2540 dev_priv->psr.busy_frontbuffer_bits);
2541 seq_printf(m, "Re-enable work scheduled: %s\n",
2542 yesno(work_busy(&dev_priv->psr.work.work)));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002543
Nagaraju, Vathsala7e3eb592016-12-09 23:42:09 +05302544 if (HAS_DDI(dev_priv)) {
2545 if (dev_priv->psr.psr2_support)
2546 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2547 else
2548 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2549 } else {
Damien Lespiau3553a8e2015-03-09 14:17:58 +00002550 for_each_pipe(dev_priv, pipe) {
Chris Wilson9c870d02016-10-24 13:42:15 +01002551 enum transcoder cpu_transcoder =
2552 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2553 enum intel_display_power_domain power_domain;
2554
2555 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2556 if (!intel_display_power_get_if_enabled(dev_priv,
2557 power_domain))
2558 continue;
2559
Damien Lespiau3553a8e2015-03-09 14:17:58 +00002560 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2561 VLV_EDP_PSR_CURR_STATE_MASK;
2562 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2563 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2564 enabled = true;
Chris Wilson9c870d02016-10-24 13:42:15 +01002565
2566 intel_display_power_put(dev_priv, power_domain);
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002567 }
2568 }
Rodrigo Vivi60e5ffe2016-02-01 12:02:07 -08002569
2570 seq_printf(m, "Main link in standby mode: %s\n",
2571 yesno(dev_priv->psr.link_standby));
2572
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002573 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002574
David Weinehall36cdd012016-08-22 13:59:31 +03002575 if (!HAS_DDI(dev_priv))
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002576 for_each_pipe(dev_priv, pipe) {
2577 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2578 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2579 seq_printf(m, " pipe %c", pipe_name(pipe));
2580 }
2581 seq_puts(m, "\n");
2582
Rodrigo Vivi05eec3c2015-11-23 14:16:40 -08002583 /*
2584 * VLV/CHV PSR has no kind of performance counter
2585 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2586 */
David Weinehall36cdd012016-08-22 13:59:31 +03002587 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Ville Syrjälä443a3892015-11-11 20:34:15 +02002588 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
Rodrigo Vivia031d702013-10-03 16:15:06 -03002589 EDP_PSR_PERF_CNT_MASK;
Rodrigo Vivia6cbdb82014-11-14 08:52:40 -08002590
2591 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2592 }
Nagaraju, Vathsala6ba1f9e2017-01-06 22:02:32 +05302593 if (dev_priv->psr.psr2_support) {
Dhinakaran Pandiyan861023e2017-12-20 12:10:21 -08002594 u32 psr2 = I915_READ(EDP_PSR2_STATUS);
Nagaraju, Vathsala6ba1f9e2017-01-06 22:02:32 +05302595
Dhinakaran Pandiyan861023e2017-12-20 12:10:21 -08002596 seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
Chris Wilsonb86bef202017-01-16 13:06:21 +00002597 psr2, psr2_live_status(psr2));
Nagaraju, Vathsala6ba1f9e2017-01-06 22:02:32 +05302598 }
Daniel Vetterfa128fa2014-07-11 10:30:17 -07002599 mutex_unlock(&dev_priv->psr.lock);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002600
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02002601 intel_runtime_pm_put(dev_priv);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03002602 return 0;
2603}
2604
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002605static int i915_sink_crc(struct seq_file *m, void *data)
2606{
David Weinehall36cdd012016-08-22 13:59:31 +03002607 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2608 struct drm_device *dev = &dev_priv->drm;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002609 struct intel_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01002610 struct drm_connector_list_iter conn_iter;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002611 struct intel_dp *intel_dp = NULL;
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002612 struct drm_modeset_acquire_ctx ctx;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002613 int ret;
2614 u8 crc[6];
2615
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002616 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2617
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01002618 drm_connector_list_iter_begin(dev, &conn_iter);
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002619
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01002620 for_each_intel_connector_iter(connector, &conn_iter) {
Maarten Lankhorst26c17cf2016-06-20 15:57:38 +02002621 struct drm_crtc *crtc;
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002622 struct drm_connector_state *state;
Maarten Lankhorst93313532017-11-10 12:34:59 +01002623 struct intel_crtc_state *crtc_state;
Paulo Zanonib6ae3c72014-02-13 17:51:33 -02002624
Maarten Lankhorst26c17cf2016-06-20 15:57:38 +02002625 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002626 continue;
2627
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002628retry:
2629 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2630 if (ret)
2631 goto err;
2632
2633 state = connector->base.state;
2634 if (!state->best_encoder)
2635 continue;
2636
2637 crtc = state->crtc;
2638 ret = drm_modeset_lock(&crtc->mutex, &ctx);
2639 if (ret)
2640 goto err;
2641
Maarten Lankhorst93313532017-11-10 12:34:59 +01002642 crtc_state = to_intel_crtc_state(crtc->state);
2643 if (!crtc_state->base.active)
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002644 continue;
2645
Maarten Lankhorst93313532017-11-10 12:34:59 +01002646 /*
2647 * We need to wait for all crtc updates to complete, to make
2648 * sure any pending modesets and plane updates are completed.
2649 */
2650 if (crtc_state->base.commit) {
2651 ret = wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
2652
2653 if (ret)
2654 goto err;
2655 }
2656
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002657 intel_dp = enc_to_intel_dp(state->best_encoder);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002658
Maarten Lankhorst93313532017-11-10 12:34:59 +01002659 ret = intel_dp_sink_crc(intel_dp, crtc_state, crc);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002660 if (ret)
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002661 goto err;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002662
2663 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2664 crc[0], crc[1], crc[2],
2665 crc[3], crc[4], crc[5]);
2666 goto out;
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002667
2668err:
2669 if (ret == -EDEADLK) {
2670 ret = drm_modeset_backoff(&ctx);
2671 if (!ret)
2672 goto retry;
2673 }
2674 goto out;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002675 }
2676 ret = -ENODEV;
2677out:
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01002678 drm_connector_list_iter_end(&conn_iter);
Maarten Lankhorst10bf0a32017-11-10 12:34:58 +01002679 drm_modeset_drop_locks(&ctx);
2680 drm_modeset_acquire_fini(&ctx);
2681
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02002682 return ret;
2683}
2684
Jesse Barnesec013e72013-08-20 10:29:23 +01002685static int i915_energy_uJ(struct seq_file *m, void *data)
2686{
David Weinehall36cdd012016-08-22 13:59:31 +03002687 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Gabriel Krisman Bertazid38014e2017-07-26 02:30:16 -03002688 unsigned long long power;
Jesse Barnesec013e72013-08-20 10:29:23 +01002689 u32 units;
2690
David Weinehall36cdd012016-08-22 13:59:31 +03002691 if (INTEL_GEN(dev_priv) < 6)
Jesse Barnesec013e72013-08-20 10:29:23 +01002692 return -ENODEV;
2693
Paulo Zanoni36623ef2014-02-21 13:52:23 -03002694 intel_runtime_pm_get(dev_priv);
2695
Gabriel Krisman Bertazid38014e2017-07-26 02:30:16 -03002696 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2697 intel_runtime_pm_put(dev_priv);
2698 return -ENODEV;
2699 }
2700
2701 units = (power & 0x1f00) >> 8;
Jesse Barnesec013e72013-08-20 10:29:23 +01002702 power = I915_READ(MCH_SECP_NRG_STTS);
Gabriel Krisman Bertazid38014e2017-07-26 02:30:16 -03002703 power = (1000000 * power) >> units; /* convert to uJ */
Jesse Barnesec013e72013-08-20 10:29:23 +01002704
Paulo Zanoni36623ef2014-02-21 13:52:23 -03002705 intel_runtime_pm_put(dev_priv);
2706
Gabriel Krisman Bertazid38014e2017-07-26 02:30:16 -03002707 seq_printf(m, "%llu", power);
Paulo Zanoni371db662013-08-19 13:18:10 -03002708
2709 return 0;
2710}
2711
Damien Lespiau6455c872015-06-04 18:23:57 +01002712static int i915_runtime_pm_status(struct seq_file *m, void *unused)
Paulo Zanoni371db662013-08-19 13:18:10 -03002713{
David Weinehall36cdd012016-08-22 13:59:31 +03002714 struct drm_i915_private *dev_priv = node_to_i915(m->private);
David Weinehall52a05c32016-08-22 13:32:44 +03002715 struct pci_dev *pdev = dev_priv->drm.pdev;
Paulo Zanoni371db662013-08-19 13:18:10 -03002716
Chris Wilsona156e642016-04-03 14:14:21 +01002717 if (!HAS_RUNTIME_PM(dev_priv))
2718 seq_puts(m, "Runtime power management not supported\n");
Paulo Zanoni371db662013-08-19 13:18:10 -03002719
Chris Wilson67d97da2016-07-04 08:08:31 +01002720 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
Paulo Zanoni371db662013-08-19 13:18:10 -03002721 seq_printf(m, "IRQs disabled: %s\n",
Jesse Barnes9df7575f2014-06-20 09:29:20 -07002722 yesno(!intel_irqs_enabled(dev_priv)));
Chris Wilson0d804182015-06-15 12:52:28 +01002723#ifdef CONFIG_PM
Damien Lespiaua6aaec82015-06-04 18:23:58 +01002724 seq_printf(m, "Usage count: %d\n",
David Weinehall36cdd012016-08-22 13:59:31 +03002725 atomic_read(&dev_priv->drm.dev->power.usage_count));
Chris Wilson0d804182015-06-15 12:52:28 +01002726#else
2727 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2728#endif
Chris Wilsona156e642016-04-03 14:14:21 +01002729 seq_printf(m, "PCI device power state: %s [%d]\n",
David Weinehall52a05c32016-08-22 13:32:44 +03002730 pci_power_name(pdev->current_state),
2731 pdev->current_state);
Paulo Zanoni371db662013-08-19 13:18:10 -03002732
Jesse Barnesec013e72013-08-20 10:29:23 +01002733 return 0;
2734}
2735
Imre Deak1da51582013-11-25 17:15:35 +02002736static int i915_power_domain_info(struct seq_file *m, void *unused)
2737{
David Weinehall36cdd012016-08-22 13:59:31 +03002738 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Imre Deak1da51582013-11-25 17:15:35 +02002739 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2740 int i;
2741
2742 mutex_lock(&power_domains->lock);
2743
2744 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2745 for (i = 0; i < power_domains->power_well_count; i++) {
2746 struct i915_power_well *power_well;
2747 enum intel_display_power_domain power_domain;
2748
2749 power_well = &power_domains->power_wells[i];
2750 seq_printf(m, "%-25s %d\n", power_well->name,
2751 power_well->count);
2752
Joonas Lahtinen8385c2e2017-02-08 15:12:10 +02002753 for_each_power_domain(power_domain, power_well->domains)
Imre Deak1da51582013-11-25 17:15:35 +02002754 seq_printf(m, " %-23s %d\n",
Daniel Stone9895ad02015-11-20 15:55:33 +00002755 intel_display_power_domain_str(power_domain),
Imre Deak1da51582013-11-25 17:15:35 +02002756 power_domains->domain_use_count[power_domain]);
Imre Deak1da51582013-11-25 17:15:35 +02002757 }
2758
2759 mutex_unlock(&power_domains->lock);
2760
2761 return 0;
2762}
2763
Damien Lespiaub7cec662015-10-27 14:47:01 +02002764static int i915_dmc_info(struct seq_file *m, void *unused)
2765{
David Weinehall36cdd012016-08-22 13:59:31 +03002766 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Damien Lespiaub7cec662015-10-27 14:47:01 +02002767 struct intel_csr *csr;
2768
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00002769 if (!HAS_CSR(dev_priv))
2770 return -ENODEV;
Damien Lespiaub7cec662015-10-27 14:47:01 +02002771
2772 csr = &dev_priv->csr;
2773
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02002774 intel_runtime_pm_get(dev_priv);
2775
Damien Lespiaub7cec662015-10-27 14:47:01 +02002776 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2777 seq_printf(m, "path: %s\n", csr->fw_path);
2778
2779 if (!csr->dmc_payload)
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02002780 goto out;
Damien Lespiaub7cec662015-10-27 14:47:01 +02002781
2782 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2783 CSR_VERSION_MINOR(csr->version));
2784
Mika Kuoppala48de5682017-05-09 13:05:22 +03002785 if (IS_KABYLAKE(dev_priv) ||
2786 (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
Damien Lespiau83372062015-10-30 17:53:32 +02002787 seq_printf(m, "DC3 -> DC5 count: %d\n",
2788 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2789 seq_printf(m, "DC5 -> DC6 count: %d\n",
2790 I915_READ(SKL_CSR_DC5_DC6_COUNT));
David Weinehall36cdd012016-08-22 13:59:31 +03002791 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
Mika Kuoppala16e11b92015-10-27 14:47:03 +02002792 seq_printf(m, "DC3 -> DC5 count: %d\n",
2793 I915_READ(BXT_CSR_DC3_DC5_COUNT));
Damien Lespiau83372062015-10-30 17:53:32 +02002794 }
2795
Mika Kuoppala6fb403d2015-10-30 17:54:47 +02002796out:
2797 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2798 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2799 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2800
Damien Lespiau83372062015-10-30 17:53:32 +02002801 intel_runtime_pm_put(dev_priv);
2802
Damien Lespiaub7cec662015-10-27 14:47:01 +02002803 return 0;
2804}
2805
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002806static void intel_seq_print_mode(struct seq_file *m, int tabs,
2807 struct drm_display_mode *mode)
2808{
2809 int i;
2810
2811 for (i = 0; i < tabs; i++)
2812 seq_putc(m, '\t');
2813
2814 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2815 mode->base.id, mode->name,
2816 mode->vrefresh, mode->clock,
2817 mode->hdisplay, mode->hsync_start,
2818 mode->hsync_end, mode->htotal,
2819 mode->vdisplay, mode->vsync_start,
2820 mode->vsync_end, mode->vtotal,
2821 mode->type, mode->flags);
2822}
2823
2824static void intel_encoder_info(struct seq_file *m,
2825 struct intel_crtc *intel_crtc,
2826 struct intel_encoder *intel_encoder)
2827{
David Weinehall36cdd012016-08-22 13:59:31 +03002828 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2829 struct drm_device *dev = &dev_priv->drm;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002830 struct drm_crtc *crtc = &intel_crtc->base;
2831 struct intel_connector *intel_connector;
2832 struct drm_encoder *encoder;
2833
2834 encoder = &intel_encoder->base;
2835 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
Jani Nikula8e329a032014-06-03 14:56:21 +03002836 encoder->base.id, encoder->name);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002837 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2838 struct drm_connector *connector = &intel_connector->base;
2839 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2840 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03002841 connector->name,
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002842 drm_get_connector_status_name(connector->status));
2843 if (connector->status == connector_status_connected) {
2844 struct drm_display_mode *mode = &crtc->mode;
2845 seq_printf(m, ", mode:\n");
2846 intel_seq_print_mode(m, 2, mode);
2847 } else {
2848 seq_putc(m, '\n');
2849 }
2850 }
2851}
2852
2853static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2854{
David Weinehall36cdd012016-08-22 13:59:31 +03002855 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2856 struct drm_device *dev = &dev_priv->drm;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002857 struct drm_crtc *crtc = &intel_crtc->base;
2858 struct intel_encoder *intel_encoder;
Maarten Lankhorst23a48d52015-09-10 16:07:57 +02002859 struct drm_plane_state *plane_state = crtc->primary->state;
2860 struct drm_framebuffer *fb = plane_state->fb;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002861
Maarten Lankhorst23a48d52015-09-10 16:07:57 +02002862 if (fb)
Matt Roper5aa8a932014-06-16 10:12:55 -07002863 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
Maarten Lankhorst23a48d52015-09-10 16:07:57 +02002864 fb->base.id, plane_state->src_x >> 16,
2865 plane_state->src_y >> 16, fb->width, fb->height);
Matt Roper5aa8a932014-06-16 10:12:55 -07002866 else
2867 seq_puts(m, "\tprimary plane disabled\n");
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002868 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2869 intel_encoder_info(m, intel_crtc, intel_encoder);
2870}
2871
2872static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2873{
2874 struct drm_display_mode *mode = panel->fixed_mode;
2875
2876 seq_printf(m, "\tfixed mode:\n");
2877 intel_seq_print_mode(m, 2, mode);
2878}
2879
2880static void intel_dp_info(struct seq_file *m,
2881 struct intel_connector *intel_connector)
2882{
2883 struct intel_encoder *intel_encoder = intel_connector->encoder;
2884 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2885
2886 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
Jani Nikula742f4912015-09-03 11:16:09 +03002887 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02002888 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002889 intel_panel_info(m, &intel_connector->panel);
Mika Kahola80209e52016-09-09 14:10:57 +03002890
2891 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2892 &intel_dp->aux);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002893}
2894
Libin Yang9a148a92016-11-28 20:07:05 +08002895static void intel_dp_mst_info(struct seq_file *m,
2896 struct intel_connector *intel_connector)
2897{
2898 struct intel_encoder *intel_encoder = intel_connector->encoder;
2899 struct intel_dp_mst_encoder *intel_mst =
2900 enc_to_mst(&intel_encoder->base);
2901 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2902 struct intel_dp *intel_dp = &intel_dig_port->dp;
2903 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2904 intel_connector->port);
2905
2906 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2907}
2908
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002909static void intel_hdmi_info(struct seq_file *m,
2910 struct intel_connector *intel_connector)
2911{
2912 struct intel_encoder *intel_encoder = intel_connector->encoder;
2913 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2914
Jani Nikula742f4912015-09-03 11:16:09 +03002915 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002916}
2917
2918static void intel_lvds_info(struct seq_file *m,
2919 struct intel_connector *intel_connector)
2920{
2921 intel_panel_info(m, &intel_connector->panel);
2922}
2923
2924static void intel_connector_info(struct seq_file *m,
2925 struct drm_connector *connector)
2926{
2927 struct intel_connector *intel_connector = to_intel_connector(connector);
2928 struct intel_encoder *intel_encoder = intel_connector->encoder;
Jesse Barnesf103fc72014-02-20 12:39:57 -08002929 struct drm_display_mode *mode;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002930
2931 seq_printf(m, "connector %d: type %s, status: %s\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03002932 connector->base.id, connector->name,
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002933 drm_get_connector_status_name(connector->status));
2934 if (connector->status == connector_status_connected) {
2935 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2936 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2937 connector->display_info.width_mm,
2938 connector->display_info.height_mm);
2939 seq_printf(m, "\tsubpixel order: %s\n",
2940 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2941 seq_printf(m, "\tCEA rev: %d\n",
2942 connector->display_info.cea_rev);
2943 }
Maarten Lankhorstee648a72016-06-21 12:00:38 +02002944
Maarten Lankhorst77d1f612017-06-26 10:33:49 +02002945 if (!intel_encoder)
Maarten Lankhorstee648a72016-06-21 12:00:38 +02002946 return;
2947
2948 switch (connector->connector_type) {
2949 case DRM_MODE_CONNECTOR_DisplayPort:
2950 case DRM_MODE_CONNECTOR_eDP:
Libin Yang9a148a92016-11-28 20:07:05 +08002951 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2952 intel_dp_mst_info(m, intel_connector);
2953 else
2954 intel_dp_info(m, intel_connector);
Maarten Lankhorstee648a72016-06-21 12:00:38 +02002955 break;
2956 case DRM_MODE_CONNECTOR_LVDS:
2957 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
Dave Airlie36cd7442014-05-02 13:44:18 +10002958 intel_lvds_info(m, intel_connector);
Maarten Lankhorstee648a72016-06-21 12:00:38 +02002959 break;
2960 case DRM_MODE_CONNECTOR_HDMIA:
2961 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
Ville Syrjälä7e732ca2017-10-27 22:31:24 +03002962 intel_encoder->type == INTEL_OUTPUT_DDI)
Maarten Lankhorstee648a72016-06-21 12:00:38 +02002963 intel_hdmi_info(m, intel_connector);
2964 break;
2965 default:
2966 break;
Dave Airlie36cd7442014-05-02 13:44:18 +10002967 }
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002968
Jesse Barnesf103fc72014-02-20 12:39:57 -08002969 seq_printf(m, "\tmodes:\n");
2970 list_for_each_entry(mode, &connector->modes, head)
2971 intel_seq_print_mode(m, 2, mode);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002972}
2973
Robert Fekete3abc4e02015-10-27 16:58:32 +01002974static const char *plane_type(enum drm_plane_type type)
2975{
2976 switch (type) {
2977 case DRM_PLANE_TYPE_OVERLAY:
2978 return "OVL";
2979 case DRM_PLANE_TYPE_PRIMARY:
2980 return "PRI";
2981 case DRM_PLANE_TYPE_CURSOR:
2982 return "CUR";
2983 /*
2984 * Deliberately omitting default: to generate compiler warnings
2985 * when a new drm_plane_type gets added.
2986 */
2987 }
2988
2989 return "unknown";
2990}
2991
2992static const char *plane_rotation(unsigned int rotation)
2993{
2994 static char buf[48];
2995 /*
Robert Fossc2c446a2017-05-19 16:50:17 -04002996 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
Robert Fekete3abc4e02015-10-27 16:58:32 +01002997 * will print them all to visualize if the values are misused
2998 */
2999 snprintf(buf, sizeof(buf),
3000 "%s%s%s%s%s%s(0x%08x)",
Robert Fossc2c446a2017-05-19 16:50:17 -04003001 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3002 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3003 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3004 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3005 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3006 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
Robert Fekete3abc4e02015-10-27 16:58:32 +01003007 rotation);
3008
3009 return buf;
3010}
3011
3012static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3013{
David Weinehall36cdd012016-08-22 13:59:31 +03003014 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3015 struct drm_device *dev = &dev_priv->drm;
Robert Fekete3abc4e02015-10-27 16:58:32 +01003016 struct intel_plane *intel_plane;
3017
3018 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3019 struct drm_plane_state *state;
3020 struct drm_plane *plane = &intel_plane->base;
Eric Engestromb3c11ac2016-11-12 01:12:56 +00003021 struct drm_format_name_buf format_name;
Robert Fekete3abc4e02015-10-27 16:58:32 +01003022
3023 if (!plane->state) {
3024 seq_puts(m, "plane->state is NULL!\n");
3025 continue;
3026 }
3027
3028 state = plane->state;
3029
Eric Engestrom90844f02016-08-15 01:02:38 +01003030 if (state->fb) {
Ville Syrjälä438b74a2016-12-14 23:32:55 +02003031 drm_get_format_name(state->fb->format->format,
3032 &format_name);
Eric Engestrom90844f02016-08-15 01:02:38 +01003033 } else {
Eric Engestromb3c11ac2016-11-12 01:12:56 +00003034 sprintf(format_name.str, "N/A");
Eric Engestrom90844f02016-08-15 01:02:38 +01003035 }
3036
Robert Fekete3abc4e02015-10-27 16:58:32 +01003037 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3038 plane->base.id,
3039 plane_type(intel_plane->base.type),
3040 state->crtc_x, state->crtc_y,
3041 state->crtc_w, state->crtc_h,
3042 (state->src_x >> 16),
3043 ((state->src_x & 0xffff) * 15625) >> 10,
3044 (state->src_y >> 16),
3045 ((state->src_y & 0xffff) * 15625) >> 10,
3046 (state->src_w >> 16),
3047 ((state->src_w & 0xffff) * 15625) >> 10,
3048 (state->src_h >> 16),
3049 ((state->src_h & 0xffff) * 15625) >> 10,
Eric Engestromb3c11ac2016-11-12 01:12:56 +00003050 format_name.str,
Robert Fekete3abc4e02015-10-27 16:58:32 +01003051 plane_rotation(state->rotation));
3052 }
3053}
3054
3055static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3056{
3057 struct intel_crtc_state *pipe_config;
3058 int num_scalers = intel_crtc->num_scalers;
3059 int i;
3060
3061 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3062
3063 /* Not all platformas have a scaler */
3064 if (num_scalers) {
3065 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3066 num_scalers,
3067 pipe_config->scaler_state.scaler_users,
3068 pipe_config->scaler_state.scaler_id);
3069
A.Sunil Kamath58415912016-11-20 23:20:26 +05303070 for (i = 0; i < num_scalers; i++) {
Robert Fekete3abc4e02015-10-27 16:58:32 +01003071 struct intel_scaler *sc =
3072 &pipe_config->scaler_state.scalers[i];
3073
3074 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3075 i, yesno(sc->in_use), sc->mode);
3076 }
3077 seq_puts(m, "\n");
3078 } else {
3079 seq_puts(m, "\tNo scalers available on this platform\n");
3080 }
3081}
3082
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003083static int i915_display_info(struct seq_file *m, void *unused)
3084{
David Weinehall36cdd012016-08-22 13:59:31 +03003085 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3086 struct drm_device *dev = &dev_priv->drm;
Chris Wilson065f2ec2014-03-12 09:13:13 +00003087 struct intel_crtc *crtc;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003088 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003089 struct drm_connector_list_iter conn_iter;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003090
Paulo Zanonib0e5ddf2014-04-01 14:55:10 -03003091 intel_runtime_pm_get(dev_priv);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003092 seq_printf(m, "CRTC info\n");
3093 seq_printf(m, "---------\n");
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003094 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003095 struct intel_crtc_state *pipe_config;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003096
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003097 drm_modeset_lock(&crtc->base.mutex, NULL);
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003098 pipe_config = to_intel_crtc_state(crtc->base.state);
3099
Robert Fekete3abc4e02015-10-27 16:58:32 +01003100 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
Chris Wilson065f2ec2014-03-12 09:13:13 +00003101 crtc->base.base.id, pipe_name(crtc->pipe),
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003102 yesno(pipe_config->base.active),
Robert Fekete3abc4e02015-10-27 16:58:32 +01003103 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3104 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3105
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003106 if (pipe_config->base.active) {
Ville Syrjäläcd5dcbf2017-03-27 21:55:35 +03003107 struct intel_plane *cursor =
3108 to_intel_plane(crtc->base.cursor);
3109
Chris Wilson065f2ec2014-03-12 09:13:13 +00003110 intel_crtc_info(m, crtc);
3111
Ville Syrjäläcd5dcbf2017-03-27 21:55:35 +03003112 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3113 yesno(cursor->base.state->visible),
3114 cursor->base.state->crtc_x,
3115 cursor->base.state->crtc_y,
3116 cursor->base.state->crtc_w,
3117 cursor->base.state->crtc_h,
3118 cursor->cursor.base);
Robert Fekete3abc4e02015-10-27 16:58:32 +01003119 intel_scaler_info(m, crtc);
3120 intel_plane_info(m, crtc);
Paulo Zanonia23dc652014-04-01 14:55:11 -03003121 }
Daniel Vettercace8412014-05-22 17:56:31 +02003122
3123 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3124 yesno(!crtc->cpu_fifo_underrun_disabled),
3125 yesno(!crtc->pch_fifo_underrun_disabled));
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003126 drm_modeset_unlock(&crtc->base.mutex);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003127 }
3128
3129 seq_printf(m, "\n");
3130 seq_printf(m, "Connector info\n");
3131 seq_printf(m, "--------------\n");
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003132 mutex_lock(&dev->mode_config.mutex);
3133 drm_connector_list_iter_begin(dev, &conn_iter);
3134 drm_for_each_connector_iter(connector, &conn_iter)
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003135 intel_connector_info(m, connector);
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003136 drm_connector_list_iter_end(&conn_iter);
3137 mutex_unlock(&dev->mode_config.mutex);
3138
Paulo Zanonib0e5ddf2014-04-01 14:55:10 -03003139 intel_runtime_pm_put(dev_priv);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003140
3141 return 0;
3142}
3143
Chris Wilson1b365952016-10-04 21:11:31 +01003144static int i915_engine_info(struct seq_file *m, void *unused)
3145{
3146 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3147 struct intel_engine_cs *engine;
Akash Goel3b3f1652016-10-13 22:44:48 +05303148 enum intel_engine_id id;
Chris Wilsonf636edb2017-10-09 12:02:57 +01003149 struct drm_printer p;
Chris Wilson1b365952016-10-04 21:11:31 +01003150
Chris Wilson9c870d02016-10-24 13:42:15 +01003151 intel_runtime_pm_get(dev_priv);
3152
Chris Wilsonf73b5672017-03-02 15:03:56 +00003153 seq_printf(m, "GT awake? %s\n",
3154 yesno(dev_priv->gt.awake));
3155 seq_printf(m, "Global active requests: %d\n",
3156 dev_priv->gt.active_requests);
Lionel Landwerlinf577a032017-11-13 23:34:53 +00003157 seq_printf(m, "CS timestamp frequency: %u kHz\n",
3158 dev_priv->info.cs_timestamp_frequency_khz);
Chris Wilsonf73b5672017-03-02 15:03:56 +00003159
Chris Wilsonf636edb2017-10-09 12:02:57 +01003160 p = drm_seq_file_printer(m);
3161 for_each_engine(engine, dev_priv, id)
Chris Wilson0db18b12017-12-08 01:23:00 +00003162 intel_engine_dump(engine, &p, "%s\n", engine->name);
Chris Wilson1b365952016-10-04 21:11:31 +01003163
Chris Wilson9c870d02016-10-24 13:42:15 +01003164 intel_runtime_pm_put(dev_priv);
3165
Chris Wilson1b365952016-10-04 21:11:31 +01003166 return 0;
3167}
3168
Chris Wilsonc5418a82017-10-13 21:26:19 +01003169static int i915_shrinker_info(struct seq_file *m, void *unused)
3170{
3171 struct drm_i915_private *i915 = node_to_i915(m->private);
3172
3173 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3174 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3175
3176 return 0;
3177}
3178
Daniel Vetter728e29d2014-06-25 22:01:53 +03003179static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3180{
David Weinehall36cdd012016-08-22 13:59:31 +03003181 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3182 struct drm_device *dev = &dev_priv->drm;
Daniel Vetter728e29d2014-06-25 22:01:53 +03003183 int i;
3184
3185 drm_modeset_lock_all(dev);
3186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3187 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3188
3189 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
Maarten Lankhorst2dd66ebd2016-03-14 09:27:52 +01003190 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
Ander Conselvan de Oliveira2c42e532016-12-29 17:22:09 +02003191 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
Daniel Vetter728e29d2014-06-25 22:01:53 +03003192 seq_printf(m, " tracked hardware state:\n");
Ander Conselvan de Oliveira2c42e532016-12-29 17:22:09 +02003193 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003194 seq_printf(m, " dpll_md: 0x%08x\n",
Ander Conselvan de Oliveira2c42e532016-12-29 17:22:09 +02003195 pll->state.hw_state.dpll_md);
3196 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
3197 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
3198 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
Daniel Vetter728e29d2014-06-25 22:01:53 +03003199 }
3200 drm_modeset_unlock_all(dev);
3201
3202 return 0;
3203}
3204
Damien Lespiau1ed1ef92014-08-30 16:50:59 +01003205static int i915_wa_registers(struct seq_file *m, void *unused)
Arun Siluvery888b5992014-08-26 14:44:51 +01003206{
3207 int i;
3208 int ret;
Tvrtko Ursuline2f80392016-03-16 11:00:36 +00003209 struct intel_engine_cs *engine;
David Weinehall36cdd012016-08-22 13:59:31 +03003210 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3211 struct drm_device *dev = &dev_priv->drm;
Arun Siluvery33136b02016-01-21 21:43:47 +00003212 struct i915_workarounds *workarounds = &dev_priv->workarounds;
Dave Gordonc3232b12016-03-23 18:19:53 +00003213 enum intel_engine_id id;
Arun Siluvery888b5992014-08-26 14:44:51 +01003214
Arun Siluvery888b5992014-08-26 14:44:51 +01003215 ret = mutex_lock_interruptible(&dev->struct_mutex);
3216 if (ret)
3217 return ret;
3218
3219 intel_runtime_pm_get(dev_priv);
3220
Arun Siluvery33136b02016-01-21 21:43:47 +00003221 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
Akash Goel3b3f1652016-10-13 22:44:48 +05303222 for_each_engine(engine, dev_priv, id)
Arun Siluvery33136b02016-01-21 21:43:47 +00003223 seq_printf(m, "HW whitelist count for %s: %d\n",
Dave Gordonc3232b12016-03-23 18:19:53 +00003224 engine->name, workarounds->hw_whitelist_count[id]);
Arun Siluvery33136b02016-01-21 21:43:47 +00003225 for (i = 0; i < workarounds->count; ++i) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003226 i915_reg_t addr;
3227 u32 mask, value, read;
Mika Kuoppala2fa60f62014-10-07 17:21:27 +03003228 bool ok;
Arun Siluvery888b5992014-08-26 14:44:51 +01003229
Arun Siluvery33136b02016-01-21 21:43:47 +00003230 addr = workarounds->reg[i].addr;
3231 mask = workarounds->reg[i].mask;
3232 value = workarounds->reg[i].value;
Mika Kuoppala2fa60f62014-10-07 17:21:27 +03003233 read = I915_READ(addr);
3234 ok = (value & mask) == (read & mask);
3235 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003236 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
Arun Siluvery888b5992014-08-26 14:44:51 +01003237 }
3238
3239 intel_runtime_pm_put(dev_priv);
3240 mutex_unlock(&dev->struct_mutex);
3241
3242 return 0;
3243}
3244
Kumar, Maheshd2d4f392017-08-17 19:15:29 +05303245static int i915_ipc_status_show(struct seq_file *m, void *data)
3246{
3247 struct drm_i915_private *dev_priv = m->private;
3248
3249 seq_printf(m, "Isochronous Priority Control: %s\n",
3250 yesno(dev_priv->ipc_enabled));
3251 return 0;
3252}
3253
3254static int i915_ipc_status_open(struct inode *inode, struct file *file)
3255{
3256 struct drm_i915_private *dev_priv = inode->i_private;
3257
3258 if (!HAS_IPC(dev_priv))
3259 return -ENODEV;
3260
3261 return single_open(file, i915_ipc_status_show, dev_priv);
3262}
3263
3264static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3265 size_t len, loff_t *offp)
3266{
3267 struct seq_file *m = file->private_data;
3268 struct drm_i915_private *dev_priv = m->private;
3269 int ret;
3270 bool enable;
3271
3272 ret = kstrtobool_from_user(ubuf, len, &enable);
3273 if (ret < 0)
3274 return ret;
3275
3276 intel_runtime_pm_get(dev_priv);
3277 if (!dev_priv->ipc_enabled && enable)
3278 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3279 dev_priv->wm.distrust_bios_wm = true;
3280 dev_priv->ipc_enabled = enable;
3281 intel_enable_ipc(dev_priv);
3282 intel_runtime_pm_put(dev_priv);
3283
3284 return len;
3285}
3286
3287static const struct file_operations i915_ipc_status_fops = {
3288 .owner = THIS_MODULE,
3289 .open = i915_ipc_status_open,
3290 .read = seq_read,
3291 .llseek = seq_lseek,
3292 .release = single_release,
3293 .write = i915_ipc_status_write
3294};
3295
Damien Lespiauc5511e42014-11-04 17:06:51 +00003296static int i915_ddb_info(struct seq_file *m, void *unused)
3297{
David Weinehall36cdd012016-08-22 13:59:31 +03003298 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3299 struct drm_device *dev = &dev_priv->drm;
Damien Lespiauc5511e42014-11-04 17:06:51 +00003300 struct skl_ddb_allocation *ddb;
3301 struct skl_ddb_entry *entry;
3302 enum pipe pipe;
3303 int plane;
3304
David Weinehall36cdd012016-08-22 13:59:31 +03003305 if (INTEL_GEN(dev_priv) < 9)
Michal Wajdeczkoab309a62017-12-15 14:36:35 +00003306 return -ENODEV;
Damien Lespiau2fcffe12014-12-03 17:33:24 +00003307
Damien Lespiauc5511e42014-11-04 17:06:51 +00003308 drm_modeset_lock_all(dev);
3309
3310 ddb = &dev_priv->wm.skl_hw.ddb;
3311
3312 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3313
3314 for_each_pipe(dev_priv, pipe) {
3315 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3316
Matt Roper8b364b42016-10-26 15:51:28 -07003317 for_each_universal_plane(dev_priv, pipe, plane) {
Damien Lespiauc5511e42014-11-04 17:06:51 +00003318 entry = &ddb->plane[pipe][plane];
3319 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3320 entry->start, entry->end,
3321 skl_ddb_entry_size(entry));
3322 }
3323
Matt Roper4969d332015-09-24 15:53:10 -07003324 entry = &ddb->plane[pipe][PLANE_CURSOR];
Damien Lespiauc5511e42014-11-04 17:06:51 +00003325 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3326 entry->end, skl_ddb_entry_size(entry));
3327 }
3328
3329 drm_modeset_unlock_all(dev);
3330
3331 return 0;
3332}
3333
Vandana Kannana54746e2015-03-03 20:53:10 +05303334static void drrs_status_per_crtc(struct seq_file *m,
David Weinehall36cdd012016-08-22 13:59:31 +03003335 struct drm_device *dev,
3336 struct intel_crtc *intel_crtc)
Vandana Kannana54746e2015-03-03 20:53:10 +05303337{
Chris Wilsonfac5e232016-07-04 11:34:36 +01003338 struct drm_i915_private *dev_priv = to_i915(dev);
Vandana Kannana54746e2015-03-03 20:53:10 +05303339 struct i915_drrs *drrs = &dev_priv->drrs;
3340 int vrefresh = 0;
Maarten Lankhorst26875fe2016-06-20 15:57:36 +02003341 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003342 struct drm_connector_list_iter conn_iter;
Vandana Kannana54746e2015-03-03 20:53:10 +05303343
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003344 drm_connector_list_iter_begin(dev, &conn_iter);
3345 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorst26875fe2016-06-20 15:57:36 +02003346 if (connector->state->crtc != &intel_crtc->base)
3347 continue;
3348
3349 seq_printf(m, "%s:\n", connector->name);
Vandana Kannana54746e2015-03-03 20:53:10 +05303350 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003351 drm_connector_list_iter_end(&conn_iter);
Vandana Kannana54746e2015-03-03 20:53:10 +05303352
3353 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3354 seq_puts(m, "\tVBT: DRRS_type: Static");
3355 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3356 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3357 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3358 seq_puts(m, "\tVBT: DRRS_type: None");
3359 else
3360 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3361
3362 seq_puts(m, "\n\n");
3363
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003364 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
Vandana Kannana54746e2015-03-03 20:53:10 +05303365 struct intel_panel *panel;
3366
3367 mutex_lock(&drrs->mutex);
3368 /* DRRS Supported */
3369 seq_puts(m, "\tDRRS Supported: Yes\n");
3370
3371 /* disable_drrs() will make drrs->dp NULL */
3372 if (!drrs->dp) {
C, Ramalingamce6e2132017-11-20 09:53:47 +05303373 seq_puts(m, "Idleness DRRS: Disabled\n");
3374 if (dev_priv->psr.enabled)
3375 seq_puts(m,
3376 "\tAs PSR is enabled, DRRS is not enabled\n");
Vandana Kannana54746e2015-03-03 20:53:10 +05303377 mutex_unlock(&drrs->mutex);
3378 return;
3379 }
3380
3381 panel = &drrs->dp->attached_connector->panel;
3382 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3383 drrs->busy_frontbuffer_bits);
3384
3385 seq_puts(m, "\n\t\t");
3386 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3387 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3388 vrefresh = panel->fixed_mode->vrefresh;
3389 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3390 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3391 vrefresh = panel->downclock_mode->vrefresh;
3392 } else {
3393 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3394 drrs->refresh_rate_type);
3395 mutex_unlock(&drrs->mutex);
3396 return;
3397 }
3398 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3399
3400 seq_puts(m, "\n\t\t");
3401 mutex_unlock(&drrs->mutex);
3402 } else {
3403 /* DRRS not supported. Print the VBT parameter*/
3404 seq_puts(m, "\tDRRS Supported : No");
3405 }
3406 seq_puts(m, "\n");
3407}
3408
3409static int i915_drrs_status(struct seq_file *m, void *unused)
3410{
David Weinehall36cdd012016-08-22 13:59:31 +03003411 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3412 struct drm_device *dev = &dev_priv->drm;
Vandana Kannana54746e2015-03-03 20:53:10 +05303413 struct intel_crtc *intel_crtc;
3414 int active_crtc_cnt = 0;
3415
Maarten Lankhorst26875fe2016-06-20 15:57:36 +02003416 drm_modeset_lock_all(dev);
Vandana Kannana54746e2015-03-03 20:53:10 +05303417 for_each_intel_crtc(dev, intel_crtc) {
Maarten Lankhorstf77076c2015-06-01 12:50:08 +02003418 if (intel_crtc->base.state->active) {
Vandana Kannana54746e2015-03-03 20:53:10 +05303419 active_crtc_cnt++;
3420 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3421
3422 drrs_status_per_crtc(m, dev, intel_crtc);
3423 }
Vandana Kannana54746e2015-03-03 20:53:10 +05303424 }
Maarten Lankhorst26875fe2016-06-20 15:57:36 +02003425 drm_modeset_unlock_all(dev);
Vandana Kannana54746e2015-03-03 20:53:10 +05303426
3427 if (!active_crtc_cnt)
3428 seq_puts(m, "No active crtc found\n");
3429
3430 return 0;
3431}
3432
Dave Airlie11bed952014-05-12 15:22:27 +10003433static int i915_dp_mst_info(struct seq_file *m, void *unused)
3434{
David Weinehall36cdd012016-08-22 13:59:31 +03003435 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3436 struct drm_device *dev = &dev_priv->drm;
Dave Airlie11bed952014-05-12 15:22:27 +10003437 struct intel_encoder *intel_encoder;
3438 struct intel_digital_port *intel_dig_port;
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02003439 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003440 struct drm_connector_list_iter conn_iter;
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02003441
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003442 drm_connector_list_iter_begin(dev, &conn_iter);
3443 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02003444 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
Dave Airlie11bed952014-05-12 15:22:27 +10003445 continue;
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02003446
3447 intel_encoder = intel_attached_encoder(connector);
3448 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3449 continue;
3450
3451 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlie11bed952014-05-12 15:22:27 +10003452 if (!intel_dig_port->dp.can_mst)
3453 continue;
Maarten Lankhorstb6dabe32016-06-20 15:57:37 +02003454
Jim Bride40ae80c2016-04-14 10:18:37 -07003455 seq_printf(m, "MST Source Port %c\n",
Ville Syrjälä8f4f2792017-11-09 17:24:34 +02003456 port_name(intel_dig_port->base.port));
Dave Airlie11bed952014-05-12 15:22:27 +10003457 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3458 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003459 drm_connector_list_iter_end(&conn_iter);
3460
Dave Airlie11bed952014-05-12 15:22:27 +10003461 return 0;
3462}
3463
Todd Previteeb3394fa2015-04-18 00:04:19 -07003464static ssize_t i915_displayport_test_active_write(struct file *file,
David Weinehall36cdd012016-08-22 13:59:31 +03003465 const char __user *ubuf,
3466 size_t len, loff_t *offp)
Todd Previteeb3394fa2015-04-18 00:04:19 -07003467{
3468 char *input_buffer;
3469 int status = 0;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003470 struct drm_device *dev;
3471 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003472 struct drm_connector_list_iter conn_iter;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003473 struct intel_dp *intel_dp;
3474 int val = 0;
3475
Sudip Mukherjee9aaffa32015-07-21 17:36:45 +05303476 dev = ((struct seq_file *)file->private_data)->private;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003477
Todd Previteeb3394fa2015-04-18 00:04:19 -07003478 if (len == 0)
3479 return 0;
3480
Geliang Tang261aeba2017-05-06 23:40:17 +08003481 input_buffer = memdup_user_nul(ubuf, len);
3482 if (IS_ERR(input_buffer))
3483 return PTR_ERR(input_buffer);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003484
Todd Previteeb3394fa2015-04-18 00:04:19 -07003485 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3486
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003487 drm_connector_list_iter_begin(dev, &conn_iter);
3488 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003489 struct intel_encoder *encoder;
3490
Todd Previteeb3394fa2015-04-18 00:04:19 -07003491 if (connector->connector_type !=
3492 DRM_MODE_CONNECTOR_DisplayPort)
3493 continue;
3494
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003495 encoder = to_intel_encoder(connector->encoder);
3496 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3497 continue;
3498
3499 if (encoder && connector->status == connector_status_connected) {
3500 intel_dp = enc_to_intel_dp(&encoder->base);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003501 status = kstrtoint(input_buffer, 10, &val);
3502 if (status < 0)
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003503 break;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003504 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3505 /* To prevent erroneous activation of the compliance
3506 * testing code, only accept an actual value of 1 here
3507 */
3508 if (val == 1)
Manasi Navarec1617ab2016-12-09 16:22:50 -08003509 intel_dp->compliance.test_active = 1;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003510 else
Manasi Navarec1617ab2016-12-09 16:22:50 -08003511 intel_dp->compliance.test_active = 0;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003512 }
3513 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003514 drm_connector_list_iter_end(&conn_iter);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003515 kfree(input_buffer);
3516 if (status < 0)
3517 return status;
3518
3519 *offp += len;
3520 return len;
3521}
3522
3523static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3524{
3525 struct drm_device *dev = m->private;
3526 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003527 struct drm_connector_list_iter conn_iter;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003528 struct intel_dp *intel_dp;
3529
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003530 drm_connector_list_iter_begin(dev, &conn_iter);
3531 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003532 struct intel_encoder *encoder;
3533
Todd Previteeb3394fa2015-04-18 00:04:19 -07003534 if (connector->connector_type !=
3535 DRM_MODE_CONNECTOR_DisplayPort)
3536 continue;
3537
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003538 encoder = to_intel_encoder(connector->encoder);
3539 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3540 continue;
3541
3542 if (encoder && connector->status == connector_status_connected) {
3543 intel_dp = enc_to_intel_dp(&encoder->base);
Manasi Navarec1617ab2016-12-09 16:22:50 -08003544 if (intel_dp->compliance.test_active)
Todd Previteeb3394fa2015-04-18 00:04:19 -07003545 seq_puts(m, "1");
3546 else
3547 seq_puts(m, "0");
3548 } else
3549 seq_puts(m, "0");
3550 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003551 drm_connector_list_iter_end(&conn_iter);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003552
3553 return 0;
3554}
3555
3556static int i915_displayport_test_active_open(struct inode *inode,
David Weinehall36cdd012016-08-22 13:59:31 +03003557 struct file *file)
Todd Previteeb3394fa2015-04-18 00:04:19 -07003558{
David Weinehall36cdd012016-08-22 13:59:31 +03003559 struct drm_i915_private *dev_priv = inode->i_private;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003560
David Weinehall36cdd012016-08-22 13:59:31 +03003561 return single_open(file, i915_displayport_test_active_show,
3562 &dev_priv->drm);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003563}
3564
3565static const struct file_operations i915_displayport_test_active_fops = {
3566 .owner = THIS_MODULE,
3567 .open = i915_displayport_test_active_open,
3568 .read = seq_read,
3569 .llseek = seq_lseek,
3570 .release = single_release,
3571 .write = i915_displayport_test_active_write
3572};
3573
3574static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3575{
3576 struct drm_device *dev = m->private;
3577 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003578 struct drm_connector_list_iter conn_iter;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003579 struct intel_dp *intel_dp;
3580
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003581 drm_connector_list_iter_begin(dev, &conn_iter);
3582 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003583 struct intel_encoder *encoder;
3584
Todd Previteeb3394fa2015-04-18 00:04:19 -07003585 if (connector->connector_type !=
3586 DRM_MODE_CONNECTOR_DisplayPort)
3587 continue;
3588
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003589 encoder = to_intel_encoder(connector->encoder);
3590 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3591 continue;
3592
3593 if (encoder && connector->status == connector_status_connected) {
3594 intel_dp = enc_to_intel_dp(&encoder->base);
Manasi Navareb48a5ba2017-01-20 19:09:28 -08003595 if (intel_dp->compliance.test_type ==
3596 DP_TEST_LINK_EDID_READ)
3597 seq_printf(m, "%lx",
3598 intel_dp->compliance.test_data.edid);
Manasi Navare611032b2017-01-24 08:21:49 -08003599 else if (intel_dp->compliance.test_type ==
3600 DP_TEST_LINK_VIDEO_PATTERN) {
3601 seq_printf(m, "hdisplay: %d\n",
3602 intel_dp->compliance.test_data.hdisplay);
3603 seq_printf(m, "vdisplay: %d\n",
3604 intel_dp->compliance.test_data.vdisplay);
3605 seq_printf(m, "bpc: %u\n",
3606 intel_dp->compliance.test_data.bpc);
3607 }
Todd Previteeb3394fa2015-04-18 00:04:19 -07003608 } else
3609 seq_puts(m, "0");
3610 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003611 drm_connector_list_iter_end(&conn_iter);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003612
3613 return 0;
3614}
3615static int i915_displayport_test_data_open(struct inode *inode,
David Weinehall36cdd012016-08-22 13:59:31 +03003616 struct file *file)
Todd Previteeb3394fa2015-04-18 00:04:19 -07003617{
David Weinehall36cdd012016-08-22 13:59:31 +03003618 struct drm_i915_private *dev_priv = inode->i_private;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003619
David Weinehall36cdd012016-08-22 13:59:31 +03003620 return single_open(file, i915_displayport_test_data_show,
3621 &dev_priv->drm);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003622}
3623
3624static const struct file_operations i915_displayport_test_data_fops = {
3625 .owner = THIS_MODULE,
3626 .open = i915_displayport_test_data_open,
3627 .read = seq_read,
3628 .llseek = seq_lseek,
3629 .release = single_release
3630};
3631
3632static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3633{
3634 struct drm_device *dev = m->private;
3635 struct drm_connector *connector;
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003636 struct drm_connector_list_iter conn_iter;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003637 struct intel_dp *intel_dp;
3638
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003639 drm_connector_list_iter_begin(dev, &conn_iter);
3640 drm_for_each_connector_iter(connector, &conn_iter) {
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003641 struct intel_encoder *encoder;
3642
Todd Previteeb3394fa2015-04-18 00:04:19 -07003643 if (connector->connector_type !=
3644 DRM_MODE_CONNECTOR_DisplayPort)
3645 continue;
3646
Maarten Lankhorsta874b6a2017-06-26 10:18:35 +02003647 encoder = to_intel_encoder(connector->encoder);
3648 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3649 continue;
3650
3651 if (encoder && connector->status == connector_status_connected) {
3652 intel_dp = enc_to_intel_dp(&encoder->base);
Manasi Navarec1617ab2016-12-09 16:22:50 -08003653 seq_printf(m, "%02lx", intel_dp->compliance.test_type);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003654 } else
3655 seq_puts(m, "0");
3656 }
Daniel Vetter3f6a5e12017-03-01 10:52:21 +01003657 drm_connector_list_iter_end(&conn_iter);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003658
3659 return 0;
3660}
3661
3662static int i915_displayport_test_type_open(struct inode *inode,
3663 struct file *file)
3664{
David Weinehall36cdd012016-08-22 13:59:31 +03003665 struct drm_i915_private *dev_priv = inode->i_private;
Todd Previteeb3394fa2015-04-18 00:04:19 -07003666
David Weinehall36cdd012016-08-22 13:59:31 +03003667 return single_open(file, i915_displayport_test_type_show,
3668 &dev_priv->drm);
Todd Previteeb3394fa2015-04-18 00:04:19 -07003669}
3670
3671static const struct file_operations i915_displayport_test_type_fops = {
3672 .owner = THIS_MODULE,
3673 .open = i915_displayport_test_type_open,
3674 .read = seq_read,
3675 .llseek = seq_lseek,
3676 .release = single_release
3677};
3678
Damien Lespiau97e94b22014-11-04 17:06:50 +00003679static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
Ville Syrjälä369a1342014-01-22 14:36:08 +02003680{
David Weinehall36cdd012016-08-22 13:59:31 +03003681 struct drm_i915_private *dev_priv = m->private;
3682 struct drm_device *dev = &dev_priv->drm;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003683 int level;
Ville Syrjäläde38b952015-06-24 22:00:09 +03003684 int num_levels;
3685
David Weinehall36cdd012016-08-22 13:59:31 +03003686 if (IS_CHERRYVIEW(dev_priv))
Ville Syrjäläde38b952015-06-24 22:00:09 +03003687 num_levels = 3;
David Weinehall36cdd012016-08-22 13:59:31 +03003688 else if (IS_VALLEYVIEW(dev_priv))
Ville Syrjäläde38b952015-06-24 22:00:09 +03003689 num_levels = 1;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03003690 else if (IS_G4X(dev_priv))
3691 num_levels = 3;
Ville Syrjäläde38b952015-06-24 22:00:09 +03003692 else
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003693 num_levels = ilk_wm_max_level(dev_priv) + 1;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003694
3695 drm_modeset_lock_all(dev);
3696
3697 for (level = 0; level < num_levels; level++) {
3698 unsigned int latency = wm[level];
3699
Damien Lespiau97e94b22014-11-04 17:06:50 +00003700 /*
3701 * - WM1+ latency values in 0.5us units
Ville Syrjäläde38b952015-06-24 22:00:09 +03003702 * - latencies are in us on gen9/vlv/chv
Damien Lespiau97e94b22014-11-04 17:06:50 +00003703 */
Ville Syrjälä04548cb2017-04-21 21:14:29 +03003704 if (INTEL_GEN(dev_priv) >= 9 ||
3705 IS_VALLEYVIEW(dev_priv) ||
3706 IS_CHERRYVIEW(dev_priv) ||
3707 IS_G4X(dev_priv))
Damien Lespiau97e94b22014-11-04 17:06:50 +00003708 latency *= 10;
3709 else if (level > 0)
Ville Syrjälä369a1342014-01-22 14:36:08 +02003710 latency *= 5;
3711
3712 seq_printf(m, "WM%d %u (%u.%u usec)\n",
Damien Lespiau97e94b22014-11-04 17:06:50 +00003713 level, wm[level], latency / 10, latency % 10);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003714 }
3715
3716 drm_modeset_unlock_all(dev);
3717}
3718
3719static int pri_wm_latency_show(struct seq_file *m, void *data)
3720{
David Weinehall36cdd012016-08-22 13:59:31 +03003721 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003722 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003723
David Weinehall36cdd012016-08-22 13:59:31 +03003724 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003725 latencies = dev_priv->wm.skl_latency;
3726 else
David Weinehall36cdd012016-08-22 13:59:31 +03003727 latencies = dev_priv->wm.pri_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003728
3729 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003730
3731 return 0;
3732}
3733
3734static int spr_wm_latency_show(struct seq_file *m, void *data)
3735{
David Weinehall36cdd012016-08-22 13:59:31 +03003736 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003737 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003738
David Weinehall36cdd012016-08-22 13:59:31 +03003739 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003740 latencies = dev_priv->wm.skl_latency;
3741 else
David Weinehall36cdd012016-08-22 13:59:31 +03003742 latencies = dev_priv->wm.spr_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003743
3744 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003745
3746 return 0;
3747}
3748
3749static int cur_wm_latency_show(struct seq_file *m, void *data)
3750{
David Weinehall36cdd012016-08-22 13:59:31 +03003751 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003752 const uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003753
David Weinehall36cdd012016-08-22 13:59:31 +03003754 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003755 latencies = dev_priv->wm.skl_latency;
3756 else
David Weinehall36cdd012016-08-22 13:59:31 +03003757 latencies = dev_priv->wm.cur_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003758
3759 wm_latency_show(m, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003760
3761 return 0;
3762}
3763
3764static int pri_wm_latency_open(struct inode *inode, struct file *file)
3765{
David Weinehall36cdd012016-08-22 13:59:31 +03003766 struct drm_i915_private *dev_priv = inode->i_private;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003767
Ville Syrjälä04548cb2017-04-21 21:14:29 +03003768 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003769 return -ENODEV;
3770
David Weinehall36cdd012016-08-22 13:59:31 +03003771 return single_open(file, pri_wm_latency_show, dev_priv);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003772}
3773
3774static int spr_wm_latency_open(struct inode *inode, struct file *file)
3775{
David Weinehall36cdd012016-08-22 13:59:31 +03003776 struct drm_i915_private *dev_priv = inode->i_private;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003777
David Weinehall36cdd012016-08-22 13:59:31 +03003778 if (HAS_GMCH_DISPLAY(dev_priv))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003779 return -ENODEV;
3780
David Weinehall36cdd012016-08-22 13:59:31 +03003781 return single_open(file, spr_wm_latency_show, dev_priv);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003782}
3783
3784static int cur_wm_latency_open(struct inode *inode, struct file *file)
3785{
David Weinehall36cdd012016-08-22 13:59:31 +03003786 struct drm_i915_private *dev_priv = inode->i_private;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003787
David Weinehall36cdd012016-08-22 13:59:31 +03003788 if (HAS_GMCH_DISPLAY(dev_priv))
Ville Syrjälä369a1342014-01-22 14:36:08 +02003789 return -ENODEV;
3790
David Weinehall36cdd012016-08-22 13:59:31 +03003791 return single_open(file, cur_wm_latency_show, dev_priv);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003792}
3793
3794static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
Damien Lespiau97e94b22014-11-04 17:06:50 +00003795 size_t len, loff_t *offp, uint16_t wm[8])
Ville Syrjälä369a1342014-01-22 14:36:08 +02003796{
3797 struct seq_file *m = file->private_data;
David Weinehall36cdd012016-08-22 13:59:31 +03003798 struct drm_i915_private *dev_priv = m->private;
3799 struct drm_device *dev = &dev_priv->drm;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003800 uint16_t new[8] = { 0 };
Ville Syrjäläde38b952015-06-24 22:00:09 +03003801 int num_levels;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003802 int level;
3803 int ret;
3804 char tmp[32];
3805
David Weinehall36cdd012016-08-22 13:59:31 +03003806 if (IS_CHERRYVIEW(dev_priv))
Ville Syrjäläde38b952015-06-24 22:00:09 +03003807 num_levels = 3;
David Weinehall36cdd012016-08-22 13:59:31 +03003808 else if (IS_VALLEYVIEW(dev_priv))
Ville Syrjäläde38b952015-06-24 22:00:09 +03003809 num_levels = 1;
Ville Syrjälä04548cb2017-04-21 21:14:29 +03003810 else if (IS_G4X(dev_priv))
3811 num_levels = 3;
Ville Syrjäläde38b952015-06-24 22:00:09 +03003812 else
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01003813 num_levels = ilk_wm_max_level(dev_priv) + 1;
Ville Syrjäläde38b952015-06-24 22:00:09 +03003814
Ville Syrjälä369a1342014-01-22 14:36:08 +02003815 if (len >= sizeof(tmp))
3816 return -EINVAL;
3817
3818 if (copy_from_user(tmp, ubuf, len))
3819 return -EFAULT;
3820
3821 tmp[len] = '\0';
3822
Damien Lespiau97e94b22014-11-04 17:06:50 +00003823 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3824 &new[0], &new[1], &new[2], &new[3],
3825 &new[4], &new[5], &new[6], &new[7]);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003826 if (ret != num_levels)
3827 return -EINVAL;
3828
3829 drm_modeset_lock_all(dev);
3830
3831 for (level = 0; level < num_levels; level++)
3832 wm[level] = new[level];
3833
3834 drm_modeset_unlock_all(dev);
3835
3836 return len;
3837}
3838
3839
3840static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3841 size_t len, loff_t *offp)
3842{
3843 struct seq_file *m = file->private_data;
David Weinehall36cdd012016-08-22 13:59:31 +03003844 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003845 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003846
David Weinehall36cdd012016-08-22 13:59:31 +03003847 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003848 latencies = dev_priv->wm.skl_latency;
3849 else
David Weinehall36cdd012016-08-22 13:59:31 +03003850 latencies = dev_priv->wm.pri_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003851
3852 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003853}
3854
3855static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3856 size_t len, loff_t *offp)
3857{
3858 struct seq_file *m = file->private_data;
David Weinehall36cdd012016-08-22 13:59:31 +03003859 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003860 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003861
David Weinehall36cdd012016-08-22 13:59:31 +03003862 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003863 latencies = dev_priv->wm.skl_latency;
3864 else
David Weinehall36cdd012016-08-22 13:59:31 +03003865 latencies = dev_priv->wm.spr_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003866
3867 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003868}
3869
3870static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3871 size_t len, loff_t *offp)
3872{
3873 struct seq_file *m = file->private_data;
David Weinehall36cdd012016-08-22 13:59:31 +03003874 struct drm_i915_private *dev_priv = m->private;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003875 uint16_t *latencies;
Ville Syrjälä369a1342014-01-22 14:36:08 +02003876
David Weinehall36cdd012016-08-22 13:59:31 +03003877 if (INTEL_GEN(dev_priv) >= 9)
Damien Lespiau97e94b22014-11-04 17:06:50 +00003878 latencies = dev_priv->wm.skl_latency;
3879 else
David Weinehall36cdd012016-08-22 13:59:31 +03003880 latencies = dev_priv->wm.cur_latency;
Damien Lespiau97e94b22014-11-04 17:06:50 +00003881
3882 return wm_latency_write(file, ubuf, len, offp, latencies);
Ville Syrjälä369a1342014-01-22 14:36:08 +02003883}
3884
3885static const struct file_operations i915_pri_wm_latency_fops = {
3886 .owner = THIS_MODULE,
3887 .open = pri_wm_latency_open,
3888 .read = seq_read,
3889 .llseek = seq_lseek,
3890 .release = single_release,
3891 .write = pri_wm_latency_write
3892};
3893
3894static const struct file_operations i915_spr_wm_latency_fops = {
3895 .owner = THIS_MODULE,
3896 .open = spr_wm_latency_open,
3897 .read = seq_read,
3898 .llseek = seq_lseek,
3899 .release = single_release,
3900 .write = spr_wm_latency_write
3901};
3902
3903static const struct file_operations i915_cur_wm_latency_fops = {
3904 .owner = THIS_MODULE,
3905 .open = cur_wm_latency_open,
3906 .read = seq_read,
3907 .llseek = seq_lseek,
3908 .release = single_release,
3909 .write = cur_wm_latency_write
3910};
3911
Kees Cook647416f2013-03-10 14:10:06 -07003912static int
3913i915_wedged_get(void *data, u64 *val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003914{
David Weinehall36cdd012016-08-22 13:59:31 +03003915 struct drm_i915_private *dev_priv = data;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003916
Chris Wilsond98c52c2016-04-13 17:35:05 +01003917 *val = i915_terminally_wedged(&dev_priv->gpu_error);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003918
Kees Cook647416f2013-03-10 14:10:06 -07003919 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003920}
3921
Kees Cook647416f2013-03-10 14:10:06 -07003922static int
3923i915_wedged_set(void *data, u64 val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003924{
Chris Wilson598b6b52017-03-25 13:47:35 +00003925 struct drm_i915_private *i915 = data;
3926 struct intel_engine_cs *engine;
3927 unsigned int tmp;
Imre Deakd46c0512014-04-14 20:24:27 +03003928
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02003929 /*
3930 * There is no safeguard against this debugfs entry colliding
3931 * with the hangcheck calling same i915_handle_error() in
3932 * parallel, causing an explosion. For now we assume that the
3933 * test harness is responsible enough not to inject gpu hangs
3934 * while it is writing to 'i915_wedged'
3935 */
3936
Chris Wilson598b6b52017-03-25 13:47:35 +00003937 if (i915_reset_backoff(&i915->gpu_error))
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02003938 return -EAGAIN;
3939
Chris Wilson598b6b52017-03-25 13:47:35 +00003940 for_each_engine_masked(engine, i915, val, tmp) {
3941 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
3942 engine->hangcheck.stalled = true;
3943 }
Imre Deakd46c0512014-04-14 20:24:27 +03003944
Chris Wilson598b6b52017-03-25 13:47:35 +00003945 i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
3946
3947 wait_on_bit(&i915->gpu_error.flags,
Chris Wilsond3df42b2017-03-16 17:13:05 +00003948 I915_RESET_HANDOFF,
3949 TASK_UNINTERRUPTIBLE);
3950
Kees Cook647416f2013-03-10 14:10:06 -07003951 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003952}
3953
Kees Cook647416f2013-03-10 14:10:06 -07003954DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3955 i915_wedged_get, i915_wedged_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03003956 "%llu\n");
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003957
Kees Cook647416f2013-03-10 14:10:06 -07003958static int
Chris Wilson64486ae2017-03-07 15:59:08 +00003959fault_irq_set(struct drm_i915_private *i915,
3960 unsigned long *irq,
3961 unsigned long val)
3962{
3963 int err;
3964
3965 err = mutex_lock_interruptible(&i915->drm.struct_mutex);
3966 if (err)
3967 return err;
3968
3969 err = i915_gem_wait_for_idle(i915,
3970 I915_WAIT_LOCKED |
3971 I915_WAIT_INTERRUPTIBLE);
3972 if (err)
3973 goto err_unlock;
3974
Chris Wilson64486ae2017-03-07 15:59:08 +00003975 *irq = val;
3976 mutex_unlock(&i915->drm.struct_mutex);
3977
3978 /* Flush idle worker to disarm irq */
Chris Wilson7c262402017-10-06 11:40:38 +01003979 drain_delayed_work(&i915->gt.idle_work);
Chris Wilson64486ae2017-03-07 15:59:08 +00003980
3981 return 0;
3982
3983err_unlock:
3984 mutex_unlock(&i915->drm.struct_mutex);
3985 return err;
3986}
3987
3988static int
Chris Wilson094f9a52013-09-25 17:34:55 +01003989i915_ring_missed_irq_get(void *data, u64 *val)
3990{
David Weinehall36cdd012016-08-22 13:59:31 +03003991 struct drm_i915_private *dev_priv = data;
Chris Wilson094f9a52013-09-25 17:34:55 +01003992
3993 *val = dev_priv->gpu_error.missed_irq_rings;
3994 return 0;
3995}
3996
3997static int
3998i915_ring_missed_irq_set(void *data, u64 val)
3999{
Chris Wilson64486ae2017-03-07 15:59:08 +00004000 struct drm_i915_private *i915 = data;
Chris Wilson094f9a52013-09-25 17:34:55 +01004001
Chris Wilson64486ae2017-03-07 15:59:08 +00004002 return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
Chris Wilson094f9a52013-09-25 17:34:55 +01004003}
4004
4005DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4006 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4007 "0x%08llx\n");
4008
4009static int
4010i915_ring_test_irq_get(void *data, u64 *val)
4011{
David Weinehall36cdd012016-08-22 13:59:31 +03004012 struct drm_i915_private *dev_priv = data;
Chris Wilson094f9a52013-09-25 17:34:55 +01004013
4014 *val = dev_priv->gpu_error.test_irq_rings;
4015
4016 return 0;
4017}
4018
4019static int
4020i915_ring_test_irq_set(void *data, u64 val)
4021{
Chris Wilson64486ae2017-03-07 15:59:08 +00004022 struct drm_i915_private *i915 = data;
Chris Wilson094f9a52013-09-25 17:34:55 +01004023
Chris Wilson64486ae2017-03-07 15:59:08 +00004024 val &= INTEL_INFO(i915)->ring_mask;
Chris Wilson094f9a52013-09-25 17:34:55 +01004025 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
Chris Wilson094f9a52013-09-25 17:34:55 +01004026
Chris Wilson64486ae2017-03-07 15:59:08 +00004027 return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
Chris Wilson094f9a52013-09-25 17:34:55 +01004028}
4029
4030DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4031 i915_ring_test_irq_get, i915_ring_test_irq_set,
4032 "0x%08llx\n");
4033
Chris Wilsonb4a0b322017-10-18 13:16:21 +01004034#define DROP_UNBOUND BIT(0)
4035#define DROP_BOUND BIT(1)
4036#define DROP_RETIRE BIT(2)
4037#define DROP_ACTIVE BIT(3)
4038#define DROP_FREED BIT(4)
4039#define DROP_SHRINK_ALL BIT(5)
4040#define DROP_IDLE BIT(6)
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01004041#define DROP_ALL (DROP_UNBOUND | \
4042 DROP_BOUND | \
4043 DROP_RETIRE | \
4044 DROP_ACTIVE | \
Chris Wilson8eadc192017-03-08 14:46:22 +00004045 DROP_FREED | \
Chris Wilsonb4a0b322017-10-18 13:16:21 +01004046 DROP_SHRINK_ALL |\
4047 DROP_IDLE)
Kees Cook647416f2013-03-10 14:10:06 -07004048static int
4049i915_drop_caches_get(void *data, u64 *val)
Chris Wilsondd624af2013-01-15 12:39:35 +00004050{
Kees Cook647416f2013-03-10 14:10:06 -07004051 *val = DROP_ALL;
Chris Wilsondd624af2013-01-15 12:39:35 +00004052
Kees Cook647416f2013-03-10 14:10:06 -07004053 return 0;
Chris Wilsondd624af2013-01-15 12:39:35 +00004054}
4055
Kees Cook647416f2013-03-10 14:10:06 -07004056static int
4057i915_drop_caches_set(void *data, u64 val)
Chris Wilsondd624af2013-01-15 12:39:35 +00004058{
David Weinehall36cdd012016-08-22 13:59:31 +03004059 struct drm_i915_private *dev_priv = data;
4060 struct drm_device *dev = &dev_priv->drm;
Chris Wilson00c26cf2017-05-24 17:26:53 +01004061 int ret = 0;
Chris Wilsondd624af2013-01-15 12:39:35 +00004062
Chris Wilsonb4a0b322017-10-18 13:16:21 +01004063 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4064 val, val & DROP_ALL);
Chris Wilsondd624af2013-01-15 12:39:35 +00004065
4066 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4067 * on ioctls on -EAGAIN. */
Chris Wilson00c26cf2017-05-24 17:26:53 +01004068 if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4069 ret = mutex_lock_interruptible(&dev->struct_mutex);
Chris Wilsondd624af2013-01-15 12:39:35 +00004070 if (ret)
Chris Wilson00c26cf2017-05-24 17:26:53 +01004071 return ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00004072
Chris Wilson00c26cf2017-05-24 17:26:53 +01004073 if (val & DROP_ACTIVE)
4074 ret = i915_gem_wait_for_idle(dev_priv,
4075 I915_WAIT_INTERRUPTIBLE |
4076 I915_WAIT_LOCKED);
4077
4078 if (val & DROP_RETIRE)
4079 i915_gem_retire_requests(dev_priv);
4080
4081 mutex_unlock(&dev->struct_mutex);
4082 }
Chris Wilsondd624af2013-01-15 12:39:35 +00004083
Peter Zijlstrad92a8cf2017-03-03 10:13:38 +01004084 fs_reclaim_acquire(GFP_KERNEL);
Chris Wilson21ab4e72014-09-09 11:16:08 +01004085 if (val & DROP_BOUND)
Chris Wilson912d5722017-09-06 16:19:30 -07004086 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
Chris Wilson4ad72b72014-09-03 19:23:37 +01004087
Chris Wilson21ab4e72014-09-09 11:16:08 +01004088 if (val & DROP_UNBOUND)
Chris Wilson912d5722017-09-06 16:19:30 -07004089 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
Chris Wilsondd624af2013-01-15 12:39:35 +00004090
Chris Wilson8eadc192017-03-08 14:46:22 +00004091 if (val & DROP_SHRINK_ALL)
4092 i915_gem_shrink_all(dev_priv);
Peter Zijlstrad92a8cf2017-03-03 10:13:38 +01004093 fs_reclaim_release(GFP_KERNEL);
Chris Wilson8eadc192017-03-08 14:46:22 +00004094
Chris Wilsonb4a0b322017-10-18 13:16:21 +01004095 if (val & DROP_IDLE)
4096 drain_delayed_work(&dev_priv->gt.idle_work);
4097
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01004098 if (val & DROP_FREED) {
4099 synchronize_rcu();
Chris Wilsonbdeb9782016-12-23 14:57:56 +00004100 i915_gem_drain_freed_objects(dev_priv);
Chris Wilsonfbbd37b2016-10-28 13:58:42 +01004101 }
4102
Kees Cook647416f2013-03-10 14:10:06 -07004103 return ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00004104}
4105
Kees Cook647416f2013-03-10 14:10:06 -07004106DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4107 i915_drop_caches_get, i915_drop_caches_set,
4108 "0x%08llx\n");
Chris Wilsondd624af2013-01-15 12:39:35 +00004109
Kees Cook647416f2013-03-10 14:10:06 -07004110static int
4111i915_max_freq_get(void *data, u64 *val)
Jesse Barnes358733e2011-07-27 11:53:01 -07004112{
David Weinehall36cdd012016-08-22 13:59:31 +03004113 struct drm_i915_private *dev_priv = data;
Daniel Vetter004777c2012-08-09 15:07:01 +02004114
David Weinehall36cdd012016-08-22 13:59:31 +03004115 if (INTEL_GEN(dev_priv) < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004116 return -ENODEV;
4117
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004118 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
Kees Cook647416f2013-03-10 14:10:06 -07004119 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07004120}
4121
Kees Cook647416f2013-03-10 14:10:06 -07004122static int
4123i915_max_freq_set(void *data, u64 val)
Jesse Barnes358733e2011-07-27 11:53:01 -07004124{
David Weinehall36cdd012016-08-22 13:59:31 +03004125 struct drm_i915_private *dev_priv = data;
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004126 struct intel_rps *rps = &dev_priv->gt_pm.rps;
Akash Goelbc4d91f2015-02-26 16:09:47 +05304127 u32 hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07004128 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004129
David Weinehall36cdd012016-08-22 13:59:31 +03004130 if (INTEL_GEN(dev_priv) < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004131 return -ENODEV;
Jesse Barnes358733e2011-07-27 11:53:01 -07004132
Kees Cook647416f2013-03-10 14:10:06 -07004133 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
Jesse Barnes358733e2011-07-27 11:53:01 -07004134
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004135 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004136 if (ret)
4137 return ret;
4138
Jesse Barnes358733e2011-07-27 11:53:01 -07004139 /*
4140 * Turbo will still be enabled, but won't go above the set value.
4141 */
Akash Goelbc4d91f2015-02-26 16:09:47 +05304142 val = intel_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004143
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004144 hw_max = rps->max_freq;
4145 hw_min = rps->min_freq;
Jesse Barnes0a073b82013-04-17 15:54:58 -07004146
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004147 if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004148 mutex_unlock(&dev_priv->pcu_lock);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004149 return -EINVAL;
4150 }
4151
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004152 rps->max_freq_softlimit = val;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004153
Chris Wilson9fcee2f2017-01-26 10:19:19 +00004154 if (intel_set_rps(dev_priv, val))
4155 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004156
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004157 mutex_unlock(&dev_priv->pcu_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07004158
Kees Cook647416f2013-03-10 14:10:06 -07004159 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07004160}
4161
Kees Cook647416f2013-03-10 14:10:06 -07004162DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4163 i915_max_freq_get, i915_max_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03004164 "%llu\n");
Jesse Barnes358733e2011-07-27 11:53:01 -07004165
Kees Cook647416f2013-03-10 14:10:06 -07004166static int
4167i915_min_freq_get(void *data, u64 *val)
Jesse Barnes1523c312012-05-25 12:34:54 -07004168{
David Weinehall36cdd012016-08-22 13:59:31 +03004169 struct drm_i915_private *dev_priv = data;
Daniel Vetter004777c2012-08-09 15:07:01 +02004170
Chris Wilson62e1baa2016-07-13 09:10:36 +01004171 if (INTEL_GEN(dev_priv) < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004172 return -ENODEV;
4173
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004174 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
Kees Cook647416f2013-03-10 14:10:06 -07004175 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07004176}
4177
Kees Cook647416f2013-03-10 14:10:06 -07004178static int
4179i915_min_freq_set(void *data, u64 val)
Jesse Barnes1523c312012-05-25 12:34:54 -07004180{
David Weinehall36cdd012016-08-22 13:59:31 +03004181 struct drm_i915_private *dev_priv = data;
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004182 struct intel_rps *rps = &dev_priv->gt_pm.rps;
Akash Goelbc4d91f2015-02-26 16:09:47 +05304183 u32 hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07004184 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02004185
Chris Wilson62e1baa2016-07-13 09:10:36 +01004186 if (INTEL_GEN(dev_priv) < 6)
Daniel Vetter004777c2012-08-09 15:07:01 +02004187 return -ENODEV;
Jesse Barnes1523c312012-05-25 12:34:54 -07004188
Kees Cook647416f2013-03-10 14:10:06 -07004189 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
Jesse Barnes1523c312012-05-25 12:34:54 -07004190
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004191 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02004192 if (ret)
4193 return ret;
4194
Jesse Barnes1523c312012-05-25 12:34:54 -07004195 /*
4196 * Turbo will still be enabled, but won't go below the set value.
4197 */
Akash Goelbc4d91f2015-02-26 16:09:47 +05304198 val = intel_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004199
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004200 hw_max = rps->max_freq;
4201 hw_min = rps->min_freq;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004202
David Weinehall36cdd012016-08-22 13:59:31 +03004203 if (val < hw_min ||
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004204 val > hw_max || val > rps->max_freq_softlimit) {
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004205 mutex_unlock(&dev_priv->pcu_lock);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004206 return -EINVAL;
4207 }
4208
Sagar Arun Kamble562d9ba2017-10-10 22:30:06 +01004209 rps->min_freq_softlimit = val;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004210
Chris Wilson9fcee2f2017-01-26 10:19:19 +00004211 if (intel_set_rps(dev_priv, val))
4212 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06004213
Sagar Arun Kamble9f817502017-10-10 22:30:05 +01004214 mutex_unlock(&dev_priv->pcu_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07004215
Kees Cook647416f2013-03-10 14:10:06 -07004216 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07004217}
4218
Kees Cook647416f2013-03-10 14:10:06 -07004219DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4220 i915_min_freq_get, i915_min_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03004221 "%llu\n");
Jesse Barnes1523c312012-05-25 12:34:54 -07004222
Kees Cook647416f2013-03-10 14:10:06 -07004223static int
4224i915_cache_sharing_get(void *data, u64 *val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004225{
David Weinehall36cdd012016-08-22 13:59:31 +03004226 struct drm_i915_private *dev_priv = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004227 u32 snpcr;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004228
David Weinehall36cdd012016-08-22 13:59:31 +03004229 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
Daniel Vetter004777c2012-08-09 15:07:01 +02004230 return -ENODEV;
4231
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004232 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02004233
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004234 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004235
4236 intel_runtime_pm_put(dev_priv);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004237
Kees Cook647416f2013-03-10 14:10:06 -07004238 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004239
Kees Cook647416f2013-03-10 14:10:06 -07004240 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004241}
4242
Kees Cook647416f2013-03-10 14:10:06 -07004243static int
4244i915_cache_sharing_set(void *data, u64 val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004245{
David Weinehall36cdd012016-08-22 13:59:31 +03004246 struct drm_i915_private *dev_priv = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004247 u32 snpcr;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004248
David Weinehall36cdd012016-08-22 13:59:31 +03004249 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
Daniel Vetter004777c2012-08-09 15:07:01 +02004250 return -ENODEV;
4251
Kees Cook647416f2013-03-10 14:10:06 -07004252 if (val > 3)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004253 return -EINVAL;
4254
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004255 intel_runtime_pm_get(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07004256 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004257
4258 /* Update the cache sharing policy here as well */
4259 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4260 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4261 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4262 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4263
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004264 intel_runtime_pm_put(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07004265 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004266}
4267
Kees Cook647416f2013-03-10 14:10:06 -07004268DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4269 i915_cache_sharing_get, i915_cache_sharing_set,
4270 "%llu\n");
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07004271
David Weinehall36cdd012016-08-22 13:59:31 +03004272static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
Imre Deak915490d2016-08-31 19:13:01 +03004273 struct sseu_dev_info *sseu)
Jeff McGee5d395252015-04-03 18:13:17 -07004274{
Ville Syrjälä0a0b4572015-08-21 20:45:27 +03004275 int ss_max = 2;
Jeff McGee5d395252015-04-03 18:13:17 -07004276 int ss;
4277 u32 sig1[ss_max], sig2[ss_max];
4278
4279 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4280 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4281 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4282 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4283
4284 for (ss = 0; ss < ss_max; ss++) {
4285 unsigned int eu_cnt;
4286
4287 if (sig1[ss] & CHV_SS_PG_ENABLE)
4288 /* skip disabled subslice */
4289 continue;
4290
Imre Deakf08a0c92016-08-31 19:13:04 +03004291 sseu->slice_mask = BIT(0);
Imre Deak57ec1712016-08-31 19:13:05 +03004292 sseu->subslice_mask |= BIT(ss);
Jeff McGee5d395252015-04-03 18:13:17 -07004293 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4294 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4295 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4296 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
Imre Deak915490d2016-08-31 19:13:01 +03004297 sseu->eu_total += eu_cnt;
4298 sseu->eu_per_subslice = max_t(unsigned int,
4299 sseu->eu_per_subslice, eu_cnt);
Jeff McGee5d395252015-04-03 18:13:17 -07004300 }
Jeff McGee5d395252015-04-03 18:13:17 -07004301}
4302
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07004303static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
4304 struct sseu_dev_info *sseu)
4305{
4306 const struct intel_device_info *info = INTEL_INFO(dev_priv);
4307 int s_max = 6, ss_max = 4;
4308 int s, ss;
4309 u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
4310
4311 for (s = 0; s < s_max; s++) {
4312 /*
4313 * FIXME: Valid SS Mask respects the spec and read
4314 * only valid bits for those registers, excluding reserverd
4315 * although this seems wrong because it would leave many
4316 * subslices without ACK.
4317 */
4318 s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
4319 GEN10_PGCTL_VALID_SS_MASK(s);
4320 eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
4321 eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
4322 }
4323
4324 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4325 GEN9_PGCTL_SSA_EU19_ACK |
4326 GEN9_PGCTL_SSA_EU210_ACK |
4327 GEN9_PGCTL_SSA_EU311_ACK;
4328 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4329 GEN9_PGCTL_SSB_EU19_ACK |
4330 GEN9_PGCTL_SSB_EU210_ACK |
4331 GEN9_PGCTL_SSB_EU311_ACK;
4332
4333 for (s = 0; s < s_max; s++) {
4334 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4335 /* skip disabled slice */
4336 continue;
4337
4338 sseu->slice_mask |= BIT(s);
4339 sseu->subslice_mask = info->sseu.subslice_mask;
4340
4341 for (ss = 0; ss < ss_max; ss++) {
4342 unsigned int eu_cnt;
4343
4344 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4345 /* skip disabled subslice */
4346 continue;
4347
4348 eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
4349 eu_mask[ss % 2]);
4350 sseu->eu_total += eu_cnt;
4351 sseu->eu_per_subslice = max_t(unsigned int,
4352 sseu->eu_per_subslice,
4353 eu_cnt);
4354 }
4355 }
4356}
4357
David Weinehall36cdd012016-08-22 13:59:31 +03004358static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
Imre Deak915490d2016-08-31 19:13:01 +03004359 struct sseu_dev_info *sseu)
Jeff McGee5d395252015-04-03 18:13:17 -07004360{
Jeff McGee1c046bc2015-04-03 18:13:18 -07004361 int s_max = 3, ss_max = 4;
Jeff McGee5d395252015-04-03 18:13:17 -07004362 int s, ss;
4363 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4364
Jeff McGee1c046bc2015-04-03 18:13:18 -07004365 /* BXT has a single slice and at most 3 subslices. */
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02004366 if (IS_GEN9_LP(dev_priv)) {
Jeff McGee1c046bc2015-04-03 18:13:18 -07004367 s_max = 1;
4368 ss_max = 3;
4369 }
4370
4371 for (s = 0; s < s_max; s++) {
4372 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4373 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4374 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4375 }
4376
Jeff McGee5d395252015-04-03 18:13:17 -07004377 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4378 GEN9_PGCTL_SSA_EU19_ACK |
4379 GEN9_PGCTL_SSA_EU210_ACK |
4380 GEN9_PGCTL_SSA_EU311_ACK;
4381 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4382 GEN9_PGCTL_SSB_EU19_ACK |
4383 GEN9_PGCTL_SSB_EU210_ACK |
4384 GEN9_PGCTL_SSB_EU311_ACK;
4385
4386 for (s = 0; s < s_max; s++) {
4387 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4388 /* skip disabled slice */
4389 continue;
4390
Imre Deakf08a0c92016-08-31 19:13:04 +03004391 sseu->slice_mask |= BIT(s);
Jeff McGee1c046bc2015-04-03 18:13:18 -07004392
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07004393 if (IS_GEN9_BC(dev_priv))
Imre Deak57ec1712016-08-31 19:13:05 +03004394 sseu->subslice_mask =
4395 INTEL_INFO(dev_priv)->sseu.subslice_mask;
Jeff McGee1c046bc2015-04-03 18:13:18 -07004396
Jeff McGee5d395252015-04-03 18:13:17 -07004397 for (ss = 0; ss < ss_max; ss++) {
4398 unsigned int eu_cnt;
4399
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +02004400 if (IS_GEN9_LP(dev_priv)) {
Imre Deak57ec1712016-08-31 19:13:05 +03004401 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4402 /* skip disabled subslice */
4403 continue;
Jeff McGee1c046bc2015-04-03 18:13:18 -07004404
Imre Deak57ec1712016-08-31 19:13:05 +03004405 sseu->subslice_mask |= BIT(ss);
4406 }
Jeff McGee1c046bc2015-04-03 18:13:18 -07004407
Jeff McGee5d395252015-04-03 18:13:17 -07004408 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4409 eu_mask[ss%2]);
Imre Deak915490d2016-08-31 19:13:01 +03004410 sseu->eu_total += eu_cnt;
4411 sseu->eu_per_subslice = max_t(unsigned int,
4412 sseu->eu_per_subslice,
4413 eu_cnt);
Jeff McGee5d395252015-04-03 18:13:17 -07004414 }
4415 }
4416}
4417
David Weinehall36cdd012016-08-22 13:59:31 +03004418static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
Imre Deak915490d2016-08-31 19:13:01 +03004419 struct sseu_dev_info *sseu)
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004420{
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004421 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
David Weinehall36cdd012016-08-22 13:59:31 +03004422 int s;
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004423
Imre Deakf08a0c92016-08-31 19:13:04 +03004424 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004425
Imre Deakf08a0c92016-08-31 19:13:04 +03004426 if (sseu->slice_mask) {
Imre Deak57ec1712016-08-31 19:13:05 +03004427 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
Imre Deak43b67992016-08-31 19:13:02 +03004428 sseu->eu_per_subslice =
4429 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
Imre Deak57ec1712016-08-31 19:13:05 +03004430 sseu->eu_total = sseu->eu_per_subslice *
4431 sseu_subslice_total(sseu);
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004432
4433 /* subtract fused off EU(s) from enabled slice(s) */
Imre Deak795b38b2016-08-31 19:13:07 +03004434 for (s = 0; s < fls(sseu->slice_mask); s++) {
Imre Deak43b67992016-08-31 19:13:02 +03004435 u8 subslice_7eu =
4436 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004437
Imre Deak915490d2016-08-31 19:13:01 +03004438 sseu->eu_total -= hweight8(subslice_7eu);
Łukasz Daniluk91bedd32015-09-25 11:54:58 +02004439 }
4440 }
4441}
4442
Imre Deak615d8902016-08-31 19:13:03 +03004443static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4444 const struct sseu_dev_info *sseu)
4445{
4446 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4447 const char *type = is_available_info ? "Available" : "Enabled";
4448
Imre Deakc67ba532016-08-31 19:13:06 +03004449 seq_printf(m, " %s Slice Mask: %04x\n", type,
4450 sseu->slice_mask);
Imre Deak615d8902016-08-31 19:13:03 +03004451 seq_printf(m, " %s Slice Total: %u\n", type,
Imre Deakf08a0c92016-08-31 19:13:04 +03004452 hweight8(sseu->slice_mask));
Imre Deak615d8902016-08-31 19:13:03 +03004453 seq_printf(m, " %s Subslice Total: %u\n", type,
Imre Deak57ec1712016-08-31 19:13:05 +03004454 sseu_subslice_total(sseu));
Imre Deakc67ba532016-08-31 19:13:06 +03004455 seq_printf(m, " %s Subslice Mask: %04x\n", type,
4456 sseu->subslice_mask);
Imre Deak615d8902016-08-31 19:13:03 +03004457 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
Imre Deak57ec1712016-08-31 19:13:05 +03004458 hweight8(sseu->subslice_mask));
Imre Deak615d8902016-08-31 19:13:03 +03004459 seq_printf(m, " %s EU Total: %u\n", type,
4460 sseu->eu_total);
4461 seq_printf(m, " %s EU Per Subslice: %u\n", type,
4462 sseu->eu_per_subslice);
4463
4464 if (!is_available_info)
4465 return;
4466
4467 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4468 if (HAS_POOLED_EU(dev_priv))
4469 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
4470
4471 seq_printf(m, " Has Slice Power Gating: %s\n",
4472 yesno(sseu->has_slice_pg));
4473 seq_printf(m, " Has Subslice Power Gating: %s\n",
4474 yesno(sseu->has_subslice_pg));
4475 seq_printf(m, " Has EU Power Gating: %s\n",
4476 yesno(sseu->has_eu_pg));
4477}
4478
Jeff McGee38732182015-02-13 10:27:54 -06004479static int i915_sseu_status(struct seq_file *m, void *unused)
4480{
David Weinehall36cdd012016-08-22 13:59:31 +03004481 struct drm_i915_private *dev_priv = node_to_i915(m->private);
Imre Deak915490d2016-08-31 19:13:01 +03004482 struct sseu_dev_info sseu;
Jeff McGee38732182015-02-13 10:27:54 -06004483
David Weinehall36cdd012016-08-22 13:59:31 +03004484 if (INTEL_GEN(dev_priv) < 8)
Jeff McGee38732182015-02-13 10:27:54 -06004485 return -ENODEV;
4486
4487 seq_puts(m, "SSEU Device Info\n");
Imre Deak615d8902016-08-31 19:13:03 +03004488 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
Jeff McGee38732182015-02-13 10:27:54 -06004489
Jeff McGee7f992ab2015-02-13 10:27:55 -06004490 seq_puts(m, "SSEU Device Status\n");
Imre Deak915490d2016-08-31 19:13:01 +03004491 memset(&sseu, 0, sizeof(sseu));
David Weinehall238010e2016-08-01 17:33:27 +03004492
4493 intel_runtime_pm_get(dev_priv);
4494
David Weinehall36cdd012016-08-22 13:59:31 +03004495 if (IS_CHERRYVIEW(dev_priv)) {
Imre Deak915490d2016-08-31 19:13:01 +03004496 cherryview_sseu_device_status(dev_priv, &sseu);
David Weinehall36cdd012016-08-22 13:59:31 +03004497 } else if (IS_BROADWELL(dev_priv)) {
Imre Deak915490d2016-08-31 19:13:01 +03004498 broadwell_sseu_device_status(dev_priv, &sseu);
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07004499 } else if (IS_GEN9(dev_priv)) {
Imre Deak915490d2016-08-31 19:13:01 +03004500 gen9_sseu_device_status(dev_priv, &sseu);
Rodrigo Vivif8c3dcf2017-10-25 17:15:46 -07004501 } else if (INTEL_GEN(dev_priv) >= 10) {
4502 gen10_sseu_device_status(dev_priv, &sseu);
Jeff McGee7f992ab2015-02-13 10:27:55 -06004503 }
David Weinehall238010e2016-08-01 17:33:27 +03004504
4505 intel_runtime_pm_put(dev_priv);
4506
Imre Deak615d8902016-08-31 19:13:03 +03004507 i915_print_sseu_info(m, false, &sseu);
Jeff McGee7f992ab2015-02-13 10:27:55 -06004508
Jeff McGee38732182015-02-13 10:27:54 -06004509 return 0;
4510}
4511
Ben Widawsky6d794d42011-04-25 11:25:56 -07004512static int i915_forcewake_open(struct inode *inode, struct file *file)
4513{
Chris Wilsond7a133d2017-09-07 14:44:41 +01004514 struct drm_i915_private *i915 = inode->i_private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07004515
Chris Wilsond7a133d2017-09-07 14:44:41 +01004516 if (INTEL_GEN(i915) < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004517 return 0;
4518
Chris Wilsond7a133d2017-09-07 14:44:41 +01004519 intel_runtime_pm_get(i915);
4520 intel_uncore_forcewake_user_get(i915);
Ben Widawsky6d794d42011-04-25 11:25:56 -07004521
4522 return 0;
4523}
4524
Ben Widawskyc43b5632012-04-16 14:07:40 -07004525static int i915_forcewake_release(struct inode *inode, struct file *file)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004526{
Chris Wilsond7a133d2017-09-07 14:44:41 +01004527 struct drm_i915_private *i915 = inode->i_private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07004528
Chris Wilsond7a133d2017-09-07 14:44:41 +01004529 if (INTEL_GEN(i915) < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07004530 return 0;
4531
Chris Wilsond7a133d2017-09-07 14:44:41 +01004532 intel_uncore_forcewake_user_put(i915);
4533 intel_runtime_pm_put(i915);
Ben Widawsky6d794d42011-04-25 11:25:56 -07004534
4535 return 0;
4536}
4537
4538static const struct file_operations i915_forcewake_fops = {
4539 .owner = THIS_MODULE,
4540 .open = i915_forcewake_open,
4541 .release = i915_forcewake_release,
4542};
4543
Lyude317eaa92017-02-03 21:18:25 -05004544static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4545{
4546 struct drm_i915_private *dev_priv = m->private;
4547 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4548
4549 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4550 seq_printf(m, "Detected: %s\n",
4551 yesno(delayed_work_pending(&hotplug->reenable_work)));
4552
4553 return 0;
4554}
4555
4556static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4557 const char __user *ubuf, size_t len,
4558 loff_t *offp)
4559{
4560 struct seq_file *m = file->private_data;
4561 struct drm_i915_private *dev_priv = m->private;
4562 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4563 unsigned int new_threshold;
4564 int i;
4565 char *newline;
4566 char tmp[16];
4567
4568 if (len >= sizeof(tmp))
4569 return -EINVAL;
4570
4571 if (copy_from_user(tmp, ubuf, len))
4572 return -EFAULT;
4573
4574 tmp[len] = '\0';
4575
4576 /* Strip newline, if any */
4577 newline = strchr(tmp, '\n');
4578 if (newline)
4579 *newline = '\0';
4580
4581 if (strcmp(tmp, "reset") == 0)
4582 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4583 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4584 return -EINVAL;
4585
4586 if (new_threshold > 0)
4587 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4588 new_threshold);
4589 else
4590 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4591
4592 spin_lock_irq(&dev_priv->irq_lock);
4593 hotplug->hpd_storm_threshold = new_threshold;
4594 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4595 for_each_hpd_pin(i)
4596 hotplug->stats[i].count = 0;
4597 spin_unlock_irq(&dev_priv->irq_lock);
4598
4599 /* Re-enable hpd immediately if we were in an irq storm */
4600 flush_delayed_work(&dev_priv->hotplug.reenable_work);
4601
4602 return len;
4603}
4604
4605static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4606{
4607 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4608}
4609
4610static const struct file_operations i915_hpd_storm_ctl_fops = {
4611 .owner = THIS_MODULE,
4612 .open = i915_hpd_storm_ctl_open,
4613 .read = seq_read,
4614 .llseek = seq_lseek,
4615 .release = single_release,
4616 .write = i915_hpd_storm_ctl_write
4617};
4618
C, Ramalingam35954e82017-11-08 00:08:23 +05304619static int i915_drrs_ctl_set(void *data, u64 val)
4620{
4621 struct drm_i915_private *dev_priv = data;
4622 struct drm_device *dev = &dev_priv->drm;
4623 struct intel_crtc *intel_crtc;
4624 struct intel_encoder *encoder;
4625 struct intel_dp *intel_dp;
4626
4627 if (INTEL_GEN(dev_priv) < 7)
4628 return -ENODEV;
4629
4630 drm_modeset_lock_all(dev);
4631 for_each_intel_crtc(dev, intel_crtc) {
4632 if (!intel_crtc->base.state->active ||
4633 !intel_crtc->config->has_drrs)
4634 continue;
4635
4636 for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
4637 if (encoder->type != INTEL_OUTPUT_EDP)
4638 continue;
4639
4640 DRM_DEBUG_DRIVER("Manually %sabling DRRS. %llu\n",
4641 val ? "en" : "dis", val);
4642
4643 intel_dp = enc_to_intel_dp(&encoder->base);
4644 if (val)
4645 intel_edp_drrs_enable(intel_dp,
4646 intel_crtc->config);
4647 else
4648 intel_edp_drrs_disable(intel_dp,
4649 intel_crtc->config);
4650 }
4651 }
4652 drm_modeset_unlock_all(dev);
4653
4654 return 0;
4655}
4656
4657DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n");
4658
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01004659static const struct drm_info_list i915_debugfs_list[] = {
Chris Wilson311bd682011-01-13 19:06:50 +00004660 {"i915_capabilities", i915_capabilities, 0},
Chris Wilson73aa8082010-09-30 11:46:12 +01004661 {"i915_gem_objects", i915_gem_object_info, 0},
Chris Wilson08c18322011-01-10 00:00:24 +00004662 {"i915_gem_gtt", i915_gem_gtt_info, 0},
Chris Wilson6d2b88852013-08-07 18:30:54 +01004663 {"i915_gem_stolen", i915_gem_stolen_list_info },
Chris Wilsona6172a82009-02-11 14:26:38 +00004664 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05004665 {"i915_gem_interrupt", i915_interrupt_info, 0},
Brad Volkin493018d2014-12-11 12:13:08 -08004666 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
Dave Gordon8b417c22015-08-12 15:43:44 +01004667 {"i915_guc_info", i915_guc_info, 0},
Alex Daifdf5d352015-08-12 15:43:37 +01004668 {"i915_guc_load_status", i915_guc_load_status_info, 0},
Alex Dai4c7e77f2015-08-12 15:43:40 +01004669 {"i915_guc_log_dump", i915_guc_log_dump, 0},
Daniele Ceraolo Spurioac58d2a2017-05-22 10:50:28 -07004670 {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
Oscar Mateoa8b93702017-05-10 15:04:51 +00004671 {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
Anusha Srivatsa0509ead2017-01-18 08:05:56 -08004672 {"i915_huc_load_status", i915_huc_load_status_info, 0},
Deepak Sadb4bd12014-03-31 11:30:02 +05304673 {"i915_frequency_info", i915_frequency_info, 0},
Chris Wilsonf6544492015-01-26 18:03:04 +02004674 {"i915_hangcheck_info", i915_hangcheck_info, 0},
Michel Thierry061d06a2017-06-20 10:57:49 +01004675 {"i915_reset_info", i915_reset_info, 0},
Jesse Barnesf97108d2010-01-29 11:27:07 -08004676 {"i915_drpc_info", i915_drpc_info, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07004677 {"i915_emon_status", i915_emon_status, 0},
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07004678 {"i915_ring_freq_table", i915_ring_freq_table, 0},
Daniel Vetter9a851782015-06-18 10:30:22 +02004679 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
Jesse Barnesb5e50c32010-02-05 12:42:41 -08004680 {"i915_fbc_status", i915_fbc_status, 0},
Paulo Zanoni92d44622013-05-31 16:33:24 -03004681 {"i915_ips_status", i915_ips_status, 0},
Jesse Barnes4a9bef32010-02-05 12:47:35 -08004682 {"i915_sr_status", i915_sr_status, 0},
Chris Wilson44834a62010-08-19 16:09:23 +01004683 {"i915_opregion", i915_opregion, 0},
Jani Nikulaada8f952015-12-15 13:17:12 +02004684 {"i915_vbt", i915_vbt, 0},
Chris Wilson37811fc2010-08-25 22:45:57 +01004685 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
Ben Widawskye76d3632011-03-19 18:14:29 -07004686 {"i915_context_status", i915_context_status, 0},
Mika Kuoppalaf65367b2015-01-16 11:34:42 +02004687 {"i915_forcewake_domains", i915_forcewake_domains, 0},
Daniel Vetterea16a3c2011-12-14 13:57:16 +01004688 {"i915_swizzle_info", i915_swizzle_info, 0},
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01004689 {"i915_ppgtt_info", i915_ppgtt_info, 0},
Ben Widawsky63573eb2013-07-04 11:02:07 -07004690 {"i915_llc", i915_llc, 0},
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03004691 {"i915_edp_psr_status", i915_edp_psr_status, 0},
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02004692 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
Jesse Barnesec013e72013-08-20 10:29:23 +01004693 {"i915_energy_uJ", i915_energy_uJ, 0},
Damien Lespiau6455c872015-06-04 18:23:57 +01004694 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
Imre Deak1da51582013-11-25 17:15:35 +02004695 {"i915_power_domain_info", i915_power_domain_info, 0},
Damien Lespiaub7cec662015-10-27 14:47:01 +02004696 {"i915_dmc_info", i915_dmc_info, 0},
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08004697 {"i915_display_info", i915_display_info, 0},
Chris Wilson1b365952016-10-04 21:11:31 +01004698 {"i915_engine_info", i915_engine_info, 0},
Chris Wilsonc5418a82017-10-13 21:26:19 +01004699 {"i915_shrinker_info", i915_shrinker_info, 0},
Daniel Vetter728e29d2014-06-25 22:01:53 +03004700 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
Dave Airlie11bed952014-05-12 15:22:27 +10004701 {"i915_dp_mst_info", i915_dp_mst_info, 0},
Damien Lespiau1ed1ef92014-08-30 16:50:59 +01004702 {"i915_wa_registers", i915_wa_registers, 0},
Damien Lespiauc5511e42014-11-04 17:06:51 +00004703 {"i915_ddb_info", i915_ddb_info, 0},
Jeff McGee38732182015-02-13 10:27:54 -06004704 {"i915_sseu_status", i915_sseu_status, 0},
Vandana Kannana54746e2015-03-03 20:53:10 +05304705 {"i915_drrs_status", i915_drrs_status, 0},
Chris Wilson1854d5c2015-04-07 16:20:32 +01004706 {"i915_rps_boost_info", i915_rps_boost_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05004707};
Ben Gamari27c202a2009-07-01 22:26:52 -04004708#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
Ben Gamari20172632009-02-17 20:08:50 -05004709
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01004710static const struct i915_debugfs_files {
Daniel Vetter34b96742013-07-04 20:49:44 +02004711 const char *name;
4712 const struct file_operations *fops;
4713} i915_debugfs_files[] = {
4714 {"i915_wedged", &i915_wedged_fops},
4715 {"i915_max_freq", &i915_max_freq_fops},
4716 {"i915_min_freq", &i915_min_freq_fops},
4717 {"i915_cache_sharing", &i915_cache_sharing_fops},
Chris Wilson094f9a52013-09-25 17:34:55 +01004718 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4719 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
Daniel Vetter34b96742013-07-04 20:49:44 +02004720 {"i915_gem_drop_caches", &i915_drop_caches_fops},
Chris Wilson98a2f412016-10-12 10:05:18 +01004721#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
Daniel Vetter34b96742013-07-04 20:49:44 +02004722 {"i915_error_state", &i915_error_state_fops},
Chris Wilson5a4c6f12017-02-14 16:46:11 +00004723 {"i915_gpu_info", &i915_gpu_info_fops},
Chris Wilson98a2f412016-10-12 10:05:18 +01004724#endif
Daniel Vetter34b96742013-07-04 20:49:44 +02004725 {"i915_next_seqno", &i915_next_seqno_fops},
Damien Lespiaubd9db022013-10-15 18:55:36 +01004726 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
Ville Syrjälä369a1342014-01-22 14:36:08 +02004727 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4728 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4729 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
Ville Syrjälä4127dc42017-06-06 15:44:12 +03004730 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
Todd Previteeb3394fa2015-04-18 00:04:19 -07004731 {"i915_dp_test_data", &i915_displayport_test_data_fops},
4732 {"i915_dp_test_type", &i915_displayport_test_type_fops},
Sagar Arun Kamble685534e2016-10-12 21:54:41 +05304733 {"i915_dp_test_active", &i915_displayport_test_active_fops},
Lyude317eaa92017-02-03 21:18:25 -05004734 {"i915_guc_log_control", &i915_guc_log_control_fops},
Kumar, Maheshd2d4f392017-08-17 19:15:29 +05304735 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
C, Ramalingam35954e82017-11-08 00:08:23 +05304736 {"i915_ipc_status", &i915_ipc_status_fops},
4737 {"i915_drrs_ctl", &i915_drrs_ctl_fops}
Daniel Vetter34b96742013-07-04 20:49:44 +02004738};
4739
Chris Wilson1dac8912016-06-24 14:00:17 +01004740int i915_debugfs_register(struct drm_i915_private *dev_priv)
Ben Gamari20172632009-02-17 20:08:50 -05004741{
Chris Wilson91c8a322016-07-05 10:40:23 +01004742 struct drm_minor *minor = dev_priv->drm.primary;
Noralf Trønnesb05eeb02017-01-26 23:56:21 +01004743 struct dentry *ent;
Daniel Vetter34b96742013-07-04 20:49:44 +02004744 int ret, i;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01004745
Noralf Trønnesb05eeb02017-01-26 23:56:21 +01004746 ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4747 minor->debugfs_root, to_i915(minor->dev),
4748 &i915_forcewake_fops);
4749 if (!ent)
4750 return -ENOMEM;
Daniel Vetter6a9c3082011-12-14 13:57:11 +01004751
Tomeu Vizoso731035f2016-12-12 13:29:48 +01004752 ret = intel_pipe_crc_create(minor);
4753 if (ret)
4754 return ret;
Damien Lespiau07144422013-10-15 18:55:40 +01004755
Daniel Vetter34b96742013-07-04 20:49:44 +02004756 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
Noralf Trønnesb05eeb02017-01-26 23:56:21 +01004757 ent = debugfs_create_file(i915_debugfs_files[i].name,
4758 S_IRUGO | S_IWUSR,
4759 minor->debugfs_root,
4760 to_i915(minor->dev),
Daniel Vetter34b96742013-07-04 20:49:44 +02004761 i915_debugfs_files[i].fops);
Noralf Trønnesb05eeb02017-01-26 23:56:21 +01004762 if (!ent)
4763 return -ENOMEM;
Daniel Vetter34b96742013-07-04 20:49:44 +02004764 }
Mika Kuoppala40633212012-12-04 15:12:00 +02004765
Ben Gamari27c202a2009-07-01 22:26:52 -04004766 return drm_debugfs_create_files(i915_debugfs_list,
4767 I915_DEBUGFS_ENTRIES,
Ben Gamari20172632009-02-17 20:08:50 -05004768 minor->debugfs_root, minor);
4769}
4770
Jani Nikulaaa7471d2015-04-01 11:15:21 +03004771struct dpcd_block {
4772 /* DPCD dump start address. */
4773 unsigned int offset;
4774 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4775 unsigned int end;
4776 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4777 size_t size;
4778 /* Only valid for eDP. */
4779 bool edp;
4780};
4781
4782static const struct dpcd_block i915_dpcd_debug[] = {
4783 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4784 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4785 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4786 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4787 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4788 { .offset = DP_SET_POWER },
4789 { .offset = DP_EDP_DPCD_REV },
4790 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4791 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4792 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4793};
4794
4795static int i915_dpcd_show(struct seq_file *m, void *data)
4796{
4797 struct drm_connector *connector = m->private;
4798 struct intel_dp *intel_dp =
4799 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4800 uint8_t buf[16];
4801 ssize_t err;
4802 int i;
4803
Mika Kuoppala5c1a8872015-05-15 13:09:21 +03004804 if (connector->status != connector_status_connected)
4805 return -ENODEV;
4806
Jani Nikulaaa7471d2015-04-01 11:15:21 +03004807 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4808 const struct dpcd_block *b = &i915_dpcd_debug[i];
4809 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4810
4811 if (b->edp &&
4812 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4813 continue;
4814
4815 /* low tech for now */
4816 if (WARN_ON(size > sizeof(buf)))
4817 continue;
4818
4819 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4820 if (err <= 0) {
4821 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4822 size, b->offset, err);
4823 continue;
4824 }
4825
4826 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
kbuild test robotb3f9d7d2015-04-16 18:34:06 +08004827 }
Jani Nikulaaa7471d2015-04-01 11:15:21 +03004828
4829 return 0;
4830}
4831
4832static int i915_dpcd_open(struct inode *inode, struct file *file)
4833{
4834 return single_open(file, i915_dpcd_show, inode->i_private);
4835}
4836
4837static const struct file_operations i915_dpcd_fops = {
4838 .owner = THIS_MODULE,
4839 .open = i915_dpcd_open,
4840 .read = seq_read,
4841 .llseek = seq_lseek,
4842 .release = single_release,
4843};
4844
David Weinehallecbd6782016-08-23 12:23:56 +03004845static int i915_panel_show(struct seq_file *m, void *data)
4846{
4847 struct drm_connector *connector = m->private;
4848 struct intel_dp *intel_dp =
4849 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4850
4851 if (connector->status != connector_status_connected)
4852 return -ENODEV;
4853
4854 seq_printf(m, "Panel power up delay: %d\n",
4855 intel_dp->panel_power_up_delay);
4856 seq_printf(m, "Panel power down delay: %d\n",
4857 intel_dp->panel_power_down_delay);
4858 seq_printf(m, "Backlight on delay: %d\n",
4859 intel_dp->backlight_on_delay);
4860 seq_printf(m, "Backlight off delay: %d\n",
4861 intel_dp->backlight_off_delay);
4862
4863 return 0;
4864}
4865
4866static int i915_panel_open(struct inode *inode, struct file *file)
4867{
4868 return single_open(file, i915_panel_show, inode->i_private);
4869}
4870
4871static const struct file_operations i915_panel_fops = {
4872 .owner = THIS_MODULE,
4873 .open = i915_panel_open,
4874 .read = seq_read,
4875 .llseek = seq_lseek,
4876 .release = single_release,
4877};
4878
Jani Nikulaaa7471d2015-04-01 11:15:21 +03004879/**
4880 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4881 * @connector: pointer to a registered drm_connector
4882 *
4883 * Cleanup will be done by drm_connector_unregister() through a call to
4884 * drm_debugfs_connector_remove().
4885 *
4886 * Returns 0 on success, negative error codes on error.
4887 */
4888int i915_debugfs_connector_add(struct drm_connector *connector)
4889{
4890 struct dentry *root = connector->debugfs_entry;
4891
4892 /* The connector must have been registered beforehands. */
4893 if (!root)
4894 return -ENODEV;
4895
4896 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4897 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
David Weinehallecbd6782016-08-23 12:23:56 +03004898 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4899 connector, &i915_dpcd_fops);
4900
4901 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4902 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4903 connector, &i915_panel_fops);
Jani Nikulaaa7471d2015-04-01 11:15:21 +03004904
4905 return 0;
4906}