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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Ken Zhang420dd202013-01-08 14:28:20 -05004 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070053#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Kalyan Thota9284a272012-11-02 20:55:30 +053074#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053075#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
Ken Zhang4e83b932012-12-02 21:15:47 -050076 struct mdp_display_commit)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053077#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
Ken Zhang420dd202013-01-08 14:28:20 -050078#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Deva Ramasubramanian166b0982013-01-25 20:11:41 -080079#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
80 unsigned int)
Terence Hampson3e636aa2013-05-08 19:01:51 -040081#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
Kuogee Hsieha77eca62012-09-13 13:22:04 -070082
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070083#define FB_TYPE_3D_PANEL 0x10101010
84#define MDP_IMGTYPE2_START 0x10000
85#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070086
87enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088 NOTIFY_UPDATE_START,
89 NOTIFY_UPDATE_STOP,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -070090 NOTIFY_UPDATE_POWER_OFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070091};
92
93enum {
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070094 NOTIFY_TYPE_NO_UPDATE,
95 NOTIFY_TYPE_SUSPEND,
96 NOTIFY_TYPE_UPDATE,
97};
98
99enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100 MDP_RGB_565, /* RGB 565 planer */
101 MDP_XRGB_8888, /* RGB 888 padded */
102 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +0530103 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104 MDP_ARGB_8888, /* ARGB 888 */
105 MDP_RGB_888, /* RGB 888 planer */
106 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
107 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
Pawan Kumar42acdef2013-03-21 19:55:49 +0530108 MDP_CBYCRY_H2V1, /* CbYCrY interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700109 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
110 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700111 MDP_Y_CRCB_H1V2,
112 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700113 MDP_RGBA_8888, /* ARGB 888 */
114 MDP_BGRA_8888, /* ABGR 888 */
115 MDP_RGBX_8888, /* RGBX 888 */
116 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
117 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
118 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530119 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700120 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
121 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
122 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700123 MDP_YCRCB_H1V1, /* YCrCb interleave */
124 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700125 MDP_BGR_565, /* BGR 565 planer */
Adrian Salido-Morenod559ef12012-07-12 20:16:14 -0700126 MDP_BGR_888, /* BGR 888 */
Adrian Salido-Moreno330c0bf2012-08-22 14:15:33 -0700127 MDP_Y_CBCR_H2V2_VENUS,
Pawan Kumar79854382013-02-14 15:27:12 +0530128 MDP_BGRX_8888, /* BGRX 8888 */
Shalabh Jainbea586a2013-08-23 12:30:48 -0700129 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */
130 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */
131 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */
132 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */
133 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */
134 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */
135 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */
136 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */
Ramkumar Radhakrishnan97180fa2013-08-06 20:50:52 -0700137 MDP_YCBYCR_H2V1, /* YCbYCr interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700138 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800139 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700140 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700142};
143
144enum {
145 PMEM_IMG,
146 FB_IMG,
147};
148
Liyuan Lid9736632011-11-11 13:47:59 -0800149enum {
150 HSIC_HUE = 0,
151 HSIC_SAT,
152 HSIC_INT,
153 HSIC_CON,
154 NUM_HSIC_PARAM,
155};
156
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700157#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700158#define MDSS_MDP_RIGHT_MIXER 0x100
159
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700160/* mdp_blit_req flag values */
161#define MDP_ROT_NOP 0
162#define MDP_FLIP_LR 0x1
163#define MDP_FLIP_UD 0x2
164#define MDP_ROT_90 0x4
165#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
166#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
167#define MDP_DITHER 0x8
168#define MDP_BLUR 0x10
169#define MDP_BLEND_FG_PREMULT 0x20000
Padmanabhan Komandurudd10bf12012-10-17 20:27:33 +0530170#define MDP_IS_FG 0x40000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700171#define MDP_DEINTERLACE 0x80000000
172#define MDP_SHARPENING 0x40000000
173#define MDP_NO_DMA_BARRIER_START 0x20000000
174#define MDP_NO_DMA_BARRIER_END 0x10000000
175#define MDP_NO_BLIT 0x08000000
176#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
177#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
178 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
179#define MDP_BLIT_SRC_GEM 0x04000000
180#define MDP_BLIT_DST_GEM 0x02000000
181#define MDP_BLIT_NON_CACHED 0x01000000
182#define MDP_OV_PIPE_SHARE 0x00800000
183#define MDP_DEINTERLACE_ODD 0x00400000
184#define MDP_OV_PLAY_NOWAIT 0x00200000
185#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700186#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530187#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800188#define MDP_BORDERFILL_SUPPORTED 0x00010000
189#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Adrian Salido-Moreno9a8485c2013-02-06 14:08:28 -0800190#define MDP_OV_PIPE_FORCE_DMA 0x00004000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800191#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Sree Sesha Aravind Vadrevu35143132013-03-12 02:32:06 -0700192#define MDP_BWC_EN 0x00000400
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700193#define MDP_DECIMATION_EN 0x00000800
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700194#define MDP_TRANSP_NOP 0xffffffff
195#define MDP_ALPHA_NOP 0xff
196
197#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
198#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
199#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
200#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
201#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
202/* Sentinel: Don't use! */
203#define MDP_FB_PAGE_PROTECTION_INVALID (5)
204/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
205#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700206
207struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700208 uint32_t x;
209 uint32_t y;
210 uint32_t w;
211 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700212};
213
214struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700215 uint32_t width;
216 uint32_t height;
217 uint32_t format;
218 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700219 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700220 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700221};
222
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700223/*
224 * {3x3} + {3} ccs matrix
225 */
226
227#define MDP_CCS_RGB2YUV 0
228#define MDP_CCS_YUV2RGB 1
229
230#define MDP_CCS_SIZE 9
231#define MDP_BV_SIZE 3
232
233struct mdp_ccs {
234 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
235 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
236 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
237};
238
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800239struct mdp_csc {
240 int id;
241 uint32_t csc_mv[9];
242 uint32_t csc_pre_bv[3];
243 uint32_t csc_post_bv[3];
244 uint32_t csc_pre_lv[6];
245 uint32_t csc_post_lv[6];
246};
247
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700248/* The version of the mdp_blit_req structure so that
249 * user applications can selectively decide which functionality
250 * to include
251 */
252
253#define MDP_BLIT_REQ_VERSION 2
254
Daniel Walkerda6df072010-04-23 16:04:20 -0700255struct mdp_blit_req {
256 struct mdp_img src;
257 struct mdp_img dst;
258 struct mdp_rect src_rect;
259 struct mdp_rect dst_rect;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700260 uint32_t alpha;
261 uint32_t transp_mask;
262 uint32_t flags;
263 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700264};
265
266struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700267 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700268 struct mdp_blit_req req[];
269};
270
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700271#define MSMFB_DATA_VERSION 2
272
273struct msmfb_data {
274 uint32_t offset;
275 int memory_id;
276 int id;
277 uint32_t flags;
278 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800279 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700280};
281
282#define MSMFB_NEW_REQUEST -1
283
284struct msmfb_overlay_data {
285 uint32_t id;
286 struct msmfb_data data;
287 uint32_t version_key;
288 struct msmfb_data plane1_data;
289 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700290 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700291};
292
293struct msmfb_img {
294 uint32_t width;
295 uint32_t height;
296 uint32_t format;
297};
298
Vinay Kalia27020d12011-10-14 17:50:29 -0700299#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
300struct msmfb_writeback_data {
301 struct msmfb_data buf_info;
302 struct msmfb_img img;
303};
304
Ken Zhang77ce0192012-08-10 11:27:19 -0400305#define MDP_PP_OPS_ENABLE 0x1
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700306#define MDP_PP_OPS_READ 0x2
307#define MDP_PP_OPS_WRITE 0x4
Ken Zhang77ce0192012-08-10 11:27:19 -0400308#define MDP_PP_OPS_DISABLE 0x8
Ken Zhang824758e2012-08-15 11:02:21 -0400309#define MDP_PP_IGC_FLAG_ROM0 0x10
310#define MDP_PP_IGC_FLAG_ROM1 0x20
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700311
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700312#define MDSS_PP_DSPP_CFG 0x000
313#define MDSS_PP_SSPP_CFG 0x100
314#define MDSS_PP_LM_CFG 0x200
315#define MDSS_PP_WB_CFG 0x300
Ping Li8231ae42013-01-09 20:39:25 -0500316
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700317#define MDSS_PP_ARG_MASK 0x3C00
318#define MDSS_PP_ARG_NUM 4
Carl Vanderlip793aa582013-03-18 10:18:47 -0700319#define MDSS_PP_ARG_SHIFT 10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700320#define MDSS_PP_LOCATION_MASK 0x0300
321#define MDSS_PP_LOGICAL_MASK 0x00FF
Ping Li8231ae42013-01-09 20:39:25 -0500322
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700323#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
324#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
Ping Li8231ae42013-01-09 20:39:25 -0500325#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
326#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
327
328
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700329struct mdp_qseed_cfg {
330 uint32_t table_num;
331 uint32_t ops;
332 uint32_t len;
333 uint32_t *data;
334};
335
Ping Li87cca832013-01-30 18:27:52 -0500336struct mdp_sharp_cfg {
337 uint32_t flags;
338 uint32_t strength;
339 uint32_t edge_thr;
340 uint32_t smooth_thr;
341 uint32_t noise_thr;
342};
343
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700344struct mdp_qseed_cfg_data {
345 uint32_t block;
346 struct mdp_qseed_cfg qseed_data;
347};
348
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800349#define MDP_OVERLAY_PP_CSC_CFG 0x1
350#define MDP_OVERLAY_PP_QSEED_CFG 0x2
351#define MDP_OVERLAY_PP_PA_CFG 0x4
352#define MDP_OVERLAY_PP_IGC_CFG 0x8
Ping Li87cca832013-01-30 18:27:52 -0500353#define MDP_OVERLAY_PP_SHARP_CFG 0x10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700354#define MDP_OVERLAY_PP_HIST_CFG 0x20
Carl Vanderlip57027132013-03-18 13:53:16 -0700355#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700356
357#define MDP_CSC_FLAG_ENABLE 0x1
358#define MDP_CSC_FLAG_YUV_IN 0x2
359#define MDP_CSC_FLAG_YUV_OUT 0x4
360
361struct mdp_csc_cfg {
362 /* flags for enable CSC, toggling RGB,YUV input/output */
363 uint32_t flags;
364 uint32_t csc_mv[9];
365 uint32_t csc_pre_bv[3];
366 uint32_t csc_post_bv[3];
367 uint32_t csc_pre_lv[6];
368 uint32_t csc_post_lv[6];
369};
370
371struct mdp_csc_cfg_data {
372 uint32_t block;
373 struct mdp_csc_cfg csc_data;
374};
375
Ping Li58229242012-11-30 14:05:43 -0500376struct mdp_pa_cfg {
377 uint32_t flags;
378 uint32_t hue_adj;
379 uint32_t sat_adj;
380 uint32_t val_adj;
381 uint32_t cont_adj;
382};
383
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800384struct mdp_igc_lut_data {
385 uint32_t block;
386 uint32_t len, ops;
387 uint32_t *c0_c1_data;
388 uint32_t *c2_data;
389};
390
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700391struct mdp_histogram_cfg {
392 uint32_t ops;
393 uint32_t block;
394 uint8_t frame_cnt;
395 uint8_t bit_mask;
396 uint16_t num_bins;
397};
398
Carl Vanderlip57027132013-03-18 13:53:16 -0700399struct mdp_hist_lut_data {
400 uint32_t block;
401 uint32_t ops;
402 uint32_t len;
403 uint32_t *data;
404};
405
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700406struct mdp_overlay_pp_params {
407 uint32_t config_ops;
408 struct mdp_csc_cfg csc_cfg;
409 struct mdp_qseed_cfg qseed_cfg[2];
Ping Li58229242012-11-30 14:05:43 -0500410 struct mdp_pa_cfg pa_cfg;
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800411 struct mdp_igc_lut_data igc_cfg;
Ping Li87cca832013-01-30 18:27:52 -0500412 struct mdp_sharp_cfg sharp_cfg;
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700413 struct mdp_histogram_cfg hist_cfg;
Carl Vanderlip57027132013-03-18 13:53:16 -0700414 struct mdp_hist_lut_data hist_lut_cfg;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700415};
416
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530417/**
418 * enum mdss_mdp_blend_op - Different blend operations set by userspace
419 *
420 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
421 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
422 * would appear opaque in case fg plane alpha is
423 * 0xff.
424 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has
425 * alpha pre-multiplication done. If fg plane alpha
426 * is less than 0xff, apply modulation as well. This
427 * operation is intended on layers having alpha
428 * channel.
429 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha
430 * pre-multiplied. Apply pre-multiplication. If fg
431 * plane alpha is less than 0xff, apply modulation as
432 * well.
433 * @BLEND_OP_MAX: Used to track maximum blend operation possible by
434 * mdp.
435 */
436enum mdss_mdp_blend_op {
437 BLEND_OP_NOT_DEFINED = 0,
438 BLEND_OP_OPAQUE,
439 BLEND_OP_PREMULTIPLIED,
440 BLEND_OP_COVERAGE,
441 BLEND_OP_MAX,
442};
443
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700444struct mdp_overlay {
445 struct msmfb_img src;
446 struct mdp_rect src_rect;
447 struct mdp_rect dst_rect;
448 uint32_t z_order; /* stage number */
449 uint32_t is_fg; /* control alpha & transp */
450 uint32_t alpha;
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530451 uint32_t blend_op;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700452 uint32_t transp_mask;
453 uint32_t flags;
454 uint32_t id;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700455 uint32_t user_data[7];
456 uint8_t horz_deci;
457 uint8_t vert_deci;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700458 struct mdp_overlay_pp_params overlay_pp_cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700459};
460
461struct msmfb_overlay_3d {
462 uint32_t is_3d;
463 uint32_t width;
464 uint32_t height;
465};
466
467
468struct msmfb_overlay_blt {
469 uint32_t enable;
470 uint32_t offset;
471 uint32_t width;
472 uint32_t height;
473 uint32_t bpp;
474};
475
476struct mdp_histogram {
477 uint32_t frame_cnt;
478 uint32_t bin_cnt;
479 uint32_t *r;
480 uint32_t *g;
481 uint32_t *b;
482};
483
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700484enum {
485 DISPLAY_MISR_EDP,
486 DISPLAY_MISR_DSI0,
487 DISPLAY_MISR_DSI1,
488 DISPLAY_MISR_HDMI,
489 DISPLAY_MISR_LCDC,
490 DISPLAY_MISR_ATV,
491 DISPLAY_MISR_DSI_CMD,
492 DISPLAY_MISR_MAX
493};
494
495enum {
496 MISR_OP_NONE,
497 MISR_OP_SFM,
498 MISR_OP_MFM,
499 MISR_OP_BM,
500 MISR_OP_MAX
501};
502
503struct mdp_misr {
504 uint32_t block_id;
505 uint32_t frame_count;
506 uint32_t crc_op_mode;
507 uint32_t crc_value[32];
508};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800509
510/*
511
Ken Zhang6a431632012-08-08 16:46:22 -0400512 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800513
514 MDP_BLOCK_RESERVED is provided for backward compatibility and is
515 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
516 instead.
517
Ken Zhang6a431632012-08-08 16:46:22 -0400518 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
519 same for others.
520
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800521*/
522
523enum {
524 MDP_BLOCK_RESERVED = 0,
525 MDP_BLOCK_OVERLAY_0,
526 MDP_BLOCK_OVERLAY_1,
527 MDP_BLOCK_VG_1,
528 MDP_BLOCK_VG_2,
529 MDP_BLOCK_RGB_1,
530 MDP_BLOCK_RGB_2,
531 MDP_BLOCK_DMA_P,
532 MDP_BLOCK_DMA_S,
533 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700534 MDP_BLOCK_OVERLAY_2,
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700535 MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
Ken Zhang6a431632012-08-08 16:46:22 -0400536 MDP_LOGICAL_BLOCK_DISP_1,
537 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800538 MDP_BLOCK_MAX,
539};
540
Carl Vanderlipba093a22011-11-22 13:59:59 -0800541/*
542 * mdp_histogram_start_req is used to provide the parameters for
543 * histogram start request
544 */
545
546struct mdp_histogram_start_req {
547 uint32_t block;
548 uint8_t frame_cnt;
549 uint8_t bit_mask;
Carl Vanderlip16316322012-10-08 16:47:34 -0700550 uint16_t num_bins;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800551};
552
553/*
554 * mdp_histogram_data is used to return the histogram data, once
555 * the histogram is done/stopped/cance
556 */
557
558struct mdp_histogram_data {
559 uint32_t block;
Ken Zhang0f523bd2012-08-23 11:14:03 -0400560 uint32_t bin_cnt;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800561 uint32_t *c0;
562 uint32_t *c1;
563 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800564 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800565};
566
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800567struct mdp_pcc_coeff {
568 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
569};
570
571struct mdp_pcc_cfg_data {
572 uint32_t block;
573 uint32_t ops;
574 struct mdp_pcc_coeff r, g, b;
575};
576
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400577#define MDP_GAMUT_TABLE_NUM 8
578
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800579enum {
580 mdp_lut_igc,
581 mdp_lut_pgc,
582 mdp_lut_hist,
583 mdp_lut_max,
584};
585
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800586struct mdp_ar_gc_lut_data {
587 uint32_t x_start;
588 uint32_t slope;
589 uint32_t offset;
590};
591
592struct mdp_pgc_lut_data {
593 uint32_t block;
594 uint32_t flags;
595 uint8_t num_r_stages;
596 uint8_t num_g_stages;
597 uint8_t num_b_stages;
598 struct mdp_ar_gc_lut_data *r_data;
599 struct mdp_ar_gc_lut_data *g_data;
600 struct mdp_ar_gc_lut_data *b_data;
601};
602
603
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800604struct mdp_lut_cfg_data {
605 uint32_t lut_type;
606 union {
607 struct mdp_igc_lut_data igc_lut_data;
608 struct mdp_pgc_lut_data pgc_lut_data;
609 struct mdp_hist_lut_data hist_lut_data;
610 } data;
611};
612
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700613struct mdp_bl_scale_data {
614 uint32_t min_lvl;
615 uint32_t scale;
616};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700617
Ken Zhang77ce0192012-08-10 11:27:19 -0400618struct mdp_pa_cfg_data {
619 uint32_t block;
Ping Li58229242012-11-30 14:05:43 -0500620 struct mdp_pa_cfg pa_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400621};
622
Ken Zhang7fb85772012-08-18 14:51:33 -0400623struct mdp_dither_cfg_data {
624 uint32_t block;
625 uint32_t flags;
626 uint32_t g_y_depth;
627 uint32_t r_cr_depth;
628 uint32_t b_cb_depth;
629};
630
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400631struct mdp_gamut_cfg_data {
632 uint32_t block;
633 uint32_t flags;
634 uint32_t gamut_first;
635 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
636 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
637 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
638 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
639};
640
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700641struct mdp_calib_config_data {
642 uint32_t ops;
643 uint32_t addr;
644 uint32_t data;
645};
646
Arpita Banerjee676eea22013-06-04 19:43:24 -0700647struct mdp_calib_config_buffer {
648 uint32_t ops;
649 uint32_t size;
650 uint32_t *buffer;
651};
652
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700653struct mdp_calib_dcm_state {
654 uint32_t ops;
655 uint32_t dcm_state;
656};
657
658enum {
659 DCM_UNINIT,
660 DCM_UNBLANK,
661 DCM_ENTER,
662 DCM_EXIT,
663 DCM_BLANK,
664};
665
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700666#define MDSS_MAX_BL_BRIGHTNESS 255
667#define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1)
668
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700669#define MDSS_AD_MODE_AUTO_BL 0x0
670#define MDSS_AD_MODE_AUTO_STR 0x1
671#define MDSS_AD_MODE_TARG_STR 0x3
672#define MDSS_AD_MODE_MAN_STR 0x7
Carl Vanderlip819c5092013-05-19 12:08:33 -0700673#define MDSS_AD_MODE_CALIB 0xF
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700674
675#define MDP_PP_AD_INIT 0x10
676#define MDP_PP_AD_CFG 0x20
677
678struct mdss_ad_init {
679 uint32_t asym_lut[33];
680 uint32_t color_corr_lut[33];
681 uint8_t i_control[2];
682 uint16_t black_lvl;
683 uint16_t white_lvl;
684 uint8_t var;
685 uint8_t limit_ampl;
686 uint8_t i_dither;
687 uint8_t slope_max;
688 uint8_t slope_min;
689 uint8_t dither_ctl;
690 uint8_t format;
691 uint8_t auto_size;
692 uint16_t frame_w;
693 uint16_t frame_h;
694 uint8_t logo_v;
695 uint8_t logo_h;
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700696 uint32_t bl_lin_len;
697 uint32_t *bl_lin;
698 uint32_t *bl_lin_inv;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700699};
700
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700701#define MDSS_AD_BL_CTRL_MODE_EN 1
702#define MDSS_AD_BL_CTRL_MODE_DIS 0
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700703struct mdss_ad_cfg {
704 uint32_t mode;
705 uint32_t al_calib_lut[33];
706 uint16_t backlight_min;
707 uint16_t backlight_max;
708 uint16_t backlight_scale;
709 uint16_t amb_light_min;
710 uint16_t filter[2];
711 uint16_t calib[4];
712 uint8_t strength_limit;
713 uint8_t t_filter_recursion;
Carl Vanderlip956360e2013-04-04 20:57:17 -0700714 uint16_t stab_itr;
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700715 uint32_t bl_ctrl_mode;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700716};
717
718/* ops uses standard MDP_PP_* flags */
719struct mdss_ad_init_cfg {
720 uint32_t ops;
721 union {
722 struct mdss_ad_init init;
723 struct mdss_ad_cfg cfg;
724 } params;
725};
726
727/* mode uses MDSS_AD_MODE_* flags */
728struct mdss_ad_input {
729 uint32_t mode;
730 union {
731 uint32_t amb_light;
732 uint32_t strength;
Carl Vanderlip819c5092013-05-19 12:08:33 -0700733 uint32_t calib_bl;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700734 } in;
Carl Vanderlip16e79532013-04-02 11:12:16 -0700735 uint32_t output;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700736};
737
Carl Vanderlipa088b7c2013-05-17 13:52:53 -0700738#define MDSS_CALIB_MODE_BL 0x1
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700739struct mdss_calib_cfg {
740 uint32_t ops;
741 uint32_t calib_mask;
742};
743
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800744enum {
745 mdp_op_pcc_cfg,
746 mdp_op_csc_cfg,
747 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700748 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700749 mdp_bl_scale_cfg,
Ken Zhang77ce0192012-08-10 11:27:19 -0400750 mdp_op_pa_cfg,
Ken Zhang7fb85772012-08-18 14:51:33 -0400751 mdp_op_dither_cfg,
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400752 mdp_op_gamut_cfg,
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700753 mdp_op_calib_cfg,
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700754 mdp_op_ad_cfg,
755 mdp_op_ad_input,
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700756 mdp_op_calib_mode,
Arpita Banerjee676eea22013-06-04 19:43:24 -0700757 mdp_op_calib_buffer,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700758 mdp_op_calib_dcm_state,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800759 mdp_op_max,
760};
761
Pawan Kumar9807ea12013-02-14 18:12:02 +0530762enum {
763 WB_FORMAT_NV12,
764 WB_FORMAT_RGB_565,
765 WB_FORMAT_RGB_888,
766 WB_FORMAT_xRGB_8888,
767 WB_FORMAT_ARGB_8888,
Pawan Kumaree811932013-07-09 15:45:01 +0530768 WB_FORMAT_BGRA_8888,
769 WB_FORMAT_BGRX_8888,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530770 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
771};
772
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800773struct msmfb_mdp_pp {
774 uint32_t op;
775 union {
776 struct mdp_pcc_cfg_data pcc_cfg_data;
777 struct mdp_csc_cfg_data csc_cfg_data;
778 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700779 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700780 struct mdp_bl_scale_data bl_scale_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400781 struct mdp_pa_cfg_data pa_cfg_data;
Ken Zhang7fb85772012-08-18 14:51:33 -0400782 struct mdp_dither_cfg_data dither_cfg_data;
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400783 struct mdp_gamut_cfg_data gamut_cfg_data;
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700784 struct mdp_calib_config_data calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700785 struct mdss_ad_init_cfg ad_init_cfg;
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700786 struct mdss_calib_cfg mdss_calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700787 struct mdss_ad_input ad_input;
Arpita Banerjee676eea22013-06-04 19:43:24 -0700788 struct mdp_calib_config_buffer calib_buffer;
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700789 struct mdp_calib_dcm_state calib_dcm;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800790 } data;
791};
792
Manoj Raoa8e39d92013-02-16 08:47:21 -0800793#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
Ken Zhang5cf85c02012-08-23 19:32:52 -0700794enum {
795 metadata_op_none,
796 metadata_op_base_blend,
Ken Zhang420dd202013-01-08 14:28:20 -0500797 metadata_op_frame_rate,
Manoj Raoa8e39d92013-02-16 08:47:21 -0800798 metadata_op_vic,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530799 metadata_op_wb_format,
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800800 metadata_op_get_caps,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700801 metadata_op_crc,
Ken Zhang5cf85c02012-08-23 19:32:52 -0700802 metadata_op_max
803};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800804
Ken Zhang5cf85c02012-08-23 19:32:52 -0700805struct mdp_blend_cfg {
806 uint32_t is_premultiplied;
807};
808
Pawan Kumar9807ea12013-02-14 18:12:02 +0530809struct mdp_mixer_cfg {
810 uint32_t writeback_format;
811 uint32_t alpha;
812};
813
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800814struct mdss_hw_caps {
815 uint32_t mdp_rev;
816 uint8_t rgb_pipes;
817 uint8_t vig_pipes;
818 uint8_t dma_pipes;
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700819 uint32_t features;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800820};
821
Ken Zhang5cf85c02012-08-23 19:32:52 -0700822struct msmfb_metadata {
823 uint32_t op;
824 uint32_t flags;
825 union {
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700826 struct mdp_misr misr_request;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700827 struct mdp_blend_cfg blend_cfg;
Pawan Kumar9807ea12013-02-14 18:12:02 +0530828 struct mdp_mixer_cfg mixer_cfg;
Ken Zhang420dd202013-01-08 14:28:20 -0500829 uint32_t panel_frame_rate;
Manoj Raoa8e39d92013-02-16 08:47:21 -0800830 uint32_t video_info_code;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800831 struct mdss_hw_caps caps;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700832 } data;
833};
Ken Zhang5295d802012-11-07 18:33:16 -0500834
Adrian Salido-Moreno1a74a492013-05-11 21:24:43 -0700835#define MDP_MAX_FENCE_FD 32
Ken Zhang5295d802012-11-07 18:33:16 -0500836#define MDP_BUF_SYNC_FLAG_WAIT 1
837
838struct mdp_buf_sync {
839 uint32_t flags;
840 uint32_t acq_fen_fd_cnt;
841 int *acq_fen_fd;
842 int *rel_fen_fd;
843};
844
Terence Hampson3e636aa2013-05-08 19:01:51 -0400845struct mdp_async_blit_req_list {
846 struct mdp_buf_sync sync;
847 uint32_t count;
848 struct mdp_blit_req req[];
849};
850
Ken Zhang4e83b932012-12-02 21:15:47 -0500851#define MDP_DISPLAY_COMMIT_OVERLAY 1
Ken Zhang5e8588d2012-10-01 11:46:42 -0700852struct mdp_buf_fence {
853 uint32_t flags;
854 uint32_t acq_fen_fd_cnt;
855 int acq_fen_fd[MDP_MAX_FENCE_FD];
856 int rel_fen_fd[MDP_MAX_FENCE_FD];
857};
858
Ken Zhang4e83b932012-12-02 21:15:47 -0500859
860struct mdp_display_commit {
861 uint32_t flags;
862 uint32_t wait_for_finish;
863 struct fb_var_screeninfo var;
Ken Zhang5e8588d2012-10-01 11:46:42 -0700864 struct mdp_buf_fence buf_fence;
Ken Zhang4e83b932012-12-02 21:15:47 -0500865};
866
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700867struct mdp_page_protection {
868 uint32_t page_protection;
869};
870
kuogee hsieh405dc302011-07-21 15:06:59 -0700871
872struct mdp_mixer_info {
873 int pndx;
874 int pnum;
875 int ptype;
876 int mixer_num;
877 int z_order;
878};
879
880#define MAX_PIPE_PER_MIXER 4
881
882struct msmfb_mixer_info_req {
883 int mixer_num;
884 int cnt;
885 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
886};
887
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700888enum {
889 DISPLAY_SUBSYSTEM_ID,
890 ROTATOR_SUBSYSTEM_ID,
891};
kuogee hsieh405dc302011-07-21 15:06:59 -0700892
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800893enum {
894 MDP_IOMMU_DOMAIN_CP,
895 MDP_IOMMU_DOMAIN_NS,
896};
897
Deva Ramasubramanian166b0982013-01-25 20:11:41 -0800898enum {
899 MDP_WRITEBACK_MIRROR_OFF,
900 MDP_WRITEBACK_MIRROR_ON,
901 MDP_WRITEBACK_MIRROR_PAUSE,
902 MDP_WRITEBACK_MIRROR_RESUME,
903};
904
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700905#ifdef __KERNEL__
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800906int msm_fb_get_iommu_domain(struct fb_info *info, int domain);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700907/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700908int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
909 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -0700910struct fb_info *msm_fb_get_writeback_fb(void);
911int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800912int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700913int msm_fb_writeback_queue_buffer(struct fb_info *info,
914 struct msmfb_data *data);
915int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
916 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800917int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700918int msm_fb_writeback_terminate(struct fb_info *info);
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800919int msm_fb_writeback_set_secure(struct fb_info *info, int enable);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700920#endif
921
922#endif /*_MSM_MDP_H_*/