sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | e6c53e0 | 2011-10-23 07:33:43 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2011 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 37 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 41 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 42 | #include "libvex_guest_ppc64.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 43 | #include "libvex_guest_s390x.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 44 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 45 | #include "main_globals.h" |
| 46 | #include "main_util.h" |
| 47 | #include "host_generic_regs.h" |
| 48 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 49 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 50 | #include "host_x86_defs.h" |
| 51 | #include "host_amd64_defs.h" |
| 52 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 53 | #include "host_arm_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 54 | #include "host_s390_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 55 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 56 | #include "guest_generic_bb_to_IR.h" |
| 57 | #include "guest_x86_defs.h" |
| 58 | #include "guest_amd64_defs.h" |
| 59 | #include "guest_arm_defs.h" |
| 60 | #include "guest_ppc_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 61 | #include "guest_s390_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 62 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 63 | #include "host_generic_simd128.h" |
| 64 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 65 | |
| 66 | /* This file contains the top level interface to the library. */ |
| 67 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 68 | /* --------- fwds ... --------- */ |
| 69 | |
| 70 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
| 71 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
| 72 | |
| 73 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 74 | /* --------- Initialise the library. --------- */ |
| 75 | |
| 76 | /* Exported to library client. */ |
| 77 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 78 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 79 | { |
| 80 | vcon->iropt_verbosity = 0; |
| 81 | vcon->iropt_level = 2; |
| 82 | vcon->iropt_precise_memory_exns = False; |
| 83 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 84 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 85 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 86 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | |
| 90 | /* Exported to library client. */ |
| 91 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 92 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 93 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 94 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 95 | void (*failure_exit) ( void ), |
| 96 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 97 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 98 | /* debug paranoia level */ |
| 99 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 100 | /* Are we supporting valgrind checking? */ |
| 101 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 102 | /* Control ... */ |
| 103 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 104 | ) |
| 105 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 106 | /* First off, do enough minimal setup so that the following |
| 107 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 108 | vex_failure_exit = failure_exit; |
| 109 | vex_log_bytes = log_bytes; |
| 110 | |
| 111 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 112 | vassert(!vex_initdone); |
| 113 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 114 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 115 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 116 | |
| 117 | vassert(vcon->iropt_verbosity >= 0); |
| 118 | vassert(vcon->iropt_level >= 0); |
| 119 | vassert(vcon->iropt_level <= 2); |
| 120 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 121 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 122 | vassert(vcon->guest_max_insns >= 1); |
| 123 | vassert(vcon->guest_max_insns <= 100); |
| 124 | vassert(vcon->guest_chase_thresh >= 0); |
| 125 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 126 | vassert(vcon->guest_chase_cond == True |
| 127 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 128 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 129 | /* Check that Vex has been built with sizes of basic types as |
| 130 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 131 | a serious configuration error and should be corrected |
| 132 | immediately. If any of these assertions fail you can fully |
| 133 | expect Vex not to work properly, if at all. */ |
| 134 | |
| 135 | vassert(1 == sizeof(UChar)); |
| 136 | vassert(1 == sizeof(Char)); |
| 137 | vassert(2 == sizeof(UShort)); |
| 138 | vassert(2 == sizeof(Short)); |
| 139 | vassert(4 == sizeof(UInt)); |
| 140 | vassert(4 == sizeof(Int)); |
| 141 | vassert(8 == sizeof(ULong)); |
| 142 | vassert(8 == sizeof(Long)); |
| 143 | vassert(4 == sizeof(Float)); |
| 144 | vassert(8 == sizeof(Double)); |
| 145 | vassert(1 == sizeof(Bool)); |
| 146 | vassert(4 == sizeof(Addr32)); |
| 147 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 148 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 149 | vassert(16 == sizeof(V128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 150 | |
| 151 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 152 | vassert(sizeof(void*) == sizeof(int*)); |
| 153 | vassert(sizeof(void*) == sizeof(HWord)); |
| 154 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 155 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 156 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 157 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 158 | /* These take a lot of space, so make sure we don't have |
| 159 | any unnoticed size regressions. */ |
| 160 | if (VEX_HOST_WORDSIZE == 4) { |
| 161 | vassert(sizeof(IRExpr) == 24); |
| 162 | vassert(sizeof(IRStmt) == 20 /* x86 */ |
| 163 | || sizeof(IRStmt) == 24 /* arm */); |
| 164 | } else { |
| 165 | vassert(sizeof(IRExpr) == 48); |
| 166 | vassert(sizeof(IRStmt) == 40); |
| 167 | } |
| 168 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 169 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 170 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 171 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 172 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 173 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 174 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | |
| 178 | /* --------- Make a translation. --------- */ |
| 179 | |
| 180 | /* Exported to library client. */ |
| 181 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 182 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 183 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 184 | /* This the bundle of functions we need to do the back-end stuff |
| 185 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 186 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 187 | HReg* available_real_regs; |
| 188 | Int n_available_real_regs; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 189 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 190 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 191 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 192 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 193 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 194 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
| 195 | void (*ppInstr) ( HInstr*, Bool ); |
| 196 | void (*ppReg) ( HReg ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 197 | HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo*, |
| 198 | Int, Int, Bool, Bool, Addr64 ); |
| 199 | Int (*emit) ( /*MB_MOD*/Bool*, |
| 200 | UChar*, Int, HInstr*, Bool, |
| 201 | void*, void*, void*, void* ); |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 202 | IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 203 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 204 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 205 | DisOneInstrFn disInstrFn; |
| 206 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 207 | VexGuestLayout* guest_layout; |
| 208 | Bool host_is_bigendian = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 209 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 210 | HInstrArray* vcode; |
| 211 | HInstrArray* rcode; |
| 212 | Int i, j, k, out_used, guest_sizeB; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 213 | Int offB_TISTART, offB_TILEN, offB_GUEST_IP, szB_GUEST_IP; |
| 214 | Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; |
| 215 | UChar insn_bytes[64]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 216 | IRType guest_word_type; |
| 217 | IRType host_word_type; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 218 | Bool mode64, chainingAllowed; |
| 219 | Addr64 max_ga; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 220 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 221 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 222 | available_real_regs = NULL; |
| 223 | n_available_real_regs = 0; |
| 224 | isMove = NULL; |
| 225 | getRegUsage = NULL; |
| 226 | mapRegs = NULL; |
| 227 | genSpill = NULL; |
| 228 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 229 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 230 | ppInstr = NULL; |
| 231 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 232 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 233 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 234 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 235 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 236 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 237 | guest_word_type = Ity_INVALID; |
| 238 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 239 | offB_TISTART = 0; |
| 240 | offB_TILEN = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 241 | offB_GUEST_IP = 0; |
| 242 | szB_GUEST_IP = 0; |
| 243 | offB_HOST_EvC_COUNTER = 0; |
| 244 | offB_HOST_EvC_FAILADDR = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 245 | mode64 = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 246 | chainingAllowed = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 247 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 248 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 249 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 250 | vassert(vex_initdone); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 251 | vassert(vta->needs_self_check != NULL); |
| 252 | vassert(vta->disp_cp_xassisted != NULL); |
| 253 | /* Both the chainers and the indir are either NULL or non-NULL. */ |
| 254 | if (vta->disp_cp_chain_me_to_slowEP != NULL) { |
| 255 | vassert(vta->disp_cp_chain_me_to_fastEP != NULL); |
| 256 | vassert(vta->disp_cp_xindir != NULL); |
| 257 | chainingAllowed = True; |
| 258 | } else { |
| 259 | vassert(vta->disp_cp_chain_me_to_fastEP == NULL); |
| 260 | vassert(vta->disp_cp_xindir == NULL); |
| 261 | } |
florian | 2eeeb9b | 2011-09-23 18:03:21 +0000 | [diff] [blame] | 262 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 263 | vexSetAllocModeTEMP_and_clear(); |
| 264 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 265 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 266 | /* First off, check that the guest and host insn sets |
| 267 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 268 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 269 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 270 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 271 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 272 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 273 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 274 | &available_real_regs ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 275 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 276 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 277 | getRegUsage_X86Instr; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 278 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 279 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 280 | genSpill_X86; |
| 281 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 282 | genReload_X86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 283 | directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; |
| 284 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
| 285 | ppReg = (void(*)(HReg)) ppHRegX86; |
| 286 | iselSB = iselSB_X86; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 287 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 288 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 289 | emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 290 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 291 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 292 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 293 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 294 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 295 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 296 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 297 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 298 | &available_real_regs ); |
| 299 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 300 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 301 | getRegUsage_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 302 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 303 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 304 | genSpill_AMD64; |
| 305 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 306 | genReload_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 307 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 308 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 309 | iselSB = iselSB_AMD64; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 310 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 311 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 312 | emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 313 | host_is_bigendian = False; |
| 314 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 315 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 316 | break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 317 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 318 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 319 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 320 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 321 | &available_real_regs, mode64 ); |
| 322 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 323 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 324 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 325 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 326 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 327 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 328 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 329 | iselSB = iselSB_PPC; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 330 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 331 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 332 | emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 333 | host_is_bigendian = True; |
| 334 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 335 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 336 | break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 337 | #if 0 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 338 | case VexArchPPC64: |
| 339 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 340 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 341 | &available_real_regs, mode64 ); |
| 342 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 343 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 344 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 345 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 346 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 347 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 348 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 349 | iselSB = iselSB_PPC; |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 350 | emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*)) |
| 351 | emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 352 | host_is_bigendian = True; |
| 353 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 354 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 355 | /* return-to-dispatcher scheme */ |
| 356 | vassert(vta->dispatch_unassisted == NULL); |
| 357 | vassert(vta->dispatch_assisted == NULL); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 358 | break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 359 | #endif |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 360 | case VexArchS390X: |
| 361 | mode64 = True; |
| 362 | getAllocableRegs_S390 ( &n_available_real_regs, |
| 363 | &available_real_regs, mode64 ); |
| 364 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_S390Instr; |
| 365 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_S390Instr; |
| 366 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_S390Instr; |
| 367 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_S390; |
| 368 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_S390; |
| 369 | ppInstr = (void(*)(HInstr*, Bool)) ppS390Instr; |
| 370 | ppReg = (void(*)(HReg)) ppHRegS390; |
| 371 | iselSB = iselSB_S390; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 372 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 373 | void*,void*,void*,void*)) emit_S390Instr; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 374 | host_is_bigendian = True; |
| 375 | host_word_type = Ity_I64; |
| 376 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 377 | break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 378 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 379 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 380 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 381 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 382 | &available_real_regs ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 383 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; |
| 384 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; |
| 385 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; |
| 386 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; |
| 387 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; |
| 388 | ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; |
| 389 | ppReg = (void(*)(HReg)) ppHRegARM; |
| 390 | iselSB = iselSB_ARM; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 391 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 392 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 393 | emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 394 | host_is_bigendian = False; |
| 395 | host_word_type = Ity_I32; |
| 396 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 397 | break; |
| 398 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 399 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 400 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 401 | } |
| 402 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 403 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 404 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 405 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 406 | case VexArchX86: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 407 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
| 408 | disInstrFn = disInstr_X86; |
| 409 | specHelper = guest_x86_spechelper; |
| 410 | guest_sizeB = sizeof(VexGuestX86State); |
| 411 | guest_word_type = Ity_I32; |
| 412 | guest_layout = &x86guest_layout; |
| 413 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 414 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
| 415 | offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); |
| 416 | szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); |
| 417 | offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); |
| 418 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 419 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 420 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 421 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); |
| 422 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
| 423 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 424 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 425 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 426 | case VexArchAMD64: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 427 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 428 | disInstrFn = disInstr_AMD64; |
| 429 | specHelper = guest_amd64_spechelper; |
| 430 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 431 | guest_word_type = Ity_I64; |
| 432 | guest_layout = &amd64guest_layout; |
| 433 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 434 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
| 435 | offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); |
| 436 | szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); |
| 437 | offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); |
| 438 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 439 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 440 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 441 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 442 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
| 443 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 444 | break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 445 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 446 | case VexArchPPC32: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 447 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 448 | disInstrFn = disInstr_PPC; |
| 449 | specHelper = guest_ppc32_spechelper; |
| 450 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 451 | guest_word_type = Ity_I32; |
| 452 | guest_layout = &ppc32Guest_layout; |
| 453 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 454 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
| 455 | offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); |
| 456 | szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); |
| 457 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); |
| 458 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 459 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 460 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 461 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 462 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
| 463 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 464 | break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 465 | #if 0 |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 466 | case VexArchPPC64: |
| 467 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 468 | disInstrFn = disInstr_PPC; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 469 | specHelper = guest_ppc64_spechelper; |
| 470 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 471 | guest_word_type = Ity_I64; |
| 472 | guest_layout = &ppc64Guest_layout; |
| 473 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 474 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 475 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 476 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 477 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
| 478 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 479 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 480 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 481 | break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 482 | #endif |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 483 | case VexArchS390X: |
| 484 | preciseMemExnsFn = guest_s390x_state_requires_precise_mem_exns; |
| 485 | disInstrFn = disInstr_S390; |
| 486 | specHelper = guest_s390x_spechelper; |
| 487 | guest_sizeB = sizeof(VexGuestS390XState); |
| 488 | guest_word_type = Ity_I64; |
| 489 | guest_layout = &s390xGuest_layout; |
| 490 | offB_TISTART = offsetof(VexGuestS390XState,guest_TISTART); |
| 491 | offB_TILEN = offsetof(VexGuestS390XState,guest_TILEN); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 492 | offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); |
| 493 | szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); |
| 494 | offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); |
| 495 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 496 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); |
| 497 | vassert(0 == sizeof(VexGuestS390XState) % 16); |
| 498 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8); |
| 499 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_TILEN ) == 8); |
| 500 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); |
| 501 | break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 502 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 503 | case VexArchARM: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 504 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 505 | disInstrFn = disInstr_ARM; |
| 506 | specHelper = guest_arm_spechelper; |
| 507 | guest_sizeB = sizeof(VexGuestARMState); |
| 508 | guest_word_type = Ity_I32; |
| 509 | guest_layout = &armGuest_layout; |
| 510 | offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); |
| 511 | offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); |
| 512 | offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); |
| 513 | szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); |
| 514 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); |
| 515 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 516 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
| 517 | vassert(0 == sizeof(VexGuestARMState) % 16); |
| 518 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); |
| 519 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); |
| 520 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 521 | break; |
| 522 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 523 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 524 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 525 | } |
| 526 | |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 527 | /* Set up result struct. */ |
| 528 | VexTranslateResult res; |
| 529 | res.status = VexTransOK; |
| 530 | res.n_sc_extents = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 531 | res.offs_profInc = -1; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 532 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 533 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 534 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 535 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 536 | we are simulating one flavour of an architecture a different |
| 537 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 538 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 539 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 540 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 541 | vexAllocSanityCheck(); |
| 542 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 543 | if (vex_traceflags & VEX_TRACE_FE) |
| 544 | vex_printf("\n------------------------" |
| 545 | " Front end " |
| 546 | "------------------------\n\n"); |
| 547 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 548 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 549 | &res.n_sc_extents, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 550 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 551 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 552 | vta->guest_bytes, |
| 553 | vta->guest_bytes_addr, |
| 554 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 555 | host_is_bigendian, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 556 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 557 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 558 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 559 | guest_word_type, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 560 | vta->needs_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 561 | vta->preamble_function, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 562 | offB_TISTART, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 563 | offB_TILEN, |
| 564 | offB_GUEST_IP, |
| 565 | szB_GUEST_IP ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 566 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 567 | vexAllocSanityCheck(); |
| 568 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 569 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 570 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 571 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 572 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 573 | res.status = VexTransAccessFail; return res; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 574 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 575 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 576 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 577 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 578 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 579 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 580 | } |
| 581 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 582 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 583 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 584 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 585 | vex_printf("can't show code due to extents > 1\n"); |
| 586 | } else { |
| 587 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 588 | UChar* p = (UChar*)vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 589 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 590 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 591 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 592 | guest_bytes_read ); |
| 593 | for (i = 0; i < guest_bytes_read; i++) { |
| 594 | UInt b = (UInt)p[i]; |
| 595 | vex_printf(" %02x", b ); |
| 596 | sum = (sum << 1) ^ b; |
| 597 | } |
| 598 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 599 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 600 | } |
| 601 | |
| 602 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 603 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 604 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 605 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 606 | vexAllocSanityCheck(); |
| 607 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 608 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 609 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 610 | vta->guest_bytes_addr, |
| 611 | vta->arch_guest ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 612 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 613 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 614 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 615 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 616 | vex_printf("\n------------------------" |
| 617 | " After pre-instr IR optimisation " |
| 618 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 619 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 620 | vex_printf("\n"); |
| 621 | } |
| 622 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 623 | vexAllocSanityCheck(); |
| 624 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 625 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 626 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 627 | irsb = vta->instrument1(vta->callback_opaque, |
| 628 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 629 | vta->guest_extents, |
| 630 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 631 | vexAllocSanityCheck(); |
| 632 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 633 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 634 | irsb = vta->instrument2(vta->callback_opaque, |
| 635 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 636 | vta->guest_extents, |
| 637 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 638 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 639 | if (vex_traceflags & VEX_TRACE_INST) { |
| 640 | vex_printf("\n------------------------" |
| 641 | " After instrumentation " |
| 642 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 643 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 644 | vex_printf("\n"); |
| 645 | } |
| 646 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 647 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 648 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 649 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 650 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 651 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 652 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 653 | do_deadcode_BB( irsb ); |
| 654 | irsb = cprop_BB( irsb ); |
| 655 | do_deadcode_BB( irsb ); |
| 656 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 657 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 658 | } |
| 659 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 660 | vexAllocSanityCheck(); |
| 661 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 662 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 663 | vex_printf("\n------------------------" |
| 664 | " After post-instr IR optimisation " |
| 665 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 666 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 667 | vex_printf("\n"); |
| 668 | } |
| 669 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 670 | /* Turn it into virtual-registerised code. Build trees -- this |
| 671 | also throws away any dead bindings. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 672 | max_ga = ado_treebuild_BB( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 673 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 674 | if (vta->finaltidy) { |
| 675 | irsb = vta->finaltidy(irsb); |
| 676 | } |
| 677 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 678 | vexAllocSanityCheck(); |
| 679 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 680 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 681 | vex_printf("\n------------------------" |
| 682 | " After tree-building " |
| 683 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 684 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 685 | vex_printf("\n"); |
| 686 | } |
| 687 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 688 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 689 | if (0) { |
| 690 | *(vta->host_bytes_used) = 0; |
| 691 | res.status = VexTransOK; return res; |
| 692 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 693 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 694 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 695 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 696 | vex_printf("\n------------------------" |
| 697 | " Instruction selection " |
| 698 | "------------------------\n"); |
| 699 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 700 | /* No guest has its IP field at offset zero. If this fails it |
| 701 | means some transformation pass somewhere failed to update/copy |
| 702 | irsb->offsIP properly. */ |
| 703 | vassert(irsb->offsIP >= 16); |
| 704 | |
| 705 | vcode = iselSB ( irsb, vta->arch_host, |
| 706 | &vta->archinfo_host, |
| 707 | &vta->abiinfo_both, |
| 708 | offB_HOST_EvC_COUNTER, |
| 709 | offB_HOST_EvC_FAILADDR, |
| 710 | chainingAllowed, |
| 711 | vta->addProfInc, |
| 712 | max_ga ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 713 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 714 | vexAllocSanityCheck(); |
| 715 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 716 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 717 | vex_printf("\n"); |
| 718 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 719 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 720 | for (i = 0; i < vcode->arr_used; i++) { |
| 721 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 722 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 723 | vex_printf("\n"); |
| 724 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 725 | vex_printf("\n"); |
| 726 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 727 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 728 | /* Register allocate. */ |
| 729 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 730 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 731 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 732 | genSpill, genReload, directReload, |
| 733 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 734 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 735 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 736 | vexAllocSanityCheck(); |
| 737 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 738 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 739 | vex_printf("\n------------------------" |
| 740 | " Register-allocated code " |
| 741 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 742 | for (i = 0; i < rcode->arr_used; i++) { |
| 743 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 744 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 745 | vex_printf("\n"); |
| 746 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 747 | vex_printf("\n"); |
| 748 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 749 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 750 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 751 | if (0) { |
| 752 | *(vta->host_bytes_used) = 0; |
| 753 | res.status = VexTransOK; return res; |
| 754 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 755 | /* end HACK */ |
| 756 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 757 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 758 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 759 | vex_printf("\n------------------------" |
| 760 | " Assembly " |
| 761 | "------------------------\n\n"); |
| 762 | } |
| 763 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 764 | out_used = 0; /* tracks along the host_bytes array */ |
| 765 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 766 | HInstr* hi = rcode->arr[i]; |
| 767 | Bool hi_isProfInc = False; |
| 768 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
| 769 | ppInstr(hi, mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 770 | vex_printf("\n"); |
| 771 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 772 | j = emit( &hi_isProfInc, |
| 773 | insn_bytes, sizeof insn_bytes, hi, mode64, |
| 774 | vta->disp_cp_chain_me_to_slowEP, |
| 775 | vta->disp_cp_chain_me_to_fastEP, |
| 776 | vta->disp_cp_xindir, |
| 777 | vta->disp_cp_xassisted ); |
| 778 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 779 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 780 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 781 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 782 | else |
| 783 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 784 | vex_printf("\n\n"); |
| 785 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 786 | if (UNLIKELY(out_used + j > vta->host_bytes_size)) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 787 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 788 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 789 | res.status = VexTransOutputFull; |
| 790 | return res; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 791 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 792 | if (UNLIKELY(hi_isProfInc)) { |
| 793 | vassert(vta->addProfInc); /* else where did it come from? */ |
| 794 | vassert(res.offs_profInc == -1); /* there can be only one (tm) */ |
| 795 | vassert(out_used >= 0); |
| 796 | res.offs_profInc = out_used; |
| 797 | } |
| 798 | { UChar* dst = &vta->host_bytes[out_used]; |
| 799 | for (k = 0; k < j; k++) { |
| 800 | dst[k] = insn_bytes[k]; |
| 801 | } |
| 802 | out_used += j; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 803 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 804 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 805 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 806 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 807 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 808 | vexAllocSanityCheck(); |
| 809 | |
| 810 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 811 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 812 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 813 | res.status = VexTransOK; |
| 814 | return res; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 818 | /* --------- Chain/Unchain XDirects. --------- */ |
| 819 | |
| 820 | VexInvalRange LibVEX_Chain ( VexArch arch_host, |
| 821 | void* place_to_chain, |
| 822 | void* disp_cp_chain_me_EXPECTED, |
| 823 | void* place_to_jump_to ) |
| 824 | { |
| 825 | VexInvalRange (*chainXDirect)(void*, void*, void*) = NULL; |
| 826 | switch (arch_host) { |
| 827 | case VexArchX86: |
| 828 | chainXDirect = chainXDirect_X86; break; |
| 829 | case VexArchAMD64: |
| 830 | chainXDirect = chainXDirect_AMD64; break; |
| 831 | case VexArchARM: |
| 832 | chainXDirect = chainXDirect_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 833 | case VexArchS390X: |
| 834 | chainXDirect = chainXDirect_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 835 | case VexArchPPC32: |
| 836 | return chainXDirect_PPC(place_to_chain, |
| 837 | disp_cp_chain_me_EXPECTED, |
| 838 | place_to_jump_to, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 839 | default: |
| 840 | vassert(0); |
| 841 | } |
| 842 | vassert(chainXDirect); |
| 843 | VexInvalRange vir |
| 844 | = chainXDirect(place_to_chain, disp_cp_chain_me_EXPECTED, |
| 845 | place_to_jump_to); |
| 846 | return vir; |
| 847 | } |
| 848 | |
| 849 | VexInvalRange LibVEX_UnChain ( VexArch arch_host, |
| 850 | void* place_to_unchain, |
| 851 | void* place_to_jump_to_EXPECTED, |
| 852 | void* disp_cp_chain_me ) |
| 853 | { |
| 854 | VexInvalRange (*unchainXDirect)(void*, void*, void*) = NULL; |
| 855 | switch (arch_host) { |
| 856 | case VexArchX86: |
| 857 | unchainXDirect = unchainXDirect_X86; break; |
| 858 | case VexArchAMD64: |
| 859 | unchainXDirect = unchainXDirect_AMD64; break; |
| 860 | case VexArchARM: |
| 861 | unchainXDirect = unchainXDirect_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 862 | case VexArchS390X: |
| 863 | unchainXDirect = unchainXDirect_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 864 | case VexArchPPC32: |
| 865 | return unchainXDirect_PPC(place_to_unchain, |
| 866 | place_to_jump_to_EXPECTED, |
| 867 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 868 | default: |
| 869 | vassert(0); |
| 870 | } |
| 871 | vassert(unchainXDirect); |
| 872 | VexInvalRange vir |
| 873 | = unchainXDirect(place_to_unchain, place_to_jump_to_EXPECTED, |
| 874 | disp_cp_chain_me); |
| 875 | return vir; |
| 876 | } |
| 877 | |
| 878 | Int LibVEX_evCheckSzB ( VexArch arch_host ) |
| 879 | { |
| 880 | static Int cached = 0; /* DO NOT MAKE NON-STATIC */ |
| 881 | if (UNLIKELY(cached == 0)) { |
| 882 | switch (arch_host) { |
| 883 | case VexArchX86: |
| 884 | cached = evCheckSzB_X86(); break; |
| 885 | case VexArchAMD64: |
| 886 | cached = evCheckSzB_AMD64(); break; |
| 887 | case VexArchARM: |
| 888 | cached = evCheckSzB_ARM(); break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 889 | case VexArchS390X: |
| 890 | cached = evCheckSzB_S390(); break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 891 | case VexArchPPC32: |
| 892 | cached = evCheckSzB_PPC(); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 893 | default: |
| 894 | vassert(0); |
| 895 | } |
| 896 | } |
| 897 | return cached; |
| 898 | } |
| 899 | |
| 900 | VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, |
| 901 | void* place_to_patch, |
| 902 | ULong* location_of_counter ) |
| 903 | { |
| 904 | VexInvalRange (*patchProfInc)(void*,ULong*) = NULL; |
| 905 | switch (arch_host) { |
| 906 | case VexArchX86: |
| 907 | patchProfInc = patchProfInc_X86; break; |
| 908 | case VexArchAMD64: |
| 909 | patchProfInc = patchProfInc_AMD64; break; |
| 910 | case VexArchARM: |
| 911 | patchProfInc = patchProfInc_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 912 | case VexArchS390X: |
| 913 | patchProfInc = patchProfInc_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame^] | 914 | case VexArchPPC32: |
| 915 | return patchProfInc_PPC(place_to_patch, |
| 916 | location_of_counter, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 917 | default: |
| 918 | vassert(0); |
| 919 | } |
| 920 | vassert(patchProfInc); |
| 921 | VexInvalRange vir |
| 922 | = patchProfInc(place_to_patch, location_of_counter); |
| 923 | return vir; |
| 924 | } |
| 925 | |
| 926 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 927 | /* --------- Emulation warnings. --------- */ |
| 928 | |
| 929 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 930 | { |
| 931 | switch (ew) { |
| 932 | case EmWarn_NONE: |
| 933 | return "none"; |
| 934 | case EmWarn_X86_x87exns: |
| 935 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 936 | case EmWarn_X86_x87precision: |
| 937 | return "Selection of non-80-bit x87 FP precision"; |
| 938 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 939 | return "Unmasking SSE FP exceptions"; |
| 940 | case EmWarn_X86_fz: |
| 941 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 942 | case EmWarn_X86_daz: |
| 943 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 944 | case EmWarn_X86_acFlag: |
| 945 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 946 | case EmWarn_PPCexns: |
| 947 | return "Unmasking PPC32/64 FP exceptions"; |
| 948 | case EmWarn_PPC64_redir_overflow: |
| 949 | return "PPC64 function redirection stack overflow"; |
| 950 | case EmWarn_PPC64_redir_underflow: |
| 951 | return "PPC64 function redirection stack underflow"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 952 | default: |
| 953 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 954 | } |
| 955 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 956 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 957 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 958 | |
| 959 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 960 | { |
| 961 | switch (arch) { |
| 962 | case VexArch_INVALID: return "INVALID"; |
| 963 | case VexArchX86: return "X86"; |
| 964 | case VexArchAMD64: return "AMD64"; |
| 965 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 966 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 967 | case VexArchPPC64: return "PPC64"; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 968 | case VexArchS390X: return "S390X"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 969 | default: return "VexArch???"; |
| 970 | } |
| 971 | } |
| 972 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 973 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 974 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 975 | HChar* str = show_hwcaps(arch,hwcaps); |
| 976 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 977 | } |
| 978 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 979 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 980 | /* Write default settings info *vai. */ |
| 981 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 982 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 983 | vai->hwcaps = 0; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 984 | vai->ppc_cache_line_szB = 0; |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 985 | vai->ppc_dcbz_szB = 0; |
| 986 | vai->ppc_dcbzl_szB = 0; |
| 987 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 988 | } |
| 989 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 990 | /* Write default settings info *vbi. */ |
| 991 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 992 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 993 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 994 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 995 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 996 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 997 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
| 998 | vbi->guest_ppc_sc_continues_at_LR = False; |
| 999 | vbi->host_ppc_calls_use_fndescrs = False; |
| 1000 | vbi->host_ppc32_regalign_int64_args = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1003 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1004 | /* Return a string showing the hwcaps in a nice way. The string will |
| 1005 | be NULL for invalid combinations of flags, so these functions also |
| 1006 | serve as a way to validate hwcaps values. */ |
| 1007 | |
| 1008 | static HChar* show_hwcaps_x86 ( UInt hwcaps ) |
| 1009 | { |
| 1010 | /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */ |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1011 | switch (hwcaps) { |
| 1012 | case 0: |
| 1013 | return "x86-sse0"; |
| 1014 | case VEX_HWCAPS_X86_SSE1: |
| 1015 | return "x86-sse1"; |
| 1016 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2: |
| 1017 | return "x86-sse1-sse2"; |
| 1018 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1019 | | VEX_HWCAPS_X86_LZCNT: |
| 1020 | return "x86-sse1-sse2-lzcnt"; |
| 1021 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1022 | | VEX_HWCAPS_X86_SSE3: |
| 1023 | return "x86-sse1-sse2-sse3"; |
| 1024 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1025 | | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT: |
| 1026 | return "x86-sse1-sse2-sse3-lzcnt"; |
| 1027 | default: |
| 1028 | return NULL; |
| 1029 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1030 | } |
| 1031 | |
| 1032 | static HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
| 1033 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1034 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 1035 | don't expect to come across anything which can do SSE3 but can't |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1036 | do CX16. Still, we can handle that case. LZCNT is similarly |
| 1037 | orthogonal. */ |
| 1038 | switch (hwcaps) { |
| 1039 | case 0: |
| 1040 | return "amd64-sse2"; |
| 1041 | case VEX_HWCAPS_AMD64_SSE3: |
| 1042 | return "amd64-sse3"; |
| 1043 | case VEX_HWCAPS_AMD64_CX16: |
| 1044 | return "amd64-sse2-cx16"; |
| 1045 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16: |
| 1046 | return "amd64-sse3-cx16"; |
| 1047 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_LZCNT: |
| 1048 | return "amd64-sse3-lzcnt"; |
| 1049 | case VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT: |
| 1050 | return "amd64-sse2-cx16-lzcnt"; |
| 1051 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16 |
| 1052 | | VEX_HWCAPS_AMD64_LZCNT: |
| 1053 | return "amd64-sse3-cx16-lzcnt"; |
| 1054 | |
| 1055 | default: |
| 1056 | return NULL; |
| 1057 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1058 | } |
| 1059 | |
| 1060 | static HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
| 1061 | { |
| 1062 | /* Monotonic with complications. Basically V > F > baseline, |
| 1063 | but once you have F then you can have FX or GX too. */ |
| 1064 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 1065 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 1066 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 1067 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1068 | const UInt VX = VEX_HWCAPS_PPC32_VX; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1069 | UInt c = hwcaps; |
| 1070 | if (c == 0) return "ppc32-int"; |
| 1071 | if (c == F) return "ppc32-int-flt"; |
| 1072 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 1073 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 1074 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 1075 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 1076 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 1077 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 1078 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1079 | if (c == (F|V|FX|GX|VX)) return "ppc32-int-flt-vmx-FX-GX-VX"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1080 | return NULL; |
| 1081 | } |
| 1082 | |
| 1083 | static HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
| 1084 | { |
| 1085 | /* Monotonic with complications. Basically V > baseline(==F), |
| 1086 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1087 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 1088 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 1089 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1090 | const UInt VX = VEX_HWCAPS_PPC64_VX; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1091 | UInt c = hwcaps; |
| 1092 | if (c == 0) return "ppc64-int-flt"; |
| 1093 | if (c == FX) return "ppc64-int-flt-FX"; |
| 1094 | if (c == GX) return "ppc64-int-flt-GX"; |
| 1095 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 1096 | if (c == V) return "ppc64-int-flt-vmx"; |
| 1097 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 1098 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 1099 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1100 | if (c == (V|FX|GX|VX)) return "ppc64-int-flt-vmx-FX-GX-VX"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1101 | return NULL; |
| 1102 | } |
| 1103 | |
| 1104 | static HChar* show_hwcaps_arm ( UInt hwcaps ) |
| 1105 | { |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 1106 | Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); |
| 1107 | Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP | |
| 1108 | VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0); |
| 1109 | switch (VEX_ARM_ARCHLEVEL(hwcaps)) { |
| 1110 | case 5: |
| 1111 | if (N) |
| 1112 | return NULL; |
| 1113 | if (vfp) |
| 1114 | return "ARMv5-vfp"; |
| 1115 | else |
| 1116 | return "ARMv5"; |
| 1117 | return NULL; |
| 1118 | case 6: |
| 1119 | if (N) |
| 1120 | return NULL; |
| 1121 | if (vfp) |
| 1122 | return "ARMv6-vfp"; |
| 1123 | else |
| 1124 | return "ARMv6"; |
| 1125 | return NULL; |
| 1126 | case 7: |
| 1127 | if (vfp) { |
| 1128 | if (N) |
| 1129 | return "ARMv7-vfp-neon"; |
| 1130 | else |
| 1131 | return "ARMv7-vfp"; |
| 1132 | } else { |
| 1133 | if (N) |
| 1134 | return "ARMv7-neon"; |
| 1135 | else |
| 1136 | return "ARMv7"; |
| 1137 | } |
| 1138 | default: |
| 1139 | return NULL; |
| 1140 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1141 | return NULL; |
| 1142 | } |
| 1143 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1144 | static HChar* show_hwcaps_s390x ( UInt hwcaps ) |
| 1145 | { |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1146 | static const HChar prefix[] = "s390x"; |
| 1147 | static const HChar facilities[][6] = { |
| 1148 | { "ldisp" }, |
| 1149 | { "eimm" }, |
| 1150 | { "gie" }, |
| 1151 | { "dfp" }, |
| 1152 | { "fgx" }, |
| 1153 | }; |
| 1154 | static HChar buf[sizeof facilities + sizeof prefix + 1]; |
| 1155 | static HChar *p; |
| 1156 | |
| 1157 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1158 | |
sewardj | 652b56a | 2011-04-13 15:38:17 +0000 | [diff] [blame] | 1159 | hwcaps = VEX_HWCAPS_S390X(hwcaps); |
| 1160 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1161 | p = buf + vex_sprintf(buf, "%s", prefix); |
| 1162 | if (hwcaps & VEX_HWCAPS_S390X_LDISP) |
| 1163 | p = p + vex_sprintf(p, "-%s", facilities[0]); |
| 1164 | if (hwcaps & VEX_HWCAPS_S390X_EIMM) |
| 1165 | p = p + vex_sprintf(p, "-%s", facilities[1]); |
| 1166 | if (hwcaps & VEX_HWCAPS_S390X_GIE) |
| 1167 | p = p + vex_sprintf(p, "-%s", facilities[2]); |
| 1168 | if (hwcaps & VEX_HWCAPS_S390X_DFP) |
| 1169 | p = p + vex_sprintf(p, "-%s", facilities[3]); |
| 1170 | if (hwcaps & VEX_HWCAPS_S390X_FGX) |
| 1171 | p = p + vex_sprintf(p, "-%s", facilities[4]); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1172 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1173 | /* If there are no facilities, add "zarch" */ |
| 1174 | if (hwcaps == 0) |
| 1175 | vex_sprintf(p, "-%s", "zarch"); |
| 1176 | |
| 1177 | return buf; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1178 | } |
| 1179 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1180 | /* ---- */ |
| 1181 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1182 | { |
| 1183 | switch (arch) { |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1184 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1185 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 1186 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 1187 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1188 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1189 | case VexArchS390X: return show_hwcaps_s390x(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1190 | default: return NULL; |
| 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1195 | { |
| 1196 | return show_hwcaps(arch,hwcaps) != NULL; |
| 1197 | } |
| 1198 | |
| 1199 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1200 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1201 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1202 | /*---------------------------------------------------------------*/ |