blob: 47f8629a1e33af6ddebadd9ddebe2dda6201babc [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070035#include "fb.h"
Chia-I Wu09142132014-08-11 15:42:55 +080036
Chia-I Wu3c3edc02014-09-09 10:32:59 +080037/**
38 * Free all resources used by a writer. Note that the initial size is not
39 * reset.
40 */
41static void cmd_writer_reset(struct intel_cmd *cmd,
42 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080043{
Chia-I Wu68f319d2014-09-09 09:43:21 +080044 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080045
Chia-I Wu3c3edc02014-09-09 10:32:59 +080046 if (writer->ptr) {
47 intel_bo_unmap(writer->bo);
48 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080049 }
50
Chia-I Wu3c3edc02014-09-09 10:32:59 +080051 if (writer->bo) {
52 intel_bo_unreference(writer->bo);
53 writer->bo = NULL;
54 }
55
Chia-I Wue24c3292014-08-21 14:05:23 +080056 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080057
58 if (writer->items) {
59 icd_free(writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060060 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080061 writer->item_alloc = 0;
62 writer->item_used = 0;
63 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080064}
65
66/**
67 * Discard everything written so far.
68 */
69static void cmd_writer_discard(struct intel_cmd *cmd,
70 enum intel_cmd_writer_type which)
71{
72 struct intel_cmd_writer *writer = &cmd->writers[which];
73
74 intel_bo_truncate_relocs(writer->bo, 0);
75 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080076 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080077}
78
79static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
80 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060081 size_t size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080082{
83 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
84 [INTEL_CMD_WRITER_BATCH] = "batch",
Chia-I Wu15cccf72015-02-10 04:07:40 +080085 [INTEL_CMD_WRITER_SURFACE] = "surface",
86 [INTEL_CMD_WRITER_STATE] = "state",
Chia-I Wu3c3edc02014-09-09 10:32:59 +080087 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
88 };
89
Chia-I Wu72292b72014-09-09 10:48:33 +080090 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080091}
92
93/**
94 * Allocate and map the buffer for writing.
95 */
96static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
97 enum intel_cmd_writer_type which)
98{
99 struct intel_cmd_writer *writer = &cmd->writers[which];
100 struct intel_bo *bo;
101
102 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
103 if (bo) {
104 if (writer->bo)
105 intel_bo_unreference(writer->bo);
106 writer->bo = bo;
107 } else if (writer->bo) {
108 /* reuse the old bo */
109 cmd_writer_discard(cmd, which);
110 } else {
111 return XGL_ERROR_OUT_OF_GPU_MEMORY;
112 }
113
114 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800115 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800116
117 writer->ptr = intel_bo_map(writer->bo, true);
118 if (!writer->ptr)
119 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800120
121 return XGL_SUCCESS;
122}
123
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800124/**
125 * Unmap the buffer for submission.
126 */
127static void cmd_writer_unmap(struct intel_cmd *cmd,
128 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800129{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800130 struct intel_cmd_writer *writer = &cmd->writers[which];
131
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800132 intel_bo_unmap(writer->bo);
133 writer->ptr = NULL;
134}
135
136/**
137 * Grow a mapped writer to at least \p new_size. Failures are handled
138 * silently.
139 */
140void cmd_writer_grow(struct intel_cmd *cmd,
141 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600142 size_t new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800143{
144 struct intel_cmd_writer *writer = &cmd->writers[which];
145 struct intel_bo *new_bo;
146 void *new_ptr;
147
148 if (new_size < writer->size << 1)
149 new_size = writer->size << 1;
150 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800151 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800152
153 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
154 if (!new_bo) {
155 cmd_writer_discard(cmd, which);
156 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
157 return;
158 }
159
160 /* map and copy the data over */
161 new_ptr = intel_bo_map(new_bo, true);
162 if (!new_ptr) {
163 intel_bo_unreference(new_bo);
164 cmd_writer_discard(cmd, which);
165 cmd->result = XGL_ERROR_UNKNOWN;
166 return;
167 }
168
Chia-I Wu72292b72014-09-09 10:48:33 +0800169 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800170
171 intel_bo_unmap(writer->bo);
172 intel_bo_unreference(writer->bo);
173
174 writer->size = new_size;
175 writer->bo = new_bo;
176 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800177}
178
Chia-I Wu00b51a82014-09-09 12:07:37 +0800179/**
180 * Record an item for later decoding.
181 */
182void cmd_writer_record(struct intel_cmd *cmd,
183 enum intel_cmd_writer_type which,
184 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600185 size_t offset, size_t size)
Chia-I Wu00b51a82014-09-09 12:07:37 +0800186{
187 struct intel_cmd_writer *writer = &cmd->writers[which];
188 struct intel_cmd_item *item;
189
190 if (writer->item_used == writer->item_alloc) {
191 const unsigned new_alloc = (writer->item_alloc) ?
192 writer->item_alloc << 1 : 256;
193 struct intel_cmd_item *items;
194
195 items = icd_alloc(sizeof(writer->items[0]) * new_alloc,
196 0, XGL_SYSTEM_ALLOC_DEBUG);
197 if (!items) {
198 writer->item_used = 0;
199 cmd->result = XGL_ERROR_OUT_OF_MEMORY;
200 return;
201 }
202
203 memcpy(items, writer->items,
204 sizeof(writer->items[0]) * writer->item_alloc);
205
206 icd_free(writer->items);
207
208 writer->items = items;
209 writer->item_alloc = new_alloc;
210 }
211
212 item = &writer->items[writer->item_used++];
213 item->type = type;
214 item->offset = offset;
215 item->size = size;
216}
217
Chia-I Wu5e25c272014-08-21 20:19:12 +0800218static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800219 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600220 size_t offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800221{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800222 struct intel_cmd_writer *writer = &cmd->writers[which];
223
Chia-I Wu72292b72014-09-09 10:48:33 +0800224 assert(offset + sizeof(val) <= writer->used);
225 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800226}
227
Chia-I Wu730e5362014-08-19 12:15:09 +0800228static void cmd_reset(struct intel_cmd *cmd)
229{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600230 uint32_t i;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800231
232 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
233 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800234
Chia-I Wua57761b2014-10-14 14:27:44 +0800235 if (cmd->bind.shader_cache.entries)
236 icd_free(cmd->bind.shader_cache.entries);
237
Chia-I Wuf8385062015-01-04 16:27:24 +0800238 if (cmd->bind.dset.graphics_dynamic_offsets)
239 icd_free(cmd->bind.dset.graphics_dynamic_offsets);
240 if (cmd->bind.dset.compute_dynamic_offsets)
241 icd_free(cmd->bind.dset.compute_dynamic_offsets);
242
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800243 memset(&cmd->bind, 0, sizeof(cmd->bind));
244
Chia-I Wu343b1372014-08-20 16:39:20 +0800245 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800246 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800247}
248
249static void cmd_destroy(struct intel_obj *obj)
250{
251 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
252
253 intel_cmd_destroy(cmd);
254}
255
256XGL_RESULT intel_cmd_create(struct intel_dev *dev,
257 const XGL_CMD_BUFFER_CREATE_INFO *info,
258 struct intel_cmd **cmd_ret)
259{
Chia-I Wu63883292014-08-25 13:50:26 +0800260 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800261 struct intel_cmd *cmd;
262
Chia-I Wu63883292014-08-25 13:50:26 +0800263 switch (info->queueType) {
264 case XGL_QUEUE_TYPE_GRAPHICS:
265 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
266 break;
267 case XGL_QUEUE_TYPE_COMPUTE:
268 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
269 break;
270 case XGL_QUEUE_TYPE_DMA:
271 pipeline_select = -1;
272 break;
273 default:
274 return XGL_ERROR_INVALID_VALUE;
275 break;
276 }
277
Chia-I Wu730e5362014-08-19 12:15:09 +0800278 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
279 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
280 if (!cmd)
281 return XGL_ERROR_OUT_OF_MEMORY;
282
283 cmd->obj.destroy = cmd_destroy;
284
285 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800286 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800287 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800288
Chia-I Wue0cdd832014-08-25 12:38:56 +0800289 /*
290 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
291 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
292 * and end offsets, for each referenced memories.
293 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800294 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
295 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
296 4096, XGL_SYSTEM_ALLOC_INTERNAL);
297 if (!cmd->relocs) {
298 intel_cmd_destroy(cmd);
299 return XGL_ERROR_OUT_OF_MEMORY;
300 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800301
302 *cmd_ret = cmd;
303
304 return XGL_SUCCESS;
305}
306
307void intel_cmd_destroy(struct intel_cmd *cmd)
308{
309 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800310
311 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800312 intel_base_destroy(&cmd->obj.base);
313}
314
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700315XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, const XGL_CMD_BUFFER_BEGIN_INFO* info)
Chia-I Wu730e5362014-08-19 12:15:09 +0800316{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800317 XGL_RESULT ret;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600318 uint32_t i;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700319 XGL_FLAGS flags = 0;
320 XGL_CMD_BUFFER_BEGIN_INFO* next= (XGL_CMD_BUFFER_BEGIN_INFO*) info;
321 XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *ginfo;
Chia-I Wu730e5362014-08-19 12:15:09 +0800322
323 cmd_reset(cmd);
324
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700325 while (next != NULL) {
326 switch (next->sType) {
327 case XGL_STRUCTURE_TYPE_CMD_BUFFER_BEGIN_INFO:
328 flags = next->flags;
329 break;
330 case XGL_STRUCTURE_TYPE_CMD_BUFFER_GRAPHICS_BEGIN_INFO:
331 ginfo = (XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *) next;
Jon Ashburnb1dbb372015-02-02 09:58:11 -0700332 intel_cmd_begin_render_pass(cmd, (struct intel_render_pass *)
333 ginfo->renderPass);
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700334 break;
335 default:
336 return XGL_ERROR_INVALID_VALUE;
337 break;
338 }
339 next = (XGL_CMD_BUFFER_BEGIN_INFO*) next->pNext;
340 }
341
Chia-I Wu24565ee2014-08-21 20:24:31 +0800342 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800343 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800344 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800345 }
346
Chia-I Wu68f319d2014-09-09 09:43:21 +0800347 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600348 const uint32_t size = cmd->dev->gpu->max_batch_buffer_size / 2;
349 uint32_t divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800350
351 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
352 divider *= 4;
353
Chia-I Wu68f319d2014-09-09 09:43:21 +0800354 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800355 cmd->writers[INTEL_CMD_WRITER_SURFACE].size = size / divider / 2;
356 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider / 2;
Chia-I Wu72292b72014-09-09 10:48:33 +0800357 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800358 }
359
Chia-I Wu68f319d2014-09-09 09:43:21 +0800360 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800361 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800362 if (ret != XGL_SUCCESS) {
363 cmd_reset(cmd);
364 return ret;
365 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800366 }
367
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800368 cmd_batch_begin(cmd);
369
Chia-I Wu24565ee2014-08-21 20:24:31 +0800370 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800371}
372
373XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
374{
375 struct intel_winsys *winsys = cmd->dev->winsys;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600376 uint32_t i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800377
Chia-I Wub8762122014-12-01 22:51:03 +0800378 /* no matching intel_cmd_begin() */
379 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].ptr)
380 return XGL_ERROR_INCOMPLETE_COMMAND_BUFFER;
381
Chia-I Wue24c3292014-08-21 14:05:23 +0800382 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800383
Chia-I Wu343b1372014-08-20 16:39:20 +0800384 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800385 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800386 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800387 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800388 uint64_t presumed_offset;
389 int err;
390
Chia-I Wud7d1e482014-10-18 13:25:10 +0800391 /*
392 * Once a bo is used as a reloc target, libdrm_intel disallows more
393 * relocs to be added to it. That may happen when
394 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
395 * in another pass.
396 */
397 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
398 continue;
399
Chia-I Wu72292b72014-09-09 10:48:33 +0800400 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800401 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800402 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800403 if (err) {
404 cmd->result = XGL_ERROR_UNKNOWN;
405 break;
406 }
407
408 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800409 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800410 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800411 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800412 for (i = 0; i < cmd->reloc_used; i++) {
413 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
414 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
415 uint64_t presumed_offset;
416 int err;
417
418 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
419 continue;
420
421 err = intel_bo_add_reloc(writer->bo, reloc->offset,
422 cmd->writers[reloc->target].bo, reloc->target_offset,
423 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
424 &presumed_offset);
425 if (err) {
426 cmd->result = XGL_ERROR_UNKNOWN;
427 break;
428 }
429
430 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
431 cmd_writer_patch(cmd, reloc->which, reloc->offset,
432 (uint32_t) presumed_offset);
433 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800434
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800435 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
436 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800437
Chia-I Wu04966702014-08-20 15:05:03 +0800438 if (cmd->result != XGL_SUCCESS)
439 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800440
Chia-I Wu68f319d2014-09-09 09:43:21 +0800441 if (intel_winsys_can_submit_bo(winsys,
442 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800443 return XGL_SUCCESS;
444 else
445 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
446}
447
Chia-I Wu96177272015-01-03 15:27:41 +0800448ICD_EXPORT XGL_RESULT XGLAPI xglCreateCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800449 XGL_DEVICE device,
450 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
451 XGL_CMD_BUFFER* pCmdBuffer)
452{
Chia-I Wu730e5362014-08-19 12:15:09 +0800453 struct intel_dev *dev = intel_dev(device);
454
455 return intel_cmd_create(dev, pCreateInfo,
456 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800457}
458
Chia-I Wu96177272015-01-03 15:27:41 +0800459ICD_EXPORT XGL_RESULT XGLAPI xglBeginCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800460 XGL_CMD_BUFFER cmdBuffer,
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700461 const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu09142132014-08-11 15:42:55 +0800462{
Chia-I Wu730e5362014-08-19 12:15:09 +0800463 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
464
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700465 return intel_cmd_begin(cmd, info);
Chia-I Wu09142132014-08-11 15:42:55 +0800466}
467
Chia-I Wu96177272015-01-03 15:27:41 +0800468ICD_EXPORT XGL_RESULT XGLAPI xglEndCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800469 XGL_CMD_BUFFER cmdBuffer)
470{
Chia-I Wu730e5362014-08-19 12:15:09 +0800471 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
472
473 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800474}
475
Chia-I Wu96177272015-01-03 15:27:41 +0800476ICD_EXPORT XGL_RESULT XGLAPI xglResetCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800477 XGL_CMD_BUFFER cmdBuffer)
478{
Chia-I Wu730e5362014-08-19 12:15:09 +0800479 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
480
481 cmd_reset(cmd);
482
483 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800484}
485
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600486ICD_EXPORT void XGLAPI xglCmdInitAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800487 XGL_CMD_BUFFER cmdBuffer,
488 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600489 uint32_t startCounter,
490 uint32_t counterCount,
491 const uint32_t* pData)
Chia-I Wu09142132014-08-11 15:42:55 +0800492{
493}
494
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600495ICD_EXPORT void XGLAPI xglCmdLoadAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800496 XGL_CMD_BUFFER cmdBuffer,
497 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600498 uint32_t startCounter,
499 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800500 XGL_BUFFER srcBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800501 XGL_GPU_SIZE srcOffset)
502{
503}
504
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600505ICD_EXPORT void XGLAPI xglCmdSaveAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800506 XGL_CMD_BUFFER cmdBuffer,
507 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600508 uint32_t startCounter,
509 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800510 XGL_BUFFER destBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800511 XGL_GPU_SIZE destOffset)
512{
513}
514
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600515ICD_EXPORT void XGLAPI xglCmdDbgMarkerBegin(
Chia-I Wu09142132014-08-11 15:42:55 +0800516 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600517 const char* pMarker)
Chia-I Wu09142132014-08-11 15:42:55 +0800518{
519}
520
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600521ICD_EXPORT void XGLAPI xglCmdDbgMarkerEnd(
Chia-I Wu09142132014-08-11 15:42:55 +0800522 XGL_CMD_BUFFER cmdBuffer)
523{
524}