Eugene Zelenko | 076468c | 2017-09-20 21:35:51 +0000 | [diff] [blame] | 1 | //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 9 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 10 | #include "MCTargetDesc/ARMAddressingModes.h" |
| 11 | #include "MCTargetDesc/ARMBaseInfo.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 12 | #include "MCTargetDesc/ARMMCTargetDesc.h" |
Eugene Zelenko | 076468c | 2017-09-20 21:35:51 +0000 | [diff] [blame] | 13 | #include "Utils/ARMBaseInfo.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 14 | #include "llvm/MC/MCContext.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 15 | #include "llvm/MC/MCDisassembler/MCDisassembler.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 16 | #include "llvm/MC/MCFixedLenDisassembler.h" |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 17 | #include "llvm/MC/MCInst.h" |
Benjamin Kramer | 48b5bbf | 2011-11-11 12:39:41 +0000 | [diff] [blame] | 18 | #include "llvm/MC/MCInstrDesc.h" |
Dylan Noblesmith | 7a3973d | 2012-04-03 15:48:14 +0000 | [diff] [blame] | 19 | #include "llvm/MC/MCSubtargetInfo.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 20 | #include "llvm/MC/SubtargetFeature.h" |
| 21 | #include "llvm/Support/Compiler.h" |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 22 | #include "llvm/Support/ErrorHandling.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 23 | #include "llvm/Support/MathExtras.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 24 | #include "llvm/Support/TargetRegistry.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 25 | #include "llvm/Support/raw_ostream.h" |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 26 | #include <algorithm> |
| 27 | #include <cassert> |
| 28 | #include <cstdint> |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 29 | #include <vector> |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 30 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 31 | using namespace llvm; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 32 | |
Chandler Carruth | 84e68b2 | 2014-04-22 02:41:26 +0000 | [diff] [blame] | 33 | #define DEBUG_TYPE "arm-disassembler" |
| 34 | |
Eugene Zelenko | 076468c | 2017-09-20 21:35:51 +0000 | [diff] [blame] | 35 | using DecodeStatus = MCDisassembler::DecodeStatus; |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 36 | |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 37 | namespace { |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 38 | |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 39 | // Handles the condition code status of instructions in IT blocks |
| 40 | class ITStatus |
| 41 | { |
| 42 | public: |
| 43 | // Returns the condition code for instruction in IT block |
| 44 | unsigned getITCC() { |
| 45 | unsigned CC = ARMCC::AL; |
| 46 | if (instrInITBlock()) |
| 47 | CC = ITStates.back(); |
| 48 | return CC; |
| 49 | } |
| 50 | |
| 51 | // Advances the IT block state to the next T or E |
| 52 | void advanceITState() { |
| 53 | ITStates.pop_back(); |
| 54 | } |
| 55 | |
| 56 | // Returns true if the current instruction is in an IT block |
| 57 | bool instrInITBlock() { |
| 58 | return !ITStates.empty(); |
| 59 | } |
| 60 | |
| 61 | // Returns true if current instruction is the last instruction in an IT block |
| 62 | bool instrLastInITBlock() { |
| 63 | return ITStates.size() == 1; |
| 64 | } |
| 65 | |
| 66 | // Called when decoding an IT instruction. Sets the IT state for the following |
Vinicius Tinti | 67cf33d | 2015-11-20 23:20:12 +0000 | [diff] [blame] | 67 | // instructions that for the IT block. Firstcond and Mask correspond to the |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 68 | // fields in the IT instruction encoding. |
| 69 | void setITState(char Firstcond, char Mask) { |
| 70 | // (3 - the number of trailing zeros) is the number of then / else. |
Richard Barton | f435b09 | 2012-04-27 08:42:59 +0000 | [diff] [blame] | 71 | unsigned CondBit0 = Firstcond & 1; |
Michael J. Spencer | df1ecbd7 | 2013-05-24 22:23:49 +0000 | [diff] [blame] | 72 | unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 73 | unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); |
| 74 | assert(NumTZ <= 3 && "Invalid IT mask!"); |
| 75 | // push condition codes onto the stack the correct order for the pops |
| 76 | for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { |
| 77 | bool T = ((Mask >> Pos) & 1) == CondBit0; |
| 78 | if (T) |
| 79 | ITStates.push_back(CCBits); |
| 80 | else |
| 81 | ITStates.push_back(CCBits ^ 1); |
| 82 | } |
| 83 | ITStates.push_back(CCBits); |
| 84 | } |
| 85 | |
| 86 | private: |
| 87 | std::vector<unsigned char> ITStates; |
| 88 | }; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 89 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 90 | /// ARM disassembler for all ARM platforms. |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 91 | class ARMDisassembler : public MCDisassembler { |
| 92 | public: |
Lang Hames | a1bc0f5 | 2014-04-15 04:40:56 +0000 | [diff] [blame] | 93 | ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : |
| 94 | MCDisassembler(STI, Ctx) { |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 97 | ~ARMDisassembler() override = default; |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 98 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 99 | DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 100 | ArrayRef<uint8_t> Bytes, uint64_t Address, |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 101 | raw_ostream &VStream, |
| 102 | raw_ostream &CStream) const override; |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 103 | }; |
| 104 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 105 | /// Thumb disassembler for all Thumb platforms. |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 106 | class ThumbDisassembler : public MCDisassembler { |
| 107 | public: |
Lang Hames | a1bc0f5 | 2014-04-15 04:40:56 +0000 | [diff] [blame] | 108 | ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : |
| 109 | MCDisassembler(STI, Ctx) { |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 112 | ~ThumbDisassembler() override = default; |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 113 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 114 | DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 115 | ArrayRef<uint8_t> Bytes, uint64_t Address, |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 116 | raw_ostream &VStream, |
| 117 | raw_ostream &CStream) const override; |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 118 | |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 119 | private: |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 120 | mutable ITStatus ITBlock; |
Eugene Zelenko | 076468c | 2017-09-20 21:35:51 +0000 | [diff] [blame] | 121 | |
Owen Anderson | 2fefa42 | 2011-09-08 22:42:49 +0000 | [diff] [blame] | 122 | DecodeStatus AddThumbPredicate(MCInst&) const; |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 123 | void UpdateThumbVFPPredicate(MCInst&) const; |
| 124 | }; |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 125 | |
| 126 | } // end anonymous namespace |
Owen Anderson | ed96b58 | 2011-09-01 23:35:51 +0000 | [diff] [blame] | 127 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 128 | static bool Check(DecodeStatus &Out, DecodeStatus In) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 129 | switch (In) { |
| 130 | case MCDisassembler::Success: |
| 131 | // Out stays the same. |
| 132 | return true; |
| 133 | case MCDisassembler::SoftFail: |
| 134 | Out = In; |
| 135 | return true; |
| 136 | case MCDisassembler::Fail: |
| 137 | Out = In; |
| 138 | return false; |
| 139 | } |
David Blaikie | 46a9f01 | 2012-01-20 21:51:11 +0000 | [diff] [blame] | 140 | llvm_unreachable("Invalid DecodeStatus!"); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 141 | } |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 142 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 143 | // Forward declare these because the autogenerated code will reference them. |
| 144 | // Definitions are further down. |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 145 | static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 146 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 147 | static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 148 | unsigned RegNo, uint64_t Address, |
| 149 | const void *Decoder); |
Mihai Popa | dc1764c5 | 2013-05-13 14:10:04 +0000 | [diff] [blame] | 150 | static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, |
| 151 | unsigned RegNo, uint64_t Address, |
| 152 | const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 153 | static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 154 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 155 | static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 156 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 157 | static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 158 | uint64_t Address, const void *Decoder); |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 159 | static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, |
| 160 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 161 | static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 162 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 163 | static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 164 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 165 | static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 166 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 167 | static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 168 | unsigned RegNo, |
| 169 | uint64_t Address, |
| 170 | const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 171 | static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 172 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 173 | static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 174 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 175 | static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 176 | unsigned RegNo, uint64_t Address, |
| 177 | const void *Decoder); |
Johnny Chen | 74491bb | 2010-08-12 01:40:54 +0000 | [diff] [blame] | 178 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 179 | static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 180 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 181 | static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 182 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 183 | static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 184 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 185 | static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 186 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 187 | static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 188 | uint64_t Address, const void *Decoder); |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 189 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 190 | static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 191 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 192 | static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 193 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 194 | static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 195 | unsigned Insn, |
| 196 | uint64_t Address, |
| 197 | const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 198 | static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 199 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 200 | static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 201 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 202 | static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 203 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 204 | static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 205 | uint64_t Address, const void *Decoder); |
| 206 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 207 | static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 208 | unsigned Insn, |
| 209 | uint64_t Adddress, |
| 210 | const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 211 | static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 212 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 213 | static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 214 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 215 | static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 216 | uint64_t Address, const void *Decoder); |
Sjoerd Meijer | d906bf1 | 2016-06-03 14:03:27 +0000 | [diff] [blame] | 217 | static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, |
| 218 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 219 | static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | 3d2e0e9d | 2011-08-09 23:05:39 +0000 | [diff] [blame] | 220 | uint64_t Address, const void *Decoder); |
Vladimir Sukharev | 0e0f8d2 | 2015-04-16 11:34:25 +0000 | [diff] [blame] | 221 | static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, |
| 222 | uint64_t Address, const void *Decoder); |
| 223 | static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, |
| 224 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 225 | static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 226 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 227 | static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 228 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 229 | static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 230 | uint64_t Address, const void *Decoder); |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 231 | static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, |
| 232 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 233 | static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 234 | uint64_t Address, const void *Decoder); |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 235 | static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, |
| 236 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 237 | static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 238 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 239 | static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 240 | uint64_t Address, const void *Decoder); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 241 | static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, |
| 242 | uint64_t Address, const void *Decoder); |
| 243 | static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, |
| 244 | uint64_t Address, const void *Decoder); |
| 245 | static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, |
| 246 | uint64_t Address, const void *Decoder); |
| 247 | static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, |
| 248 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 249 | static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 250 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 251 | static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 252 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 253 | static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 254 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 255 | static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 256 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 257 | static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 258 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 259 | static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 260 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 261 | static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 262 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 263 | static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 264 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 265 | static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 266 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 267 | static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 268 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 269 | static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 270 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 271 | static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 272 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 273 | static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 274 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 275 | static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 276 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 277 | static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 278 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 279 | static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, |
Owen Anderson | e008931 | 2011-08-09 23:25:42 +0000 | [diff] [blame] | 280 | uint64_t Address, const void *Decoder); |
Amaury de la Vieuville | 43cb13a | 2013-06-10 14:17:08 +0000 | [diff] [blame] | 281 | static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, |
| 282 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 283 | static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, |
Owen Anderson | 6066340 | 2011-08-11 20:21:46 +0000 | [diff] [blame] | 284 | uint64_t Address, const void *Decoder); |
Tim Northover | ee843ef | 2014-08-15 10:47:12 +0000 | [diff] [blame] | 285 | static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, |
| 286 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 287 | static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 288 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 289 | static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, |
Owen Anderson | c5798a3a5 | 2011-08-12 17:58:32 +0000 | [diff] [blame] | 290 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 291 | static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 292 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 293 | static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 294 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 295 | static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 296 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 297 | static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 298 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 299 | static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 300 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 301 | static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 302 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 303 | static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 304 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 305 | static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 306 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 307 | static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 308 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 309 | static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 310 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 311 | static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 312 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 313 | static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 314 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 315 | static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 316 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 317 | static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 318 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 319 | static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 320 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 321 | static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 322 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 323 | static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 324 | uint64_t Address, const void *Decoder); |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 325 | static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, |
| 326 | unsigned Val, |
| 327 | uint64_t Address, |
| 328 | const void *Decoder); |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 329 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 330 | static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 331 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 332 | static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 333 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 334 | static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 335 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 336 | static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 337 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 338 | static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 339 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 340 | static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 341 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 342 | static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 343 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 344 | static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 345 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 346 | static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 347 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 348 | static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 349 | uint64_t Address, const void *Decoder); |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 350 | static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, |
| 351 | uint64_t Address, const void* Decoder); |
| 352 | static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, |
| 353 | uint64_t Address, const void* Decoder); |
| 354 | static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, |
| 355 | uint64_t Address, const void* Decoder); |
| 356 | static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, |
| 357 | uint64_t Address, const void* Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 358 | static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 359 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 360 | static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 361 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 362 | static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, |
Jim Grosbach | a05627e | 2011-09-09 18:37:27 +0000 | [diff] [blame] | 363 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 364 | static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 365 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 366 | static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 367 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 368 | static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 369 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 370 | static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 371 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 372 | static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 373 | uint64_t Address, const void *Decoder); |
Amaury de la Vieuville | 631df63 | 2013-06-08 13:38:52 +0000 | [diff] [blame] | 374 | static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, |
| 375 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 376 | static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 377 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 378 | static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 379 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 380 | static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, |
Jim Grosbach | 05541f4 | 2011-09-19 22:21:13 +0000 | [diff] [blame] | 381 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 382 | static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 383 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 384 | static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 385 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 386 | static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 387 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 388 | static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 389 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 390 | static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, |
Owen Anderson | 37612a3 | 2011-08-24 22:40:22 +0000 | [diff] [blame] | 391 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 392 | static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 393 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 394 | static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 395 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 396 | static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 397 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 398 | static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 399 | uint64_t Address, const void *Decoder); |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 400 | static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | f01e2de | 2011-09-26 21:06:22 +0000 | [diff] [blame] | 401 | uint64_t Address, const void *Decoder); |
| 402 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 403 | static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, |
Silviu Baranga | d213f21 | 2012-03-22 13:24:43 +0000 | [diff] [blame] | 404 | uint64_t Address, const void *Decoder); |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 405 | static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, |
Ranjeet Singh | 39d2d09 | 2016-06-17 00:52:41 +0000 | [diff] [blame] | 406 | uint64_t Address, const void *Decoder); |
Andre Vieira | 640527f | 2017-09-22 12:17:42 +0000 | [diff] [blame] | 407 | static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, |
| 408 | uint64_t Address, const void *Decoder); |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 409 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 410 | #include "ARMGenDisassemblerTables.inc" |
Sean Callanan | 814e69b | 2010-04-13 21:21:57 +0000 | [diff] [blame] | 411 | |
Lang Hames | a1bc0f5 | 2014-04-15 04:40:56 +0000 | [diff] [blame] | 412 | static MCDisassembler *createARMDisassembler(const Target &T, |
| 413 | const MCSubtargetInfo &STI, |
| 414 | MCContext &Ctx) { |
| 415 | return new ARMDisassembler(STI, Ctx); |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 416 | } |
| 417 | |
Lang Hames | a1bc0f5 | 2014-04-15 04:40:56 +0000 | [diff] [blame] | 418 | static MCDisassembler *createThumbDisassembler(const Target &T, |
| 419 | const MCSubtargetInfo &STI, |
| 420 | MCContext &Ctx) { |
| 421 | return new ThumbDisassembler(STI, Ctx); |
Johnny Chen | 7b999ea | 2010-04-02 22:27:38 +0000 | [diff] [blame] | 422 | } |
| 423 | |
Charlie Turner | 30895f9 | 2014-12-01 08:50:27 +0000 | [diff] [blame] | 424 | // Post-decoding checks |
| 425 | static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, |
| 426 | uint64_t Address, raw_ostream &OS, |
| 427 | raw_ostream &CS, |
| 428 | uint32_t Insn, |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 429 | DecodeStatus Result) { |
Charlie Turner | 30895f9 | 2014-12-01 08:50:27 +0000 | [diff] [blame] | 430 | switch (MI.getOpcode()) { |
| 431 | case ARM::HVC: { |
| 432 | // HVC is undefined if condition = 0xf otherwise upredictable |
| 433 | // if condition != 0xe |
| 434 | uint32_t Cond = (Insn >> 28) & 0xF; |
| 435 | if (Cond == 0xF) |
| 436 | return MCDisassembler::Fail; |
| 437 | if (Cond != 0xE) |
| 438 | return MCDisassembler::SoftFail; |
| 439 | return Result; |
| 440 | } |
| 441 | default: return Result; |
| 442 | } |
| 443 | } |
| 444 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 445 | DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 446 | ArrayRef<uint8_t> Bytes, |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 447 | uint64_t Address, raw_ostream &OS, |
| 448 | raw_ostream &CS) const { |
| 449 | CommentStream = &CS; |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 450 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 451 | assert(!STI.getFeatureBits()[ARM::ModeThumb] && |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 452 | "Asked to disassemble an ARM instruction but Subtarget is in Thumb " |
| 453 | "mode!"); |
James Molloy | 8067df9 | 2011-09-07 19:42:28 +0000 | [diff] [blame] | 454 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 455 | // We want to read exactly 4 bytes of data. |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 456 | if (Bytes.size() < 4) { |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 457 | Size = 0; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 458 | return MCDisassembler::Fail; |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 459 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 460 | |
| 461 | // Encoded as a small-endian 32-bit word in the stream. |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 462 | uint32_t Insn = |
| 463 | (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 464 | |
| 465 | // Calling the auto-generated decoder function. |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 466 | DecodeStatus Result = |
| 467 | decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); |
| 468 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 469 | Size = 4; |
Charlie Turner | 30895f9 | 2014-12-01 08:50:27 +0000 | [diff] [blame] | 470 | return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 471 | } |
| 472 | |
Sjoerd Meijer | aea3a99 | 2017-03-13 09:41:10 +0000 | [diff] [blame] | 473 | struct DecodeTable { |
| 474 | const uint8_t *P; |
| 475 | bool DecodePred; |
| 476 | }; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 477 | |
Sjoerd Meijer | aea3a99 | 2017-03-13 09:41:10 +0000 | [diff] [blame] | 478 | const DecodeTable Tables[] = { |
| 479 | {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, |
| 480 | {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, |
| 481 | {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, |
| 482 | {DecoderTablev8Crypto32, false}, |
| 483 | }; |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 484 | |
Sjoerd Meijer | aea3a99 | 2017-03-13 09:41:10 +0000 | [diff] [blame] | 485 | for (auto Table : Tables) { |
| 486 | Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); |
| 487 | if (Result != MCDisassembler::Fail) { |
| 488 | Size = 4; |
| 489 | // Add a fake predicate operand, because we share these instruction |
| 490 | // definitions with Thumb2 where these instructions are predicable. |
| 491 | if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) |
| 492 | return MCDisassembler::Fail; |
| 493 | return Result; |
| 494 | } |
Amara Emerson | 3308909 | 2013-09-19 11:59:01 +0000 | [diff] [blame] | 495 | } |
| 496 | |
Sjoerd Meijer | 7426c97 | 2017-08-11 09:52:30 +0000 | [diff] [blame] | 497 | Result = |
| 498 | decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); |
| 499 | if (Result != MCDisassembler::Fail) { |
| 500 | Size = 4; |
| 501 | return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); |
| 502 | } |
| 503 | |
Eugene Leviant | 6269d39 | 2017-06-29 15:38:47 +0000 | [diff] [blame] | 504 | Size = 4; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 505 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | namespace llvm { |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 509 | |
Benjamin Kramer | 0d6d098 | 2011-10-22 16:50:00 +0000 | [diff] [blame] | 510 | extern const MCInstrDesc ARMInsts[]; |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 511 | |
| 512 | } // end namespace llvm |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 513 | |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 514 | /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the |
| 515 | /// immediate Value in the MCInst. The immediate Value has had any PC |
| 516 | /// adjustment made by the caller. If the instruction is a branch instruction |
| 517 | /// then isBranch is true, else false. If the getOpInfo() function was set as |
| 518 | /// part of the setupForSymbolicDisassembly() call then that function is called |
| 519 | /// to get any symbolic information at the Address for this instruction. If |
| 520 | /// that returns non-zero then the symbolic information it returns is used to |
| 521 | /// create an MCExpr and that is added as an operand to the MCInst. If |
| 522 | /// getOpInfo() returns zero and isBranch is true then a symbol look up for |
| 523 | /// Value is done and if a symbol is found an MCExpr is created with that, else |
| 524 | /// an MCExpr with Value is created. This function returns true if it adds an |
| 525 | /// operand to the MCInst and false otherwise. |
| 526 | static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, |
| 527 | bool isBranch, uint64_t InstSize, |
| 528 | MCInst &MI, const void *Decoder) { |
| 529 | const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); |
Ahmed Bougacha | ad1084d | 2013-05-24 00:39:57 +0000 | [diff] [blame] | 530 | // FIXME: Does it make sense for value to be negative? |
| 531 | return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, |
| 532 | /* Offset */ 0, InstSize); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being |
| 536 | /// referenced by a load instruction with the base register that is the Pc. |
| 537 | /// These can often be values in a literal pool near the Address of the |
| 538 | /// instruction. The Address of the instruction and its immediate Value are |
| 539 | /// used as a possible literal pool entry. The SymbolLookUp call back will |
Sylvestre Ledru | 35521e2 | 2012-07-23 08:51:15 +0000 | [diff] [blame] | 540 | /// return the name of a symbol referenced by the literal pool's entry if |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 541 | /// the referenced address is that of a symbol. Or it will return a pointer to |
| 542 | /// a literal 'C' string if the referenced address of the literal pool's entry |
| 543 | /// is an address into a section with 'C' string literals. |
| 544 | static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, |
Kevin Enderby | 6fbcd8d | 2012-02-23 18:18:17 +0000 | [diff] [blame] | 545 | const void *Decoder) { |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 546 | const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); |
Ahmed Bougacha | ad1084d | 2013-05-24 00:39:57 +0000 | [diff] [blame] | 547 | Dis->tryAddingPcLoadReferenceComment(Value, Address); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 548 | } |
| 549 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 550 | // Thumb1 instructions don't have explicit S bits. Rather, they |
| 551 | // implicitly set CPSR. Since it's not represented in the encoding, the |
| 552 | // auto-generated decoder won't inject the CPSR operand. We need to fix |
| 553 | // that as a post-pass. |
| 554 | static void AddThumb1SBit(MCInst &MI, bool InITBlock) { |
| 555 | const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 556 | unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 557 | MCInst::iterator I = MI.begin(); |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 558 | for (unsigned i = 0; i < NumOps; ++i, ++I) { |
| 559 | if (I == MI.end()) break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 560 | if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 561 | if (i > 0 && OpInfo[i-1].isPredicate()) continue; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 562 | MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 563 | return; |
| 564 | } |
| 565 | } |
| 566 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 567 | MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | // Most Thumb instructions don't have explicit predicates in the |
| 571 | // encoding, but rather get their predicates from IT context. We need |
| 572 | // to fix up the predicate operands using this context information as a |
| 573 | // post-pass. |
Owen Anderson | 2fefa42 | 2011-09-08 22:42:49 +0000 | [diff] [blame] | 574 | MCDisassembler::DecodeStatus |
| 575 | ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 576 | MCDisassembler::DecodeStatus S = Success; |
| 577 | |
Sjoerd Meijer | d906bf1 | 2016-06-03 14:03:27 +0000 | [diff] [blame] | 578 | const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); |
| 579 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 580 | // A few instructions actually have predicates encoded in them. Don't |
| 581 | // try to overwrite it if we're seeing one of those. |
| 582 | switch (MI.getOpcode()) { |
| 583 | case ARM::tBcc: |
| 584 | case ARM::t2Bcc: |
Owen Anderson | 2fefa42 | 2011-09-08 22:42:49 +0000 | [diff] [blame] | 585 | case ARM::tCBZ: |
| 586 | case ARM::tCBNZ: |
Owen Anderson | 61e4604 | 2011-09-19 23:47:10 +0000 | [diff] [blame] | 587 | case ARM::tCPS: |
| 588 | case ARM::t2CPS3p: |
| 589 | case ARM::t2CPS2p: |
| 590 | case ARM::t2CPS1p: |
Owen Anderson | 163be01 | 2011-09-19 23:57:20 +0000 | [diff] [blame] | 591 | case ARM::tMOVSr: |
Owen Anderson | 44f76ea | 2011-10-13 17:58:39 +0000 | [diff] [blame] | 592 | case ARM::tSETEND: |
Owen Anderson | 33d3953 | 2011-09-08 22:48:37 +0000 | [diff] [blame] | 593 | // Some instructions (mostly conditional branches) are not |
| 594 | // allowed in IT blocks. |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 595 | if (ITBlock.instrInITBlock()) |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 596 | S = SoftFail; |
| 597 | else |
| 598 | return Success; |
| 599 | break; |
Sjoerd Meijer | d906bf1 | 2016-06-03 14:03:27 +0000 | [diff] [blame] | 600 | case ARM::t2HINT: |
| 601 | if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) |
| 602 | S = SoftFail; |
| 603 | break; |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 604 | case ARM::tB: |
| 605 | case ARM::t2B: |
Owen Anderson | f902d92 | 2011-09-19 22:34:23 +0000 | [diff] [blame] | 606 | case ARM::t2TBB: |
| 607 | case ARM::t2TBH: |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 608 | // Some instructions (mostly unconditional branches) can |
| 609 | // only appears at the end of, or outside of, an IT. |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 610 | if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 611 | S = SoftFail; |
Owen Anderson | 2fefa42 | 2011-09-08 22:42:49 +0000 | [diff] [blame] | 612 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 613 | default: |
| 614 | break; |
| 615 | } |
| 616 | |
| 617 | // If we're in an IT block, base the predicate on that. Otherwise, |
| 618 | // assume a predicate of AL. |
| 619 | unsigned CC; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 620 | CC = ITBlock.getITCC(); |
| 621 | if (CC == 0xF) |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 622 | CC = ARMCC::AL; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 623 | if (ITBlock.instrInITBlock()) |
| 624 | ITBlock.advanceITState(); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 625 | |
| 626 | const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 627 | unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 628 | MCInst::iterator I = MI.begin(); |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 629 | for (unsigned i = 0; i < NumOps; ++i, ++I) { |
| 630 | if (I == MI.end()) break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 631 | if (OpInfo[i].isPredicate()) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 632 | I = MI.insert(I, MCOperand::createImm(CC)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 633 | ++I; |
| 634 | if (CC == ARMCC::AL) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 635 | MI.insert(I, MCOperand::createReg(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 636 | else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 637 | MI.insert(I, MCOperand::createReg(ARM::CPSR)); |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 638 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 639 | } |
| 640 | } |
| 641 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 642 | I = MI.insert(I, MCOperand::createImm(CC)); |
Owen Anderson | 187e1e4 | 2011-08-17 18:14:48 +0000 | [diff] [blame] | 643 | ++I; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 644 | if (CC == ARMCC::AL) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 645 | MI.insert(I, MCOperand::createReg(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 646 | else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 647 | MI.insert(I, MCOperand::createReg(ARM::CPSR)); |
Owen Anderson | 2fefa42 | 2011-09-08 22:42:49 +0000 | [diff] [blame] | 648 | |
Owen Anderson | 29cfe6c | 2011-09-09 21:48:23 +0000 | [diff] [blame] | 649 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 650 | } |
| 651 | |
| 652 | // Thumb VFP instructions are a special case. Because we share their |
| 653 | // encodings between ARM and Thumb modes, and they are predicable in ARM |
| 654 | // mode, the auto-generated decoder will give them an (incorrect) |
| 655 | // predicate operand. We need to rewrite these operands based on the IT |
| 656 | // context as a post-pass. |
| 657 | void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { |
| 658 | unsigned CC; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 659 | CC = ITBlock.getITCC(); |
| 660 | if (ITBlock.instrInITBlock()) |
| 661 | ITBlock.advanceITState(); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 662 | |
| 663 | const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; |
| 664 | MCInst::iterator I = MI.begin(); |
Owen Anderson | 216cfaa | 2011-08-24 21:35:46 +0000 | [diff] [blame] | 665 | unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; |
| 666 | for (unsigned i = 0; i < NumOps; ++i, ++I) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 667 | if (OpInfo[i].isPredicate() ) { |
| 668 | I->setImm(CC); |
| 669 | ++I; |
| 670 | if (CC == ARMCC::AL) |
| 671 | I->setReg(0); |
| 672 | else |
| 673 | I->setReg(ARM::CPSR); |
| 674 | return; |
| 675 | } |
| 676 | } |
| 677 | } |
| 678 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 679 | DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 680 | ArrayRef<uint8_t> Bytes, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 681 | uint64_t Address, |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 682 | raw_ostream &OS, |
| 683 | raw_ostream &CS) const { |
| 684 | CommentStream = &CS; |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 685 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 686 | assert(STI.getFeatureBits()[ARM::ModeThumb] && |
James Molloy | 8067df9 | 2011-09-07 19:42:28 +0000 | [diff] [blame] | 687 | "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); |
| 688 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 689 | // We want to read exactly 2 bytes of data. |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 690 | if (Bytes.size() < 2) { |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 691 | Size = 0; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 692 | return MCDisassembler::Fail; |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 693 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 694 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 695 | uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; |
| 696 | DecodeStatus Result = |
| 697 | decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); |
| 698 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 699 | Size = 2; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 700 | Check(Result, AddThumbPredicate(MI)); |
| 701 | return Result; |
Owen Anderson | 91a8f9b | 2011-08-16 23:45:44 +0000 | [diff] [blame] | 702 | } |
| 703 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 704 | Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, |
| 705 | STI); |
| 706 | if (Result) { |
Owen Anderson | 91a8f9b | 2011-08-16 23:45:44 +0000 | [diff] [blame] | 707 | Size = 2; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 708 | bool InITBlock = ITBlock.instrInITBlock(); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 709 | Check(Result, AddThumbPredicate(MI)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 710 | AddThumb1SBit(MI, InITBlock); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 711 | return Result; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 712 | } |
| 713 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 714 | Result = |
| 715 | decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); |
| 716 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 717 | Size = 2; |
Owen Anderson | 6a5c150 | 2011-10-06 23:33:11 +0000 | [diff] [blame] | 718 | |
| 719 | // Nested IT blocks are UNPREDICTABLE. Must be checked before we add |
| 720 | // the Thumb predicate. |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 721 | if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 722 | Result = MCDisassembler::SoftFail; |
Owen Anderson | 6a5c150 | 2011-10-06 23:33:11 +0000 | [diff] [blame] | 723 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 724 | Check(Result, AddThumbPredicate(MI)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 725 | |
| 726 | // If we find an IT instruction, we need to parse its condition |
| 727 | // code and mask operands so that we can apply them correctly |
| 728 | // to the subsequent instructions. |
| 729 | if (MI.getOpcode() == ARM::t2IT) { |
Owen Anderson | f1e3844 | 2011-09-14 21:06:21 +0000 | [diff] [blame] | 730 | |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 731 | unsigned Firstcond = MI.getOperand(0).getImm(); |
Owen Anderson | 2fa06a7 | 2011-08-30 22:58:27 +0000 | [diff] [blame] | 732 | unsigned Mask = MI.getOperand(1).getImm(); |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 733 | ITBlock.setITState(Firstcond, Mask); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 734 | } |
| 735 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 736 | return Result; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | // We want to read exactly 4 bytes of data. |
Rafael Espindola | 7fc5b87 | 2014-11-12 02:04:27 +0000 | [diff] [blame] | 740 | if (Bytes.size() < 4) { |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 741 | Size = 0; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 742 | return MCDisassembler::Fail; |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 743 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 744 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 745 | uint32_t Insn32 = |
| 746 | (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 747 | Result = |
| 748 | decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); |
| 749 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 750 | Size = 4; |
Richard Barton | e960000 | 2012-04-24 11:13:20 +0000 | [diff] [blame] | 751 | bool InITBlock = ITBlock.instrInITBlock(); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 752 | Check(Result, AddThumbPredicate(MI)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 753 | AddThumb1SBit(MI, InITBlock); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 754 | return Result; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 755 | } |
| 756 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 757 | Result = |
| 758 | decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); |
| 759 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 760 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 761 | Check(Result, AddThumbPredicate(MI)); |
| 762 | return Result; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 763 | } |
| 764 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 765 | if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 766 | Result = |
| 767 | decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); |
| 768 | if (Result != MCDisassembler::Fail) { |
Amaury de la Vieuville | 8449c0d | 2013-06-24 09:15:01 +0000 | [diff] [blame] | 769 | Size = 4; |
| 770 | UpdateThumbVFPPredicate(MI); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 771 | return Result; |
Amaury de la Vieuville | 8449c0d | 2013-06-24 09:15:01 +0000 | [diff] [blame] | 772 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 773 | } |
| 774 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 775 | Result = |
| 776 | decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); |
| 777 | if (Result != MCDisassembler::Fail) { |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 778 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 779 | return Result; |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 780 | } |
| 781 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 782 | if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 783 | Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, |
| 784 | STI); |
| 785 | if (Result != MCDisassembler::Fail) { |
Amaury de la Vieuville | 8449c0d | 2013-06-24 09:15:01 +0000 | [diff] [blame] | 786 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 787 | Check(Result, AddThumbPredicate(MI)); |
| 788 | return Result; |
Amaury de la Vieuville | 8449c0d | 2013-06-24 09:15:01 +0000 | [diff] [blame] | 789 | } |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 790 | } |
| 791 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 792 | if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 793 | uint32_t NEONLdStInsn = Insn32; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 794 | NEONLdStInsn &= 0xF0FFFFFF; |
| 795 | NEONLdStInsn |= 0x04000000; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 796 | Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 797 | Address, this, STI); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 798 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 799 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 800 | Check(Result, AddThumbPredicate(MI)); |
| 801 | return Result; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 802 | } |
| 803 | } |
| 804 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 805 | if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 806 | uint32_t NEONDataInsn = Insn32; |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 807 | NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 |
| 808 | NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 |
| 809 | NEONDataInsn |= 0x12000000; // Set bits 28 and 25 |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 810 | Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 811 | Address, this, STI); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 812 | if (Result != MCDisassembler::Fail) { |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 813 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 814 | Check(Result, AddThumbPredicate(MI)); |
| 815 | return Result; |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 816 | } |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 817 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 818 | uint32_t NEONCryptoInsn = Insn32; |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 819 | NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 |
| 820 | NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 |
| 821 | NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 822 | Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 823 | Address, this, STI); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 824 | if (Result != MCDisassembler::Fail) { |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 825 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 826 | return Result; |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 827 | } |
Amara Emerson | 3308909 | 2013-09-19 11:59:01 +0000 | [diff] [blame] | 828 | |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 829 | uint32_t NEONv8Insn = Insn32; |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 830 | NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 831 | Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 832 | this, STI); |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 833 | if (Result != MCDisassembler::Fail) { |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 834 | Size = 4; |
Rafael Espindola | 4aa6bea | 2014-11-10 18:11:10 +0000 | [diff] [blame] | 835 | return Result; |
Artyom Skrobov | c1be9c1 | 2013-10-30 18:10:09 +0000 | [diff] [blame] | 836 | } |
Joey Gouly | df68600 | 2013-07-17 13:59:38 +0000 | [diff] [blame] | 837 | } |
| 838 | |
Sjoerd Meijer | 7426c97 | 2017-08-11 09:52:30 +0000 | [diff] [blame] | 839 | Result = |
| 840 | decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); |
| 841 | if (Result != MCDisassembler::Fail) { |
| 842 | Size = 4; |
| 843 | Check(Result, AddThumbPredicate(MI)); |
| 844 | return Result; |
| 845 | } |
| 846 | |
Benjamin Kramer | aa38dba | 2011-08-26 18:21:36 +0000 | [diff] [blame] | 847 | Size = 0; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 848 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 849 | } |
| 850 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 851 | extern "C" void LLVMInitializeARMDisassembler() { |
Mehdi Amini | f42454b | 2016-10-09 23:00:34 +0000 | [diff] [blame] | 852 | TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 853 | createARMDisassembler); |
Mehdi Amini | f42454b | 2016-10-09 23:00:34 +0000 | [diff] [blame] | 854 | TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), |
Christian Pirker | 2a11160 | 2014-03-28 14:35:30 +0000 | [diff] [blame] | 855 | createARMDisassembler); |
Mehdi Amini | f42454b | 2016-10-09 23:00:34 +0000 | [diff] [blame] | 856 | TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), |
Christian Pirker | 2a11160 | 2014-03-28 14:35:30 +0000 | [diff] [blame] | 857 | createThumbDisassembler); |
Mehdi Amini | f42454b | 2016-10-09 23:00:34 +0000 | [diff] [blame] | 858 | TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 859 | createThumbDisassembler); |
| 860 | } |
| 861 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 862 | static const uint16_t GPRDecoderTable[] = { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 863 | ARM::R0, ARM::R1, ARM::R2, ARM::R3, |
| 864 | ARM::R4, ARM::R5, ARM::R6, ARM::R7, |
| 865 | ARM::R8, ARM::R9, ARM::R10, ARM::R11, |
| 866 | ARM::R12, ARM::SP, ARM::LR, ARM::PC |
| 867 | }; |
| 868 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 869 | static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 870 | uint64_t Address, const void *Decoder) { |
| 871 | if (RegNo > 15) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 872 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 873 | |
| 874 | unsigned Register = GPRDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 875 | Inst.addOperand(MCOperand::createReg(Register)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 876 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 877 | } |
| 878 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 879 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 880 | DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 881 | uint64_t Address, const void *Decoder) { |
Silviu Baranga | 32a4933 | 2012-03-20 15:54:56 +0000 | [diff] [blame] | 882 | DecodeStatus S = MCDisassembler::Success; |
Vinicius Tinti | 67cf33d | 2015-11-20 23:20:12 +0000 | [diff] [blame] | 883 | |
Silviu Baranga | 32a4933 | 2012-03-20 15:54:56 +0000 | [diff] [blame] | 884 | if (RegNo == 15) |
| 885 | S = MCDisassembler::SoftFail; |
| 886 | |
| 887 | Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
| 888 | |
| 889 | return S; |
Owen Anderson | 042619f | 2011-08-09 22:48:45 +0000 | [diff] [blame] | 890 | } |
| 891 | |
Mihai Popa | dc1764c5 | 2013-05-13 14:10:04 +0000 | [diff] [blame] | 892 | static DecodeStatus |
| 893 | DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, |
| 894 | uint64_t Address, const void *Decoder) { |
| 895 | DecodeStatus S = MCDisassembler::Success; |
| 896 | |
| 897 | if (RegNo == 15) |
| 898 | { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 899 | Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); |
Mihai Popa | dc1764c5 | 2013-05-13 14:10:04 +0000 | [diff] [blame] | 900 | return MCDisassembler::Success; |
| 901 | } |
| 902 | |
| 903 | Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
| 904 | return S; |
| 905 | } |
| 906 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 907 | static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 908 | uint64_t Address, const void *Decoder) { |
| 909 | if (RegNo > 7) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 910 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 911 | return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); |
| 912 | } |
| 913 | |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 914 | static const uint16_t GPRPairDecoderTable[] = { |
| 915 | ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, |
| 916 | ARM::R8_R9, ARM::R10_R11, ARM::R12_SP |
| 917 | }; |
| 918 | |
| 919 | static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, |
| 920 | uint64_t Address, const void *Decoder) { |
| 921 | DecodeStatus S = MCDisassembler::Success; |
| 922 | |
| 923 | if (RegNo > 13) |
| 924 | return MCDisassembler::Fail; |
| 925 | |
| 926 | if ((RegNo & 1) || RegNo == 0xe) |
| 927 | S = MCDisassembler::SoftFail; |
| 928 | |
| 929 | unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 930 | Inst.addOperand(MCOperand::createReg(RegisterPair)); |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 931 | return S; |
| 932 | } |
| 933 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 934 | static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 935 | uint64_t Address, const void *Decoder) { |
| 936 | unsigned Register = 0; |
| 937 | switch (RegNo) { |
| 938 | case 0: |
| 939 | Register = ARM::R0; |
| 940 | break; |
| 941 | case 1: |
| 942 | Register = ARM::R1; |
| 943 | break; |
| 944 | case 2: |
| 945 | Register = ARM::R2; |
| 946 | break; |
| 947 | case 3: |
| 948 | Register = ARM::R3; |
| 949 | break; |
| 950 | case 9: |
| 951 | Register = ARM::R9; |
| 952 | break; |
| 953 | case 12: |
| 954 | Register = ARM::R12; |
| 955 | break; |
| 956 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 957 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 958 | } |
| 959 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 960 | Inst.addOperand(MCOperand::createReg(Register)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 961 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 962 | } |
| 963 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 964 | static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 965 | uint64_t Address, const void *Decoder) { |
Amaury de la Vieuville | 8175bda | 2013-06-24 09:14:54 +0000 | [diff] [blame] | 966 | DecodeStatus S = MCDisassembler::Success; |
Artyom Skrobov | b4398107 | 2015-10-28 13:58:36 +0000 | [diff] [blame] | 967 | |
| 968 | const FeatureBitset &featureBits = |
| 969 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 970 | |
| 971 | if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) |
Amaury de la Vieuville | 8175bda | 2013-06-24 09:14:54 +0000 | [diff] [blame] | 972 | S = MCDisassembler::SoftFail; |
Artyom Skrobov | b4398107 | 2015-10-28 13:58:36 +0000 | [diff] [blame] | 973 | |
Amaury de la Vieuville | 8175bda | 2013-06-24 09:14:54 +0000 | [diff] [blame] | 974 | Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); |
| 975 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 976 | } |
| 977 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 978 | static const uint16_t SPRDecoderTable[] = { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 979 | ARM::S0, ARM::S1, ARM::S2, ARM::S3, |
| 980 | ARM::S4, ARM::S5, ARM::S6, ARM::S7, |
| 981 | ARM::S8, ARM::S9, ARM::S10, ARM::S11, |
| 982 | ARM::S12, ARM::S13, ARM::S14, ARM::S15, |
| 983 | ARM::S16, ARM::S17, ARM::S18, ARM::S19, |
| 984 | ARM::S20, ARM::S21, ARM::S22, ARM::S23, |
| 985 | ARM::S24, ARM::S25, ARM::S26, ARM::S27, |
| 986 | ARM::S28, ARM::S29, ARM::S30, ARM::S31 |
| 987 | }; |
| 988 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 989 | static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 990 | uint64_t Address, const void *Decoder) { |
| 991 | if (RegNo > 31) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 992 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 993 | |
| 994 | unsigned Register = SPRDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 995 | Inst.addOperand(MCOperand::createReg(Register)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 996 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 997 | } |
| 998 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 999 | static const uint16_t DPRDecoderTable[] = { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1000 | ARM::D0, ARM::D1, ARM::D2, ARM::D3, |
| 1001 | ARM::D4, ARM::D5, ARM::D6, ARM::D7, |
| 1002 | ARM::D8, ARM::D9, ARM::D10, ARM::D11, |
| 1003 | ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| 1004 | ARM::D16, ARM::D17, ARM::D18, ARM::D19, |
| 1005 | ARM::D20, ARM::D21, ARM::D22, ARM::D23, |
| 1006 | ARM::D24, ARM::D25, ARM::D26, ARM::D27, |
| 1007 | ARM::D28, ARM::D29, ARM::D30, ARM::D31 |
| 1008 | }; |
| 1009 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1010 | static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1011 | uint64_t Address, const void *Decoder) { |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 1012 | const FeatureBitset &featureBits = |
| 1013 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 1014 | |
| 1015 | bool hasD16 = featureBits[ARM::FeatureD16]; |
Oliver Stannard | 9e89d8c | 2014-11-05 12:06:39 +0000 | [diff] [blame] | 1016 | |
| 1017 | if (RegNo > 31 || (hasD16 && RegNo > 15)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1018 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1019 | |
| 1020 | unsigned Register = DPRDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1021 | Inst.addOperand(MCOperand::createReg(Register)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1022 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1023 | } |
| 1024 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1025 | static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1026 | uint64_t Address, const void *Decoder) { |
| 1027 | if (RegNo > 7) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1028 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1029 | return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); |
| 1030 | } |
| 1031 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1032 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1033 | DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 1034 | uint64_t Address, const void *Decoder) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1035 | if (RegNo > 15) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1036 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1037 | return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); |
| 1038 | } |
| 1039 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 1040 | static const uint16_t QPRDecoderTable[] = { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1041 | ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, |
| 1042 | ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, |
| 1043 | ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, |
| 1044 | ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 |
| 1045 | }; |
| 1046 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1047 | static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1048 | uint64_t Address, const void *Decoder) { |
Mihai Popa | dcf0922 | 2013-05-20 14:42:43 +0000 | [diff] [blame] | 1049 | if (RegNo > 31 || (RegNo & 1) != 0) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1050 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1051 | RegNo >>= 1; |
| 1052 | |
| 1053 | unsigned Register = QPRDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1054 | Inst.addOperand(MCOperand::createReg(Register)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1055 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 1058 | static const uint16_t DPairDecoderTable[] = { |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1059 | ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, |
| 1060 | ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, |
| 1061 | ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, |
| 1062 | ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, |
| 1063 | ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, |
| 1064 | ARM::Q15 |
| 1065 | }; |
| 1066 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1067 | static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1068 | uint64_t Address, const void *Decoder) { |
| 1069 | if (RegNo > 30) |
| 1070 | return MCDisassembler::Fail; |
| 1071 | |
| 1072 | unsigned Register = DPairDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1073 | Inst.addOperand(MCOperand::createReg(Register)); |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1074 | return MCDisassembler::Success; |
| 1075 | } |
| 1076 | |
Craig Topper | ca658c2 | 2012-03-11 07:16:55 +0000 | [diff] [blame] | 1077 | static const uint16_t DPairSpacedDecoderTable[] = { |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 1078 | ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, |
| 1079 | ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, |
| 1080 | ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, |
| 1081 | ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, |
| 1082 | ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, |
| 1083 | ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, |
| 1084 | ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, |
| 1085 | ARM::D28_D30, ARM::D29_D31 |
| 1086 | }; |
| 1087 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1088 | static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 1089 | unsigned RegNo, |
| 1090 | uint64_t Address, |
| 1091 | const void *Decoder) { |
| 1092 | if (RegNo > 29) |
| 1093 | return MCDisassembler::Fail; |
| 1094 | |
| 1095 | unsigned Register = DPairSpacedDecoderTable[RegNo]; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1096 | Inst.addOperand(MCOperand::createReg(Register)); |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 1097 | return MCDisassembler::Success; |
| 1098 | } |
| 1099 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1100 | static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1101 | uint64_t Address, const void *Decoder) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1102 | if (Val == 0xF) return MCDisassembler::Fail; |
Owen Anderson | 7a2401d | 2011-08-09 21:07:45 +0000 | [diff] [blame] | 1103 | // AL predicate is not allowed on Thumb1 branches. |
| 1104 | if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1105 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1106 | Inst.addOperand(MCOperand::createImm(Val)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1107 | if (Val == ARMCC::AL) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1108 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1109 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1110 | Inst.addOperand(MCOperand::createReg(ARM::CPSR)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1111 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1112 | } |
| 1113 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1114 | static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1115 | uint64_t Address, const void *Decoder) { |
| 1116 | if (Val) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1117 | Inst.addOperand(MCOperand::createReg(ARM::CPSR)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1118 | else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1119 | Inst.addOperand(MCOperand::createReg(0)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1120 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1121 | } |
| 1122 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1123 | static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1124 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1125 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1126 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1127 | unsigned Rm = fieldFromInstruction(Val, 0, 4); |
| 1128 | unsigned type = fieldFromInstruction(Val, 5, 2); |
| 1129 | unsigned imm = fieldFromInstruction(Val, 7, 5); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1130 | |
| 1131 | // Register-immediate |
Artyom Skrobov | b4398107 | 2015-10-28 13:58:36 +0000 | [diff] [blame] | 1132 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1133 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1134 | |
| 1135 | ARM_AM::ShiftOpc Shift = ARM_AM::lsl; |
| 1136 | switch (type) { |
| 1137 | case 0: |
| 1138 | Shift = ARM_AM::lsl; |
| 1139 | break; |
| 1140 | case 1: |
| 1141 | Shift = ARM_AM::lsr; |
| 1142 | break; |
| 1143 | case 2: |
| 1144 | Shift = ARM_AM::asr; |
| 1145 | break; |
| 1146 | case 3: |
| 1147 | Shift = ARM_AM::ror; |
| 1148 | break; |
| 1149 | } |
| 1150 | |
| 1151 | if (Shift == ARM_AM::ror && imm == 0) |
| 1152 | Shift = ARM_AM::rrx; |
| 1153 | |
| 1154 | unsigned Op = Shift | (imm << 3); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1155 | Inst.addOperand(MCOperand::createImm(Op)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1156 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1157 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1158 | } |
| 1159 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1160 | static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1161 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1162 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1163 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1164 | unsigned Rm = fieldFromInstruction(Val, 0, 4); |
| 1165 | unsigned type = fieldFromInstruction(Val, 5, 2); |
| 1166 | unsigned Rs = fieldFromInstruction(Val, 8, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1167 | |
| 1168 | // Register-register |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1169 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
| 1170 | return MCDisassembler::Fail; |
| 1171 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) |
| 1172 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1173 | |
| 1174 | ARM_AM::ShiftOpc Shift = ARM_AM::lsl; |
| 1175 | switch (type) { |
| 1176 | case 0: |
| 1177 | Shift = ARM_AM::lsl; |
| 1178 | break; |
| 1179 | case 1: |
| 1180 | Shift = ARM_AM::lsr; |
| 1181 | break; |
| 1182 | case 2: |
| 1183 | Shift = ARM_AM::asr; |
| 1184 | break; |
| 1185 | case 3: |
| 1186 | Shift = ARM_AM::ror; |
| 1187 | break; |
| 1188 | } |
| 1189 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1190 | Inst.addOperand(MCOperand::createImm(Shift)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1191 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1192 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1195 | static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1196 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1197 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1198 | |
Tim Northover | 08a8660 | 2013-10-22 19:00:39 +0000 | [diff] [blame] | 1199 | bool NeedDisjointWriteback = false; |
| 1200 | unsigned WritebackReg = 0; |
Owen Anderson | 53db43b | 2011-09-09 23:13:33 +0000 | [diff] [blame] | 1201 | switch (Inst.getOpcode()) { |
Tim Northover | 08a8660 | 2013-10-22 19:00:39 +0000 | [diff] [blame] | 1202 | default: |
| 1203 | break; |
| 1204 | case ARM::LDMIA_UPD: |
| 1205 | case ARM::LDMDB_UPD: |
| 1206 | case ARM::LDMIB_UPD: |
| 1207 | case ARM::LDMDA_UPD: |
| 1208 | case ARM::t2LDMIA_UPD: |
| 1209 | case ARM::t2LDMDB_UPD: |
| 1210 | case ARM::t2STMIA_UPD: |
| 1211 | case ARM::t2STMDB_UPD: |
| 1212 | NeedDisjointWriteback = true; |
| 1213 | WritebackReg = Inst.getOperand(0).getReg(); |
| 1214 | break; |
Owen Anderson | 53db43b | 2011-09-09 23:13:33 +0000 | [diff] [blame] | 1215 | } |
| 1216 | |
Owen Anderson | 6066340 | 2011-08-11 20:21:46 +0000 | [diff] [blame] | 1217 | // Empty register lists are not allowed. |
Benjamin Kramer | 8bad66e | 2013-05-19 22:01:57 +0000 | [diff] [blame] | 1218 | if (Val == 0) return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1219 | for (unsigned i = 0; i < 16; ++i) { |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1220 | if (Val & (1 << i)) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1221 | if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) |
| 1222 | return MCDisassembler::Fail; |
Owen Anderson | 53db43b | 2011-09-09 23:13:33 +0000 | [diff] [blame] | 1223 | // Writeback not allowed if Rn is in the target list. |
Tim Northover | 08a8660 | 2013-10-22 19:00:39 +0000 | [diff] [blame] | 1224 | if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) |
Owen Anderson | 53db43b | 2011-09-09 23:13:33 +0000 | [diff] [blame] | 1225 | Check(S, MCDisassembler::SoftFail); |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1226 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1227 | } |
| 1228 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1229 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1230 | } |
| 1231 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1232 | static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1233 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1234 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1235 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1236 | unsigned Vd = fieldFromInstruction(Val, 8, 5); |
| 1237 | unsigned regs = fieldFromInstruction(Val, 0, 8); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1238 | |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1239 | // In case of unpredictable encoding, tweak the operands. |
| 1240 | if (regs == 0 || (Vd + regs) > 32) { |
| 1241 | regs = Vd + regs > 32 ? 32 - Vd : regs; |
| 1242 | regs = std::max( 1u, regs); |
| 1243 | S = MCDisassembler::SoftFail; |
| 1244 | } |
| 1245 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1246 | if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) |
| 1247 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1248 | for (unsigned i = 0; i < (regs - 1); ++i) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1249 | if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) |
| 1250 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1251 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1252 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1253 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1254 | } |
| 1255 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1256 | static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1257 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1258 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1259 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1260 | unsigned Vd = fieldFromInstruction(Val, 8, 5); |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1261 | unsigned regs = fieldFromInstruction(Val, 1, 7); |
Silviu Baranga | 9560af8 | 2012-05-03 16:38:40 +0000 | [diff] [blame] | 1262 | |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1263 | // In case of unpredictable encoding, tweak the operands. |
| 1264 | if (regs == 0 || regs > 16 || (Vd + regs) > 32) { |
| 1265 | regs = Vd + regs > 32 ? 32 - Vd : regs; |
| 1266 | regs = std::max( 1u, regs); |
| 1267 | regs = std::min(16u, regs); |
| 1268 | S = MCDisassembler::SoftFail; |
| 1269 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1270 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1271 | if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
| 1272 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1273 | for (unsigned i = 0; i < (regs - 1); ++i) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1274 | if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) |
| 1275 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 1276 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1277 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1278 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1279 | } |
| 1280 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1281 | static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1282 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 1283 | // This operand encodes a mask of contiguous zeros between a specified MSB |
| 1284 | // and LSB. To decode it, we create the mask of all bits MSB-and-lower, |
| 1285 | // the mask of all bits LSB-and-lower, and then xor them to create |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 1286 | // the mask of that's all ones on [msb, lsb]. Finally we not it to |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 1287 | // create the final mask. |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1288 | unsigned msb = fieldFromInstruction(Val, 5, 5); |
| 1289 | unsigned lsb = fieldFromInstruction(Val, 0, 5); |
Owen Anderson | 3ca958c | 2011-09-16 22:29:48 +0000 | [diff] [blame] | 1290 | |
Owen Anderson | 502cd9d | 2011-09-16 23:30:01 +0000 | [diff] [blame] | 1291 | DecodeStatus S = MCDisassembler::Success; |
Kevin Enderby | 136d674 | 2012-11-29 23:47:11 +0000 | [diff] [blame] | 1292 | if (lsb > msb) { |
| 1293 | Check(S, MCDisassembler::SoftFail); |
| 1294 | // The check above will cause the warning for the "potentially undefined |
| 1295 | // instruction encoding" but we can't build a bad MCOperand value here |
| 1296 | // with a lsb > msb or else printing the MCInst will cause a crash. |
| 1297 | lsb = msb; |
| 1298 | } |
Owen Anderson | 502cd9d | 2011-09-16 23:30:01 +0000 | [diff] [blame] | 1299 | |
Owen Anderson | b925e93 | 2011-09-16 23:04:48 +0000 | [diff] [blame] | 1300 | uint32_t msb_mask = 0xFFFFFFFF; |
| 1301 | if (msb != 31) msb_mask = (1U << (msb+1)) - 1; |
| 1302 | uint32_t lsb_mask = (1U << lsb) - 1; |
Owen Anderson | 3ca958c | 2011-09-16 22:29:48 +0000 | [diff] [blame] | 1303 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1304 | Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); |
Owen Anderson | 502cd9d | 2011-09-16 23:30:01 +0000 | [diff] [blame] | 1305 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1306 | } |
| 1307 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1308 | static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1309 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1310 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1311 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1312 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1313 | unsigned CRd = fieldFromInstruction(Insn, 12, 4); |
| 1314 | unsigned coproc = fieldFromInstruction(Insn, 8, 4); |
| 1315 | unsigned imm = fieldFromInstruction(Insn, 0, 8); |
| 1316 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1317 | unsigned U = fieldFromInstruction(Insn, 23, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1318 | |
| 1319 | switch (Inst.getOpcode()) { |
| 1320 | case ARM::LDC_OFFSET: |
| 1321 | case ARM::LDC_PRE: |
| 1322 | case ARM::LDC_POST: |
| 1323 | case ARM::LDC_OPTION: |
| 1324 | case ARM::LDCL_OFFSET: |
| 1325 | case ARM::LDCL_PRE: |
| 1326 | case ARM::LDCL_POST: |
| 1327 | case ARM::LDCL_OPTION: |
| 1328 | case ARM::STC_OFFSET: |
| 1329 | case ARM::STC_PRE: |
| 1330 | case ARM::STC_POST: |
| 1331 | case ARM::STC_OPTION: |
| 1332 | case ARM::STCL_OFFSET: |
| 1333 | case ARM::STCL_PRE: |
| 1334 | case ARM::STCL_POST: |
| 1335 | case ARM::STCL_OPTION: |
Owen Anderson | 18d17aa | 2011-09-07 21:10:42 +0000 | [diff] [blame] | 1336 | case ARM::t2LDC_OFFSET: |
| 1337 | case ARM::t2LDC_PRE: |
| 1338 | case ARM::t2LDC_POST: |
| 1339 | case ARM::t2LDC_OPTION: |
| 1340 | case ARM::t2LDCL_OFFSET: |
| 1341 | case ARM::t2LDCL_PRE: |
| 1342 | case ARM::t2LDCL_POST: |
| 1343 | case ARM::t2LDCL_OPTION: |
| 1344 | case ARM::t2STC_OFFSET: |
| 1345 | case ARM::t2STC_PRE: |
| 1346 | case ARM::t2STC_POST: |
| 1347 | case ARM::t2STC_OPTION: |
| 1348 | case ARM::t2STCL_OFFSET: |
| 1349 | case ARM::t2STCL_PRE: |
| 1350 | case ARM::t2STCL_POST: |
| 1351 | case ARM::t2STCL_OPTION: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1352 | if (coproc == 0xA || coproc == 0xB) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1353 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1354 | break; |
| 1355 | default: |
| 1356 | break; |
| 1357 | } |
| 1358 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 1359 | const FeatureBitset &featureBits = |
| 1360 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 1361 | if (featureBits[ARM::HasV8Ops] && (coproc != 14)) |
Artyom Skrobov | e686cec | 2013-11-08 16:16:30 +0000 | [diff] [blame] | 1362 | return MCDisassembler::Fail; |
| 1363 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1364 | Inst.addOperand(MCOperand::createImm(coproc)); |
| 1365 | Inst.addOperand(MCOperand::createImm(CRd)); |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1366 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1367 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1368 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1369 | switch (Inst.getOpcode()) { |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1370 | case ARM::t2LDC2_OFFSET: |
| 1371 | case ARM::t2LDC2L_OFFSET: |
| 1372 | case ARM::t2LDC2_PRE: |
| 1373 | case ARM::t2LDC2L_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1374 | case ARM::t2STC2_OFFSET: |
| 1375 | case ARM::t2STC2L_OFFSET: |
| 1376 | case ARM::t2STC2_PRE: |
| 1377 | case ARM::t2STC2L_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1378 | case ARM::LDC2_OFFSET: |
| 1379 | case ARM::LDC2L_OFFSET: |
| 1380 | case ARM::LDC2_PRE: |
| 1381 | case ARM::LDC2L_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1382 | case ARM::STC2_OFFSET: |
| 1383 | case ARM::STC2L_OFFSET: |
| 1384 | case ARM::STC2_PRE: |
| 1385 | case ARM::STC2L_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1386 | case ARM::t2LDC_OFFSET: |
| 1387 | case ARM::t2LDCL_OFFSET: |
| 1388 | case ARM::t2LDC_PRE: |
| 1389 | case ARM::t2LDCL_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1390 | case ARM::t2STC_OFFSET: |
| 1391 | case ARM::t2STCL_OFFSET: |
| 1392 | case ARM::t2STC_PRE: |
| 1393 | case ARM::t2STCL_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1394 | case ARM::LDC_OFFSET: |
| 1395 | case ARM::LDCL_OFFSET: |
| 1396 | case ARM::LDC_PRE: |
| 1397 | case ARM::LDCL_PRE: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1398 | case ARM::STC_OFFSET: |
| 1399 | case ARM::STCL_OFFSET: |
| 1400 | case ARM::STC_PRE: |
| 1401 | case ARM::STCL_PRE: |
Jim Grosbach | a098a89 | 2011-10-12 21:59:02 +0000 | [diff] [blame] | 1402 | imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1403 | Inst.addOperand(MCOperand::createImm(imm)); |
Jim Grosbach | a098a89 | 2011-10-12 21:59:02 +0000 | [diff] [blame] | 1404 | break; |
| 1405 | case ARM::t2LDC2_POST: |
| 1406 | case ARM::t2LDC2L_POST: |
| 1407 | case ARM::t2STC2_POST: |
| 1408 | case ARM::t2STC2L_POST: |
| 1409 | case ARM::LDC2_POST: |
| 1410 | case ARM::LDC2L_POST: |
| 1411 | case ARM::STC2_POST: |
| 1412 | case ARM::STC2L_POST: |
| 1413 | case ARM::t2LDC_POST: |
| 1414 | case ARM::t2LDCL_POST: |
| 1415 | case ARM::t2STC_POST: |
| 1416 | case ARM::t2STCL_POST: |
| 1417 | case ARM::LDC_POST: |
| 1418 | case ARM::LDCL_POST: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1419 | case ARM::STC_POST: |
| 1420 | case ARM::STCL_POST: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1421 | imm |= U << 8; |
Justin Bogner | cd1d5aa | 2016-08-17 20:30:52 +0000 | [diff] [blame] | 1422 | LLVM_FALLTHROUGH; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1423 | default: |
Jim Grosbach | 54a20ed | 2011-10-12 20:54:17 +0000 | [diff] [blame] | 1424 | // The 'option' variant doesn't encode 'U' in the immediate since |
| 1425 | // the immediate is unsigned [0,255]. |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1426 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1427 | break; |
| 1428 | } |
| 1429 | |
| 1430 | switch (Inst.getOpcode()) { |
| 1431 | case ARM::LDC_OFFSET: |
| 1432 | case ARM::LDC_PRE: |
| 1433 | case ARM::LDC_POST: |
| 1434 | case ARM::LDC_OPTION: |
| 1435 | case ARM::LDCL_OFFSET: |
| 1436 | case ARM::LDCL_PRE: |
| 1437 | case ARM::LDCL_POST: |
| 1438 | case ARM::LDCL_OPTION: |
| 1439 | case ARM::STC_OFFSET: |
| 1440 | case ARM::STC_PRE: |
| 1441 | case ARM::STC_POST: |
| 1442 | case ARM::STC_OPTION: |
| 1443 | case ARM::STCL_OFFSET: |
| 1444 | case ARM::STCL_PRE: |
| 1445 | case ARM::STCL_POST: |
| 1446 | case ARM::STCL_OPTION: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1447 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1448 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1449 | break; |
| 1450 | default: |
| 1451 | break; |
| 1452 | } |
| 1453 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1454 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1455 | } |
| 1456 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1457 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1458 | DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 1459 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1460 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1461 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1462 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1463 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 1464 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 1465 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 1466 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1467 | unsigned reg = fieldFromInstruction(Insn, 25, 1); |
| 1468 | unsigned P = fieldFromInstruction(Insn, 24, 1); |
| 1469 | unsigned W = fieldFromInstruction(Insn, 21, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1470 | |
| 1471 | // On stores, the writeback operand precedes Rt. |
| 1472 | switch (Inst.getOpcode()) { |
| 1473 | case ARM::STR_POST_IMM: |
| 1474 | case ARM::STR_POST_REG: |
Owen Anderson | 3a850f2 | 2011-08-11 20:47:56 +0000 | [diff] [blame] | 1475 | case ARM::STRB_POST_IMM: |
| 1476 | case ARM::STRB_POST_REG: |
Jim Grosbach | e259421 | 2011-08-11 22:18:00 +0000 | [diff] [blame] | 1477 | case ARM::STRT_POST_REG: |
| 1478 | case ARM::STRT_POST_IMM: |
Jim Grosbach | 2a50260 | 2011-08-11 20:04:56 +0000 | [diff] [blame] | 1479 | case ARM::STRBT_POST_REG: |
| 1480 | case ARM::STRBT_POST_IMM: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1481 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1482 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1483 | break; |
| 1484 | default: |
| 1485 | break; |
| 1486 | } |
| 1487 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1488 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 1489 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1490 | |
| 1491 | // On loads, the writeback operand comes after Rt. |
| 1492 | switch (Inst.getOpcode()) { |
| 1493 | case ARM::LDR_POST_IMM: |
| 1494 | case ARM::LDR_POST_REG: |
Owen Anderson | 3a850f2 | 2011-08-11 20:47:56 +0000 | [diff] [blame] | 1495 | case ARM::LDRB_POST_IMM: |
| 1496 | case ARM::LDRB_POST_REG: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1497 | case ARM::LDRBT_POST_REG: |
| 1498 | case ARM::LDRBT_POST_IMM: |
Jim Grosbach | d5d6359 | 2011-08-10 23:43:54 +0000 | [diff] [blame] | 1499 | case ARM::LDRT_POST_REG: |
| 1500 | case ARM::LDRT_POST_IMM: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1501 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1502 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1503 | break; |
| 1504 | default: |
| 1505 | break; |
| 1506 | } |
| 1507 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1508 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1509 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1510 | |
| 1511 | ARM_AM::AddrOpc Op = ARM_AM::add; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1512 | if (!fieldFromInstruction(Insn, 23, 1)) |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1513 | Op = ARM_AM::sub; |
| 1514 | |
| 1515 | bool writeback = (P == 0) || (W == 1); |
| 1516 | unsigned idx_mode = 0; |
| 1517 | if (P && writeback) |
| 1518 | idx_mode = ARMII::IndexModePre; |
| 1519 | else if (!P && writeback) |
| 1520 | idx_mode = ARMII::IndexModePost; |
| 1521 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1522 | if (writeback && (Rn == 15 || Rn == Rt)) |
| 1523 | S = MCDisassembler::SoftFail; // UNPREDICTABLE |
Owen Anderson | 3477f2c | 2011-08-11 19:00:18 +0000 | [diff] [blame] | 1524 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1525 | if (reg) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1526 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
| 1527 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1528 | ARM_AM::ShiftOpc Opc = ARM_AM::lsl; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1529 | switch( fieldFromInstruction(Insn, 5, 2)) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1530 | case 0: |
| 1531 | Opc = ARM_AM::lsl; |
| 1532 | break; |
| 1533 | case 1: |
| 1534 | Opc = ARM_AM::lsr; |
| 1535 | break; |
| 1536 | case 2: |
| 1537 | Opc = ARM_AM::asr; |
| 1538 | break; |
| 1539 | case 3: |
| 1540 | Opc = ARM_AM::ror; |
| 1541 | break; |
| 1542 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1543 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1544 | } |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1545 | unsigned amt = fieldFromInstruction(Insn, 7, 5); |
Tim Northover | 0c97e76 | 2012-09-22 11:18:12 +0000 | [diff] [blame] | 1546 | if (Opc == ARM_AM::ror && amt == 0) |
| 1547 | Opc = ARM_AM::rrx; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1548 | unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); |
| 1549 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1550 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1551 | } else { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1552 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1553 | unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1554 | Inst.addOperand(MCOperand::createImm(tmp)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1555 | } |
| 1556 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1557 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1558 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1559 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1560 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1561 | } |
| 1562 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1563 | static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1564 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1565 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1566 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1567 | unsigned Rn = fieldFromInstruction(Val, 13, 4); |
| 1568 | unsigned Rm = fieldFromInstruction(Val, 0, 4); |
| 1569 | unsigned type = fieldFromInstruction(Val, 5, 2); |
| 1570 | unsigned imm = fieldFromInstruction(Val, 7, 5); |
| 1571 | unsigned U = fieldFromInstruction(Val, 12, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1572 | |
Owen Anderson | d151b09 | 2011-08-09 21:38:14 +0000 | [diff] [blame] | 1573 | ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1574 | switch (type) { |
| 1575 | case 0: |
| 1576 | ShOp = ARM_AM::lsl; |
| 1577 | break; |
| 1578 | case 1: |
| 1579 | ShOp = ARM_AM::lsr; |
| 1580 | break; |
| 1581 | case 2: |
| 1582 | ShOp = ARM_AM::asr; |
| 1583 | break; |
| 1584 | case 3: |
| 1585 | ShOp = ARM_AM::ror; |
| 1586 | break; |
| 1587 | } |
| 1588 | |
Tim Northover | 0c97e76 | 2012-09-22 11:18:12 +0000 | [diff] [blame] | 1589 | if (ShOp == ARM_AM::ror && imm == 0) |
| 1590 | ShOp = ARM_AM::rrx; |
| 1591 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1592 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1593 | return MCDisassembler::Fail; |
| 1594 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 1595 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1596 | unsigned shift; |
| 1597 | if (U) |
| 1598 | shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); |
| 1599 | else |
| 1600 | shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1601 | Inst.addOperand(MCOperand::createImm(shift)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1602 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1603 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1604 | } |
| 1605 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1606 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1607 | DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 1608 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1609 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1610 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1611 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 1612 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1613 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 1614 | unsigned type = fieldFromInstruction(Insn, 22, 1); |
| 1615 | unsigned imm = fieldFromInstruction(Insn, 8, 4); |
| 1616 | unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; |
| 1617 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1618 | unsigned W = fieldFromInstruction(Insn, 21, 1); |
| 1619 | unsigned P = fieldFromInstruction(Insn, 24, 1); |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1620 | unsigned Rt2 = Rt + 1; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1621 | |
| 1622 | bool writeback = (W == 1) | (P == 0); |
Owen Anderson | 1d5d2ca | 2011-08-15 20:51:32 +0000 | [diff] [blame] | 1623 | |
| 1624 | // For {LD,ST}RD, Rt must be even, else undefined. |
| 1625 | switch (Inst.getOpcode()) { |
| 1626 | case ARM::STRD: |
| 1627 | case ARM::STRD_PRE: |
| 1628 | case ARM::STRD_POST: |
| 1629 | case ARM::LDRD: |
| 1630 | case ARM::LDRD_PRE: |
| 1631 | case ARM::LDRD_POST: |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1632 | if (Rt & 0x1) S = MCDisassembler::SoftFail; |
| 1633 | break; |
| 1634 | default: |
| 1635 | break; |
| 1636 | } |
| 1637 | switch (Inst.getOpcode()) { |
| 1638 | case ARM::STRD: |
| 1639 | case ARM::STRD_PRE: |
| 1640 | case ARM::STRD_POST: |
| 1641 | if (P == 0 && W == 1) |
| 1642 | S = MCDisassembler::SoftFail; |
Vinicius Tinti | 67cf33d | 2015-11-20 23:20:12 +0000 | [diff] [blame] | 1643 | |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1644 | if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) |
| 1645 | S = MCDisassembler::SoftFail; |
| 1646 | if (type && Rm == 15) |
| 1647 | S = MCDisassembler::SoftFail; |
| 1648 | if (Rt2 == 15) |
| 1649 | S = MCDisassembler::SoftFail; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1650 | if (!type && fieldFromInstruction(Insn, 8, 4)) |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1651 | S = MCDisassembler::SoftFail; |
| 1652 | break; |
| 1653 | case ARM::STRH: |
| 1654 | case ARM::STRH_PRE: |
| 1655 | case ARM::STRH_POST: |
| 1656 | if (Rt == 15) |
| 1657 | S = MCDisassembler::SoftFail; |
| 1658 | if (writeback && (Rn == 15 || Rn == Rt)) |
| 1659 | S = MCDisassembler::SoftFail; |
| 1660 | if (!type && Rm == 15) |
| 1661 | S = MCDisassembler::SoftFail; |
| 1662 | break; |
| 1663 | case ARM::LDRD: |
| 1664 | case ARM::LDRD_PRE: |
| 1665 | case ARM::LDRD_POST: |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 1666 | if (type && Rn == 15) { |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1667 | if (Rt2 == 15) |
| 1668 | S = MCDisassembler::SoftFail; |
| 1669 | break; |
| 1670 | } |
| 1671 | if (P == 0 && W == 1) |
| 1672 | S = MCDisassembler::SoftFail; |
| 1673 | if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) |
| 1674 | S = MCDisassembler::SoftFail; |
| 1675 | if (!type && writeback && Rn == 15) |
| 1676 | S = MCDisassembler::SoftFail; |
| 1677 | if (writeback && (Rn == Rt || Rn == Rt2)) |
| 1678 | S = MCDisassembler::SoftFail; |
| 1679 | break; |
| 1680 | case ARM::LDRH: |
| 1681 | case ARM::LDRH_PRE: |
| 1682 | case ARM::LDRH_POST: |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 1683 | if (type && Rn == 15) { |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1684 | if (Rt == 15) |
| 1685 | S = MCDisassembler::SoftFail; |
| 1686 | break; |
| 1687 | } |
| 1688 | if (Rt == 15) |
| 1689 | S = MCDisassembler::SoftFail; |
| 1690 | if (!type && Rm == 15) |
| 1691 | S = MCDisassembler::SoftFail; |
| 1692 | if (!type && writeback && (Rn == 15 || Rn == Rt)) |
| 1693 | S = MCDisassembler::SoftFail; |
| 1694 | break; |
| 1695 | case ARM::LDRSH: |
| 1696 | case ARM::LDRSH_PRE: |
| 1697 | case ARM::LDRSH_POST: |
| 1698 | case ARM::LDRSB: |
| 1699 | case ARM::LDRSB_PRE: |
| 1700 | case ARM::LDRSB_POST: |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 1701 | if (type && Rn == 15) { |
Silviu Baranga | 4afd7d2 | 2012-03-22 14:14:49 +0000 | [diff] [blame] | 1702 | if (Rt == 15) |
| 1703 | S = MCDisassembler::SoftFail; |
| 1704 | break; |
| 1705 | } |
| 1706 | if (type && (Rt == 15 || (writeback && Rn == Rt))) |
| 1707 | S = MCDisassembler::SoftFail; |
| 1708 | if (!type && (Rt == 15 || Rm == 15)) |
| 1709 | S = MCDisassembler::SoftFail; |
| 1710 | if (!type && writeback && (Rn == 15 || Rn == Rt)) |
| 1711 | S = MCDisassembler::SoftFail; |
Owen Anderson | 1d5d2ca | 2011-08-15 20:51:32 +0000 | [diff] [blame] | 1712 | break; |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1713 | default: |
| 1714 | break; |
Owen Anderson | 1d5d2ca | 2011-08-15 20:51:32 +0000 | [diff] [blame] | 1715 | } |
| 1716 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1717 | if (writeback) { // Writeback |
| 1718 | if (P) |
| 1719 | U |= ARMII::IndexModePre << 9; |
| 1720 | else |
| 1721 | U |= ARMII::IndexModePost << 9; |
| 1722 | |
| 1723 | // On stores, the writeback operand precedes Rt. |
| 1724 | switch (Inst.getOpcode()) { |
| 1725 | case ARM::STRD: |
| 1726 | case ARM::STRD_PRE: |
| 1727 | case ARM::STRD_POST: |
Owen Anderson | 60138ea | 2011-08-12 20:02:50 +0000 | [diff] [blame] | 1728 | case ARM::STRH: |
| 1729 | case ARM::STRH_PRE: |
| 1730 | case ARM::STRH_POST: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1731 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1732 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1733 | break; |
| 1734 | default: |
| 1735 | break; |
| 1736 | } |
| 1737 | } |
| 1738 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1739 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 1740 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1741 | switch (Inst.getOpcode()) { |
| 1742 | case ARM::STRD: |
| 1743 | case ARM::STRD_PRE: |
| 1744 | case ARM::STRD_POST: |
| 1745 | case ARM::LDRD: |
| 1746 | case ARM::LDRD_PRE: |
| 1747 | case ARM::LDRD_POST: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1748 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) |
| 1749 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1750 | break; |
| 1751 | default: |
| 1752 | break; |
| 1753 | } |
| 1754 | |
| 1755 | if (writeback) { |
| 1756 | // On loads, the writeback operand comes after Rt. |
| 1757 | switch (Inst.getOpcode()) { |
| 1758 | case ARM::LDRD: |
| 1759 | case ARM::LDRD_PRE: |
| 1760 | case ARM::LDRD_POST: |
Owen Anderson | 2d1d7a1 | 2011-08-12 20:36:11 +0000 | [diff] [blame] | 1761 | case ARM::LDRH: |
| 1762 | case ARM::LDRH_PRE: |
| 1763 | case ARM::LDRH_POST: |
| 1764 | case ARM::LDRSH: |
| 1765 | case ARM::LDRSH_PRE: |
| 1766 | case ARM::LDRSH_POST: |
| 1767 | case ARM::LDRSB: |
| 1768 | case ARM::LDRSB_PRE: |
| 1769 | case ARM::LDRSB_POST: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1770 | case ARM::LDRHTr: |
| 1771 | case ARM::LDRSBTr: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1772 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1773 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1774 | break; |
| 1775 | default: |
| 1776 | break; |
| 1777 | } |
| 1778 | } |
| 1779 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1780 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1781 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1782 | |
| 1783 | if (type) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1784 | Inst.addOperand(MCOperand::createReg(0)); |
| 1785 | Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1786 | } else { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1787 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 1788 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1789 | Inst.addOperand(MCOperand::createImm(U)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1790 | } |
| 1791 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1792 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1793 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1794 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1795 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1796 | } |
| 1797 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1798 | static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1799 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1800 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1801 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1802 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1803 | unsigned mode = fieldFromInstruction(Insn, 23, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1804 | |
| 1805 | switch (mode) { |
| 1806 | case 0: |
| 1807 | mode = ARM_AM::da; |
| 1808 | break; |
| 1809 | case 1: |
| 1810 | mode = ARM_AM::ia; |
| 1811 | break; |
| 1812 | case 2: |
| 1813 | mode = ARM_AM::db; |
| 1814 | break; |
| 1815 | case 3: |
| 1816 | mode = ARM_AM::ib; |
| 1817 | break; |
| 1818 | } |
| 1819 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1820 | Inst.addOperand(MCOperand::createImm(mode)); |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1821 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1822 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1823 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1824 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1825 | } |
| 1826 | |
Amaury de la Vieuville | 631df63 | 2013-06-08 13:38:52 +0000 | [diff] [blame] | 1827 | static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, |
| 1828 | uint64_t Address, const void *Decoder) { |
| 1829 | DecodeStatus S = MCDisassembler::Success; |
| 1830 | |
| 1831 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 1832 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 1833 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1834 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1835 | |
| 1836 | if (pred == 0xF) |
| 1837 | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
| 1838 | |
| 1839 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
| 1840 | return MCDisassembler::Fail; |
| 1841 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
| 1842 | return MCDisassembler::Fail; |
| 1843 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
| 1844 | return MCDisassembler::Fail; |
| 1845 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1846 | return MCDisassembler::Fail; |
| 1847 | return S; |
| 1848 | } |
| 1849 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1850 | static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1851 | unsigned Insn, |
| 1852 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1853 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1854 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1855 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 1856 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1857 | unsigned reglist = fieldFromInstruction(Insn, 0, 16); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1858 | |
| 1859 | if (pred == 0xF) { |
Amaury de la Vieuville | 68bcd02 | 2013-06-08 13:43:59 +0000 | [diff] [blame] | 1860 | // Ambiguous with RFE and SRS |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1861 | switch (Inst.getOpcode()) { |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1862 | case ARM::LDMDA: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1863 | Inst.setOpcode(ARM::RFEDA); |
| 1864 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1865 | case ARM::LDMDA_UPD: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1866 | Inst.setOpcode(ARM::RFEDA_UPD); |
| 1867 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1868 | case ARM::LDMDB: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1869 | Inst.setOpcode(ARM::RFEDB); |
| 1870 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1871 | case ARM::LDMDB_UPD: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1872 | Inst.setOpcode(ARM::RFEDB_UPD); |
| 1873 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1874 | case ARM::LDMIA: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1875 | Inst.setOpcode(ARM::RFEIA); |
| 1876 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1877 | case ARM::LDMIA_UPD: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1878 | Inst.setOpcode(ARM::RFEIA_UPD); |
| 1879 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1880 | case ARM::LDMIB: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1881 | Inst.setOpcode(ARM::RFEIB); |
| 1882 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1883 | case ARM::LDMIB_UPD: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1884 | Inst.setOpcode(ARM::RFEIB_UPD); |
| 1885 | break; |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1886 | case ARM::STMDA: |
| 1887 | Inst.setOpcode(ARM::SRSDA); |
| 1888 | break; |
| 1889 | case ARM::STMDA_UPD: |
| 1890 | Inst.setOpcode(ARM::SRSDA_UPD); |
| 1891 | break; |
| 1892 | case ARM::STMDB: |
| 1893 | Inst.setOpcode(ARM::SRSDB); |
| 1894 | break; |
| 1895 | case ARM::STMDB_UPD: |
| 1896 | Inst.setOpcode(ARM::SRSDB_UPD); |
| 1897 | break; |
| 1898 | case ARM::STMIA: |
| 1899 | Inst.setOpcode(ARM::SRSIA); |
| 1900 | break; |
| 1901 | case ARM::STMIA_UPD: |
| 1902 | Inst.setOpcode(ARM::SRSIA_UPD); |
| 1903 | break; |
| 1904 | case ARM::STMIB: |
| 1905 | Inst.setOpcode(ARM::SRSIB); |
| 1906 | break; |
| 1907 | case ARM::STMIB_UPD: |
| 1908 | Inst.setOpcode(ARM::SRSIB_UPD); |
| 1909 | break; |
| 1910 | default: |
Amaury de la Vieuville | 68bcd02 | 2013-06-08 13:43:59 +0000 | [diff] [blame] | 1911 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1912 | } |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1913 | |
| 1914 | // For stores (which become SRS's, the only operand is the mode. |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1915 | if (fieldFromInstruction(Insn, 20, 1) == 0) { |
Amaury de la Vieuville | 68bcd02 | 2013-06-08 13:43:59 +0000 | [diff] [blame] | 1916 | // Check SRS encoding constraints |
| 1917 | if (!(fieldFromInstruction(Insn, 22, 1) == 1 && |
| 1918 | fieldFromInstruction(Insn, 20, 1) == 0)) |
| 1919 | return MCDisassembler::Fail; |
| 1920 | |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1921 | Inst.addOperand( |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1922 | MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); |
Owen Anderson | 192a760 | 2011-08-18 22:31:17 +0000 | [diff] [blame] | 1923 | return S; |
| 1924 | } |
| 1925 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1926 | return DecodeRFEInstruction(Inst, Insn, Address, Decoder); |
| 1927 | } |
| 1928 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1929 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1930 | return MCDisassembler::Fail; |
| 1931 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 1932 | return MCDisassembler::Fail; // Tied |
| 1933 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1934 | return MCDisassembler::Fail; |
| 1935 | if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) |
| 1936 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1937 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 1938 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1939 | } |
| 1940 | |
Sjoerd Meijer | d906bf1 | 2016-06-03 14:03:27 +0000 | [diff] [blame] | 1941 | // Check for UNPREDICTABLE predicated ESB instruction |
| 1942 | static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, |
| 1943 | uint64_t Address, const void *Decoder) { |
| 1944 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 1945 | unsigned imm8 = fieldFromInstruction(Insn, 0, 8); |
| 1946 | const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); |
| 1947 | const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); |
| 1948 | |
| 1949 | DecodeStatus S = MCDisassembler::Success; |
| 1950 | |
| 1951 | Inst.addOperand(MCOperand::createImm(imm8)); |
| 1952 | |
| 1953 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 1954 | return MCDisassembler::Fail; |
| 1955 | |
| 1956 | // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, |
| 1957 | // so all predicates should be allowed. |
| 1958 | if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) |
| 1959 | S = MCDisassembler::SoftFail; |
| 1960 | |
| 1961 | return S; |
| 1962 | } |
| 1963 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 1964 | static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1965 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 1966 | unsigned imod = fieldFromInstruction(Insn, 18, 2); |
| 1967 | unsigned M = fieldFromInstruction(Insn, 17, 1); |
| 1968 | unsigned iflags = fieldFromInstruction(Insn, 6, 3); |
| 1969 | unsigned mode = fieldFromInstruction(Insn, 0, 5); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1970 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 1971 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | 3d2e0e9d | 2011-08-09 23:05:39 +0000 | [diff] [blame] | 1972 | |
Amaury de la Vieuville | 631df63 | 2013-06-08 13:38:52 +0000 | [diff] [blame] | 1973 | // This decoder is called from multiple location that do not check |
| 1974 | // the full encoding is valid before they do. |
| 1975 | if (fieldFromInstruction(Insn, 5, 1) != 0 || |
| 1976 | fieldFromInstruction(Insn, 16, 1) != 0 || |
| 1977 | fieldFromInstruction(Insn, 20, 8) != 0x10) |
| 1978 | return MCDisassembler::Fail; |
| 1979 | |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 1980 | // imod == '01' --> UNPREDICTABLE |
| 1981 | // NOTE: Even though this is technically UNPREDICTABLE, we choose to |
| 1982 | // return failure here. The '01' imod value is unprintable, so there's |
| 1983 | // nothing useful we could do even if we returned UNPREDICTABLE. |
| 1984 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1985 | if (imod == 1) return MCDisassembler::Fail; |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 1986 | |
| 1987 | if (imod && M) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1988 | Inst.setOpcode(ARM::CPS3p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1989 | Inst.addOperand(MCOperand::createImm(imod)); |
| 1990 | Inst.addOperand(MCOperand::createImm(iflags)); |
| 1991 | Inst.addOperand(MCOperand::createImm(mode)); |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 1992 | } else if (imod && !M) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1993 | Inst.setOpcode(ARM::CPS2p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1994 | Inst.addOperand(MCOperand::createImm(imod)); |
| 1995 | Inst.addOperand(MCOperand::createImm(iflags)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 1996 | if (mode) S = MCDisassembler::SoftFail; |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 1997 | } else if (!imod && M) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1998 | Inst.setOpcode(ARM::CPS1p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 1999 | Inst.addOperand(MCOperand::createImm(mode)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 2000 | if (iflags) S = MCDisassembler::SoftFail; |
Owen Anderson | 5d2db89 | 2011-08-18 22:15:25 +0000 | [diff] [blame] | 2001 | } else { |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 2002 | // imod == '00' && M == '0' --> UNPREDICTABLE |
Owen Anderson | 5d2db89 | 2011-08-18 22:15:25 +0000 | [diff] [blame] | 2003 | Inst.setOpcode(ARM::CPS1p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2004 | Inst.addOperand(MCOperand::createImm(mode)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 2005 | S = MCDisassembler::SoftFail; |
Owen Anderson | 5d2db89 | 2011-08-18 22:15:25 +0000 | [diff] [blame] | 2006 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2007 | |
Owen Anderson | 67d6f11 | 2011-08-18 22:11:02 +0000 | [diff] [blame] | 2008 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2009 | } |
| 2010 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2011 | static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2012 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2013 | unsigned imod = fieldFromInstruction(Insn, 9, 2); |
| 2014 | unsigned M = fieldFromInstruction(Insn, 8, 1); |
| 2015 | unsigned iflags = fieldFromInstruction(Insn, 5, 3); |
| 2016 | unsigned mode = fieldFromInstruction(Insn, 0, 5); |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2017 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2018 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2019 | |
| 2020 | // imod == '01' --> UNPREDICTABLE |
| 2021 | // NOTE: Even though this is technically UNPREDICTABLE, we choose to |
| 2022 | // return failure here. The '01' imod value is unprintable, so there's |
| 2023 | // nothing useful we could do even if we returned UNPREDICTABLE. |
| 2024 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 2025 | if (imod == 1) return MCDisassembler::Fail; |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2026 | |
| 2027 | if (imod && M) { |
| 2028 | Inst.setOpcode(ARM::t2CPS3p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2029 | Inst.addOperand(MCOperand::createImm(imod)); |
| 2030 | Inst.addOperand(MCOperand::createImm(iflags)); |
| 2031 | Inst.addOperand(MCOperand::createImm(mode)); |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2032 | } else if (imod && !M) { |
| 2033 | Inst.setOpcode(ARM::t2CPS2p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2034 | Inst.addOperand(MCOperand::createImm(imod)); |
| 2035 | Inst.addOperand(MCOperand::createImm(iflags)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 2036 | if (mode) S = MCDisassembler::SoftFail; |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2037 | } else if (!imod && M) { |
| 2038 | Inst.setOpcode(ARM::t2CPS1p); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2039 | Inst.addOperand(MCOperand::createImm(mode)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 2040 | if (iflags) S = MCDisassembler::SoftFail; |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2041 | } else { |
Quentin Colombet | a83d5e9 | 2013-04-26 17:54:54 +0000 | [diff] [blame] | 2042 | // imod == '00' && M == '0' --> this is a HINT instruction |
| 2043 | int imm = fieldFromInstruction(Insn, 0, 8); |
| 2044 | // HINT are defined only for immediate in [0..4] |
| 2045 | if(imm > 4) return MCDisassembler::Fail; |
| 2046 | Inst.setOpcode(ARM::t2HINT); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2047 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2048 | } |
| 2049 | |
| 2050 | return S; |
| 2051 | } |
| 2052 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2053 | static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2054 | uint64_t Address, const void *Decoder) { |
| 2055 | DecodeStatus S = MCDisassembler::Success; |
| 2056 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2057 | unsigned Rd = fieldFromInstruction(Insn, 8, 4); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2058 | unsigned imm = 0; |
| 2059 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2060 | imm |= (fieldFromInstruction(Insn, 0, 8) << 0); |
| 2061 | imm |= (fieldFromInstruction(Insn, 12, 3) << 8); |
| 2062 | imm |= (fieldFromInstruction(Insn, 16, 4) << 12); |
| 2063 | imm |= (fieldFromInstruction(Insn, 26, 1) << 11); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2064 | |
| 2065 | if (Inst.getOpcode() == ARM::t2MOVTi16) |
| 2066 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2067 | return MCDisassembler::Fail; |
| 2068 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2069 | return MCDisassembler::Fail; |
| 2070 | |
| 2071 | if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2072 | Inst.addOperand(MCOperand::createImm(imm)); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2073 | |
| 2074 | return S; |
| 2075 | } |
| 2076 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2077 | static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2078 | uint64_t Address, const void *Decoder) { |
| 2079 | DecodeStatus S = MCDisassembler::Success; |
| 2080 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2081 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 2082 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2083 | unsigned imm = 0; |
| 2084 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2085 | imm |= (fieldFromInstruction(Insn, 0, 12) << 0); |
| 2086 | imm |= (fieldFromInstruction(Insn, 16, 4) << 12); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2087 | |
| 2088 | if (Inst.getOpcode() == ARM::MOVTi16) |
Tim Northover | a155ab2 | 2013-04-19 09:58:09 +0000 | [diff] [blame] | 2089 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2090 | return MCDisassembler::Fail; |
Tim Northover | a155ab2 | 2013-04-19 09:58:09 +0000 | [diff] [blame] | 2091 | |
| 2092 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2093 | return MCDisassembler::Fail; |
| 2094 | |
| 2095 | if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2096 | Inst.addOperand(MCOperand::createImm(imm)); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2097 | |
| 2098 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 2099 | return MCDisassembler::Fail; |
| 2100 | |
| 2101 | return S; |
| 2102 | } |
Owen Anderson | 9b7bd15 | 2011-08-23 17:45:18 +0000 | [diff] [blame] | 2103 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2104 | static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2105 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2106 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2107 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2108 | unsigned Rd = fieldFromInstruction(Insn, 16, 4); |
| 2109 | unsigned Rn = fieldFromInstruction(Insn, 0, 4); |
| 2110 | unsigned Rm = fieldFromInstruction(Insn, 8, 4); |
| 2111 | unsigned Ra = fieldFromInstruction(Insn, 12, 4); |
| 2112 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2113 | |
| 2114 | if (pred == 0xF) |
| 2115 | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
| 2116 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2117 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
| 2118 | return MCDisassembler::Fail; |
| 2119 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
| 2120 | return MCDisassembler::Fail; |
| 2121 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
| 2122 | return MCDisassembler::Fail; |
| 2123 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) |
| 2124 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2125 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2126 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 2127 | return MCDisassembler::Fail; |
Owen Anderson | 2f7aa73 | 2011-08-11 22:05:38 +0000 | [diff] [blame] | 2128 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2129 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2130 | } |
| 2131 | |
Vladimir Sukharev | 0e0f8d2 | 2015-04-16 11:34:25 +0000 | [diff] [blame] | 2132 | static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, |
| 2133 | uint64_t Address, const void *Decoder) { |
| 2134 | DecodeStatus S = MCDisassembler::Success; |
| 2135 | |
| 2136 | unsigned Pred = fieldFromInstruction(Insn, 28, 4); |
| 2137 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 2138 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 2139 | |
| 2140 | if (Pred == 0xF) |
| 2141 | return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); |
| 2142 | |
| 2143 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2144 | return MCDisassembler::Fail; |
| 2145 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 2146 | return MCDisassembler::Fail; |
| 2147 | if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) |
| 2148 | return MCDisassembler::Fail; |
| 2149 | |
| 2150 | return S; |
| 2151 | } |
| 2152 | |
| 2153 | static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, |
| 2154 | uint64_t Address, const void *Decoder) { |
| 2155 | DecodeStatus S = MCDisassembler::Success; |
| 2156 | |
| 2157 | unsigned Imm = fieldFromInstruction(Insn, 9, 1); |
| 2158 | |
| 2159 | const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 2160 | const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); |
| 2161 | |
| 2162 | if (!FeatureBits[ARM::HasV8_1aOps] || |
| 2163 | !FeatureBits[ARM::HasV8Ops]) |
Vladimir Sukharev | 0e0f8d2 | 2015-04-16 11:34:25 +0000 | [diff] [blame] | 2164 | return MCDisassembler::Fail; |
| 2165 | |
| 2166 | // Decoder can be called from DecodeTST, which does not check the full |
| 2167 | // encoding is valid. |
| 2168 | if (fieldFromInstruction(Insn, 20,12) != 0xf11 || |
| 2169 | fieldFromInstruction(Insn, 4,4) != 0) |
| 2170 | return MCDisassembler::Fail; |
| 2171 | if (fieldFromInstruction(Insn, 10,10) != 0 || |
| 2172 | fieldFromInstruction(Insn, 0,4) != 0) |
| 2173 | S = MCDisassembler::SoftFail; |
| 2174 | |
| 2175 | Inst.setOpcode(ARM::SETPAN); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2176 | Inst.addOperand(MCOperand::createImm(Imm)); |
Vladimir Sukharev | 0e0f8d2 | 2015-04-16 11:34:25 +0000 | [diff] [blame] | 2177 | |
| 2178 | return S; |
| 2179 | } |
| 2180 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2181 | static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2182 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2183 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2184 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2185 | unsigned add = fieldFromInstruction(Val, 12, 1); |
| 2186 | unsigned imm = fieldFromInstruction(Val, 0, 12); |
| 2187 | unsigned Rn = fieldFromInstruction(Val, 13, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2188 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2189 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2190 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2191 | |
| 2192 | if (!add) imm *= -1; |
| 2193 | if (imm == 0 && !add) imm = INT32_MIN; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2194 | Inst.addOperand(MCOperand::createImm(imm)); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 2195 | if (Rn == 15) |
| 2196 | tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2197 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2198 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2199 | } |
| 2200 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2201 | static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2202 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2203 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2204 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2205 | unsigned Rn = fieldFromInstruction(Val, 9, 4); |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 2206 | // U == 1 to add imm, 0 to subtract it. |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2207 | unsigned U = fieldFromInstruction(Val, 8, 1); |
| 2208 | unsigned imm = fieldFromInstruction(Val, 0, 8); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2209 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2210 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2211 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2212 | |
| 2213 | if (U) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2214 | Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2215 | else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2216 | Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2217 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2218 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2219 | } |
| 2220 | |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 2221 | static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, |
| 2222 | uint64_t Address, const void *Decoder) { |
| 2223 | DecodeStatus S = MCDisassembler::Success; |
| 2224 | |
| 2225 | unsigned Rn = fieldFromInstruction(Val, 9, 4); |
| 2226 | // U == 1 to add imm, 0 to subtract it. |
| 2227 | unsigned U = fieldFromInstruction(Val, 8, 1); |
| 2228 | unsigned imm = fieldFromInstruction(Val, 0, 8); |
| 2229 | |
| 2230 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2231 | return MCDisassembler::Fail; |
| 2232 | |
| 2233 | if (U) |
| 2234 | Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); |
| 2235 | else |
| 2236 | Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); |
| 2237 | |
| 2238 | return S; |
| 2239 | } |
| 2240 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2241 | static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2242 | uint64_t Address, const void *Decoder) { |
| 2243 | return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); |
| 2244 | } |
| 2245 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2246 | static DecodeStatus |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 2247 | DecodeT2BInstruction(MCInst &Inst, unsigned Insn, |
| 2248 | uint64_t Address, const void *Decoder) { |
Kevin Enderby | 6fd9624 | 2012-10-29 23:27:20 +0000 | [diff] [blame] | 2249 | DecodeStatus Status = MCDisassembler::Success; |
| 2250 | |
| 2251 | // Note the J1 and J2 values are from the encoded instruction. So here |
| 2252 | // change them to I1 and I2 values via as documented: |
| 2253 | // I1 = NOT(J1 EOR S); |
| 2254 | // I2 = NOT(J2 EOR S); |
| 2255 | // and build the imm32 with one trailing zero as documented: |
| 2256 | // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); |
| 2257 | unsigned S = fieldFromInstruction(Insn, 26, 1); |
| 2258 | unsigned J1 = fieldFromInstruction(Insn, 13, 1); |
| 2259 | unsigned J2 = fieldFromInstruction(Insn, 11, 1); |
| 2260 | unsigned I1 = !(J1 ^ S); |
| 2261 | unsigned I2 = !(J2 ^ S); |
| 2262 | unsigned imm10 = fieldFromInstruction(Insn, 16, 10); |
| 2263 | unsigned imm11 = fieldFromInstruction(Insn, 0, 11); |
| 2264 | unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; |
Amaury de la Vieuville | bd2b610 | 2013-06-13 16:41:55 +0000 | [diff] [blame] | 2265 | int imm32 = SignExtend32<25>(tmp << 1); |
Kevin Enderby | 6fd9624 | 2012-10-29 23:27:20 +0000 | [diff] [blame] | 2266 | if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 2267 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2268 | Inst.addOperand(MCOperand::createImm(imm32)); |
Kevin Enderby | 6fd9624 | 2012-10-29 23:27:20 +0000 | [diff] [blame] | 2269 | |
| 2270 | return Status; |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 2271 | } |
| 2272 | |
| 2273 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2274 | DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 2275 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2276 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2277 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2278 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 2279 | unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2280 | |
| 2281 | if (pred == 0xF) { |
| 2282 | Inst.setOpcode(ARM::BLXi); |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2283 | imm |= fieldFromInstruction(Insn, 24, 1) << 1; |
Kevin Enderby | 6fbcd8d | 2012-02-23 18:18:17 +0000 | [diff] [blame] | 2284 | if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, |
| 2285 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2286 | Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2287 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2288 | } |
| 2289 | |
Kevin Enderby | 6fbcd8d | 2012-02-23 18:18:17 +0000 | [diff] [blame] | 2290 | if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, |
| 2291 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2292 | Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2293 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 2294 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2295 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2296 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2297 | } |
| 2298 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2299 | static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2300 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2301 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2302 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2303 | unsigned Rm = fieldFromInstruction(Val, 0, 4); |
| 2304 | unsigned align = fieldFromInstruction(Val, 4, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2305 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2306 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 2307 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2308 | if (!align) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2309 | Inst.addOperand(MCOperand::createImm(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2310 | else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2311 | Inst.addOperand(MCOperand::createImm(4 << align)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2312 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2313 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2314 | } |
| 2315 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2316 | static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2317 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2318 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2319 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2320 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 2321 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 2322 | unsigned wb = fieldFromInstruction(Insn, 16, 4); |
| 2323 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 2324 | Rn |= fieldFromInstruction(Insn, 4, 2) << 4; |
| 2325 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2326 | |
| 2327 | // First output register |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 2328 | switch (Inst.getOpcode()) { |
Jim Grosbach | 13a292c | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 2329 | case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: |
| 2330 | case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: |
| 2331 | case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: |
| 2332 | case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: |
| 2333 | case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: |
| 2334 | case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: |
| 2335 | case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: |
| 2336 | case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: |
| 2337 | case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 2338 | if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
| 2339 | return MCDisassembler::Fail; |
| 2340 | break; |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 2341 | case ARM::VLD2b16: |
| 2342 | case ARM::VLD2b32: |
| 2343 | case ARM::VLD2b8: |
| 2344 | case ARM::VLD2b16wb_fixed: |
| 2345 | case ARM::VLD2b16wb_register: |
| 2346 | case ARM::VLD2b32wb_fixed: |
| 2347 | case ARM::VLD2b32wb_register: |
| 2348 | case ARM::VLD2b8wb_fixed: |
| 2349 | case ARM::VLD2b8wb_register: |
| 2350 | if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
| 2351 | return MCDisassembler::Fail; |
| 2352 | break; |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 2353 | default: |
| 2354 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2355 | return MCDisassembler::Fail; |
| 2356 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2357 | |
| 2358 | // Second output register |
| 2359 | switch (Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2360 | case ARM::VLD3d8: |
| 2361 | case ARM::VLD3d16: |
| 2362 | case ARM::VLD3d32: |
| 2363 | case ARM::VLD3d8_UPD: |
| 2364 | case ARM::VLD3d16_UPD: |
| 2365 | case ARM::VLD3d32_UPD: |
| 2366 | case ARM::VLD4d8: |
| 2367 | case ARM::VLD4d16: |
| 2368 | case ARM::VLD4d32: |
| 2369 | case ARM::VLD4d8_UPD: |
| 2370 | case ARM::VLD4d16_UPD: |
| 2371 | case ARM::VLD4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2372 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) |
| 2373 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2374 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2375 | case ARM::VLD3q8: |
| 2376 | case ARM::VLD3q16: |
| 2377 | case ARM::VLD3q32: |
| 2378 | case ARM::VLD3q8_UPD: |
| 2379 | case ARM::VLD3q16_UPD: |
| 2380 | case ARM::VLD3q32_UPD: |
| 2381 | case ARM::VLD4q8: |
| 2382 | case ARM::VLD4q16: |
| 2383 | case ARM::VLD4q32: |
| 2384 | case ARM::VLD4q8_UPD: |
| 2385 | case ARM::VLD4q16_UPD: |
| 2386 | case ARM::VLD4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2387 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) |
| 2388 | return MCDisassembler::Fail; |
Adrian Prantl | 0e6694d | 2017-12-19 22:05:25 +0000 | [diff] [blame^] | 2389 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2390 | default: |
| 2391 | break; |
| 2392 | } |
| 2393 | |
| 2394 | // Third output register |
| 2395 | switch(Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2396 | case ARM::VLD3d8: |
| 2397 | case ARM::VLD3d16: |
| 2398 | case ARM::VLD3d32: |
| 2399 | case ARM::VLD3d8_UPD: |
| 2400 | case ARM::VLD3d16_UPD: |
| 2401 | case ARM::VLD3d32_UPD: |
| 2402 | case ARM::VLD4d8: |
| 2403 | case ARM::VLD4d16: |
| 2404 | case ARM::VLD4d32: |
| 2405 | case ARM::VLD4d8_UPD: |
| 2406 | case ARM::VLD4d16_UPD: |
| 2407 | case ARM::VLD4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2408 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) |
| 2409 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2410 | break; |
| 2411 | case ARM::VLD3q8: |
| 2412 | case ARM::VLD3q16: |
| 2413 | case ARM::VLD3q32: |
| 2414 | case ARM::VLD3q8_UPD: |
| 2415 | case ARM::VLD3q16_UPD: |
| 2416 | case ARM::VLD3q32_UPD: |
| 2417 | case ARM::VLD4q8: |
| 2418 | case ARM::VLD4q16: |
| 2419 | case ARM::VLD4q32: |
| 2420 | case ARM::VLD4q8_UPD: |
| 2421 | case ARM::VLD4q16_UPD: |
| 2422 | case ARM::VLD4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2423 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) |
| 2424 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2425 | break; |
| 2426 | default: |
| 2427 | break; |
| 2428 | } |
| 2429 | |
| 2430 | // Fourth output register |
| 2431 | switch (Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2432 | case ARM::VLD4d8: |
| 2433 | case ARM::VLD4d16: |
| 2434 | case ARM::VLD4d32: |
| 2435 | case ARM::VLD4d8_UPD: |
| 2436 | case ARM::VLD4d16_UPD: |
| 2437 | case ARM::VLD4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2438 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) |
| 2439 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2440 | break; |
| 2441 | case ARM::VLD4q8: |
| 2442 | case ARM::VLD4q16: |
| 2443 | case ARM::VLD4q32: |
| 2444 | case ARM::VLD4q8_UPD: |
| 2445 | case ARM::VLD4q16_UPD: |
| 2446 | case ARM::VLD4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2447 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) |
| 2448 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2449 | break; |
| 2450 | default: |
| 2451 | break; |
| 2452 | } |
| 2453 | |
| 2454 | // Writeback operand |
| 2455 | switch (Inst.getOpcode()) { |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2456 | case ARM::VLD1d8wb_fixed: |
| 2457 | case ARM::VLD1d16wb_fixed: |
| 2458 | case ARM::VLD1d32wb_fixed: |
| 2459 | case ARM::VLD1d64wb_fixed: |
| 2460 | case ARM::VLD1d8wb_register: |
| 2461 | case ARM::VLD1d16wb_register: |
| 2462 | case ARM::VLD1d32wb_register: |
| 2463 | case ARM::VLD1d64wb_register: |
| 2464 | case ARM::VLD1q8wb_fixed: |
| 2465 | case ARM::VLD1q16wb_fixed: |
| 2466 | case ARM::VLD1q32wb_fixed: |
| 2467 | case ARM::VLD1q64wb_fixed: |
| 2468 | case ARM::VLD1q8wb_register: |
| 2469 | case ARM::VLD1q16wb_register: |
| 2470 | case ARM::VLD1q32wb_register: |
| 2471 | case ARM::VLD1q64wb_register: |
Jim Grosbach | 92fd05e | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 2472 | case ARM::VLD1d8Twb_fixed: |
| 2473 | case ARM::VLD1d8Twb_register: |
| 2474 | case ARM::VLD1d16Twb_fixed: |
| 2475 | case ARM::VLD1d16Twb_register: |
| 2476 | case ARM::VLD1d32Twb_fixed: |
| 2477 | case ARM::VLD1d32Twb_register: |
| 2478 | case ARM::VLD1d64Twb_fixed: |
| 2479 | case ARM::VLD1d64Twb_register: |
Jim Grosbach | 17ec1a1 | 2011-10-25 00:14:01 +0000 | [diff] [blame] | 2480 | case ARM::VLD1d8Qwb_fixed: |
| 2481 | case ARM::VLD1d8Qwb_register: |
| 2482 | case ARM::VLD1d16Qwb_fixed: |
| 2483 | case ARM::VLD1d16Qwb_register: |
| 2484 | case ARM::VLD1d32Qwb_fixed: |
| 2485 | case ARM::VLD1d32Qwb_register: |
| 2486 | case ARM::VLD1d64Qwb_fixed: |
| 2487 | case ARM::VLD1d64Qwb_register: |
Jim Grosbach | d146a02 | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 2488 | case ARM::VLD2d8wb_fixed: |
| 2489 | case ARM::VLD2d16wb_fixed: |
| 2490 | case ARM::VLD2d32wb_fixed: |
| 2491 | case ARM::VLD2q8wb_fixed: |
| 2492 | case ARM::VLD2q16wb_fixed: |
| 2493 | case ARM::VLD2q32wb_fixed: |
| 2494 | case ARM::VLD2d8wb_register: |
| 2495 | case ARM::VLD2d16wb_register: |
| 2496 | case ARM::VLD2d32wb_register: |
| 2497 | case ARM::VLD2q8wb_register: |
| 2498 | case ARM::VLD2q16wb_register: |
| 2499 | case ARM::VLD2q32wb_register: |
| 2500 | case ARM::VLD2b8wb_fixed: |
| 2501 | case ARM::VLD2b16wb_fixed: |
| 2502 | case ARM::VLD2b32wb_fixed: |
| 2503 | case ARM::VLD2b8wb_register: |
| 2504 | case ARM::VLD2b16wb_register: |
| 2505 | case ARM::VLD2b32wb_register: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2506 | Inst.addOperand(MCOperand::createImm(0)); |
Kevin Enderby | d2980cd | 2012-04-11 00:25:40 +0000 | [diff] [blame] | 2507 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2508 | case ARM::VLD3d8_UPD: |
| 2509 | case ARM::VLD3d16_UPD: |
| 2510 | case ARM::VLD3d32_UPD: |
| 2511 | case ARM::VLD3q8_UPD: |
| 2512 | case ARM::VLD3q16_UPD: |
| 2513 | case ARM::VLD3q32_UPD: |
| 2514 | case ARM::VLD4d8_UPD: |
| 2515 | case ARM::VLD4d16_UPD: |
| 2516 | case ARM::VLD4d32_UPD: |
| 2517 | case ARM::VLD4q8_UPD: |
| 2518 | case ARM::VLD4q16_UPD: |
| 2519 | case ARM::VLD4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2520 | if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) |
| 2521 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2522 | break; |
| 2523 | default: |
| 2524 | break; |
| 2525 | } |
| 2526 | |
| 2527 | // AddrMode6 Base (register+alignment) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2528 | if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) |
| 2529 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2530 | |
| 2531 | // AddrMode6 Offset (register) |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2532 | switch (Inst.getOpcode()) { |
| 2533 | default: |
| 2534 | // The below have been updated to have explicit am6offset split |
| 2535 | // between fixed and register offset. For those instructions not |
| 2536 | // yet updated, we need to add an additional reg0 operand for the |
| 2537 | // fixed variant. |
| 2538 | // |
| 2539 | // The fixed offset encodes as Rm == 0xd, so we check for that. |
| 2540 | if (Rm == 0xd) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2541 | Inst.addOperand(MCOperand::createReg(0)); |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2542 | break; |
| 2543 | } |
| 2544 | // Fall through to handle the register offset variant. |
Justin Bogner | cd1d5aa | 2016-08-17 20:30:52 +0000 | [diff] [blame] | 2545 | LLVM_FALLTHROUGH; |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2546 | case ARM::VLD1d8wb_fixed: |
| 2547 | case ARM::VLD1d16wb_fixed: |
| 2548 | case ARM::VLD1d32wb_fixed: |
| 2549 | case ARM::VLD1d64wb_fixed: |
Owen Anderson | 8a6ebd0 | 2011-10-27 22:53:10 +0000 | [diff] [blame] | 2550 | case ARM::VLD1d8Twb_fixed: |
| 2551 | case ARM::VLD1d16Twb_fixed: |
| 2552 | case ARM::VLD1d32Twb_fixed: |
| 2553 | case ARM::VLD1d64Twb_fixed: |
Owen Anderson | 40703f4 | 2011-10-31 17:17:32 +0000 | [diff] [blame] | 2554 | case ARM::VLD1d8Qwb_fixed: |
| 2555 | case ARM::VLD1d16Qwb_fixed: |
| 2556 | case ARM::VLD1d32Qwb_fixed: |
| 2557 | case ARM::VLD1d64Qwb_fixed: |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2558 | case ARM::VLD1d8wb_register: |
| 2559 | case ARM::VLD1d16wb_register: |
| 2560 | case ARM::VLD1d32wb_register: |
| 2561 | case ARM::VLD1d64wb_register: |
| 2562 | case ARM::VLD1q8wb_fixed: |
| 2563 | case ARM::VLD1q16wb_fixed: |
| 2564 | case ARM::VLD1q32wb_fixed: |
| 2565 | case ARM::VLD1q64wb_fixed: |
| 2566 | case ARM::VLD1q8wb_register: |
| 2567 | case ARM::VLD1q16wb_register: |
| 2568 | case ARM::VLD1q32wb_register: |
| 2569 | case ARM::VLD1q64wb_register: |
| 2570 | // The fixed offset post-increment encodes Rm == 0xd. The no-writeback |
| 2571 | // variant encodes Rm == 0xf. Anything else is a register offset post- |
| 2572 | // increment and we need to add the register operand to the instruction. |
| 2573 | if (Rm != 0xD && Rm != 0xF && |
| 2574 | !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2575 | return MCDisassembler::Fail; |
Jim Grosbach | 2098cb1 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 2576 | break; |
Kevin Enderby | d2980cd | 2012-04-11 00:25:40 +0000 | [diff] [blame] | 2577 | case ARM::VLD2d8wb_fixed: |
| 2578 | case ARM::VLD2d16wb_fixed: |
| 2579 | case ARM::VLD2d32wb_fixed: |
| 2580 | case ARM::VLD2b8wb_fixed: |
| 2581 | case ARM::VLD2b16wb_fixed: |
| 2582 | case ARM::VLD2b32wb_fixed: |
| 2583 | case ARM::VLD2q8wb_fixed: |
| 2584 | case ARM::VLD2q16wb_fixed: |
| 2585 | case ARM::VLD2q32wb_fixed: |
| 2586 | break; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 2587 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2588 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2589 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2590 | } |
| 2591 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2592 | static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, |
| 2593 | uint64_t Address, const void *Decoder) { |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2594 | unsigned type = fieldFromInstruction(Insn, 8, 4); |
| 2595 | unsigned align = fieldFromInstruction(Insn, 4, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2596 | if (type == 6 && (align & 2)) return MCDisassembler::Fail; |
| 2597 | if (type == 7 && (align & 2)) return MCDisassembler::Fail; |
| 2598 | if (type == 10 && align == 3) return MCDisassembler::Fail; |
| 2599 | |
| 2600 | unsigned load = fieldFromInstruction(Insn, 21, 1); |
| 2601 | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
| 2602 | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2603 | } |
| 2604 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2605 | static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, |
| 2606 | uint64_t Address, const void *Decoder) { |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2607 | unsigned size = fieldFromInstruction(Insn, 6, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2608 | if (size == 3) return MCDisassembler::Fail; |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2609 | |
| 2610 | unsigned type = fieldFromInstruction(Insn, 8, 4); |
| 2611 | unsigned align = fieldFromInstruction(Insn, 4, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2612 | if (type == 8 && align == 3) return MCDisassembler::Fail; |
| 2613 | if (type == 9 && align == 3) return MCDisassembler::Fail; |
| 2614 | |
| 2615 | unsigned load = fieldFromInstruction(Insn, 21, 1); |
| 2616 | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
| 2617 | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2618 | } |
| 2619 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2620 | static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, |
| 2621 | uint64_t Address, const void *Decoder) { |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2622 | unsigned size = fieldFromInstruction(Insn, 6, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2623 | if (size == 3) return MCDisassembler::Fail; |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2624 | |
| 2625 | unsigned align = fieldFromInstruction(Insn, 4, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2626 | if (align & 2) return MCDisassembler::Fail; |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2627 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2628 | unsigned load = fieldFromInstruction(Insn, 21, 1); |
| 2629 | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
| 2630 | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2631 | } |
| 2632 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2633 | static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, |
| 2634 | uint64_t Address, const void *Decoder) { |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2635 | unsigned size = fieldFromInstruction(Insn, 6, 2); |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2636 | if (size == 3) return MCDisassembler::Fail; |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2637 | |
Amaury de la Vieuville | 064546c | 2013-06-11 08:14:14 +0000 | [diff] [blame] | 2638 | unsigned load = fieldFromInstruction(Insn, 21, 1); |
| 2639 | return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) |
| 2640 | : DecodeVSTInstruction(Inst, Insn, Address, Decoder); |
Mihai Popa | f41e3f5 | 2013-05-20 14:57:05 +0000 | [diff] [blame] | 2641 | } |
| 2642 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2643 | static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2644 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2645 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2646 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2647 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 2648 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 2649 | unsigned wb = fieldFromInstruction(Insn, 16, 4); |
| 2650 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 2651 | Rn |= fieldFromInstruction(Insn, 4, 2) << 4; |
| 2652 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2653 | |
| 2654 | // Writeback Operand |
| 2655 | switch (Inst.getOpcode()) { |
Jim Grosbach | 05df460 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 2656 | case ARM::VST1d8wb_fixed: |
| 2657 | case ARM::VST1d16wb_fixed: |
| 2658 | case ARM::VST1d32wb_fixed: |
| 2659 | case ARM::VST1d64wb_fixed: |
| 2660 | case ARM::VST1d8wb_register: |
| 2661 | case ARM::VST1d16wb_register: |
| 2662 | case ARM::VST1d32wb_register: |
| 2663 | case ARM::VST1d64wb_register: |
| 2664 | case ARM::VST1q8wb_fixed: |
| 2665 | case ARM::VST1q16wb_fixed: |
| 2666 | case ARM::VST1q32wb_fixed: |
| 2667 | case ARM::VST1q64wb_fixed: |
| 2668 | case ARM::VST1q8wb_register: |
| 2669 | case ARM::VST1q16wb_register: |
| 2670 | case ARM::VST1q32wb_register: |
| 2671 | case ARM::VST1q64wb_register: |
Jim Grosbach | 98d032f | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 2672 | case ARM::VST1d8Twb_fixed: |
| 2673 | case ARM::VST1d16Twb_fixed: |
| 2674 | case ARM::VST1d32Twb_fixed: |
| 2675 | case ARM::VST1d64Twb_fixed: |
| 2676 | case ARM::VST1d8Twb_register: |
| 2677 | case ARM::VST1d16Twb_register: |
| 2678 | case ARM::VST1d32Twb_register: |
| 2679 | case ARM::VST1d64Twb_register: |
Jim Grosbach | 5ee209c | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 2680 | case ARM::VST1d8Qwb_fixed: |
| 2681 | case ARM::VST1d16Qwb_fixed: |
| 2682 | case ARM::VST1d32Qwb_fixed: |
| 2683 | case ARM::VST1d64Qwb_fixed: |
| 2684 | case ARM::VST1d8Qwb_register: |
| 2685 | case ARM::VST1d16Qwb_register: |
| 2686 | case ARM::VST1d32Qwb_register: |
| 2687 | case ARM::VST1d64Qwb_register: |
Jim Grosbach | 88ac761 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 2688 | case ARM::VST2d8wb_fixed: |
| 2689 | case ARM::VST2d16wb_fixed: |
| 2690 | case ARM::VST2d32wb_fixed: |
| 2691 | case ARM::VST2d8wb_register: |
| 2692 | case ARM::VST2d16wb_register: |
| 2693 | case ARM::VST2d32wb_register: |
| 2694 | case ARM::VST2q8wb_fixed: |
| 2695 | case ARM::VST2q16wb_fixed: |
| 2696 | case ARM::VST2q32wb_fixed: |
| 2697 | case ARM::VST2q8wb_register: |
| 2698 | case ARM::VST2q16wb_register: |
| 2699 | case ARM::VST2q32wb_register: |
| 2700 | case ARM::VST2b8wb_fixed: |
| 2701 | case ARM::VST2b16wb_fixed: |
| 2702 | case ARM::VST2b32wb_fixed: |
| 2703 | case ARM::VST2b8wb_register: |
| 2704 | case ARM::VST2b16wb_register: |
| 2705 | case ARM::VST2b32wb_register: |
Kevin Enderby | 72f18bb | 2012-04-11 22:40:17 +0000 | [diff] [blame] | 2706 | if (Rm == 0xF) |
| 2707 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2708 | Inst.addOperand(MCOperand::createImm(0)); |
Kevin Enderby | 7e7d5ee | 2012-03-21 20:54:32 +0000 | [diff] [blame] | 2709 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2710 | case ARM::VST3d8_UPD: |
| 2711 | case ARM::VST3d16_UPD: |
| 2712 | case ARM::VST3d32_UPD: |
| 2713 | case ARM::VST3q8_UPD: |
| 2714 | case ARM::VST3q16_UPD: |
| 2715 | case ARM::VST3q32_UPD: |
| 2716 | case ARM::VST4d8_UPD: |
| 2717 | case ARM::VST4d16_UPD: |
| 2718 | case ARM::VST4d32_UPD: |
| 2719 | case ARM::VST4q8_UPD: |
| 2720 | case ARM::VST4q16_UPD: |
| 2721 | case ARM::VST4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2722 | if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) |
| 2723 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2724 | break; |
| 2725 | default: |
| 2726 | break; |
| 2727 | } |
| 2728 | |
| 2729 | // AddrMode6 Base (register+alignment) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2730 | if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) |
| 2731 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2732 | |
| 2733 | // AddrMode6 Offset (register) |
Owen Anderson | 69e54a7 | 2011-11-01 22:18:13 +0000 | [diff] [blame] | 2734 | switch (Inst.getOpcode()) { |
| 2735 | default: |
| 2736 | if (Rm == 0xD) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2737 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | 69e54a7 | 2011-11-01 22:18:13 +0000 | [diff] [blame] | 2738 | else if (Rm != 0xF) { |
| 2739 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 2740 | return MCDisassembler::Fail; |
| 2741 | } |
| 2742 | break; |
| 2743 | case ARM::VST1d8wb_fixed: |
| 2744 | case ARM::VST1d16wb_fixed: |
| 2745 | case ARM::VST1d32wb_fixed: |
| 2746 | case ARM::VST1d64wb_fixed: |
| 2747 | case ARM::VST1q8wb_fixed: |
| 2748 | case ARM::VST1q16wb_fixed: |
| 2749 | case ARM::VST1q32wb_fixed: |
| 2750 | case ARM::VST1q64wb_fixed: |
Kevin Enderby | 7e7d5ee | 2012-03-21 20:54:32 +0000 | [diff] [blame] | 2751 | case ARM::VST1d8Twb_fixed: |
| 2752 | case ARM::VST1d16Twb_fixed: |
| 2753 | case ARM::VST1d32Twb_fixed: |
| 2754 | case ARM::VST1d64Twb_fixed: |
| 2755 | case ARM::VST1d8Qwb_fixed: |
| 2756 | case ARM::VST1d16Qwb_fixed: |
| 2757 | case ARM::VST1d32Qwb_fixed: |
| 2758 | case ARM::VST1d64Qwb_fixed: |
| 2759 | case ARM::VST2d8wb_fixed: |
| 2760 | case ARM::VST2d16wb_fixed: |
| 2761 | case ARM::VST2d32wb_fixed: |
| 2762 | case ARM::VST2q8wb_fixed: |
| 2763 | case ARM::VST2q16wb_fixed: |
| 2764 | case ARM::VST2q32wb_fixed: |
| 2765 | case ARM::VST2b8wb_fixed: |
| 2766 | case ARM::VST2b16wb_fixed: |
| 2767 | case ARM::VST2b32wb_fixed: |
Owen Anderson | 69e54a7 | 2011-11-01 22:18:13 +0000 | [diff] [blame] | 2768 | break; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 2769 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2770 | |
| 2771 | // First input register |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 2772 | switch (Inst.getOpcode()) { |
| 2773 | case ARM::VST1q16: |
| 2774 | case ARM::VST1q32: |
| 2775 | case ARM::VST1q64: |
| 2776 | case ARM::VST1q8: |
| 2777 | case ARM::VST1q16wb_fixed: |
| 2778 | case ARM::VST1q16wb_register: |
| 2779 | case ARM::VST1q32wb_fixed: |
| 2780 | case ARM::VST1q32wb_register: |
| 2781 | case ARM::VST1q64wb_fixed: |
| 2782 | case ARM::VST1q64wb_register: |
| 2783 | case ARM::VST1q8wb_fixed: |
| 2784 | case ARM::VST1q8wb_register: |
| 2785 | case ARM::VST2d16: |
| 2786 | case ARM::VST2d32: |
| 2787 | case ARM::VST2d8: |
| 2788 | case ARM::VST2d16wb_fixed: |
| 2789 | case ARM::VST2d16wb_register: |
| 2790 | case ARM::VST2d32wb_fixed: |
| 2791 | case ARM::VST2d32wb_register: |
| 2792 | case ARM::VST2d8wb_fixed: |
| 2793 | case ARM::VST2d8wb_register: |
| 2794 | if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
| 2795 | return MCDisassembler::Fail; |
| 2796 | break; |
Jim Grosbach | e5307f9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 2797 | case ARM::VST2b16: |
| 2798 | case ARM::VST2b32: |
| 2799 | case ARM::VST2b8: |
| 2800 | case ARM::VST2b16wb_fixed: |
| 2801 | case ARM::VST2b16wb_register: |
| 2802 | case ARM::VST2b32wb_fixed: |
| 2803 | case ARM::VST2b32wb_register: |
| 2804 | case ARM::VST2b8wb_fixed: |
| 2805 | case ARM::VST2b8wb_register: |
| 2806 | if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
| 2807 | return MCDisassembler::Fail; |
| 2808 | break; |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 2809 | default: |
| 2810 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2811 | return MCDisassembler::Fail; |
| 2812 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2813 | |
| 2814 | // Second input register |
| 2815 | switch (Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2816 | case ARM::VST3d8: |
| 2817 | case ARM::VST3d16: |
| 2818 | case ARM::VST3d32: |
| 2819 | case ARM::VST3d8_UPD: |
| 2820 | case ARM::VST3d16_UPD: |
| 2821 | case ARM::VST3d32_UPD: |
| 2822 | case ARM::VST4d8: |
| 2823 | case ARM::VST4d16: |
| 2824 | case ARM::VST4d32: |
| 2825 | case ARM::VST4d8_UPD: |
| 2826 | case ARM::VST4d16_UPD: |
| 2827 | case ARM::VST4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2828 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) |
| 2829 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2830 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2831 | case ARM::VST3q8: |
| 2832 | case ARM::VST3q16: |
| 2833 | case ARM::VST3q32: |
| 2834 | case ARM::VST3q8_UPD: |
| 2835 | case ARM::VST3q16_UPD: |
| 2836 | case ARM::VST3q32_UPD: |
| 2837 | case ARM::VST4q8: |
| 2838 | case ARM::VST4q16: |
| 2839 | case ARM::VST4q32: |
| 2840 | case ARM::VST4q8_UPD: |
| 2841 | case ARM::VST4q16_UPD: |
| 2842 | case ARM::VST4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2843 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) |
| 2844 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2845 | break; |
| 2846 | default: |
| 2847 | break; |
| 2848 | } |
| 2849 | |
| 2850 | // Third input register |
| 2851 | switch (Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2852 | case ARM::VST3d8: |
| 2853 | case ARM::VST3d16: |
| 2854 | case ARM::VST3d32: |
| 2855 | case ARM::VST3d8_UPD: |
| 2856 | case ARM::VST3d16_UPD: |
| 2857 | case ARM::VST3d32_UPD: |
| 2858 | case ARM::VST4d8: |
| 2859 | case ARM::VST4d16: |
| 2860 | case ARM::VST4d32: |
| 2861 | case ARM::VST4d8_UPD: |
| 2862 | case ARM::VST4d16_UPD: |
| 2863 | case ARM::VST4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2864 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) |
| 2865 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2866 | break; |
| 2867 | case ARM::VST3q8: |
| 2868 | case ARM::VST3q16: |
| 2869 | case ARM::VST3q32: |
| 2870 | case ARM::VST3q8_UPD: |
| 2871 | case ARM::VST3q16_UPD: |
| 2872 | case ARM::VST3q32_UPD: |
| 2873 | case ARM::VST4q8: |
| 2874 | case ARM::VST4q16: |
| 2875 | case ARM::VST4q32: |
| 2876 | case ARM::VST4q8_UPD: |
| 2877 | case ARM::VST4q16_UPD: |
| 2878 | case ARM::VST4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2879 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) |
| 2880 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2881 | break; |
| 2882 | default: |
| 2883 | break; |
| 2884 | } |
| 2885 | |
| 2886 | // Fourth input register |
| 2887 | switch (Inst.getOpcode()) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2888 | case ARM::VST4d8: |
| 2889 | case ARM::VST4d16: |
| 2890 | case ARM::VST4d32: |
| 2891 | case ARM::VST4d8_UPD: |
| 2892 | case ARM::VST4d16_UPD: |
| 2893 | case ARM::VST4d32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2894 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) |
| 2895 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2896 | break; |
| 2897 | case ARM::VST4q8: |
| 2898 | case ARM::VST4q16: |
| 2899 | case ARM::VST4q32: |
| 2900 | case ARM::VST4q8_UPD: |
| 2901 | case ARM::VST4q16_UPD: |
| 2902 | case ARM::VST4q32_UPD: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2903 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) |
| 2904 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2905 | break; |
| 2906 | default: |
| 2907 | break; |
| 2908 | } |
| 2909 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2910 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2911 | } |
| 2912 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2913 | static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2914 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2915 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2916 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2917 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 2918 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 2919 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 2920 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 2921 | unsigned align = fieldFromInstruction(Insn, 4, 1); |
| 2922 | unsigned size = fieldFromInstruction(Insn, 6, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2923 | |
Tim Northover | 00e071a | 2012-09-06 15:27:12 +0000 | [diff] [blame] | 2924 | if (size == 0 && align == 1) |
| 2925 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2926 | align *= (1 << size); |
| 2927 | |
Jim Grosbach | 13a292c | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 2928 | switch (Inst.getOpcode()) { |
| 2929 | case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: |
| 2930 | case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: |
| 2931 | case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: |
| 2932 | case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: |
| 2933 | if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
| 2934 | return MCDisassembler::Fail; |
| 2935 | break; |
| 2936 | default: |
| 2937 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2938 | return MCDisassembler::Fail; |
| 2939 | break; |
| 2940 | } |
Owen Anderson | ac92e77 | 2011-08-22 18:22:06 +0000 | [diff] [blame] | 2941 | if (Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2942 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2943 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 2944 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2945 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2946 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2947 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2948 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2949 | |
Jim Grosbach | a68c9a8 | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 2950 | // The fixed offset post-increment encodes Rm == 0xd. The no-writeback |
| 2951 | // variant encodes Rm == 0xf. Anything else is a register offset post- |
| 2952 | // increment and we need to add the register operand to the instruction. |
| 2953 | if (Rm != 0xD && Rm != 0xF && |
| 2954 | !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 2955 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2956 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2957 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2958 | } |
| 2959 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 2960 | static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2961 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2962 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 2963 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 2964 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 2965 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 2966 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 2967 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 2968 | unsigned align = fieldFromInstruction(Insn, 4, 1); |
| 2969 | unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2970 | align *= 2*size; |
| 2971 | |
Jim Grosbach | 13a292c | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 2972 | switch (Inst.getOpcode()) { |
| 2973 | case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: |
| 2974 | case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: |
| 2975 | case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: |
| 2976 | case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: |
| 2977 | if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) |
| 2978 | return MCDisassembler::Fail; |
| 2979 | break; |
Jim Grosbach | ed428bc | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 2980 | case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: |
| 2981 | case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: |
| 2982 | case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: |
| 2983 | case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: |
| 2984 | if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) |
| 2985 | return MCDisassembler::Fail; |
| 2986 | break; |
Jim Grosbach | 13a292c | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 2987 | default: |
| 2988 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 2989 | return MCDisassembler::Fail; |
| 2990 | break; |
| 2991 | } |
Kevin Enderby | 520eb3b | 2012-03-06 18:33:12 +0000 | [diff] [blame] | 2992 | |
| 2993 | if (Rm != 0xF) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2994 | Inst.addOperand(MCOperand::createImm(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2995 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 2996 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 2997 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 2998 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2999 | |
Kevin Enderby | 29ae538 | 2012-04-17 00:49:27 +0000 | [diff] [blame] | 3000 | if (Rm != 0xD && Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3001 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3002 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3003 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3004 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3005 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3006 | } |
| 3007 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3008 | static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3009 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3010 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3011 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3012 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 3013 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 3014 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3015 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 3016 | unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3017 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3018 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3019 | return MCDisassembler::Fail; |
| 3020 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) |
| 3021 | return MCDisassembler::Fail; |
| 3022 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) |
| 3023 | return MCDisassembler::Fail; |
Owen Anderson | ac92e77 | 2011-08-22 18:22:06 +0000 | [diff] [blame] | 3024 | if (Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3025 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3026 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3027 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3028 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3029 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3030 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3031 | Inst.addOperand(MCOperand::createImm(0)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3032 | |
| 3033 | if (Rm == 0xD) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3034 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3035 | else if (Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3036 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3037 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3038 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3039 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3040 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3041 | } |
| 3042 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3043 | static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3044 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3045 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3046 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3047 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 3048 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 3049 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3050 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 3051 | unsigned size = fieldFromInstruction(Insn, 6, 2); |
| 3052 | unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; |
| 3053 | unsigned align = fieldFromInstruction(Insn, 4, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3054 | |
| 3055 | if (size == 0x3) { |
Tim Northover | 00e071a | 2012-09-06 15:27:12 +0000 | [diff] [blame] | 3056 | if (align == 0) |
| 3057 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3058 | align = 16; |
| 3059 | } else { |
| 3060 | if (size == 2) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3061 | align *= 8; |
| 3062 | } else { |
| 3063 | size = 1 << size; |
| 3064 | align *= 4*size; |
| 3065 | } |
| 3066 | } |
| 3067 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3068 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3069 | return MCDisassembler::Fail; |
| 3070 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) |
| 3071 | return MCDisassembler::Fail; |
| 3072 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) |
| 3073 | return MCDisassembler::Fail; |
| 3074 | if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) |
| 3075 | return MCDisassembler::Fail; |
Owen Anderson | ac92e77 | 2011-08-22 18:22:06 +0000 | [diff] [blame] | 3076 | if (Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3077 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3078 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3079 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3080 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3081 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3082 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3083 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3084 | |
| 3085 | if (Rm == 0xD) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3086 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3087 | else if (Rm != 0xF) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3088 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3089 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3090 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3091 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3092 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3093 | } |
| 3094 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3095 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3096 | DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 3097 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3098 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3099 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3100 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 3101 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 3102 | unsigned imm = fieldFromInstruction(Insn, 0, 4); |
| 3103 | imm |= fieldFromInstruction(Insn, 16, 3) << 4; |
| 3104 | imm |= fieldFromInstruction(Insn, 24, 1) << 7; |
| 3105 | imm |= fieldFromInstruction(Insn, 8, 4) << 8; |
| 3106 | imm |= fieldFromInstruction(Insn, 5, 1) << 12; |
| 3107 | unsigned Q = fieldFromInstruction(Insn, 6, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3108 | |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3109 | if (Q) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3110 | if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3111 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3112 | } else { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3113 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3114 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3115 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3116 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3117 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3118 | |
| 3119 | switch (Inst.getOpcode()) { |
| 3120 | case ARM::VORRiv4i16: |
| 3121 | case ARM::VORRiv2i32: |
| 3122 | case ARM::VBICiv4i16: |
| 3123 | case ARM::VBICiv2i32: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3124 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3125 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3126 | break; |
| 3127 | case ARM::VORRiv8i16: |
| 3128 | case ARM::VORRiv4i32: |
| 3129 | case ARM::VBICiv8i16: |
| 3130 | case ARM::VBICiv4i32: |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3131 | if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3132 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3133 | break; |
| 3134 | default: |
| 3135 | break; |
| 3136 | } |
| 3137 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3138 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3139 | } |
| 3140 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3141 | static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3142 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3143 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3144 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3145 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 3146 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 3147 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 3148 | Rm |= fieldFromInstruction(Insn, 5, 1) << 4; |
| 3149 | unsigned size = fieldFromInstruction(Insn, 18, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3150 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3151 | if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3152 | return MCDisassembler::Fail; |
| 3153 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3154 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3155 | Inst.addOperand(MCOperand::createImm(8 << size)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3156 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3157 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3158 | } |
| 3159 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3160 | static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3161 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3162 | Inst.addOperand(MCOperand::createImm(8 - Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3163 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3164 | } |
| 3165 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3166 | static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3167 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3168 | Inst.addOperand(MCOperand::createImm(16 - Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3169 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3170 | } |
| 3171 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3172 | static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3173 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3174 | Inst.addOperand(MCOperand::createImm(32 - Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3175 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3176 | } |
| 3177 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3178 | static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3179 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3180 | Inst.addOperand(MCOperand::createImm(64 - Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3181 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3182 | } |
| 3183 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3184 | static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3185 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3186 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3187 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3188 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 3189 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 3190 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3191 | Rn |= fieldFromInstruction(Insn, 7, 1) << 4; |
| 3192 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 3193 | Rm |= fieldFromInstruction(Insn, 5, 1) << 4; |
| 3194 | unsigned op = fieldFromInstruction(Insn, 6, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3195 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3196 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3197 | return MCDisassembler::Fail; |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3198 | if (op) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3199 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 3200 | return MCDisassembler::Fail; // Writeback |
Owen Anderson | ed25385 | 2011-08-11 18:24:51 +0000 | [diff] [blame] | 3201 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3202 | |
Jim Grosbach | c988e0c | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 3203 | switch (Inst.getOpcode()) { |
| 3204 | case ARM::VTBL2: |
| 3205 | case ARM::VTBX2: |
| 3206 | if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) |
| 3207 | return MCDisassembler::Fail; |
| 3208 | break; |
| 3209 | default: |
| 3210 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3211 | return MCDisassembler::Fail; |
| 3212 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3213 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3214 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3215 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3216 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3217 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3218 | } |
| 3219 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3220 | static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3221 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3222 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3223 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3224 | unsigned dst = fieldFromInstruction(Insn, 8, 3); |
| 3225 | unsigned imm = fieldFromInstruction(Insn, 0, 8); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3226 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3227 | if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) |
| 3228 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3229 | |
Owen Anderson | a01bcbf | 2011-08-26 18:09:22 +0000 | [diff] [blame] | 3230 | switch(Inst.getOpcode()) { |
Owen Anderson | 5658b49 | 2011-08-26 19:39:26 +0000 | [diff] [blame] | 3231 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3232 | return MCDisassembler::Fail; |
Owen Anderson | a01bcbf | 2011-08-26 18:09:22 +0000 | [diff] [blame] | 3233 | case ARM::tADR: |
Owen Anderson | 240d20a | 2011-08-26 21:47:57 +0000 | [diff] [blame] | 3234 | break; // tADR does not explicitly represent the PC as an operand. |
Owen Anderson | a01bcbf | 2011-08-26 18:09:22 +0000 | [diff] [blame] | 3235 | case ARM::tADDrSPi: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3236 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
Owen Anderson | a01bcbf | 2011-08-26 18:09:22 +0000 | [diff] [blame] | 3237 | break; |
Owen Anderson | a01bcbf | 2011-08-26 18:09:22 +0000 | [diff] [blame] | 3238 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3239 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3240 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3241 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3242 | } |
| 3243 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3244 | static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3245 | uint64_t Address, const void *Decoder) { |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 3246 | if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, |
| 3247 | true, 2, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3248 | Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3249 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3250 | } |
| 3251 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3252 | static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3253 | uint64_t Address, const void *Decoder) { |
Kevin Enderby | cabbae6 | 2012-05-04 22:09:52 +0000 | [diff] [blame] | 3254 | if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 3255 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3256 | Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3257 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3258 | } |
| 3259 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3260 | static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3261 | uint64_t Address, const void *Decoder) { |
Gordon Keiser | 772cf46 | 2013-03-28 19:22:28 +0000 | [diff] [blame] | 3262 | if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 3263 | true, 2, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3264 | Inst.addOperand(MCOperand::createImm(Val << 1)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3265 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3266 | } |
| 3267 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3268 | static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3269 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3270 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3271 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3272 | unsigned Rn = fieldFromInstruction(Val, 0, 3); |
| 3273 | unsigned Rm = fieldFromInstruction(Val, 3, 3); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3274 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3275 | if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3276 | return MCDisassembler::Fail; |
| 3277 | if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3278 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3279 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3280 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3281 | } |
| 3282 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3283 | static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3284 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3285 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3286 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3287 | unsigned Rn = fieldFromInstruction(Val, 0, 3); |
| 3288 | unsigned imm = fieldFromInstruction(Val, 3, 5); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3289 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3290 | if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3291 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3292 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3293 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3294 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3295 | } |
| 3296 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3297 | static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3298 | uint64_t Address, const void *Decoder) { |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 3299 | unsigned imm = Val << 2; |
| 3300 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3301 | Inst.addOperand(MCOperand::createImm(imm)); |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 3302 | tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3303 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3304 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3305 | } |
| 3306 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3307 | static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3308 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3309 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
| 3310 | Inst.addOperand(MCOperand::createImm(Val)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3311 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3312 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3313 | } |
| 3314 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3315 | static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3316 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3317 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3318 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3319 | unsigned Rn = fieldFromInstruction(Val, 6, 4); |
| 3320 | unsigned Rm = fieldFromInstruction(Val, 2, 4); |
| 3321 | unsigned imm = fieldFromInstruction(Val, 0, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3322 | |
Amaury de la Vieuville | e2bb1d1 | 2013-06-18 08:02:56 +0000 | [diff] [blame] | 3323 | // Thumb stores cannot use PC as dest register. |
| 3324 | switch (Inst.getOpcode()) { |
| 3325 | case ARM::t2STRHs: |
| 3326 | case ARM::t2STRBs: |
| 3327 | case ARM::t2STRs: |
| 3328 | if (Rn == 15) |
| 3329 | return MCDisassembler::Fail; |
Adrian Prantl | 0e6694d | 2017-12-19 22:05:25 +0000 | [diff] [blame^] | 3330 | break; |
Amaury de la Vieuville | e2bb1d1 | 2013-06-18 08:02:56 +0000 | [diff] [blame] | 3331 | default: |
| 3332 | break; |
| 3333 | } |
| 3334 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3335 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3336 | return MCDisassembler::Fail; |
| 3337 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3338 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3339 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3340 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3341 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3342 | } |
| 3343 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3344 | static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3345 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3346 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3347 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3348 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3349 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3350 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 3351 | const FeatureBitset &featureBits = |
| 3352 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 3353 | |
| 3354 | bool hasMP = featureBits[ARM::FeatureMP]; |
| 3355 | bool hasV7Ops = featureBits[ARM::HasV7Ops]; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3356 | |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3357 | if (Rn == 15) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3358 | switch (Inst.getOpcode()) { |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3359 | case ARM::t2LDRBs: |
| 3360 | Inst.setOpcode(ARM::t2LDRBpci); |
| 3361 | break; |
| 3362 | case ARM::t2LDRHs: |
| 3363 | Inst.setOpcode(ARM::t2LDRHpci); |
| 3364 | break; |
| 3365 | case ARM::t2LDRSHs: |
| 3366 | Inst.setOpcode(ARM::t2LDRSHpci); |
| 3367 | break; |
| 3368 | case ARM::t2LDRSBs: |
| 3369 | Inst.setOpcode(ARM::t2LDRSBpci); |
| 3370 | break; |
| 3371 | case ARM::t2LDRs: |
| 3372 | Inst.setOpcode(ARM::t2LDRpci); |
| 3373 | break; |
| 3374 | case ARM::t2PLDs: |
| 3375 | Inst.setOpcode(ARM::t2PLDpci); |
| 3376 | break; |
| 3377 | case ARM::t2PLIs: |
| 3378 | Inst.setOpcode(ARM::t2PLIpci); |
| 3379 | break; |
| 3380 | default: |
| 3381 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3382 | } |
| 3383 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3384 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3385 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3386 | |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3387 | if (Rt == 15) { |
| 3388 | switch (Inst.getOpcode()) { |
| 3389 | case ARM::t2LDRSHs: |
| 3390 | return MCDisassembler::Fail; |
| 3391 | case ARM::t2LDRHs: |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3392 | Inst.setOpcode(ARM::t2PLDWs); |
| 3393 | break; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3394 | case ARM::t2LDRSBs: |
| 3395 | Inst.setOpcode(ARM::t2PLIs); |
Adrian Prantl | 0e6694d | 2017-12-19 22:05:25 +0000 | [diff] [blame^] | 3396 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3397 | default: |
| 3398 | break; |
| 3399 | } |
| 3400 | } |
| 3401 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3402 | switch (Inst.getOpcode()) { |
| 3403 | case ARM::t2PLDs: |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3404 | break; |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3405 | case ARM::t2PLIs: |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3406 | if (!hasV7Ops) |
| 3407 | return MCDisassembler::Fail; |
| 3408 | break; |
| 3409 | case ARM::t2PLDWs: |
| 3410 | if (!hasV7Ops || !hasMP) |
| 3411 | return MCDisassembler::Fail; |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3412 | break; |
| 3413 | default: |
| 3414 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3415 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3416 | } |
| 3417 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3418 | unsigned addrmode = fieldFromInstruction(Insn, 4, 2); |
| 3419 | addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; |
| 3420 | addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3421 | if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) |
| 3422 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3423 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3424 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3425 | } |
| 3426 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3427 | static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, |
| 3428 | uint64_t Address, const void* Decoder) { |
| 3429 | DecodeStatus S = MCDisassembler::Success; |
| 3430 | |
| 3431 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3432 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 3433 | unsigned U = fieldFromInstruction(Insn, 9, 1); |
| 3434 | unsigned imm = fieldFromInstruction(Insn, 0, 8); |
| 3435 | imm |= (U << 8); |
| 3436 | imm |= (Rn << 9); |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3437 | unsigned add = fieldFromInstruction(Insn, 9, 1); |
| 3438 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 3439 | const FeatureBitset &featureBits = |
| 3440 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 3441 | |
| 3442 | bool hasMP = featureBits[ARM::FeatureMP]; |
| 3443 | bool hasV7Ops = featureBits[ARM::HasV7Ops]; |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3444 | |
| 3445 | if (Rn == 15) { |
| 3446 | switch (Inst.getOpcode()) { |
| 3447 | case ARM::t2LDRi8: |
| 3448 | Inst.setOpcode(ARM::t2LDRpci); |
| 3449 | break; |
| 3450 | case ARM::t2LDRBi8: |
| 3451 | Inst.setOpcode(ARM::t2LDRBpci); |
| 3452 | break; |
| 3453 | case ARM::t2LDRSBi8: |
| 3454 | Inst.setOpcode(ARM::t2LDRSBpci); |
| 3455 | break; |
| 3456 | case ARM::t2LDRHi8: |
| 3457 | Inst.setOpcode(ARM::t2LDRHpci); |
| 3458 | break; |
| 3459 | case ARM::t2LDRSHi8: |
| 3460 | Inst.setOpcode(ARM::t2LDRSHpci); |
| 3461 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3462 | case ARM::t2PLDi8: |
| 3463 | Inst.setOpcode(ARM::t2PLDpci); |
| 3464 | break; |
| 3465 | case ARM::t2PLIi8: |
| 3466 | Inst.setOpcode(ARM::t2PLIpci); |
| 3467 | break; |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3468 | default: |
| 3469 | return MCDisassembler::Fail; |
| 3470 | } |
| 3471 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3472 | } |
| 3473 | |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3474 | if (Rt == 15) { |
| 3475 | switch (Inst.getOpcode()) { |
| 3476 | case ARM::t2LDRSHi8: |
| 3477 | return MCDisassembler::Fail; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3478 | case ARM::t2LDRHi8: |
| 3479 | if (!add) |
| 3480 | Inst.setOpcode(ARM::t2PLDWi8); |
| 3481 | break; |
| 3482 | case ARM::t2LDRSBi8: |
| 3483 | Inst.setOpcode(ARM::t2PLIi8); |
| 3484 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3485 | default: |
| 3486 | break; |
| 3487 | } |
| 3488 | } |
| 3489 | |
| 3490 | switch (Inst.getOpcode()) { |
| 3491 | case ARM::t2PLDi8: |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3492 | break; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3493 | case ARM::t2PLIi8: |
| 3494 | if (!hasV7Ops) |
| 3495 | return MCDisassembler::Fail; |
| 3496 | break; |
| 3497 | case ARM::t2PLDWi8: |
| 3498 | if (!hasV7Ops || !hasMP) |
| 3499 | return MCDisassembler::Fail; |
| 3500 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3501 | default: |
| 3502 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3503 | return MCDisassembler::Fail; |
| 3504 | } |
| 3505 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3506 | if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) |
| 3507 | return MCDisassembler::Fail; |
| 3508 | return S; |
| 3509 | } |
| 3510 | |
| 3511 | static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, |
| 3512 | uint64_t Address, const void* Decoder) { |
| 3513 | DecodeStatus S = MCDisassembler::Success; |
| 3514 | |
| 3515 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3516 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 3517 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 3518 | imm |= (Rn << 13); |
| 3519 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 3520 | const FeatureBitset &featureBits = |
| 3521 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 3522 | |
| 3523 | bool hasMP = featureBits[ARM::FeatureMP]; |
| 3524 | bool hasV7Ops = featureBits[ARM::HasV7Ops]; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3525 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3526 | if (Rn == 15) { |
| 3527 | switch (Inst.getOpcode()) { |
| 3528 | case ARM::t2LDRi12: |
| 3529 | Inst.setOpcode(ARM::t2LDRpci); |
| 3530 | break; |
| 3531 | case ARM::t2LDRHi12: |
| 3532 | Inst.setOpcode(ARM::t2LDRHpci); |
| 3533 | break; |
| 3534 | case ARM::t2LDRSHi12: |
| 3535 | Inst.setOpcode(ARM::t2LDRSHpci); |
| 3536 | break; |
| 3537 | case ARM::t2LDRBi12: |
| 3538 | Inst.setOpcode(ARM::t2LDRBpci); |
| 3539 | break; |
| 3540 | case ARM::t2LDRSBi12: |
| 3541 | Inst.setOpcode(ARM::t2LDRSBpci); |
| 3542 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3543 | case ARM::t2PLDi12: |
| 3544 | Inst.setOpcode(ARM::t2PLDpci); |
| 3545 | break; |
| 3546 | case ARM::t2PLIi12: |
| 3547 | Inst.setOpcode(ARM::t2PLIpci); |
| 3548 | break; |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3549 | default: |
| 3550 | return MCDisassembler::Fail; |
| 3551 | } |
| 3552 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3553 | } |
| 3554 | |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3555 | if (Rt == 15) { |
| 3556 | switch (Inst.getOpcode()) { |
| 3557 | case ARM::t2LDRSHi12: |
| 3558 | return MCDisassembler::Fail; |
| 3559 | case ARM::t2LDRHi12: |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3560 | Inst.setOpcode(ARM::t2PLDWi12); |
| 3561 | break; |
| 3562 | case ARM::t2LDRSBi12: |
| 3563 | Inst.setOpcode(ARM::t2PLIi12); |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3564 | break; |
| 3565 | default: |
| 3566 | break; |
| 3567 | } |
| 3568 | } |
| 3569 | |
| 3570 | switch (Inst.getOpcode()) { |
| 3571 | case ARM::t2PLDi12: |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3572 | break; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3573 | case ARM::t2PLIi12: |
| 3574 | if (!hasV7Ops) |
| 3575 | return MCDisassembler::Fail; |
| 3576 | break; |
| 3577 | case ARM::t2PLDWi12: |
| 3578 | if (!hasV7Ops || !hasMP) |
| 3579 | return MCDisassembler::Fail; |
| 3580 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3581 | default: |
| 3582 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3583 | return MCDisassembler::Fail; |
| 3584 | } |
| 3585 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3586 | if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) |
| 3587 | return MCDisassembler::Fail; |
| 3588 | return S; |
| 3589 | } |
| 3590 | |
| 3591 | static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, |
| 3592 | uint64_t Address, const void* Decoder) { |
| 3593 | DecodeStatus S = MCDisassembler::Success; |
| 3594 | |
| 3595 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3596 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 3597 | unsigned imm = fieldFromInstruction(Insn, 0, 8); |
| 3598 | imm |= (Rn << 9); |
| 3599 | |
| 3600 | if (Rn == 15) { |
| 3601 | switch (Inst.getOpcode()) { |
| 3602 | case ARM::t2LDRT: |
| 3603 | Inst.setOpcode(ARM::t2LDRpci); |
| 3604 | break; |
| 3605 | case ARM::t2LDRBT: |
| 3606 | Inst.setOpcode(ARM::t2LDRBpci); |
| 3607 | break; |
| 3608 | case ARM::t2LDRHT: |
| 3609 | Inst.setOpcode(ARM::t2LDRHpci); |
| 3610 | break; |
| 3611 | case ARM::t2LDRSBT: |
| 3612 | Inst.setOpcode(ARM::t2LDRSBpci); |
| 3613 | break; |
| 3614 | case ARM::t2LDRSHT: |
| 3615 | Inst.setOpcode(ARM::t2LDRSHpci); |
| 3616 | break; |
| 3617 | default: |
| 3618 | return MCDisassembler::Fail; |
| 3619 | } |
| 3620 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3621 | } |
| 3622 | |
| 3623 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3624 | return MCDisassembler::Fail; |
| 3625 | if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) |
| 3626 | return MCDisassembler::Fail; |
| 3627 | return S; |
| 3628 | } |
| 3629 | |
| 3630 | static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, |
| 3631 | uint64_t Address, const void* Decoder) { |
| 3632 | DecodeStatus S = MCDisassembler::Success; |
| 3633 | |
| 3634 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 3635 | unsigned U = fieldFromInstruction(Insn, 23, 1); |
| 3636 | int imm = fieldFromInstruction(Insn, 0, 12); |
| 3637 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 3638 | const FeatureBitset &featureBits = |
| 3639 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 3640 | |
| 3641 | bool hasV7Ops = featureBits[ARM::HasV7Ops]; |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3642 | |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3643 | if (Rt == 15) { |
| 3644 | switch (Inst.getOpcode()) { |
| 3645 | case ARM::t2LDRBpci: |
| 3646 | case ARM::t2LDRHpci: |
| 3647 | Inst.setOpcode(ARM::t2PLDpci); |
| 3648 | break; |
| 3649 | case ARM::t2LDRSBpci: |
| 3650 | Inst.setOpcode(ARM::t2PLIpci); |
| 3651 | break; |
| 3652 | case ARM::t2LDRSHpci: |
| 3653 | return MCDisassembler::Fail; |
| 3654 | default: |
| 3655 | break; |
| 3656 | } |
| 3657 | } |
| 3658 | |
| 3659 | switch(Inst.getOpcode()) { |
| 3660 | case ARM::t2PLDpci: |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3661 | break; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3662 | case ARM::t2PLIpci: |
Oliver Stannard | 39a85ab | 2014-10-23 08:52:58 +0000 | [diff] [blame] | 3663 | if (!hasV7Ops) |
| 3664 | return MCDisassembler::Fail; |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3665 | break; |
| 3666 | default: |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3667 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 3668 | return MCDisassembler::Fail; |
| 3669 | } |
| 3670 | |
| 3671 | if (!U) { |
| 3672 | // Special case for #-0. |
| 3673 | if (imm == 0) |
| 3674 | imm = INT32_MIN; |
| 3675 | else |
| 3676 | imm = -imm; |
| 3677 | } |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3678 | Inst.addOperand(MCOperand::createImm(imm)); |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3679 | |
| 3680 | return S; |
| 3681 | } |
| 3682 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3683 | static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3684 | uint64_t Address, const void *Decoder) { |
Jiangning Liu | 6a43bf7 | 2012-08-02 08:29:50 +0000 | [diff] [blame] | 3685 | if (Val == 0) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3686 | Inst.addOperand(MCOperand::createImm(INT32_MIN)); |
Jiangning Liu | 6a43bf7 | 2012-08-02 08:29:50 +0000 | [diff] [blame] | 3687 | else { |
| 3688 | int imm = Val & 0xFF; |
| 3689 | |
| 3690 | if (!(Val & 0x100)) imm *= -1; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3691 | Inst.addOperand(MCOperand::createImm(imm * 4)); |
Jiangning Liu | 6a43bf7 | 2012-08-02 08:29:50 +0000 | [diff] [blame] | 3692 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3693 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3694 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3695 | } |
| 3696 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3697 | static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3698 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3699 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3700 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3701 | unsigned Rn = fieldFromInstruction(Val, 9, 4); |
| 3702 | unsigned imm = fieldFromInstruction(Val, 0, 9); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3703 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3704 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3705 | return MCDisassembler::Fail; |
| 3706 | if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) |
| 3707 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3708 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3709 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3710 | } |
| 3711 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3712 | static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, |
Jim Grosbach | a05627e | 2011-09-09 18:37:27 +0000 | [diff] [blame] | 3713 | uint64_t Address, const void *Decoder) { |
| 3714 | DecodeStatus S = MCDisassembler::Success; |
| 3715 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3716 | unsigned Rn = fieldFromInstruction(Val, 8, 4); |
| 3717 | unsigned imm = fieldFromInstruction(Val, 0, 8); |
Jim Grosbach | a05627e | 2011-09-09 18:37:27 +0000 | [diff] [blame] | 3718 | |
| 3719 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
| 3720 | return MCDisassembler::Fail; |
| 3721 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3722 | Inst.addOperand(MCOperand::createImm(imm)); |
Jim Grosbach | a05627e | 2011-09-09 18:37:27 +0000 | [diff] [blame] | 3723 | |
| 3724 | return S; |
| 3725 | } |
| 3726 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3727 | static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3728 | uint64_t Address, const void *Decoder) { |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3729 | int imm = Val & 0xFF; |
Owen Anderson | fe82365 | 2011-09-16 21:08:33 +0000 | [diff] [blame] | 3730 | if (Val == 0) |
| 3731 | imm = INT32_MIN; |
| 3732 | else if (!(Val & 0x100)) |
| 3733 | imm *= -1; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3734 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3735 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3736 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3737 | } |
| 3738 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3739 | static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3740 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3741 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3742 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3743 | unsigned Rn = fieldFromInstruction(Val, 9, 4); |
| 3744 | unsigned imm = fieldFromInstruction(Val, 0, 9); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3745 | |
Amaury de la Vieuville | e2bb1d1 | 2013-06-18 08:02:56 +0000 | [diff] [blame] | 3746 | // Thumb stores cannot use PC as dest register. |
| 3747 | switch (Inst.getOpcode()) { |
| 3748 | case ARM::t2STRT: |
| 3749 | case ARM::t2STRBT: |
| 3750 | case ARM::t2STRHT: |
| 3751 | case ARM::t2STRi8: |
| 3752 | case ARM::t2STRHi8: |
| 3753 | case ARM::t2STRBi8: |
| 3754 | if (Rn == 15) |
| 3755 | return MCDisassembler::Fail; |
| 3756 | break; |
| 3757 | default: |
| 3758 | break; |
| 3759 | } |
| 3760 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3761 | // Some instructions always use an additive offset. |
| 3762 | switch (Inst.getOpcode()) { |
| 3763 | case ARM::t2LDRT: |
| 3764 | case ARM::t2LDRBT: |
| 3765 | case ARM::t2LDRHT: |
| 3766 | case ARM::t2LDRSBT: |
| 3767 | case ARM::t2LDRSHT: |
Owen Anderson | ddfcec9 | 2011-09-19 18:07:10 +0000 | [diff] [blame] | 3768 | case ARM::t2STRT: |
| 3769 | case ARM::t2STRBT: |
| 3770 | case ARM::t2STRHT: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3771 | imm |= 0x100; |
| 3772 | break; |
| 3773 | default: |
| 3774 | break; |
| 3775 | } |
| 3776 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3777 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3778 | return MCDisassembler::Fail; |
| 3779 | if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) |
| 3780 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3781 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3782 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3783 | } |
| 3784 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3785 | static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 3786 | uint64_t Address, const void *Decoder) { |
| 3787 | DecodeStatus S = MCDisassembler::Success; |
| 3788 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3789 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 3790 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3791 | unsigned addr = fieldFromInstruction(Insn, 0, 8); |
| 3792 | addr |= fieldFromInstruction(Insn, 9, 1) << 8; |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 3793 | addr |= Rn << 9; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3794 | unsigned load = fieldFromInstruction(Insn, 20, 1); |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 3795 | |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3796 | if (Rn == 15) { |
| 3797 | switch (Inst.getOpcode()) { |
| 3798 | case ARM::t2LDR_PRE: |
| 3799 | case ARM::t2LDR_POST: |
| 3800 | Inst.setOpcode(ARM::t2LDRpci); |
| 3801 | break; |
| 3802 | case ARM::t2LDRB_PRE: |
| 3803 | case ARM::t2LDRB_POST: |
| 3804 | Inst.setOpcode(ARM::t2LDRBpci); |
| 3805 | break; |
| 3806 | case ARM::t2LDRH_PRE: |
| 3807 | case ARM::t2LDRH_POST: |
| 3808 | Inst.setOpcode(ARM::t2LDRHpci); |
| 3809 | break; |
| 3810 | case ARM::t2LDRSB_PRE: |
| 3811 | case ARM::t2LDRSB_POST: |
Amaury de la Vieuville | 4b6c076 | 2013-06-24 09:11:38 +0000 | [diff] [blame] | 3812 | if (Rt == 15) |
| 3813 | Inst.setOpcode(ARM::t2PLIpci); |
| 3814 | else |
| 3815 | Inst.setOpcode(ARM::t2LDRSBpci); |
Amaury de la Vieuville | 4d3e3f2 | 2013-06-18 08:03:06 +0000 | [diff] [blame] | 3816 | break; |
| 3817 | case ARM::t2LDRSH_PRE: |
| 3818 | case ARM::t2LDRSH_POST: |
| 3819 | Inst.setOpcode(ARM::t2LDRSHpci); |
| 3820 | break; |
| 3821 | default: |
| 3822 | return MCDisassembler::Fail; |
| 3823 | } |
| 3824 | return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); |
| 3825 | } |
| 3826 | |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 3827 | if (!load) { |
| 3828 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3829 | return MCDisassembler::Fail; |
| 3830 | } |
| 3831 | |
Joe Abbey | f686be4 | 2013-03-26 13:58:53 +0000 | [diff] [blame] | 3832 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 3833 | return MCDisassembler::Fail; |
| 3834 | |
| 3835 | if (load) { |
| 3836 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3837 | return MCDisassembler::Fail; |
| 3838 | } |
| 3839 | |
| 3840 | if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) |
| 3841 | return MCDisassembler::Fail; |
| 3842 | |
| 3843 | return S; |
| 3844 | } |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3845 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3846 | static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3847 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3848 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3849 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3850 | unsigned Rn = fieldFromInstruction(Val, 13, 4); |
| 3851 | unsigned imm = fieldFromInstruction(Val, 0, 12); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3852 | |
Amaury de la Vieuville | e2bb1d1 | 2013-06-18 08:02:56 +0000 | [diff] [blame] | 3853 | // Thumb stores cannot use PC as dest register. |
| 3854 | switch (Inst.getOpcode()) { |
| 3855 | case ARM::t2STRi12: |
| 3856 | case ARM::t2STRBi12: |
| 3857 | case ARM::t2STRHi12: |
| 3858 | if (Rn == 15) |
| 3859 | return MCDisassembler::Fail; |
Adrian Prantl | 0e6694d | 2017-12-19 22:05:25 +0000 | [diff] [blame^] | 3860 | break; |
Amaury de la Vieuville | e2bb1d1 | 2013-06-18 08:02:56 +0000 | [diff] [blame] | 3861 | default: |
| 3862 | break; |
| 3863 | } |
| 3864 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3865 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3866 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3867 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3868 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3869 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3870 | } |
| 3871 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3872 | static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3873 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3874 | unsigned imm = fieldFromInstruction(Insn, 0, 7); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3875 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3876 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
| 3877 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
| 3878 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3879 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3880 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3881 | } |
| 3882 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3883 | static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3884 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3885 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3886 | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3887 | if (Inst.getOpcode() == ARM::tADDrSP) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3888 | unsigned Rdm = fieldFromInstruction(Insn, 0, 3); |
| 3889 | Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3890 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3891 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) |
| 3892 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3893 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3894 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) |
| 3895 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3896 | } else if (Inst.getOpcode() == ARM::tADDspr) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3897 | unsigned Rm = fieldFromInstruction(Insn, 3, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3898 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3899 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
| 3900 | Inst.addOperand(MCOperand::createReg(ARM::SP)); |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3901 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3902 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3903 | } |
| 3904 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3905 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3906 | } |
| 3907 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3908 | static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3909 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3910 | unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; |
| 3911 | unsigned flags = fieldFromInstruction(Insn, 0, 3); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3912 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3913 | Inst.addOperand(MCOperand::createImm(imod)); |
| 3914 | Inst.addOperand(MCOperand::createImm(flags)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3915 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3916 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3917 | } |
| 3918 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3919 | static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3920 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3921 | DecodeStatus S = MCDisassembler::Success; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3922 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 3923 | unsigned add = fieldFromInstruction(Insn, 4, 1); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3924 | |
Silviu Baranga | d213f21 | 2012-03-22 13:24:43 +0000 | [diff] [blame] | 3925 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3926 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3927 | Inst.addOperand(MCOperand::createImm(add)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3928 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3929 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3930 | } |
| 3931 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3932 | static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, |
Owen Anderson | 5d69f63 | 2011-08-10 17:36:48 +0000 | [diff] [blame] | 3933 | uint64_t Address, const void *Decoder) { |
NAKAMURA Takumi | 70c1aa0 | 2012-05-22 21:47:02 +0000 | [diff] [blame] | 3934 | // Val is passed in as S:J1:J2:imm10H:imm10L:'0' |
Kevin Enderby | 9142230 | 2012-05-03 22:41:56 +0000 | [diff] [blame] | 3935 | // Note only one trailing zero not two. Also the J1 and J2 values are from |
| 3936 | // the encoded instruction. So here change to I1 and I2 values via: |
| 3937 | // I1 = NOT(J1 EOR S); |
| 3938 | // I2 = NOT(J2 EOR S); |
| 3939 | // and build the imm32 with two trailing zeros as documented: |
NAKAMURA Takumi | 70c1aa0 | 2012-05-22 21:47:02 +0000 | [diff] [blame] | 3940 | // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); |
Kevin Enderby | 9142230 | 2012-05-03 22:41:56 +0000 | [diff] [blame] | 3941 | unsigned S = (Val >> 23) & 1; |
| 3942 | unsigned J1 = (Val >> 22) & 1; |
| 3943 | unsigned J2 = (Val >> 21) & 1; |
| 3944 | unsigned I1 = !(J1 ^ S); |
| 3945 | unsigned I2 = !(J2 ^ S); |
| 3946 | unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); |
| 3947 | int imm32 = SignExtend32<25>(tmp << 1); |
| 3948 | |
Jim Grosbach | 79ebc51 | 2011-10-20 17:28:20 +0000 | [diff] [blame] | 3949 | if (!tryAddingSymbolicOperand(Address, |
Kevin Enderby | 9142230 | 2012-05-03 22:41:56 +0000 | [diff] [blame] | 3950 | (Address & ~2u) + imm32 + 4, |
Kevin Enderby | 5dcda64 | 2011-10-04 22:44:48 +0000 | [diff] [blame] | 3951 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3952 | Inst.addOperand(MCOperand::createImm(imm32)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3953 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3954 | } |
| 3955 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3956 | static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3957 | uint64_t Address, const void *Decoder) { |
| 3958 | if (Val == 0xA || Val == 0xB) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3959 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3960 | |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 3961 | const FeatureBitset &featureBits = |
| 3962 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 3963 | |
| 3964 | if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) |
Artyom Skrobov | e686cec | 2013-11-08 16:16:30 +0000 | [diff] [blame] | 3965 | return MCDisassembler::Fail; |
| 3966 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 3967 | Inst.addOperand(MCOperand::createImm(Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3968 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3969 | } |
| 3970 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3971 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3972 | DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, |
Jim Grosbach | 05541f4 | 2011-09-19 22:21:13 +0000 | [diff] [blame] | 3973 | uint64_t Address, const void *Decoder) { |
| 3974 | DecodeStatus S = MCDisassembler::Success; |
| 3975 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3976 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 3977 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
Jim Grosbach | 05541f4 | 2011-09-19 22:21:13 +0000 | [diff] [blame] | 3978 | |
| 3979 | if (Rn == ARM::SP) S = MCDisassembler::SoftFail; |
| 3980 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 3981 | return MCDisassembler::Fail; |
| 3982 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 3983 | return MCDisassembler::Fail; |
| 3984 | return S; |
| 3985 | } |
| 3986 | |
| 3987 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 3988 | DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 3989 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 3990 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 3991 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3992 | unsigned pred = fieldFromInstruction(Insn, 22, 4); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3993 | if (pred == 0xE || pred == 0xF) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 3994 | unsigned opc = fieldFromInstruction(Insn, 4, 28); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3995 | switch (opc) { |
| 3996 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 3997 | return MCDisassembler::Fail; |
Owen Anderson | 4af0aa9 | 2011-08-31 22:00:41 +0000 | [diff] [blame] | 3998 | case 0xf3bf8f4: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 3999 | Inst.setOpcode(ARM::t2DSB); |
| 4000 | break; |
Owen Anderson | 4af0aa9 | 2011-08-31 22:00:41 +0000 | [diff] [blame] | 4001 | case 0xf3bf8f5: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4002 | Inst.setOpcode(ARM::t2DMB); |
| 4003 | break; |
Owen Anderson | 4af0aa9 | 2011-08-31 22:00:41 +0000 | [diff] [blame] | 4004 | case 0xf3bf8f6: |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4005 | Inst.setOpcode(ARM::t2ISB); |
Owen Anderson | cd5612d | 2011-09-07 17:55:19 +0000 | [diff] [blame] | 4006 | break; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4007 | } |
| 4008 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4009 | unsigned imm = fieldFromInstruction(Insn, 0, 4); |
Owen Anderson | e008931 | 2011-08-09 23:25:42 +0000 | [diff] [blame] | 4010 | return DecodeMemBarrierOption(Inst, imm, Address, Decoder); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4011 | } |
| 4012 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4013 | unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; |
| 4014 | brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; |
| 4015 | brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; |
| 4016 | brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; |
| 4017 | brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4018 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4019 | if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) |
| 4020 | return MCDisassembler::Fail; |
| 4021 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4022 | return MCDisassembler::Fail; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4023 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4024 | return S; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4025 | } |
| 4026 | |
| 4027 | // Decode a shifted immediate operand. These basically consist |
| 4028 | // of an 8-bit value, and a 4-bit directive that specifies either |
| 4029 | // a splat operation or a rotation. |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4030 | static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4031 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4032 | unsigned ctrl = fieldFromInstruction(Val, 10, 2); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4033 | if (ctrl == 0) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4034 | unsigned byte = fieldFromInstruction(Val, 8, 2); |
| 4035 | unsigned imm = fieldFromInstruction(Val, 0, 8); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4036 | switch (byte) { |
| 4037 | case 0: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4038 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4039 | break; |
| 4040 | case 1: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4041 | Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4042 | break; |
| 4043 | case 2: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4044 | Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4045 | break; |
| 4046 | case 3: |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4047 | Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4048 | (imm << 8) | imm)); |
| 4049 | break; |
| 4050 | } |
| 4051 | } else { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4052 | unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; |
| 4053 | unsigned rot = fieldFromInstruction(Val, 7, 5); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4054 | unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4055 | Inst.addOperand(MCOperand::createImm(imm)); |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4056 | } |
| 4057 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4058 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4059 | } |
| 4060 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4061 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4062 | DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 4063 | uint64_t Address, const void *Decoder) { |
Richard Barton | f1ef87d | 2012-06-06 09:12:53 +0000 | [diff] [blame] | 4064 | if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, |
Kevin Enderby | 40d4e47 | 2012-04-12 23:13:34 +0000 | [diff] [blame] | 4065 | true, 2, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4066 | Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4067 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4068 | } |
| 4069 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4070 | static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 4071 | uint64_t Address, |
| 4072 | const void *Decoder) { |
Kevin Enderby | 9142230 | 2012-05-03 22:41:56 +0000 | [diff] [blame] | 4073 | // Val is passed in as S:J1:J2:imm10:imm11 |
| 4074 | // Note no trailing zero after imm11. Also the J1 and J2 values are from |
| 4075 | // the encoded instruction. So here change to I1 and I2 values via: |
| 4076 | // I1 = NOT(J1 EOR S); |
| 4077 | // I2 = NOT(J2 EOR S); |
| 4078 | // and build the imm32 with one trailing zero as documented: |
NAKAMURA Takumi | 70c1aa0 | 2012-05-22 21:47:02 +0000 | [diff] [blame] | 4079 | // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); |
Kevin Enderby | 9142230 | 2012-05-03 22:41:56 +0000 | [diff] [blame] | 4080 | unsigned S = (Val >> 23) & 1; |
| 4081 | unsigned J1 = (Val >> 22) & 1; |
| 4082 | unsigned J2 = (Val >> 21) & 1; |
| 4083 | unsigned I1 = !(J1 ^ S); |
| 4084 | unsigned I2 = !(J2 ^ S); |
| 4085 | unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); |
| 4086 | int imm32 = SignExtend32<25>(tmp << 1); |
| 4087 | |
| 4088 | if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, |
Kevin Enderby | 6fbcd8d | 2012-02-23 18:18:17 +0000 | [diff] [blame] | 4089 | true, 4, Inst, Decoder)) |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4090 | Inst.addOperand(MCOperand::createImm(imm32)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4091 | return MCDisassembler::Success; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4092 | } |
| 4093 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4094 | static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, |
Owen Anderson | e008931 | 2011-08-09 23:25:42 +0000 | [diff] [blame] | 4095 | uint64_t Address, const void *Decoder) { |
Jiangning Liu | 288e1af | 2012-08-02 08:21:27 +0000 | [diff] [blame] | 4096 | if (Val & ~0xf) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4097 | return MCDisassembler::Fail; |
Owen Anderson | e008931 | 2011-08-09 23:25:42 +0000 | [diff] [blame] | 4098 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4099 | Inst.addOperand(MCOperand::createImm(Val)); |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4100 | return MCDisassembler::Success; |
Owen Anderson | e008931 | 2011-08-09 23:25:42 +0000 | [diff] [blame] | 4101 | } |
| 4102 | |
Amaury de la Vieuville | 43cb13a | 2013-06-10 14:17:08 +0000 | [diff] [blame] | 4103 | static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, |
| 4104 | uint64_t Address, const void *Decoder) { |
| 4105 | if (Val & ~0xf) |
| 4106 | return MCDisassembler::Fail; |
| 4107 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4108 | Inst.addOperand(MCOperand::createImm(Val)); |
Amaury de la Vieuville | 43cb13a | 2013-06-10 14:17:08 +0000 | [diff] [blame] | 4109 | return MCDisassembler::Success; |
| 4110 | } |
| 4111 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4112 | static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, |
Owen Anderson | 6066340 | 2011-08-11 20:21:46 +0000 | [diff] [blame] | 4113 | uint64_t Address, const void *Decoder) { |
Renato Golin | 92c816c | 2014-09-01 11:25:07 +0000 | [diff] [blame] | 4114 | DecodeStatus S = MCDisassembler::Success; |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 4115 | const FeatureBitset &FeatureBits = |
| 4116 | ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 4117 | |
| 4118 | if (FeatureBits[ARM::FeatureMClass]) { |
James Molloy | 137ce60 | 2014-08-01 12:42:11 +0000 | [diff] [blame] | 4119 | unsigned ValLow = Val & 0xff; |
| 4120 | |
| 4121 | // Validate the SYSm value first. |
| 4122 | switch (ValLow) { |
| 4123 | case 0: // apsr |
| 4124 | case 1: // iapsr |
| 4125 | case 2: // eapsr |
| 4126 | case 3: // xpsr |
| 4127 | case 5: // ipsr |
| 4128 | case 6: // epsr |
| 4129 | case 7: // iepsr |
| 4130 | case 8: // msp |
| 4131 | case 9: // psp |
| 4132 | case 16: // primask |
| 4133 | case 20: // control |
| 4134 | break; |
| 4135 | case 17: // basepri |
| 4136 | case 18: // basepri_max |
| 4137 | case 19: // faultmask |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 4138 | if (!(FeatureBits[ARM::HasV7Ops])) |
James Molloy | 137ce60 | 2014-08-01 12:42:11 +0000 | [diff] [blame] | 4139 | // Values basepri, basepri_max and faultmask are only valid for v7m. |
| 4140 | return MCDisassembler::Fail; |
| 4141 | break; |
Bradley Smith | f277c8a | 2016-01-25 11:25:36 +0000 | [diff] [blame] | 4142 | case 0x8a: // msplim_ns |
| 4143 | case 0x8b: // psplim_ns |
| 4144 | case 0x91: // basepri_ns |
| 4145 | case 0x92: // basepri_max_ns |
| 4146 | case 0x93: // faultmask_ns |
| 4147 | if (!(FeatureBits[ARM::HasV8MMainlineOps])) |
| 4148 | return MCDisassembler::Fail; |
Justin Bogner | cd1d5aa | 2016-08-17 20:30:52 +0000 | [diff] [blame] | 4149 | LLVM_FALLTHROUGH; |
Bradley Smith | f277c8a | 2016-01-25 11:25:36 +0000 | [diff] [blame] | 4150 | case 10: // msplim |
| 4151 | case 11: // psplim |
| 4152 | case 0x88: // msp_ns |
| 4153 | case 0x89: // psp_ns |
| 4154 | case 0x90: // primask_ns |
| 4155 | case 0x94: // control_ns |
| 4156 | case 0x98: // sp_ns |
| 4157 | if (!(FeatureBits[ARM::Feature8MSecExt])) |
| 4158 | return MCDisassembler::Fail; |
| 4159 | break; |
James Molloy | 137ce60 | 2014-08-01 12:42:11 +0000 | [diff] [blame] | 4160 | default: |
| 4161 | return MCDisassembler::Fail; |
| 4162 | } |
| 4163 | |
Renato Golin | 92c816c | 2014-09-01 11:25:07 +0000 | [diff] [blame] | 4164 | if (Inst.getOpcode() == ARM::t2MSR_M) { |
| 4165 | unsigned Mask = fieldFromInstruction(Val, 10, 2); |
Michael Kuperstein | db0712f | 2015-05-26 10:47:10 +0000 | [diff] [blame] | 4166 | if (!(FeatureBits[ARM::HasV7Ops])) { |
Renato Golin | 92c816c | 2014-09-01 11:25:07 +0000 | [diff] [blame] | 4167 | // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are |
| 4168 | // unpredictable. |
| 4169 | if (Mask != 2) |
| 4170 | S = MCDisassembler::SoftFail; |
| 4171 | } |
| 4172 | else { |
| 4173 | // The ARMv7-M architecture stores an additional 2-bit mask value in |
| 4174 | // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and |
| 4175 | // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if |
| 4176 | // the NZCVQ bits should be moved by the instruction. Bit mask{0} |
| 4177 | // indicates the move for the GE{3:0} bits, the mask{0} bit can be set |
| 4178 | // only if the processor includes the DSP extension. |
| 4179 | if (Mask == 0 || (Mask != 2 && ValLow > 3) || |
Artyom Skrobov | cf29644 | 2015-09-24 17:31:16 +0000 | [diff] [blame] | 4180 | (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) |
Renato Golin | 92c816c | 2014-09-01 11:25:07 +0000 | [diff] [blame] | 4181 | S = MCDisassembler::SoftFail; |
| 4182 | } |
James Molloy | 137ce60 | 2014-08-01 12:42:11 +0000 | [diff] [blame] | 4183 | } |
| 4184 | } else { |
| 4185 | // A/R class |
| 4186 | if (Val == 0) |
| 4187 | return MCDisassembler::Fail; |
| 4188 | } |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4189 | Inst.addOperand(MCOperand::createImm(Val)); |
Renato Golin | 92c816c | 2014-09-01 11:25:07 +0000 | [diff] [blame] | 4190 | return S; |
Owen Anderson | 6066340 | 2011-08-11 20:21:46 +0000 | [diff] [blame] | 4191 | } |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4192 | |
Tim Northover | ee843ef | 2014-08-15 10:47:12 +0000 | [diff] [blame] | 4193 | static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, |
| 4194 | uint64_t Address, const void *Decoder) { |
Tim Northover | ee843ef | 2014-08-15 10:47:12 +0000 | [diff] [blame] | 4195 | unsigned R = fieldFromInstruction(Val, 5, 1); |
| 4196 | unsigned SysM = fieldFromInstruction(Val, 0, 5); |
| 4197 | |
| 4198 | // The table of encodings for these banked registers comes from B9.2.3 of the |
| 4199 | // ARM ARM. There are patterns, but nothing regular enough to make this logic |
| 4200 | // neater. So by fiat, these values are UNPREDICTABLE: |
| 4201 | if (!R) { |
| 4202 | if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || |
| 4203 | SysM == 0x1a || SysM == 0x1b) |
| 4204 | return MCDisassembler::SoftFail; |
| 4205 | } else { |
| 4206 | if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && |
| 4207 | SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) |
| 4208 | return MCDisassembler::SoftFail; |
| 4209 | } |
| 4210 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4211 | Inst.addOperand(MCOperand::createImm(Val)); |
Tim Northover | ee843ef | 2014-08-15 10:47:12 +0000 | [diff] [blame] | 4212 | return MCDisassembler::Success; |
| 4213 | } |
| 4214 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4215 | static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, |
Jim Grosbach | d14b70d | 2011-08-17 21:58:18 +0000 | [diff] [blame] | 4216 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4217 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4218 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4219 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4220 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4221 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | c5798a3a5 | 2011-08-12 17:58:32 +0000 | [diff] [blame] | 4222 | |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 4223 | if (Rn == 0xF) |
| 4224 | S = MCDisassembler::SoftFail; |
Owen Anderson | c5798a3a5 | 2011-08-12 17:58:32 +0000 | [diff] [blame] | 4225 | |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 4226 | if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4227 | return MCDisassembler::Fail; |
| 4228 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4229 | return MCDisassembler::Fail; |
| 4230 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4231 | return MCDisassembler::Fail; |
Owen Anderson | c5798a3a5 | 2011-08-12 17:58:32 +0000 | [diff] [blame] | 4232 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4233 | return S; |
Owen Anderson | c5798a3a5 | 2011-08-12 17:58:32 +0000 | [diff] [blame] | 4234 | } |
| 4235 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4236 | static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 4237 | uint64_t Address, |
| 4238 | const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4239 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4240 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4241 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4242 | unsigned Rt = fieldFromInstruction(Insn, 0, 4); |
| 4243 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4244 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4245 | |
Tim Northover | 27ff504 | 2013-04-19 15:44:32 +0000 | [diff] [blame] | 4246 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4247 | return MCDisassembler::Fail; |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4248 | |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 4249 | if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) |
| 4250 | S = MCDisassembler::SoftFail; |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4251 | |
Amaury de la Vieuville | 53ff029 | 2013-06-11 08:03:20 +0000 | [diff] [blame] | 4252 | if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4253 | return MCDisassembler::Fail; |
| 4254 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4255 | return MCDisassembler::Fail; |
| 4256 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4257 | return MCDisassembler::Fail; |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4258 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4259 | return S; |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4260 | } |
| 4261 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4262 | static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4263 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4264 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4265 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4266 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4267 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4268 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 4269 | imm |= fieldFromInstruction(Insn, 16, 4) << 13; |
| 4270 | imm |= fieldFromInstruction(Insn, 23, 1) << 12; |
| 4271 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4272 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4273 | if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4274 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4275 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 4276 | return MCDisassembler::Fail; |
| 4277 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4278 | return MCDisassembler::Fail; |
| 4279 | if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) |
| 4280 | return MCDisassembler::Fail; |
| 4281 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4282 | return MCDisassembler::Fail; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4283 | |
| 4284 | return S; |
| 4285 | } |
| 4286 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4287 | static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4288 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4289 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4290 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4291 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4292 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4293 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 4294 | imm |= fieldFromInstruction(Insn, 16, 4) << 13; |
| 4295 | imm |= fieldFromInstruction(Insn, 23, 1) << 12; |
| 4296 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 4297 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4298 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4299 | if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; |
| 4300 | if (Rm == 0xF) S = MCDisassembler::SoftFail; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4301 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4302 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 4303 | return MCDisassembler::Fail; |
| 4304 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4305 | return MCDisassembler::Fail; |
| 4306 | if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) |
| 4307 | return MCDisassembler::Fail; |
| 4308 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4309 | return MCDisassembler::Fail; |
Owen Anderson | 16d33f3 | 2011-08-26 20:43:14 +0000 | [diff] [blame] | 4310 | |
| 4311 | return S; |
| 4312 | } |
| 4313 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4314 | static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4315 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4316 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4317 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4318 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4319 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4320 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 4321 | imm |= fieldFromInstruction(Insn, 16, 4) << 13; |
| 4322 | imm |= fieldFromInstruction(Insn, 23, 1) << 12; |
| 4323 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | b685c9f | 2011-08-11 21:34:58 +0000 | [diff] [blame] | 4324 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4325 | if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4326 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4327 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4328 | return MCDisassembler::Fail; |
| 4329 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 4330 | return MCDisassembler::Fail; |
| 4331 | if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) |
| 4332 | return MCDisassembler::Fail; |
| 4333 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4334 | return MCDisassembler::Fail; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4335 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4336 | return S; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4337 | } |
| 4338 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4339 | static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4340 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4341 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4342 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4343 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4344 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4345 | unsigned imm = fieldFromInstruction(Insn, 0, 12); |
| 4346 | imm |= fieldFromInstruction(Insn, 16, 4) << 13; |
| 4347 | imm |= fieldFromInstruction(Insn, 23, 1) << 12; |
| 4348 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4349 | |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4350 | if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4351 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4352 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4353 | return MCDisassembler::Fail; |
| 4354 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 4355 | return MCDisassembler::Fail; |
| 4356 | if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) |
| 4357 | return MCDisassembler::Fail; |
| 4358 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4359 | return MCDisassembler::Fail; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4360 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4361 | return S; |
Owen Anderson | 3987a61 | 2011-08-12 18:12:39 +0000 | [diff] [blame] | 4362 | } |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4363 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4364 | static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4365 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4366 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4367 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4368 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4369 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4370 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4371 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4372 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4373 | |
| 4374 | unsigned align = 0; |
| 4375 | unsigned index = 0; |
| 4376 | switch (size) { |
| 4377 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4378 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4379 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4380 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4381 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4382 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4383 | break; |
| 4384 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4385 | if (fieldFromInstruction(Insn, 5, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4386 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4387 | index = fieldFromInstruction(Insn, 6, 2); |
| 4388 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4389 | align = 2; |
| 4390 | break; |
| 4391 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4392 | if (fieldFromInstruction(Insn, 6, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4393 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4394 | index = fieldFromInstruction(Insn, 7, 1); |
Tim Northover | fb3cdd8 | 2012-09-06 15:17:49 +0000 | [diff] [blame] | 4395 | |
| 4396 | switch (fieldFromInstruction(Insn, 4, 2)) { |
| 4397 | case 0 : |
| 4398 | align = 0; break; |
| 4399 | case 3: |
| 4400 | align = 4; break; |
| 4401 | default: |
| 4402 | return MCDisassembler::Fail; |
| 4403 | } |
| 4404 | break; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4405 | } |
| 4406 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4407 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4408 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4409 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4410 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4411 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4412 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4413 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4414 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4415 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4416 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4417 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4418 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4419 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4420 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4421 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4422 | } |
| 4423 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4424 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4425 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4426 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4427 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4428 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4429 | } |
| 4430 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4431 | static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4432 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4433 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4434 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4435 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4436 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4437 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4438 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4439 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4440 | |
| 4441 | unsigned align = 0; |
| 4442 | unsigned index = 0; |
| 4443 | switch (size) { |
| 4444 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4445 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4446 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4447 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4448 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4449 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4450 | break; |
| 4451 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4452 | if (fieldFromInstruction(Insn, 5, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4453 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4454 | index = fieldFromInstruction(Insn, 6, 2); |
| 4455 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4456 | align = 2; |
| 4457 | break; |
| 4458 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4459 | if (fieldFromInstruction(Insn, 6, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4460 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4461 | index = fieldFromInstruction(Insn, 7, 1); |
Tim Northover | fb3cdd8 | 2012-09-06 15:17:49 +0000 | [diff] [blame] | 4462 | |
| 4463 | switch (fieldFromInstruction(Insn, 4, 2)) { |
| 4464 | case 0: |
| 4465 | align = 0; break; |
| 4466 | case 3: |
| 4467 | align = 4; break; |
| 4468 | default: |
| 4469 | return MCDisassembler::Fail; |
| 4470 | } |
| 4471 | break; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4472 | } |
| 4473 | |
| 4474 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4475 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4476 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4477 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4478 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4479 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4480 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4481 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4482 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4483 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4484 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4485 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4486 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4487 | } |
| 4488 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4489 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4490 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4491 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4492 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4493 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4494 | } |
| 4495 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4496 | static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4497 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4498 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4499 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4500 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4501 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4502 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4503 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4504 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4505 | |
| 4506 | unsigned align = 0; |
| 4507 | unsigned index = 0; |
| 4508 | unsigned inc = 1; |
| 4509 | switch (size) { |
| 4510 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4511 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4512 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4513 | index = fieldFromInstruction(Insn, 5, 3); |
| 4514 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4515 | align = 2; |
| 4516 | break; |
| 4517 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4518 | index = fieldFromInstruction(Insn, 6, 2); |
| 4519 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4520 | align = 4; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4521 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4522 | inc = 2; |
| 4523 | break; |
| 4524 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4525 | if (fieldFromInstruction(Insn, 5, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4526 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4527 | index = fieldFromInstruction(Insn, 7, 1); |
| 4528 | if (fieldFromInstruction(Insn, 4, 1) != 0) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4529 | align = 8; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4530 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4531 | inc = 2; |
| 4532 | break; |
| 4533 | } |
| 4534 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4535 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4536 | return MCDisassembler::Fail; |
| 4537 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4538 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4539 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4540 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4541 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4542 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4543 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4544 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4545 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4546 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4547 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4548 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4549 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4550 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4551 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4552 | } |
| 4553 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4554 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4555 | return MCDisassembler::Fail; |
| 4556 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4557 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4558 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4559 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4560 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4561 | } |
| 4562 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4563 | static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4564 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4565 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4566 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4567 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4568 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4569 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4570 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4571 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4572 | |
| 4573 | unsigned align = 0; |
| 4574 | unsigned index = 0; |
| 4575 | unsigned inc = 1; |
| 4576 | switch (size) { |
| 4577 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4578 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4579 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4580 | index = fieldFromInstruction(Insn, 5, 3); |
| 4581 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4582 | align = 2; |
| 4583 | break; |
| 4584 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4585 | index = fieldFromInstruction(Insn, 6, 2); |
| 4586 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4587 | align = 4; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4588 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4589 | inc = 2; |
| 4590 | break; |
| 4591 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4592 | if (fieldFromInstruction(Insn, 5, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4593 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4594 | index = fieldFromInstruction(Insn, 7, 1); |
| 4595 | if (fieldFromInstruction(Insn, 4, 1) != 0) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4596 | align = 8; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4597 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4598 | inc = 2; |
| 4599 | break; |
| 4600 | } |
| 4601 | |
| 4602 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4603 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4604 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4605 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4606 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4607 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4608 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4609 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4610 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4611 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4612 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4613 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4614 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4615 | } |
| 4616 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4617 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4618 | return MCDisassembler::Fail; |
| 4619 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4620 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4621 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4622 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4623 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4624 | } |
| 4625 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4626 | static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4627 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4628 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4629 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4630 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4631 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4632 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4633 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4634 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4635 | |
| 4636 | unsigned align = 0; |
| 4637 | unsigned index = 0; |
| 4638 | unsigned inc = 1; |
| 4639 | switch (size) { |
| 4640 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4641 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4642 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4643 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4644 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4645 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4646 | break; |
| 4647 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4648 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4649 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4650 | index = fieldFromInstruction(Insn, 6, 2); |
| 4651 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4652 | inc = 2; |
| 4653 | break; |
| 4654 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4655 | if (fieldFromInstruction(Insn, 4, 2)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4656 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4657 | index = fieldFromInstruction(Insn, 7, 1); |
| 4658 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4659 | inc = 2; |
| 4660 | break; |
| 4661 | } |
| 4662 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4663 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4664 | return MCDisassembler::Fail; |
| 4665 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4666 | return MCDisassembler::Fail; |
| 4667 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4668 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4669 | |
| 4670 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4671 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4672 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4673 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4674 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4675 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4676 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 2fa06a7 | 2011-08-30 22:58:27 +0000 | [diff] [blame] | 4677 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4678 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4679 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4680 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4681 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4682 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4683 | } |
| 4684 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4685 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4686 | return MCDisassembler::Fail; |
| 4687 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4688 | return MCDisassembler::Fail; |
| 4689 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4690 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4691 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4692 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4693 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4694 | } |
| 4695 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4696 | static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4697 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4698 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4699 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4700 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4701 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4702 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4703 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4704 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4705 | |
| 4706 | unsigned align = 0; |
| 4707 | unsigned index = 0; |
| 4708 | unsigned inc = 1; |
| 4709 | switch (size) { |
| 4710 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4711 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4712 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4713 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4714 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4715 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4716 | break; |
| 4717 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4718 | if (fieldFromInstruction(Insn, 4, 1)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4719 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4720 | index = fieldFromInstruction(Insn, 6, 2); |
| 4721 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4722 | inc = 2; |
| 4723 | break; |
| 4724 | case 2: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4725 | if (fieldFromInstruction(Insn, 4, 2)) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4726 | return MCDisassembler::Fail; // UNDEFINED |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4727 | index = fieldFromInstruction(Insn, 7, 1); |
| 4728 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4729 | inc = 2; |
| 4730 | break; |
| 4731 | } |
| 4732 | |
| 4733 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4734 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4735 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4736 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4737 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4738 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4739 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4740 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4741 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4742 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4743 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4744 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4745 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4746 | } |
| 4747 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4748 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4749 | return MCDisassembler::Fail; |
| 4750 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4751 | return MCDisassembler::Fail; |
| 4752 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4753 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4754 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4755 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4756 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4757 | } |
| 4758 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4759 | static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4760 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4761 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4762 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4763 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4764 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4765 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4766 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4767 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4768 | |
| 4769 | unsigned align = 0; |
| 4770 | unsigned index = 0; |
| 4771 | unsigned inc = 1; |
| 4772 | switch (size) { |
| 4773 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4774 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4775 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4776 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4777 | align = 4; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4778 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4779 | break; |
| 4780 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4781 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4782 | align = 8; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4783 | index = fieldFromInstruction(Insn, 6, 2); |
| 4784 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4785 | inc = 2; |
| 4786 | break; |
| 4787 | case 2: |
Tim Northover | fb3cdd8 | 2012-09-06 15:17:49 +0000 | [diff] [blame] | 4788 | switch (fieldFromInstruction(Insn, 4, 2)) { |
| 4789 | case 0: |
| 4790 | align = 0; break; |
| 4791 | case 3: |
| 4792 | return MCDisassembler::Fail; |
| 4793 | default: |
| 4794 | align = 4 << fieldFromInstruction(Insn, 4, 2); break; |
| 4795 | } |
| 4796 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4797 | index = fieldFromInstruction(Insn, 7, 1); |
| 4798 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4799 | inc = 2; |
| 4800 | break; |
| 4801 | } |
| 4802 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4803 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4804 | return MCDisassembler::Fail; |
| 4805 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4806 | return MCDisassembler::Fail; |
| 4807 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4808 | return MCDisassembler::Fail; |
| 4809 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) |
| 4810 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4811 | |
| 4812 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4813 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4814 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4815 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4816 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4817 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4818 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4819 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4820 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4821 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4822 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4823 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4824 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4825 | } |
| 4826 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4827 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4828 | return MCDisassembler::Fail; |
| 4829 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4830 | return MCDisassembler::Fail; |
| 4831 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4832 | return MCDisassembler::Fail; |
| 4833 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) |
| 4834 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4835 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4836 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4837 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4838 | } |
| 4839 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4840 | static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4841 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4842 | DecodeStatus S = MCDisassembler::Success; |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4843 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4844 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4845 | unsigned Rm = fieldFromInstruction(Insn, 0, 4); |
| 4846 | unsigned Rd = fieldFromInstruction(Insn, 12, 4); |
| 4847 | Rd |= fieldFromInstruction(Insn, 22, 1) << 4; |
| 4848 | unsigned size = fieldFromInstruction(Insn, 10, 2); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4849 | |
| 4850 | unsigned align = 0; |
| 4851 | unsigned index = 0; |
| 4852 | unsigned inc = 1; |
| 4853 | switch (size) { |
| 4854 | default: |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4855 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4856 | case 0: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4857 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4858 | align = 4; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4859 | index = fieldFromInstruction(Insn, 5, 3); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4860 | break; |
| 4861 | case 1: |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4862 | if (fieldFromInstruction(Insn, 4, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4863 | align = 8; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4864 | index = fieldFromInstruction(Insn, 6, 2); |
| 4865 | if (fieldFromInstruction(Insn, 5, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4866 | inc = 2; |
| 4867 | break; |
| 4868 | case 2: |
Tim Northover | fb3cdd8 | 2012-09-06 15:17:49 +0000 | [diff] [blame] | 4869 | switch (fieldFromInstruction(Insn, 4, 2)) { |
| 4870 | case 0: |
| 4871 | align = 0; break; |
| 4872 | case 3: |
| 4873 | return MCDisassembler::Fail; |
| 4874 | default: |
| 4875 | align = 4 << fieldFromInstruction(Insn, 4, 2); break; |
| 4876 | } |
| 4877 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4878 | index = fieldFromInstruction(Insn, 7, 1); |
| 4879 | if (fieldFromInstruction(Insn, 6, 1)) |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4880 | inc = 2; |
| 4881 | break; |
| 4882 | } |
| 4883 | |
| 4884 | if (Rm != 0xF) { // Writeback |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4885 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4886 | return MCDisassembler::Fail; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4887 | } |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4888 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 4889 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4890 | Inst.addOperand(MCOperand::createImm(align)); |
Owen Anderson | 721c370 | 2011-08-22 18:42:13 +0000 | [diff] [blame] | 4891 | if (Rm != 0xF) { |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4892 | if (Rm != 0xD) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4893 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) |
| 4894 | return MCDisassembler::Fail; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4895 | } else |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4896 | Inst.addOperand(MCOperand::createReg(0)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4897 | } |
| 4898 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4899 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) |
| 4900 | return MCDisassembler::Fail; |
| 4901 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) |
| 4902 | return MCDisassembler::Fail; |
| 4903 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) |
| 4904 | return MCDisassembler::Fail; |
| 4905 | if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) |
| 4906 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4907 | Inst.addOperand(MCOperand::createImm(index)); |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4908 | |
Owen Anderson | a4043c4 | 2011-08-17 17:44:15 +0000 | [diff] [blame] | 4909 | return S; |
Owen Anderson | b9d82f4 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 4910 | } |
| 4911 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4912 | static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4913 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4914 | DecodeStatus S = MCDisassembler::Success; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4915 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4916 | unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); |
| 4917 | unsigned Rm = fieldFromInstruction(Insn, 5, 1); |
| 4918 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 4919 | Rm |= fieldFromInstruction(Insn, 0, 4) << 1; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4920 | |
| 4921 | if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4922 | S = MCDisassembler::SoftFail; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4923 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4924 | if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) |
| 4925 | return MCDisassembler::Fail; |
| 4926 | if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) |
| 4927 | return MCDisassembler::Fail; |
| 4928 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) |
| 4929 | return MCDisassembler::Fail; |
| 4930 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) |
| 4931 | return MCDisassembler::Fail; |
| 4932 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4933 | return MCDisassembler::Fail; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4934 | |
| 4935 | return S; |
| 4936 | } |
| 4937 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4938 | static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4939 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4940 | DecodeStatus S = MCDisassembler::Success; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4941 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4942 | unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); |
| 4943 | unsigned Rm = fieldFromInstruction(Insn, 5, 1); |
| 4944 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
| 4945 | Rm |= fieldFromInstruction(Insn, 0, 4) << 1; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4946 | |
| 4947 | if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4948 | S = MCDisassembler::SoftFail; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4949 | |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4950 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) |
| 4951 | return MCDisassembler::Fail; |
| 4952 | if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) |
| 4953 | return MCDisassembler::Fail; |
| 4954 | if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) |
| 4955 | return MCDisassembler::Fail; |
| 4956 | if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) |
| 4957 | return MCDisassembler::Fail; |
| 4958 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 4959 | return MCDisassembler::Fail; |
Owen Anderson | df698b0 | 2011-08-22 20:27:12 +0000 | [diff] [blame] | 4960 | |
| 4961 | return S; |
| 4962 | } |
Owen Anderson | eb1367b | 2011-08-22 23:44:04 +0000 | [diff] [blame] | 4963 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4964 | static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, |
Owen Anderson | 2fa06a7 | 2011-08-30 22:58:27 +0000 | [diff] [blame] | 4965 | uint64_t Address, const void *Decoder) { |
Owen Anderson | 03aadae | 2011-09-01 23:23:50 +0000 | [diff] [blame] | 4966 | DecodeStatus S = MCDisassembler::Success; |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4967 | unsigned pred = fieldFromInstruction(Insn, 4, 4); |
| 4968 | unsigned mask = fieldFromInstruction(Insn, 0, 4); |
Owen Anderson | 2fa06a7 | 2011-08-30 22:58:27 +0000 | [diff] [blame] | 4969 | |
| 4970 | if (pred == 0xF) { |
| 4971 | pred = 0xE; |
James Molloy | db4ce60 | 2011-09-01 18:02:14 +0000 | [diff] [blame] | 4972 | S = MCDisassembler::SoftFail; |
Owen Anderson | 5230041 | 2011-08-24 17:21:43 +0000 | [diff] [blame] | 4973 | } |
| 4974 | |
Amaury de la Vieuville | 2f0ac8d | 2013-06-24 09:11:45 +0000 | [diff] [blame] | 4975 | if (mask == 0x0) |
| 4976 | return MCDisassembler::Fail; |
Owen Anderson | 2fa06a7 | 2011-08-30 22:58:27 +0000 | [diff] [blame] | 4977 | |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 4978 | Inst.addOperand(MCOperand::createImm(pred)); |
| 4979 | Inst.addOperand(MCOperand::createImm(mask)); |
Owen Anderson | 37612a3 | 2011-08-24 22:40:22 +0000 | [diff] [blame] | 4980 | return S; |
| 4981 | } |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 4982 | |
| 4983 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 4984 | DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 4985 | uint64_t Address, const void *Decoder) { |
| 4986 | DecodeStatus S = MCDisassembler::Success; |
| 4987 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 4988 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 4989 | unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); |
| 4990 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 4991 | unsigned addr = fieldFromInstruction(Insn, 0, 8); |
| 4992 | unsigned W = fieldFromInstruction(Insn, 21, 1); |
| 4993 | unsigned U = fieldFromInstruction(Insn, 23, 1); |
| 4994 | unsigned P = fieldFromInstruction(Insn, 24, 1); |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 4995 | bool writeback = (W == 1) | (P == 0); |
| 4996 | |
| 4997 | addr |= (U << 8) | (Rn << 9); |
| 4998 | |
| 4999 | if (writeback && (Rn == Rt || Rn == Rt2)) |
| 5000 | Check(S, MCDisassembler::SoftFail); |
| 5001 | if (Rt == Rt2) |
| 5002 | Check(S, MCDisassembler::SoftFail); |
| 5003 | |
| 5004 | // Rt |
| 5005 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 5006 | return MCDisassembler::Fail; |
| 5007 | // Rt2 |
| 5008 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) |
| 5009 | return MCDisassembler::Fail; |
| 5010 | // Writeback operand |
| 5011 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 5012 | return MCDisassembler::Fail; |
| 5013 | // addr |
| 5014 | if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) |
| 5015 | return MCDisassembler::Fail; |
| 5016 | |
| 5017 | return S; |
| 5018 | } |
| 5019 | |
| 5020 | static DecodeStatus |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5021 | DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 5022 | uint64_t Address, const void *Decoder) { |
| 5023 | DecodeStatus S = MCDisassembler::Success; |
| 5024 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5025 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 5026 | unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); |
| 5027 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 5028 | unsigned addr = fieldFromInstruction(Insn, 0, 8); |
| 5029 | unsigned W = fieldFromInstruction(Insn, 21, 1); |
| 5030 | unsigned U = fieldFromInstruction(Insn, 23, 1); |
| 5031 | unsigned P = fieldFromInstruction(Insn, 24, 1); |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 5032 | bool writeback = (W == 1) | (P == 0); |
| 5033 | |
| 5034 | addr |= (U << 8) | (Rn << 9); |
| 5035 | |
| 5036 | if (writeback && (Rn == Rt || Rn == Rt2)) |
| 5037 | Check(S, MCDisassembler::SoftFail); |
| 5038 | |
| 5039 | // Writeback operand |
| 5040 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) |
| 5041 | return MCDisassembler::Fail; |
| 5042 | // Rt |
| 5043 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) |
| 5044 | return MCDisassembler::Fail; |
| 5045 | // Rt2 |
| 5046 | if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) |
| 5047 | return MCDisassembler::Fail; |
| 5048 | // addr |
| 5049 | if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) |
| 5050 | return MCDisassembler::Fail; |
| 5051 | |
| 5052 | return S; |
| 5053 | } |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 5054 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5055 | static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 5056 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5057 | unsigned sign1 = fieldFromInstruction(Insn, 21, 1); |
| 5058 | unsigned sign2 = fieldFromInstruction(Insn, 23, 1); |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 5059 | if (sign1 != sign2) return MCDisassembler::Fail; |
| 5060 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5061 | unsigned Val = fieldFromInstruction(Insn, 0, 8); |
| 5062 | Val |= fieldFromInstruction(Insn, 12, 3) << 8; |
| 5063 | Val |= fieldFromInstruction(Insn, 26, 1) << 11; |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 5064 | Val |= sign1 << 12; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5065 | Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); |
Owen Anderson | 5bfb0e0 | 2011-09-09 22:24:36 +0000 | [diff] [blame] | 5066 | |
| 5067 | return MCDisassembler::Success; |
| 5068 | } |
| 5069 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5070 | static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, |
Owen Anderson | f01e2de | 2011-09-26 21:06:22 +0000 | [diff] [blame] | 5071 | uint64_t Address, |
| 5072 | const void *Decoder) { |
| 5073 | DecodeStatus S = MCDisassembler::Success; |
| 5074 | |
| 5075 | // Shift of "asr #32" is not allowed in Thumb2 mode. |
Bradley Smith | 3131e85 | 2015-01-19 16:37:17 +0000 | [diff] [blame] | 5076 | if (Val == 0x20) S = MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5077 | Inst.addOperand(MCOperand::createImm(Val)); |
Owen Anderson | f01e2de | 2011-09-26 21:06:22 +0000 | [diff] [blame] | 5078 | return S; |
| 5079 | } |
| 5080 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5081 | static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 5082 | uint64_t Address, const void *Decoder) { |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5083 | unsigned Rt = fieldFromInstruction(Insn, 12, 4); |
| 5084 | unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); |
| 5085 | unsigned Rn = fieldFromInstruction(Insn, 16, 4); |
| 5086 | unsigned pred = fieldFromInstruction(Insn, 28, 4); |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 5087 | |
| 5088 | if (pred == 0xF) |
| 5089 | return DecodeCPSInstruction(Inst, Insn, Address, Decoder); |
| 5090 | |
| 5091 | DecodeStatus S = MCDisassembler::Success; |
Silviu Baranga | ca45af9 | 2012-04-18 14:18:57 +0000 | [diff] [blame] | 5092 | |
| 5093 | if (Rt == Rn || Rn == Rt2) |
| 5094 | S = MCDisassembler::SoftFail; |
| 5095 | |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 5096 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
| 5097 | return MCDisassembler::Fail; |
| 5098 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
| 5099 | return MCDisassembler::Fail; |
| 5100 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
| 5101 | return MCDisassembler::Fail; |
| 5102 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 5103 | return MCDisassembler::Fail; |
| 5104 | |
| 5105 | return S; |
| 5106 | } |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5107 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5108 | static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5109 | uint64_t Address, const void *Decoder) { |
Oliver Stannard | 2de8c16 | 2015-12-16 12:37:39 +0000 | [diff] [blame] | 5110 | const FeatureBitset &featureBits = |
| 5111 | ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 5112 | bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; |
| 5113 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5114 | unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); |
| 5115 | Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); |
| 5116 | unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); |
| 5117 | Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); |
| 5118 | unsigned imm = fieldFromInstruction(Insn, 16, 6); |
| 5119 | unsigned cmode = fieldFromInstruction(Insn, 8, 4); |
Amaury de la Vieuville | f4ec0c85 | 2013-06-08 13:54:05 +0000 | [diff] [blame] | 5120 | unsigned op = fieldFromInstruction(Insn, 5, 1); |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5121 | |
| 5122 | DecodeStatus S = MCDisassembler::Success; |
| 5123 | |
Oliver Stannard | 2de8c16 | 2015-12-16 12:37:39 +0000 | [diff] [blame] | 5124 | // If the top 3 bits of imm are clear, this is a VMOV (immediate) |
| 5125 | if (!(imm & 0x38)) { |
| 5126 | if (cmode == 0xF) { |
| 5127 | if (op == 1) return MCDisassembler::Fail; |
| 5128 | Inst.setOpcode(ARM::VMOVv2f32); |
| 5129 | } |
| 5130 | if (hasFullFP16) { |
| 5131 | if (cmode == 0xE) { |
| 5132 | if (op == 1) { |
| 5133 | Inst.setOpcode(ARM::VMOVv1i64); |
| 5134 | } else { |
| 5135 | Inst.setOpcode(ARM::VMOVv8i8); |
| 5136 | } |
| 5137 | } |
| 5138 | if (cmode == 0xD) { |
| 5139 | if (op == 1) { |
| 5140 | Inst.setOpcode(ARM::VMVNv2i32); |
| 5141 | } else { |
| 5142 | Inst.setOpcode(ARM::VMOVv2i32); |
| 5143 | } |
| 5144 | } |
| 5145 | if (cmode == 0xC) { |
| 5146 | if (op == 1) { |
| 5147 | Inst.setOpcode(ARM::VMVNv2i32); |
| 5148 | } else { |
| 5149 | Inst.setOpcode(ARM::VMOVv2i32); |
| 5150 | } |
| 5151 | } |
| 5152 | } |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5153 | return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); |
| 5154 | } |
| 5155 | |
Amaury de la Vieuville | ea7bb57 | 2013-06-08 13:29:11 +0000 | [diff] [blame] | 5156 | if (!(imm & 0x20)) return MCDisassembler::Fail; |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5157 | |
| 5158 | if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) |
| 5159 | return MCDisassembler::Fail; |
| 5160 | if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) |
| 5161 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5162 | Inst.addOperand(MCOperand::createImm(64 - imm)); |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5163 | |
| 5164 | return S; |
| 5165 | } |
| 5166 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5167 | static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5168 | uint64_t Address, const void *Decoder) { |
Oliver Stannard | 2de8c16 | 2015-12-16 12:37:39 +0000 | [diff] [blame] | 5169 | const FeatureBitset &featureBits = |
| 5170 | ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 5171 | bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; |
| 5172 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5173 | unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); |
| 5174 | Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); |
| 5175 | unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); |
| 5176 | Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); |
| 5177 | unsigned imm = fieldFromInstruction(Insn, 16, 6); |
| 5178 | unsigned cmode = fieldFromInstruction(Insn, 8, 4); |
Amaury de la Vieuville | f4ec0c85 | 2013-06-08 13:54:05 +0000 | [diff] [blame] | 5179 | unsigned op = fieldFromInstruction(Insn, 5, 1); |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5180 | |
| 5181 | DecodeStatus S = MCDisassembler::Success; |
| 5182 | |
Oliver Stannard | 2de8c16 | 2015-12-16 12:37:39 +0000 | [diff] [blame] | 5183 | // If the top 3 bits of imm are clear, this is a VMOV (immediate) |
| 5184 | if (!(imm & 0x38)) { |
| 5185 | if (cmode == 0xF) { |
| 5186 | if (op == 1) return MCDisassembler::Fail; |
| 5187 | Inst.setOpcode(ARM::VMOVv4f32); |
| 5188 | } |
| 5189 | if (hasFullFP16) { |
| 5190 | if (cmode == 0xE) { |
| 5191 | if (op == 1) { |
| 5192 | Inst.setOpcode(ARM::VMOVv2i64); |
| 5193 | } else { |
| 5194 | Inst.setOpcode(ARM::VMOVv16i8); |
| 5195 | } |
| 5196 | } |
| 5197 | if (cmode == 0xD) { |
| 5198 | if (op == 1) { |
| 5199 | Inst.setOpcode(ARM::VMVNv4i32); |
| 5200 | } else { |
| 5201 | Inst.setOpcode(ARM::VMOVv4i32); |
| 5202 | } |
| 5203 | } |
| 5204 | if (cmode == 0xC) { |
| 5205 | if (op == 1) { |
| 5206 | Inst.setOpcode(ARM::VMVNv4i32); |
| 5207 | } else { |
| 5208 | Inst.setOpcode(ARM::VMOVv4i32); |
| 5209 | } |
| 5210 | } |
| 5211 | } |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5212 | return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); |
| 5213 | } |
| 5214 | |
Amaury de la Vieuville | ea7bb57 | 2013-06-08 13:29:11 +0000 | [diff] [blame] | 5215 | if (!(imm & 0x20)) return MCDisassembler::Fail; |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5216 | |
| 5217 | if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) |
| 5218 | return MCDisassembler::Fail; |
| 5219 | if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) |
| 5220 | return MCDisassembler::Fail; |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5221 | Inst.addOperand(MCOperand::createImm(64 - imm)); |
Owen Anderson | 0ac9058 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5222 | |
| 5223 | return S; |
| 5224 | } |
Silviu Baranga | d213f21 | 2012-03-22 13:24:43 +0000 | [diff] [blame] | 5225 | |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 5226 | static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, |
| 5227 | unsigned Insn, |
| 5228 | uint64_t Address, |
| 5229 | const void *Decoder) { |
| 5230 | unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); |
| 5231 | Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); |
| 5232 | unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); |
| 5233 | Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); |
| 5234 | unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); |
| 5235 | Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); |
| 5236 | unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); |
| 5237 | unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); |
| 5238 | |
| 5239 | DecodeStatus S = MCDisassembler::Success; |
| 5240 | |
| 5241 | auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; |
| 5242 | |
| 5243 | if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) |
| 5244 | return MCDisassembler::Fail; |
| 5245 | if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) |
| 5246 | return MCDisassembler::Fail; |
| 5247 | if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) |
| 5248 | return MCDisassembler::Fail; |
| 5249 | if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) |
| 5250 | return MCDisassembler::Fail; |
| 5251 | // The lane index does not have any bits in the encoding, because it can only |
| 5252 | // be 0. |
| 5253 | Inst.addOperand(MCOperand::createImm(0)); |
| 5254 | Inst.addOperand(MCOperand::createImm(rotate)); |
| 5255 | |
| 5256 | return S; |
| 5257 | } |
| 5258 | |
Craig Topper | f6e7e12 | 2012-03-27 07:21:54 +0000 | [diff] [blame] | 5259 | static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, |
Silviu Baranga | d213f21 | 2012-03-22 13:24:43 +0000 | [diff] [blame] | 5260 | uint64_t Address, const void *Decoder) { |
| 5261 | DecodeStatus S = MCDisassembler::Success; |
| 5262 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5263 | unsigned Rn = fieldFromInstruction(Val, 16, 4); |
| 5264 | unsigned Rt = fieldFromInstruction(Val, 12, 4); |
| 5265 | unsigned Rm = fieldFromInstruction(Val, 0, 4); |
| 5266 | Rm |= (fieldFromInstruction(Val, 23, 1) << 4); |
| 5267 | unsigned Cond = fieldFromInstruction(Val, 28, 4); |
Vinicius Tinti | 67cf33d | 2015-11-20 23:20:12 +0000 | [diff] [blame] | 5268 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5269 | if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) |
Silviu Baranga | d213f21 | 2012-03-22 13:24:43 +0000 | [diff] [blame] | 5270 | S = MCDisassembler::SoftFail; |
| 5271 | |
| 5272 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
| 5273 | return MCDisassembler::Fail; |
| 5274 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) |
| 5275 | return MCDisassembler::Fail; |
| 5276 | if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) |
| 5277 | return MCDisassembler::Fail; |
| 5278 | if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) |
| 5279 | return MCDisassembler::Fail; |
| 5280 | if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) |
| 5281 | return MCDisassembler::Fail; |
| 5282 | |
| 5283 | return S; |
| 5284 | } |
| 5285 | |
Eugene Zelenko | e79c077 | 2017-01-27 23:58:02 +0000 | [diff] [blame] | 5286 | static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, |
Ranjeet Singh | 39d2d09 | 2016-06-17 00:52:41 +0000 | [diff] [blame] | 5287 | uint64_t Address, const void *Decoder) { |
Silviu Baranga | 41f1fcd | 2012-04-18 13:12:50 +0000 | [diff] [blame] | 5288 | DecodeStatus S = MCDisassembler::Success; |
| 5289 | |
Jim Grosbach | ecaef49 | 2012-08-14 19:06:05 +0000 | [diff] [blame] | 5290 | unsigned CRm = fieldFromInstruction(Val, 0, 4); |
| 5291 | unsigned opc1 = fieldFromInstruction(Val, 4, 4); |
| 5292 | unsigned cop = fieldFromInstruction(Val, 8, 4); |
| 5293 | unsigned Rt = fieldFromInstruction(Val, 12, 4); |
| 5294 | unsigned Rt2 = fieldFromInstruction(Val, 16, 4); |
Silviu Baranga | 41f1fcd | 2012-04-18 13:12:50 +0000 | [diff] [blame] | 5295 | |
| 5296 | if ((cop & ~0x1) == 0xa) |
| 5297 | return MCDisassembler::Fail; |
| 5298 | |
| 5299 | if (Rt == Rt2) |
| 5300 | S = MCDisassembler::SoftFail; |
| 5301 | |
Ranjeet Singh | 39d2d09 | 2016-06-17 00:52:41 +0000 | [diff] [blame] | 5302 | // We have to check if the instruction is MRRC2 |
| 5303 | // or MCRR2 when constructing the operands for |
| 5304 | // Inst. Reason is because MRRC2 stores to two |
| 5305 | // registers so it's tablegen desc has has two |
| 5306 | // outputs whereas MCRR doesn't store to any |
| 5307 | // registers so all of it's operands are listed |
| 5308 | // as inputs, therefore the operand order for |
| 5309 | // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] |
| 5310 | // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] |
| 5311 | |
| 5312 | if (Inst.getOpcode() == ARM::MRRC2) { |
| 5313 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
| 5314 | return MCDisassembler::Fail; |
| 5315 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
| 5316 | return MCDisassembler::Fail; |
| 5317 | } |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5318 | Inst.addOperand(MCOperand::createImm(cop)); |
| 5319 | Inst.addOperand(MCOperand::createImm(opc1)); |
Ranjeet Singh | 39d2d09 | 2016-06-17 00:52:41 +0000 | [diff] [blame] | 5320 | if (Inst.getOpcode() == ARM::MCRR2) { |
| 5321 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) |
| 5322 | return MCDisassembler::Fail; |
| 5323 | if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) |
| 5324 | return MCDisassembler::Fail; |
| 5325 | } |
Jim Grosbach | e9119e4 | 2015-05-13 18:37:00 +0000 | [diff] [blame] | 5326 | Inst.addOperand(MCOperand::createImm(CRm)); |
Silviu Baranga | 41f1fcd | 2012-04-18 13:12:50 +0000 | [diff] [blame] | 5327 | |
| 5328 | return S; |
| 5329 | } |
Andre Vieira | 640527f | 2017-09-22 12:17:42 +0000 | [diff] [blame] | 5330 | |
| 5331 | static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, |
| 5332 | uint64_t Address, |
| 5333 | const void *Decoder) { |
| 5334 | const FeatureBitset &featureBits = |
| 5335 | ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); |
| 5336 | DecodeStatus S = MCDisassembler::Success; |
| 5337 | |
| 5338 | unsigned Rt = fieldFromInstruction(Val, 12, 4); |
| 5339 | |
| 5340 | if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { |
| 5341 | if (Rt == 13 || Rt == 15) |
| 5342 | S = MCDisassembler::SoftFail; |
| 5343 | Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); |
| 5344 | } else |
| 5345 | Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); |
| 5346 | |
Andre Vieira | d4a2570 | 2017-10-18 14:47:37 +0000 | [diff] [blame] | 5347 | if (featureBits[ARM::ModeThumb]) { |
| 5348 | Inst.addOperand(MCOperand::createImm(ARMCC::AL)); |
| 5349 | Inst.addOperand(MCOperand::createReg(0)); |
| 5350 | } else { |
| 5351 | unsigned pred = fieldFromInstruction(Val, 28, 4); |
| 5352 | if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) |
| 5353 | return MCDisassembler::Fail; |
| 5354 | } |
Andre Vieira | 640527f | 2017-09-22 12:17:42 +0000 | [diff] [blame] | 5355 | |
| 5356 | return S; |
| 5357 | } |