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Eugene Zelenko076468c2017-09-20 21:35:51 +00001//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
Johnny Chen7b999ea2010-04-02 22:27:38 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chen7b999ea2010-04-02 22:27:38 +00009
Owen Andersone0152a72011-08-09 20:55:18 +000010#include "MCTargetDesc/ARMAddressingModes.h"
11#include "MCTargetDesc/ARMBaseInfo.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000012#include "MCTargetDesc/ARMMCTargetDesc.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000013#include "Utils/ARMBaseInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000014#include "llvm/MC/MCContext.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000015#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen7b999ea2010-04-02 22:27:38 +000017#include "llvm/MC/MCInst.h"
Benjamin Kramer48b5bbf2011-11-11 12:39:41 +000018#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith7a3973d2012-04-03 15:48:14 +000019#include "llvm/MC/MCSubtargetInfo.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000020#include "llvm/MC/SubtargetFeature.h"
21#include "llvm/Support/Compiler.h"
Johnny Chen7b999ea2010-04-02 22:27:38 +000022#include "llvm/Support/ErrorHandling.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000023#include "llvm/Support/MathExtras.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000024#include "llvm/Support/TargetRegistry.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000025#include "llvm/Support/raw_ostream.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000026#include <algorithm>
27#include <cassert>
28#include <cstdint>
Richard Bartone9600002012-04-24 11:13:20 +000029#include <vector>
Johnny Chen7b999ea2010-04-02 22:27:38 +000030
James Molloydb4ce602011-09-01 18:02:14 +000031using namespace llvm;
Owen Andersona4043c42011-08-17 17:44:15 +000032
Chandler Carruth84e68b22014-04-22 02:41:26 +000033#define DEBUG_TYPE "arm-disassembler"
34
Eugene Zelenko076468c2017-09-20 21:35:51 +000035using DecodeStatus = MCDisassembler::DecodeStatus;
Owen Anderson03aadae2011-09-01 23:23:50 +000036
Owen Andersoned96b582011-09-01 23:35:51 +000037namespace {
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000038
Richard Bartone9600002012-04-24 11:13:20 +000039 // Handles the condition code status of instructions in IT blocks
40 class ITStatus
41 {
42 public:
43 // Returns the condition code for instruction in IT block
44 unsigned getITCC() {
45 unsigned CC = ARMCC::AL;
46 if (instrInITBlock())
47 CC = ITStates.back();
48 return CC;
49 }
50
51 // Advances the IT block state to the next T or E
52 void advanceITState() {
53 ITStates.pop_back();
54 }
55
56 // Returns true if the current instruction is in an IT block
57 bool instrInITBlock() {
58 return !ITStates.empty();
59 }
60
61 // Returns true if current instruction is the last instruction in an IT block
62 bool instrLastInITBlock() {
63 return ITStates.size() == 1;
64 }
65
66 // Called when decoding an IT instruction. Sets the IT state for the following
Vinicius Tinti67cf33d2015-11-20 23:20:12 +000067 // instructions that for the IT block. Firstcond and Mask correspond to the
Richard Bartone9600002012-04-24 11:13:20 +000068 // fields in the IT instruction encoding.
69 void setITState(char Firstcond, char Mask) {
70 // (3 - the number of trailing zeros) is the number of then / else.
Richard Bartonf435b092012-04-27 08:42:59 +000071 unsigned CondBit0 = Firstcond & 1;
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +000072 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Bartone9600002012-04-24 11:13:20 +000073 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74 assert(NumTZ <= 3 && "Invalid IT mask!");
75 // push condition codes onto the stack the correct order for the pops
76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77 bool T = ((Mask >> Pos) & 1) == CondBit0;
78 if (T)
79 ITStates.push_back(CCBits);
80 else
81 ITStates.push_back(CCBits ^ 1);
82 }
83 ITStates.push_back(CCBits);
84 }
85
86 private:
87 std::vector<unsigned char> ITStates;
88 };
Richard Bartone9600002012-04-24 11:13:20 +000089
Rafael Espindola4aa6bea2014-11-10 18:11:10 +000090/// ARM disassembler for all ARM platforms.
Owen Andersoned96b582011-09-01 23:35:51 +000091class ARMDisassembler : public MCDisassembler {
92public:
Lang Hamesa1bc0f52014-04-15 04:40:56 +000093 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
Owen Andersoned96b582011-09-01 23:35:51 +000095 }
96
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000097 ~ARMDisassembler() override = default;
Owen Andersoned96b582011-09-01 23:35:51 +000098
Rafael Espindola4aa6bea2014-11-10 18:11:10 +000099 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000100 ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000101 raw_ostream &VStream,
102 raw_ostream &CStream) const override;
Owen Andersoned96b582011-09-01 23:35:51 +0000103};
104
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000105/// Thumb disassembler for all Thumb platforms.
Owen Andersoned96b582011-09-01 23:35:51 +0000106class ThumbDisassembler : public MCDisassembler {
107public:
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109 MCDisassembler(STI, Ctx) {
Owen Andersoned96b582011-09-01 23:35:51 +0000110 }
111
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000112 ~ThumbDisassembler() override = default;
Owen Andersoned96b582011-09-01 23:35:51 +0000113
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000115 ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000116 raw_ostream &VStream,
117 raw_ostream &CStream) const override;
Owen Andersoned96b582011-09-01 23:35:51 +0000118
Owen Andersoned96b582011-09-01 23:35:51 +0000119private:
Richard Bartone9600002012-04-24 11:13:20 +0000120 mutable ITStatus ITBlock;
Eugene Zelenko076468c2017-09-20 21:35:51 +0000121
Owen Anderson2fefa422011-09-08 22:42:49 +0000122 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersoned96b582011-09-01 23:35:51 +0000123 void UpdateThumbVFPPredicate(MCInst&) const;
124};
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000125
126} // end anonymous namespace
Owen Andersoned96b582011-09-01 23:35:51 +0000127
Owen Anderson03aadae2011-09-01 23:23:50 +0000128static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloydb4ce602011-09-01 18:02:14 +0000129 switch (In) {
130 case MCDisassembler::Success:
131 // Out stays the same.
132 return true;
133 case MCDisassembler::SoftFail:
134 Out = In;
135 return true;
136 case MCDisassembler::Fail:
137 Out = In;
138 return false;
139 }
David Blaikie46a9f012012-01-20 21:51:11 +0000140 llvm_unreachable("Invalid DecodeStatus!");
James Molloydb4ce602011-09-01 18:02:14 +0000141}
Owen Andersona4043c42011-08-17 17:44:15 +0000142
Owen Andersone0152a72011-08-09 20:55:18 +0000143// Forward declare these because the autogenerated code will reference them.
144// Definitions are further down.
Craig Topperf6e7e122012-03-27 07:21:54 +0000145static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000146 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000147static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000148 unsigned RegNo, uint64_t Address,
149 const void *Decoder);
Mihai Popadc1764c52013-05-13 14:10:04 +0000150static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
151 unsigned RegNo, uint64_t Address,
152 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000153static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000154 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000155static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000156 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000157static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000158 uint64_t Address, const void *Decoder);
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000159static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000161static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000162 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000163static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000164 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000165static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000166 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000167static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000168 unsigned RegNo,
169 uint64_t Address,
170 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000171static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000172 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000173static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc988e0c2012-03-05 19:33:30 +0000174 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000175static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbache5307f92012-03-05 21:43:40 +0000176 unsigned RegNo, uint64_t Address,
177 const void *Decoder);
Johnny Chen74491bb2010-08-12 01:40:54 +0000178
Craig Topperf6e7e122012-03-27 07:21:54 +0000179static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000180 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000181static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000182 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000183static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000184 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000185static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000186 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000187static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000188 uint64_t Address, const void *Decoder);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000189
Craig Topperf6e7e122012-03-27 07:21:54 +0000190static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000191 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000192static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000193 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000194static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000195 unsigned Insn,
196 uint64_t Address,
197 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000198static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000199 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000200static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000201 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000202static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000203 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000204static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000205 uint64_t Address, const void *Decoder);
206
Craig Topperf6e7e122012-03-27 07:21:54 +0000207static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Andersone0152a72011-08-09 20:55:18 +0000208 unsigned Insn,
209 uint64_t Adddress,
210 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000211static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +0000212 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000213static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +0000214 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000215static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000216 uint64_t Address, const void *Decoder);
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000217static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000219static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson3d2e0e9d2011-08-09 23:05:39 +0000220 uint64_t Address, const void *Decoder);
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +0000221static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000225static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson9b7bd152011-08-23 17:45:18 +0000226 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000227static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000228 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000229static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000230 uint64_t Address, const void *Decoder);
Oliver Stannard65b85382016-01-25 10:26:26 +0000231static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000233static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000234 uint64_t Address, const void *Decoder);
Kevin Enderby40d4e472012-04-12 23:13:34 +0000235static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
236 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000237static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000238 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000239static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000240 uint64_t Address, const void *Decoder);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +0000241static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000249static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000250 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000251static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000252 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000253static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000254 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000255static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000256 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000257static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000258 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000259static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000260 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000261static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000262 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000263static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000264 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000265static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000266 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000267static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000268 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000269static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000270 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000271static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000272 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000273static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000274 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000275static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000276 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000277static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000278 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000279static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersone0089312011-08-09 23:25:42 +0000280 uint64_t Address, const void *Decoder);
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000281static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000283static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson60663402011-08-11 20:21:46 +0000284 uint64_t Address, const void *Decoder);
Tim Northoveree843ef2014-08-15 10:47:12 +0000285static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000287static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersonb685c9f2011-08-11 21:34:58 +0000288 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000289static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Andersonc5798a3a52011-08-12 17:58:32 +0000290 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000291static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +0000292 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000293static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +0000294 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000295static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +0000296 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000297static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +0000298 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000299static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000300 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000301static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000302 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000303static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000304 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000305static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000306 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000307static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000308 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000309static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000310 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000311static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000312 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000313static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000314 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000315static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +0000316 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000317static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +0000318 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000319static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersondde461c2011-10-28 18:02:13 +0000320 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000321static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +0000322 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000323static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +0000324 uint64_t Address, const void *Decoder);
Sam Parker963da5b2017-09-29 13:11:33 +0000325static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
326 unsigned Val,
327 uint64_t Address,
328 const void *Decoder);
Owen Anderson0ac90582011-11-15 19:55:00 +0000329
Craig Topperf6e7e122012-03-27 07:21:54 +0000330static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000331 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000332static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000333 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000334static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000335 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000336static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000337 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000338static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000339 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000340static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000341 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000342static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000343 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000344static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000345 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000346static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000347 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000348static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000349 uint64_t Address, const void *Decoder);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +0000350static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void* Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000358static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000359 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000360static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000361 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000362static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbacha05627e2011-09-09 18:37:27 +0000363 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000364static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000365 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000366static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000367 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000368static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000369 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000370static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000371 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000372static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000373 uint64_t Address, const void *Decoder);
Amaury de la Vieuville631df632013-06-08 13:38:52 +0000374static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000376static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000377 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000378static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000379 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000380static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach05541f42011-09-19 22:21:13 +0000381 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000382static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000383 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000384static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000385 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000386static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000387 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000388static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000389 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000390static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson37612a32011-08-24 22:40:22 +0000391 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000392static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +0000393 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000394static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +0000395 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000396static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson5bfb0e02011-09-09 22:24:36 +0000397 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000398static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona9ebf6f2011-09-12 18:56:30 +0000399 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000400static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Andersonf01e2de2011-09-26 21:06:22 +0000401 uint64_t Address, const void *Decoder);
402
Craig Topperf6e7e122012-03-27 07:21:54 +0000403static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangad213f212012-03-22 13:24:43 +0000404 uint64_t Address, const void *Decoder);
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000405static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh39d2d092016-06-17 00:52:41 +0000406 uint64_t Address, const void *Decoder);
Andre Vieira640527f2017-09-22 12:17:42 +0000407static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
408 uint64_t Address, const void *Decoder);
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000409
Owen Andersone0152a72011-08-09 20:55:18 +0000410#include "ARMGenDisassemblerTables.inc"
Sean Callanan814e69b2010-04-13 21:21:57 +0000411
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000412static MCDisassembler *createARMDisassembler(const Target &T,
413 const MCSubtargetInfo &STI,
414 MCContext &Ctx) {
415 return new ARMDisassembler(STI, Ctx);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000416}
417
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000418static MCDisassembler *createThumbDisassembler(const Target &T,
419 const MCSubtargetInfo &STI,
420 MCContext &Ctx) {
421 return new ThumbDisassembler(STI, Ctx);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000422}
423
Charlie Turner30895f92014-12-01 08:50:27 +0000424// Post-decoding checks
425static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
426 uint64_t Address, raw_ostream &OS,
427 raw_ostream &CS,
428 uint32_t Insn,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000429 DecodeStatus Result) {
Charlie Turner30895f92014-12-01 08:50:27 +0000430 switch (MI.getOpcode()) {
431 case ARM::HVC: {
432 // HVC is undefined if condition = 0xf otherwise upredictable
433 // if condition != 0xe
434 uint32_t Cond = (Insn >> 28) & 0xF;
435 if (Cond == 0xF)
436 return MCDisassembler::Fail;
437 if (Cond != 0xE)
438 return MCDisassembler::SoftFail;
439 return Result;
440 }
441 default: return Result;
442 }
443}
444
Owen Anderson03aadae2011-09-01 23:23:50 +0000445DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000446 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000447 uint64_t Address, raw_ostream &OS,
448 raw_ostream &CS) const {
449 CommentStream = &CS;
Kevin Enderby5dcda642011-10-04 22:44:48 +0000450
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000451 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000452 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
453 "mode!");
James Molloy8067df92011-09-07 19:42:28 +0000454
Owen Andersone0152a72011-08-09 20:55:18 +0000455 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000456 if (Bytes.size() < 4) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000457 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000458 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000459 }
Owen Andersone0152a72011-08-09 20:55:18 +0000460
461 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000462 uint32_t Insn =
463 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Owen Andersone0152a72011-08-09 20:55:18 +0000464
465 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000466 DecodeStatus Result =
467 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
468 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000469 Size = 4;
Charlie Turner30895f92014-12-01 08:50:27 +0000470 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Andersone0152a72011-08-09 20:55:18 +0000471 }
472
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000473 struct DecodeTable {
474 const uint8_t *P;
475 bool DecodePred;
476 };
Owen Andersone0152a72011-08-09 20:55:18 +0000477
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000478 const DecodeTable Tables[] = {
479 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
480 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
481 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
482 {DecoderTablev8Crypto32, false},
483 };
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000484
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000485 for (auto Table : Tables) {
486 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
487 if (Result != MCDisassembler::Fail) {
488 Size = 4;
489 // Add a fake predicate operand, because we share these instruction
490 // definitions with Thumb2 where these instructions are predicable.
491 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
492 return MCDisassembler::Fail;
493 return Result;
494 }
Amara Emerson33089092013-09-19 11:59:01 +0000495 }
496
Sjoerd Meijer7426c972017-08-11 09:52:30 +0000497 Result =
498 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
499 if (Result != MCDisassembler::Fail) {
500 Size = 4;
501 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
502 }
503
Eugene Leviant6269d392017-06-29 15:38:47 +0000504 Size = 4;
James Molloydb4ce602011-09-01 18:02:14 +0000505 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000506}
507
508namespace llvm {
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000509
Benjamin Kramer0d6d0982011-10-22 16:50:00 +0000510extern const MCInstrDesc ARMInsts[];
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000511
512} // end namespace llvm
Owen Andersone0152a72011-08-09 20:55:18 +0000513
Kevin Enderby5dcda642011-10-04 22:44:48 +0000514/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
515/// immediate Value in the MCInst. The immediate Value has had any PC
516/// adjustment made by the caller. If the instruction is a branch instruction
517/// then isBranch is true, else false. If the getOpInfo() function was set as
518/// part of the setupForSymbolicDisassembly() call then that function is called
519/// to get any symbolic information at the Address for this instruction. If
520/// that returns non-zero then the symbolic information it returns is used to
521/// create an MCExpr and that is added as an operand to the MCInst. If
522/// getOpInfo() returns zero and isBranch is true then a symbol look up for
523/// Value is done and if a symbol is found an MCExpr is created with that, else
524/// an MCExpr with Value is created. This function returns true if it adds an
525/// operand to the MCInst and false otherwise.
526static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
527 bool isBranch, uint64_t InstSize,
528 MCInst &MI, const void *Decoder) {
529 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougachaad1084d2013-05-24 00:39:57 +0000530 // FIXME: Does it make sense for value to be negative?
531 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
532 /* Offset */ 0, InstSize);
Kevin Enderby5dcda642011-10-04 22:44:48 +0000533}
534
535/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
536/// referenced by a load instruction with the base register that is the Pc.
537/// These can often be values in a literal pool near the Address of the
538/// instruction. The Address of the instruction and its immediate Value are
539/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru35521e22012-07-23 08:51:15 +0000540/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby5dcda642011-10-04 22:44:48 +0000541/// the referenced address is that of a symbol. Or it will return a pointer to
542/// a literal 'C' string if the referenced address of the literal pool's entry
543/// is an address into a section with 'C' string literals.
544static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +0000545 const void *Decoder) {
Kevin Enderby5dcda642011-10-04 22:44:48 +0000546 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougachaad1084d2013-05-24 00:39:57 +0000547 Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby5dcda642011-10-04 22:44:48 +0000548}
549
Owen Andersone0152a72011-08-09 20:55:18 +0000550// Thumb1 instructions don't have explicit S bits. Rather, they
551// implicitly set CPSR. Since it's not represented in the encoding, the
552// auto-generated decoder won't inject the CPSR operand. We need to fix
553// that as a post-pass.
554static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
555 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson187e1e42011-08-17 18:14:48 +0000556 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Andersone0152a72011-08-09 20:55:18 +0000557 MCInst::iterator I = MI.begin();
Owen Anderson187e1e42011-08-17 18:14:48 +0000558 for (unsigned i = 0; i < NumOps; ++i, ++I) {
559 if (I == MI.end()) break;
Owen Andersone0152a72011-08-09 20:55:18 +0000560 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson187e1e42011-08-17 18:14:48 +0000561 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbache9119e42015-05-13 18:37:00 +0000562 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +0000563 return;
564 }
565 }
566
Jim Grosbache9119e42015-05-13 18:37:00 +0000567 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +0000568}
569
570// Most Thumb instructions don't have explicit predicates in the
571// encoding, but rather get their predicates from IT context. We need
572// to fix up the predicate operands using this context information as a
573// post-pass.
Owen Anderson2fefa422011-09-08 22:42:49 +0000574MCDisassembler::DecodeStatus
575ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000576 MCDisassembler::DecodeStatus S = Success;
577
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000578 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
579
Owen Andersone0152a72011-08-09 20:55:18 +0000580 // A few instructions actually have predicates encoded in them. Don't
581 // try to overwrite it if we're seeing one of those.
582 switch (MI.getOpcode()) {
583 case ARM::tBcc:
584 case ARM::t2Bcc:
Owen Anderson2fefa422011-09-08 22:42:49 +0000585 case ARM::tCBZ:
586 case ARM::tCBNZ:
Owen Anderson61e46042011-09-19 23:47:10 +0000587 case ARM::tCPS:
588 case ARM::t2CPS3p:
589 case ARM::t2CPS2p:
590 case ARM::t2CPS1p:
Owen Anderson163be012011-09-19 23:57:20 +0000591 case ARM::tMOVSr:
Owen Anderson44f76ea2011-10-13 17:58:39 +0000592 case ARM::tSETEND:
Owen Anderson33d39532011-09-08 22:48:37 +0000593 // Some instructions (mostly conditional branches) are not
594 // allowed in IT blocks.
Richard Bartone9600002012-04-24 11:13:20 +0000595 if (ITBlock.instrInITBlock())
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000596 S = SoftFail;
597 else
598 return Success;
599 break;
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000600 case ARM::t2HINT:
601 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
602 S = SoftFail;
603 break;
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000604 case ARM::tB:
605 case ARM::t2B:
Owen Andersonf902d922011-09-19 22:34:23 +0000606 case ARM::t2TBB:
607 case ARM::t2TBH:
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000608 // Some instructions (mostly unconditional branches) can
609 // only appears at the end of, or outside of, an IT.
Richard Bartone9600002012-04-24 11:13:20 +0000610 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000611 S = SoftFail;
Owen Anderson2fefa422011-09-08 22:42:49 +0000612 break;
Owen Andersone0152a72011-08-09 20:55:18 +0000613 default:
614 break;
615 }
616
617 // If we're in an IT block, base the predicate on that. Otherwise,
618 // assume a predicate of AL.
619 unsigned CC;
Richard Bartone9600002012-04-24 11:13:20 +0000620 CC = ITBlock.getITCC();
621 if (CC == 0xF)
Owen Andersone0152a72011-08-09 20:55:18 +0000622 CC = ARMCC::AL;
Richard Bartone9600002012-04-24 11:13:20 +0000623 if (ITBlock.instrInITBlock())
624 ITBlock.advanceITState();
Owen Andersone0152a72011-08-09 20:55:18 +0000625
626 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson187e1e42011-08-17 18:14:48 +0000627 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Andersone0152a72011-08-09 20:55:18 +0000628 MCInst::iterator I = MI.begin();
Owen Anderson187e1e42011-08-17 18:14:48 +0000629 for (unsigned i = 0; i < NumOps; ++i, ++I) {
630 if (I == MI.end()) break;
Owen Andersone0152a72011-08-09 20:55:18 +0000631 if (OpInfo[i].isPredicate()) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000632 I = MI.insert(I, MCOperand::createImm(CC));
Owen Andersone0152a72011-08-09 20:55:18 +0000633 ++I;
634 if (CC == ARMCC::AL)
Jim Grosbache9119e42015-05-13 18:37:00 +0000635 MI.insert(I, MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +0000636 else
Jim Grosbache9119e42015-05-13 18:37:00 +0000637 MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000638 return S;
Owen Andersone0152a72011-08-09 20:55:18 +0000639 }
640 }
641
Jim Grosbache9119e42015-05-13 18:37:00 +0000642 I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson187e1e42011-08-17 18:14:48 +0000643 ++I;
Owen Andersone0152a72011-08-09 20:55:18 +0000644 if (CC == ARMCC::AL)
Jim Grosbache9119e42015-05-13 18:37:00 +0000645 MI.insert(I, MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +0000646 else
Jim Grosbache9119e42015-05-13 18:37:00 +0000647 MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson2fefa422011-09-08 22:42:49 +0000648
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000649 return S;
Owen Andersone0152a72011-08-09 20:55:18 +0000650}
651
652// Thumb VFP instructions are a special case. Because we share their
653// encodings between ARM and Thumb modes, and they are predicable in ARM
654// mode, the auto-generated decoder will give them an (incorrect)
655// predicate operand. We need to rewrite these operands based on the IT
656// context as a post-pass.
657void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
658 unsigned CC;
Richard Bartone9600002012-04-24 11:13:20 +0000659 CC = ITBlock.getITCC();
660 if (ITBlock.instrInITBlock())
661 ITBlock.advanceITState();
Owen Andersone0152a72011-08-09 20:55:18 +0000662
663 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
664 MCInst::iterator I = MI.begin();
Owen Anderson216cfaa2011-08-24 21:35:46 +0000665 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
666 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Andersone0152a72011-08-09 20:55:18 +0000667 if (OpInfo[i].isPredicate() ) {
668 I->setImm(CC);
669 ++I;
670 if (CC == ARMCC::AL)
671 I->setReg(0);
672 else
673 I->setReg(ARM::CPSR);
674 return;
675 }
676 }
677}
678
Owen Anderson03aadae2011-09-01 23:23:50 +0000679DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000680 ArrayRef<uint8_t> Bytes,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000681 uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000682 raw_ostream &OS,
683 raw_ostream &CS) const {
684 CommentStream = &CS;
Kevin Enderby5dcda642011-10-04 22:44:48 +0000685
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000686 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy8067df92011-09-07 19:42:28 +0000687 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
688
Owen Andersone0152a72011-08-09 20:55:18 +0000689 // We want to read exactly 2 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000690 if (Bytes.size() < 2) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000691 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000692 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000693 }
Owen Andersone0152a72011-08-09 20:55:18 +0000694
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000695 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
696 DecodeStatus Result =
697 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
698 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000699 Size = 2;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000700 Check(Result, AddThumbPredicate(MI));
701 return Result;
Owen Anderson91a8f9b2011-08-16 23:45:44 +0000702 }
703
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000704 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
705 STI);
706 if (Result) {
Owen Anderson91a8f9b2011-08-16 23:45:44 +0000707 Size = 2;
Richard Bartone9600002012-04-24 11:13:20 +0000708 bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000709 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000710 AddThumb1SBit(MI, InITBlock);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000711 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000712 }
713
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000714 Result =
715 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
716 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000717 Size = 2;
Owen Anderson6a5c1502011-10-06 23:33:11 +0000718
719 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
720 // the Thumb predicate.
Richard Bartone9600002012-04-24 11:13:20 +0000721 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000722 Result = MCDisassembler::SoftFail;
Owen Anderson6a5c1502011-10-06 23:33:11 +0000723
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000724 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000725
726 // If we find an IT instruction, we need to parse its condition
727 // code and mask operands so that we can apply them correctly
728 // to the subsequent instructions.
729 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersonf1e38442011-09-14 21:06:21 +0000730
Richard Bartone9600002012-04-24 11:13:20 +0000731 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson2fa06a72011-08-30 22:58:27 +0000732 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartone9600002012-04-24 11:13:20 +0000733 ITBlock.setITState(Firstcond, Mask);
Owen Andersone0152a72011-08-09 20:55:18 +0000734 }
735
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000736 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000737 }
738
739 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000740 if (Bytes.size() < 4) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000741 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000742 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000743 }
Owen Andersone0152a72011-08-09 20:55:18 +0000744
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000745 uint32_t Insn32 =
746 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000747 Result =
748 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
749 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000750 Size = 4;
Richard Bartone9600002012-04-24 11:13:20 +0000751 bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000752 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000753 AddThumb1SBit(MI, InITBlock);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000754 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000755 }
756
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000757 Result =
758 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
759 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000760 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000761 Check(Result, AddThumbPredicate(MI));
762 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000763 }
764
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000765 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000766 Result =
767 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000769 Size = 4;
770 UpdateThumbVFPPredicate(MI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000771 return Result;
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000772 }
Owen Andersone0152a72011-08-09 20:55:18 +0000773 }
774
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000775 Result =
776 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
777 if (Result != MCDisassembler::Fail) {
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000778 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000779 return Result;
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000780 }
781
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000782 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000783 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
784 STI);
785 if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000786 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000787 Check(Result, AddThumbPredicate(MI));
788 return Result;
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000789 }
Owen Andersona6201f02011-08-15 23:38:54 +0000790 }
791
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000792 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000793 uint32_t NEONLdStInsn = Insn32;
Owen Andersona6201f02011-08-15 23:38:54 +0000794 NEONLdStInsn &= 0xF0FFFFFF;
795 NEONLdStInsn |= 0x04000000;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000796 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbachecaef492012-08-14 19:06:05 +0000797 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000798 if (Result != MCDisassembler::Fail) {
Owen Andersona6201f02011-08-15 23:38:54 +0000799 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000800 Check(Result, AddThumbPredicate(MI));
801 return Result;
Owen Andersona6201f02011-08-15 23:38:54 +0000802 }
803 }
804
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000805 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000806 uint32_t NEONDataInsn = Insn32;
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000807 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
808 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
809 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000810 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbachecaef492012-08-14 19:06:05 +0000811 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000812 if (Result != MCDisassembler::Fail) {
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000813 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000814 Check(Result, AddThumbPredicate(MI));
815 return Result;
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000816 }
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000817
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000818 uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000819 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
820 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
821 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000822 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000823 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000824 if (Result != MCDisassembler::Fail) {
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000825 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000826 return Result;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000827 }
Amara Emerson33089092013-09-19 11:59:01 +0000828
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000829 uint32_t NEONv8Insn = Insn32;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000830 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000831 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000832 this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000833 if (Result != MCDisassembler::Fail) {
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000834 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000835 return Result;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000836 }
Joey Goulydf686002013-07-17 13:59:38 +0000837 }
838
Sjoerd Meijer7426c972017-08-11 09:52:30 +0000839 Result =
840 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
841 if (Result != MCDisassembler::Fail) {
842 Size = 4;
843 Check(Result, AddThumbPredicate(MI));
844 return Result;
845 }
846
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000847 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000848 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000849}
850
Owen Andersone0152a72011-08-09 20:55:18 +0000851extern "C" void LLVMInitializeARMDisassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000852 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
Owen Andersone0152a72011-08-09 20:55:18 +0000853 createARMDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000854 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
Christian Pirker2a111602014-03-28 14:35:30 +0000855 createARMDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000856 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
Christian Pirker2a111602014-03-28 14:35:30 +0000857 createThumbDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000858 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
Owen Andersone0152a72011-08-09 20:55:18 +0000859 createThumbDisassembler);
860}
861
Craig Topperca658c22012-03-11 07:16:55 +0000862static const uint16_t GPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +0000863 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
864 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
865 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
866 ARM::R12, ARM::SP, ARM::LR, ARM::PC
867};
868
Craig Topperf6e7e122012-03-27 07:21:54 +0000869static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000870 uint64_t Address, const void *Decoder) {
871 if (RegNo > 15)
James Molloydb4ce602011-09-01 18:02:14 +0000872 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000873
874 unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000875 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +0000876 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +0000877}
878
Owen Anderson03aadae2011-09-01 23:23:50 +0000879static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +0000880DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000881 uint64_t Address, const void *Decoder) {
Silviu Baranga32a49332012-03-20 15:54:56 +0000882 DecodeStatus S = MCDisassembler::Success;
Vinicius Tinti67cf33d2015-11-20 23:20:12 +0000883
Silviu Baranga32a49332012-03-20 15:54:56 +0000884 if (RegNo == 15)
885 S = MCDisassembler::SoftFail;
886
887 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
888
889 return S;
Owen Anderson042619f2011-08-09 22:48:45 +0000890}
891
Mihai Popadc1764c52013-05-13 14:10:04 +0000892static DecodeStatus
893DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
894 uint64_t Address, const void *Decoder) {
895 DecodeStatus S = MCDisassembler::Success;
896
897 if (RegNo == 15)
898 {
Jim Grosbache9119e42015-05-13 18:37:00 +0000899 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popadc1764c52013-05-13 14:10:04 +0000900 return MCDisassembler::Success;
901 }
902
903 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
904 return S;
905}
906
Craig Topperf6e7e122012-03-27 07:21:54 +0000907static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000908 uint64_t Address, const void *Decoder) {
909 if (RegNo > 7)
James Molloydb4ce602011-09-01 18:02:14 +0000910 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000911 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
912}
913
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000914static const uint16_t GPRPairDecoderTable[] = {
915 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
916 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
917};
918
919static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address, const void *Decoder) {
921 DecodeStatus S = MCDisassembler::Success;
922
923 if (RegNo > 13)
924 return MCDisassembler::Fail;
925
926 if ((RegNo & 1) || RegNo == 0xe)
927 S = MCDisassembler::SoftFail;
928
929 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbache9119e42015-05-13 18:37:00 +0000930 Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000931 return S;
932}
933
Craig Topperf6e7e122012-03-27 07:21:54 +0000934static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000935 uint64_t Address, const void *Decoder) {
936 unsigned Register = 0;
937 switch (RegNo) {
938 case 0:
939 Register = ARM::R0;
940 break;
941 case 1:
942 Register = ARM::R1;
943 break;
944 case 2:
945 Register = ARM::R2;
946 break;
947 case 3:
948 Register = ARM::R3;
949 break;
950 case 9:
951 Register = ARM::R9;
952 break;
953 case 12:
954 Register = ARM::R12;
955 break;
956 default:
James Molloydb4ce602011-09-01 18:02:14 +0000957 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000958 }
959
Jim Grosbache9119e42015-05-13 18:37:00 +0000960 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +0000961 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +0000962}
963
Craig Topperf6e7e122012-03-27 07:21:54 +0000964static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000965 uint64_t Address, const void *Decoder) {
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +0000966 DecodeStatus S = MCDisassembler::Success;
Artyom Skrobovb43981072015-10-28 13:58:36 +0000967
968 const FeatureBitset &featureBits =
969 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
970
971 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +0000972 S = MCDisassembler::SoftFail;
Artyom Skrobovb43981072015-10-28 13:58:36 +0000973
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +0000974 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
975 return S;
Owen Andersone0152a72011-08-09 20:55:18 +0000976}
977
Craig Topperca658c22012-03-11 07:16:55 +0000978static const uint16_t SPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +0000979 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
980 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
981 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
982 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
983 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
984 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
985 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
986 ARM::S28, ARM::S29, ARM::S30, ARM::S31
987};
988
Craig Topperf6e7e122012-03-27 07:21:54 +0000989static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000990 uint64_t Address, const void *Decoder) {
991 if (RegNo > 31)
James Molloydb4ce602011-09-01 18:02:14 +0000992 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000993
994 unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000995 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +0000996 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +0000997}
998
Craig Topperca658c22012-03-11 07:16:55 +0000999static const uint16_t DPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +00001000 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1001 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1002 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1003 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1004 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1005 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1006 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1007 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1008};
1009
Craig Topperf6e7e122012-03-27 07:21:54 +00001010static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001011 uint64_t Address, const void *Decoder) {
Michael Kupersteindb0712f2015-05-26 10:47:10 +00001012 const FeatureBitset &featureBits =
1013 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1014
1015 bool hasD16 = featureBits[ARM::FeatureD16];
Oliver Stannard9e89d8c2014-11-05 12:06:39 +00001016
1017 if (RegNo > 31 || (hasD16 && RegNo > 15))
James Molloydb4ce602011-09-01 18:02:14 +00001018 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001019
1020 unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001021 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +00001022 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001023}
1024
Craig Topperf6e7e122012-03-27 07:21:54 +00001025static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001026 uint64_t Address, const void *Decoder) {
1027 if (RegNo > 7)
James Molloydb4ce602011-09-01 18:02:14 +00001028 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001029 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030}
1031
Owen Anderson03aadae2011-09-01 23:23:50 +00001032static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001033DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001034 uint64_t Address, const void *Decoder) {
Owen Andersone0152a72011-08-09 20:55:18 +00001035 if (RegNo > 15)
James Molloydb4ce602011-09-01 18:02:14 +00001036 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001037 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1038}
1039
Craig Topperca658c22012-03-11 07:16:55 +00001040static const uint16_t QPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +00001041 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1042 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1043 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1044 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045};
1046
Craig Topperf6e7e122012-03-27 07:21:54 +00001047static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001048 uint64_t Address, const void *Decoder) {
Mihai Popadcf09222013-05-20 14:42:43 +00001049 if (RegNo > 31 || (RegNo & 1) != 0)
James Molloydb4ce602011-09-01 18:02:14 +00001050 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001051 RegNo >>= 1;
1052
1053 unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001054 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +00001055 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001056}
1057
Craig Topperca658c22012-03-11 07:16:55 +00001058static const uint16_t DPairDecoderTable[] = {
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001059 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1060 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1061 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1062 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1063 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1064 ARM::Q15
1065};
1066
Craig Topperf6e7e122012-03-27 07:21:54 +00001067static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001068 uint64_t Address, const void *Decoder) {
1069 if (RegNo > 30)
1070 return MCDisassembler::Fail;
1071
1072 unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001073 Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001074 return MCDisassembler::Success;
1075}
1076
Craig Topperca658c22012-03-11 07:16:55 +00001077static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbache5307f92012-03-05 21:43:40 +00001078 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1079 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1080 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1081 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1082 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1083 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1084 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1085 ARM::D28_D30, ARM::D29_D31
1086};
1087
Craig Topperf6e7e122012-03-27 07:21:54 +00001088static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbache5307f92012-03-05 21:43:40 +00001089 unsigned RegNo,
1090 uint64_t Address,
1091 const void *Decoder) {
1092 if (RegNo > 29)
1093 return MCDisassembler::Fail;
1094
1095 unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001096 Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbache5307f92012-03-05 21:43:40 +00001097 return MCDisassembler::Success;
1098}
1099
Craig Topperf6e7e122012-03-27 07:21:54 +00001100static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001101 uint64_t Address, const void *Decoder) {
James Molloydb4ce602011-09-01 18:02:14 +00001102 if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson7a2401d2011-08-09 21:07:45 +00001103 // AL predicate is not allowed on Thumb1 branches.
1104 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloydb4ce602011-09-01 18:02:14 +00001105 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00001106 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersone0152a72011-08-09 20:55:18 +00001107 if (Val == ARMCC::AL) {
Jim Grosbache9119e42015-05-13 18:37:00 +00001108 Inst.addOperand(MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +00001109 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00001110 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
James Molloydb4ce602011-09-01 18:02:14 +00001111 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001112}
1113
Craig Topperf6e7e122012-03-27 07:21:54 +00001114static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001115 uint64_t Address, const void *Decoder) {
1116 if (Val)
Jim Grosbache9119e42015-05-13 18:37:00 +00001117 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +00001118 else
Jim Grosbache9119e42015-05-13 18:37:00 +00001119 Inst.addOperand(MCOperand::createReg(0));
James Molloydb4ce602011-09-01 18:02:14 +00001120 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001121}
1122
Craig Topperf6e7e122012-03-27 07:21:54 +00001123static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001124 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001125 DecodeStatus S = MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001126
Jim Grosbachecaef492012-08-14 19:06:05 +00001127 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1128 unsigned type = fieldFromInstruction(Val, 5, 2);
1129 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00001130
1131 // Register-immediate
Artyom Skrobovb43981072015-10-28 13:58:36 +00001132 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00001133 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001134
1135 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1136 switch (type) {
1137 case 0:
1138 Shift = ARM_AM::lsl;
1139 break;
1140 case 1:
1141 Shift = ARM_AM::lsr;
1142 break;
1143 case 2:
1144 Shift = ARM_AM::asr;
1145 break;
1146 case 3:
1147 Shift = ARM_AM::ror;
1148 break;
1149 }
1150
1151 if (Shift == ARM_AM::ror && imm == 0)
1152 Shift = ARM_AM::rrx;
1153
1154 unsigned Op = Shift | (imm << 3);
Jim Grosbache9119e42015-05-13 18:37:00 +00001155 Inst.addOperand(MCOperand::createImm(Op));
Owen Andersone0152a72011-08-09 20:55:18 +00001156
Owen Andersona4043c42011-08-17 17:44:15 +00001157 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001158}
1159
Craig Topperf6e7e122012-03-27 07:21:54 +00001160static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001161 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001162 DecodeStatus S = MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001163
Jim Grosbachecaef492012-08-14 19:06:05 +00001164 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1165 unsigned type = fieldFromInstruction(Val, 5, 2);
1166 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00001167
1168 // Register-register
Owen Anderson03aadae2011-09-01 23:23:50 +00001169 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1170 return MCDisassembler::Fail;
1171 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1172 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001173
1174 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1175 switch (type) {
1176 case 0:
1177 Shift = ARM_AM::lsl;
1178 break;
1179 case 1:
1180 Shift = ARM_AM::lsr;
1181 break;
1182 case 2:
1183 Shift = ARM_AM::asr;
1184 break;
1185 case 3:
1186 Shift = ARM_AM::ror;
1187 break;
1188 }
1189
Jim Grosbache9119e42015-05-13 18:37:00 +00001190 Inst.addOperand(MCOperand::createImm(Shift));
Owen Andersone0152a72011-08-09 20:55:18 +00001191
Owen Andersona4043c42011-08-17 17:44:15 +00001192 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001193}
1194
Craig Topperf6e7e122012-03-27 07:21:54 +00001195static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001196 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001197 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001198
Tim Northover08a86602013-10-22 19:00:39 +00001199 bool NeedDisjointWriteback = false;
1200 unsigned WritebackReg = 0;
Owen Anderson53db43b2011-09-09 23:13:33 +00001201 switch (Inst.getOpcode()) {
Tim Northover08a86602013-10-22 19:00:39 +00001202 default:
1203 break;
1204 case ARM::LDMIA_UPD:
1205 case ARM::LDMDB_UPD:
1206 case ARM::LDMIB_UPD:
1207 case ARM::LDMDA_UPD:
1208 case ARM::t2LDMIA_UPD:
1209 case ARM::t2LDMDB_UPD:
1210 case ARM::t2STMIA_UPD:
1211 case ARM::t2STMDB_UPD:
1212 NeedDisjointWriteback = true;
1213 WritebackReg = Inst.getOperand(0).getReg();
1214 break;
Owen Anderson53db43b2011-09-09 23:13:33 +00001215 }
1216
Owen Anderson60663402011-08-11 20:21:46 +00001217 // Empty register lists are not allowed.
Benjamin Kramer8bad66e2013-05-19 22:01:57 +00001218 if (Val == 0) return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001219 for (unsigned i = 0; i < 16; ++i) {
Owen Andersoned253852011-08-11 18:24:51 +00001220 if (Val & (1 << i)) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001221 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1222 return MCDisassembler::Fail;
Owen Anderson53db43b2011-09-09 23:13:33 +00001223 // Writeback not allowed if Rn is in the target list.
Tim Northover08a86602013-10-22 19:00:39 +00001224 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson53db43b2011-09-09 23:13:33 +00001225 Check(S, MCDisassembler::SoftFail);
Owen Andersoned253852011-08-11 18:24:51 +00001226 }
Owen Andersone0152a72011-08-09 20:55:18 +00001227 }
1228
Owen Andersona4043c42011-08-17 17:44:15 +00001229 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001230}
1231
Craig Topperf6e7e122012-03-27 07:21:54 +00001232static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001233 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001234 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001235
Jim Grosbachecaef492012-08-14 19:06:05 +00001236 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1237 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00001238
Tim Northover4173e292013-05-31 15:55:51 +00001239 // In case of unpredictable encoding, tweak the operands.
1240 if (regs == 0 || (Vd + regs) > 32) {
1241 regs = Vd + regs > 32 ? 32 - Vd : regs;
1242 regs = std::max( 1u, regs);
1243 S = MCDisassembler::SoftFail;
1244 }
1245
Owen Anderson03aadae2011-09-01 23:23:50 +00001246 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1247 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001248 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001249 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001251 }
Owen Andersone0152a72011-08-09 20:55:18 +00001252
Owen Andersona4043c42011-08-17 17:44:15 +00001253 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001254}
1255
Craig Topperf6e7e122012-03-27 07:21:54 +00001256static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001257 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001258 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001259
Jim Grosbachecaef492012-08-14 19:06:05 +00001260 unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover4173e292013-05-31 15:55:51 +00001261 unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga9560af82012-05-03 16:38:40 +00001262
Tim Northover4173e292013-05-31 15:55:51 +00001263 // In case of unpredictable encoding, tweak the operands.
1264 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1265 regs = Vd + regs > 32 ? 32 - Vd : regs;
1266 regs = std::max( 1u, regs);
1267 regs = std::min(16u, regs);
1268 S = MCDisassembler::SoftFail;
1269 }
Owen Andersone0152a72011-08-09 20:55:18 +00001270
Owen Anderson03aadae2011-09-01 23:23:50 +00001271 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1272 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001273 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001274 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1275 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001276 }
Owen Andersone0152a72011-08-09 20:55:18 +00001277
Owen Andersona4043c42011-08-17 17:44:15 +00001278 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001279}
1280
Craig Topperf6e7e122012-03-27 07:21:54 +00001281static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001282 uint64_t Address, const void *Decoder) {
Owen Anderson5d69f632011-08-10 17:36:48 +00001283 // This operand encodes a mask of contiguous zeros between a specified MSB
1284 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1285 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001286 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson5d69f632011-08-10 17:36:48 +00001287 // create the final mask.
Jim Grosbachecaef492012-08-14 19:06:05 +00001288 unsigned msb = fieldFromInstruction(Val, 5, 5);
1289 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson3ca958c2011-09-16 22:29:48 +00001290
Owen Anderson502cd9d2011-09-16 23:30:01 +00001291 DecodeStatus S = MCDisassembler::Success;
Kevin Enderby136d6742012-11-29 23:47:11 +00001292 if (lsb > msb) {
1293 Check(S, MCDisassembler::SoftFail);
1294 // The check above will cause the warning for the "potentially undefined
1295 // instruction encoding" but we can't build a bad MCOperand value here
1296 // with a lsb > msb or else printing the MCInst will cause a crash.
1297 lsb = msb;
1298 }
Owen Anderson502cd9d2011-09-16 23:30:01 +00001299
Owen Andersonb925e932011-09-16 23:04:48 +00001300 uint32_t msb_mask = 0xFFFFFFFF;
1301 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1302 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson3ca958c2011-09-16 22:29:48 +00001303
Jim Grosbache9119e42015-05-13 18:37:00 +00001304 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson502cd9d2011-09-16 23:30:01 +00001305 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001306}
1307
Craig Topperf6e7e122012-03-27 07:21:54 +00001308static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00001309 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001310 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001311
Jim Grosbachecaef492012-08-14 19:06:05 +00001312 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1313 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1314 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1315 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1316 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1317 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001318
1319 switch (Inst.getOpcode()) {
1320 case ARM::LDC_OFFSET:
1321 case ARM::LDC_PRE:
1322 case ARM::LDC_POST:
1323 case ARM::LDC_OPTION:
1324 case ARM::LDCL_OFFSET:
1325 case ARM::LDCL_PRE:
1326 case ARM::LDCL_POST:
1327 case ARM::LDCL_OPTION:
1328 case ARM::STC_OFFSET:
1329 case ARM::STC_PRE:
1330 case ARM::STC_POST:
1331 case ARM::STC_OPTION:
1332 case ARM::STCL_OFFSET:
1333 case ARM::STCL_PRE:
1334 case ARM::STCL_POST:
1335 case ARM::STCL_OPTION:
Owen Anderson18d17aa2011-09-07 21:10:42 +00001336 case ARM::t2LDC_OFFSET:
1337 case ARM::t2LDC_PRE:
1338 case ARM::t2LDC_POST:
1339 case ARM::t2LDC_OPTION:
1340 case ARM::t2LDCL_OFFSET:
1341 case ARM::t2LDCL_PRE:
1342 case ARM::t2LDCL_POST:
1343 case ARM::t2LDCL_OPTION:
1344 case ARM::t2STC_OFFSET:
1345 case ARM::t2STC_PRE:
1346 case ARM::t2STC_POST:
1347 case ARM::t2STC_OPTION:
1348 case ARM::t2STCL_OFFSET:
1349 case ARM::t2STCL_PRE:
1350 case ARM::t2STCL_POST:
1351 case ARM::t2STCL_OPTION:
Owen Andersone0152a72011-08-09 20:55:18 +00001352 if (coproc == 0xA || coproc == 0xB)
James Molloydb4ce602011-09-01 18:02:14 +00001353 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001354 break;
1355 default:
1356 break;
1357 }
1358
Michael Kupersteindb0712f2015-05-26 10:47:10 +00001359 const FeatureBitset &featureBits =
1360 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1361 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobove686cec2013-11-08 16:16:30 +00001362 return MCDisassembler::Fail;
1363
Jim Grosbache9119e42015-05-13 18:37:00 +00001364 Inst.addOperand(MCOperand::createImm(coproc));
1365 Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson03aadae2011-09-01 23:23:50 +00001366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1367 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001368
Owen Andersone0152a72011-08-09 20:55:18 +00001369 switch (Inst.getOpcode()) {
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001370 case ARM::t2LDC2_OFFSET:
1371 case ARM::t2LDC2L_OFFSET:
1372 case ARM::t2LDC2_PRE:
1373 case ARM::t2LDC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001374 case ARM::t2STC2_OFFSET:
1375 case ARM::t2STC2L_OFFSET:
1376 case ARM::t2STC2_PRE:
1377 case ARM::t2STC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001378 case ARM::LDC2_OFFSET:
1379 case ARM::LDC2L_OFFSET:
1380 case ARM::LDC2_PRE:
1381 case ARM::LDC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001382 case ARM::STC2_OFFSET:
1383 case ARM::STC2L_OFFSET:
1384 case ARM::STC2_PRE:
1385 case ARM::STC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001386 case ARM::t2LDC_OFFSET:
1387 case ARM::t2LDCL_OFFSET:
1388 case ARM::t2LDC_PRE:
1389 case ARM::t2LDCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001390 case ARM::t2STC_OFFSET:
1391 case ARM::t2STCL_OFFSET:
1392 case ARM::t2STC_PRE:
1393 case ARM::t2STCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001394 case ARM::LDC_OFFSET:
1395 case ARM::LDCL_OFFSET:
1396 case ARM::LDC_PRE:
1397 case ARM::LDCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001398 case ARM::STC_OFFSET:
1399 case ARM::STCL_OFFSET:
1400 case ARM::STC_PRE:
1401 case ARM::STCL_PRE:
Jim Grosbacha098a892011-10-12 21:59:02 +00001402 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbache9119e42015-05-13 18:37:00 +00001403 Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbacha098a892011-10-12 21:59:02 +00001404 break;
1405 case ARM::t2LDC2_POST:
1406 case ARM::t2LDC2L_POST:
1407 case ARM::t2STC2_POST:
1408 case ARM::t2STC2L_POST:
1409 case ARM::LDC2_POST:
1410 case ARM::LDC2L_POST:
1411 case ARM::STC2_POST:
1412 case ARM::STC2L_POST:
1413 case ARM::t2LDC_POST:
1414 case ARM::t2LDCL_POST:
1415 case ARM::t2STC_POST:
1416 case ARM::t2STCL_POST:
1417 case ARM::LDC_POST:
1418 case ARM::LDCL_POST:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001419 case ARM::STC_POST:
1420 case ARM::STCL_POST:
Owen Andersone0152a72011-08-09 20:55:18 +00001421 imm |= U << 8;
Justin Bognercd1d5aa2016-08-17 20:30:52 +00001422 LLVM_FALLTHROUGH;
Owen Andersone0152a72011-08-09 20:55:18 +00001423 default:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001424 // The 'option' variant doesn't encode 'U' in the immediate since
1425 // the immediate is unsigned [0,255].
Jim Grosbache9119e42015-05-13 18:37:00 +00001426 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00001427 break;
1428 }
1429
1430 switch (Inst.getOpcode()) {
1431 case ARM::LDC_OFFSET:
1432 case ARM::LDC_PRE:
1433 case ARM::LDC_POST:
1434 case ARM::LDC_OPTION:
1435 case ARM::LDCL_OFFSET:
1436 case ARM::LDCL_PRE:
1437 case ARM::LDCL_POST:
1438 case ARM::LDCL_OPTION:
1439 case ARM::STC_OFFSET:
1440 case ARM::STC_PRE:
1441 case ARM::STC_POST:
1442 case ARM::STC_OPTION:
1443 case ARM::STCL_OFFSET:
1444 case ARM::STCL_PRE:
1445 case ARM::STCL_POST:
1446 case ARM::STCL_OPTION:
Owen Anderson03aadae2011-09-01 23:23:50 +00001447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1448 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001449 break;
1450 default:
1451 break;
1452 }
1453
Owen Andersona4043c42011-08-17 17:44:15 +00001454 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001455}
1456
Owen Anderson03aadae2011-09-01 23:23:50 +00001457static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001458DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001459 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001460 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001461
Jim Grosbachecaef492012-08-14 19:06:05 +00001462 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1463 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1464 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1465 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1466 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1467 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1468 unsigned P = fieldFromInstruction(Insn, 24, 1);
1469 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001470
1471 // On stores, the writeback operand precedes Rt.
1472 switch (Inst.getOpcode()) {
1473 case ARM::STR_POST_IMM:
1474 case ARM::STR_POST_REG:
Owen Anderson3a850f22011-08-11 20:47:56 +00001475 case ARM::STRB_POST_IMM:
1476 case ARM::STRB_POST_REG:
Jim Grosbache2594212011-08-11 22:18:00 +00001477 case ARM::STRT_POST_REG:
1478 case ARM::STRT_POST_IMM:
Jim Grosbach2a502602011-08-11 20:04:56 +00001479 case ARM::STRBT_POST_REG:
1480 case ARM::STRBT_POST_IMM:
Owen Anderson03aadae2011-09-01 23:23:50 +00001481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1482 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001483 break;
1484 default:
1485 break;
1486 }
1487
Owen Anderson03aadae2011-09-01 23:23:50 +00001488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1489 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001490
1491 // On loads, the writeback operand comes after Rt.
1492 switch (Inst.getOpcode()) {
1493 case ARM::LDR_POST_IMM:
1494 case ARM::LDR_POST_REG:
Owen Anderson3a850f22011-08-11 20:47:56 +00001495 case ARM::LDRB_POST_IMM:
1496 case ARM::LDRB_POST_REG:
Owen Andersone0152a72011-08-09 20:55:18 +00001497 case ARM::LDRBT_POST_REG:
1498 case ARM::LDRBT_POST_IMM:
Jim Grosbachd5d63592011-08-10 23:43:54 +00001499 case ARM::LDRT_POST_REG:
1500 case ARM::LDRT_POST_IMM:
Owen Anderson03aadae2011-09-01 23:23:50 +00001501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1502 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001503 break;
1504 default:
1505 break;
1506 }
1507
Owen Anderson03aadae2011-09-01 23:23:50 +00001508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001510
1511 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachecaef492012-08-14 19:06:05 +00001512 if (!fieldFromInstruction(Insn, 23, 1))
Owen Andersone0152a72011-08-09 20:55:18 +00001513 Op = ARM_AM::sub;
1514
1515 bool writeback = (P == 0) || (W == 1);
1516 unsigned idx_mode = 0;
1517 if (P && writeback)
1518 idx_mode = ARMII::IndexModePre;
1519 else if (!P && writeback)
1520 idx_mode = ARMII::IndexModePost;
1521
Owen Anderson03aadae2011-09-01 23:23:50 +00001522 if (writeback && (Rn == 15 || Rn == Rt))
1523 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson3477f2c2011-08-11 19:00:18 +00001524
Owen Andersone0152a72011-08-09 20:55:18 +00001525 if (reg) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001526 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1527 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001528 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachecaef492012-08-14 19:06:05 +00001529 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Andersone0152a72011-08-09 20:55:18 +00001530 case 0:
1531 Opc = ARM_AM::lsl;
1532 break;
1533 case 1:
1534 Opc = ARM_AM::lsr;
1535 break;
1536 case 2:
1537 Opc = ARM_AM::asr;
1538 break;
1539 case 3:
1540 Opc = ARM_AM::ror;
1541 break;
1542 default:
James Molloydb4ce602011-09-01 18:02:14 +00001543 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001544 }
Jim Grosbachecaef492012-08-14 19:06:05 +00001545 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover0c97e762012-09-22 11:18:12 +00001546 if (Opc == ARM_AM::ror && amt == 0)
1547 Opc = ARM_AM::rrx;
Owen Andersone0152a72011-08-09 20:55:18 +00001548 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1549
Jim Grosbache9119e42015-05-13 18:37:00 +00001550 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00001551 } else {
Jim Grosbache9119e42015-05-13 18:37:00 +00001552 Inst.addOperand(MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +00001553 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbache9119e42015-05-13 18:37:00 +00001554 Inst.addOperand(MCOperand::createImm(tmp));
Owen Andersone0152a72011-08-09 20:55:18 +00001555 }
1556
Owen Anderson03aadae2011-09-01 23:23:50 +00001557 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1558 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001559
Owen Andersona4043c42011-08-17 17:44:15 +00001560 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001561}
1562
Craig Topperf6e7e122012-03-27 07:21:54 +00001563static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001564 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001565 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001566
Jim Grosbachecaef492012-08-14 19:06:05 +00001567 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1568 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1569 unsigned type = fieldFromInstruction(Val, 5, 2);
1570 unsigned imm = fieldFromInstruction(Val, 7, 5);
1571 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001572
Owen Andersond151b092011-08-09 21:38:14 +00001573 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Andersone0152a72011-08-09 20:55:18 +00001574 switch (type) {
1575 case 0:
1576 ShOp = ARM_AM::lsl;
1577 break;
1578 case 1:
1579 ShOp = ARM_AM::lsr;
1580 break;
1581 case 2:
1582 ShOp = ARM_AM::asr;
1583 break;
1584 case 3:
1585 ShOp = ARM_AM::ror;
1586 break;
1587 }
1588
Tim Northover0c97e762012-09-22 11:18:12 +00001589 if (ShOp == ARM_AM::ror && imm == 0)
1590 ShOp = ARM_AM::rrx;
1591
Owen Anderson03aadae2011-09-01 23:23:50 +00001592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1593 return MCDisassembler::Fail;
1594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1595 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001596 unsigned shift;
1597 if (U)
1598 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1599 else
1600 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbache9119e42015-05-13 18:37:00 +00001601 Inst.addOperand(MCOperand::createImm(shift));
Owen Andersone0152a72011-08-09 20:55:18 +00001602
Owen Andersona4043c42011-08-17 17:44:15 +00001603 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001604}
1605
Owen Anderson03aadae2011-09-01 23:23:50 +00001606static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001607DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001608 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001609 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001610
Jim Grosbachecaef492012-08-14 19:06:05 +00001611 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1612 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1613 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1614 unsigned type = fieldFromInstruction(Insn, 22, 1);
1615 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1616 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1617 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1618 unsigned W = fieldFromInstruction(Insn, 21, 1);
1619 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001620 unsigned Rt2 = Rt + 1;
Owen Andersone0152a72011-08-09 20:55:18 +00001621
1622 bool writeback = (W == 1) | (P == 0);
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001623
1624 // For {LD,ST}RD, Rt must be even, else undefined.
1625 switch (Inst.getOpcode()) {
1626 case ARM::STRD:
1627 case ARM::STRD_PRE:
1628 case ARM::STRD_POST:
1629 case ARM::LDRD:
1630 case ARM::LDRD_PRE:
1631 case ARM::LDRD_POST:
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001632 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1633 break;
1634 default:
1635 break;
1636 }
1637 switch (Inst.getOpcode()) {
1638 case ARM::STRD:
1639 case ARM::STRD_PRE:
1640 case ARM::STRD_POST:
1641 if (P == 0 && W == 1)
1642 S = MCDisassembler::SoftFail;
Vinicius Tinti67cf33d2015-11-20 23:20:12 +00001643
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001644 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1645 S = MCDisassembler::SoftFail;
1646 if (type && Rm == 15)
1647 S = MCDisassembler::SoftFail;
1648 if (Rt2 == 15)
1649 S = MCDisassembler::SoftFail;
Jim Grosbachecaef492012-08-14 19:06:05 +00001650 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001651 S = MCDisassembler::SoftFail;
1652 break;
1653 case ARM::STRH:
1654 case ARM::STRH_PRE:
1655 case ARM::STRH_POST:
1656 if (Rt == 15)
1657 S = MCDisassembler::SoftFail;
1658 if (writeback && (Rn == 15 || Rn == Rt))
1659 S = MCDisassembler::SoftFail;
1660 if (!type && Rm == 15)
1661 S = MCDisassembler::SoftFail;
1662 break;
1663 case ARM::LDRD:
1664 case ARM::LDRD_PRE:
1665 case ARM::LDRD_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001666 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001667 if (Rt2 == 15)
1668 S = MCDisassembler::SoftFail;
1669 break;
1670 }
1671 if (P == 0 && W == 1)
1672 S = MCDisassembler::SoftFail;
1673 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1674 S = MCDisassembler::SoftFail;
1675 if (!type && writeback && Rn == 15)
1676 S = MCDisassembler::SoftFail;
1677 if (writeback && (Rn == Rt || Rn == Rt2))
1678 S = MCDisassembler::SoftFail;
1679 break;
1680 case ARM::LDRH:
1681 case ARM::LDRH_PRE:
1682 case ARM::LDRH_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001683 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001684 if (Rt == 15)
1685 S = MCDisassembler::SoftFail;
1686 break;
1687 }
1688 if (Rt == 15)
1689 S = MCDisassembler::SoftFail;
1690 if (!type && Rm == 15)
1691 S = MCDisassembler::SoftFail;
1692 if (!type && writeback && (Rn == 15 || Rn == Rt))
1693 S = MCDisassembler::SoftFail;
1694 break;
1695 case ARM::LDRSH:
1696 case ARM::LDRSH_PRE:
1697 case ARM::LDRSH_POST:
1698 case ARM::LDRSB:
1699 case ARM::LDRSB_PRE:
1700 case ARM::LDRSB_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001701 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001702 if (Rt == 15)
1703 S = MCDisassembler::SoftFail;
1704 break;
1705 }
1706 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1707 S = MCDisassembler::SoftFail;
1708 if (!type && (Rt == 15 || Rm == 15))
1709 S = MCDisassembler::SoftFail;
1710 if (!type && writeback && (Rn == 15 || Rn == Rt))
1711 S = MCDisassembler::SoftFail;
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001712 break;
Owen Anderson03aadae2011-09-01 23:23:50 +00001713 default:
1714 break;
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001715 }
1716
Owen Andersone0152a72011-08-09 20:55:18 +00001717 if (writeback) { // Writeback
1718 if (P)
1719 U |= ARMII::IndexModePre << 9;
1720 else
1721 U |= ARMII::IndexModePost << 9;
1722
1723 // On stores, the writeback operand precedes Rt.
1724 switch (Inst.getOpcode()) {
1725 case ARM::STRD:
1726 case ARM::STRD_PRE:
1727 case ARM::STRD_POST:
Owen Anderson60138ea2011-08-12 20:02:50 +00001728 case ARM::STRH:
1729 case ARM::STRH_PRE:
1730 case ARM::STRH_POST:
Owen Anderson03aadae2011-09-01 23:23:50 +00001731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1732 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001733 break;
1734 default:
1735 break;
1736 }
1737 }
1738
Owen Anderson03aadae2011-09-01 23:23:50 +00001739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1740 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001741 switch (Inst.getOpcode()) {
1742 case ARM::STRD:
1743 case ARM::STRD_PRE:
1744 case ARM::STRD_POST:
1745 case ARM::LDRD:
1746 case ARM::LDRD_PRE:
1747 case ARM::LDRD_POST:
Owen Anderson03aadae2011-09-01 23:23:50 +00001748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1749 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001750 break;
1751 default:
1752 break;
1753 }
1754
1755 if (writeback) {
1756 // On loads, the writeback operand comes after Rt.
1757 switch (Inst.getOpcode()) {
1758 case ARM::LDRD:
1759 case ARM::LDRD_PRE:
1760 case ARM::LDRD_POST:
Owen Anderson2d1d7a12011-08-12 20:36:11 +00001761 case ARM::LDRH:
1762 case ARM::LDRH_PRE:
1763 case ARM::LDRH_POST:
1764 case ARM::LDRSH:
1765 case ARM::LDRSH_PRE:
1766 case ARM::LDRSH_POST:
1767 case ARM::LDRSB:
1768 case ARM::LDRSB_PRE:
1769 case ARM::LDRSB_POST:
Owen Andersone0152a72011-08-09 20:55:18 +00001770 case ARM::LDRHTr:
1771 case ARM::LDRSBTr:
Owen Anderson03aadae2011-09-01 23:23:50 +00001772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1773 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001774 break;
1775 default:
1776 break;
1777 }
1778 }
1779
Owen Anderson03aadae2011-09-01 23:23:50 +00001780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1781 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001782
1783 if (type) {
Jim Grosbache9119e42015-05-13 18:37:00 +00001784 Inst.addOperand(MCOperand::createReg(0));
1785 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
Owen Andersone0152a72011-08-09 20:55:18 +00001786 } else {
Owen Anderson03aadae2011-09-01 23:23:50 +00001787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1788 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00001789 Inst.addOperand(MCOperand::createImm(U));
Owen Andersone0152a72011-08-09 20:55:18 +00001790 }
1791
Owen Anderson03aadae2011-09-01 23:23:50 +00001792 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1793 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001794
Owen Andersona4043c42011-08-17 17:44:15 +00001795 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001796}
1797
Craig Topperf6e7e122012-03-27 07:21:54 +00001798static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00001799 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001800 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001801
Jim Grosbachecaef492012-08-14 19:06:05 +00001802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1803 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00001804
1805 switch (mode) {
1806 case 0:
1807 mode = ARM_AM::da;
1808 break;
1809 case 1:
1810 mode = ARM_AM::ia;
1811 break;
1812 case 2:
1813 mode = ARM_AM::db;
1814 break;
1815 case 3:
1816 mode = ARM_AM::ib;
1817 break;
1818 }
1819
Jim Grosbache9119e42015-05-13 18:37:00 +00001820 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson03aadae2011-09-01 23:23:50 +00001821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1822 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001823
Owen Andersona4043c42011-08-17 17:44:15 +00001824 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001825}
1826
Amaury de la Vieuville631df632013-06-08 13:38:52 +00001827static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1828 uint64_t Address, const void *Decoder) {
1829 DecodeStatus S = MCDisassembler::Success;
1830
1831 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1832 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1833 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1834 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1835
1836 if (pred == 0xF)
1837 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1838
1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1840 return MCDisassembler::Fail;
1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1842 return MCDisassembler::Fail;
1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1844 return MCDisassembler::Fail;
1845 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1846 return MCDisassembler::Fail;
1847 return S;
1848}
1849
Craig Topperf6e7e122012-03-27 07:21:54 +00001850static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Andersone0152a72011-08-09 20:55:18 +00001851 unsigned Insn,
1852 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001853 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001854
Jim Grosbachecaef492012-08-14 19:06:05 +00001855 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1856 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1857 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Andersone0152a72011-08-09 20:55:18 +00001858
1859 if (pred == 0xF) {
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001860 // Ambiguous with RFE and SRS
Owen Andersone0152a72011-08-09 20:55:18 +00001861 switch (Inst.getOpcode()) {
Owen Anderson192a7602011-08-18 22:31:17 +00001862 case ARM::LDMDA:
Owen Andersone0152a72011-08-09 20:55:18 +00001863 Inst.setOpcode(ARM::RFEDA);
1864 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001865 case ARM::LDMDA_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001866 Inst.setOpcode(ARM::RFEDA_UPD);
1867 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001868 case ARM::LDMDB:
Owen Andersone0152a72011-08-09 20:55:18 +00001869 Inst.setOpcode(ARM::RFEDB);
1870 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001871 case ARM::LDMDB_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001872 Inst.setOpcode(ARM::RFEDB_UPD);
1873 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001874 case ARM::LDMIA:
Owen Andersone0152a72011-08-09 20:55:18 +00001875 Inst.setOpcode(ARM::RFEIA);
1876 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001877 case ARM::LDMIA_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001878 Inst.setOpcode(ARM::RFEIA_UPD);
1879 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001880 case ARM::LDMIB:
Owen Andersone0152a72011-08-09 20:55:18 +00001881 Inst.setOpcode(ARM::RFEIB);
1882 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001883 case ARM::LDMIB_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001884 Inst.setOpcode(ARM::RFEIB_UPD);
1885 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001886 case ARM::STMDA:
1887 Inst.setOpcode(ARM::SRSDA);
1888 break;
1889 case ARM::STMDA_UPD:
1890 Inst.setOpcode(ARM::SRSDA_UPD);
1891 break;
1892 case ARM::STMDB:
1893 Inst.setOpcode(ARM::SRSDB);
1894 break;
1895 case ARM::STMDB_UPD:
1896 Inst.setOpcode(ARM::SRSDB_UPD);
1897 break;
1898 case ARM::STMIA:
1899 Inst.setOpcode(ARM::SRSIA);
1900 break;
1901 case ARM::STMIA_UPD:
1902 Inst.setOpcode(ARM::SRSIA_UPD);
1903 break;
1904 case ARM::STMIB:
1905 Inst.setOpcode(ARM::SRSIB);
1906 break;
1907 case ARM::STMIB_UPD:
1908 Inst.setOpcode(ARM::SRSIB_UPD);
1909 break;
1910 default:
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001911 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001912 }
Owen Anderson192a7602011-08-18 22:31:17 +00001913
1914 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachecaef492012-08-14 19:06:05 +00001915 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001916 // Check SRS encoding constraints
1917 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1918 fieldFromInstruction(Insn, 20, 1) == 0))
1919 return MCDisassembler::Fail;
1920
Owen Anderson192a7602011-08-18 22:31:17 +00001921 Inst.addOperand(
Jim Grosbache9119e42015-05-13 18:37:00 +00001922 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson192a7602011-08-18 22:31:17 +00001923 return S;
1924 }
1925
Owen Andersone0152a72011-08-09 20:55:18 +00001926 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1927 }
1928
Owen Anderson03aadae2011-09-01 23:23:50 +00001929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1930 return MCDisassembler::Fail;
1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1932 return MCDisassembler::Fail; // Tied
1933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1934 return MCDisassembler::Fail;
1935 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1936 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001937
Owen Andersona4043c42011-08-17 17:44:15 +00001938 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001939}
1940
Sjoerd Meijerd906bf12016-06-03 14:03:27 +00001941// Check for UNPREDICTABLE predicated ESB instruction
1942static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1943 uint64_t Address, const void *Decoder) {
1944 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1945 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1946 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1947 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1948
1949 DecodeStatus S = MCDisassembler::Success;
1950
1951 Inst.addOperand(MCOperand::createImm(imm8));
1952
1953 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1954 return MCDisassembler::Fail;
1955
1956 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1957 // so all predicates should be allowed.
1958 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1959 S = MCDisassembler::SoftFail;
1960
1961 return S;
1962}
1963
Craig Topperf6e7e122012-03-27 07:21:54 +00001964static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00001965 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00001966 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1967 unsigned M = fieldFromInstruction(Insn, 17, 1);
1968 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1969 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00001970
Owen Anderson03aadae2011-09-01 23:23:50 +00001971 DecodeStatus S = MCDisassembler::Success;
Owen Anderson3d2e0e9d2011-08-09 23:05:39 +00001972
Amaury de la Vieuville631df632013-06-08 13:38:52 +00001973 // This decoder is called from multiple location that do not check
1974 // the full encoding is valid before they do.
1975 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1976 fieldFromInstruction(Insn, 16, 1) != 0 ||
1977 fieldFromInstruction(Insn, 20, 8) != 0x10)
1978 return MCDisassembler::Fail;
1979
Owen Anderson67d6f112011-08-18 22:11:02 +00001980 // imod == '01' --> UNPREDICTABLE
1981 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1982 // return failure here. The '01' imod value is unprintable, so there's
1983 // nothing useful we could do even if we returned UNPREDICTABLE.
1984
James Molloydb4ce602011-09-01 18:02:14 +00001985 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson67d6f112011-08-18 22:11:02 +00001986
1987 if (imod && M) {
Owen Andersone0152a72011-08-09 20:55:18 +00001988 Inst.setOpcode(ARM::CPS3p);
Jim Grosbache9119e42015-05-13 18:37:00 +00001989 Inst.addOperand(MCOperand::createImm(imod));
1990 Inst.addOperand(MCOperand::createImm(iflags));
1991 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson67d6f112011-08-18 22:11:02 +00001992 } else if (imod && !M) {
Owen Andersone0152a72011-08-09 20:55:18 +00001993 Inst.setOpcode(ARM::CPS2p);
Jim Grosbache9119e42015-05-13 18:37:00 +00001994 Inst.addOperand(MCOperand::createImm(imod));
1995 Inst.addOperand(MCOperand::createImm(iflags));
James Molloydb4ce602011-09-01 18:02:14 +00001996 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson67d6f112011-08-18 22:11:02 +00001997 } else if (!imod && M) {
Owen Andersone0152a72011-08-09 20:55:18 +00001998 Inst.setOpcode(ARM::CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00001999 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002000 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson5d2db892011-08-18 22:15:25 +00002001 } else {
Owen Anderson67d6f112011-08-18 22:11:02 +00002002 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson5d2db892011-08-18 22:15:25 +00002003 Inst.setOpcode(ARM::CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002004 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002005 S = MCDisassembler::SoftFail;
Owen Anderson5d2db892011-08-18 22:15:25 +00002006 }
Owen Andersone0152a72011-08-09 20:55:18 +00002007
Owen Anderson67d6f112011-08-18 22:11:02 +00002008 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002009}
2010
Craig Topperf6e7e122012-03-27 07:21:54 +00002011static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson9b7bd152011-08-23 17:45:18 +00002012 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00002013 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2014 unsigned M = fieldFromInstruction(Insn, 8, 1);
2015 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2016 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson9b7bd152011-08-23 17:45:18 +00002017
Owen Anderson03aadae2011-09-01 23:23:50 +00002018 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002019
2020 // imod == '01' --> UNPREDICTABLE
2021 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2022 // return failure here. The '01' imod value is unprintable, so there's
2023 // nothing useful we could do even if we returned UNPREDICTABLE.
2024
James Molloydb4ce602011-09-01 18:02:14 +00002025 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002026
2027 if (imod && M) {
2028 Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002029 Inst.addOperand(MCOperand::createImm(imod));
2030 Inst.addOperand(MCOperand::createImm(iflags));
2031 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson9b7bd152011-08-23 17:45:18 +00002032 } else if (imod && !M) {
2033 Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002034 Inst.addOperand(MCOperand::createImm(imod));
2035 Inst.addOperand(MCOperand::createImm(iflags));
James Molloydb4ce602011-09-01 18:02:14 +00002036 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002037 } else if (!imod && M) {
2038 Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002039 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002040 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002041 } else {
Quentin Colombeta83d5e92013-04-26 17:54:54 +00002042 // imod == '00' && M == '0' --> this is a HINT instruction
2043 int imm = fieldFromInstruction(Insn, 0, 8);
2044 // HINT are defined only for immediate in [0..4]
2045 if(imm > 4) return MCDisassembler::Fail;
2046 Inst.setOpcode(ARM::t2HINT);
Jim Grosbache9119e42015-05-13 18:37:00 +00002047 Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson9b7bd152011-08-23 17:45:18 +00002048 }
2049
2050 return S;
2051}
2052
Craig Topperf6e7e122012-03-27 07:21:54 +00002053static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +00002054 uint64_t Address, const void *Decoder) {
2055 DecodeStatus S = MCDisassembler::Success;
2056
Jim Grosbachecaef492012-08-14 19:06:05 +00002057 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002058 unsigned imm = 0;
2059
Jim Grosbachecaef492012-08-14 19:06:05 +00002060 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2061 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2062 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2063 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002064
2065 if (Inst.getOpcode() == ARM::t2MOVTi16)
2066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2067 return MCDisassembler::Fail;
2068 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2069 return MCDisassembler::Fail;
2070
2071 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002072 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002073
2074 return S;
2075}
2076
Craig Topperf6e7e122012-03-27 07:21:54 +00002077static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +00002078 uint64_t Address, const void *Decoder) {
2079 DecodeStatus S = MCDisassembler::Success;
2080
Jim Grosbachecaef492012-08-14 19:06:05 +00002081 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2082 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002083 unsigned imm = 0;
2084
Jim Grosbachecaef492012-08-14 19:06:05 +00002085 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2086 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002087
2088 if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northovera155ab22013-04-19 09:58:09 +00002089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby5dcda642011-10-04 22:44:48 +00002090 return MCDisassembler::Fail;
Tim Northovera155ab22013-04-19 09:58:09 +00002091
2092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby5dcda642011-10-04 22:44:48 +00002093 return MCDisassembler::Fail;
2094
2095 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002096 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002097
2098 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2099 return MCDisassembler::Fail;
2100
2101 return S;
2102}
Owen Anderson9b7bd152011-08-23 17:45:18 +00002103
Craig Topperf6e7e122012-03-27 07:21:54 +00002104static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002105 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002106 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002107
Jim Grosbachecaef492012-08-14 19:06:05 +00002108 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2109 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2110 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2111 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2112 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002113
2114 if (pred == 0xF)
2115 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2116
Owen Anderson03aadae2011-09-01 23:23:50 +00002117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2118 return MCDisassembler::Fail;
2119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2120 return MCDisassembler::Fail;
2121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2122 return MCDisassembler::Fail;
2123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2124 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002125
Owen Anderson03aadae2011-09-01 23:23:50 +00002126 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2127 return MCDisassembler::Fail;
Owen Anderson2f7aa732011-08-11 22:05:38 +00002128
Owen Andersona4043c42011-08-17 17:44:15 +00002129 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002130}
2131
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002132static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2133 uint64_t Address, const void *Decoder) {
2134 DecodeStatus S = MCDisassembler::Success;
2135
2136 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2137 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2138 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2139
2140 if (Pred == 0xF)
2141 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2142
2143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2144 return MCDisassembler::Fail;
2145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2146 return MCDisassembler::Fail;
2147 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2148 return MCDisassembler::Fail;
2149
2150 return S;
2151}
2152
2153static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2154 uint64_t Address, const void *Decoder) {
2155 DecodeStatus S = MCDisassembler::Success;
2156
2157 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2158
2159 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Michael Kupersteindb0712f2015-05-26 10:47:10 +00002160 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2161
2162 if (!FeatureBits[ARM::HasV8_1aOps] ||
2163 !FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002164 return MCDisassembler::Fail;
2165
2166 // Decoder can be called from DecodeTST, which does not check the full
2167 // encoding is valid.
2168 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2169 fieldFromInstruction(Insn, 4,4) != 0)
2170 return MCDisassembler::Fail;
2171 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2172 fieldFromInstruction(Insn, 0,4) != 0)
2173 S = MCDisassembler::SoftFail;
2174
2175 Inst.setOpcode(ARM::SETPAN);
Jim Grosbache9119e42015-05-13 18:37:00 +00002176 Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002177
2178 return S;
2179}
2180
Craig Topperf6e7e122012-03-27 07:21:54 +00002181static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002182 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002183 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002184
Jim Grosbachecaef492012-08-14 19:06:05 +00002185 unsigned add = fieldFromInstruction(Val, 12, 1);
2186 unsigned imm = fieldFromInstruction(Val, 0, 12);
2187 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002188
Owen Anderson03aadae2011-09-01 23:23:50 +00002189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2190 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002191
2192 if (!add) imm *= -1;
2193 if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbache9119e42015-05-13 18:37:00 +00002194 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002195 if (Rn == 15)
2196 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00002197
Owen Andersona4043c42011-08-17 17:44:15 +00002198 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002199}
2200
Craig Topperf6e7e122012-03-27 07:21:54 +00002201static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002202 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002203 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002204
Jim Grosbachecaef492012-08-14 19:06:05 +00002205 unsigned Rn = fieldFromInstruction(Val, 9, 4);
Oliver Stannard65b85382016-01-25 10:26:26 +00002206 // U == 1 to add imm, 0 to subtract it.
Jim Grosbachecaef492012-08-14 19:06:05 +00002207 unsigned U = fieldFromInstruction(Val, 8, 1);
2208 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00002209
Owen Anderson03aadae2011-09-01 23:23:50 +00002210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2211 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002212
2213 if (U)
Jim Grosbache9119e42015-05-13 18:37:00 +00002214 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Andersone0152a72011-08-09 20:55:18 +00002215 else
Jim Grosbache9119e42015-05-13 18:37:00 +00002216 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Andersone0152a72011-08-09 20:55:18 +00002217
Owen Andersona4043c42011-08-17 17:44:15 +00002218 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002219}
2220
Oliver Stannard65b85382016-01-25 10:26:26 +00002221static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2222 uint64_t Address, const void *Decoder) {
2223 DecodeStatus S = MCDisassembler::Success;
2224
2225 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2226 // U == 1 to add imm, 0 to subtract it.
2227 unsigned U = fieldFromInstruction(Val, 8, 1);
2228 unsigned imm = fieldFromInstruction(Val, 0, 8);
2229
2230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231 return MCDisassembler::Fail;
2232
2233 if (U)
2234 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2235 else
2236 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2237
2238 return S;
2239}
2240
Craig Topperf6e7e122012-03-27 07:21:54 +00002241static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002242 uint64_t Address, const void *Decoder) {
2243 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2244}
2245
Owen Anderson03aadae2011-09-01 23:23:50 +00002246static DecodeStatus
Kevin Enderby40d4e472012-04-12 23:13:34 +00002247DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2248 uint64_t Address, const void *Decoder) {
Kevin Enderby6fd96242012-10-29 23:27:20 +00002249 DecodeStatus Status = MCDisassembler::Success;
2250
2251 // Note the J1 and J2 values are from the encoded instruction. So here
2252 // change them to I1 and I2 values via as documented:
2253 // I1 = NOT(J1 EOR S);
2254 // I2 = NOT(J2 EOR S);
2255 // and build the imm32 with one trailing zero as documented:
2256 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2257 unsigned S = fieldFromInstruction(Insn, 26, 1);
2258 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2259 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2260 unsigned I1 = !(J1 ^ S);
2261 unsigned I2 = !(J2 ^ S);
2262 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2263 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2264 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
Amaury de la Vieuvillebd2b6102013-06-13 16:41:55 +00002265 int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby6fd96242012-10-29 23:27:20 +00002266 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00002267 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002268 Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby6fd96242012-10-29 23:27:20 +00002269
2270 return Status;
Kevin Enderby40d4e472012-04-12 23:13:34 +00002271}
2272
2273static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00002274DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00002275 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002276 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002277
Jim Grosbachecaef492012-08-14 19:06:05 +00002278 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2279 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Andersone0152a72011-08-09 20:55:18 +00002280
2281 if (pred == 0xF) {
2282 Inst.setOpcode(ARM::BLXi);
Jim Grosbachecaef492012-08-14 19:06:05 +00002283 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00002284 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2285 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002286 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Andersona4043c42011-08-17 17:44:15 +00002287 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002288 }
2289
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00002290 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2291 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002292 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson03aadae2011-09-01 23:23:50 +00002293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2294 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002295
Owen Andersona4043c42011-08-17 17:44:15 +00002296 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002297}
2298
Craig Topperf6e7e122012-03-27 07:21:54 +00002299static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002300 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002301 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002302
Jim Grosbachecaef492012-08-14 19:06:05 +00002303 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2304 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00002305
Owen Anderson03aadae2011-09-01 23:23:50 +00002306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2307 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002308 if (!align)
Jim Grosbache9119e42015-05-13 18:37:00 +00002309 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00002310 else
Jim Grosbache9119e42015-05-13 18:37:00 +00002311 Inst.addOperand(MCOperand::createImm(4 << align));
Owen Andersone0152a72011-08-09 20:55:18 +00002312
Owen Andersona4043c42011-08-17 17:44:15 +00002313 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002314}
2315
Craig Topperf6e7e122012-03-27 07:21:54 +00002316static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002317 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002318 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002319
Jim Grosbachecaef492012-08-14 19:06:05 +00002320 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2321 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2322 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2324 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002326
2327 // First output register
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002328 switch (Inst.getOpcode()) {
Jim Grosbach13a292c2012-03-06 22:01:44 +00002329 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2330 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2331 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2332 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2333 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2334 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2335 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2336 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2337 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002338 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2339 return MCDisassembler::Fail;
2340 break;
Jim Grosbache5307f92012-03-05 21:43:40 +00002341 case ARM::VLD2b16:
2342 case ARM::VLD2b32:
2343 case ARM::VLD2b8:
2344 case ARM::VLD2b16wb_fixed:
2345 case ARM::VLD2b16wb_register:
2346 case ARM::VLD2b32wb_fixed:
2347 case ARM::VLD2b32wb_register:
2348 case ARM::VLD2b8wb_fixed:
2349 case ARM::VLD2b8wb_register:
2350 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2351 return MCDisassembler::Fail;
2352 break;
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002353 default:
2354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2355 return MCDisassembler::Fail;
2356 }
Owen Andersone0152a72011-08-09 20:55:18 +00002357
2358 // Second output register
2359 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002360 case ARM::VLD3d8:
2361 case ARM::VLD3d16:
2362 case ARM::VLD3d32:
2363 case ARM::VLD3d8_UPD:
2364 case ARM::VLD3d16_UPD:
2365 case ARM::VLD3d32_UPD:
2366 case ARM::VLD4d8:
2367 case ARM::VLD4d16:
2368 case ARM::VLD4d32:
2369 case ARM::VLD4d8_UPD:
2370 case ARM::VLD4d16_UPD:
2371 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002372 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2373 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002374 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002375 case ARM::VLD3q8:
2376 case ARM::VLD3q16:
2377 case ARM::VLD3q32:
2378 case ARM::VLD3q8_UPD:
2379 case ARM::VLD3q16_UPD:
2380 case ARM::VLD3q32_UPD:
2381 case ARM::VLD4q8:
2382 case ARM::VLD4q16:
2383 case ARM::VLD4q32:
2384 case ARM::VLD4q8_UPD:
2385 case ARM::VLD4q16_UPD:
2386 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2388 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00002389 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002390 default:
2391 break;
2392 }
2393
2394 // Third output register
2395 switch(Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002396 case ARM::VLD3d8:
2397 case ARM::VLD3d16:
2398 case ARM::VLD3d32:
2399 case ARM::VLD3d8_UPD:
2400 case ARM::VLD3d16_UPD:
2401 case ARM::VLD3d32_UPD:
2402 case ARM::VLD4d8:
2403 case ARM::VLD4d16:
2404 case ARM::VLD4d32:
2405 case ARM::VLD4d8_UPD:
2406 case ARM::VLD4d16_UPD:
2407 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002408 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2409 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002410 break;
2411 case ARM::VLD3q8:
2412 case ARM::VLD3q16:
2413 case ARM::VLD3q32:
2414 case ARM::VLD3q8_UPD:
2415 case ARM::VLD3q16_UPD:
2416 case ARM::VLD3q32_UPD:
2417 case ARM::VLD4q8:
2418 case ARM::VLD4q16:
2419 case ARM::VLD4q32:
2420 case ARM::VLD4q8_UPD:
2421 case ARM::VLD4q16_UPD:
2422 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002423 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2424 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002425 break;
2426 default:
2427 break;
2428 }
2429
2430 // Fourth output register
2431 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002432 case ARM::VLD4d8:
2433 case ARM::VLD4d16:
2434 case ARM::VLD4d32:
2435 case ARM::VLD4d8_UPD:
2436 case ARM::VLD4d16_UPD:
2437 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002438 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2439 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002440 break;
2441 case ARM::VLD4q8:
2442 case ARM::VLD4q16:
2443 case ARM::VLD4q32:
2444 case ARM::VLD4q8_UPD:
2445 case ARM::VLD4q16_UPD:
2446 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002447 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2448 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002449 break;
2450 default:
2451 break;
2452 }
2453
2454 // Writeback operand
2455 switch (Inst.getOpcode()) {
Jim Grosbach2098cb12011-10-24 21:45:13 +00002456 case ARM::VLD1d8wb_fixed:
2457 case ARM::VLD1d16wb_fixed:
2458 case ARM::VLD1d32wb_fixed:
2459 case ARM::VLD1d64wb_fixed:
2460 case ARM::VLD1d8wb_register:
2461 case ARM::VLD1d16wb_register:
2462 case ARM::VLD1d32wb_register:
2463 case ARM::VLD1d64wb_register:
2464 case ARM::VLD1q8wb_fixed:
2465 case ARM::VLD1q16wb_fixed:
2466 case ARM::VLD1q32wb_fixed:
2467 case ARM::VLD1q64wb_fixed:
2468 case ARM::VLD1q8wb_register:
2469 case ARM::VLD1q16wb_register:
2470 case ARM::VLD1q32wb_register:
2471 case ARM::VLD1q64wb_register:
Jim Grosbach92fd05e2011-10-24 23:26:05 +00002472 case ARM::VLD1d8Twb_fixed:
2473 case ARM::VLD1d8Twb_register:
2474 case ARM::VLD1d16Twb_fixed:
2475 case ARM::VLD1d16Twb_register:
2476 case ARM::VLD1d32Twb_fixed:
2477 case ARM::VLD1d32Twb_register:
2478 case ARM::VLD1d64Twb_fixed:
2479 case ARM::VLD1d64Twb_register:
Jim Grosbach17ec1a12011-10-25 00:14:01 +00002480 case ARM::VLD1d8Qwb_fixed:
2481 case ARM::VLD1d8Qwb_register:
2482 case ARM::VLD1d16Qwb_fixed:
2483 case ARM::VLD1d16Qwb_register:
2484 case ARM::VLD1d32Qwb_fixed:
2485 case ARM::VLD1d32Qwb_register:
2486 case ARM::VLD1d64Qwb_fixed:
2487 case ARM::VLD1d64Qwb_register:
Jim Grosbachd146a022011-12-09 21:28:25 +00002488 case ARM::VLD2d8wb_fixed:
2489 case ARM::VLD2d16wb_fixed:
2490 case ARM::VLD2d32wb_fixed:
2491 case ARM::VLD2q8wb_fixed:
2492 case ARM::VLD2q16wb_fixed:
2493 case ARM::VLD2q32wb_fixed:
2494 case ARM::VLD2d8wb_register:
2495 case ARM::VLD2d16wb_register:
2496 case ARM::VLD2d32wb_register:
2497 case ARM::VLD2q8wb_register:
2498 case ARM::VLD2q16wb_register:
2499 case ARM::VLD2q32wb_register:
2500 case ARM::VLD2b8wb_fixed:
2501 case ARM::VLD2b16wb_fixed:
2502 case ARM::VLD2b32wb_fixed:
2503 case ARM::VLD2b8wb_register:
2504 case ARM::VLD2b16wb_register:
2505 case ARM::VLD2b32wb_register:
Jim Grosbache9119e42015-05-13 18:37:00 +00002506 Inst.addOperand(MCOperand::createImm(0));
Kevin Enderbyd2980cd2012-04-11 00:25:40 +00002507 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002508 case ARM::VLD3d8_UPD:
2509 case ARM::VLD3d16_UPD:
2510 case ARM::VLD3d32_UPD:
2511 case ARM::VLD3q8_UPD:
2512 case ARM::VLD3q16_UPD:
2513 case ARM::VLD3q32_UPD:
2514 case ARM::VLD4d8_UPD:
2515 case ARM::VLD4d16_UPD:
2516 case ARM::VLD4d32_UPD:
2517 case ARM::VLD4q8_UPD:
2518 case ARM::VLD4q16_UPD:
2519 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002520 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2521 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002522 break;
2523 default:
2524 break;
2525 }
2526
2527 // AddrMode6 Base (register+alignment)
Owen Anderson03aadae2011-09-01 23:23:50 +00002528 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2529 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002530
2531 // AddrMode6 Offset (register)
Jim Grosbach2098cb12011-10-24 21:45:13 +00002532 switch (Inst.getOpcode()) {
2533 default:
2534 // The below have been updated to have explicit am6offset split
2535 // between fixed and register offset. For those instructions not
2536 // yet updated, we need to add an additional reg0 operand for the
2537 // fixed variant.
2538 //
2539 // The fixed offset encodes as Rm == 0xd, so we check for that.
2540 if (Rm == 0xd) {
Jim Grosbache9119e42015-05-13 18:37:00 +00002541 Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach2098cb12011-10-24 21:45:13 +00002542 break;
2543 }
2544 // Fall through to handle the register offset variant.
Justin Bognercd1d5aa2016-08-17 20:30:52 +00002545 LLVM_FALLTHROUGH;
Jim Grosbach2098cb12011-10-24 21:45:13 +00002546 case ARM::VLD1d8wb_fixed:
2547 case ARM::VLD1d16wb_fixed:
2548 case ARM::VLD1d32wb_fixed:
2549 case ARM::VLD1d64wb_fixed:
Owen Anderson8a6ebd02011-10-27 22:53:10 +00002550 case ARM::VLD1d8Twb_fixed:
2551 case ARM::VLD1d16Twb_fixed:
2552 case ARM::VLD1d32Twb_fixed:
2553 case ARM::VLD1d64Twb_fixed:
Owen Anderson40703f42011-10-31 17:17:32 +00002554 case ARM::VLD1d8Qwb_fixed:
2555 case ARM::VLD1d16Qwb_fixed:
2556 case ARM::VLD1d32Qwb_fixed:
2557 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach2098cb12011-10-24 21:45:13 +00002558 case ARM::VLD1d8wb_register:
2559 case ARM::VLD1d16wb_register:
2560 case ARM::VLD1d32wb_register:
2561 case ARM::VLD1d64wb_register:
2562 case ARM::VLD1q8wb_fixed:
2563 case ARM::VLD1q16wb_fixed:
2564 case ARM::VLD1q32wb_fixed:
2565 case ARM::VLD1q64wb_fixed:
2566 case ARM::VLD1q8wb_register:
2567 case ARM::VLD1q16wb_register:
2568 case ARM::VLD1q32wb_register:
2569 case ARM::VLD1q64wb_register:
2570 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2571 // variant encodes Rm == 0xf. Anything else is a register offset post-
2572 // increment and we need to add the register operand to the instruction.
2573 if (Rm != 0xD && Rm != 0xF &&
2574 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00002575 return MCDisassembler::Fail;
Jim Grosbach2098cb12011-10-24 21:45:13 +00002576 break;
Kevin Enderbyd2980cd2012-04-11 00:25:40 +00002577 case ARM::VLD2d8wb_fixed:
2578 case ARM::VLD2d16wb_fixed:
2579 case ARM::VLD2d32wb_fixed:
2580 case ARM::VLD2b8wb_fixed:
2581 case ARM::VLD2b16wb_fixed:
2582 case ARM::VLD2b32wb_fixed:
2583 case ARM::VLD2q8wb_fixed:
2584 case ARM::VLD2q16wb_fixed:
2585 case ARM::VLD2q32wb_fixed:
2586 break;
Owen Andersoned253852011-08-11 18:24:51 +00002587 }
Owen Andersone0152a72011-08-09 20:55:18 +00002588
Owen Andersona4043c42011-08-17 17:44:15 +00002589 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002590}
2591
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002592static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2593 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002594 unsigned type = fieldFromInstruction(Insn, 8, 4);
2595 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002596 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2597 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2598 if (type == 10 && align == 3) return MCDisassembler::Fail;
2599
2600 unsigned load = fieldFromInstruction(Insn, 21, 1);
2601 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2602 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002603}
2604
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002605static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2606 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002607 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002608 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002609
2610 unsigned type = fieldFromInstruction(Insn, 8, 4);
2611 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002612 if (type == 8 && align == 3) return MCDisassembler::Fail;
2613 if (type == 9 && align == 3) return MCDisassembler::Fail;
2614
2615 unsigned load = fieldFromInstruction(Insn, 21, 1);
2616 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2617 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002618}
2619
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002620static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2621 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002622 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002623 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002624
2625 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002626 if (align & 2) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002627
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002628 unsigned load = fieldFromInstruction(Insn, 21, 1);
2629 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2630 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002631}
2632
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002633static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2634 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002635 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002636 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002637
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002638 unsigned load = fieldFromInstruction(Insn, 21, 1);
2639 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2640 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002641}
2642
Craig Topperf6e7e122012-03-27 07:21:54 +00002643static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002644 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002645 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002646
Jim Grosbachecaef492012-08-14 19:06:05 +00002647 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2648 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2649 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2650 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2651 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2652 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002653
2654 // Writeback Operand
2655 switch (Inst.getOpcode()) {
Jim Grosbach05df4602011-10-31 21:50:31 +00002656 case ARM::VST1d8wb_fixed:
2657 case ARM::VST1d16wb_fixed:
2658 case ARM::VST1d32wb_fixed:
2659 case ARM::VST1d64wb_fixed:
2660 case ARM::VST1d8wb_register:
2661 case ARM::VST1d16wb_register:
2662 case ARM::VST1d32wb_register:
2663 case ARM::VST1d64wb_register:
2664 case ARM::VST1q8wb_fixed:
2665 case ARM::VST1q16wb_fixed:
2666 case ARM::VST1q32wb_fixed:
2667 case ARM::VST1q64wb_fixed:
2668 case ARM::VST1q8wb_register:
2669 case ARM::VST1q16wb_register:
2670 case ARM::VST1q32wb_register:
2671 case ARM::VST1q64wb_register:
Jim Grosbach98d032f2011-11-29 22:38:04 +00002672 case ARM::VST1d8Twb_fixed:
2673 case ARM::VST1d16Twb_fixed:
2674 case ARM::VST1d32Twb_fixed:
2675 case ARM::VST1d64Twb_fixed:
2676 case ARM::VST1d8Twb_register:
2677 case ARM::VST1d16Twb_register:
2678 case ARM::VST1d32Twb_register:
2679 case ARM::VST1d64Twb_register:
Jim Grosbach5ee209c2011-11-29 22:58:48 +00002680 case ARM::VST1d8Qwb_fixed:
2681 case ARM::VST1d16Qwb_fixed:
2682 case ARM::VST1d32Qwb_fixed:
2683 case ARM::VST1d64Qwb_fixed:
2684 case ARM::VST1d8Qwb_register:
2685 case ARM::VST1d16Qwb_register:
2686 case ARM::VST1d32Qwb_register:
2687 case ARM::VST1d64Qwb_register:
Jim Grosbach88ac7612011-12-14 21:32:11 +00002688 case ARM::VST2d8wb_fixed:
2689 case ARM::VST2d16wb_fixed:
2690 case ARM::VST2d32wb_fixed:
2691 case ARM::VST2d8wb_register:
2692 case ARM::VST2d16wb_register:
2693 case ARM::VST2d32wb_register:
2694 case ARM::VST2q8wb_fixed:
2695 case ARM::VST2q16wb_fixed:
2696 case ARM::VST2q32wb_fixed:
2697 case ARM::VST2q8wb_register:
2698 case ARM::VST2q16wb_register:
2699 case ARM::VST2q32wb_register:
2700 case ARM::VST2b8wb_fixed:
2701 case ARM::VST2b16wb_fixed:
2702 case ARM::VST2b32wb_fixed:
2703 case ARM::VST2b8wb_register:
2704 case ARM::VST2b16wb_register:
2705 case ARM::VST2b32wb_register:
Kevin Enderby72f18bb2012-04-11 22:40:17 +00002706 if (Rm == 0xF)
2707 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00002708 Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby7e7d5ee2012-03-21 20:54:32 +00002709 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002710 case ARM::VST3d8_UPD:
2711 case ARM::VST3d16_UPD:
2712 case ARM::VST3d32_UPD:
2713 case ARM::VST3q8_UPD:
2714 case ARM::VST3q16_UPD:
2715 case ARM::VST3q32_UPD:
2716 case ARM::VST4d8_UPD:
2717 case ARM::VST4d16_UPD:
2718 case ARM::VST4d32_UPD:
2719 case ARM::VST4q8_UPD:
2720 case ARM::VST4q16_UPD:
2721 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002722 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2723 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002724 break;
2725 default:
2726 break;
2727 }
2728
2729 // AddrMode6 Base (register+alignment)
Owen Anderson03aadae2011-09-01 23:23:50 +00002730 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2731 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002732
2733 // AddrMode6 Offset (register)
Owen Anderson69e54a72011-11-01 22:18:13 +00002734 switch (Inst.getOpcode()) {
2735 default:
2736 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00002737 Inst.addOperand(MCOperand::createReg(0));
Owen Anderson69e54a72011-11-01 22:18:13 +00002738 else if (Rm != 0xF) {
2739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2740 return MCDisassembler::Fail;
2741 }
2742 break;
2743 case ARM::VST1d8wb_fixed:
2744 case ARM::VST1d16wb_fixed:
2745 case ARM::VST1d32wb_fixed:
2746 case ARM::VST1d64wb_fixed:
2747 case ARM::VST1q8wb_fixed:
2748 case ARM::VST1q16wb_fixed:
2749 case ARM::VST1q32wb_fixed:
2750 case ARM::VST1q64wb_fixed:
Kevin Enderby7e7d5ee2012-03-21 20:54:32 +00002751 case ARM::VST1d8Twb_fixed:
2752 case ARM::VST1d16Twb_fixed:
2753 case ARM::VST1d32Twb_fixed:
2754 case ARM::VST1d64Twb_fixed:
2755 case ARM::VST1d8Qwb_fixed:
2756 case ARM::VST1d16Qwb_fixed:
2757 case ARM::VST1d32Qwb_fixed:
2758 case ARM::VST1d64Qwb_fixed:
2759 case ARM::VST2d8wb_fixed:
2760 case ARM::VST2d16wb_fixed:
2761 case ARM::VST2d32wb_fixed:
2762 case ARM::VST2q8wb_fixed:
2763 case ARM::VST2q16wb_fixed:
2764 case ARM::VST2q32wb_fixed:
2765 case ARM::VST2b8wb_fixed:
2766 case ARM::VST2b16wb_fixed:
2767 case ARM::VST2b32wb_fixed:
Owen Anderson69e54a72011-11-01 22:18:13 +00002768 break;
Owen Andersoned253852011-08-11 18:24:51 +00002769 }
Owen Andersone0152a72011-08-09 20:55:18 +00002770
2771 // First input register
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002772 switch (Inst.getOpcode()) {
2773 case ARM::VST1q16:
2774 case ARM::VST1q32:
2775 case ARM::VST1q64:
2776 case ARM::VST1q8:
2777 case ARM::VST1q16wb_fixed:
2778 case ARM::VST1q16wb_register:
2779 case ARM::VST1q32wb_fixed:
2780 case ARM::VST1q32wb_register:
2781 case ARM::VST1q64wb_fixed:
2782 case ARM::VST1q64wb_register:
2783 case ARM::VST1q8wb_fixed:
2784 case ARM::VST1q8wb_register:
2785 case ARM::VST2d16:
2786 case ARM::VST2d32:
2787 case ARM::VST2d8:
2788 case ARM::VST2d16wb_fixed:
2789 case ARM::VST2d16wb_register:
2790 case ARM::VST2d32wb_fixed:
2791 case ARM::VST2d32wb_register:
2792 case ARM::VST2d8wb_fixed:
2793 case ARM::VST2d8wb_register:
2794 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2795 return MCDisassembler::Fail;
2796 break;
Jim Grosbache5307f92012-03-05 21:43:40 +00002797 case ARM::VST2b16:
2798 case ARM::VST2b32:
2799 case ARM::VST2b8:
2800 case ARM::VST2b16wb_fixed:
2801 case ARM::VST2b16wb_register:
2802 case ARM::VST2b32wb_fixed:
2803 case ARM::VST2b32wb_register:
2804 case ARM::VST2b8wb_fixed:
2805 case ARM::VST2b8wb_register:
2806 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2807 return MCDisassembler::Fail;
2808 break;
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002809 default:
2810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2811 return MCDisassembler::Fail;
2812 }
Owen Andersone0152a72011-08-09 20:55:18 +00002813
2814 // Second input register
2815 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002816 case ARM::VST3d8:
2817 case ARM::VST3d16:
2818 case ARM::VST3d32:
2819 case ARM::VST3d8_UPD:
2820 case ARM::VST3d16_UPD:
2821 case ARM::VST3d32_UPD:
2822 case ARM::VST4d8:
2823 case ARM::VST4d16:
2824 case ARM::VST4d32:
2825 case ARM::VST4d8_UPD:
2826 case ARM::VST4d16_UPD:
2827 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002828 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2829 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002830 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002831 case ARM::VST3q8:
2832 case ARM::VST3q16:
2833 case ARM::VST3q32:
2834 case ARM::VST3q8_UPD:
2835 case ARM::VST3q16_UPD:
2836 case ARM::VST3q32_UPD:
2837 case ARM::VST4q8:
2838 case ARM::VST4q16:
2839 case ARM::VST4q32:
2840 case ARM::VST4q8_UPD:
2841 case ARM::VST4q16_UPD:
2842 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002843 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2844 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002845 break;
2846 default:
2847 break;
2848 }
2849
2850 // Third input register
2851 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002852 case ARM::VST3d8:
2853 case ARM::VST3d16:
2854 case ARM::VST3d32:
2855 case ARM::VST3d8_UPD:
2856 case ARM::VST3d16_UPD:
2857 case ARM::VST3d32_UPD:
2858 case ARM::VST4d8:
2859 case ARM::VST4d16:
2860 case ARM::VST4d32:
2861 case ARM::VST4d8_UPD:
2862 case ARM::VST4d16_UPD:
2863 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2865 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002866 break;
2867 case ARM::VST3q8:
2868 case ARM::VST3q16:
2869 case ARM::VST3q32:
2870 case ARM::VST3q8_UPD:
2871 case ARM::VST3q16_UPD:
2872 case ARM::VST3q32_UPD:
2873 case ARM::VST4q8:
2874 case ARM::VST4q16:
2875 case ARM::VST4q32:
2876 case ARM::VST4q8_UPD:
2877 case ARM::VST4q16_UPD:
2878 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002879 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2880 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002881 break;
2882 default:
2883 break;
2884 }
2885
2886 // Fourth input register
2887 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002888 case ARM::VST4d8:
2889 case ARM::VST4d16:
2890 case ARM::VST4d32:
2891 case ARM::VST4d8_UPD:
2892 case ARM::VST4d16_UPD:
2893 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002894 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2895 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002896 break;
2897 case ARM::VST4q8:
2898 case ARM::VST4q16:
2899 case ARM::VST4q32:
2900 case ARM::VST4q8_UPD:
2901 case ARM::VST4q16_UPD:
2902 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002903 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2904 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002905 break;
2906 default:
2907 break;
2908 }
2909
Owen Andersona4043c42011-08-17 17:44:15 +00002910 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002911}
2912
Craig Topperf6e7e122012-03-27 07:21:54 +00002913static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002914 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002915 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002916
Jim Grosbachecaef492012-08-14 19:06:05 +00002917 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2918 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2919 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2920 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2921 unsigned align = fieldFromInstruction(Insn, 4, 1);
2922 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00002923
Tim Northover00e071a2012-09-06 15:27:12 +00002924 if (size == 0 && align == 1)
2925 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002926 align *= (1 << size);
2927
Jim Grosbach13a292c2012-03-06 22:01:44 +00002928 switch (Inst.getOpcode()) {
2929 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2930 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2931 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2932 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2933 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2934 return MCDisassembler::Fail;
2935 break;
2936 default:
2937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2938 return MCDisassembler::Fail;
2939 break;
2940 }
Owen Andersonac92e772011-08-22 18:22:06 +00002941 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2943 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00002944 }
Owen Andersone0152a72011-08-09 20:55:18 +00002945
Owen Anderson03aadae2011-09-01 23:23:50 +00002946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2947 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00002948 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00002949
Jim Grosbacha68c9a82011-11-30 19:35:44 +00002950 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2951 // variant encodes Rm == 0xf. Anything else is a register offset post-
2952 // increment and we need to add the register operand to the instruction.
2953 if (Rm != 0xD && Rm != 0xF &&
2954 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2955 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002956
Owen Andersona4043c42011-08-17 17:44:15 +00002957 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002958}
2959
Craig Topperf6e7e122012-03-27 07:21:54 +00002960static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002961 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002962 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002963
Jim Grosbachecaef492012-08-14 19:06:05 +00002964 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2965 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2966 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2967 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2968 unsigned align = fieldFromInstruction(Insn, 4, 1);
2969 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00002970 align *= 2*size;
2971
Jim Grosbach13a292c2012-03-06 22:01:44 +00002972 switch (Inst.getOpcode()) {
2973 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2974 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2975 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2976 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2977 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2978 return MCDisassembler::Fail;
2979 break;
Jim Grosbached428bc2012-03-06 23:10:38 +00002980 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2981 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2982 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2983 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2984 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2985 return MCDisassembler::Fail;
2986 break;
Jim Grosbach13a292c2012-03-06 22:01:44 +00002987 default:
2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2989 return MCDisassembler::Fail;
2990 break;
2991 }
Kevin Enderby520eb3b2012-03-06 18:33:12 +00002992
2993 if (Rm != 0xF)
Jim Grosbache9119e42015-05-13 18:37:00 +00002994 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00002995
Owen Anderson03aadae2011-09-01 23:23:50 +00002996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2997 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00002998 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00002999
Kevin Enderby29ae5382012-04-17 00:49:27 +00003000 if (Rm != 0xD && Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3002 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003003 }
Owen Andersone0152a72011-08-09 20:55:18 +00003004
Owen Andersona4043c42011-08-17 17:44:15 +00003005 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003006}
3007
Craig Topperf6e7e122012-03-27 07:21:54 +00003008static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003009 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003010 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003011
Jim Grosbachecaef492012-08-14 19:06:05 +00003012 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3013 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3014 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3015 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3016 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Andersone0152a72011-08-09 20:55:18 +00003017
Owen Anderson03aadae2011-09-01 23:23:50 +00003018 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3019 return MCDisassembler::Fail;
3020 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3021 return MCDisassembler::Fail;
3022 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3023 return MCDisassembler::Fail;
Owen Andersonac92e772011-08-22 18:22:06 +00003024 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3026 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003027 }
Owen Andersone0152a72011-08-09 20:55:18 +00003028
Owen Anderson03aadae2011-09-01 23:23:50 +00003029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3030 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003031 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00003032
3033 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00003034 Inst.addOperand(MCOperand::createReg(0));
Owen Andersoned253852011-08-11 18:24:51 +00003035 else if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3037 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003038 }
Owen Andersone0152a72011-08-09 20:55:18 +00003039
Owen Andersona4043c42011-08-17 17:44:15 +00003040 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003041}
3042
Craig Topperf6e7e122012-03-27 07:21:54 +00003043static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003044 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003045 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003046
Jim Grosbachecaef492012-08-14 19:06:05 +00003047 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3048 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3049 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3050 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3051 unsigned size = fieldFromInstruction(Insn, 6, 2);
3052 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3053 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003054
3055 if (size == 0x3) {
Tim Northover00e071a2012-09-06 15:27:12 +00003056 if (align == 0)
3057 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003058 align = 16;
3059 } else {
3060 if (size == 2) {
Owen Andersone0152a72011-08-09 20:55:18 +00003061 align *= 8;
3062 } else {
3063 size = 1 << size;
3064 align *= 4*size;
3065 }
3066 }
3067
Owen Anderson03aadae2011-09-01 23:23:50 +00003068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3069 return MCDisassembler::Fail;
3070 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3071 return MCDisassembler::Fail;
3072 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3073 return MCDisassembler::Fail;
3074 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3075 return MCDisassembler::Fail;
Owen Andersonac92e772011-08-22 18:22:06 +00003076 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003079 }
Owen Andersone0152a72011-08-09 20:55:18 +00003080
Owen Anderson03aadae2011-09-01 23:23:50 +00003081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3082 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003083 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00003084
3085 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00003086 Inst.addOperand(MCOperand::createReg(0));
Owen Andersoned253852011-08-11 18:24:51 +00003087 else if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3089 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003090 }
Owen Andersone0152a72011-08-09 20:55:18 +00003091
Owen Andersona4043c42011-08-17 17:44:15 +00003092 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003093}
3094
Owen Anderson03aadae2011-09-01 23:23:50 +00003095static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00003096DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00003097 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003098 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003099
Jim Grosbachecaef492012-08-14 19:06:05 +00003100 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3101 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3102 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3103 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3104 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3105 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3106 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3107 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003108
Owen Andersoned253852011-08-11 18:24:51 +00003109 if (Q) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003110 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3111 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003112 } else {
Owen Anderson03aadae2011-09-01 23:23:50 +00003113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3114 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003115 }
Owen Andersone0152a72011-08-09 20:55:18 +00003116
Jim Grosbache9119e42015-05-13 18:37:00 +00003117 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003118
3119 switch (Inst.getOpcode()) {
3120 case ARM::VORRiv4i16:
3121 case ARM::VORRiv2i32:
3122 case ARM::VBICiv4i16:
3123 case ARM::VBICiv2i32:
Owen Anderson03aadae2011-09-01 23:23:50 +00003124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3125 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003126 break;
3127 case ARM::VORRiv8i16:
3128 case ARM::VORRiv4i32:
3129 case ARM::VBICiv8i16:
3130 case ARM::VBICiv4i32:
Owen Anderson03aadae2011-09-01 23:23:50 +00003131 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3132 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003133 break;
3134 default:
3135 break;
3136 }
3137
Owen Andersona4043c42011-08-17 17:44:15 +00003138 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003139}
3140
Craig Topperf6e7e122012-03-27 07:21:54 +00003141static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003142 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003143 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003144
Jim Grosbachecaef492012-08-14 19:06:05 +00003145 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3146 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3147 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3148 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3149 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00003150
Owen Anderson03aadae2011-09-01 23:23:50 +00003151 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3152 return MCDisassembler::Fail;
3153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3154 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003155 Inst.addOperand(MCOperand::createImm(8 << size));
Owen Andersone0152a72011-08-09 20:55:18 +00003156
Owen Andersona4043c42011-08-17 17:44:15 +00003157 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003158}
3159
Craig Topperf6e7e122012-03-27 07:21:54 +00003160static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003161 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003162 Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003163 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003164}
3165
Craig Topperf6e7e122012-03-27 07:21:54 +00003166static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003167 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003168 Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003169 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003170}
3171
Craig Topperf6e7e122012-03-27 07:21:54 +00003172static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003173 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003174 Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003175 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003176}
3177
Craig Topperf6e7e122012-03-27 07:21:54 +00003178static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003179 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003180 Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003181 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003182}
3183
Craig Topperf6e7e122012-03-27 07:21:54 +00003184static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003185 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003186 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003187
Jim Grosbachecaef492012-08-14 19:06:05 +00003188 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3189 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3190 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3191 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3192 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3193 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3194 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003195
Owen Anderson03aadae2011-09-01 23:23:50 +00003196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3197 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003198 if (op) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3200 return MCDisassembler::Fail; // Writeback
Owen Andersoned253852011-08-11 18:24:51 +00003201 }
Owen Andersone0152a72011-08-09 20:55:18 +00003202
Jim Grosbachc988e0c2012-03-05 19:33:30 +00003203 switch (Inst.getOpcode()) {
3204 case ARM::VTBL2:
3205 case ARM::VTBX2:
3206 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3207 return MCDisassembler::Fail;
3208 break;
3209 default:
3210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3211 return MCDisassembler::Fail;
3212 }
Owen Andersone0152a72011-08-09 20:55:18 +00003213
Owen Anderson03aadae2011-09-01 23:23:50 +00003214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3215 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003216
Owen Andersona4043c42011-08-17 17:44:15 +00003217 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003218}
3219
Craig Topperf6e7e122012-03-27 07:21:54 +00003220static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003221 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003222 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003223
Jim Grosbachecaef492012-08-14 19:06:05 +00003224 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3225 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00003226
Owen Anderson03aadae2011-09-01 23:23:50 +00003227 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3228 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003229
Owen Andersona01bcbf2011-08-26 18:09:22 +00003230 switch(Inst.getOpcode()) {
Owen Anderson5658b492011-08-26 19:39:26 +00003231 default:
James Molloydb4ce602011-09-01 18:02:14 +00003232 return MCDisassembler::Fail;
Owen Andersona01bcbf2011-08-26 18:09:22 +00003233 case ARM::tADR:
Owen Anderson240d20a2011-08-26 21:47:57 +00003234 break; // tADR does not explicitly represent the PC as an operand.
Owen Andersona01bcbf2011-08-26 18:09:22 +00003235 case ARM::tADDrSPi:
Jim Grosbache9119e42015-05-13 18:37:00 +00003236 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Andersona01bcbf2011-08-26 18:09:22 +00003237 break;
Owen Andersona01bcbf2011-08-26 18:09:22 +00003238 }
Owen Andersone0152a72011-08-09 20:55:18 +00003239
Jim Grosbache9119e42015-05-13 18:37:00 +00003240 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersona4043c42011-08-17 17:44:15 +00003241 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003242}
3243
Craig Topperf6e7e122012-03-27 07:21:54 +00003244static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003245 uint64_t Address, const void *Decoder) {
Kevin Enderby40d4e472012-04-12 23:13:34 +00003246 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3247 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003248 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloydb4ce602011-09-01 18:02:14 +00003249 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003250}
3251
Craig Topperf6e7e122012-03-27 07:21:54 +00003252static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003253 uint64_t Address, const void *Decoder) {
Kevin Enderbycabbae62012-05-04 22:09:52 +00003254 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00003255 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003256 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloydb4ce602011-09-01 18:02:14 +00003257 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003258}
3259
Craig Topperf6e7e122012-03-27 07:21:54 +00003260static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003261 uint64_t Address, const void *Decoder) {
Gordon Keiser772cf462013-03-28 19:22:28 +00003262 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00003263 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003264 Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloydb4ce602011-09-01 18:02:14 +00003265 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003266}
3267
Craig Topperf6e7e122012-03-27 07:21:54 +00003268static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003269 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003270 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003271
Jim Grosbachecaef492012-08-14 19:06:05 +00003272 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3273 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Andersone0152a72011-08-09 20:55:18 +00003274
Owen Anderson03aadae2011-09-01 23:23:50 +00003275 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3276 return MCDisassembler::Fail;
3277 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3278 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003279
Owen Andersona4043c42011-08-17 17:44:15 +00003280 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003281}
3282
Craig Topperf6e7e122012-03-27 07:21:54 +00003283static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003284 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003285 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003286
Jim Grosbachecaef492012-08-14 19:06:05 +00003287 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3288 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00003289
Owen Anderson03aadae2011-09-01 23:23:50 +00003290 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3291 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003292 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003293
Owen Andersona4043c42011-08-17 17:44:15 +00003294 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003295}
3296
Craig Topperf6e7e122012-03-27 07:21:54 +00003297static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003298 uint64_t Address, const void *Decoder) {
Kevin Enderby5dcda642011-10-04 22:44:48 +00003299 unsigned imm = Val << 2;
3300
Jim Grosbache9119e42015-05-13 18:37:00 +00003301 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00003302 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00003303
James Molloydb4ce602011-09-01 18:02:14 +00003304 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003305}
3306
Craig Topperf6e7e122012-03-27 07:21:54 +00003307static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003308 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003309 Inst.addOperand(MCOperand::createReg(ARM::SP));
3310 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersone0152a72011-08-09 20:55:18 +00003311
James Molloydb4ce602011-09-01 18:02:14 +00003312 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003313}
3314
Craig Topperf6e7e122012-03-27 07:21:54 +00003315static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003316 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003317 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003318
Jim Grosbachecaef492012-08-14 19:06:05 +00003319 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3320 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3321 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00003322
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003323 // Thumb stores cannot use PC as dest register.
3324 switch (Inst.getOpcode()) {
3325 case ARM::t2STRHs:
3326 case ARM::t2STRBs:
3327 case ARM::t2STRs:
3328 if (Rn == 15)
3329 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003330 break;
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003331 default:
3332 break;
3333 }
3334
Owen Anderson03aadae2011-09-01 23:23:50 +00003335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3336 return MCDisassembler::Fail;
3337 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3338 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003339 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003340
Owen Andersona4043c42011-08-17 17:44:15 +00003341 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003342}
3343
Craig Topperf6e7e122012-03-27 07:21:54 +00003344static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003345 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003346 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003347
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003348 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbachecaef492012-08-14 19:06:05 +00003349 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003350
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003351 const FeatureBitset &featureBits =
3352 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3353
3354 bool hasMP = featureBits[ARM::FeatureMP];
3355 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003356
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003357 if (Rn == 15) {
Owen Andersone0152a72011-08-09 20:55:18 +00003358 switch (Inst.getOpcode()) {
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003359 case ARM::t2LDRBs:
3360 Inst.setOpcode(ARM::t2LDRBpci);
3361 break;
3362 case ARM::t2LDRHs:
3363 Inst.setOpcode(ARM::t2LDRHpci);
3364 break;
3365 case ARM::t2LDRSHs:
3366 Inst.setOpcode(ARM::t2LDRSHpci);
3367 break;
3368 case ARM::t2LDRSBs:
3369 Inst.setOpcode(ARM::t2LDRSBpci);
3370 break;
3371 case ARM::t2LDRs:
3372 Inst.setOpcode(ARM::t2LDRpci);
3373 break;
3374 case ARM::t2PLDs:
3375 Inst.setOpcode(ARM::t2PLDpci);
3376 break;
3377 case ARM::t2PLIs:
3378 Inst.setOpcode(ARM::t2PLIpci);
3379 break;
3380 default:
3381 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003382 }
3383
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003384 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3385 }
Owen Andersone0152a72011-08-09 20:55:18 +00003386
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003387 if (Rt == 15) {
3388 switch (Inst.getOpcode()) {
3389 case ARM::t2LDRSHs:
3390 return MCDisassembler::Fail;
3391 case ARM::t2LDRHs:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003392 Inst.setOpcode(ARM::t2PLDWs);
3393 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003394 case ARM::t2LDRSBs:
3395 Inst.setOpcode(ARM::t2PLIs);
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003396 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003397 default:
3398 break;
3399 }
3400 }
3401
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003402 switch (Inst.getOpcode()) {
3403 case ARM::t2PLDs:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003404 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003405 case ARM::t2PLIs:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003406 if (!hasV7Ops)
3407 return MCDisassembler::Fail;
3408 break;
3409 case ARM::t2PLDWs:
3410 if (!hasV7Ops || !hasMP)
3411 return MCDisassembler::Fail;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003412 break;
3413 default:
3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3415 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003416 }
3417
Jim Grosbachecaef492012-08-14 19:06:05 +00003418 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3419 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3420 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson03aadae2011-09-01 23:23:50 +00003421 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3422 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003423
Owen Andersona4043c42011-08-17 17:44:15 +00003424 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003425}
3426
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003427static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3428 uint64_t Address, const void* Decoder) {
3429 DecodeStatus S = MCDisassembler::Success;
3430
3431 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3432 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3433 unsigned U = fieldFromInstruction(Insn, 9, 1);
3434 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3435 imm |= (U << 8);
3436 imm |= (Rn << 9);
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003437 unsigned add = fieldFromInstruction(Insn, 9, 1);
3438
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003439 const FeatureBitset &featureBits =
3440 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3441
3442 bool hasMP = featureBits[ARM::FeatureMP];
3443 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003444
3445 if (Rn == 15) {
3446 switch (Inst.getOpcode()) {
3447 case ARM::t2LDRi8:
3448 Inst.setOpcode(ARM::t2LDRpci);
3449 break;
3450 case ARM::t2LDRBi8:
3451 Inst.setOpcode(ARM::t2LDRBpci);
3452 break;
3453 case ARM::t2LDRSBi8:
3454 Inst.setOpcode(ARM::t2LDRSBpci);
3455 break;
3456 case ARM::t2LDRHi8:
3457 Inst.setOpcode(ARM::t2LDRHpci);
3458 break;
3459 case ARM::t2LDRSHi8:
3460 Inst.setOpcode(ARM::t2LDRSHpci);
3461 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003462 case ARM::t2PLDi8:
3463 Inst.setOpcode(ARM::t2PLDpci);
3464 break;
3465 case ARM::t2PLIi8:
3466 Inst.setOpcode(ARM::t2PLIpci);
3467 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003468 default:
3469 return MCDisassembler::Fail;
3470 }
3471 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3472 }
3473
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003474 if (Rt == 15) {
3475 switch (Inst.getOpcode()) {
3476 case ARM::t2LDRSHi8:
3477 return MCDisassembler::Fail;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003478 case ARM::t2LDRHi8:
3479 if (!add)
3480 Inst.setOpcode(ARM::t2PLDWi8);
3481 break;
3482 case ARM::t2LDRSBi8:
3483 Inst.setOpcode(ARM::t2PLIi8);
3484 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003485 default:
3486 break;
3487 }
3488 }
3489
3490 switch (Inst.getOpcode()) {
3491 case ARM::t2PLDi8:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003492 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003493 case ARM::t2PLIi8:
3494 if (!hasV7Ops)
3495 return MCDisassembler::Fail;
3496 break;
3497 case ARM::t2PLDWi8:
3498 if (!hasV7Ops || !hasMP)
3499 return MCDisassembler::Fail;
3500 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003501 default:
3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3503 return MCDisassembler::Fail;
3504 }
3505
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003506 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3507 return MCDisassembler::Fail;
3508 return S;
3509}
3510
3511static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3512 uint64_t Address, const void* Decoder) {
3513 DecodeStatus S = MCDisassembler::Success;
3514
3515 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3516 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3517 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3518 imm |= (Rn << 13);
3519
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003520 const FeatureBitset &featureBits =
3521 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3522
3523 bool hasMP = featureBits[ARM::FeatureMP];
3524 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003525
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003526 if (Rn == 15) {
3527 switch (Inst.getOpcode()) {
3528 case ARM::t2LDRi12:
3529 Inst.setOpcode(ARM::t2LDRpci);
3530 break;
3531 case ARM::t2LDRHi12:
3532 Inst.setOpcode(ARM::t2LDRHpci);
3533 break;
3534 case ARM::t2LDRSHi12:
3535 Inst.setOpcode(ARM::t2LDRSHpci);
3536 break;
3537 case ARM::t2LDRBi12:
3538 Inst.setOpcode(ARM::t2LDRBpci);
3539 break;
3540 case ARM::t2LDRSBi12:
3541 Inst.setOpcode(ARM::t2LDRSBpci);
3542 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003543 case ARM::t2PLDi12:
3544 Inst.setOpcode(ARM::t2PLDpci);
3545 break;
3546 case ARM::t2PLIi12:
3547 Inst.setOpcode(ARM::t2PLIpci);
3548 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003549 default:
3550 return MCDisassembler::Fail;
3551 }
3552 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3553 }
3554
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003555 if (Rt == 15) {
3556 switch (Inst.getOpcode()) {
3557 case ARM::t2LDRSHi12:
3558 return MCDisassembler::Fail;
3559 case ARM::t2LDRHi12:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003560 Inst.setOpcode(ARM::t2PLDWi12);
3561 break;
3562 case ARM::t2LDRSBi12:
3563 Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003564 break;
3565 default:
3566 break;
3567 }
3568 }
3569
3570 switch (Inst.getOpcode()) {
3571 case ARM::t2PLDi12:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003572 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003573 case ARM::t2PLIi12:
3574 if (!hasV7Ops)
3575 return MCDisassembler::Fail;
3576 break;
3577 case ARM::t2PLDWi12:
3578 if (!hasV7Ops || !hasMP)
3579 return MCDisassembler::Fail;
3580 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003581 default:
3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3583 return MCDisassembler::Fail;
3584 }
3585
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003586 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3587 return MCDisassembler::Fail;
3588 return S;
3589}
3590
3591static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3592 uint64_t Address, const void* Decoder) {
3593 DecodeStatus S = MCDisassembler::Success;
3594
3595 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3596 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3597 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3598 imm |= (Rn << 9);
3599
3600 if (Rn == 15) {
3601 switch (Inst.getOpcode()) {
3602 case ARM::t2LDRT:
3603 Inst.setOpcode(ARM::t2LDRpci);
3604 break;
3605 case ARM::t2LDRBT:
3606 Inst.setOpcode(ARM::t2LDRBpci);
3607 break;
3608 case ARM::t2LDRHT:
3609 Inst.setOpcode(ARM::t2LDRHpci);
3610 break;
3611 case ARM::t2LDRSBT:
3612 Inst.setOpcode(ARM::t2LDRSBpci);
3613 break;
3614 case ARM::t2LDRSHT:
3615 Inst.setOpcode(ARM::t2LDRSHpci);
3616 break;
3617 default:
3618 return MCDisassembler::Fail;
3619 }
3620 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3621 }
3622
3623 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3624 return MCDisassembler::Fail;
3625 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3626 return MCDisassembler::Fail;
3627 return S;
3628}
3629
3630static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3631 uint64_t Address, const void* Decoder) {
3632 DecodeStatus S = MCDisassembler::Success;
3633
3634 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3635 unsigned U = fieldFromInstruction(Insn, 23, 1);
3636 int imm = fieldFromInstruction(Insn, 0, 12);
3637
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003638 const FeatureBitset &featureBits =
3639 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3640
3641 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003642
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003643 if (Rt == 15) {
3644 switch (Inst.getOpcode()) {
3645 case ARM::t2LDRBpci:
3646 case ARM::t2LDRHpci:
3647 Inst.setOpcode(ARM::t2PLDpci);
3648 break;
3649 case ARM::t2LDRSBpci:
3650 Inst.setOpcode(ARM::t2PLIpci);
3651 break;
3652 case ARM::t2LDRSHpci:
3653 return MCDisassembler::Fail;
3654 default:
3655 break;
3656 }
3657 }
3658
3659 switch(Inst.getOpcode()) {
3660 case ARM::t2PLDpci:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003661 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003662 case ARM::t2PLIpci:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003663 if (!hasV7Ops)
3664 return MCDisassembler::Fail;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003665 break;
3666 default:
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 }
3670
3671 if (!U) {
3672 // Special case for #-0.
3673 if (imm == 0)
3674 imm = INT32_MIN;
3675 else
3676 imm = -imm;
3677 }
Jim Grosbache9119e42015-05-13 18:37:00 +00003678 Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003679
3680 return S;
3681}
3682
Craig Topperf6e7e122012-03-27 07:21:54 +00003683static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003684 uint64_t Address, const void *Decoder) {
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003685 if (Val == 0)
Jim Grosbache9119e42015-05-13 18:37:00 +00003686 Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003687 else {
3688 int imm = Val & 0xFF;
3689
3690 if (!(Val & 0x100)) imm *= -1;
Jim Grosbache9119e42015-05-13 18:37:00 +00003691 Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003692 }
Owen Andersone0152a72011-08-09 20:55:18 +00003693
James Molloydb4ce602011-09-01 18:02:14 +00003694 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003695}
3696
Craig Topperf6e7e122012-03-27 07:21:54 +00003697static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003698 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003699 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003700
Jim Grosbachecaef492012-08-14 19:06:05 +00003701 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3702 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Andersone0152a72011-08-09 20:55:18 +00003703
Owen Anderson03aadae2011-09-01 23:23:50 +00003704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3705 return MCDisassembler::Fail;
3706 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3707 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003708
Owen Andersona4043c42011-08-17 17:44:15 +00003709 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003710}
3711
Craig Topperf6e7e122012-03-27 07:21:54 +00003712static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbacha05627e2011-09-09 18:37:27 +00003713 uint64_t Address, const void *Decoder) {
3714 DecodeStatus S = MCDisassembler::Success;
3715
Jim Grosbachecaef492012-08-14 19:06:05 +00003716 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3717 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbacha05627e2011-09-09 18:37:27 +00003718
3719 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3720 return MCDisassembler::Fail;
3721
Jim Grosbache9119e42015-05-13 18:37:00 +00003722 Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbacha05627e2011-09-09 18:37:27 +00003723
3724 return S;
3725}
3726
Craig Topperf6e7e122012-03-27 07:21:54 +00003727static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003728 uint64_t Address, const void *Decoder) {
Owen Andersone0152a72011-08-09 20:55:18 +00003729 int imm = Val & 0xFF;
Owen Andersonfe823652011-09-16 21:08:33 +00003730 if (Val == 0)
3731 imm = INT32_MIN;
3732 else if (!(Val & 0x100))
3733 imm *= -1;
Jim Grosbache9119e42015-05-13 18:37:00 +00003734 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003735
James Molloydb4ce602011-09-01 18:02:14 +00003736 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003737}
3738
Craig Topperf6e7e122012-03-27 07:21:54 +00003739static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003740 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003741 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003742
Jim Grosbachecaef492012-08-14 19:06:05 +00003743 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3744 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Andersone0152a72011-08-09 20:55:18 +00003745
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003746 // Thumb stores cannot use PC as dest register.
3747 switch (Inst.getOpcode()) {
3748 case ARM::t2STRT:
3749 case ARM::t2STRBT:
3750 case ARM::t2STRHT:
3751 case ARM::t2STRi8:
3752 case ARM::t2STRHi8:
3753 case ARM::t2STRBi8:
3754 if (Rn == 15)
3755 return MCDisassembler::Fail;
3756 break;
3757 default:
3758 break;
3759 }
3760
Owen Andersone0152a72011-08-09 20:55:18 +00003761 // Some instructions always use an additive offset.
3762 switch (Inst.getOpcode()) {
3763 case ARM::t2LDRT:
3764 case ARM::t2LDRBT:
3765 case ARM::t2LDRHT:
3766 case ARM::t2LDRSBT:
3767 case ARM::t2LDRSHT:
Owen Andersonddfcec92011-09-19 18:07:10 +00003768 case ARM::t2STRT:
3769 case ARM::t2STRBT:
3770 case ARM::t2STRHT:
Owen Andersone0152a72011-08-09 20:55:18 +00003771 imm |= 0x100;
3772 break;
3773 default:
3774 break;
3775 }
3776
Owen Anderson03aadae2011-09-01 23:23:50 +00003777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3778 return MCDisassembler::Fail;
3779 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3780 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003781
Owen Andersona4043c42011-08-17 17:44:15 +00003782 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003783}
3784
Craig Topperf6e7e122012-03-27 07:21:54 +00003785static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003786 uint64_t Address, const void *Decoder) {
3787 DecodeStatus S = MCDisassembler::Success;
3788
Jim Grosbachecaef492012-08-14 19:06:05 +00003789 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3790 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3791 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3792 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003793 addr |= Rn << 9;
Jim Grosbachecaef492012-08-14 19:06:05 +00003794 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003795
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003796 if (Rn == 15) {
3797 switch (Inst.getOpcode()) {
3798 case ARM::t2LDR_PRE:
3799 case ARM::t2LDR_POST:
3800 Inst.setOpcode(ARM::t2LDRpci);
3801 break;
3802 case ARM::t2LDRB_PRE:
3803 case ARM::t2LDRB_POST:
3804 Inst.setOpcode(ARM::t2LDRBpci);
3805 break;
3806 case ARM::t2LDRH_PRE:
3807 case ARM::t2LDRH_POST:
3808 Inst.setOpcode(ARM::t2LDRHpci);
3809 break;
3810 case ARM::t2LDRSB_PRE:
3811 case ARM::t2LDRSB_POST:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003812 if (Rt == 15)
3813 Inst.setOpcode(ARM::t2PLIpci);
3814 else
3815 Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003816 break;
3817 case ARM::t2LDRSH_PRE:
3818 case ARM::t2LDRSH_POST:
3819 Inst.setOpcode(ARM::t2LDRSHpci);
3820 break;
3821 default:
3822 return MCDisassembler::Fail;
3823 }
3824 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3825 }
3826
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003827 if (!load) {
3828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3829 return MCDisassembler::Fail;
3830 }
3831
Joe Abbeyf686be42013-03-26 13:58:53 +00003832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003833 return MCDisassembler::Fail;
3834
3835 if (load) {
3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3837 return MCDisassembler::Fail;
3838 }
3839
3840 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3841 return MCDisassembler::Fail;
3842
3843 return S;
3844}
Owen Andersone0152a72011-08-09 20:55:18 +00003845
Craig Topperf6e7e122012-03-27 07:21:54 +00003846static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003847 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003848 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003849
Jim Grosbachecaef492012-08-14 19:06:05 +00003850 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3851 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Andersone0152a72011-08-09 20:55:18 +00003852
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003853 // Thumb stores cannot use PC as dest register.
3854 switch (Inst.getOpcode()) {
3855 case ARM::t2STRi12:
3856 case ARM::t2STRBi12:
3857 case ARM::t2STRHi12:
3858 if (Rn == 15)
3859 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003860 break;
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003861 default:
3862 break;
3863 }
3864
Owen Anderson03aadae2011-09-01 23:23:50 +00003865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3866 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003867 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003868
Owen Andersona4043c42011-08-17 17:44:15 +00003869 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003870}
3871
Craig Topperf6e7e122012-03-27 07:21:54 +00003872static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003873 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003874 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Andersone0152a72011-08-09 20:55:18 +00003875
Jim Grosbache9119e42015-05-13 18:37:00 +00003876 Inst.addOperand(MCOperand::createReg(ARM::SP));
3877 Inst.addOperand(MCOperand::createReg(ARM::SP));
3878 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003879
James Molloydb4ce602011-09-01 18:02:14 +00003880 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003881}
3882
Craig Topperf6e7e122012-03-27 07:21:54 +00003883static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003884 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003885 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003886
Owen Andersone0152a72011-08-09 20:55:18 +00003887 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003888 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3889 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Andersone0152a72011-08-09 20:55:18 +00003890
Owen Anderson03aadae2011-09-01 23:23:50 +00003891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3892 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003893 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson03aadae2011-09-01 23:23:50 +00003894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3895 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003896 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003897 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00003898
Jim Grosbache9119e42015-05-13 18:37:00 +00003899 Inst.addOperand(MCOperand::createReg(ARM::SP));
3900 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson03aadae2011-09-01 23:23:50 +00003901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3902 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003903 }
3904
Owen Andersona4043c42011-08-17 17:44:15 +00003905 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003906}
3907
Craig Topperf6e7e122012-03-27 07:21:54 +00003908static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003909 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003910 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3911 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Andersone0152a72011-08-09 20:55:18 +00003912
Jim Grosbache9119e42015-05-13 18:37:00 +00003913 Inst.addOperand(MCOperand::createImm(imod));
3914 Inst.addOperand(MCOperand::createImm(flags));
Owen Andersone0152a72011-08-09 20:55:18 +00003915
James Molloydb4ce602011-09-01 18:02:14 +00003916 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003917}
3918
Craig Topperf6e7e122012-03-27 07:21:54 +00003919static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003920 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003921 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00003922 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3923 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003924
Silviu Barangad213f212012-03-22 13:24:43 +00003925 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00003926 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003927 Inst.addOperand(MCOperand::createImm(add));
Owen Andersone0152a72011-08-09 20:55:18 +00003928
Owen Andersona4043c42011-08-17 17:44:15 +00003929 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003930}
3931
Craig Topperf6e7e122012-03-27 07:21:54 +00003932static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003933 uint64_t Address, const void *Decoder) {
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00003934 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby91422302012-05-03 22:41:56 +00003935 // Note only one trailing zero not two. Also the J1 and J2 values are from
3936 // the encoded instruction. So here change to I1 and I2 values via:
3937 // I1 = NOT(J1 EOR S);
3938 // I2 = NOT(J2 EOR S);
3939 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00003940 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby91422302012-05-03 22:41:56 +00003941 unsigned S = (Val >> 23) & 1;
3942 unsigned J1 = (Val >> 22) & 1;
3943 unsigned J2 = (Val >> 21) & 1;
3944 unsigned I1 = !(J1 ^ S);
3945 unsigned I2 = !(J2 ^ S);
3946 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3947 int imm32 = SignExtend32<25>(tmp << 1);
3948
Jim Grosbach79ebc512011-10-20 17:28:20 +00003949 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby91422302012-05-03 22:41:56 +00003950 (Address & ~2u) + imm32 + 4,
Kevin Enderby5dcda642011-10-04 22:44:48 +00003951 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003952 Inst.addOperand(MCOperand::createImm(imm32));
James Molloydb4ce602011-09-01 18:02:14 +00003953 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003954}
3955
Craig Topperf6e7e122012-03-27 07:21:54 +00003956static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003957 uint64_t Address, const void *Decoder) {
3958 if (Val == 0xA || Val == 0xB)
James Molloydb4ce602011-09-01 18:02:14 +00003959 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003960
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003961 const FeatureBitset &featureBits =
3962 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3963
3964 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
Artyom Skrobove686cec2013-11-08 16:16:30 +00003965 return MCDisassembler::Fail;
3966
Jim Grosbache9119e42015-05-13 18:37:00 +00003967 Inst.addOperand(MCOperand::createImm(Val));
James Molloydb4ce602011-09-01 18:02:14 +00003968 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003969}
3970
Owen Anderson03aadae2011-09-01 23:23:50 +00003971static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00003972DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach05541f42011-09-19 22:21:13 +00003973 uint64_t Address, const void *Decoder) {
3974 DecodeStatus S = MCDisassembler::Success;
3975
Jim Grosbachecaef492012-08-14 19:06:05 +00003976 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3977 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach05541f42011-09-19 22:21:13 +00003978
3979 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3981 return MCDisassembler::Fail;
3982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3983 return MCDisassembler::Fail;
3984 return S;
3985}
3986
3987static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00003988DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00003989 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003990 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003991
Jim Grosbachecaef492012-08-14 19:06:05 +00003992 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00003993 if (pred == 0xE || pred == 0xF) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003994 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Andersone0152a72011-08-09 20:55:18 +00003995 switch (opc) {
3996 default:
James Molloydb4ce602011-09-01 18:02:14 +00003997 return MCDisassembler::Fail;
Owen Anderson4af0aa92011-08-31 22:00:41 +00003998 case 0xf3bf8f4:
Owen Andersone0152a72011-08-09 20:55:18 +00003999 Inst.setOpcode(ARM::t2DSB);
4000 break;
Owen Anderson4af0aa92011-08-31 22:00:41 +00004001 case 0xf3bf8f5:
Owen Andersone0152a72011-08-09 20:55:18 +00004002 Inst.setOpcode(ARM::t2DMB);
4003 break;
Owen Anderson4af0aa92011-08-31 22:00:41 +00004004 case 0xf3bf8f6:
Owen Andersone0152a72011-08-09 20:55:18 +00004005 Inst.setOpcode(ARM::t2ISB);
Owen Andersoncd5612d2011-09-07 17:55:19 +00004006 break;
Owen Andersone0152a72011-08-09 20:55:18 +00004007 }
4008
Jim Grosbachecaef492012-08-14 19:06:05 +00004009 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0089312011-08-09 23:25:42 +00004010 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00004011 }
4012
Jim Grosbachecaef492012-08-14 19:06:05 +00004013 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4014 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4015 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4016 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4017 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Andersone0152a72011-08-09 20:55:18 +00004018
Owen Anderson03aadae2011-09-01 23:23:50 +00004019 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4020 return MCDisassembler::Fail;
4021 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4022 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00004023
Owen Andersona4043c42011-08-17 17:44:15 +00004024 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00004025}
4026
4027// Decode a shifted immediate operand. These basically consist
4028// of an 8-bit value, and a 4-bit directive that specifies either
4029// a splat operation or a rotation.
Craig Topperf6e7e122012-03-27 07:21:54 +00004030static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00004031 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00004032 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00004033 if (ctrl == 0) {
Jim Grosbachecaef492012-08-14 19:06:05 +00004034 unsigned byte = fieldFromInstruction(Val, 8, 2);
4035 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00004036 switch (byte) {
4037 case 0:
Jim Grosbache9119e42015-05-13 18:37:00 +00004038 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004039 break;
4040 case 1:
Jim Grosbache9119e42015-05-13 18:37:00 +00004041 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004042 break;
4043 case 2:
Jim Grosbache9119e42015-05-13 18:37:00 +00004044 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
Owen Andersone0152a72011-08-09 20:55:18 +00004045 break;
4046 case 3:
Jim Grosbache9119e42015-05-13 18:37:00 +00004047 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
Owen Andersone0152a72011-08-09 20:55:18 +00004048 (imm << 8) | imm));
4049 break;
4050 }
4051 } else {
Jim Grosbachecaef492012-08-14 19:06:05 +00004052 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4053 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00004054 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
Jim Grosbache9119e42015-05-13 18:37:00 +00004055 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004056 }
4057
James Molloydb4ce602011-09-01 18:02:14 +00004058 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004059}
4060
Owen Anderson03aadae2011-09-01 23:23:50 +00004061static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00004062DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004063 uint64_t Address, const void *Decoder) {
Richard Bartonf1ef87d2012-06-06 09:12:53 +00004064 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00004065 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00004066 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloydb4ce602011-09-01 18:02:14 +00004067 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004068}
4069
Craig Topperf6e7e122012-03-27 07:21:54 +00004070static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004071 uint64_t Address,
4072 const void *Decoder) {
Kevin Enderby91422302012-05-03 22:41:56 +00004073 // Val is passed in as S:J1:J2:imm10:imm11
4074 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4075 // the encoded instruction. So here change to I1 and I2 values via:
4076 // I1 = NOT(J1 EOR S);
4077 // I2 = NOT(J2 EOR S);
4078 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00004079 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby91422302012-05-03 22:41:56 +00004080 unsigned S = (Val >> 23) & 1;
4081 unsigned J1 = (Val >> 22) & 1;
4082 unsigned J2 = (Val >> 21) & 1;
4083 unsigned I1 = !(J1 ^ S);
4084 unsigned I2 = !(J2 ^ S);
4085 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4086 int imm32 = SignExtend32<25>(tmp << 1);
4087
4088 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00004089 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00004090 Inst.addOperand(MCOperand::createImm(imm32));
James Molloydb4ce602011-09-01 18:02:14 +00004091 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004092}
4093
Craig Topperf6e7e122012-03-27 07:21:54 +00004094static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersone0089312011-08-09 23:25:42 +00004095 uint64_t Address, const void *Decoder) {
Jiangning Liu288e1af2012-08-02 08:21:27 +00004096 if (Val & ~0xf)
James Molloydb4ce602011-09-01 18:02:14 +00004097 return MCDisassembler::Fail;
Owen Andersone0089312011-08-09 23:25:42 +00004098
Jim Grosbache9119e42015-05-13 18:37:00 +00004099 Inst.addOperand(MCOperand::createImm(Val));
James Molloydb4ce602011-09-01 18:02:14 +00004100 return MCDisassembler::Success;
Owen Andersone0089312011-08-09 23:25:42 +00004101}
4102
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00004103static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4104 uint64_t Address, const void *Decoder) {
4105 if (Val & ~0xf)
4106 return MCDisassembler::Fail;
4107
Jim Grosbache9119e42015-05-13 18:37:00 +00004108 Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00004109 return MCDisassembler::Success;
4110}
4111
Craig Topperf6e7e122012-03-27 07:21:54 +00004112static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson60663402011-08-11 20:21:46 +00004113 uint64_t Address, const void *Decoder) {
Renato Golin92c816c2014-09-01 11:25:07 +00004114 DecodeStatus S = MCDisassembler::Success;
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004115 const FeatureBitset &FeatureBits =
4116 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4117
4118 if (FeatureBits[ARM::FeatureMClass]) {
James Molloy137ce602014-08-01 12:42:11 +00004119 unsigned ValLow = Val & 0xff;
4120
4121 // Validate the SYSm value first.
4122 switch (ValLow) {
4123 case 0: // apsr
4124 case 1: // iapsr
4125 case 2: // eapsr
4126 case 3: // xpsr
4127 case 5: // ipsr
4128 case 6: // epsr
4129 case 7: // iepsr
4130 case 8: // msp
4131 case 9: // psp
4132 case 16: // primask
4133 case 20: // control
4134 break;
4135 case 17: // basepri
4136 case 18: // basepri_max
4137 case 19: // faultmask
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004138 if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy137ce602014-08-01 12:42:11 +00004139 // Values basepri, basepri_max and faultmask are only valid for v7m.
4140 return MCDisassembler::Fail;
4141 break;
Bradley Smithf277c8a2016-01-25 11:25:36 +00004142 case 0x8a: // msplim_ns
4143 case 0x8b: // psplim_ns
4144 case 0x91: // basepri_ns
4145 case 0x92: // basepri_max_ns
4146 case 0x93: // faultmask_ns
4147 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4148 return MCDisassembler::Fail;
Justin Bognercd1d5aa2016-08-17 20:30:52 +00004149 LLVM_FALLTHROUGH;
Bradley Smithf277c8a2016-01-25 11:25:36 +00004150 case 10: // msplim
4151 case 11: // psplim
4152 case 0x88: // msp_ns
4153 case 0x89: // psp_ns
4154 case 0x90: // primask_ns
4155 case 0x94: // control_ns
4156 case 0x98: // sp_ns
4157 if (!(FeatureBits[ARM::Feature8MSecExt]))
4158 return MCDisassembler::Fail;
4159 break;
James Molloy137ce602014-08-01 12:42:11 +00004160 default:
4161 return MCDisassembler::Fail;
4162 }
4163
Renato Golin92c816c2014-09-01 11:25:07 +00004164 if (Inst.getOpcode() == ARM::t2MSR_M) {
4165 unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004166 if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin92c816c2014-09-01 11:25:07 +00004167 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4168 // unpredictable.
4169 if (Mask != 2)
4170 S = MCDisassembler::SoftFail;
4171 }
4172 else {
4173 // The ARMv7-M architecture stores an additional 2-bit mask value in
4174 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4175 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4176 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4177 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4178 // only if the processor includes the DSP extension.
4179 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
Artyom Skrobovcf296442015-09-24 17:31:16 +00004180 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
Renato Golin92c816c2014-09-01 11:25:07 +00004181 S = MCDisassembler::SoftFail;
4182 }
James Molloy137ce602014-08-01 12:42:11 +00004183 }
4184 } else {
4185 // A/R class
4186 if (Val == 0)
4187 return MCDisassembler::Fail;
4188 }
Jim Grosbache9119e42015-05-13 18:37:00 +00004189 Inst.addOperand(MCOperand::createImm(Val));
Renato Golin92c816c2014-09-01 11:25:07 +00004190 return S;
Owen Anderson60663402011-08-11 20:21:46 +00004191}
Owen Andersonb685c9f2011-08-11 21:34:58 +00004192
Tim Northoveree843ef2014-08-15 10:47:12 +00004193static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4194 uint64_t Address, const void *Decoder) {
Tim Northoveree843ef2014-08-15 10:47:12 +00004195 unsigned R = fieldFromInstruction(Val, 5, 1);
4196 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4197
4198 // The table of encodings for these banked registers comes from B9.2.3 of the
4199 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4200 // neater. So by fiat, these values are UNPREDICTABLE:
4201 if (!R) {
4202 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4203 SysM == 0x1a || SysM == 0x1b)
4204 return MCDisassembler::SoftFail;
4205 } else {
4206 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4207 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4208 return MCDisassembler::SoftFail;
4209 }
4210
Jim Grosbache9119e42015-05-13 18:37:00 +00004211 Inst.addOperand(MCOperand::createImm(Val));
Tim Northoveree843ef2014-08-15 10:47:12 +00004212 return MCDisassembler::Success;
4213}
4214
Craig Topperf6e7e122012-03-27 07:21:54 +00004215static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00004216 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004217 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004218
Jim Grosbachecaef492012-08-14 19:06:05 +00004219 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4220 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4221 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004222
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004223 if (Rn == 0xF)
4224 S = MCDisassembler::SoftFail;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004225
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004226 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004227 return MCDisassembler::Fail;
4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4231 return MCDisassembler::Fail;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004232
Owen Andersona4043c42011-08-17 17:44:15 +00004233 return S;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004234}
4235
Craig Topperf6e7e122012-03-27 07:21:54 +00004236static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004237 uint64_t Address,
4238 const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004239 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004240
Jim Grosbachecaef492012-08-14 19:06:05 +00004241 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4242 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4243 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4244 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonb685c9f2011-08-11 21:34:58 +00004245
Tim Northover27ff5042013-04-19 15:44:32 +00004246 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004247 return MCDisassembler::Fail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004248
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004249 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4250 S = MCDisassembler::SoftFail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004251
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004252 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004253 return MCDisassembler::Fail;
4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4257 return MCDisassembler::Fail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004258
Owen Andersona4043c42011-08-17 17:44:15 +00004259 return S;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004260}
4261
Craig Topperf6e7e122012-03-27 07:21:54 +00004262static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +00004263 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004264 DecodeStatus S = MCDisassembler::Success;
Owen Anderson16d33f32011-08-26 20:43:14 +00004265
Jim Grosbachecaef492012-08-14 19:06:05 +00004266 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4267 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4268 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4269 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4270 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4271 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson16d33f32011-08-26 20:43:14 +00004272
James Molloydb4ce602011-09-01 18:02:14 +00004273 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004274
Owen Anderson03aadae2011-09-01 23:23:50 +00004275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4276 return MCDisassembler::Fail;
4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4278 return MCDisassembler::Fail;
4279 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4280 return MCDisassembler::Fail;
4281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4282 return MCDisassembler::Fail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004283
4284 return S;
4285}
4286
Craig Topperf6e7e122012-03-27 07:21:54 +00004287static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +00004288 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004289 DecodeStatus S = MCDisassembler::Success;
Owen Anderson16d33f32011-08-26 20:43:14 +00004290
Jim Grosbachecaef492012-08-14 19:06:05 +00004291 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4292 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4293 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4294 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4295 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4296 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4297 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson16d33f32011-08-26 20:43:14 +00004298
James Molloydb4ce602011-09-01 18:02:14 +00004299 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4300 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004301
Owen Anderson03aadae2011-09-01 23:23:50 +00004302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4303 return MCDisassembler::Fail;
4304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4305 return MCDisassembler::Fail;
4306 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4307 return MCDisassembler::Fail;
4308 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4309 return MCDisassembler::Fail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004310
4311 return S;
4312}
4313
Craig Topperf6e7e122012-03-27 07:21:54 +00004314static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +00004315 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004316 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004317
Jim Grosbachecaef492012-08-14 19:06:05 +00004318 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4319 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4320 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4321 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4322 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4323 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonb685c9f2011-08-11 21:34:58 +00004324
James Molloydb4ce602011-09-01 18:02:14 +00004325 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson3987a612011-08-12 18:12:39 +00004326
Owen Anderson03aadae2011-09-01 23:23:50 +00004327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4328 return MCDisassembler::Fail;
4329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4330 return MCDisassembler::Fail;
4331 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4332 return MCDisassembler::Fail;
4333 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4334 return MCDisassembler::Fail;
Owen Anderson3987a612011-08-12 18:12:39 +00004335
Owen Andersona4043c42011-08-17 17:44:15 +00004336 return S;
Owen Anderson3987a612011-08-12 18:12:39 +00004337}
4338
Craig Topperf6e7e122012-03-27 07:21:54 +00004339static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +00004340 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004341 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004342
Jim Grosbachecaef492012-08-14 19:06:05 +00004343 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4344 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4345 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4346 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4347 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4348 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3987a612011-08-12 18:12:39 +00004349
James Molloydb4ce602011-09-01 18:02:14 +00004350 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson3987a612011-08-12 18:12:39 +00004351
Owen Anderson03aadae2011-09-01 23:23:50 +00004352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4353 return MCDisassembler::Fail;
4354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4355 return MCDisassembler::Fail;
4356 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4357 return MCDisassembler::Fail;
4358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4359 return MCDisassembler::Fail;
Owen Anderson3987a612011-08-12 18:12:39 +00004360
Owen Andersona4043c42011-08-17 17:44:15 +00004361 return S;
Owen Anderson3987a612011-08-12 18:12:39 +00004362}
Owen Andersonb9d82f42011-08-15 18:44:44 +00004363
Craig Topperf6e7e122012-03-27 07:21:54 +00004364static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004365 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004366 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004367
Jim Grosbachecaef492012-08-14 19:06:05 +00004368 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4369 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4370 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4371 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4372 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004373
4374 unsigned align = 0;
4375 unsigned index = 0;
4376 switch (size) {
4377 default:
James Molloydb4ce602011-09-01 18:02:14 +00004378 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004379 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004380 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004381 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004382 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004383 break;
4384 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004385 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004386 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004387 index = fieldFromInstruction(Insn, 6, 2);
4388 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004389 align = 2;
4390 break;
4391 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004392 if (fieldFromInstruction(Insn, 6, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004393 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004394 index = fieldFromInstruction(Insn, 7, 1);
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004395
4396 switch (fieldFromInstruction(Insn, 4, 2)) {
4397 case 0 :
4398 align = 0; break;
4399 case 3:
4400 align = 4; break;
4401 default:
4402 return MCDisassembler::Fail;
4403 }
4404 break;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004405 }
4406
Owen Anderson03aadae2011-09-01 23:23:50 +00004407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4408 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004409 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4411 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004412 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4414 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004415 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004416 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004417 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4419 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004420 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004421 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004422 }
4423
Owen Anderson03aadae2011-09-01 23:23:50 +00004424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4425 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004426 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004427
Owen Andersona4043c42011-08-17 17:44:15 +00004428 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004429}
4430
Craig Topperf6e7e122012-03-27 07:21:54 +00004431static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004432 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004433 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004434
Jim Grosbachecaef492012-08-14 19:06:05 +00004435 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4436 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4437 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4438 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4439 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004440
4441 unsigned align = 0;
4442 unsigned index = 0;
4443 switch (size) {
4444 default:
James Molloydb4ce602011-09-01 18:02:14 +00004445 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004446 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004447 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004448 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004449 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004450 break;
4451 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004452 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004453 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004454 index = fieldFromInstruction(Insn, 6, 2);
4455 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004456 align = 2;
4457 break;
4458 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004459 if (fieldFromInstruction(Insn, 6, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004460 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004461 index = fieldFromInstruction(Insn, 7, 1);
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004462
4463 switch (fieldFromInstruction(Insn, 4, 2)) {
4464 case 0:
4465 align = 0; break;
4466 case 3:
4467 align = 4; break;
4468 default:
4469 return MCDisassembler::Fail;
4470 }
4471 break;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004472 }
4473
4474 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4476 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004477 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4479 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004480 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004481 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004482 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4484 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004485 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004486 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004487 }
4488
Owen Anderson03aadae2011-09-01 23:23:50 +00004489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4490 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004491 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004492
Owen Andersona4043c42011-08-17 17:44:15 +00004493 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004494}
4495
Craig Topperf6e7e122012-03-27 07:21:54 +00004496static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004497 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004498 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004499
Jim Grosbachecaef492012-08-14 19:06:05 +00004500 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4501 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4502 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4503 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4504 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004505
4506 unsigned align = 0;
4507 unsigned index = 0;
4508 unsigned inc = 1;
4509 switch (size) {
4510 default:
James Molloydb4ce602011-09-01 18:02:14 +00004511 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004512 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004513 index = fieldFromInstruction(Insn, 5, 3);
4514 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004515 align = 2;
4516 break;
4517 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004518 index = fieldFromInstruction(Insn, 6, 2);
4519 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004520 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004521 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004522 inc = 2;
4523 break;
4524 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004525 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004526 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004527 index = fieldFromInstruction(Insn, 7, 1);
4528 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Andersonb9d82f42011-08-15 18:44:44 +00004529 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004530 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004531 inc = 2;
4532 break;
4533 }
4534
Owen Anderson03aadae2011-09-01 23:23:50 +00004535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4536 return MCDisassembler::Fail;
4537 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4538 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004539 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4541 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004542 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4544 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004545 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004546 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004547 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4549 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004550 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004551 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004552 }
4553
Owen Anderson03aadae2011-09-01 23:23:50 +00004554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4555 return MCDisassembler::Fail;
4556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4557 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004558 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004559
Owen Andersona4043c42011-08-17 17:44:15 +00004560 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004561}
4562
Craig Topperf6e7e122012-03-27 07:21:54 +00004563static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004564 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004565 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004566
Jim Grosbachecaef492012-08-14 19:06:05 +00004567 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4568 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4569 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4570 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4571 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004572
4573 unsigned align = 0;
4574 unsigned index = 0;
4575 unsigned inc = 1;
4576 switch (size) {
4577 default:
James Molloydb4ce602011-09-01 18:02:14 +00004578 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004579 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004580 index = fieldFromInstruction(Insn, 5, 3);
4581 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004582 align = 2;
4583 break;
4584 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004585 index = fieldFromInstruction(Insn, 6, 2);
4586 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004587 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004588 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004589 inc = 2;
4590 break;
4591 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004592 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004593 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004594 index = fieldFromInstruction(Insn, 7, 1);
4595 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Andersonb9d82f42011-08-15 18:44:44 +00004596 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004597 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004598 inc = 2;
4599 break;
4600 }
4601
4602 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4604 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004605 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4607 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004608 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004609 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004610 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4612 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004613 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004614 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004615 }
4616
Owen Anderson03aadae2011-09-01 23:23:50 +00004617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4618 return MCDisassembler::Fail;
4619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4620 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004621 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004622
Owen Andersona4043c42011-08-17 17:44:15 +00004623 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004624}
4625
Craig Topperf6e7e122012-03-27 07:21:54 +00004626static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004627 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004628 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004629
Jim Grosbachecaef492012-08-14 19:06:05 +00004630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4631 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4632 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4633 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4634 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004635
4636 unsigned align = 0;
4637 unsigned index = 0;
4638 unsigned inc = 1;
4639 switch (size) {
4640 default:
James Molloydb4ce602011-09-01 18:02:14 +00004641 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004642 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004643 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004644 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004645 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004646 break;
4647 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004648 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004649 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004650 index = fieldFromInstruction(Insn, 6, 2);
4651 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004652 inc = 2;
4653 break;
4654 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004655 if (fieldFromInstruction(Insn, 4, 2))
James Molloydb4ce602011-09-01 18:02:14 +00004656 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004657 index = fieldFromInstruction(Insn, 7, 1);
4658 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004659 inc = 2;
4660 break;
4661 }
4662
Owen Anderson03aadae2011-09-01 23:23:50 +00004663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4664 return MCDisassembler::Fail;
4665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4666 return MCDisassembler::Fail;
4667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4668 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004669
4670 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4672 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004673 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4675 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004676 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson2fa06a72011-08-30 22:58:27 +00004677 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004678 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4680 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004681 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004682 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004683 }
4684
Owen Anderson03aadae2011-09-01 23:23:50 +00004685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4686 return MCDisassembler::Fail;
4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4688 return MCDisassembler::Fail;
4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4690 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004691 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004692
Owen Andersona4043c42011-08-17 17:44:15 +00004693 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004694}
4695
Craig Topperf6e7e122012-03-27 07:21:54 +00004696static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004697 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004698 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004699
Jim Grosbachecaef492012-08-14 19:06:05 +00004700 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4701 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4702 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4703 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4704 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004705
4706 unsigned align = 0;
4707 unsigned index = 0;
4708 unsigned inc = 1;
4709 switch (size) {
4710 default:
James Molloydb4ce602011-09-01 18:02:14 +00004711 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004712 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004713 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004714 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004715 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004716 break;
4717 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004718 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004719 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004720 index = fieldFromInstruction(Insn, 6, 2);
4721 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004722 inc = 2;
4723 break;
4724 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004725 if (fieldFromInstruction(Insn, 4, 2))
James Molloydb4ce602011-09-01 18:02:14 +00004726 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004727 index = fieldFromInstruction(Insn, 7, 1);
4728 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004729 inc = 2;
4730 break;
4731 }
4732
4733 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4735 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004736 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4738 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004739 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004740 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004741 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4743 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004744 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004745 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004746 }
4747
Owen Anderson03aadae2011-09-01 23:23:50 +00004748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4749 return MCDisassembler::Fail;
4750 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4751 return MCDisassembler::Fail;
4752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4753 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004754 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004755
Owen Andersona4043c42011-08-17 17:44:15 +00004756 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004757}
4758
Craig Topperf6e7e122012-03-27 07:21:54 +00004759static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004760 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004761 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004762
Jim Grosbachecaef492012-08-14 19:06:05 +00004763 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4764 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4765 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4766 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4767 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004768
4769 unsigned align = 0;
4770 unsigned index = 0;
4771 unsigned inc = 1;
4772 switch (size) {
4773 default:
James Molloydb4ce602011-09-01 18:02:14 +00004774 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004775 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004776 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004777 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004778 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004779 break;
4780 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004781 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004782 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004783 index = fieldFromInstruction(Insn, 6, 2);
4784 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004785 inc = 2;
4786 break;
4787 case 2:
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004788 switch (fieldFromInstruction(Insn, 4, 2)) {
4789 case 0:
4790 align = 0; break;
4791 case 3:
4792 return MCDisassembler::Fail;
4793 default:
4794 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4795 }
4796
Jim Grosbachecaef492012-08-14 19:06:05 +00004797 index = fieldFromInstruction(Insn, 7, 1);
4798 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004799 inc = 2;
4800 break;
4801 }
4802
Owen Anderson03aadae2011-09-01 23:23:50 +00004803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4804 return MCDisassembler::Fail;
4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4806 return MCDisassembler::Fail;
4807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4808 return MCDisassembler::Fail;
4809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4810 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004811
4812 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4814 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004815 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4817 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004818 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004819 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004820 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4822 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004823 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004824 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004825 }
4826
Owen Anderson03aadae2011-09-01 23:23:50 +00004827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4828 return MCDisassembler::Fail;
4829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4830 return MCDisassembler::Fail;
4831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4832 return MCDisassembler::Fail;
4833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4834 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004835 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004836
Owen Andersona4043c42011-08-17 17:44:15 +00004837 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004838}
4839
Craig Topperf6e7e122012-03-27 07:21:54 +00004840static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004841 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004842 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004843
Jim Grosbachecaef492012-08-14 19:06:05 +00004844 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4845 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4846 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4847 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4848 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004849
4850 unsigned align = 0;
4851 unsigned index = 0;
4852 unsigned inc = 1;
4853 switch (size) {
4854 default:
James Molloydb4ce602011-09-01 18:02:14 +00004855 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004856 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004857 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004858 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004859 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004860 break;
4861 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004862 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004863 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004864 index = fieldFromInstruction(Insn, 6, 2);
4865 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004866 inc = 2;
4867 break;
4868 case 2:
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004869 switch (fieldFromInstruction(Insn, 4, 2)) {
4870 case 0:
4871 align = 0; break;
4872 case 3:
4873 return MCDisassembler::Fail;
4874 default:
4875 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4876 }
4877
Jim Grosbachecaef492012-08-14 19:06:05 +00004878 index = fieldFromInstruction(Insn, 7, 1);
4879 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004880 inc = 2;
4881 break;
4882 }
4883
4884 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004885 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4886 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004887 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4889 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004890 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004891 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004892 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4894 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004895 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004896 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004897 }
4898
Owen Anderson03aadae2011-09-01 23:23:50 +00004899 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4900 return MCDisassembler::Fail;
4901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4902 return MCDisassembler::Fail;
4903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4904 return MCDisassembler::Fail;
4905 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4906 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004907 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004908
Owen Andersona4043c42011-08-17 17:44:15 +00004909 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004910}
4911
Craig Topperf6e7e122012-03-27 07:21:54 +00004912static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +00004913 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004914 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00004915 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4916 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4917 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4918 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4919 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Andersondf698b02011-08-22 20:27:12 +00004920
4921 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloydb4ce602011-09-01 18:02:14 +00004922 S = MCDisassembler::SoftFail;
Owen Andersondf698b02011-08-22 20:27:12 +00004923
Owen Anderson03aadae2011-09-01 23:23:50 +00004924 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4925 return MCDisassembler::Fail;
4926 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4927 return MCDisassembler::Fail;
4928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4929 return MCDisassembler::Fail;
4930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4931 return MCDisassembler::Fail;
4932 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4933 return MCDisassembler::Fail;
Owen Andersondf698b02011-08-22 20:27:12 +00004934
4935 return S;
4936}
4937
Craig Topperf6e7e122012-03-27 07:21:54 +00004938static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +00004939 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004940 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00004941 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4942 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4943 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4944 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4945 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Andersondf698b02011-08-22 20:27:12 +00004946
4947 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloydb4ce602011-09-01 18:02:14 +00004948 S = MCDisassembler::SoftFail;
Owen Andersondf698b02011-08-22 20:27:12 +00004949
Owen Anderson03aadae2011-09-01 23:23:50 +00004950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4951 return MCDisassembler::Fail;
4952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4953 return MCDisassembler::Fail;
4954 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4955 return MCDisassembler::Fail;
4956 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4957 return MCDisassembler::Fail;
4958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4959 return MCDisassembler::Fail;
Owen Andersondf698b02011-08-22 20:27:12 +00004960
4961 return S;
4962}
Owen Andersoneb1367b2011-08-22 23:44:04 +00004963
Craig Topperf6e7e122012-03-27 07:21:54 +00004964static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson2fa06a72011-08-30 22:58:27 +00004965 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004966 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00004967 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4968 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson2fa06a72011-08-30 22:58:27 +00004969
4970 if (pred == 0xF) {
4971 pred = 0xE;
James Molloydb4ce602011-09-01 18:02:14 +00004972 S = MCDisassembler::SoftFail;
Owen Anderson52300412011-08-24 17:21:43 +00004973 }
4974
Amaury de la Vieuville2f0ac8d2013-06-24 09:11:45 +00004975 if (mask == 0x0)
4976 return MCDisassembler::Fail;
Owen Anderson2fa06a72011-08-30 22:58:27 +00004977
Jim Grosbache9119e42015-05-13 18:37:00 +00004978 Inst.addOperand(MCOperand::createImm(pred));
4979 Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson37612a32011-08-24 22:40:22 +00004980 return S;
4981}
Jim Grosbach7db8d692011-09-08 22:07:06 +00004982
4983static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00004984DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +00004985 uint64_t Address, const void *Decoder) {
4986 DecodeStatus S = MCDisassembler::Success;
4987
Jim Grosbachecaef492012-08-14 19:06:05 +00004988 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4989 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4990 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4991 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4992 unsigned W = fieldFromInstruction(Insn, 21, 1);
4993 unsigned U = fieldFromInstruction(Insn, 23, 1);
4994 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach7db8d692011-09-08 22:07:06 +00004995 bool writeback = (W == 1) | (P == 0);
4996
4997 addr |= (U << 8) | (Rn << 9);
4998
4999 if (writeback && (Rn == Rt || Rn == Rt2))
5000 Check(S, MCDisassembler::SoftFail);
5001 if (Rt == Rt2)
5002 Check(S, MCDisassembler::SoftFail);
5003
5004 // Rt
5005 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5006 return MCDisassembler::Fail;
5007 // Rt2
5008 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5009 return MCDisassembler::Fail;
5010 // Writeback operand
5011 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5012 return MCDisassembler::Fail;
5013 // addr
5014 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5015 return MCDisassembler::Fail;
5016
5017 return S;
5018}
5019
5020static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00005021DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +00005022 uint64_t Address, const void *Decoder) {
5023 DecodeStatus S = MCDisassembler::Success;
5024
Jim Grosbachecaef492012-08-14 19:06:05 +00005025 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5026 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5027 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5028 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5029 unsigned W = fieldFromInstruction(Insn, 21, 1);
5030 unsigned U = fieldFromInstruction(Insn, 23, 1);
5031 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach7db8d692011-09-08 22:07:06 +00005032 bool writeback = (W == 1) | (P == 0);
5033
5034 addr |= (U << 8) | (Rn << 9);
5035
5036 if (writeback && (Rn == Rt || Rn == Rt2))
5037 Check(S, MCDisassembler::SoftFail);
5038
5039 // Writeback operand
5040 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5041 return MCDisassembler::Fail;
5042 // Rt
5043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5044 return MCDisassembler::Fail;
5045 // Rt2
5046 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5047 return MCDisassembler::Fail;
5048 // addr
5049 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5050 return MCDisassembler::Fail;
5051
5052 return S;
5053}
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005054
Craig Topperf6e7e122012-03-27 07:21:54 +00005055static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005056 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00005057 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5058 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005059 if (sign1 != sign2) return MCDisassembler::Fail;
5060
Jim Grosbachecaef492012-08-14 19:06:05 +00005061 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5062 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5063 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005064 Val |= sign1 << 12;
Jim Grosbache9119e42015-05-13 18:37:00 +00005065 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005066
5067 return MCDisassembler::Success;
5068}
5069
Craig Topperf6e7e122012-03-27 07:21:54 +00005070static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Andersonf01e2de2011-09-26 21:06:22 +00005071 uint64_t Address,
5072 const void *Decoder) {
5073 DecodeStatus S = MCDisassembler::Success;
5074
5075 // Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith3131e852015-01-19 16:37:17 +00005076 if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005077 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersonf01e2de2011-09-26 21:06:22 +00005078 return S;
5079}
5080
Craig Topperf6e7e122012-03-27 07:21:54 +00005081static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersondde461c2011-10-28 18:02:13 +00005082 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00005083 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5084 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5085 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5086 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersondde461c2011-10-28 18:02:13 +00005087
5088 if (pred == 0xF)
5089 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5090
5091 DecodeStatus S = MCDisassembler::Success;
Silviu Barangaca45af92012-04-18 14:18:57 +00005092
5093 if (Rt == Rn || Rn == Rt2)
5094 S = MCDisassembler::SoftFail;
5095
Owen Andersondde461c2011-10-28 18:02:13 +00005096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5097 return MCDisassembler::Fail;
5098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5099 return MCDisassembler::Fail;
5100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5101 return MCDisassembler::Fail;
5102 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5103 return MCDisassembler::Fail;
5104
5105 return S;
5106}
Owen Anderson0ac90582011-11-15 19:55:00 +00005107
Craig Topperf6e7e122012-03-27 07:21:54 +00005108static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +00005109 uint64_t Address, const void *Decoder) {
Oliver Stannard2de8c162015-12-16 12:37:39 +00005110 const FeatureBitset &featureBits =
5111 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5112 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5113
Jim Grosbachecaef492012-08-14 19:06:05 +00005114 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5115 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5116 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5117 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5118 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5119 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuvillef4ec0c852013-06-08 13:54:05 +00005120 unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson0ac90582011-11-15 19:55:00 +00005121
5122 DecodeStatus S = MCDisassembler::Success;
5123
Oliver Stannard2de8c162015-12-16 12:37:39 +00005124 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5125 if (!(imm & 0x38)) {
5126 if (cmode == 0xF) {
5127 if (op == 1) return MCDisassembler::Fail;
5128 Inst.setOpcode(ARM::VMOVv2f32);
5129 }
5130 if (hasFullFP16) {
5131 if (cmode == 0xE) {
5132 if (op == 1) {
5133 Inst.setOpcode(ARM::VMOVv1i64);
5134 } else {
5135 Inst.setOpcode(ARM::VMOVv8i8);
5136 }
5137 }
5138 if (cmode == 0xD) {
5139 if (op == 1) {
5140 Inst.setOpcode(ARM::VMVNv2i32);
5141 } else {
5142 Inst.setOpcode(ARM::VMOVv2i32);
5143 }
5144 }
5145 if (cmode == 0xC) {
5146 if (op == 1) {
5147 Inst.setOpcode(ARM::VMVNv2i32);
5148 } else {
5149 Inst.setOpcode(ARM::VMOVv2i32);
5150 }
5151 }
5152 }
Owen Anderson0ac90582011-11-15 19:55:00 +00005153 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5154 }
5155
Amaury de la Vieuvilleea7bb572013-06-08 13:29:11 +00005156 if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson0ac90582011-11-15 19:55:00 +00005157
5158 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5159 return MCDisassembler::Fail;
5160 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5161 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005162 Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson0ac90582011-11-15 19:55:00 +00005163
5164 return S;
5165}
5166
Craig Topperf6e7e122012-03-27 07:21:54 +00005167static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +00005168 uint64_t Address, const void *Decoder) {
Oliver Stannard2de8c162015-12-16 12:37:39 +00005169 const FeatureBitset &featureBits =
5170 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5171 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5172
Jim Grosbachecaef492012-08-14 19:06:05 +00005173 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5174 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5175 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5176 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5177 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5178 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuvillef4ec0c852013-06-08 13:54:05 +00005179 unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson0ac90582011-11-15 19:55:00 +00005180
5181 DecodeStatus S = MCDisassembler::Success;
5182
Oliver Stannard2de8c162015-12-16 12:37:39 +00005183 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5184 if (!(imm & 0x38)) {
5185 if (cmode == 0xF) {
5186 if (op == 1) return MCDisassembler::Fail;
5187 Inst.setOpcode(ARM::VMOVv4f32);
5188 }
5189 if (hasFullFP16) {
5190 if (cmode == 0xE) {
5191 if (op == 1) {
5192 Inst.setOpcode(ARM::VMOVv2i64);
5193 } else {
5194 Inst.setOpcode(ARM::VMOVv16i8);
5195 }
5196 }
5197 if (cmode == 0xD) {
5198 if (op == 1) {
5199 Inst.setOpcode(ARM::VMVNv4i32);
5200 } else {
5201 Inst.setOpcode(ARM::VMOVv4i32);
5202 }
5203 }
5204 if (cmode == 0xC) {
5205 if (op == 1) {
5206 Inst.setOpcode(ARM::VMVNv4i32);
5207 } else {
5208 Inst.setOpcode(ARM::VMOVv4i32);
5209 }
5210 }
5211 }
Owen Anderson0ac90582011-11-15 19:55:00 +00005212 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5213 }
5214
Amaury de la Vieuvilleea7bb572013-06-08 13:29:11 +00005215 if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson0ac90582011-11-15 19:55:00 +00005216
5217 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5218 return MCDisassembler::Fail;
5219 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5220 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005221 Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson0ac90582011-11-15 19:55:00 +00005222
5223 return S;
5224}
Silviu Barangad213f212012-03-22 13:24:43 +00005225
Sam Parker963da5b2017-09-29 13:11:33 +00005226static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5227 unsigned Insn,
5228 uint64_t Address,
5229 const void *Decoder) {
5230 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5231 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5232 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5233 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5234 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5235 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5236 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5237 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5238
5239 DecodeStatus S = MCDisassembler::Success;
5240
5241 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5242
5243 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5244 return MCDisassembler::Fail;
5245 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5246 return MCDisassembler::Fail;
5247 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5248 return MCDisassembler::Fail;
5249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5250 return MCDisassembler::Fail;
5251 // The lane index does not have any bits in the encoding, because it can only
5252 // be 0.
5253 Inst.addOperand(MCOperand::createImm(0));
5254 Inst.addOperand(MCOperand::createImm(rotate));
5255
5256 return S;
5257}
5258
Craig Topperf6e7e122012-03-27 07:21:54 +00005259static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangad213f212012-03-22 13:24:43 +00005260 uint64_t Address, const void *Decoder) {
5261 DecodeStatus S = MCDisassembler::Success;
5262
Jim Grosbachecaef492012-08-14 19:06:05 +00005263 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5264 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5265 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5266 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5267 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Vinicius Tinti67cf33d2015-11-20 23:20:12 +00005268
Jim Grosbachecaef492012-08-14 19:06:05 +00005269 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangad213f212012-03-22 13:24:43 +00005270 S = MCDisassembler::SoftFail;
5271
5272 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5273 return MCDisassembler::Fail;
5274 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5275 return MCDisassembler::Fail;
5276 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5277 return MCDisassembler::Fail;
5278 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5279 return MCDisassembler::Fail;
5280 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5281 return MCDisassembler::Fail;
5282
5283 return S;
5284}
5285
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00005286static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005287 uint64_t Address, const void *Decoder) {
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005288 DecodeStatus S = MCDisassembler::Success;
5289
Jim Grosbachecaef492012-08-14 19:06:05 +00005290 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5291 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5292 unsigned cop = fieldFromInstruction(Val, 8, 4);
5293 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5294 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005295
5296 if ((cop & ~0x1) == 0xa)
5297 return MCDisassembler::Fail;
5298
5299 if (Rt == Rt2)
5300 S = MCDisassembler::SoftFail;
5301
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005302 // We have to check if the instruction is MRRC2
5303 // or MCRR2 when constructing the operands for
5304 // Inst. Reason is because MRRC2 stores to two
5305 // registers so it's tablegen desc has has two
5306 // outputs whereas MCRR doesn't store to any
5307 // registers so all of it's operands are listed
5308 // as inputs, therefore the operand order for
5309 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5310 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5311
5312 if (Inst.getOpcode() == ARM::MRRC2) {
5313 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5314 return MCDisassembler::Fail;
5315 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5316 return MCDisassembler::Fail;
5317 }
Jim Grosbache9119e42015-05-13 18:37:00 +00005318 Inst.addOperand(MCOperand::createImm(cop));
5319 Inst.addOperand(MCOperand::createImm(opc1));
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005320 if (Inst.getOpcode() == ARM::MCRR2) {
5321 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5322 return MCDisassembler::Fail;
5323 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5324 return MCDisassembler::Fail;
5325 }
Jim Grosbache9119e42015-05-13 18:37:00 +00005326 Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005327
5328 return S;
5329}
Andre Vieira640527f2017-09-22 12:17:42 +00005330
5331static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5332 uint64_t Address,
5333 const void *Decoder) {
5334 const FeatureBitset &featureBits =
5335 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5336 DecodeStatus S = MCDisassembler::Success;
5337
5338 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5339
5340 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5341 if (Rt == 13 || Rt == 15)
5342 S = MCDisassembler::SoftFail;
5343 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5344 } else
5345 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5346
Andre Vieirad4a25702017-10-18 14:47:37 +00005347 if (featureBits[ARM::ModeThumb]) {
5348 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5349 Inst.addOperand(MCOperand::createReg(0));
5350 } else {
5351 unsigned pred = fieldFromInstruction(Val, 28, 4);
5352 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5353 return MCDisassembler::Fail;
5354 }
Andre Vieira640527f2017-09-22 12:17:42 +00005355
5356 return S;
5357}