blob: 934a545c079d0378feb7cc018f70c68689154b04 [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +00001//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +000024
Simon Pilgrimc21deec2018-03-24 19:37:28 +000025 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +000026 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +000028}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +000069// Integer division issued on port 0.
Craig Topper8104f262018-04-02 05:33:28 +000070def BWDivider : ProcResource<1>;
71// FP division and sqrt on port 0.
72def BWFPDivider : ProcResource<1>;
Simon Pilgrim30c38c32018-03-19 14:46:07 +000073
Gadi Haber323f2e12017-10-24 20:19:47 +000074// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75// cycles after the memory operand.
76def : ReadAdvance<ReadAfterLd, 5>;
77
78// Many SchedWrites are defined in pairs with and without a folded load.
79// Instructions with folded loads are usually micro-fused, so they only appear
80// as two micro-ops when queued in the reservation station.
81// This multiclass defines the resource usage for variants with and without
82// folded loads.
83multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +000084 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +000085 int Lat, list<int> Res = [1], int UOps = 1,
86 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +000087 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +000088 def : WriteRes<SchedRW, ExePorts> {
89 let Latency = Lat;
90 let ResourceCycles = Res;
91 let NumMicroOps = UOps;
92 }
Gadi Haber323f2e12017-10-24 20:19:47 +000093
Simon Pilgrime3547af2018-03-25 10:21:19 +000094 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
95 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +000096 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +000097 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +000098 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +000099 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000100 }
101}
102
Craig Topperf131b602018-04-06 16:16:46 +0000103// A folded store needs a cycle on port 4 for the store data, and an extra port
104// 2/3/7 cycle to recompute the address.
105def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000106
107// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000108defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
109defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
110defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000111defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000112def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000113
114def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
115
Craig Topperb7baa352018-04-08 17:53:18 +0000116defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move.
117def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
118def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
119 let Latency = 2;
120 let NumMicroOps = 3;
121}
122
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000123// Bit counts.
124defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
125defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
126defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
127defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
128
Gadi Haber323f2e12017-10-24 20:19:47 +0000129// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000130defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000131
Craig Topper89310f52018-03-29 20:41:39 +0000132// BMI1 BEXTR, BMI2 BZHI
133defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
134defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
135
Gadi Haber323f2e12017-10-24 20:19:47 +0000136// Loads, stores, and moves, not folded with other operations.
137def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
138def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
139def : WriteRes<WriteMove, [BWPort0156]>;
140
141// Idioms that clear a register, like xorps %xmm0, %xmm0.
142// These can often bypass execution ports completely.
143def : WriteRes<WriteZero, []>;
144
Sanjoy Das1074eb22017-12-12 19:11:31 +0000145// Treat misc copies as a move.
146def : InstRW<[WriteMove], (instrs COPY)>;
147
Gadi Haber323f2e12017-10-24 20:19:47 +0000148// Branches don't produce values, so they have no latency, but they still
149// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000150defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000151
152// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000153def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
154def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
155def : WriteRes<WriteFMove, [BWPort5]>;
156
Simon Pilgrim86e3c2692018-04-17 07:22:44 +0000157defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub.
158defm : BWWriteResPair<WriteFCmp, [BWPort1], 3>; // Floating point compare.
159defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000160defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
161defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
162defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
163defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
164defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
165defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
Simon Pilgrimd14d2e72018-04-20 21:16:05 +0000166defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs.
167defm : BWWriteResPair<WriteFLogic, [BWPort5], 1>; // Floating point and/or/xor logicals.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000168defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
Simon Pilgrim89c8a102018-04-11 13:49:19 +0000169defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1>; // Floating point vector variable shuffles.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000170defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
Simon Pilgrim96855ec2018-04-22 14:43:12 +0000171defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000172
173// FMA Scheduling helper class.
174// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
175
176// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000177def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
178def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
179def : WriteRes<WriteVecMove, [BWPort015]>;
180
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000181defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
Simon Pilgrimd14d2e72018-04-20 21:16:05 +0000182defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector integer and/or/xor.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000183defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
184defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
Craig Topper13a0f832018-03-31 04:54:32 +0000185defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000186defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
Simon Pilgrim89c8a102018-04-11 13:49:19 +0000187defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1>; // Vector variable shuffles.
Simon Pilgrim06e16542018-04-22 18:35:53 +0000188defm : BWWriteResPair<WriteBlend, [BWPort5], 1>; // Vector blends.
Simon Pilgrim96855ec2018-04-22 14:43:12 +0000189defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
Simon Pilgrima41ae2f2018-04-22 10:39:16 +0000190defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
Craig Toppere56a2fc2018-04-17 19:35:19 +0000191defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
Gadi Haber323f2e12017-10-24 20:19:47 +0000192
Gadi Haber323f2e12017-10-24 20:19:47 +0000193// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000194defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
195defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
196defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000197
198// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000199
Gadi Haber323f2e12017-10-24 20:19:47 +0000200// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000201def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000202 let Latency = 11;
203 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000204 let ResourceCycles = [3];
205}
206def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000207 let Latency = 16;
208 let NumMicroOps = 4;
209 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000210}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000211
212// Packed Compare Explicit Length Strings, Return Mask
213def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
214 let Latency = 19;
215 let NumMicroOps = 9;
216 let ResourceCycles = [4,3,1,1];
217}
218def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
219 let Latency = 24;
220 let NumMicroOps = 10;
221 let ResourceCycles = [4,3,1,1,1];
222}
223
224// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000225def : WriteRes<WritePCmpIStrI, [BWPort0]> {
226 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000227 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000228 let ResourceCycles = [3];
229}
230def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000231 let Latency = 16;
232 let NumMicroOps = 4;
233 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000234}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000235
236// Packed Compare Explicit Length Strings, Return Index
237def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
238 let Latency = 18;
239 let NumMicroOps = 8;
240 let ResourceCycles = [4,3,1];
241}
242def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
243 let Latency = 23;
244 let NumMicroOps = 9;
245 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000246}
247
Simon Pilgrima2f26782018-03-27 20:38:54 +0000248// MOVMSK Instructions.
249def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
250def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
251def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
252
Gadi Haber323f2e12017-10-24 20:19:47 +0000253// AES instructions.
254def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
255 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000256 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000257 let ResourceCycles = [1];
258}
259def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000260 let Latency = 12;
261 let NumMicroOps = 2;
262 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000263}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000264
Gadi Haber323f2e12017-10-24 20:19:47 +0000265def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
266 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000267 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000268 let ResourceCycles = [2];
269}
270def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000271 let Latency = 19;
272 let NumMicroOps = 3;
273 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000274}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000275
276def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
277 let Latency = 29;
278 let NumMicroOps = 11;
279 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000280}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000281def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
282 let Latency = 33;
283 let NumMicroOps = 11;
284 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000285}
286
287// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000288defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000289
290// Catch-all for expensive system instructions.
291def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
292
293// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000294defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
Simon Pilgrim89c8a102018-04-11 13:49:19 +0000295defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3>; // Fp 256-bit width vector variable shuffles.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000296defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
Simon Pilgrim89c8a102018-04-11 13:49:19 +0000297defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3>; // 256-bit width vector variable shuffles.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000298defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000299
300// Old microcoded instructions that nobody use.
301def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
302
303// Fence instructions.
304def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
305
Craig Topper05242bf2018-04-21 18:07:36 +0000306// Load/store MXCSR.
307def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
308def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
309
Gadi Haber323f2e12017-10-24 20:19:47 +0000310// Nop, not very useful expect it provides a model for nops!
311def : WriteRes<WriteNop, []>;
312
313////////////////////////////////////////////////////////////////////////////////
314// Horizontal add/sub instructions.
315////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000316
Simon Pilgrimef8d3ae2018-04-22 15:25:59 +0000317defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3>;
318defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000319
320// Remaining instrs.
321
322def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
323 let Latency = 1;
324 let NumMicroOps = 1;
325 let ResourceCycles = [1];
326}
Craig Topper5a69a002018-03-21 06:28:42 +0000327def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
328 "MMX_MOVD64grr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000329 "(V?)MOVPDI2DIrr",
330 "(V?)MOVPQIto64rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000331 "VPSLLVQ(Y?)rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000332 "VPSRLVQ(Y?)rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000333 "VTESTPD(Y?)rr",
334 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000335
336def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
337 let Latency = 1;
338 let NumMicroOps = 1;
339 let ResourceCycles = [1];
340}
Craig Topper5a69a002018-03-21 06:28:42 +0000341def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
342 "COM_FST0r",
343 "UCOM_FPr",
344 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000345
346def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
347 let Latency = 1;
348 let NumMicroOps = 1;
349 let ResourceCycles = [1];
350}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000351def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000352 "MMX_MOVD64to64rr",
353 "MMX_MOVQ2DQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000354 "(V?)MOV64toPQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000355 "(V?)MOVDI2PDIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000356 "(V?)PSLLDQ(Y?)ri",
Simon Pilgrim74ccc6a2018-04-21 19:11:55 +0000357 "(V?)PSRLDQ(Y?)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000358
359def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
360 let Latency = 1;
361 let NumMicroOps = 1;
362 let ResourceCycles = [1];
363}
364def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
365
366def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
367 let Latency = 1;
368 let NumMicroOps = 1;
369 let ResourceCycles = [1];
370}
Simon Pilgrim8cd01aa2018-04-23 16:10:50 +0000371def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000372
373def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
374 let Latency = 1;
375 let NumMicroOps = 1;
376 let ResourceCycles = [1];
377}
Craig Topperfbe31322018-04-05 21:56:19 +0000378def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000379def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
380 "ADC(16|32|64)i",
381 "ADC(8|16|32|64)rr",
382 "ADCX(32|64)rr",
383 "ADOX(32|64)rr",
384 "BT(16|32|64)ri8",
385 "BT(16|32|64)rr",
386 "BTC(16|32|64)ri8",
387 "BTC(16|32|64)rr",
388 "BTR(16|32|64)ri8",
389 "BTR(16|32|64)rr",
390 "BTS(16|32|64)ri8",
391 "BTS(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000392 "SBB(16|32|64)ri",
393 "SBB(16|32|64)i",
Craig Topperdfccafe2018-04-18 06:41:25 +0000394 "SBB(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000395
396def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
397 let Latency = 1;
398 let NumMicroOps = 1;
399 let ResourceCycles = [1];
400}
Craig Topper5a69a002018-03-21 06:28:42 +0000401def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
402 "BLSI(32|64)rr",
403 "BLSMSK(32|64)rr",
404 "BLSR(32|64)rr",
Simon Pilgrim74ccc6a2018-04-21 19:11:55 +0000405 "LEA(16|32|64)(_32)?r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000406
407def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
408 let Latency = 1;
409 let NumMicroOps = 1;
410 let ResourceCycles = [1];
411}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000412def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Simon Pilgrimd14d2e72018-04-20 21:16:05 +0000413 "VPBLENDD(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000414
415def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
416 let Latency = 1;
417 let NumMicroOps = 1;
418 let ResourceCycles = [1];
419}
Craig Topperdfccafe2018-04-18 06:41:25 +0000420def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Agner's data
Craig Topper5a69a002018-03-21 06:28:42 +0000421 "NOOP",
Craig Topper655e1db2018-04-17 19:35:14 +0000422 "SAHF", // TODO: This doesn't match Agner's data
Craig Topper5a69a002018-03-21 06:28:42 +0000423 "SGDT64m",
424 "SIDT64m",
425 "SLDT64m",
426 "SMSW16m",
Craig Topper5a69a002018-03-21 06:28:42 +0000427 "STRm",
Craig Topperb5f26592018-04-19 18:00:17 +0000428 "SYSCALL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000429
430def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
431 let Latency = 1;
432 let NumMicroOps = 2;
433 let ResourceCycles = [1,1];
434}
Craig Topper5a69a002018-03-21 06:28:42 +0000435def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
436 "MMX_MOVD64from64rm",
437 "MMX_MOVD64mr",
438 "MMX_MOVNTQmr",
439 "MMX_MOVQ64mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000440 "MOVNTI_64mr",
441 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000442 "ST_FP32m",
443 "ST_FP64m",
444 "ST_FP80m",
445 "VEXTRACTF128mr",
446 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000447 "(V?)MOVAPD(Y?)mr",
448 "(V?)MOVAPS(Y?)mr",
449 "(V?)MOVDQA(Y?)mr",
450 "(V?)MOVDQU(Y?)mr",
451 "(V?)MOVHPDmr",
452 "(V?)MOVHPSmr",
453 "(V?)MOVLPDmr",
454 "(V?)MOVLPSmr",
455 "(V?)MOVNTDQ(V?)mr",
456 "(V?)MOVNTPD(V?)mr",
457 "(V?)MOVNTPS(V?)mr",
458 "(V?)MOVPDI2DImr",
459 "(V?)MOVPQI2QImr",
460 "(V?)MOVPQIto64mr",
461 "(V?)MOVSDmr",
462 "(V?)MOVSSmr",
463 "(V?)MOVUPD(Y?)mr",
464 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000465
466def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
467 let Latency = 2;
468 let NumMicroOps = 2;
469 let ResourceCycles = [2];
470}
Simon Pilgrim96855ec2018-04-22 14:43:12 +0000471def: InstRW<[BWWriteResGroup11], (instregex "MMX_PINSRWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000472 "(V?)PINSRBrr",
473 "(V?)PINSRDrr",
474 "(V?)PINSRQrr",
475 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000476
477def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
478 let Latency = 2;
479 let NumMicroOps = 2;
480 let ResourceCycles = [2];
481}
Simon Pilgrim8cd01aa2018-04-23 16:10:50 +0000482def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000483
484def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
485 let Latency = 2;
486 let NumMicroOps = 2;
487 let ResourceCycles = [2];
488}
Craig Topper5a69a002018-03-21 06:28:42 +0000489def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
490 "ROL(8|16|32|64)ri",
491 "ROR(8|16|32|64)r1",
492 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000493
494def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
495 let Latency = 2;
496 let NumMicroOps = 2;
497 let ResourceCycles = [2];
498}
Craig Topper5a69a002018-03-21 06:28:42 +0000499def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
500 "MFENCE",
501 "WAIT",
502 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000503
504def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
505 let Latency = 2;
506 let NumMicroOps = 2;
507 let ResourceCycles = [1,1];
508}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000509def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
510 "VCVTPH2PS(Y?)rr",
511 "(V?)CVTPS2PDrr",
512 "(V?)CVTSS2SDrr",
513 "(V?)EXTRACTPSrr",
514 "(V?)PEXTRBrr",
515 "(V?)PEXTRDrr",
516 "(V?)PEXTRQrr",
517 "(V?)PEXTRWrr",
518 "(V?)PSLLDrr",
519 "(V?)PSLLQrr",
520 "(V?)PSLLWrr",
521 "(V?)PSRADrr",
522 "(V?)PSRAWrr",
523 "(V?)PSRLDrr",
524 "(V?)PSRLQrr",
525 "(V?)PSRLWrr",
526 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000527
528def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
529 let Latency = 2;
530 let NumMicroOps = 2;
531 let ResourceCycles = [1,1];
532}
533def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
534
535def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
536 let Latency = 2;
537 let NumMicroOps = 2;
538 let ResourceCycles = [1,1];
539}
540def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
541
542def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
543 let Latency = 2;
544 let NumMicroOps = 2;
545 let ResourceCycles = [1,1];
546}
547def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
548
549def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
550 let Latency = 2;
551 let NumMicroOps = 2;
552 let ResourceCycles = [1,1];
553}
Craig Topper498875f2018-04-04 17:54:19 +0000554def: InstRW<[BWWriteResGroup19], (instrs BSWAP64r)>;
555
556def BWWriteResGroup19_1 : SchedWriteRes<[BWPort15]> {
557 let Latency = 1;
558 let NumMicroOps = 1;
559 let ResourceCycles = [1];
560}
561def: InstRW<[BWWriteResGroup19_1], (instrs BSWAP32r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000562
563def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
564 let Latency = 2;
565 let NumMicroOps = 2;
566 let ResourceCycles = [1,1];
567}
Craig Topper2d451e72018-03-18 08:38:06 +0000568def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000569def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000570def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
571 "ADC8ri",
572 "CMOV(A|BE)(16|32|64)rr",
573 "SBB8i8",
574 "SBB8ri",
575 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000576
577def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
578 let Latency = 2;
579 let NumMicroOps = 3;
580 let ResourceCycles = [1,1,1];
581}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000582def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
583 "(V?)PEXTRBmr",
584 "(V?)PEXTRDmr",
585 "(V?)PEXTRQmr",
Craig Topper05242bf2018-04-21 18:07:36 +0000586 "(V?)PEXTRWmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000587
588def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
589 let Latency = 2;
590 let NumMicroOps = 3;
591 let ResourceCycles = [1,1,1];
592}
593def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
594
Gadi Haber323f2e12017-10-24 20:19:47 +0000595def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
596 let Latency = 2;
597 let NumMicroOps = 3;
598 let ResourceCycles = [1,1,1];
599}
600def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
601
602def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
603 let Latency = 2;
604 let NumMicroOps = 3;
605 let ResourceCycles = [1,1,1];
606}
Craig Topper2d451e72018-03-18 08:38:06 +0000607def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000608def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
609 "PUSH64i8",
610 "STOSB",
611 "STOSL",
612 "STOSQ",
613 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000614
Gadi Haber323f2e12017-10-24 20:19:47 +0000615def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
616 let Latency = 3;
617 let NumMicroOps = 1;
618 let ResourceCycles = [1];
619}
Simon Pilgrimc0f654f2018-04-21 11:25:02 +0000620def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000621 "PDEP(32|64)rr",
622 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000623 "SHLD(16|32|64)rri8",
624 "SHRD(16|32|64)rri8",
Simon Pilgrim920802c2018-04-21 21:16:44 +0000625 "(V?)CVTDQ2PS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000626
627def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
Craig Topperf846e2d2018-04-19 05:34:05 +0000628 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000629 let NumMicroOps = 2;
630 let ResourceCycles = [1,1];
631}
Clement Courbet327fac42018-03-07 08:14:02 +0000632def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000633
634def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
635 let Latency = 3;
636 let NumMicroOps = 1;
637 let ResourceCycles = [1];
638}
Simon Pilgrim825ead92018-04-21 20:45:12 +0000639def: InstRW<[BWWriteResGroup28], (instregex "VPBROADCASTBrr",
640 "VPBROADCASTWrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000641 "VPMOVSXBDYrr",
642 "VPMOVSXBQYrr",
643 "VPMOVSXBWYrr",
644 "VPMOVSXDQYrr",
645 "VPMOVSXWDYrr",
646 "VPMOVSXWQYrr",
647 "VPMOVZXBDYrr",
648 "VPMOVZXBQYrr",
649 "VPMOVZXBWYrr",
650 "VPMOVZXDQYrr",
651 "VPMOVZXWDYrr",
652 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000653
654def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
655 let Latency = 3;
656 let NumMicroOps = 1;
657 let ResourceCycles = [1];
658}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000659def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
660 "(V?)MULPS(Y?)rr",
661 "(V?)MULSDrr",
662 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000663
664def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
Craig Topperb5f26592018-04-19 18:00:17 +0000665 let Latency = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000666 let NumMicroOps = 3;
667 let ResourceCycles = [3];
668}
Craig Topperb5f26592018-04-19 18:00:17 +0000669def: InstRW<[BWWriteResGroup30], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
670 XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
671 XCHG16ar, XCHG32ar, XCHG64ar)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000672
673def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
674 let Latency = 3;
675 let NumMicroOps = 3;
676 let ResourceCycles = [2,1];
677}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000678def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
679 "VPSRAVD(Y?)rr",
680 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000681
Gadi Haber323f2e12017-10-24 20:19:47 +0000682def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
683 let Latency = 3;
684 let NumMicroOps = 3;
685 let ResourceCycles = [2,1];
686}
Craig Topper5a69a002018-03-21 06:28:42 +0000687def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
688 "MMX_PACKSSWBirr",
689 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000690
691def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
692 let Latency = 3;
693 let NumMicroOps = 3;
694 let ResourceCycles = [1,2];
695}
696def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
697
698def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
699 let Latency = 3;
700 let NumMicroOps = 3;
701 let ResourceCycles = [1,2];
702}
Craig Topper5a69a002018-03-21 06:28:42 +0000703def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
704 "RCL(8|16|32|64)ri",
705 "RCR(8|16|32|64)r1",
706 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000707
708def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
709 let Latency = 3;
710 let NumMicroOps = 3;
711 let ResourceCycles = [2,1];
712}
Craig Topper5a69a002018-03-21 06:28:42 +0000713def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
714 "ROR(8|16|32|64)rCL",
715 "SAR(8|16|32|64)rCL",
716 "SHL(8|16|32|64)rCL",
717 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000718
719def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
720 let Latency = 3;
721 let NumMicroOps = 4;
722 let ResourceCycles = [1,1,1,1];
723}
724def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
725
726def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
727 let Latency = 3;
728 let NumMicroOps = 4;
729 let ResourceCycles = [1,1,1,1];
730}
Craig Topper5a69a002018-03-21 06:28:42 +0000731def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
732 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000733
734def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
735 let Latency = 4;
736 let NumMicroOps = 2;
737 let ResourceCycles = [1,1];
738}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000739def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
740 "(V?)CVTSD2SIrr",
741 "(V?)CVTSS2SI64rr",
742 "(V?)CVTSS2SIrr",
743 "(V?)CVTTSD2SI64rr",
744 "(V?)CVTTSD2SIrr",
745 "(V?)CVTTSS2SI64rr",
746 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000747
748def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
749 let Latency = 4;
750 let NumMicroOps = 2;
751 let ResourceCycles = [1,1];
752}
Craig Topper5a69a002018-03-21 06:28:42 +0000753def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
754 "VPSLLDYrr",
755 "VPSLLQYrr",
756 "VPSLLWYrr",
757 "VPSRADYrr",
758 "VPSRAWYrr",
759 "VPSRLDYrr",
760 "VPSRLQYrr",
761 "VPSRLWYrr",
762 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000763
764def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
765 let Latency = 4;
766 let NumMicroOps = 2;
767 let ResourceCycles = [1,1];
768}
769def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
770
771def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
772 let Latency = 4;
773 let NumMicroOps = 2;
774 let ResourceCycles = [1,1];
775}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000776def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000777def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000778 "MMX_CVTPI2PDirr",
779 "MMX_CVTPS2PIirr",
780 "MMX_CVTTPD2PIirr",
781 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000782 "(V?)CVTDQ2PDrr",
783 "(V?)CVTPD2DQrr",
784 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000785 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000786 "(V?)CVTSD2SSrr",
787 "(V?)CVTSI642SDrr",
788 "(V?)CVTSI2SDrr",
789 "(V?)CVTSI2SSrr",
790 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000791
792def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
793 let Latency = 4;
794 let NumMicroOps = 4;
Craig Topperf846e2d2018-04-19 05:34:05 +0000795 let ResourceCycles = [1,1,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000796}
Craig Topper5a69a002018-03-21 06:28:42 +0000797def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000798
799def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
800 let Latency = 4;
801 let NumMicroOps = 3;
802 let ResourceCycles = [1,1,1];
803}
804def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
805
806def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
807 let Latency = 4;
808 let NumMicroOps = 3;
809 let ResourceCycles = [1,1,1];
810}
Craig Topper5a69a002018-03-21 06:28:42 +0000811def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
812 "ISTT_FP32m",
813 "ISTT_FP64m",
814 "IST_F16m",
815 "IST_F32m",
816 "IST_FP16m",
817 "IST_FP32m",
818 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000819 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000820
821def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
822 let Latency = 4;
823 let NumMicroOps = 4;
824 let ResourceCycles = [4];
825}
Simon Pilgrim8cd01aa2018-04-23 16:10:50 +0000826def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000827
828def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
829 let Latency = 4;
830 let NumMicroOps = 4;
831 let ResourceCycles = [1,3];
832}
833def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
834
835def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
836 let Latency = 5;
837 let NumMicroOps = 1;
838 let ResourceCycles = [1];
839}
Simon Pilgrim74ccc6a2018-04-21 19:11:55 +0000840def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000841
Gadi Haber323f2e12017-10-24 20:19:47 +0000842def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
843 let Latency = 5;
844 let NumMicroOps = 1;
845 let ResourceCycles = [1];
846}
Simon Pilgrim02fc3752018-04-21 12:15:42 +0000847def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16",
Craig Topper5a69a002018-03-21 06:28:42 +0000848 "MOVSX(16|32|64)rm32",
849 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000850 "MOVZX(16|32|64)rm16",
851 "MOVZX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000852 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000853 "(V?)MOVDDUPrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000854 "(V?)MOVSHDUPrm",
855 "(V?)MOVSLDUPrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000856 "VPBROADCASTDrm",
857 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000858
859def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
860 let Latency = 5;
861 let NumMicroOps = 3;
862 let ResourceCycles = [1,2];
863}
Simon Pilgrimef8d3ae2018-04-22 15:25:59 +0000864def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000865
866def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
867 let Latency = 5;
868 let NumMicroOps = 3;
869 let ResourceCycles = [1,1,1];
870}
871def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
872
873def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000874 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000875 let NumMicroOps = 3;
876 let ResourceCycles = [1,1,1];
877}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000878def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000879
880def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
881 let Latency = 5;
882 let NumMicroOps = 4;
883 let ResourceCycles = [1,1,1,1];
884}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000885def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
886 "VMASKMOVPS(Y?)mr",
887 "VPMASKMOVD(Y?)mr",
888 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000889
890def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
891 let Latency = 5;
892 let NumMicroOps = 5;
893 let ResourceCycles = [1,4];
894}
895def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
896
897def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
898 let Latency = 5;
899 let NumMicroOps = 5;
900 let ResourceCycles = [1,4];
901}
902def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
903
904def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
905 let Latency = 5;
906 let NumMicroOps = 5;
907 let ResourceCycles = [2,3];
908}
Craig Topper5a69a002018-03-21 06:28:42 +0000909def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000910
911def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
912 let Latency = 5;
913 let NumMicroOps = 6;
914 let ResourceCycles = [1,1,4];
915}
Craig Topper5a69a002018-03-21 06:28:42 +0000916def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000917
918def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
919 let Latency = 6;
920 let NumMicroOps = 1;
921 let ResourceCycles = [1];
922}
Craig Topper5a69a002018-03-21 06:28:42 +0000923def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
924 "LD_F64m",
925 "LD_F80m",
926 "VBROADCASTF128",
927 "VBROADCASTI128",
928 "VBROADCASTSDYrm",
929 "VBROADCASTSSYrm",
930 "VLDDQUYrm",
931 "VMOVAPDYrm",
932 "VMOVAPSYrm",
933 "VMOVDDUPYrm",
934 "VMOVDQAYrm",
935 "VMOVDQUYrm",
936 "VMOVNTDQAYrm",
937 "VMOVSHDUPYrm",
938 "VMOVSLDUPYrm",
939 "VMOVUPDYrm",
940 "VMOVUPSYrm",
941 "VPBROADCASTDYrm",
942 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000943 "(V?)ROUNDPD(Y?)r",
944 "(V?)ROUNDPS(Y?)r",
945 "(V?)ROUNDSDr",
946 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000947
948def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
949 let Latency = 6;
950 let NumMicroOps = 2;
951 let ResourceCycles = [1,1];
952}
Simon Pilgrim0a334a82018-04-23 11:57:15 +0000953def: InstRW<[BWWriteResGroup59], (instregex "VCVTPH2PS(Y?)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000954 "(V?)CVTPS2PDrm",
955 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000956 "VPSLLVQrm",
957 "VPSRLVQrm",
958 "VTESTPDrm",
959 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000960
961def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
962 let Latency = 6;
963 let NumMicroOps = 2;
964 let ResourceCycles = [1,1];
965}
Craig Topper5a69a002018-03-21 06:28:42 +0000966def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
967 "VCVTPD2DQYrr",
968 "VCVTPD2PSYrr",
969 "VCVTPS2PHYrr",
970 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000971
972def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
973 let Latency = 6;
974 let NumMicroOps = 2;
975 let ResourceCycles = [1,1];
976}
Simon Pilgrim0a334a82018-04-23 11:57:15 +0000977def: InstRW<[BWWriteResGroup61], (instregex "(V?)INSERTPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000978 "(V?)MOVHPDrm",
979 "(V?)MOVHPSrm",
980 "(V?)MOVLPDrm",
981 "(V?)MOVLPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000982 "(V?)PACKSSDWrm",
983 "(V?)PACKSSWBrm",
984 "(V?)PACKUSDWrm",
985 "(V?)PACKUSWBrm",
986 "(V?)PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000987 "VPERMILPDmi",
988 "VPERMILPDrm",
989 "VPERMILPSmi",
990 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000991 "(V?)PINSRBrm",
992 "(V?)PINSRDrm",
993 "(V?)PINSRQrm",
994 "(V?)PINSRWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000995 "(V?)PSHUFBrm",
996 "(V?)PSHUFDmi",
997 "(V?)PSHUFHWmi",
998 "(V?)PSHUFLWmi",
999 "(V?)PUNPCKHBWrm",
1000 "(V?)PUNPCKHDQrm",
1001 "(V?)PUNPCKHQDQrm",
1002 "(V?)PUNPCKHWDrm",
1003 "(V?)PUNPCKLBWrm",
1004 "(V?)PUNPCKLDQrm",
1005 "(V?)PUNPCKLQDQrm",
1006 "(V?)PUNPCKLWDrm",
1007 "(V?)SHUFPDrmi",
1008 "(V?)SHUFPSrmi",
1009 "(V?)UNPCKHPDrm",
1010 "(V?)UNPCKHPSrm",
1011 "(V?)UNPCKLPDrm",
Simon Pilgrimd14d2e72018-04-20 21:16:05 +00001012 "(V?)UNPCKLPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001013
1014def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1015 let Latency = 6;
1016 let NumMicroOps = 2;
1017 let ResourceCycles = [1,1];
1018}
Craig Topper5a69a002018-03-21 06:28:42 +00001019def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1020 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001021
1022def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1023 let Latency = 6;
1024 let NumMicroOps = 2;
1025 let ResourceCycles = [1,1];
1026}
Craig Topperdfccafe2018-04-18 06:41:25 +00001027def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
Craig Topperc50570f2018-04-06 17:12:18 +00001028def: InstRW<[BWWriteResGroup63, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
1029 ADCX32rm, ADCX64rm,
1030 ADOX32rm, ADOX64rm,
1031 SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001032
1033def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1034 let Latency = 6;
1035 let NumMicroOps = 2;
1036 let ResourceCycles = [1,1];
1037}
Craig Topper5a69a002018-03-21 06:28:42 +00001038def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1039 "BLSI(32|64)rm",
1040 "BLSMSK(32|64)rm",
1041 "BLSR(32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +00001042 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001043 "(V?)PABSBrm",
1044 "(V?)PABSDrm",
1045 "(V?)PABSWrm",
1046 "(V?)PADDBrm",
1047 "(V?)PADDDrm",
1048 "(V?)PADDQrm",
1049 "(V?)PADDSBrm",
1050 "(V?)PADDSWrm",
1051 "(V?)PADDUSBrm",
1052 "(V?)PADDUSWrm",
1053 "(V?)PADDWrm",
1054 "(V?)PAVGBrm",
1055 "(V?)PAVGWrm",
1056 "(V?)PCMPEQBrm",
1057 "(V?)PCMPEQDrm",
1058 "(V?)PCMPEQQrm",
1059 "(V?)PCMPEQWrm",
1060 "(V?)PCMPGTBrm",
1061 "(V?)PCMPGTDrm",
1062 "(V?)PCMPGTWrm",
1063 "(V?)PMAXSBrm",
1064 "(V?)PMAXSDrm",
1065 "(V?)PMAXSWrm",
1066 "(V?)PMAXUBrm",
1067 "(V?)PMAXUDrm",
1068 "(V?)PMAXUWrm",
1069 "(V?)PMINSBrm",
1070 "(V?)PMINSDrm",
1071 "(V?)PMINSWrm",
1072 "(V?)PMINUBrm",
1073 "(V?)PMINUDrm",
1074 "(V?)PMINUWrm",
1075 "(V?)PSIGNBrm",
1076 "(V?)PSIGNDrm",
1077 "(V?)PSIGNWrm",
1078 "(V?)PSUBBrm",
1079 "(V?)PSUBDrm",
1080 "(V?)PSUBQrm",
1081 "(V?)PSUBSBrm",
1082 "(V?)PSUBSWrm",
1083 "(V?)PSUBUSBrm",
1084 "(V?)PSUBUSWrm",
1085 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001086
1087def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1088 let Latency = 6;
1089 let NumMicroOps = 2;
1090 let ResourceCycles = [1,1];
1091}
Simon Pilgrim06e16542018-04-22 18:35:53 +00001092def: InstRW<[BWWriteResGroup65], (instregex "VINSERTF128rm",
Craig Topper5a69a002018-03-21 06:28:42 +00001093 "VINSERTI128rm",
Simon Pilgrimd14d2e72018-04-20 21:16:05 +00001094 "VPBLENDDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001095
1096def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1097 let Latency = 6;
1098 let NumMicroOps = 2;
1099 let ResourceCycles = [1,1];
1100}
Craig Topper2d451e72018-03-18 08:38:06 +00001101def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topperf0d04262018-04-06 16:16:48 +00001102def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001103
1104def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1105 let Latency = 6;
1106 let NumMicroOps = 4;
1107 let ResourceCycles = [1,1,2];
1108}
Craig Topper5a69a002018-03-21 06:28:42 +00001109def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1110 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001111
1112def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1113 let Latency = 6;
1114 let NumMicroOps = 4;
1115 let ResourceCycles = [1,1,1,1];
1116}
1117def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1118
1119def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1120 let Latency = 6;
1121 let NumMicroOps = 4;
1122 let ResourceCycles = [1,1,1,1];
1123}
Craig Topper5a69a002018-03-21 06:28:42 +00001124def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1125 "BTR(16|32|64)mi8",
1126 "BTS(16|32|64)mi8",
1127 "SAR(8|16|32|64)m1",
1128 "SAR(8|16|32|64)mi",
1129 "SHL(8|16|32|64)m1",
1130 "SHL(8|16|32|64)mi",
1131 "SHR(8|16|32|64)m1",
1132 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001133
1134def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1135 let Latency = 6;
1136 let NumMicroOps = 4;
1137 let ResourceCycles = [1,1,1,1];
1138}
Craig Topperf0d04262018-04-06 16:16:48 +00001139def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1140 "PUSH(16|32|64)rmm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001141
1142def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1143 let Latency = 6;
1144 let NumMicroOps = 6;
1145 let ResourceCycles = [1,5];
1146}
1147def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1148
Gadi Haber323f2e12017-10-24 20:19:47 +00001149def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1150 let Latency = 7;
1151 let NumMicroOps = 2;
1152 let ResourceCycles = [1,1];
1153}
Craig Topper5a69a002018-03-21 06:28:42 +00001154def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1155 "VPSLLQYrm",
1156 "VPSLLVQYrm",
1157 "VPSLLWYrm",
1158 "VPSRADYrm",
1159 "VPSRAWYrm",
1160 "VPSRLDYrm",
1161 "VPSRLQYrm",
1162 "VPSRLVQYrm",
1163 "VPSRLWYrm",
1164 "VTESTPDYrm",
1165 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001166
1167def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1168 let Latency = 7;
1169 let NumMicroOps = 2;
1170 let ResourceCycles = [1,1];
1171}
Craig Topper5a69a002018-03-21 06:28:42 +00001172def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1173 "FCOM64m",
1174 "FCOMP32m",
1175 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001176
1177def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1178 let Latency = 7;
1179 let NumMicroOps = 2;
1180 let ResourceCycles = [1,1];
1181}
Craig Topper5a69a002018-03-21 06:28:42 +00001182def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1183 "VANDNPSYrm",
1184 "VANDPDYrm",
1185 "VANDPSYrm",
1186 "VORPDYrm",
1187 "VORPSYrm",
1188 "VPACKSSDWYrm",
1189 "VPACKSSWBYrm",
1190 "VPACKUSDWYrm",
1191 "VPACKUSWBYrm",
1192 "VPALIGNRYrmi",
1193 "VPBLENDWYrmi",
1194 "VPERMILPDYmi",
1195 "VPERMILPDYrm",
1196 "VPERMILPSYmi",
1197 "VPERMILPSYrm",
1198 "VPSHUFBYrm",
1199 "VPSHUFDYmi",
1200 "VPSHUFHWYmi",
1201 "VPSHUFLWYmi",
1202 "VPUNPCKHBWYrm",
1203 "VPUNPCKHDQYrm",
1204 "VPUNPCKHQDQYrm",
1205 "VPUNPCKHWDYrm",
1206 "VPUNPCKLBWYrm",
1207 "VPUNPCKLDQYrm",
1208 "VPUNPCKLQDQYrm",
1209 "VPUNPCKLWDYrm",
1210 "VSHUFPDYrmi",
1211 "VSHUFPSYrmi",
1212 "VUNPCKHPDYrm",
1213 "VUNPCKHPSYrm",
1214 "VUNPCKLPDYrm",
1215 "VUNPCKLPSYrm",
1216 "VXORPDYrm",
1217 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001218
1219def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1220 let Latency = 7;
1221 let NumMicroOps = 2;
1222 let ResourceCycles = [1,1];
1223}
Craig Topper5a69a002018-03-21 06:28:42 +00001224def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1225 "VPABSDYrm",
1226 "VPABSWYrm",
1227 "VPADDBYrm",
1228 "VPADDDYrm",
1229 "VPADDQYrm",
1230 "VPADDSBYrm",
1231 "VPADDSWYrm",
1232 "VPADDUSBYrm",
1233 "VPADDUSWYrm",
1234 "VPADDWYrm",
1235 "VPAVGBYrm",
1236 "VPAVGWYrm",
1237 "VPCMPEQBYrm",
1238 "VPCMPEQDYrm",
1239 "VPCMPEQQYrm",
1240 "VPCMPEQWYrm",
1241 "VPCMPGTBYrm",
1242 "VPCMPGTDYrm",
1243 "VPCMPGTWYrm",
1244 "VPMAXSBYrm",
1245 "VPMAXSDYrm",
1246 "VPMAXSWYrm",
1247 "VPMAXUBYrm",
1248 "VPMAXUDYrm",
1249 "VPMAXUWYrm",
1250 "VPMINSBYrm",
1251 "VPMINSDYrm",
1252 "VPMINSWYrm",
1253 "VPMINUBYrm",
1254 "VPMINUDYrm",
1255 "VPMINUWYrm",
1256 "VPSIGNBYrm",
1257 "VPSIGNDYrm",
1258 "VPSIGNWYrm",
1259 "VPSUBBYrm",
1260 "VPSUBDYrm",
1261 "VPSUBQYrm",
1262 "VPSUBSBYrm",
1263 "VPSUBSWYrm",
1264 "VPSUBUSBYrm",
1265 "VPSUBUSWYrm",
1266 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001267
1268def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1269 let Latency = 7;
1270 let NumMicroOps = 2;
1271 let ResourceCycles = [1,1];
1272}
Craig Topper5a69a002018-03-21 06:28:42 +00001273def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1274 "VBLENDPSYrmi",
1275 "VPANDNYrm",
1276 "VPANDYrm",
1277 "VPBLENDDYrmi",
1278 "VPORYrm",
1279 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001280
Gadi Haber323f2e12017-10-24 20:19:47 +00001281def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1282 let Latency = 7;
1283 let NumMicroOps = 3;
1284 let ResourceCycles = [2,1];
1285}
Simon Pilgrim96855ec2018-04-22 14:43:12 +00001286def: InstRW<[BWWriteResGroup79], (instregex "MMX_PACKSSDWirm",
Craig Topper5a69a002018-03-21 06:28:42 +00001287 "MMX_PACKSSWBirm",
1288 "MMX_PACKUSWBirm",
Craig Topper5a69a002018-03-21 06:28:42 +00001289 "VMASKMOVPDrm",
1290 "VMASKMOVPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +00001291 "VPMASKMOVDrm",
1292 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001293
1294def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1295 let Latency = 7;
1296 let NumMicroOps = 3;
1297 let ResourceCycles = [1,2];
1298}
Craig Topper3b0b96c2018-04-05 21:16:26 +00001299def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1300 SCASB, SCASL, SCASQ, SCASW)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001301
1302def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1303 let Latency = 7;
1304 let NumMicroOps = 3;
1305 let ResourceCycles = [1,1,1];
1306}
Craig Topper5a69a002018-03-21 06:28:42 +00001307def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1308 "PSLLQrm",
1309 "PSLLWrm",
1310 "PSRADrm",
1311 "PSRAWrm",
1312 "PSRLDrm",
1313 "PSRLQrm",
1314 "PSRLWrm",
1315 "PTESTrm",
1316 "VPSLLDrm",
1317 "VPSLLQrm",
1318 "VPSLLWrm",
1319 "VPSRADrm",
1320 "VPSRAWrm",
1321 "VPSRLDrm",
1322 "VPSRLQrm",
1323 "VPSRLWrm",
1324 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001325
1326def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1327 let Latency = 7;
1328 let NumMicroOps = 3;
1329 let ResourceCycles = [1,1,1];
1330}
1331def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1332
Gadi Haber323f2e12017-10-24 20:19:47 +00001333def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1334 let Latency = 7;
1335 let NumMicroOps = 3;
1336 let ResourceCycles = [1,1,1];
1337}
Craig Topper5a69a002018-03-21 06:28:42 +00001338def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1339 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001340
Gadi Haber323f2e12017-10-24 20:19:47 +00001341def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1342 let Latency = 7;
1343 let NumMicroOps = 3;
1344 let ResourceCycles = [1,1,1];
1345}
Craig Topperf4cd9082018-01-19 05:47:32 +00001346def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001347
1348def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1349 let Latency = 7;
1350 let NumMicroOps = 5;
1351 let ResourceCycles = [1,1,1,2];
1352}
Craig Topper5a69a002018-03-21 06:28:42 +00001353def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1354 "ROL(8|16|32|64)mi",
1355 "ROR(8|16|32|64)m1",
1356 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001357
1358def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1359 let Latency = 7;
1360 let NumMicroOps = 5;
1361 let ResourceCycles = [1,1,1,2];
1362}
Craig Topper5a69a002018-03-21 06:28:42 +00001363def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001364
1365def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1366 let Latency = 7;
1367 let NumMicroOps = 5;
1368 let ResourceCycles = [1,1,1,1,1];
1369}
Craig Topper5a69a002018-03-21 06:28:42 +00001370def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1371 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001372
1373def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1374 let Latency = 7;
1375 let NumMicroOps = 7;
1376 let ResourceCycles = [2,2,1,2];
1377}
Craig Topper2d451e72018-03-18 08:38:06 +00001378def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001379
1380def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1381 let Latency = 8;
1382 let NumMicroOps = 2;
1383 let ResourceCycles = [1,1];
1384}
Simon Pilgrimf33d9052018-03-26 18:19:28 +00001385def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +00001386 "PDEP(32|64)rm",
1387 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001388 "(V?)ADDPDrm",
1389 "(V?)ADDPSrm",
1390 "(V?)ADDSDrm",
1391 "(V?)ADDSSrm",
1392 "(V?)ADDSUBPDrm",
1393 "(V?)ADDSUBPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001394 "(V?)CVTDQ2PSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001395 "(V?)SUBPDrm",
1396 "(V?)SUBPSrm",
1397 "(V?)SUBSDrm",
Simon Pilgrim86e3c2692018-04-17 07:22:44 +00001398 "(V?)SUBSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001399
1400def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
Craig Topperf846e2d2018-04-19 05:34:05 +00001401 let Latency = 8;
Gadi Haber323f2e12017-10-24 20:19:47 +00001402 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001403 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +00001404}
Craig Topperf846e2d2018-04-19 05:34:05 +00001405def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001406
Craig Topperf846e2d2018-04-19 05:34:05 +00001407def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort06, BWPort0156, BWPort23]> {
1408 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +00001409 let NumMicroOps = 5;
Craig Topperf846e2d2018-04-19 05:34:05 +00001410 let ResourceCycles = [1,1,2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +00001411}
Craig Topper5a69a002018-03-21 06:28:42 +00001412def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001413
Gadi Haber323f2e12017-10-24 20:19:47 +00001414def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1415 let Latency = 8;
1416 let NumMicroOps = 2;
1417 let ResourceCycles = [1,1];
1418}
Craig Topper5a69a002018-03-21 06:28:42 +00001419def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1420 "VPMOVSXBQYrm",
1421 "VPMOVSXBWYrm",
1422 "VPMOVSXDQYrm",
1423 "VPMOVSXWDYrm",
1424 "VPMOVSXWQYrm",
1425 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001426
1427def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1428 let Latency = 8;
1429 let NumMicroOps = 2;
1430 let ResourceCycles = [1,1];
1431}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001432def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1433 "(V?)MULPSrm",
1434 "(V?)MULSDrm",
1435 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001436
1437def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1438 let Latency = 8;
1439 let NumMicroOps = 3;
1440 let ResourceCycles = [2,1];
1441}
Craig Topper5a69a002018-03-21 06:28:42 +00001442def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1443 "VBLENDVPSYrm",
1444 "VMASKMOVPDYrm",
1445 "VMASKMOVPSYrm",
1446 "VPBLENDVBYrm",
1447 "VPMASKMOVDYrm",
1448 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001449
1450def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1451 let Latency = 8;
1452 let NumMicroOps = 4;
1453 let ResourceCycles = [2,1,1];
1454}
Craig Topper5a69a002018-03-21 06:28:42 +00001455def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1456 "VPSRAVDrm",
1457 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001458
Gadi Haber323f2e12017-10-24 20:19:47 +00001459def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1460 let Latency = 8;
1461 let NumMicroOps = 5;
1462 let ResourceCycles = [1,1,1,2];
1463}
Craig Topper5a69a002018-03-21 06:28:42 +00001464def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
1465 "RCL(8|16|32|64)mi",
1466 "RCR(8|16|32|64)m1",
1467 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001468
1469def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1470 let Latency = 8;
1471 let NumMicroOps = 5;
1472 let ResourceCycles = [1,1,2,1];
1473}
Craig Topper13a16502018-03-19 00:56:09 +00001474def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001475
1476def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1477 let Latency = 8;
1478 let NumMicroOps = 6;
1479 let ResourceCycles = [1,1,1,3];
1480}
Craig Topper9f834812018-04-01 21:54:24 +00001481def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001482
1483def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1484 let Latency = 8;
1485 let NumMicroOps = 6;
1486 let ResourceCycles = [1,1,1,2,1];
1487}
Craig Topper9f834812018-04-01 21:54:24 +00001488def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
Craig Topper5a69a002018-03-21 06:28:42 +00001489 "CMPXCHG(8|16|32|64)rm",
1490 "ROL(8|16|32|64)mCL",
1491 "SAR(8|16|32|64)mCL",
1492 "SBB(8|16|32|64)mi",
Craig Topper5a69a002018-03-21 06:28:42 +00001493 "SHL(8|16|32|64)mCL",
1494 "SHR(8|16|32|64)mCL")>;
Craig Topperc50570f2018-04-06 17:12:18 +00001495def: InstRW<[BWWriteResGroup100, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
1496 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001497
1498def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1499 let Latency = 9;
1500 let NumMicroOps = 2;
1501 let ResourceCycles = [1,1];
1502}
Craig Topper5a69a002018-03-21 06:28:42 +00001503def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
1504 "ADD_F64m",
1505 "ILD_F16m",
1506 "ILD_F32m",
1507 "ILD_F64m",
1508 "SUBR_F32m",
1509 "SUBR_F64m",
1510 "SUB_F32m",
1511 "SUB_F64m",
1512 "VADDPDYrm",
1513 "VADDPSYrm",
1514 "VADDSUBPDYrm",
1515 "VADDSUBPSYrm",
1516 "VCMPPDYrmi",
1517 "VCMPPSYrmi",
Craig Topper5a69a002018-03-21 06:28:42 +00001518 "VCVTPS2DQYrm",
1519 "VCVTTPS2DQYrm",
1520 "VMAX(C?)PDYrm",
1521 "VMAX(C?)PSYrm",
1522 "VMIN(C?)PDYrm",
1523 "VMIN(C?)PSYrm",
1524 "VSUBPDYrm",
1525 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001526
1527def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
1528 let Latency = 9;
1529 let NumMicroOps = 2;
1530 let ResourceCycles = [1,1];
1531}
Craig Topper5a69a002018-03-21 06:28:42 +00001532def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
1533 "VPERM2I128rm",
1534 "VPERMDYrm",
1535 "VPERMPDYmi",
1536 "VPERMPSYrm",
1537 "VPERMQYmi",
1538 "VPMOVZXBDYrm",
1539 "VPMOVZXBQYrm",
1540 "VPMOVZXBWYrm",
1541 "VPMOVZXDQYrm",
1542 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001543
1544def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
1545 let Latency = 9;
1546 let NumMicroOps = 2;
1547 let ResourceCycles = [1,1];
1548}
Craig Topper5a69a002018-03-21 06:28:42 +00001549def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
1550 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001551
1552def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
1553 let Latency = 9;
1554 let NumMicroOps = 3;
1555 let ResourceCycles = [1,1,1];
1556}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001557def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001558
1559def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1560 let Latency = 9;
1561 let NumMicroOps = 3;
1562 let ResourceCycles = [1,1,1];
1563}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001564def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
1565 "(V?)CVTSD2SIrm",
1566 "(V?)CVTSS2SI64rm",
1567 "(V?)CVTSS2SIrm",
1568 "(V?)CVTTSD2SI64rm",
1569 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +00001570 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001571 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001572
1573def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1574 let Latency = 9;
1575 let NumMicroOps = 3;
1576 let ResourceCycles = [1,1,1];
1577}
1578def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
1579
1580def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1581 let Latency = 9;
1582 let NumMicroOps = 3;
1583 let ResourceCycles = [1,1,1];
1584}
Craig Topper4a3be6e2018-03-22 19:22:51 +00001585def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001586def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +00001587 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +00001588 "CVTTPD2DQrm",
1589 "MMX_CVTPD2PIirm",
1590 "MMX_CVTPI2PDirm",
1591 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001592 "(V?)CVTDQ2PDrm",
1593 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001594
1595def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1596 let Latency = 9;
1597 let NumMicroOps = 3;
1598 let ResourceCycles = [1,1,1];
1599}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001600def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1601 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001602
1603def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1604 let Latency = 9;
1605 let NumMicroOps = 4;
1606 let ResourceCycles = [2,1,1];
1607}
Craig Topper5a69a002018-03-21 06:28:42 +00001608def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
1609 "VPSRAVDYrm",
1610 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001611
1612def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1613 let Latency = 9;
1614 let NumMicroOps = 4;
1615 let ResourceCycles = [2,1,1];
1616}
Craig Topper5a69a002018-03-21 06:28:42 +00001617def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
1618 "VPHADDSWYrm",
1619 "VPHADDWYrm",
1620 "VPHSUBDYrm",
1621 "VPHSUBSWYrm",
1622 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001623
1624def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
1625 let Latency = 9;
1626 let NumMicroOps = 4;
1627 let ResourceCycles = [1,1,1,1];
1628}
Craig Topper5a69a002018-03-21 06:28:42 +00001629def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
1630 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001631
1632def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1633 let Latency = 9;
1634 let NumMicroOps = 5;
1635 let ResourceCycles = [1,1,3];
1636}
1637def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
1638
1639def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1640 let Latency = 9;
1641 let NumMicroOps = 5;
1642 let ResourceCycles = [1,2,1,1];
1643}
Craig Topper5a69a002018-03-21 06:28:42 +00001644def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1645 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001646
Gadi Haber323f2e12017-10-24 20:19:47 +00001647def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1648 let Latency = 10;
1649 let NumMicroOps = 2;
1650 let ResourceCycles = [1,1];
1651}
Simon Pilgrim0a334a82018-04-23 11:57:15 +00001652def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001653 "(V?)PHMINPOSUWrm",
1654 "(V?)PMADDUBSWrm",
1655 "(V?)PMADDWDrm",
Simon Pilgrim091680b2018-04-22 18:09:50 +00001656 "(V?)PSADBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001657
1658def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
1659 let Latency = 10;
1660 let NumMicroOps = 2;
1661 let ResourceCycles = [1,1];
1662}
Craig Topperf82867c2017-12-13 23:11:30 +00001663def: InstRW<[BWWriteResGroup116],
1664 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
1665 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001666
1667def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1668 let Latency = 10;
1669 let NumMicroOps = 3;
1670 let ResourceCycles = [2,1];
1671}
Craig Topper5a69a002018-03-21 06:28:42 +00001672def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
1673 "FICOM32m",
1674 "FICOMP16m",
1675 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001676
1677def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1678 let Latency = 10;
1679 let NumMicroOps = 3;
1680 let ResourceCycles = [1,1,1];
1681}
1682def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
1683
Gadi Haber323f2e12017-10-24 20:19:47 +00001684def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1685 let Latency = 10;
1686 let NumMicroOps = 4;
1687 let ResourceCycles = [1,1,1,1];
1688}
1689def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1690
1691def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +00001692 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +00001693 let NumMicroOps = 4;
1694 let ResourceCycles = [1,1,1,1];
1695}
Craig Topper4a3be6e2018-03-22 19:22:51 +00001696def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001697
Craig Topper8104f262018-04-02 05:33:28 +00001698def BWWriteResGroup122 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00001699 let Latency = 11;
1700 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +00001701 let ResourceCycles = [1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +00001702}
Craig Topper8104f262018-04-02 05:33:28 +00001703def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr")>;
1704
1705def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1706 let Latency = 11;
1707 let NumMicroOps = 1;
1708 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1709}
1710def: InstRW<[BWWriteResGroup122_1], (instregex "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001711
1712def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1713 let Latency = 11;
1714 let NumMicroOps = 2;
1715 let ResourceCycles = [1,1];
1716}
Craig Topper5a69a002018-03-21 06:28:42 +00001717def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
1718 "MUL_F64m",
1719 "VPCMPGTQYrm",
1720 "VPMADDUBSWYrm",
1721 "VPMADDWDYrm",
1722 "VPMULDQYrm",
1723 "VPMULHRSWYrm",
1724 "VPMULHUWYrm",
1725 "VPMULHWYrm",
1726 "VPMULLWYrm",
1727 "VPMULUDQYrm",
1728 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001729
1730def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
1731 let Latency = 11;
1732 let NumMicroOps = 2;
1733 let ResourceCycles = [1,1];
1734}
Craig Topperf82867c2017-12-13 23:11:30 +00001735def: InstRW<[BWWriteResGroup124],
1736 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001737
Gadi Haber323f2e12017-10-24 20:19:47 +00001738def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
1739 let Latency = 11;
1740 let NumMicroOps = 3;
1741 let ResourceCycles = [2,1];
1742}
Craig Topper5a69a002018-03-21 06:28:42 +00001743def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
1744 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001745
1746def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
1747 let Latency = 11;
1748 let NumMicroOps = 3;
1749 let ResourceCycles = [2,1];
1750}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001751def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
1752 "(V?)ROUNDPSm",
1753 "(V?)ROUNDSDm",
1754 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001755
1756def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1757 let Latency = 11;
1758 let NumMicroOps = 3;
1759 let ResourceCycles = [1,1,1];
1760}
1761def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
1762
1763def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1764 let Latency = 11;
1765 let NumMicroOps = 4;
1766 let ResourceCycles = [1,2,1];
1767}
Craig Topper5a69a002018-03-21 06:28:42 +00001768def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
1769 "VHADDPSYrm",
1770 "VHSUBPDYrm",
1771 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001772
1773def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1774 let Latency = 11;
1775 let NumMicroOps = 6;
1776 let ResourceCycles = [1,1,1,1,2];
1777}
Craig Topper5a69a002018-03-21 06:28:42 +00001778def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
1779 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001780
1781def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1782 let Latency = 11;
1783 let NumMicroOps = 7;
1784 let ResourceCycles = [2,2,3];
1785}
Craig Topper5a69a002018-03-21 06:28:42 +00001786def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1787 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001788
1789def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1790 let Latency = 11;
1791 let NumMicroOps = 9;
1792 let ResourceCycles = [1,4,1,3];
1793}
1794def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
1795
1796def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1797 let Latency = 11;
1798 let NumMicroOps = 11;
1799 let ResourceCycles = [2,9];
1800}
Craig Topper2d451e72018-03-18 08:38:06 +00001801def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1802def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001803
Gadi Haber323f2e12017-10-24 20:19:47 +00001804def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1805 let Latency = 12;
1806 let NumMicroOps = 3;
1807 let ResourceCycles = [2,1];
1808}
Craig Topper5a69a002018-03-21 06:28:42 +00001809def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
1810 "ADD_FI32m",
1811 "SUBR_FI16m",
1812 "SUBR_FI32m",
1813 "SUB_FI16m",
1814 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +00001815 "VROUNDPDYm",
1816 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001817
Craig Topper8104f262018-04-02 05:33:28 +00001818def BWWriteResGroup137 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +00001819 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +00001820 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +00001821 let ResourceCycles = [1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +00001822}
Craig Topper8104f262018-04-02 05:33:28 +00001823def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr")>;
1824
1825def BWWriteResGroup137_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1826 let Latency = 11;
1827 let NumMicroOps = 1;
1828 let ResourceCycles = [1,4];
1829}
1830def: InstRW<[BWWriteResGroup137_1], (instregex "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001831
1832def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1833 let Latency = 13;
1834 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +00001835 let ResourceCycles = [1,2,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +00001836}
1837def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
1838
Craig Topper8104f262018-04-02 05:33:28 +00001839def BWWriteResGroup139 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00001840 let Latency = 14;
1841 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +00001842 let ResourceCycles = [1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +00001843}
Craig Topper8104f262018-04-02 05:33:28 +00001844def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr")>;
1845
1846def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1847 let Latency = 14;
1848 let NumMicroOps = 1;
1849 let ResourceCycles = [1,4];
1850}
1851def: InstRW<[BWWriteResGroup139_1], (instregex "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001852
Gadi Haber323f2e12017-10-24 20:19:47 +00001853def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1854 let Latency = 14;
1855 let NumMicroOps = 3;
1856 let ResourceCycles = [1,1,1];
1857}
Craig Topper5a69a002018-03-21 06:28:42 +00001858def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
1859 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001860
1861def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
1862 let Latency = 14;
1863 let NumMicroOps = 4;
1864 let ResourceCycles = [2,1,1];
1865}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001866def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001867
1868def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1869 let Latency = 14;
1870 let NumMicroOps = 4;
1871 let ResourceCycles = [1,1,1,1];
1872}
Craig Topper5a69a002018-03-21 06:28:42 +00001873def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001874
1875def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1876 let Latency = 14;
1877 let NumMicroOps = 8;
1878 let ResourceCycles = [2,2,1,3];
1879}
1880def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1881
1882def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1883 let Latency = 14;
1884 let NumMicroOps = 10;
1885 let ResourceCycles = [2,3,1,4];
1886}
1887def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
1888
1889def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1890 let Latency = 14;
1891 let NumMicroOps = 12;
1892 let ResourceCycles = [2,1,4,5];
1893}
1894def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
1895
1896def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1897 let Latency = 15;
1898 let NumMicroOps = 1;
1899 let ResourceCycles = [1];
1900}
Craig Topper5a69a002018-03-21 06:28:42 +00001901def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
1902 "DIVR_FST0r",
1903 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001904
Gadi Haber323f2e12017-10-24 20:19:47 +00001905def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1906 let Latency = 15;
1907 let NumMicroOps = 10;
1908 let ResourceCycles = [1,1,1,4,1,2];
1909}
Craig Topper13a16502018-03-19 00:56:09 +00001910def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001911
Craig Topper8104f262018-04-02 05:33:28 +00001912def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00001913 let Latency = 16;
1914 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +00001915 let ResourceCycles = [1,1,5];
Gadi Haber323f2e12017-10-24 20:19:47 +00001916}
Craig Topper5a69a002018-03-21 06:28:42 +00001917def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
1918 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001919
1920def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
1921 let Latency = 16;
1922 let NumMicroOps = 3;
1923 let ResourceCycles = [2,1];
1924}
1925def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
1926
Gadi Haber323f2e12017-10-24 20:19:47 +00001927def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1928 let Latency = 16;
1929 let NumMicroOps = 14;
1930 let ResourceCycles = [1,1,1,4,2,5];
1931}
1932def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
1933
1934def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
1935 let Latency = 16;
1936 let NumMicroOps = 16;
1937 let ResourceCycles = [16];
1938}
Craig Topper5a69a002018-03-21 06:28:42 +00001939def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001940
Craig Topper8104f262018-04-02 05:33:28 +00001941def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00001942 let Latency = 17;
1943 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +00001944 let ResourceCycles = [2,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +00001945}
1946def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
1947
1948def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
1949 let Latency = 17;
1950 let NumMicroOps = 4;
1951 let ResourceCycles = [2,1,1];
1952}
Craig Topper5a69a002018-03-21 06:28:42 +00001953def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
1954 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001955
Craig Topper8104f262018-04-02 05:33:28 +00001956def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +00001957 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +00001958 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +00001959 let ResourceCycles = [1,1,7];
Gadi Haber323f2e12017-10-24 20:19:47 +00001960}
Craig Toppercdfcf8e2018-03-26 05:05:10 +00001961def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
1962 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001963
Gadi Haber323f2e12017-10-24 20:19:47 +00001964def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1965 let Latency = 18;
1966 let NumMicroOps = 8;
1967 let ResourceCycles = [1,1,1,5];
1968}
Craig Topper5a69a002018-03-21 06:28:42 +00001969def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +00001970def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001971
1972def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1973 let Latency = 18;
1974 let NumMicroOps = 11;
1975 let ResourceCycles = [2,1,1,3,1,3];
1976}
Craig Topper13a16502018-03-19 00:56:09 +00001977def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001978
Craig Topper8104f262018-04-02 05:33:28 +00001979def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00001980 let Latency = 19;
1981 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +00001982 let ResourceCycles = [1,1,8];
Gadi Haber323f2e12017-10-24 20:19:47 +00001983}
Simon Pilgrimc21deec2018-03-24 19:37:28 +00001984def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +00001985 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001986
Gadi Haber323f2e12017-10-24 20:19:47 +00001987def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1988 let Latency = 19;
1989 let NumMicroOps = 5;
1990 let ResourceCycles = [2,1,1,1];
1991}
Craig Topper5a69a002018-03-21 06:28:42 +00001992def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00001993
Gadi Haber323f2e12017-10-24 20:19:47 +00001994def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1995 let Latency = 20;
1996 let NumMicroOps = 1;
1997 let ResourceCycles = [1];
1998}
Craig Topper5a69a002018-03-21 06:28:42 +00001999def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2000 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +00002001 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002002
2003def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2004 let Latency = 20;
2005 let NumMicroOps = 5;
2006 let ResourceCycles = [2,1,1,1];
2007}
2008def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2009
2010def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2011 let Latency = 20;
2012 let NumMicroOps = 8;
2013 let ResourceCycles = [1,1,1,1,1,1,2];
2014}
Craig Topper5a69a002018-03-21 06:28:42 +00002015def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2016 "INSL",
2017 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002018
Craig Topper8104f262018-04-02 05:33:28 +00002019def BWWriteResGroup168 : SchedWriteRes<[BWPort0,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +00002020 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +00002021 let NumMicroOps = 1;
Craig Topper8104f262018-04-02 05:33:28 +00002022 let ResourceCycles = [1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +00002023}
Craig Topper8104f262018-04-02 05:33:28 +00002024def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr")>;
2025
2026def BWWriteResGroup168_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
2027 let Latency = 16;
2028 let NumMicroOps = 1;
2029 let ResourceCycles = [1,8];
2030}
2031def: InstRW<[BWWriteResGroup168_1], (instregex "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002032
2033def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2034 let Latency = 21;
2035 let NumMicroOps = 2;
2036 let ResourceCycles = [1,1];
2037}
Craig Topper5a69a002018-03-21 06:28:42 +00002038def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2039 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002040
Craig Topper8104f262018-04-02 05:33:28 +00002041def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00002042 let Latency = 21;
2043 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +00002044 let ResourceCycles = [2,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +00002045}
2046def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2047
2048def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2049 let Latency = 21;
2050 let NumMicroOps = 19;
2051 let ResourceCycles = [2,1,4,1,1,4,6];
2052}
2053def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2054
2055def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2056 let Latency = 22;
2057 let NumMicroOps = 18;
2058 let ResourceCycles = [1,1,16];
2059}
2060def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2061
Craig Topper8104f262018-04-02 05:33:28 +00002062def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00002063 let Latency = 23;
2064 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +00002065 let ResourceCycles = [2,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +00002066}
2067def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2068
Craig Topper8104f262018-04-02 05:33:28 +00002069def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00002070 let Latency = 23;
2071 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +00002072 let ResourceCycles = [2,1,1,10];
Gadi Haber323f2e12017-10-24 20:19:47 +00002073}
2074def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2075
Gadi Haber323f2e12017-10-24 20:19:47 +00002076def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2077 let Latency = 23;
2078 let NumMicroOps = 19;
2079 let ResourceCycles = [3,1,15];
2080}
Craig Topper391c6f92017-12-10 01:24:08 +00002081def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002082
2083def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2084 let Latency = 24;
2085 let NumMicroOps = 3;
2086 let ResourceCycles = [1,1,1];
2087}
Craig Topper5a69a002018-03-21 06:28:42 +00002088def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2089 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002090
Craig Topper8104f262018-04-02 05:33:28 +00002091def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +00002092 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +00002093 let NumMicroOps = 2;
Craig Topper8104f262018-04-02 05:33:28 +00002094 let ResourceCycles = [1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +00002095}
Craig Toppercdfcf8e2018-03-26 05:05:10 +00002096def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2097 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002098
2099def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2100 let Latency = 26;
2101 let NumMicroOps = 2;
2102 let ResourceCycles = [1,1];
2103}
Craig Topper5a69a002018-03-21 06:28:42 +00002104def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +00002105 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002106
Craig Topper8104f262018-04-02 05:33:28 +00002107def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00002108 let Latency = 27;
2109 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +00002110 let ResourceCycles = [2,1,1,14];
Gadi Haber323f2e12017-10-24 20:19:47 +00002111}
2112def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2113
2114def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2115 let Latency = 29;
2116 let NumMicroOps = 3;
2117 let ResourceCycles = [1,1,1];
2118}
Craig Topper5a69a002018-03-21 06:28:42 +00002119def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2120 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002121
Craig Topper8104f262018-04-02 05:33:28 +00002122def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
Gadi Haber323f2e12017-10-24 20:19:47 +00002123 let Latency = 29;
2124 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +00002125 let ResourceCycles = [2,1,1,16];
Gadi Haber323f2e12017-10-24 20:19:47 +00002126}
2127def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2128
2129def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2130 let Latency = 22;
2131 let NumMicroOps = 7;
2132 let ResourceCycles = [1,3,2,1];
2133}
Craig Topper17a31182017-12-16 18:35:29 +00002134def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002135
2136def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2137 let Latency = 23;
2138 let NumMicroOps = 9;
2139 let ResourceCycles = [1,3,4,1];
2140}
Craig Topper17a31182017-12-16 18:35:29 +00002141def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002142
2143def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2144 let Latency = 24;
2145 let NumMicroOps = 9;
2146 let ResourceCycles = [1,5,2,1];
2147}
Craig Topper17a31182017-12-16 18:35:29 +00002148def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002149
2150def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2151 let Latency = 25;
2152 let NumMicroOps = 7;
2153 let ResourceCycles = [1,3,2,1];
2154}
Craig Topper17a31182017-12-16 18:35:29 +00002155def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2156 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002157
2158def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2159 let Latency = 26;
2160 let NumMicroOps = 9;
2161 let ResourceCycles = [1,5,2,1];
2162}
Craig Topper17a31182017-12-16 18:35:29 +00002163def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002164
2165def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2166 let Latency = 26;
2167 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +00002168 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +00002169}
Craig Topper17a31182017-12-16 18:35:29 +00002170def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002171
2172def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2173 let Latency = 27;
2174 let NumMicroOps = 9;
2175 let ResourceCycles = [1,5,2,1];
2176}
Craig Topper17a31182017-12-16 18:35:29 +00002177def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002178
Gadi Haber323f2e12017-10-24 20:19:47 +00002179def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2180 let Latency = 29;
2181 let NumMicroOps = 27;
2182 let ResourceCycles = [1,5,1,1,19];
2183}
2184def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2185
2186def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2187 let Latency = 30;
2188 let NumMicroOps = 28;
2189 let ResourceCycles = [1,6,1,1,19];
2190}
Craig Topper2d451e72018-03-18 08:38:06 +00002191def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002192
2193def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2194 let Latency = 31;
2195 let NumMicroOps = 31;
2196 let ResourceCycles = [8,1,21,1];
2197}
2198def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2199
Craig Topper8104f262018-04-02 05:33:28 +00002200def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
2201 let Latency = 29;
Gadi Haber323f2e12017-10-24 20:19:47 +00002202 let NumMicroOps = 3;
Craig Topper8104f262018-04-02 05:33:28 +00002203 let ResourceCycles = [2,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +00002204}
2205def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2206
2207def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2208 let Latency = 34;
2209 let NumMicroOps = 8;
2210 let ResourceCycles = [2,2,2,1,1];
2211}
Craig Topper13a16502018-03-19 00:56:09 +00002212def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002213
2214def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2215 let Latency = 34;
2216 let NumMicroOps = 23;
2217 let ResourceCycles = [1,5,3,4,10];
2218}
Craig Topper5a69a002018-03-21 06:28:42 +00002219def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2220 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002221
2222def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2223 let Latency = 35;
2224 let NumMicroOps = 8;
2225 let ResourceCycles = [2,2,2,1,1];
2226}
Craig Topper13a16502018-03-19 00:56:09 +00002227def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002228
2229def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2230 let Latency = 35;
2231 let NumMicroOps = 23;
2232 let ResourceCycles = [1,5,2,1,4,10];
2233}
Craig Topper5a69a002018-03-21 06:28:42 +00002234def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2235 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002236
Craig Topper8104f262018-04-02 05:33:28 +00002237def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
2238 let Latency = 35;
Gadi Haber323f2e12017-10-24 20:19:47 +00002239 let NumMicroOps = 4;
Craig Topper8104f262018-04-02 05:33:28 +00002240 let ResourceCycles = [2,1,1,28];
Gadi Haber323f2e12017-10-24 20:19:47 +00002241}
2242def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2243
2244def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2245 let Latency = 42;
2246 let NumMicroOps = 22;
2247 let ResourceCycles = [2,20];
2248}
Craig Topper2d451e72018-03-18 08:38:06 +00002249def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002250
2251def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2252 let Latency = 60;
2253 let NumMicroOps = 64;
2254 let ResourceCycles = [2,2,8,1,10,2,39];
2255}
2256def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002257
2258def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2259 let Latency = 63;
2260 let NumMicroOps = 88;
2261 let ResourceCycles = [4,4,31,1,2,1,45];
2262}
Craig Topper2d451e72018-03-18 08:38:06 +00002263def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002264
2265def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2266 let Latency = 63;
2267 let NumMicroOps = 90;
2268 let ResourceCycles = [4,2,33,1,2,1,47];
2269}
Craig Topper2d451e72018-03-18 08:38:06 +00002270def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002271
2272def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2273 let Latency = 75;
2274 let NumMicroOps = 15;
2275 let ResourceCycles = [6,3,6];
2276}
Simon Pilgrim8cd01aa2018-04-23 16:10:50 +00002277def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002278
2279def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2280 let Latency = 80;
2281 let NumMicroOps = 32;
2282 let ResourceCycles = [7,7,3,3,1,11];
2283}
2284def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2285
2286def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2287 let Latency = 115;
2288 let NumMicroOps = 100;
2289 let ResourceCycles = [9,9,11,8,1,11,21,30];
2290}
2291def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +00002292
2293} // SchedModel
2294