Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 43 | #define MDSS_MDP_MAX_PREFILL_FETCH 25 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 44 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 45 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 46 | |
| 47 | static int mdp_rev; |
| 48 | |
| 49 | void mdp_set_revision(int rev) |
| 50 | { |
| 51 | mdp_rev = rev; |
| 52 | } |
| 53 | |
| 54 | int mdp_get_revision() |
| 55 | { |
| 56 | return mdp_rev; |
| 57 | } |
| 58 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 59 | uint32_t mdss_mdp_intf_offset() |
| 60 | { |
| 61 | uint32_t mdss_mdp_intf_off; |
| 62 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 63 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 64 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 65 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 66 | mdss_mdp_intf_off = 0x59100; |
| 67 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 68 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 69 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 70 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 71 | |
| 72 | return mdss_mdp_intf_off; |
| 73 | } |
| 74 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 75 | static uint32_t mdss_mdp_get_ppb_offset() |
| 76 | { |
| 77 | uint32_t mdss_mdp_ppb_off = 0; |
| 78 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 79 | |
| 80 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
| 81 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) |
| 82 | mdss_mdp_ppb_off = 0x1420; |
| 83 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 84 | mdss_mdp_ppb_off = 0x1334; |
| 85 | else |
| 86 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 87 | |
| 88 | return mdss_mdp_ppb_off; |
| 89 | } |
| 90 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 91 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 92 | { |
| 93 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 94 | |
| 95 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 96 | return 0xB0020; |
| 97 | else |
| 98 | return 0xC8020; |
| 99 | } |
| 100 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 101 | void mdp_clk_gating_ctrl(void) |
| 102 | { |
| 103 | writel(0x40000000, MDP_CLK_CTRL0); |
| 104 | udelay(20); |
| 105 | writel(0x40000040, MDP_CLK_CTRL0); |
| 106 | writel(0x40000000, MDP_CLK_CTRL1); |
| 107 | writel(0x00400000, MDP_CLK_CTRL3); |
| 108 | udelay(20); |
| 109 | writel(0x00404000, MDP_CLK_CTRL3); |
| 110 | writel(0x40000000, MDP_CLK_CTRL4); |
| 111 | } |
| 112 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 113 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 114 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 115 | { |
| 116 | switch (pinfo->pipe_type) { |
| 117 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 118 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 119 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 120 | break; |
| 121 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 122 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 123 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 124 | break; |
| 125 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 126 | default: |
| 127 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 128 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 129 | break; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 134 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 135 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 136 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 137 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 138 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 139 | switch (pinfo->pipe_type) { |
| 140 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 141 | if (dual_pipe_single_ctl) |
| 142 | *ctl0_reg_val = 0x220D8; |
| 143 | else |
| 144 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 145 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 146 | |
| 147 | if (pinfo->lcdc.dst_split) |
| 148 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 149 | break; |
| 150 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 151 | if (dual_pipe_single_ctl) |
| 152 | *ctl0_reg_val = 0x238C0; |
| 153 | else |
| 154 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 155 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 156 | if (pinfo->lcdc.dst_split) |
| 157 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 158 | break; |
| 159 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 160 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 161 | if (dual_pipe_single_ctl) |
| 162 | *ctl0_reg_val = 0x220C3; |
| 163 | else |
| 164 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 165 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 166 | if (pinfo->lcdc.dst_split) |
| 167 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 168 | break; |
| 169 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 170 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 171 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 172 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 173 | if (pinfo->dest == DISPLAY_2) { |
| 174 | *ctl0_reg_val |= BIT(31); |
| 175 | *ctl1_reg_val |= BIT(30); |
| 176 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 177 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 178 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 179 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 180 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 181 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
| 182 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 183 | if (pinfo->dest == DISPLAY_2) { |
| 184 | *ctl0_reg_val |= BIT(29); |
| 185 | *ctl1_reg_val |= BIT(30); |
| 186 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 187 | *ctl0_reg_val |= BIT(30); |
| 188 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 189 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 190 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 191 | } |
| 192 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 193 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 194 | *pinfo, uint32_t pipe_base) |
| 195 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 196 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 197 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 198 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 199 | uint32_t src_xy = 0, dst_xy = 0; |
| 200 | uint32_t height, width; |
| 201 | |
| 202 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 203 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 204 | |
| 205 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 206 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 207 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 208 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 209 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 210 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 211 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 212 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 213 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | stride = (fb->stride * fb->bpp/8); |
| 217 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 218 | if (fb_off == 0) { /* left */ |
| 219 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 220 | src_xy = dst_xy; |
| 221 | } else { /* right */ |
| 222 | dst_xy = (pinfo->border_top << 16); |
| 223 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 224 | } |
| 225 | |
| 226 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 227 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 228 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 229 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 230 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 231 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 232 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 233 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 234 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 235 | |
| 236 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 237 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 238 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 239 | |
| 240 | /* bit(0) is set if hflip is required. |
| 241 | * bit(1) is set if vflip is required. |
| 242 | */ |
| 243 | if (pinfo->orientation & 0x1) |
| 244 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 245 | if (pinfo->orientation & 0x2) |
| 246 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
| 247 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 248 | } |
| 249 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 250 | static void mdss_vbif_setup() |
| 251 | { |
| 252 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 253 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 254 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 255 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 256 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 257 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 258 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 259 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 260 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 261 | |
| 262 | /* |
| 263 | * Following configuration is needed because on some versions, |
| 264 | * recommended reset values are not stored. |
| 265 | */ |
| 266 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 267 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 268 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 269 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 270 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 271 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 272 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 273 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 274 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 275 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 276 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 277 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 278 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 279 | } |
| 280 | } |
| 281 | } |
| 282 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 283 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 284 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 285 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 286 | uint32_t i, j; |
| 287 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 288 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 289 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 290 | /* max 3 MMB per register */ |
| 291 | reg_val |= client_id << (((j++) % 3) * 8); |
| 292 | if ((j % 3) == 0) { |
| 293 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 294 | free_smp_offset); |
| 295 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 296 | free_smp_offset); |
| 297 | reg_val = 0; |
| 298 | free_smp_offset += 4; |
| 299 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 300 | } |
| 301 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 302 | if (j % 3) { |
| 303 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 304 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 305 | free_smp_offset += 4; |
| 306 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 307 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 308 | return free_smp_offset; |
| 309 | } |
| 310 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 311 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 312 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 313 | { |
| 314 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 315 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 316 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 317 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
| 318 | switch (pinfo->pipe_type) { |
| 319 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 320 | *left_sspp_client_id = 0x7; /* 7 */ |
| 321 | *right_sspp_client_id = 0x11; /* 17 */ |
| 322 | break; |
| 323 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 324 | *left_sspp_client_id = 0x4; /* 4 */ |
| 325 | *right_sspp_client_id = 0xD; /* 13 */ |
| 326 | break; |
| 327 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 328 | default: |
| 329 | *left_sspp_client_id = 0x1; /* 1 */ |
| 330 | *right_sspp_client_id = 0x4; /* 4 */ |
| 331 | break; |
| 332 | } |
| 333 | } else { |
| 334 | switch (pinfo->pipe_type) { |
| 335 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 336 | *left_sspp_client_id = 0x10; /* 16 */ |
| 337 | *right_sspp_client_id = 0x11; /* 17 */ |
| 338 | break; |
| 339 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 340 | *left_sspp_client_id = 0xA; /* 10 */ |
| 341 | *right_sspp_client_id = 0xD; /* 13 */ |
| 342 | break; |
| 343 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 344 | default: |
| 345 | *left_sspp_client_id = 0x1; /* 1 */ |
| 346 | *right_sspp_client_id = 0x4; /* 4 */ |
| 347 | break; |
| 348 | } |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 353 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 354 | { |
| 355 | switch (pinfo->pipe_type) { |
| 356 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 357 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 358 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 359 | break; |
| 360 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 361 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 362 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 363 | break; |
| 364 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 365 | default: |
| 366 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 367 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 368 | break; |
| 369 | } |
| 370 | } |
| 371 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 372 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 373 | uint32_t right_pipe) |
| 374 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 375 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 376 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 377 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 378 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 379 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 380 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 381 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 382 | /* 8Kb per SMP on 8916 */ |
| 383 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 384 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 385 | /* 10Kb per SMP on 8939 */ |
| 386 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 387 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 388 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 389 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 390 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 391 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 392 | fixed_smp_cnt = 2; |
| 393 | else |
| 394 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 395 | } |
| 396 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 397 | mdp_select_pipe_client_id(pinfo, |
| 398 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 399 | |
| 400 | /* Each pipe driving half the screen */ |
| 401 | if (pinfo->lcdc.dual_pipe) |
| 402 | xres /= 2; |
| 403 | |
| 404 | /* bpp = bytes per pixel of input image */ |
| 405 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 406 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 407 | |
| 408 | if (smp_cnt > 4) { |
| 409 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 410 | smp_cnt); |
| 411 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 412 | } |
| 413 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 414 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 415 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 416 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 417 | |
| 418 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 419 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 420 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 421 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 422 | } |
| 423 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 424 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 425 | fixed_smp_cnt, free_smp_offset); |
| 426 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 427 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 428 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 429 | } |
| 430 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 431 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 432 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 433 | uint32_t hsync_period, vsync_period; |
| 434 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 435 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 436 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 437 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 438 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 439 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 440 | |
| 441 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 442 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 443 | |
| 444 | lcdc = &(pinfo->lcdc); |
| 445 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 446 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 447 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 448 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 449 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 450 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 451 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 452 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 453 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 454 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 455 | } |
| 456 | } |
| 457 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 458 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 459 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 460 | writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 461 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 462 | } |
| 463 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 464 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 465 | pinfo->fbc.comp_ratio = 1; |
| 466 | |
| 467 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 468 | itp.yres = pinfo->yres; |
| 469 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 470 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 471 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 472 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 473 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 474 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 475 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 476 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 477 | |
| 478 | itp.border_clr = pinfo->lcdc.border_clr; |
| 479 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 480 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 481 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 482 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 483 | itp.width + itp.h_front_porch; |
| 484 | |
| 485 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 486 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 487 | |
| 488 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 489 | itp.hsync_pulse_width + |
| 490 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 491 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 492 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 493 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 494 | display_vstart = (itp.vsync_pulse_width + |
| 495 | itp.v_back_porch) |
| 496 | * hsync_period + itp.hsync_skew; |
| 497 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 498 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 499 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 500 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 501 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 502 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 503 | } |
| 504 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 505 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 506 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 507 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 508 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 509 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 510 | intf_base); |
| 511 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 512 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 513 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 514 | intf_base); |
| 515 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 516 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 517 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 518 | intf_base); |
| 519 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 520 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 521 | intf_base); |
| 522 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 523 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 524 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 525 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 526 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 527 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 528 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 529 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 530 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 531 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 532 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 533 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 534 | } |
| 535 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 536 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 537 | uint32_t intf_base) |
| 538 | { |
| 539 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 540 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 541 | uint32_t prefetch_avail, prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 542 | uint32_t adjust_xres = 0; |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 543 | uint32_t fetch_enable = BIT(31); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 544 | |
| 545 | struct lcdc_panel_info *lcdc = NULL; |
| 546 | |
| 547 | if (pinfo == NULL) |
| 548 | return; |
| 549 | |
| 550 | lcdc = &(pinfo->lcdc); |
| 551 | if (lcdc == NULL) |
| 552 | return; |
| 553 | |
| 554 | /* |
| 555 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 556 | * Programmable fetch is not needed if vertical back porch |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 557 | * plus vertical puls width is >= 25. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 558 | */ |
| 559 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 560 | (lcdc->v_back_porch + lcdc->v_pulse_width) >= |
| 561 | MDSS_MDP_MAX_PREFILL_FETCH) |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 562 | return; |
| 563 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 564 | adjust_xres = pinfo->xres; |
| 565 | if (pinfo->lcdc.split_display) |
| 566 | adjust_xres /= 2; |
| 567 | |
Jeevan Shriram | 4466729 | 2015-03-17 17:28:39 -0700 | [diff] [blame^] | 568 | if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) |
| 569 | adjust_xres /= pinfo->fbc.comp_ratio; |
| 570 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 571 | /* |
| 572 | * Fetch should always be outside the active lines. If the fetching |
| 573 | * is programmed within active region, hardware behavior is unknown. |
| 574 | */ |
| 575 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 576 | lcdc->v_front_porch; |
| 577 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 578 | lcdc->h_front_porch; |
| 579 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 580 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 581 | prefetch_avail = v_total - vfp_start; |
| 582 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - |
| 583 | lcdc->v_back_porch - |
| 584 | lcdc->v_pulse_width; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 585 | |
| 586 | /* |
| 587 | * In some cases, vertical front porch is too high. In such cases limit |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 588 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 589 | */ |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 590 | if (prefetch_avail > prefetch_needed) |
| 591 | prefetch_avail = prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 592 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 593 | fetch_start = (v_total - prefetch_avail) * h_total + 1; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 594 | |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 595 | if (pinfo->dfps.panel_dfps.enabled) |
| 596 | fetch_enable |= BIT(23); |
| 597 | |
| 598 | writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 599 | writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 600 | } |
| 601 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 602 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 603 | *pinfo) |
| 604 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 605 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 606 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 607 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 608 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 609 | width = fb->width; |
| 610 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 611 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 612 | width /= 2; |
| 613 | |
| 614 | /* write active region size*/ |
| 615 | mdp_rgb_size = (height << 16) | width; |
| 616 | |
| 617 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 618 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 619 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 620 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 621 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 622 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 623 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 624 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 625 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 626 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 627 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 628 | switch (pinfo->pipe_type) { |
| 629 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 630 | left_staging_level = 0x0000200; |
| 631 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 632 | break; |
| 633 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 634 | left_staging_level = 0x0040000; |
| 635 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 636 | break; |
| 637 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 638 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 639 | left_staging_level = 0x1; |
| 640 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 641 | break; |
| 642 | } |
| 643 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 644 | /* |
| 645 | * When ping-pong split is enabled and two pipes are used, |
| 646 | * both the pipes need to be staged on the same layer mixer. |
| 647 | */ |
| 648 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 649 | left_staging_level |= right_staging_level; |
| 650 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 651 | /* Base layer for layer mixer 0 */ |
| 652 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 653 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 654 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 655 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 656 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 657 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 658 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 659 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 660 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 661 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 662 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 663 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 664 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 665 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 666 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 667 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 668 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 669 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 670 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 671 | } |
| 672 | } |
| 673 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 674 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 675 | { |
| 676 | uint32_t mode = 0; |
| 677 | uint32_t budget_ctl = 0; |
| 678 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 679 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 680 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 681 | |
| 682 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 683 | |
| 684 | if (!pinfo->fbc.enabled) |
| 685 | return; |
| 686 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 687 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 688 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 689 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 690 | width = pinfo->xres; |
| 691 | if (enc_mode) |
| 692 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 693 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 694 | if (pinfo->mipi.dual_dsi) |
| 695 | width /= 2; |
| 696 | |
| 697 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 698 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 699 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 700 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 701 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 702 | |
| 703 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 704 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 705 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 706 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 707 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 708 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 709 | |
| 710 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 711 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 712 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 713 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 714 | ((fbc->lossy_mode_thd) << 8) | |
| 715 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 716 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 717 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 718 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 719 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 720 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 721 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 722 | |
| 723 | if (pinfo->mipi.dual_dsi) { |
| 724 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 725 | writel(budget_ctl, MDP_PP_1_BASE + |
| 726 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 727 | writel(lossy_mode, MDP_PP_1_BASE + |
| 728 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 729 | } |
| 730 | } |
| 731 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 732 | void mdss_qos_remapper_setup(void) |
| 733 | { |
| 734 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 735 | uint32_t map; |
| 736 | |
| 737 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 738 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 739 | MDSS_MDP_HW_REV_102)) |
| 740 | map = 0xE9; |
| 741 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 742 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 743 | map = 0xA5; |
| 744 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 745 | MDSS_MDP_HW_REV_106) || |
| 746 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 747 | MDSS_MDP_HW_REV_108)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 748 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 749 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 750 | MDSS_MDP_HW_REV_105) || |
| 751 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 752 | MDSS_MDP_HW_REV_109) || |
| 753 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 754 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 755 | map = 0xA4; |
| 756 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 757 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 758 | map = 0xFA; |
| 759 | else |
| 760 | return; |
| 761 | |
| 762 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 763 | } |
| 764 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 765 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 766 | { |
| 767 | uint32_t mask, reg_val, i; |
| 768 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 769 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 770 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 771 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 772 | |
| 773 | mdp_select_pipe_xin_id(pinfo, |
| 774 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 775 | |
| 776 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
| 777 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) { |
| 778 | vbif_qos[0] = 2; |
| 779 | vbif_qos[1] = 2; |
| 780 | vbif_qos[2] = 2; |
| 781 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 782 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 783 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
| 784 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 785 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 786 | vbif_qos[1] = 2; |
| 787 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 788 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 789 | } else { |
| 790 | return; |
| 791 | } |
| 792 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 793 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 794 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 795 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 796 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 797 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 798 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 799 | reg_val &= ~(mask); |
| 800 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 801 | |
| 802 | if (pinfo->lcdc.dual_pipe) { |
| 803 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 804 | reg_val &= ~(mask); |
| 805 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 806 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 807 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 808 | } |
| 809 | } |
| 810 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 811 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 812 | int is_main_ctl) |
| 813 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 814 | uint32_t mctl_intf_sel; |
| 815 | uint32_t sctl_intf_sel; |
| 816 | |
| 817 | if ((pinfo->dest == DISPLAY_2) || |
| 818 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 819 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 820 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 821 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 822 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 823 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 824 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 825 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 826 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 827 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 828 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 829 | } |
| 830 | |
| 831 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 832 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 833 | uint32_t *intf_base, uint32_t *sintf_base) |
| 834 | { |
| 835 | if (pinfo->dest == DISPLAY_2) { |
| 836 | *intf_sel = BIT(16); |
| 837 | *sintf_sel = BIT(8); |
| 838 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 839 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 840 | } else { |
| 841 | *intf_sel = BIT(8); |
| 842 | *sintf_sel = BIT(16); |
| 843 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 844 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 845 | } |
| 846 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 847 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 848 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 849 | } |
| 850 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 851 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 852 | struct fbcon_config *fb) |
| 853 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 854 | uint32_t intf_sel, sintf_sel; |
| 855 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 856 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 857 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 858 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 859 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 860 | |
| 861 | mdss_intf_tg_setup(pinfo, intf_base); |
| 862 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 863 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 864 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 865 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 866 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 867 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 868 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 869 | mdp_clk_gating_ctrl(); |
| 870 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 871 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 872 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 873 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 874 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 875 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 876 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 877 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 878 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 879 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 880 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 881 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 882 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 883 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 884 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 885 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 886 | |
| 887 | /* enable 3D mux for dual_pipe but single interface config */ |
| 888 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 889 | !pinfo->lcdc.split_display) |
| 890 | reg |= BIT(19) | BIT(20); |
| 891 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 892 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 893 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 894 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 895 | CTL_1 path should not be set since CTL_0 itself is going |
| 896 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 897 | if (pinfo->fbc.enabled) |
| 898 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 899 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 900 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 901 | if (!pinfo->lcdc.dst_split) { |
| 902 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 903 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 904 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 905 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 906 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 907 | |
| 908 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 909 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 910 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 911 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 912 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 913 | |
| 914 | return 0; |
| 915 | } |
| 916 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 917 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 918 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 919 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 920 | |
| 921 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 922 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 923 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 924 | mdp_clk_gating_ctrl(); |
| 925 | |
| 926 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 927 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 928 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 929 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 930 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 931 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 932 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 933 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 934 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 935 | |
| 936 | mdss_layer_mixer_setup(fb, pinfo); |
| 937 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 938 | if (pinfo->lcdc.dual_pipe) |
| 939 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 940 | else |
| 941 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 942 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 943 | writel(0x9, MDP_DISP_INTF_SEL); |
| 944 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 945 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 946 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 951 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 952 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 953 | uint32_t left_pipe, right_pipe; |
| 954 | |
| 955 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); |
| 956 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 957 | |
| 958 | mdp_clk_gating_ctrl(); |
| 959 | mdss_vbif_setup(); |
| 960 | |
| 961 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 962 | |
| 963 | mdss_qos_remapper_setup(); |
| 964 | |
| 965 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 966 | if (pinfo->lcdc.dual_pipe) |
| 967 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 968 | |
| 969 | mdss_layer_mixer_setup(fb, pinfo); |
| 970 | |
| 971 | if (pinfo->lcdc.dual_pipe) |
| 972 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 973 | else |
| 974 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 975 | |
| 976 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 977 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 978 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 979 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 980 | |
| 981 | return 0; |
| 982 | } |
| 983 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 984 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 985 | struct fbcon_config *fb) |
| 986 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 987 | uint32_t intf_sel, sintf_sel; |
| 988 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 989 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 990 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 991 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 992 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 993 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 994 | |
| 995 | if (pinfo == NULL) |
| 996 | return ERR_INVALID_ARGS; |
| 997 | |
| 998 | lcdc = &(pinfo->lcdc); |
| 999 | if (lcdc == NULL) |
| 1000 | return ERR_INVALID_ARGS; |
| 1001 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1002 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 1003 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1004 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1005 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1006 | if (pinfo->lcdc.dst_split) |
| 1007 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1008 | if (pinfo->lcdc.pipe_swap) |
| 1009 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 1010 | else |
| 1011 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1012 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1013 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1014 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1015 | } |
| 1016 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1017 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1018 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 1019 | writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 1020 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1021 | } |
| 1022 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1023 | mdp_clk_gating_ctrl(); |
| 1024 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1025 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1026 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1027 | |
| 1028 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1029 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1030 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1031 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1032 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1033 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1034 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1035 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1036 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1037 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1038 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1039 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1040 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1041 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1042 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1043 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1044 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 1045 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1046 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1047 | if (pinfo->fbc.enabled) |
| 1048 | mdss_fbc_cfg(pinfo); |
| 1049 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1050 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1051 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1052 | if (!pinfo->lcdc.dst_split) { |
| 1053 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1054 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1055 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1056 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1057 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1058 | return ret; |
| 1059 | } |
| 1060 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1061 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1062 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1063 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1064 | uint32_t timing_engine_en; |
| 1065 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1066 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1067 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1068 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1069 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1070 | |
| 1071 | if (pinfo->dest == DISPLAY_1) |
| 1072 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1073 | else |
| 1074 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1075 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1076 | |
| 1077 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1078 | } |
| 1079 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1080 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1081 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1082 | uint32_t timing_engine_en; |
| 1083 | |
| 1084 | if (pinfo->dest == DISPLAY_1) |
| 1085 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1086 | else |
| 1087 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1088 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1089 | if(!target_cont_splash_screen()) |
| 1090 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1091 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1092 | mdelay(60); |
| 1093 | /* Ping-Pong done Tear Check Read/Write */ |
| 1094 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1095 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1096 | } |
| 1097 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1098 | writel(0x00000000, MDP_INTR_EN); |
| 1099 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1100 | return NO_ERROR; |
| 1101 | } |
| 1102 | |
| 1103 | int mdp_dsi_cmd_off() |
| 1104 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1105 | if(!target_cont_splash_screen()) |
| 1106 | { |
| 1107 | /* Ping-Pong done Tear Check Read/Write */ |
| 1108 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1109 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1110 | } |
| 1111 | writel(0x00000000, MDP_INTR_EN); |
| 1112 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1113 | return NO_ERROR; |
| 1114 | } |
| 1115 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1116 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1117 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1118 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1119 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1120 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1121 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1122 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1123 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1124 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1125 | return NO_ERROR; |
| 1126 | } |
| 1127 | |
| 1128 | void mdp_disable(void) |
| 1129 | { |
| 1130 | |
| 1131 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1132 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1133 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1134 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1135 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1136 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1137 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1138 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1139 | return NO_ERROR; |
| 1140 | } |
| 1141 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1142 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1143 | { |
| 1144 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1145 | |
| 1146 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1147 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1148 | |
| 1149 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1150 | |
| 1151 | return NO_ERROR; |
| 1152 | } |
| 1153 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1154 | int mdp_edp_off(void) |
| 1155 | { |
| 1156 | if (!target_cont_splash_screen()) { |
| 1157 | |
| 1158 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1159 | mdss_mdp_intf_offset()); |
| 1160 | mdelay(60); |
| 1161 | /* Ping-Pong done Tear Check Read/Write */ |
| 1162 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1163 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1164 | writel(0x00000000, MDP_INTR_EN); |
| 1165 | } |
| 1166 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1167 | writel(0x00000000, MDP_INTR_EN); |
| 1168 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1169 | return NO_ERROR; |
| 1170 | } |