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gerrit-public.fairphone.software / kernel / msm-4.19 / 1aa09df0854efe16b7a80358a18f0a0bebafd246 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 8e80d979db2d696c1e283117a7c0cbabb10c6eef [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]14/ {
15 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]16 interrupt-parent = <&intc>;
Javier Martinez Canillasf8bf0162016-08-31 12:35:21 +0200[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
Dave Gerlach0f416d12016-09-14 16:26:53 -0700[diff] [blame]48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]106 wkup_m3: wkup_m3@100000 {
107 compatible = "ti,am3352-wkup-m3";
108 reg = <0x100000 0x4000>,
109 <0x180000 0x2000>;
110 reg-names = "umem", "dmem";
111 ti,hwmods = "wkup_m3";
112 ti,pm-firmware = "am335x-pm-firmware.elf";
113 };
114
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]115 prcm: prcm@200000 {
116 compatible = "ti,am3-prcm";
117 reg = <0x200000 0x4000>;
118
119 prcm_clocks: clocks {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123
124 prcm_clockdomains: clockdomains {
125 };
126 };
127
128 scm: scm@210000 {
129 compatible = "ti,am3-scm", "simple-bus";
130 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]131 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]132 #size-cells = <1>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]133 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]134 ranges = <0 0x210000 0x2000>;
135
136 am33xx_pinmux: pinmux@800 {
137 compatible = "pinctrl-single";
138 reg = <0x800 0x238>;
139 #address-cells = <1>;
140 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]141 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]142 pinctrl-single,register-width = <32>;
143 pinctrl-single,function-mask = <0x7f>;
144 };
145
146 scm_conf: scm_conf@0 {
Tony Lindgren1aa09df2017-01-05 11:10:40 -0800[diff] [blame^]147 compatible = "syscon", "simple-bus";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]148 reg = <0x0 0x800>;
149 #address-cells = <1>;
150 #size-cells = <1>;
Tony Lindgren1aa09df2017-01-05 11:10:40 -0800[diff] [blame^]151 ranges = <0 0 0x800>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]152
153 scm_clocks: clocks {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 };
157 };
158
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]159 wkup_m3_ipc: wkup_m3_ipc@1324 {
160 compatible = "ti,am3352-wkup-m3-ipc";
161 reg = <0x1324 0x24>;
162 interrupts = <78>;
163 ti,rproc = <&wkup_m3>;
164 mboxes = <&mailbox &mbox_wkupm3>;
165 };
166
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]167 edma_xbar: dma-router@f90 {
168 compatible = "ti,am335x-edma-crossbar";
169 reg = <0xf90 0x40>;
170 #dma-cells = <3>;
171 dma-requests = <32>;
172 dma-masters = <&edma>;
173 };
174
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]175 scm_clockdomains: clockdomains {
176 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]177 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]178 };
179
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]181 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 interrupt-controller;
183 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]184 reg = <0x48200000 0x1000>;
185 };
186
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]187 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]188 compatible = "ti,edma3-tpcc";
189 ti,hwmods = "tpcc";
190 reg = <0x49000000 0x10000>;
191 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]192 interrupts = <12 13 14>;
Robert P. J. Daya5206552016-05-24 17:20:28 -0400[diff] [blame]193 interrupt-names = "edma3_ccint", "edma3_mperr",
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]194 "edma3_ccerrint";
195 dma-requests = <64>;
196 #dma-cells = <2>;
197
198 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
199 <&edma_tptc2 0>;
200
201 ti,edma-memcpy-channels = <20 21>;
202 };
203
204 edma_tptc0: tptc@49800000 {
205 compatible = "ti,edma3-tptc";
206 ti,hwmods = "tptc0";
207 reg = <0x49800000 0x100000>;
208 interrupts = <112>;
209 interrupt-names = "edma3_tcerrint";
210 };
211
212 edma_tptc1: tptc@49900000 {
213 compatible = "ti,edma3-tptc";
214 ti,hwmods = "tptc1";
215 reg = <0x49900000 0x100000>;
216 interrupts = <113>;
217 interrupt-names = "edma3_tcerrint";
218 };
219
220 edma_tptc2: tptc@49a00000 {
221 compatible = "ti,edma3-tptc";
222 ti,hwmods = "tptc2";
223 reg = <0x49a00000 0x100000>;
224 interrupts = <114>;
225 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]226 };
227
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]228 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]229 compatible = "ti,omap4-gpio";
230 ti,hwmods = "gpio1";
231 gpio-controller;
232 #gpio-cells = <2>;
233 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]234 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]236 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]237 };
238
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]239 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]240 compatible = "ti,omap4-gpio";
241 ti,hwmods = "gpio2";
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]245 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]246 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]247 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 };
249
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]250 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]251 compatible = "ti,omap4-gpio";
252 ti,hwmods = "gpio3";
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]256 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]257 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]258 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]259 };
260
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]261 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]262 compatible = "ti,omap4-gpio";
263 ti,hwmods = "gpio4";
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]267 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]268 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]269 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]270 };
271
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]272 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]273 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]274 ti,hwmods = "uart1";
275 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]276 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]277 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]278 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]279 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]280 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]281 };
282
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]283 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]284 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]285 ti,hwmods = "uart2";
286 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]287 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]288 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]289 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]290 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]291 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]292 };
293
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]294 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]295 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]296 ti,hwmods = "uart3";
297 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]298 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]299 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]300 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]301 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]302 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]303 };
304
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]305 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]306 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]307 ti,hwmods = "uart4";
308 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]309 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]310 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]311 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]312 };
313
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]314 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]315 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]316 ti,hwmods = "uart5";
317 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]318 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]319 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]320 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]321 };
322
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]323 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]324 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]325 ti,hwmods = "uart6";
326 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]327 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]328 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]329 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]330 };
331
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]332 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]333 compatible = "ti,omap4-i2c";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]337 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]338 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]339 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]340 };
341
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]342 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]343 compatible = "ti,omap4-i2c";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]347 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]348 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]349 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]350 };
351
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]352 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]353 compatible = "ti,omap4-i2c";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]357 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]358 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]359 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]360 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]361
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]362 mmc1: mmc@48060000 {
363 compatible = "ti,omap4-hsmmc";
364 ti,hwmods = "mmc1";
365 ti,dual-volt;
366 ti,needs-special-reset;
367 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]368 dmas = <&edma_xbar 24 0 0
369 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]370 dma-names = "tx", "rx";
371 interrupts = <64>;
372 interrupt-parent = <&intc>;
373 reg = <0x48060000 0x1000>;
374 status = "disabled";
375 };
376
377 mmc2: mmc@481d8000 {
378 compatible = "ti,omap4-hsmmc";
379 ti,hwmods = "mmc2";
380 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]381 dmas = <&edma 2 0
382 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]383 dma-names = "tx", "rx";
384 interrupts = <28>;
385 interrupt-parent = <&intc>;
386 reg = <0x481d8000 0x1000>;
387 status = "disabled";
388 };
389
390 mmc3: mmc@47810000 {
391 compatible = "ti,omap4-hsmmc";
392 ti,hwmods = "mmc3";
393 ti,needs-special-reset;
394 interrupts = <29>;
395 interrupt-parent = <&intc>;
396 reg = <0x47810000 0x1000>;
397 status = "disabled";
398 };
399
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]400 hwspinlock: spinlock@480ca000 {
401 compatible = "ti,omap4-hwspinlock";
402 reg = <0x480ca000 0x1000>;
403 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]404 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]405 };
406
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]407 wdt2: wdt@44e35000 {
408 compatible = "ti,omap3-wdt";
409 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]410 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]411 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]412 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]413
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]414 dcan0: can@481cc000 {
415 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]416 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]417 reg = <0x481cc000 0x2000>;
418 clocks = <&dcan0_fck>;
419 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]420 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]421 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]422 status = "disabled";
423 };
424
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]425 dcan1: can@481d0000 {
426 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]427 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]428 reg = <0x481d0000 0x2000>;
429 clocks = <&dcan1_fck>;
430 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]431 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]432 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]433 status = "disabled";
434 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]435
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]436 mailbox: mailbox@480C8000 {
437 compatible = "ti,omap4-mailbox";
438 reg = <0x480C8000 0x200>;
439 interrupts = <77>;
440 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]441 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]442 ti,mbox-num-users = <4>;
443 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]444 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]445 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]446 ti,mbox-tx = <0 0 0>;
447 ti,mbox-rx = <0 0 3>;
448 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]449 };
450
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]451 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]452 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]453 reg = <0x44e31000 0x400>;
454 interrupts = <67>;
455 ti,hwmods = "timer1";
456 ti,timer-alwon;
457 };
458
459 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]460 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]461 reg = <0x48040000 0x400>;
462 interrupts = <68>;
463 ti,hwmods = "timer2";
464 };
465
466 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]467 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]468 reg = <0x48042000 0x400>;
469 interrupts = <69>;
470 ti,hwmods = "timer3";
471 };
472
473 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]474 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]475 reg = <0x48044000 0x400>;
476 interrupts = <92>;
477 ti,hwmods = "timer4";
478 ti,timer-pwm;
479 };
480
481 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]482 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]483 reg = <0x48046000 0x400>;
484 interrupts = <93>;
485 ti,hwmods = "timer5";
486 ti,timer-pwm;
487 };
488
489 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]490 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]491 reg = <0x48048000 0x400>;
492 interrupts = <94>;
493 ti,hwmods = "timer6";
494 ti,timer-pwm;
495 };
496
497 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]498 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]499 reg = <0x4804a000 0x400>;
500 interrupts = <95>;
501 ti,hwmods = "timer7";
502 ti,timer-pwm;
503 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]504
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]505 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]506 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]507 reg = <0x44e3e000 0x1000>;
508 interrupts = <75
509 76>;
510 ti,hwmods = "rtc";
Keerthy17fad5f2016-10-27 11:18:06 +0530[diff] [blame]511 clocks = <&clkdiv32k_ick>;
512 clock-names = "int-clk";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]513 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]514
515 spi0: spi@48030000 {
516 compatible = "ti,omap4-mcspi";
517 #address-cells = <1>;
518 #size-cells = <0>;
519 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]520 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]521 ti,spi-num-cs = <2>;
522 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]523 dmas = <&edma 16 0
524 &edma 17 0
525 &edma 18 0
526 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]527 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]528 status = "disabled";
529 };
530
531 spi1: spi@481a0000 {
532 compatible = "ti,omap4-mcspi";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]536 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]537 ti,spi-num-cs = <2>;
538 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]539 dmas = <&edma 42 0
540 &edma 43 0
541 &edma 44 0
542 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]543 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]544 status = "disabled";
545 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]546
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]547 usb: usb@47400000 {
548 compatible = "ti,am33xx-usb";
549 reg = <0x47400000 0x1000>;
550 ranges;
551 #address-cells = <1>;
552 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]553 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]554 status = "disabled";
555
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]556 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]557 compatible = "ti,am335x-usb-ctrl-module";
558 reg = <0x44e10620 0x10
559 0x44e10648 0x4>;
560 reg-names = "phy_ctrl", "wakeup";
561 status = "disabled";
562 };
563
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]564 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]565 compatible = "ti,am335x-usb-phy";
566 reg = <0x47401300 0x100>;
567 reg-names = "phy";
568 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]569 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]570 };
571
572 usb0: usb@47401000 {
573 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]574 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]575 reg = <0x47401400 0x400
576 0x47401000 0x200>;
577 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]578
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]579 interrupts = <18>;
580 interrupt-names = "mc";
581 dr_mode = "otg";
582 mentor,multipoint = <1>;
583 mentor,num-eps = <16>;
584 mentor,ram-bits = <12>;
585 mentor,power = <500>;
586 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]587
588 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
589 &cppi41dma 2 0 &cppi41dma 3 0
590 &cppi41dma 4 0 &cppi41dma 5 0
591 &cppi41dma 6 0 &cppi41dma 7 0
592 &cppi41dma 8 0 &cppi41dma 9 0
593 &cppi41dma 10 0 &cppi41dma 11 0
594 &cppi41dma 12 0 &cppi41dma 13 0
595 &cppi41dma 14 0 &cppi41dma 0 1
596 &cppi41dma 1 1 &cppi41dma 2 1
597 &cppi41dma 3 1 &cppi41dma 4 1
598 &cppi41dma 5 1 &cppi41dma 6 1
599 &cppi41dma 7 1 &cppi41dma 8 1
600 &cppi41dma 9 1 &cppi41dma 10 1
601 &cppi41dma 11 1 &cppi41dma 12 1
602 &cppi41dma 13 1 &cppi41dma 14 1>;
603 dma-names =
604 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
605 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
606 "rx14", "rx15",
607 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
608 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
609 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]610 };
611
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]612 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]613 compatible = "ti,am335x-usb-phy";
614 reg = <0x47401b00 0x100>;
615 reg-names = "phy";
616 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]617 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]618 };
619
620 usb1: usb@47401800 {
621 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]622 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]623 reg = <0x47401c00 0x400
624 0x47401800 0x200>;
625 reg-names = "mc", "control";
626 interrupts = <19>;
627 interrupt-names = "mc";
628 dr_mode = "otg";
629 mentor,multipoint = <1>;
630 mentor,num-eps = <16>;
631 mentor,ram-bits = <12>;
632 mentor,power = <500>;
633 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]634
635 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
636 &cppi41dma 17 0 &cppi41dma 18 0
637 &cppi41dma 19 0 &cppi41dma 20 0
638 &cppi41dma 21 0 &cppi41dma 22 0
639 &cppi41dma 23 0 &cppi41dma 24 0
640 &cppi41dma 25 0 &cppi41dma 26 0
641 &cppi41dma 27 0 &cppi41dma 28 0
642 &cppi41dma 29 0 &cppi41dma 15 1
643 &cppi41dma 16 1 &cppi41dma 17 1
644 &cppi41dma 18 1 &cppi41dma 19 1
645 &cppi41dma 20 1 &cppi41dma 21 1
646 &cppi41dma 22 1 &cppi41dma 23 1
647 &cppi41dma 24 1 &cppi41dma 25 1
648 &cppi41dma 26 1 &cppi41dma 27 1
649 &cppi41dma 28 1 &cppi41dma 29 1>;
650 dma-names =
651 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
652 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
653 "rx14", "rx15",
654 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
655 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
656 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]657 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]658
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]659 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]660 compatible = "ti,am3359-cppi41";
661 reg = <0x47400000 0x1000
662 0x47402000 0x1000
663 0x47403000 0x1000
664 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]665 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]666 interrupts = <17>;
667 interrupt-names = "glue";
668 #dma-cells = <2>;
669 #dma-channels = <30>;
670 #dma-requests = <256>;
671 status = "disabled";
672 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]673 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]674
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]675 epwmss0: epwmss@48300000 {
676 compatible = "ti,am33xx-pwmss";
677 reg = <0x48300000 0x10>;
678 ti,hwmods = "epwmss0";
679 #address-cells = <1>;
680 #size-cells = <1>;
681 status = "disabled";
682 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
683 0x48300180 0x48300180 0x80 /* EQEP */
684 0x48300200 0x48300200 0x80>; /* EHRPWM */
685
686 ecap0: ecap@48300100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]687 compatible = "ti,am3352-ecap",
688 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]689 #pwm-cells = <3>;
690 reg = <0x48300100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]691 clocks = <&l4ls_gclk>;
692 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]693 interrupts = <31>;
694 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]695 status = "disabled";
696 };
697
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]698 ehrpwm0: pwm@48300200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]699 compatible = "ti,am3352-ehrpwm",
700 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]701 #pwm-cells = <3>;
702 reg = <0x48300200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]703 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
704 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]705 status = "disabled";
706 };
707 };
708
709 epwmss1: epwmss@48302000 {
710 compatible = "ti,am33xx-pwmss";
711 reg = <0x48302000 0x10>;
712 ti,hwmods = "epwmss1";
713 #address-cells = <1>;
714 #size-cells = <1>;
715 status = "disabled";
716 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
717 0x48302180 0x48302180 0x80 /* EQEP */
718 0x48302200 0x48302200 0x80>; /* EHRPWM */
719
720 ecap1: ecap@48302100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]721 compatible = "ti,am3352-ecap",
722 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]723 #pwm-cells = <3>;
724 reg = <0x48302100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]725 clocks = <&l4ls_gclk>;
726 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]727 interrupts = <47>;
728 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]729 status = "disabled";
730 };
731
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]732 ehrpwm1: pwm@48302200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]733 compatible = "ti,am3352-ehrpwm",
734 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]735 #pwm-cells = <3>;
736 reg = <0x48302200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]737 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
738 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]739 status = "disabled";
740 };
741 };
742
743 epwmss2: epwmss@48304000 {
744 compatible = "ti,am33xx-pwmss";
745 reg = <0x48304000 0x10>;
746 ti,hwmods = "epwmss2";
747 #address-cells = <1>;
748 #size-cells = <1>;
749 status = "disabled";
750 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
751 0x48304180 0x48304180 0x80 /* EQEP */
752 0x48304200 0x48304200 0x80>; /* EHRPWM */
753
754 ecap2: ecap@48304100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]755 compatible = "ti,am3352-ecap",
756 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]757 #pwm-cells = <3>;
758 reg = <0x48304100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]759 clocks = <&l4ls_gclk>;
760 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]761 interrupts = <61>;
762 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]763 status = "disabled";
764 };
765
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]766 ehrpwm2: pwm@48304200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]767 compatible = "ti,am3352-ehrpwm",
768 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]769 #pwm-cells = <3>;
770 reg = <0x48304200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]771 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
772 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]773 status = "disabled";
774 };
775 };
776
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]777 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]778 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]779 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]780 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
781 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]782 cpdma_channels = <8>;
783 ale_entries = <1024>;
784 bd_ram_size = <0x2000>;
785 no_bd_ram = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]786 mac_control = <0x20>;
787 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]788 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]789 cpts_clock_mult = <0x80000000>;
790 cpts_clock_shift = <29>;
791 reg = <0x4a100000 0x800
792 0x4a101200 0x100>;
793 #address-cells = <1>;
794 #size-cells = <1>;
795 interrupt-parent = <&intc>;
796 /*
797 * c0_rx_thresh_pend
798 * c0_rx_pend
799 * c0_tx_pend
800 * c0_misc_pend
801 */
802 interrupts = <40 41 42 43>;
803 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]804 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]805 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]806
807 davinci_mdio: mdio@4a101000 {
Grygorii Strashko9efd1a62016-06-24 21:23:55 +0300[diff] [blame]808 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]809 #address-cells = <1>;
810 #size-cells = <0>;
811 ti,hwmods = "davinci_mdio";
812 bus_freq = <1000000>;
813 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]814 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]815 };
816
817 cpsw_emac0: slave@4a100200 {
818 /* Filled in by U-Boot */
819 mac-address = [ 00 00 00 00 00 00 ];
820 };
821
822 cpsw_emac1: slave@4a100300 {
823 /* Filled in by U-Boot */
824 mac-address = [ 00 00 00 00 00 00 ];
825 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]826
827 phy_sel: cpsw-phy-sel@44e10650 {
828 compatible = "ti,am3352-cpsw-phy-sel";
829 reg= <0x44e10650 0x4>;
830 reg-names = "gmii-sel";
831 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]832 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]833
834 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]835 compatible = "mmio-sram";
836 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]837 };
838
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]839 elm: elm@48080000 {
840 compatible = "ti,am3352-elm";
841 reg = <0x48080000 0x2000>;
842 interrupts = <4>;
843 ti,hwmods = "elm";
844 status = "disabled";
845 };
846
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]847 lcdc: lcdc@4830e000 {
848 compatible = "ti,am33xx-tilcdc";
849 reg = <0x4830e000 0x1000>;
850 interrupt-parent = <&intc>;
851 interrupts = <36>;
852 ti,hwmods = "lcdc";
853 status = "disabled";
854 };
855
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]856 tscadc: tscadc@44e0d000 {
857 compatible = "ti,am3359-tscadc";
858 reg = <0x44e0d000 0x1000>;
859 interrupt-parent = <&intc>;
860 interrupts = <16>;
861 ti,hwmods = "adc_tsc";
862 status = "disabled";
Mugunthan V N55e871f2016-10-05 14:34:42 +0530[diff] [blame]863 dmas = <&edma 53 0>, <&edma 57 0>;
864 dma-names = "fifo0", "fifo1";
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]865
866 tsc {
867 compatible = "ti,am3359-tsc";
868 };
869 am335x_adc: adc {
870 #io-channel-cells = <1>;
871 compatible = "ti,am3359-adc";
872 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]873 };
874
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]875 gpmc: gpmc@50000000 {
876 compatible = "ti,am3352-gpmc";
877 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]878 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]879 reg = <0x50000000 0x2000>;
880 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame]881 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]882 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]883 gpmc,num-cs = <7>;
884 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]885 #address-cells = <2>;
886 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]887 interrupt-controller;
888 #interrupt-cells = <2>;
Roger Quadros4eb4dd52016-04-07 13:25:32 +0300[diff] [blame]889 gpio-controller;
890 #gpio-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]891 status = "disabled";
892 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]893
894 sham: sham@53100000 {
895 compatible = "ti,omap4-sham";
896 ti,hwmods = "sham";
897 reg = <0x53100000 0x200>;
898 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]899 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]900 dma-names = "rx";
901 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]902
903 aes: aes@53500000 {
904 compatible = "ti,omap4-aes";
905 ti,hwmods = "aes";
906 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]907 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]908 dmas = <&edma 6 0>,
909 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]910 dma-names = "tx", "rx";
911 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]912
913 mcasp0: mcasp@48038000 {
914 compatible = "ti,am33xx-mcasp-audio";
915 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]916 reg = <0x48038000 0x2000>,
917 <0x46000000 0x400000>;
918 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]919 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]920 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]921 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]922 dmas = <&edma 8 2>,
923 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]924 dma-names = "tx", "rx";
925 };
926
927 mcasp1: mcasp@4803C000 {
928 compatible = "ti,am33xx-mcasp-audio";
929 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]930 reg = <0x4803C000 0x2000>,
931 <0x46400000 0x400000>;
932 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]933 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]934 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]935 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]936 dmas = <&edma 10 2>,
937 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]938 dma-names = "tx", "rx";
939 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]940
941 rng: rng@48310000 {
942 compatible = "ti,omap4-rng";
943 ti,hwmods = "rng";
944 reg = <0x48310000 0x2000>;
945 interrupts = <111>;
946 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]947 };
948};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]949
950/include/ "am33xx-clocks.dtsi"