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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050045#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090049#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51
52enum {
53 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090054 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020057 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090058 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090059 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090060 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090063 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090071 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090072 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090076 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090077 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +090080 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82 board_ahci_sb600 = 3,
83 board_ahci_mv = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -070084
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +090098 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +090099 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
Tejun Heo78cd52d2006-05-15 20:58:29 +0900143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900146 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900147 PORT_IRQ_UNK_FIS |
148 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
150 PORT_IRQ_TF_ERR |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155
156 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900162 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
166
Tejun Heo0be0aa92006-07-26 15:59:26 +0900167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400171
Tejun Heo417a1a62007-09-23 13:19:55 +0900172 /* hpriv->flags bits */
173 AHCI_HFLAG_NO_NCQ = (1 << 0),
174 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
175 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
176 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
177 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
178 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900179 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Tejun Heo417a1a62007-09-23 13:19:55 +0900180
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200181 /* ap->flags bits */
Tejun Heo417a1a62007-09-23 13:19:55 +0900182 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900183
184 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
185 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Tejun Heo854c73a2007-09-23 13:14:11 +0900186 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
Tejun Heo0c887582007-08-06 18:36:23 +0900187 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188};
189
190struct ahci_cmd_hdr {
191 u32 opts;
192 u32 status;
193 u32 tbl_addr;
194 u32 tbl_addr_hi;
195 u32 reserved[4];
196};
197
198struct ahci_sg {
199 u32 addr;
200 u32 addr_hi;
201 u32 reserved;
202 u32 flags_size;
203};
204
205struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900206 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900207 u32 cap; /* cap to use */
208 u32 port_map; /* port map to use */
209 u32 saved_cap; /* saved initial cap */
210 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211};
212
213struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900214 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 struct ahci_cmd_hdr *cmd_slot;
216 dma_addr_t cmd_slot_dma;
217 void *cmd_tbl;
218 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 void *rx_fis;
220 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900221 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900222 unsigned int ncq_saw_d2h:1;
223 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900224 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700225 u32 intr_mask; /* interrupts to enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226};
227
Tejun Heoda3dbb12007-07-16 14:29:40 +0900228static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
229static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900231static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233static int ahci_port_start(struct ata_port *ap);
234static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
236static void ahci_qc_prep(struct ata_queued_cmd *qc);
237static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900238static void ahci_freeze(struct ata_port *ap);
239static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900240static void ahci_pmp_attach(struct ata_port *ap);
241static void ahci_pmp_detach(struct ata_port *ap);
242static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
243static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900244static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900245static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900246static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400247static int ahci_port_resume(struct ata_port *ap);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400248static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
249static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
250 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900251#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900252static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900253static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
254static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900255#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
Jeff Garzik193515d2005-11-07 00:59:37 -0500257static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 .module = THIS_MODULE,
259 .name = DRV_NAME,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900262 .change_queue_depth = ata_scsi_change_queue_depth,
263 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 .this_id = ATA_SHT_THIS_ID,
265 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
267 .emulated = ATA_SHT_EMULATED,
268 .use_clustering = AHCI_USE_CLUSTERING,
269 .proc_name = DRV_NAME,
270 .dma_boundary = AHCI_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900272 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274};
275
Jeff Garzik057ace52005-10-22 14:27:05 -0400276static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 .check_status = ahci_check_status,
278 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 .dev_select = ata_noop_dev_select,
280
281 .tf_read = ahci_tf_read,
282
Tejun Heo7d50b602007-09-23 13:19:54 +0900283 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 .qc_prep = ahci_qc_prep,
285 .qc_issue = ahci_qc_issue,
286
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 .irq_clear = ahci_irq_clear,
288
289 .scr_read = ahci_scr_read,
290 .scr_write = ahci_scr_write,
291
Tejun Heo78cd52d2006-05-15 20:58:29 +0900292 .freeze = ahci_freeze,
293 .thaw = ahci_thaw,
294
295 .error_handler = ahci_error_handler,
296 .post_internal_cmd = ahci_post_internal_cmd,
297
Tejun Heo7d50b602007-09-23 13:19:54 +0900298 .pmp_attach = ahci_pmp_attach,
299 .pmp_detach = ahci_pmp_detach,
300 .pmp_read = ahci_pmp_read,
301 .pmp_write = ahci_pmp_write,
302
Tejun Heo438ac6d2007-03-02 17:31:26 +0900303#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900304 .port_suspend = ahci_port_suspend,
305 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900306#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900307
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 .port_start = ahci_port_start,
309 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310};
311
Tejun Heoad616ff2006-11-01 18:00:24 +0900312static const struct ata_port_operations ahci_vt8251_ops = {
Tejun Heoad616ff2006-11-01 18:00:24 +0900313 .check_status = ahci_check_status,
314 .check_altstatus = ahci_check_status,
315 .dev_select = ata_noop_dev_select,
316
317 .tf_read = ahci_tf_read,
318
Tejun Heo7d50b602007-09-23 13:19:54 +0900319 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Tejun Heoad616ff2006-11-01 18:00:24 +0900320 .qc_prep = ahci_qc_prep,
321 .qc_issue = ahci_qc_issue,
322
Tejun Heoad616ff2006-11-01 18:00:24 +0900323 .irq_clear = ahci_irq_clear,
324
325 .scr_read = ahci_scr_read,
326 .scr_write = ahci_scr_write,
327
328 .freeze = ahci_freeze,
329 .thaw = ahci_thaw,
330
331 .error_handler = ahci_vt8251_error_handler,
332 .post_internal_cmd = ahci_post_internal_cmd,
333
Tejun Heo7d50b602007-09-23 13:19:54 +0900334 .pmp_attach = ahci_pmp_attach,
335 .pmp_detach = ahci_pmp_detach,
336 .pmp_read = ahci_pmp_read,
337 .pmp_write = ahci_pmp_write,
338
Tejun Heo438ac6d2007-03-02 17:31:26 +0900339#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900340 .port_suspend = ahci_port_suspend,
341 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900342#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900343
344 .port_start = ahci_port_start,
345 .port_stop = ahci_port_stop,
346};
347
Tejun Heo417a1a62007-09-23 13:19:55 +0900348#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
349
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100350static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 /* board_ahci */
352 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900353 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900354 .link_flags = AHCI_LFLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400355 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400356 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 .port_ops = &ahci_ops,
358 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200359 /* board_ahci_vt8251 */
360 {
Tejun Heo6949b912007-09-23 13:19:55 +0900361 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900362 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900363 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200364 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400365 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900366 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200367 },
Tejun Heo41669552006-11-29 11:33:14 +0900368 /* board_ahci_ign_iferr */
369 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900370 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
371 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900372 .link_flags = AHCI_LFLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900373 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400374 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900375 .port_ops = &ahci_ops,
376 },
Conke Hu55a61602007-03-27 18:33:05 +0800377 /* board_ahci_sb600 */
378 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900379 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo6949b912007-09-23 13:19:55 +0900380 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900381 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900382 .link_flags = AHCI_LFLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800383 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400384 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800385 .port_ops = &ahci_ops,
386 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400387 /* board_ahci_mv */
388 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900389 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
390 AHCI_HFLAG_MV_PATA),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400391 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900392 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Tejun Heo0c887582007-08-06 18:36:23 +0900393 .link_flags = AHCI_LFLAG_COMMON,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400394 .pio_mask = 0x1f, /* pio0-4 */
395 .udma_mask = ATA_UDMA6,
396 .port_ops = &ahci_ops,
397 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398};
399
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500400static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400401 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400402 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
403 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
404 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
405 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
406 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900407 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400408 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
409 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
410 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
411 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900412 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
413 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
414 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
415 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
416 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
417 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
418 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
420 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
422 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
423 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
425 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
426 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
427 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
428 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400429 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
430 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400431
Tejun Heoe34bb372007-02-26 20:24:03 +0900432 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
433 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
434 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400435
436 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800437 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
henry suc69c0892007-09-20 16:07:33 -0400438 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
441 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
443 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400444
445 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400446 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900447 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400448
449 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400450 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500454 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500462 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800470 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
Peer Chen71008192007-09-24 10:16:25 +0800494 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400502
Jeff Garzik95916ed2006-07-29 04:10:14 -0400503 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400507
Jeff Garzikcd70c262007-07-08 02:29:42 -0400508 /* Marvell */
509 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
510
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500511 /* Generic, PCI class code for AHCI */
512 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500513 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500514
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 { } /* terminate list */
516};
517
518
519static struct pci_driver ahci_pci_driver = {
520 .name = DRV_NAME,
521 .id_table = ahci_pci_tbl,
522 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900523 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900524#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900525 .suspend = ahci_pci_device_suspend,
526 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900527#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528};
529
530
Tejun Heo98fa4b62006-11-02 12:17:23 +0900531static inline int ahci_nr_ports(u32 cap)
532{
533 return (cap & 0x1f) + 1;
534}
535
Jeff Garzikdab632e2007-05-28 08:33:01 -0400536static inline void __iomem *__ahci_port_base(struct ata_host *host,
537 unsigned int port_no)
538{
539 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
540
541 return mmio + 0x100 + (port_no * 0x80);
542}
543
Tejun Heo4447d352007-04-17 23:44:08 +0900544static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400546 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547}
548
Tejun Heod447df12007-03-18 22:15:33 +0900549/**
550 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900551 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900552 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900553 *
554 * Some registers containing configuration info might be setup by
555 * BIOS and might be cleared on reset. This function saves the
556 * initial values of those registers into @hpriv such that they
557 * can be restored after controller reset.
558 *
559 * If inconsistent, config values are fixed up by this function.
560 *
561 * LOCKING:
562 * None.
563 */
Tejun Heo4447d352007-04-17 23:44:08 +0900564static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900565 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900566{
Tejun Heo4447d352007-04-17 23:44:08 +0900567 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900568 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900569 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900570
571 /* Values prefixed with saved_ are written back to host after
572 * reset. Values without are used for driver operation.
573 */
574 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
575 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
576
Tejun Heo274c1fd2007-07-16 14:29:40 +0900577 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900578 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200579 dev_printk(KERN_INFO, &pdev->dev,
580 "controller can't do 64bit DMA, forcing 32bit\n");
581 cap &= ~HOST_CAP_64;
582 }
583
Tejun Heo417a1a62007-09-23 13:19:55 +0900584 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900585 dev_printk(KERN_INFO, &pdev->dev,
586 "controller can't do NCQ, turning off CAP_NCQ\n");
587 cap &= ~HOST_CAP_NCQ;
588 }
589
Tejun Heo6949b912007-09-23 13:19:55 +0900590 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
591 dev_printk(KERN_INFO, &pdev->dev,
592 "controller can't do PMP, turning off CAP_PMP\n");
593 cap &= ~HOST_CAP_PMP;
594 }
595
Jeff Garzikcd70c262007-07-08 02:29:42 -0400596 /*
597 * Temporary Marvell 6145 hack: PATA port presence
598 * is asserted through the standard AHCI port
599 * presence register, as bit 4 (counting from 0)
600 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900601 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400602 dev_printk(KERN_ERR, &pdev->dev,
603 "MV_AHCI HACK: port_map %x -> %x\n",
604 hpriv->port_map,
605 hpriv->port_map & 0xf);
606
607 port_map &= 0xf;
608 }
609
Tejun Heo17199b12007-03-18 22:26:53 +0900610 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900611 if (port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900612 u32 tmp_port_map = port_map;
613 int n_ports = ahci_nr_ports(cap);
614
615 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
616 if (tmp_port_map & (1 << i)) {
617 n_ports--;
618 tmp_port_map &= ~(1 << i);
619 }
620 }
621
Tejun Heo7a234af2007-09-03 12:44:57 +0900622 /* If n_ports and port_map are inconsistent, whine and
623 * clear port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900624 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900625 if (n_ports || tmp_port_map) {
Tejun Heo4447d352007-04-17 23:44:08 +0900626 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo17199b12007-03-18 22:26:53 +0900627 "nr_ports (%u) and implemented port map "
Tejun Heo7a234af2007-09-03 12:44:57 +0900628 "(0x%x) don't match, using nr_ports\n",
Tejun Heo17199b12007-03-18 22:26:53 +0900629 ahci_nr_ports(cap), port_map);
Tejun Heo7a234af2007-09-03 12:44:57 +0900630 port_map = 0;
631 }
632 }
633
634 /* fabricate port_map from cap.nr_ports */
635 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900636 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900637 dev_printk(KERN_WARNING, &pdev->dev,
638 "forcing PORTS_IMPL to 0x%x\n", port_map);
639
640 /* write the fixed up value to the PI register */
641 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900642 }
643
Tejun Heod447df12007-03-18 22:15:33 +0900644 /* record values to use during operation */
645 hpriv->cap = cap;
646 hpriv->port_map = port_map;
647}
648
649/**
650 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900651 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900652 *
653 * Restore initial config stored by ahci_save_initial_config().
654 *
655 * LOCKING:
656 * None.
657 */
Tejun Heo4447d352007-04-17 23:44:08 +0900658static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900659{
Tejun Heo4447d352007-04-17 23:44:08 +0900660 struct ahci_host_priv *hpriv = host->private_data;
661 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
662
Tejun Heod447df12007-03-18 22:15:33 +0900663 writel(hpriv->saved_cap, mmio + HOST_CAP);
664 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
665 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
666}
667
Tejun Heo203ef6c2007-07-16 14:29:40 +0900668static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900670 static const int offset[] = {
671 [SCR_STATUS] = PORT_SCR_STAT,
672 [SCR_CONTROL] = PORT_SCR_CTL,
673 [SCR_ERROR] = PORT_SCR_ERR,
674 [SCR_ACTIVE] = PORT_SCR_ACT,
675 [SCR_NOTIFICATION] = PORT_SCR_NTF,
676 };
677 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
Tejun Heo203ef6c2007-07-16 14:29:40 +0900679 if (sc_reg < ARRAY_SIZE(offset) &&
680 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
681 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900682 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683}
684
Tejun Heo203ef6c2007-07-16 14:29:40 +0900685static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900687 void __iomem *port_mmio = ahci_port_base(ap);
688 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689
Tejun Heo203ef6c2007-07-16 14:29:40 +0900690 if (offset) {
691 *val = readl(port_mmio + offset);
692 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900694 return -EINVAL;
695}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696
Tejun Heo203ef6c2007-07-16 14:29:40 +0900697static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
698{
699 void __iomem *port_mmio = ahci_port_base(ap);
700 int offset = ahci_scr_offset(ap, sc_reg);
701
702 if (offset) {
703 writel(val, port_mmio + offset);
704 return 0;
705 }
706 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707}
708
Tejun Heo4447d352007-04-17 23:44:08 +0900709static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900710{
Tejun Heo4447d352007-04-17 23:44:08 +0900711 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900712 u32 tmp;
713
Tejun Heod8fcd112006-07-26 15:59:25 +0900714 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900715 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900716 tmp |= PORT_CMD_START;
717 writel(tmp, port_mmio + PORT_CMD);
718 readl(port_mmio + PORT_CMD); /* flush */
719}
720
Tejun Heo4447d352007-04-17 23:44:08 +0900721static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900722{
Tejun Heo4447d352007-04-17 23:44:08 +0900723 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900724 u32 tmp;
725
726 tmp = readl(port_mmio + PORT_CMD);
727
Tejun Heod8fcd112006-07-26 15:59:25 +0900728 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900729 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
730 return 0;
731
Tejun Heod8fcd112006-07-26 15:59:25 +0900732 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900733 tmp &= ~PORT_CMD_START;
734 writel(tmp, port_mmio + PORT_CMD);
735
Tejun Heod8fcd112006-07-26 15:59:25 +0900736 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900737 tmp = ata_wait_register(port_mmio + PORT_CMD,
738 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900739 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900740 return -EIO;
741
742 return 0;
743}
744
Tejun Heo4447d352007-04-17 23:44:08 +0900745static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900746{
Tejun Heo4447d352007-04-17 23:44:08 +0900747 void __iomem *port_mmio = ahci_port_base(ap);
748 struct ahci_host_priv *hpriv = ap->host->private_data;
749 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900750 u32 tmp;
751
752 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900753 if (hpriv->cap & HOST_CAP_64)
754 writel((pp->cmd_slot_dma >> 16) >> 16,
755 port_mmio + PORT_LST_ADDR_HI);
756 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900757
Tejun Heo4447d352007-04-17 23:44:08 +0900758 if (hpriv->cap & HOST_CAP_64)
759 writel((pp->rx_fis_dma >> 16) >> 16,
760 port_mmio + PORT_FIS_ADDR_HI);
761 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900762
763 /* enable FIS reception */
764 tmp = readl(port_mmio + PORT_CMD);
765 tmp |= PORT_CMD_FIS_RX;
766 writel(tmp, port_mmio + PORT_CMD);
767
768 /* flush */
769 readl(port_mmio + PORT_CMD);
770}
771
Tejun Heo4447d352007-04-17 23:44:08 +0900772static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900773{
Tejun Heo4447d352007-04-17 23:44:08 +0900774 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900775 u32 tmp;
776
777 /* disable FIS reception */
778 tmp = readl(port_mmio + PORT_CMD);
779 tmp &= ~PORT_CMD_FIS_RX;
780 writel(tmp, port_mmio + PORT_CMD);
781
782 /* wait for completion, spec says 500ms, give it 1000 */
783 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
784 PORT_CMD_FIS_ON, 10, 1000);
785 if (tmp & PORT_CMD_FIS_ON)
786 return -EBUSY;
787
788 return 0;
789}
790
Tejun Heo4447d352007-04-17 23:44:08 +0900791static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900792{
Tejun Heo4447d352007-04-17 23:44:08 +0900793 struct ahci_host_priv *hpriv = ap->host->private_data;
794 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900795 u32 cmd;
796
797 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
798
799 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900800 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900801 cmd |= PORT_CMD_SPIN_UP;
802 writel(cmd, port_mmio + PORT_CMD);
803 }
804
805 /* wake up link */
806 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
807}
808
Tejun Heo438ac6d2007-03-02 17:31:26 +0900809#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +0900810static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900811{
Tejun Heo4447d352007-04-17 23:44:08 +0900812 struct ahci_host_priv *hpriv = ap->host->private_data;
813 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900814 u32 cmd, scontrol;
815
Tejun Heo4447d352007-04-17 23:44:08 +0900816 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +0900817 return;
818
819 /* put device into listen mode, first set PxSCTL.DET to 0 */
820 scontrol = readl(port_mmio + PORT_SCR_CTL);
821 scontrol &= ~0xf;
822 writel(scontrol, port_mmio + PORT_SCR_CTL);
823
824 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900825 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +0900826 cmd &= ~PORT_CMD_SPIN_UP;
827 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900828}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900829#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +0900830
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400831static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900832{
Tejun Heo0be0aa92006-07-26 15:59:26 +0900833 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900834 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900835
836 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900837 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900838}
839
Tejun Heo4447d352007-04-17 23:44:08 +0900840static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900841{
842 int rc;
843
844 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900845 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900846 if (rc) {
847 *emsg = "failed to stop engine";
848 return rc;
849 }
850
851 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900852 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900853 if (rc) {
854 *emsg = "failed stop FIS RX";
855 return rc;
856 }
857
Tejun Heo0be0aa92006-07-26 15:59:26 +0900858 return 0;
859}
860
Tejun Heo4447d352007-04-17 23:44:08 +0900861static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900862{
Tejun Heo4447d352007-04-17 23:44:08 +0900863 struct pci_dev *pdev = to_pci_dev(host->dev);
864 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900865 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +0900866
Jeff Garzik3cc3eb12007-09-26 00:02:41 -0400867 /* we must be in AHCI mode, before using anything
868 * AHCI-specific, such as HOST_RESET.
869 */
Tejun Heod91542c2006-07-26 15:59:26 +0900870 tmp = readl(mmio + HOST_CTL);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -0400871 if (!(tmp & HOST_AHCI_EN))
872 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
873
874 /* global controller reset */
Tejun Heod91542c2006-07-26 15:59:26 +0900875 if ((tmp & HOST_RESET) == 0) {
876 writel(tmp | HOST_RESET, mmio + HOST_CTL);
877 readl(mmio + HOST_CTL); /* flush */
878 }
879
880 /* reset must complete within 1 second, or
881 * the hardware should be considered fried.
882 */
883 ssleep(1);
884
885 tmp = readl(mmio + HOST_CTL);
886 if (tmp & HOST_RESET) {
Tejun Heo4447d352007-04-17 23:44:08 +0900887 dev_printk(KERN_ERR, host->dev,
Tejun Heod91542c2006-07-26 15:59:26 +0900888 "controller reset failed (0x%x)\n", tmp);
889 return -EIO;
890 }
891
Tejun Heo98fa4b62006-11-02 12:17:23 +0900892 /* turn on AHCI mode */
Tejun Heod91542c2006-07-26 15:59:26 +0900893 writel(HOST_AHCI_EN, mmio + HOST_CTL);
894 (void) readl(mmio + HOST_CTL); /* flush */
Tejun Heo98fa4b62006-11-02 12:17:23 +0900895
Tejun Heod447df12007-03-18 22:15:33 +0900896 /* some registers might be cleared on reset. restore initial values */
Tejun Heo4447d352007-04-17 23:44:08 +0900897 ahci_restore_initial_config(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900898
899 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
900 u16 tmp16;
901
902 /* configure PCS */
903 pci_read_config_word(pdev, 0x92, &tmp16);
904 tmp16 |= 0xf;
905 pci_write_config_word(pdev, 0x92, tmp16);
906 }
907
908 return 0;
909}
910
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400911static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
912 int port_no, void __iomem *mmio,
913 void __iomem *port_mmio)
914{
915 const char *emsg = NULL;
916 int rc;
917 u32 tmp;
918
919 /* make sure port is not active */
920 rc = ahci_deinit_port(ap, &emsg);
921 if (rc)
922 dev_printk(KERN_WARNING, &pdev->dev,
923 "%s (%d)\n", emsg, rc);
924
925 /* clear SError */
926 tmp = readl(port_mmio + PORT_SCR_ERR);
927 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
928 writel(tmp, port_mmio + PORT_SCR_ERR);
929
930 /* clear port IRQ */
931 tmp = readl(port_mmio + PORT_IRQ_STAT);
932 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
933 if (tmp)
934 writel(tmp, port_mmio + PORT_IRQ_STAT);
935
936 writel(1 << port_no, mmio + HOST_IRQ_STAT);
937}
938
Tejun Heo4447d352007-04-17 23:44:08 +0900939static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900940{
Tejun Heo417a1a62007-09-23 13:19:55 +0900941 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +0900942 struct pci_dev *pdev = to_pci_dev(host->dev);
943 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400944 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400945 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +0900946 u32 tmp;
947
Tejun Heo417a1a62007-09-23 13:19:55 +0900948 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400949 port_mmio = __ahci_port_base(host, 4);
950
951 writel(0, port_mmio + PORT_IRQ_MASK);
952
953 /* clear port IRQ */
954 tmp = readl(port_mmio + PORT_IRQ_STAT);
955 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
956 if (tmp)
957 writel(tmp, port_mmio + PORT_IRQ_STAT);
958 }
959
Tejun Heo4447d352007-04-17 23:44:08 +0900960 for (i = 0; i < host->n_ports; i++) {
961 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +0900962
Jeff Garzikcd70c262007-07-08 02:29:42 -0400963 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +0900964 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +0900965 continue;
Tejun Heod91542c2006-07-26 15:59:26 +0900966
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400967 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +0900968 }
969
970 tmp = readl(mmio + HOST_CTL);
971 VPRINTK("HOST_CTL 0x%x\n", tmp);
972 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
973 tmp = readl(mmio + HOST_CTL);
974 VPRINTK("HOST_CTL 0x%x\n", tmp);
975}
976
Tejun Heo422b7592005-12-19 22:37:17 +0900977static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978{
Tejun Heo4447d352007-04-17 23:44:08 +0900979 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +0900981 u32 tmp;
982
983 tmp = readl(port_mmio + PORT_SIG);
984 tf.lbah = (tmp >> 24) & 0xff;
985 tf.lbam = (tmp >> 16) & 0xff;
986 tf.lbal = (tmp >> 8) & 0xff;
987 tf.nsect = (tmp) & 0xff;
988
989 return ata_dev_classify(&tf);
990}
991
Tejun Heo12fad3f2006-05-15 21:03:55 +0900992static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
993 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +0900994{
Tejun Heo12fad3f2006-05-15 21:03:55 +0900995 dma_addr_t cmd_tbl_dma;
996
997 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
998
999 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1000 pp->cmd_slot[tag].status = 0;
1001 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1002 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001003}
1004
Tejun Heod2e75df2007-07-16 14:29:39 +09001005static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001006{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001007 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -04001008 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001009 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001010 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001011
Tejun Heod2e75df2007-07-16 14:29:39 +09001012 /* do we need to kick the port? */
1013 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1014 if (!busy && !force_restart)
1015 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001016
Tejun Heod2e75df2007-07-16 14:29:39 +09001017 /* stop engine */
1018 rc = ahci_stop_engine(ap);
1019 if (rc)
1020 goto out_restart;
1021
1022 /* need to do CLO? */
1023 if (!busy) {
1024 rc = 0;
1025 goto out_restart;
1026 }
1027
1028 if (!(hpriv->cap & HOST_CAP_CLO)) {
1029 rc = -EOPNOTSUPP;
1030 goto out_restart;
1031 }
1032
1033 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001034 tmp = readl(port_mmio + PORT_CMD);
1035 tmp |= PORT_CMD_CLO;
1036 writel(tmp, port_mmio + PORT_CMD);
1037
Tejun Heod2e75df2007-07-16 14:29:39 +09001038 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001039 tmp = ata_wait_register(port_mmio + PORT_CMD,
1040 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1041 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001042 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001043
Tejun Heod2e75df2007-07-16 14:29:39 +09001044 /* restart engine */
1045 out_restart:
1046 ahci_start_engine(ap);
1047 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001048}
1049
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001050static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1051 struct ata_taskfile *tf, int is_cmd, u16 flags,
1052 unsigned long timeout_msec)
1053{
1054 const u32 cmd_fis_len = 5; /* five dwords */
1055 struct ahci_port_priv *pp = ap->private_data;
1056 void __iomem *port_mmio = ahci_port_base(ap);
1057 u8 *fis = pp->cmd_tbl;
1058 u32 tmp;
1059
1060 /* prep the command */
1061 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1062 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1063
1064 /* issue & wait */
1065 writel(1, port_mmio + PORT_CMD_ISSUE);
1066
1067 if (timeout_msec) {
1068 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1069 1, timeout_msec);
1070 if (tmp & 0x1) {
1071 ahci_kick_engine(ap, 1);
1072 return -EBUSY;
1073 }
1074 } else
1075 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1076
1077 return 0;
1078}
1079
Tejun Heocc0680a2007-08-06 18:36:23 +09001080static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001081 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001082{
Tejun Heocc0680a2007-08-06 18:36:23 +09001083 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001084 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001085 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001086 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001087 int rc;
1088
1089 DPRINTK("ENTER\n");
1090
Tejun Heocc0680a2007-08-06 18:36:23 +09001091 if (ata_link_offline(link)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001092 DPRINTK("PHY reports no device\n");
1093 *class = ATA_DEV_NONE;
1094 return 0;
1095 }
1096
Tejun Heo4658f792006-03-22 21:07:03 +09001097 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001098 rc = ahci_kick_engine(ap, 1);
1099 if (rc)
Tejun Heocc0680a2007-08-06 18:36:23 +09001100 ata_link_printk(link, KERN_WARNING,
Tejun Heod2e75df2007-07-16 14:29:39 +09001101 "failed to reset engine (errno=%d)", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001102
Tejun Heocc0680a2007-08-06 18:36:23 +09001103 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001104
1105 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001106 msecs = 0;
1107 now = jiffies;
1108 if (time_after(now, deadline))
1109 msecs = jiffies_to_msecs(deadline - now);
1110
Tejun Heo4658f792006-03-22 21:07:03 +09001111 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001112 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001113 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001114 rc = -EIO;
1115 reason = "1st FIS failed";
1116 goto fail;
1117 }
1118
1119 /* spec says at least 5us, but be generous and sleep for 1ms */
1120 msleep(1);
1121
1122 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001123 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001124 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001125
1126 /* spec mandates ">= 2ms" before checking status.
1127 * We wait 150ms, because that was the magic delay used for
1128 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1129 * between when the ATA command register is written, and then
1130 * status is checked. Because waiting for "a while" before
1131 * checking status is fine, post SRST, we perform this magic
1132 * delay here as well.
1133 */
1134 msleep(150);
1135
Tejun Heo9b893912007-02-02 16:50:52 +09001136 rc = ata_wait_ready(ap, deadline);
1137 /* link occupied, -ENODEV too is an error */
1138 if (rc) {
1139 reason = "device not ready";
1140 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001141 }
Tejun Heo9b893912007-02-02 16:50:52 +09001142 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001143
1144 DPRINTK("EXIT, class=%u\n", *class);
1145 return 0;
1146
Tejun Heo4658f792006-03-22 21:07:03 +09001147 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001148 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001149 return rc;
1150}
1151
Tejun Heocc0680a2007-08-06 18:36:23 +09001152static int ahci_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001153 unsigned long deadline)
1154{
Tejun Heo7d50b602007-09-23 13:19:54 +09001155 int pmp = 0;
1156
1157 if (link->ap->flags & ATA_FLAG_PMP)
1158 pmp = SATA_PMP_CTRL_PORT;
1159
1160 return ahci_do_softreset(link, class, pmp, deadline);
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001161}
1162
Tejun Heocc0680a2007-08-06 18:36:23 +09001163static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001164 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001165{
Tejun Heocc0680a2007-08-06 18:36:23 +09001166 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001167 struct ahci_port_priv *pp = ap->private_data;
1168 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1169 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001170 int rc;
1171
1172 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173
Tejun Heo4447d352007-04-17 23:44:08 +09001174 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001175
1176 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001177 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001178 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001179 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001180
Tejun Heocc0680a2007-08-06 18:36:23 +09001181 rc = sata_std_hardreset(link, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001182
Tejun Heo4447d352007-04-17 23:44:08 +09001183 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184
Tejun Heocc0680a2007-08-06 18:36:23 +09001185 if (rc == 0 && ata_link_online(link))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001186 *class = ahci_dev_classify(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001187 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001188 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189
Tejun Heo4bd00f62006-02-11 16:26:02 +09001190 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1191 return rc;
1192}
1193
Tejun Heocc0680a2007-08-06 18:36:23 +09001194static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001195 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001196{
Tejun Heocc0680a2007-08-06 18:36:23 +09001197 struct ata_port *ap = link->ap;
Tejun Heoda3dbb12007-07-16 14:29:40 +09001198 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001199 int rc;
1200
1201 DPRINTK("ENTER\n");
1202
Tejun Heo4447d352007-04-17 23:44:08 +09001203 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001204
Tejun Heocc0680a2007-08-06 18:36:23 +09001205 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heod4b2bab2007-02-02 16:50:52 +09001206 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001207
1208 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001209 ahci_scr_read(ap, SCR_ERROR, &serror);
1210 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001211
Tejun Heo4447d352007-04-17 23:44:08 +09001212 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001213
1214 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1215
1216 /* vt8251 doesn't clear BSY on signature FIS reception,
1217 * request follow-up softreset.
1218 */
1219 return rc ?: -EAGAIN;
1220}
1221
Tejun Heocc0680a2007-08-06 18:36:23 +09001222static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001223{
Tejun Heocc0680a2007-08-06 18:36:23 +09001224 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001225 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001226 u32 new_tmp, tmp;
1227
Tejun Heocc0680a2007-08-06 18:36:23 +09001228 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001229
1230 /* Make sure port's ATAPI bit is set appropriately */
1231 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001232 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001233 new_tmp |= PORT_CMD_ATAPI;
1234 else
1235 new_tmp &= ~PORT_CMD_ATAPI;
1236 if (new_tmp != tmp) {
1237 writel(new_tmp, port_mmio + PORT_CMD);
1238 readl(port_mmio + PORT_CMD); /* flush */
1239 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240}
1241
Tejun Heo7d50b602007-09-23 13:19:54 +09001242static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1243 unsigned long deadline)
1244{
1245 return ahci_do_softreset(link, class, link->pmp, deadline);
1246}
1247
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248static u8 ahci_check_status(struct ata_port *ap)
1249{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001250 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251
1252 return readl(mmio + PORT_TFDATA) & 0xFF;
1253}
1254
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1256{
1257 struct ahci_port_priv *pp = ap->private_data;
1258 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1259
1260 ata_tf_from_fis(d2h_fis, tf);
1261}
1262
Tejun Heo12fad3f2006-05-15 21:03:55 +09001263static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001265 struct scatterlist *sg;
1266 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001267 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
1269 VPRINTK("ENTER\n");
1270
1271 /*
1272 * Next, the S/G list.
1273 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001274 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001275 ata_for_each_sg(sg, qc) {
1276 dma_addr_t addr = sg_dma_address(sg);
1277 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001279 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1280 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1281 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -05001282
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001283 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001284 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001286
1287 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288}
1289
1290static void ahci_qc_prep(struct ata_queued_cmd *qc)
1291{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001292 struct ata_port *ap = qc->ap;
1293 struct ahci_port_priv *pp = ap->private_data;
Tejun Heocc9278e2006-02-10 17:25:47 +09001294 int is_atapi = is_atapi_taskfile(&qc->tf);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001295 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 u32 opts;
1297 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001298 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299
1300 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001301 * Fill in command table information. First, the header,
1302 * a SATA Register - Host to Device command FIS.
1303 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001304 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1305
Tejun Heo7d50b602007-09-23 13:19:54 +09001306 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001307 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001308 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1309 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001310 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311
Tejun Heocc9278e2006-02-10 17:25:47 +09001312 n_elem = 0;
1313 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001314 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315
Tejun Heocc9278e2006-02-10 17:25:47 +09001316 /*
1317 * Fill in command slot information.
1318 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001319 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001320 if (qc->tf.flags & ATA_TFLAG_WRITE)
1321 opts |= AHCI_CMD_WRITE;
1322 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001323 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001324
Tejun Heo12fad3f2006-05-15 21:03:55 +09001325 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326}
1327
Tejun Heo78cd52d2006-05-15 20:58:29 +09001328static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329{
Tejun Heo417a1a62007-09-23 13:19:55 +09001330 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001331 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001332 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1333 struct ata_link *link = NULL;
1334 struct ata_queued_cmd *active_qc;
1335 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001336 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337
Tejun Heo7d50b602007-09-23 13:19:54 +09001338 /* determine active link */
1339 ata_port_for_each_link(link, ap)
1340 if (ata_link_active(link))
1341 break;
1342 if (!link)
1343 link = &ap->link;
1344
1345 active_qc = ata_qc_from_tag(ap, link->active_tag);
1346 active_ehi = &link->eh_info;
1347
1348 /* record irq stat */
1349 ata_ehi_clear_desc(host_ehi);
1350 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001351
Tejun Heo78cd52d2006-05-15 20:58:29 +09001352 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001353 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001354 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001355 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356
Tejun Heo41669552006-11-29 11:33:14 +09001357 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001358 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001359 irq_stat &= ~PORT_IRQ_IF_ERR;
1360
Conke Hu55a61602007-03-27 18:33:05 +08001361 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001362 /* If qc is active, charge it; otherwise, the active
1363 * link. There's no active qc on NCQ errors. It will
1364 * be determined by EH by reading log page 10h.
1365 */
1366 if (active_qc)
1367 active_qc->err_mask |= AC_ERR_DEV;
1368 else
1369 active_ehi->err_mask |= AC_ERR_DEV;
1370
Tejun Heo417a1a62007-09-23 13:19:55 +09001371 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001372 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001373 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374
Tejun Heo78cd52d2006-05-15 20:58:29 +09001375 if (irq_stat & PORT_IRQ_UNK_FIS) {
1376 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
Tejun Heo7d50b602007-09-23 13:19:54 +09001378 active_ehi->err_mask |= AC_ERR_HSM;
1379 active_ehi->action |= ATA_EH_SOFTRESET;
1380 ata_ehi_push_desc(active_ehi,
1381 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001382 unk[0], unk[1], unk[2], unk[3]);
1383 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001384
Tejun Heo7d50b602007-09-23 13:19:54 +09001385 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1386 active_ehi->err_mask |= AC_ERR_HSM;
1387 active_ehi->action |= ATA_EH_SOFTRESET;
1388 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1389 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001390
Tejun Heo7d50b602007-09-23 13:19:54 +09001391 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1392 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1393 host_ehi->action |= ATA_EH_SOFTRESET;
1394 ata_ehi_push_desc(host_ehi, "host bus error");
1395 }
1396
1397 if (irq_stat & PORT_IRQ_IF_ERR) {
1398 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1399 host_ehi->action |= ATA_EH_SOFTRESET;
1400 ata_ehi_push_desc(host_ehi, "interface fatal error");
1401 }
1402
1403 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1404 ata_ehi_hotplugged(host_ehi);
1405 ata_ehi_push_desc(host_ehi, "%s",
1406 irq_stat & PORT_IRQ_CONNECT ?
1407 "connection status changed" : "PHY RDY changed");
1408 }
1409
1410 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411
Tejun Heo78cd52d2006-05-15 20:58:29 +09001412 if (irq_stat & PORT_IRQ_FREEZE)
1413 ata_port_freeze(ap);
1414 else
1415 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001416}
1417
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001418static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419{
Tejun Heo4447d352007-04-17 23:44:08 +09001420 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001421 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001422 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001423 u32 status, qc_active;
Tejun Heo0291f952007-01-25 19:16:28 +09001424 int rc, known_irq = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425
1426 status = readl(port_mmio + PORT_IRQ_STAT);
1427 writel(status, port_mmio + PORT_IRQ_STAT);
1428
Tejun Heo78cd52d2006-05-15 20:58:29 +09001429 if (unlikely(status & PORT_IRQ_ERROR)) {
1430 ahci_error_intr(ap, status);
1431 return;
1432 }
1433
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001434 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo7d77b242007-09-23 13:14:13 +09001435 /* If the 'N' bit in word 0 of the FIS is set, we just
1436 * received asynchronous notification. Tell libata
1437 * about it. Note that as the SDB FIS itself is
1438 * accessible, SNotification can be emulated by the
1439 * driver but don't bother for the time being.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001440 */
1441 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1442 u32 f0 = le32_to_cpu(f[0]);
1443
Tejun Heo7d77b242007-09-23 13:14:13 +09001444 if (f0 & (1 << 15))
1445 sata_async_notification(ap);
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001446 }
1447
Tejun Heo7d50b602007-09-23 13:19:54 +09001448 /* pp->active_link is valid iff any command is in flight */
1449 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001450 qc_active = readl(port_mmio + PORT_SCR_ACT);
1451 else
1452 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1453
1454 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1455 if (rc > 0)
1456 return;
1457 if (rc < 0) {
1458 ehi->err_mask |= AC_ERR_HSM;
1459 ehi->action |= ATA_EH_SOFTRESET;
1460 ata_port_freeze(ap);
1461 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 }
1463
Tejun Heo2a3917a2006-05-15 20:58:30 +09001464 /* hmmm... a spurious interupt */
1465
Tejun Heo0291f952007-01-25 19:16:28 +09001466 /* if !NCQ, ignore. No modern ATA device has broken HSM
1467 * implementation for non-NCQ commands.
1468 */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001469 if (!ap->link.sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001470 return;
1471
Tejun Heo0291f952007-01-25 19:16:28 +09001472 if (status & PORT_IRQ_D2H_REG_FIS) {
1473 if (!pp->ncq_saw_d2h)
1474 ata_port_printk(ap, KERN_INFO,
1475 "D2H reg with I during NCQ, "
1476 "this message won't be printed again\n");
1477 pp->ncq_saw_d2h = 1;
1478 known_irq = 1;
1479 }
Tejun Heo2a3917a2006-05-15 20:58:30 +09001480
Tejun Heo0291f952007-01-25 19:16:28 +09001481 if (status & PORT_IRQ_DMAS_FIS) {
1482 if (!pp->ncq_saw_dmas)
1483 ata_port_printk(ap, KERN_INFO,
1484 "DMAS FIS during NCQ, "
1485 "this message won't be printed again\n");
1486 pp->ncq_saw_dmas = 1;
1487 known_irq = 1;
1488 }
1489
Tejun Heoa2bbd0c2007-02-21 16:34:25 +09001490 if (status & PORT_IRQ_SDB_FIS) {
Al Viro04d4f7a2007-02-09 16:39:30 +00001491 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
Tejun Heo0291f952007-01-25 19:16:28 +09001492
Tejun Heoafb2d552007-02-27 13:24:19 +09001493 if (le32_to_cpu(f[1])) {
1494 /* SDB FIS containing spurious completions
1495 * might be dangerous, whine and fail commands
1496 * with HSM violation. EH will turn off NCQ
1497 * after several such failures.
1498 */
1499 ata_ehi_push_desc(ehi,
1500 "spurious completions during NCQ "
1501 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1502 readl(port_mmio + PORT_CMD_ISSUE),
1503 readl(port_mmio + PORT_SCR_ACT),
1504 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1505 ehi->err_mask |= AC_ERR_HSM;
1506 ehi->action |= ATA_EH_SOFTRESET;
1507 ata_port_freeze(ap);
1508 } else {
1509 if (!pp->ncq_saw_sdb)
1510 ata_port_printk(ap, KERN_INFO,
1511 "spurious SDB FIS %08x:%08x during NCQ, "
1512 "this message won't be printed again\n",
1513 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1514 pp->ncq_saw_sdb = 1;
1515 }
Tejun Heo0291f952007-01-25 19:16:28 +09001516 known_irq = 1;
1517 }
1518
1519 if (!known_irq)
Tejun Heo78cd52d2006-05-15 20:58:29 +09001520 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
Tejun Heo0291f952007-01-25 19:16:28 +09001521 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001522 status, ap->link.active_tag, ap->link.sactive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523}
1524
1525static void ahci_irq_clear(struct ata_port *ap)
1526{
1527 /* TODO */
1528}
1529
David Howells7d12e782006-10-05 14:55:46 +01001530static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531{
Jeff Garzikcca39742006-08-24 03:19:22 -04001532 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533 struct ahci_host_priv *hpriv;
1534 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001535 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536 u32 irq_stat, irq_ack = 0;
1537
1538 VPRINTK("ENTER\n");
1539
Jeff Garzikcca39742006-08-24 03:19:22 -04001540 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001541 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001542
1543 /* sigh. 0xffffffff is a valid return from h/w */
1544 irq_stat = readl(mmio + HOST_IRQ_STAT);
1545 irq_stat &= hpriv->port_map;
1546 if (!irq_stat)
1547 return IRQ_NONE;
1548
Jeff Garzikcca39742006-08-24 03:19:22 -04001549 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550
Jeff Garzikcca39742006-08-24 03:19:22 -04001551 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
Jeff Garzik67846b32005-10-05 02:58:32 -04001554 if (!(irq_stat & (1 << i)))
1555 continue;
1556
Jeff Garzikcca39742006-08-24 03:19:22 -04001557 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001558 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001559 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001560 VPRINTK("port %u\n", i);
1561 } else {
1562 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001563 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001564 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001565 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001567
1568 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569 }
1570
1571 if (irq_ack) {
1572 writel(irq_ack, mmio + HOST_IRQ_STAT);
1573 handled = 1;
1574 }
1575
Jeff Garzikcca39742006-08-24 03:19:22 -04001576 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577
1578 VPRINTK("EXIT\n");
1579
1580 return IRQ_RETVAL(handled);
1581}
1582
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001583static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584{
1585 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001586 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001587 struct ahci_port_priv *pp = ap->private_data;
1588
1589 /* Keep track of the currently active link. It will be used
1590 * in completion path to determine whether NCQ phase is in
1591 * progress.
1592 */
1593 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594
Tejun Heo12fad3f2006-05-15 21:03:55 +09001595 if (qc->tf.protocol == ATA_PROT_NCQ)
1596 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1597 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1599
1600 return 0;
1601}
1602
Tejun Heo78cd52d2006-05-15 20:58:29 +09001603static void ahci_freeze(struct ata_port *ap)
1604{
Tejun Heo4447d352007-04-17 23:44:08 +09001605 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001606
1607 /* turn IRQ off */
1608 writel(0, port_mmio + PORT_IRQ_MASK);
1609}
1610
1611static void ahci_thaw(struct ata_port *ap)
1612{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001613 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001614 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001615 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001616 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001617
1618 /* clear IRQ */
1619 tmp = readl(port_mmio + PORT_IRQ_STAT);
1620 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001621 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001622
Tejun Heo7d50b602007-09-23 13:19:54 +09001623 /* turn IRQ back on, ignore BAD_PMP if PMP isn't attached */
1624 tmp = pp->intr_mask;
1625 if (!ap->nr_pmp_links)
1626 tmp &= ~PORT_IRQ_BAD_PMP;
1627 writel(tmp, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001628}
1629
1630static void ahci_error_handler(struct ata_port *ap)
1631{
Tejun Heob51e9e52006-06-29 01:29:30 +09001632 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001633 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001634 ahci_stop_engine(ap);
1635 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001636 }
1637
1638 /* perform recovery */
Tejun Heo7d50b602007-09-23 13:19:54 +09001639 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1640 ahci_hardreset, ahci_postreset,
1641 sata_pmp_std_prereset, ahci_pmp_softreset,
1642 sata_pmp_std_hardreset, sata_pmp_std_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001643}
1644
Tejun Heoad616ff2006-11-01 18:00:24 +09001645static void ahci_vt8251_error_handler(struct ata_port *ap)
1646{
Tejun Heoad616ff2006-11-01 18:00:24 +09001647 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1648 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001649 ahci_stop_engine(ap);
1650 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001651 }
1652
1653 /* perform recovery */
1654 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1655 ahci_postreset);
1656}
1657
Tejun Heo78cd52d2006-05-15 20:58:29 +09001658static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1659{
1660 struct ata_port *ap = qc->ap;
1661
Tejun Heod2e75df2007-07-16 14:29:39 +09001662 /* make DMA engine forget about the failed command */
1663 if (qc->flags & ATA_QCFLAG_FAILED)
1664 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001665}
1666
Tejun Heo7d50b602007-09-23 13:19:54 +09001667static void ahci_pmp_attach(struct ata_port *ap)
1668{
1669 void __iomem *port_mmio = ahci_port_base(ap);
1670 u32 cmd;
1671
1672 cmd = readl(port_mmio + PORT_CMD);
1673 cmd |= PORT_CMD_PMP;
1674 writel(cmd, port_mmio + PORT_CMD);
1675}
1676
1677static void ahci_pmp_detach(struct ata_port *ap)
1678{
1679 void __iomem *port_mmio = ahci_port_base(ap);
1680 struct ahci_host_priv *hpriv = ap->host->private_data;
1681 unsigned long flags;
1682 u32 cmd;
1683
1684 cmd = readl(port_mmio + PORT_CMD);
1685 cmd &= ~PORT_CMD_PMP;
1686 writel(cmd, port_mmio + PORT_CMD);
1687
1688 if (hpriv->cap & HOST_CAP_NCQ) {
1689 spin_lock_irqsave(ap->lock, flags);
1690 ap->flags |= ATA_FLAG_NCQ;
1691 spin_unlock_irqrestore(ap->lock, flags);
1692 }
1693}
1694
1695static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
1696{
1697 struct ata_port *ap = dev->link->ap;
1698 struct ata_taskfile tf;
1699 int rc;
1700
1701 ahci_kick_engine(ap, 0);
1702
1703 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
1704 rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1705 SATA_PMP_SCR_TIMEOUT);
1706 if (rc == 0) {
1707 ahci_tf_read(ap, &tf);
1708 *r_val = sata_pmp_read_val(&tf);
1709 }
1710 return rc;
1711}
1712
1713static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
1714{
1715 struct ata_port *ap = dev->link->ap;
1716 struct ata_taskfile tf;
1717
1718 ahci_kick_engine(ap, 0);
1719
1720 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
1721 return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1722 SATA_PMP_SCR_TIMEOUT);
1723}
1724
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001725static int ahci_port_resume(struct ata_port *ap)
1726{
1727 ahci_power_up(ap);
1728 ahci_start_port(ap);
1729
Tejun Heo7d50b602007-09-23 13:19:54 +09001730 if (ap->nr_pmp_links)
1731 ahci_pmp_attach(ap);
1732 else
1733 ahci_pmp_detach(ap);
1734
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001735 return 0;
1736}
1737
Tejun Heo438ac6d2007-03-02 17:31:26 +09001738#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001739static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1740{
Tejun Heoc1332872006-07-26 15:59:26 +09001741 const char *emsg = NULL;
1742 int rc;
1743
Tejun Heo4447d352007-04-17 23:44:08 +09001744 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001745 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001746 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001747 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001748 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001749 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001750 }
1751
1752 return rc;
1753}
1754
Tejun Heoc1332872006-07-26 15:59:26 +09001755static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1756{
Jeff Garzikcca39742006-08-24 03:19:22 -04001757 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001758 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001759 u32 ctl;
1760
1761 if (mesg.event == PM_EVENT_SUSPEND) {
1762 /* AHCI spec rev1.1 section 8.3.3:
1763 * Software must disable interrupts prior to requesting a
1764 * transition of the HBA to D3 state.
1765 */
1766 ctl = readl(mmio + HOST_CTL);
1767 ctl &= ~HOST_IRQ_EN;
1768 writel(ctl, mmio + HOST_CTL);
1769 readl(mmio + HOST_CTL); /* flush */
1770 }
1771
1772 return ata_pci_device_suspend(pdev, mesg);
1773}
1774
1775static int ahci_pci_device_resume(struct pci_dev *pdev)
1776{
Jeff Garzikcca39742006-08-24 03:19:22 -04001777 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001778 int rc;
1779
Tejun Heo553c4aa2006-12-26 19:39:50 +09001780 rc = ata_pci_device_do_resume(pdev);
1781 if (rc)
1782 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09001783
1784 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09001785 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001786 if (rc)
1787 return rc;
1788
Tejun Heo4447d352007-04-17 23:44:08 +09001789 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001790 }
1791
Jeff Garzikcca39742006-08-24 03:19:22 -04001792 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001793
1794 return 0;
1795}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001796#endif
Tejun Heoc1332872006-07-26 15:59:26 +09001797
Tejun Heo254950c2006-07-26 15:59:25 +09001798static int ahci_port_start(struct ata_port *ap)
1799{
Jeff Garzikcca39742006-08-24 03:19:22 -04001800 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09001801 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09001802 void *mem;
1803 dma_addr_t mem_dma;
1804 int rc;
1805
Tejun Heo24dc5f32007-01-20 16:00:28 +09001806 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09001807 if (!pp)
1808 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001809
1810 rc = ata_pad_alloc(ap, dev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001811 if (rc)
Tejun Heo254950c2006-07-26 15:59:25 +09001812 return rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001813
Tejun Heo24dc5f32007-01-20 16:00:28 +09001814 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1815 GFP_KERNEL);
1816 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09001817 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001818 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1819
1820 /*
1821 * First item in chunk of DMA memory: 32-slot command table,
1822 * 32 bytes each in size
1823 */
1824 pp->cmd_slot = mem;
1825 pp->cmd_slot_dma = mem_dma;
1826
1827 mem += AHCI_CMD_SLOT_SZ;
1828 mem_dma += AHCI_CMD_SLOT_SZ;
1829
1830 /*
1831 * Second item: Received-FIS area
1832 */
1833 pp->rx_fis = mem;
1834 pp->rx_fis_dma = mem_dma;
1835
1836 mem += AHCI_RX_FIS_SZ;
1837 mem_dma += AHCI_RX_FIS_SZ;
1838
1839 /*
1840 * Third item: data area for storing a single command
1841 * and its scatter-gather table
1842 */
1843 pp->cmd_tbl = mem;
1844 pp->cmd_tbl_dma = mem_dma;
1845
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001846 /*
1847 * Save off initial list of interrupts to be enabled.
1848 * This could be changed later
1849 */
1850 pp->intr_mask = DEF_PORT_IRQ;
1851
Tejun Heo254950c2006-07-26 15:59:25 +09001852 ap->private_data = pp;
1853
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001854 /* engage engines, captain */
1855 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09001856}
1857
1858static void ahci_port_stop(struct ata_port *ap)
1859{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001860 const char *emsg = NULL;
1861 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001862
Tejun Heo0be0aa92006-07-26 15:59:26 +09001863 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09001864 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001865 if (rc)
1866 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09001867}
1868
Tejun Heo4447d352007-04-17 23:44:08 +09001869static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872
Linus Torvalds1da177e2005-04-16 15:20:36 -07001873 if (using_dac &&
1874 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1875 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1876 if (rc) {
1877 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1878 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001879 dev_printk(KERN_ERR, &pdev->dev,
1880 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881 return rc;
1882 }
1883 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001884 } else {
1885 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1886 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001887 dev_printk(KERN_ERR, &pdev->dev,
1888 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889 return rc;
1890 }
1891 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1892 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001893 dev_printk(KERN_ERR, &pdev->dev,
1894 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 return rc;
1896 }
1897 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 return 0;
1899}
1900
Tejun Heo4447d352007-04-17 23:44:08 +09001901static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902{
Tejun Heo4447d352007-04-17 23:44:08 +09001903 struct ahci_host_priv *hpriv = host->private_data;
1904 struct pci_dev *pdev = to_pci_dev(host->dev);
1905 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 u32 vers, cap, impl, speed;
1907 const char *speed_s;
1908 u16 cc;
1909 const char *scc_s;
1910
1911 vers = readl(mmio + HOST_VERSION);
1912 cap = hpriv->cap;
1913 impl = hpriv->port_map;
1914
1915 speed = (cap >> 20) & 0xf;
1916 if (speed == 1)
1917 speed_s = "1.5";
1918 else if (speed == 2)
1919 speed_s = "3";
1920 else
1921 speed_s = "?";
1922
1923 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05001924 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05001926 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05001928 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 scc_s = "RAID";
1930 else
1931 scc_s = "unknown";
1932
Jeff Garzika9524a72005-10-30 14:39:11 -05001933 dev_printk(KERN_INFO, &pdev->dev,
1934 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1936 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937
1938 (vers >> 24) & 0xff,
1939 (vers >> 16) & 0xff,
1940 (vers >> 8) & 0xff,
1941 vers & 0xff,
1942
1943 ((cap >> 8) & 0x1f) + 1,
1944 (cap & 0x1f) + 1,
1945 speed_s,
1946 impl,
1947 scc_s);
1948
Jeff Garzika9524a72005-10-30 14:39:11 -05001949 dev_printk(KERN_INFO, &pdev->dev,
1950 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09001951 "%s%s%s%s%s%s%s"
1952 "%s%s%s%s%s%s%s\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001953 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954
1955 cap & (1 << 31) ? "64bit " : "",
1956 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09001957 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 cap & (1 << 28) ? "ilck " : "",
1959 cap & (1 << 27) ? "stag " : "",
1960 cap & (1 << 26) ? "pm " : "",
1961 cap & (1 << 25) ? "led " : "",
1962
1963 cap & (1 << 24) ? "clo " : "",
1964 cap & (1 << 19) ? "nz " : "",
1965 cap & (1 << 18) ? "only " : "",
1966 cap & (1 << 17) ? "pmp " : "",
1967 cap & (1 << 15) ? "pio " : "",
1968 cap & (1 << 14) ? "slum " : "",
1969 cap & (1 << 13) ? "part " : ""
1970 );
1971}
1972
Tejun Heo24dc5f32007-01-20 16:00:28 +09001973static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974{
1975 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09001976 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1977 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001978 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001980 struct ata_host *host;
1981 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001982
1983 VPRINTK("ENTER\n");
1984
Tejun Heo12fad3f2006-05-15 21:03:55 +09001985 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1986
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001988 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989
Tejun Heo4447d352007-04-17 23:44:08 +09001990 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001991 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001992 if (rc)
1993 return rc;
1994
Tejun Heo0d5ff562007-02-01 15:06:36 +09001995 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1996 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001997 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001998 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001999 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002000
Tejun Heo24dc5f32007-01-20 16:00:28 +09002001 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2002 if (!hpriv)
2003 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002004 hpriv->flags |= (unsigned long)pi.private_data;
2005
2006 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2007 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002008
Tejun Heo4447d352007-04-17 23:44:08 +09002009 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002010 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011
Tejun Heo4447d352007-04-17 23:44:08 +09002012 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002013 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002014 pi.flags |= ATA_FLAG_NCQ;
2015
Tejun Heo7d50b602007-09-23 13:19:54 +09002016 if (hpriv->cap & HOST_CAP_PMP)
2017 pi.flags |= ATA_FLAG_PMP;
2018
Tejun Heo4447d352007-04-17 23:44:08 +09002019 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2020 if (!host)
2021 return -ENOMEM;
2022 host->iomap = pcim_iomap_table(pdev);
2023 host->private_data = hpriv;
2024
2025 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002026 struct ata_port *ap = host->ports[i];
2027 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09002028
Tejun Heocbcdd872007-08-18 13:14:55 +09002029 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2030 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2031 0x100 + ap->port_no * 0x80, "port");
2032
Jeff Garzikdab632e2007-05-28 08:33:01 -04002033 /* standard SATA port setup */
Tejun Heo203ef6c2007-07-16 14:29:40 +09002034 if (hpriv->port_map & (1 << i))
Tejun Heo4447d352007-04-17 23:44:08 +09002035 ap->ioaddr.cmd_addr = port_mmio;
Jeff Garzikdab632e2007-05-28 08:33:01 -04002036
2037 /* disabled/not-implemented port */
2038 else
2039 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002040 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041
2042 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002043 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002044 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002045 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002046
Tejun Heo4447d352007-04-17 23:44:08 +09002047 rc = ahci_reset_controller(host);
2048 if (rc)
2049 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002050
Tejun Heo4447d352007-04-17 23:44:08 +09002051 ahci_init_controller(host);
2052 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053
Tejun Heo4447d352007-04-17 23:44:08 +09002054 pci_set_master(pdev);
2055 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2056 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002057}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058
2059static int __init ahci_init(void)
2060{
Pavel Roskinb7887192006-08-10 18:13:18 +09002061 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062}
2063
Linus Torvalds1da177e2005-04-16 15:20:36 -07002064static void __exit ahci_exit(void)
2065{
2066 pci_unregister_driver(&ahci_pci_driver);
2067}
2068
2069
2070MODULE_AUTHOR("Jeff Garzik");
2071MODULE_DESCRIPTION("AHCI SATA low-level driver");
2072MODULE_LICENSE("GPL");
2073MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002074MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002075
2076module_init(ahci_init);
2077module_exit(ahci_exit);