Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 36 | /* |
| 37 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 38 | * over cache flushing. |
| 39 | */ |
| 40 | struct pipe_control { |
| 41 | struct drm_i915_gem_object *obj; |
| 42 | volatile u32 *cpu_page; |
| 43 | u32 gtt_offset; |
| 44 | }; |
| 45 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 46 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 47 | { |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 48 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 49 | if (space < 0) |
| 50 | space += ring->size; |
| 51 | return space; |
| 52 | } |
| 53 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 54 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 56 | u32 invalidate_domains, |
| 57 | u32 flush_domains) |
| 58 | { |
| 59 | u32 cmd; |
| 60 | int ret; |
| 61 | |
| 62 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 64 | cmd |= MI_NO_WRITE_FLUSH; |
| 65 | |
| 66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 67 | cmd |= MI_READ_FLUSH; |
| 68 | |
| 69 | ret = intel_ring_begin(ring, 2); |
| 70 | if (ret) |
| 71 | return ret; |
| 72 | |
| 73 | intel_ring_emit(ring, cmd); |
| 74 | intel_ring_emit(ring, MI_NOOP); |
| 75 | intel_ring_advance(ring); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int |
| 81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 82 | u32 invalidate_domains, |
| 83 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 84 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 85 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 86 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 87 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 88 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 89 | /* |
| 90 | * read/write caches: |
| 91 | * |
| 92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 94 | * also flushed at 2d versus 3d pipeline switches. |
| 95 | * |
| 96 | * read-only caches: |
| 97 | * |
| 98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 99 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 100 | * |
| 101 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 102 | * |
| 103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 104 | * invalidated when MI_EXE_FLUSH is set. |
| 105 | * |
| 106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 107 | * invalidated with every MI_FLUSH. |
| 108 | * |
| 109 | * TLBs: |
| 110 | * |
| 111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 114 | * are flushed at any MI_FLUSH. |
| 115 | */ |
| 116 | |
| 117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 121 | cmd |= MI_EXE_FLUSH; |
| 122 | |
| 123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 124 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 125 | cmd |= MI_INVALIDATE_ISP; |
| 126 | |
| 127 | ret = intel_ring_begin(ring, 2); |
| 128 | if (ret) |
| 129 | return ret; |
| 130 | |
| 131 | intel_ring_emit(ring, cmd); |
| 132 | intel_ring_emit(ring, MI_NOOP); |
| 133 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 134 | |
| 135 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 136 | } |
| 137 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 138 | /** |
| 139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 140 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 142 | * |
| 143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 144 | * produced by non-pipelined state commands), software needs to first |
| 145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 146 | * 0. |
| 147 | * |
| 148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 150 | * |
| 151 | * And the workaround for these two requires this workaround first: |
| 152 | * |
| 153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 154 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 155 | * flushes. |
| 156 | * |
| 157 | * And this last workaround is tricky because of the requirements on |
| 158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 159 | * volume 2 part 1: |
| 160 | * |
| 161 | * "1 of the following must also be set: |
| 162 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 163 | * - Depth Cache Flush Enable ([0] of DW1) |
| 164 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 165 | * - Depth Stall ([13] of DW1) |
| 166 | * - Post-Sync Operation ([13] of DW1) |
| 167 | * - Notify Enable ([8] of DW1)" |
| 168 | * |
| 169 | * The cache flushes require the workaround flush that triggered this |
| 170 | * one, so we can't use it. Depth stall would trigger the same. |
| 171 | * Post-sync nonzero is what triggered this second workaround, so we |
| 172 | * can't use that one either. Notify enable is IRQs, which aren't |
| 173 | * really our business. That leaves only stall at scoreboard. |
| 174 | */ |
| 175 | static int |
| 176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 177 | { |
| 178 | struct pipe_control *pc = ring->private; |
| 179 | u32 scratch_addr = pc->gtt_offset + 128; |
| 180 | int ret; |
| 181 | |
| 182 | |
| 183 | ret = intel_ring_begin(ring, 6); |
| 184 | if (ret) |
| 185 | return ret; |
| 186 | |
| 187 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 188 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 189 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 190 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 191 | intel_ring_emit(ring, 0); /* low dword */ |
| 192 | intel_ring_emit(ring, 0); /* high dword */ |
| 193 | intel_ring_emit(ring, MI_NOOP); |
| 194 | intel_ring_advance(ring); |
| 195 | |
| 196 | ret = intel_ring_begin(ring, 6); |
| 197 | if (ret) |
| 198 | return ret; |
| 199 | |
| 200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 201 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 202 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 203 | intel_ring_emit(ring, 0); |
| 204 | intel_ring_emit(ring, 0); |
| 205 | intel_ring_emit(ring, MI_NOOP); |
| 206 | intel_ring_advance(ring); |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | static int |
| 212 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 213 | u32 invalidate_domains, u32 flush_domains) |
| 214 | { |
| 215 | u32 flags = 0; |
| 216 | struct pipe_control *pc = ring->private; |
| 217 | u32 scratch_addr = pc->gtt_offset + 128; |
| 218 | int ret; |
| 219 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 221 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 222 | if (ret) |
| 223 | return ret; |
| 224 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 225 | /* Just flush everything. Experiments have shown that reducing the |
| 226 | * number of bits based on the write domains has little performance |
| 227 | * impact. |
| 228 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 229 | if (flush_domains) { |
| 230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 231 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 232 | /* |
| 233 | * Ensure that any following seqno writes only happen |
| 234 | * when the render cache is indeed flushed. |
| 235 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 236 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 237 | } |
| 238 | if (invalidate_domains) { |
| 239 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 240 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 241 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 242 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 243 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 244 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 245 | /* |
| 246 | * TLB invalidate requires a post-sync write. |
| 247 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 248 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 249 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 250 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 251 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 252 | if (ret) |
| 253 | return ret; |
| 254 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 255 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 256 | intel_ring_emit(ring, flags); |
| 257 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 258 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 259 | intel_ring_advance(ring); |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 264 | static int |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 265 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 266 | { |
| 267 | int ret; |
| 268 | |
| 269 | ret = intel_ring_begin(ring, 4); |
| 270 | if (ret) |
| 271 | return ret; |
| 272 | |
| 273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 274 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 275 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 276 | intel_ring_emit(ring, 0); |
| 277 | intel_ring_emit(ring, 0); |
| 278 | intel_ring_advance(ring); |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static int |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 284 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 285 | u32 invalidate_domains, u32 flush_domains) |
| 286 | { |
| 287 | u32 flags = 0; |
| 288 | struct pipe_control *pc = ring->private; |
| 289 | u32 scratch_addr = pc->gtt_offset + 128; |
| 290 | int ret; |
| 291 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 292 | /* |
| 293 | * Ensure that any following seqno writes only happen when the render |
| 294 | * cache is indeed flushed. |
| 295 | * |
| 296 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 297 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 298 | * don't try to be clever and just set it unconditionally. |
| 299 | */ |
| 300 | flags |= PIPE_CONTROL_CS_STALL; |
| 301 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 302 | /* Just flush everything. Experiments have shown that reducing the |
| 303 | * number of bits based on the write domains has little performance |
| 304 | * impact. |
| 305 | */ |
| 306 | if (flush_domains) { |
| 307 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 308 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 309 | } |
| 310 | if (invalidate_domains) { |
| 311 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 312 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 313 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 314 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 315 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 316 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 317 | /* |
| 318 | * TLB invalidate requires a post-sync write. |
| 319 | */ |
| 320 | flags |= PIPE_CONTROL_QW_WRITE; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 321 | |
| 322 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 323 | * set before a pipe_control command that has the state cache |
| 324 | * invalidate bit set. */ |
| 325 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 326 | } |
| 327 | |
| 328 | ret = intel_ring_begin(ring, 4); |
| 329 | if (ret) |
| 330 | return ret; |
| 331 | |
| 332 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 333 | intel_ring_emit(ring, flags); |
| 334 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 335 | intel_ring_emit(ring, 0); |
| 336 | intel_ring_advance(ring); |
| 337 | |
| 338 | return 0; |
| 339 | } |
| 340 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 341 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 342 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 343 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 344 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 345 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 346 | } |
| 347 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 348 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 349 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 350 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 351 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 352 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 353 | |
| 354 | return I915_READ(acthd_reg); |
| 355 | } |
| 356 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 357 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 358 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 359 | struct drm_device *dev = ring->dev; |
| 360 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 361 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 362 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 363 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 364 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 365 | if (HAS_FORCE_WAKE(dev)) |
| 366 | gen6_gt_force_wake_get(dev_priv); |
| 367 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 368 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 369 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 370 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 371 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 372 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 373 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 374 | |
| 375 | /* G45 ring initialization fails to reset head to zero */ |
| 376 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 377 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 378 | "ctl %08x head %08x tail %08x start %08x\n", |
| 379 | ring->name, |
| 380 | I915_READ_CTL(ring), |
| 381 | I915_READ_HEAD(ring), |
| 382 | I915_READ_TAIL(ring), |
| 383 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 384 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 385 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 386 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 387 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 388 | DRM_ERROR("failed to set %s head to zero " |
| 389 | "ctl %08x head %08x tail %08x start %08x\n", |
| 390 | ring->name, |
| 391 | I915_READ_CTL(ring), |
| 392 | I915_READ_HEAD(ring), |
| 393 | I915_READ_TAIL(ring), |
| 394 | I915_READ_START(ring)); |
| 395 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 396 | } |
| 397 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 398 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 399 | * registers with the above sequence (the readback of the HEAD registers |
| 400 | * also enforces ordering), otherwise the hw might lose the new ring |
| 401 | * register values. */ |
| 402 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 403 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 404 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 405 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 406 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 407 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 408 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
| 409 | I915_READ_START(ring) == obj->gtt_offset && |
| 410 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 411 | DRM_ERROR("%s initialization failed " |
| 412 | "ctl %08x head %08x tail %08x start %08x\n", |
| 413 | ring->name, |
| 414 | I915_READ_CTL(ring), |
| 415 | I915_READ_HEAD(ring), |
| 416 | I915_READ_TAIL(ring), |
| 417 | I915_READ_START(ring)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 418 | ret = -EIO; |
| 419 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 420 | } |
| 421 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 422 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 423 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 424 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 425 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 426 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 427 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 428 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 429 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 430 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 431 | out: |
| 432 | if (HAS_FORCE_WAKE(dev)) |
| 433 | gen6_gt_force_wake_put(dev_priv); |
| 434 | |
| 435 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 436 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 437 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 438 | static int |
| 439 | init_pipe_control(struct intel_ring_buffer *ring) |
| 440 | { |
| 441 | struct pipe_control *pc; |
| 442 | struct drm_i915_gem_object *obj; |
| 443 | int ret; |
| 444 | |
| 445 | if (ring->private) |
| 446 | return 0; |
| 447 | |
| 448 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 449 | if (!pc) |
| 450 | return -ENOMEM; |
| 451 | |
| 452 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 453 | if (obj == NULL) { |
| 454 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 455 | ret = -ENOMEM; |
| 456 | goto err; |
| 457 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 458 | |
| 459 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 460 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 461 | ret = i915_gem_object_pin(obj, 4096, true, false); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 462 | if (ret) |
| 463 | goto err_unref; |
| 464 | |
| 465 | pc->gtt_offset = obj->gtt_offset; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 466 | pc->cpu_page = kmap(sg_page(obj->pages->sgl)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 467 | if (pc->cpu_page == NULL) |
| 468 | goto err_unpin; |
| 469 | |
| 470 | pc->obj = obj; |
| 471 | ring->private = pc; |
| 472 | return 0; |
| 473 | |
| 474 | err_unpin: |
| 475 | i915_gem_object_unpin(obj); |
| 476 | err_unref: |
| 477 | drm_gem_object_unreference(&obj->base); |
| 478 | err: |
| 479 | kfree(pc); |
| 480 | return ret; |
| 481 | } |
| 482 | |
| 483 | static void |
| 484 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 485 | { |
| 486 | struct pipe_control *pc = ring->private; |
| 487 | struct drm_i915_gem_object *obj; |
| 488 | |
| 489 | if (!ring->private) |
| 490 | return; |
| 491 | |
| 492 | obj = pc->obj; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 493 | |
| 494 | kunmap(sg_page(obj->pages->sgl)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 495 | i915_gem_object_unpin(obj); |
| 496 | drm_gem_object_unreference(&obj->base); |
| 497 | |
| 498 | kfree(pc); |
| 499 | ring->private = NULL; |
| 500 | } |
| 501 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 502 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 503 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 504 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 505 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 506 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 507 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 508 | if (INTEL_INFO(dev)->gen > 3) { |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 509 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Jesse Barnes | b095cd0 | 2011-08-12 15:28:32 -0700 | [diff] [blame] | 510 | if (IS_GEN7(dev)) |
| 511 | I915_WRITE(GFX_MODE_GEN7, |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 512 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 513 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 514 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 515 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 516 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 517 | ret = init_pipe_control(ring); |
| 518 | if (ret) |
| 519 | return ret; |
| 520 | } |
| 521 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 522 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 523 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 524 | * "If this bit is set, STCunit will have LRA as replacement |
| 525 | * policy. [...] This bit must be reset. LRA replacement |
| 526 | * policy is not supported." |
| 527 | */ |
| 528 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 529 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 12b0286 | 2012-06-04 14:42:50 -0700 | [diff] [blame] | 530 | |
| 531 | /* This is not explicitly set for GEN6, so read the register. |
| 532 | * see intel_ring_mi_set_context() for why we care. |
| 533 | * TODO: consider explicitly setting the bit for GEN5 |
| 534 | */ |
| 535 | ring->itlb_before_ctx_switch = |
| 536 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 537 | } |
| 538 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 539 | if (INTEL_INFO(dev)->gen >= 6) |
| 540 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 541 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 542 | if (HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 543 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 544 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 545 | return ret; |
| 546 | } |
| 547 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 548 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 549 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 550 | struct drm_device *dev = ring->dev; |
| 551 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 552 | if (!ring->private) |
| 553 | return; |
| 554 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 555 | if (HAS_BROKEN_CS_TLB(dev)) |
| 556 | drm_gem_object_unreference(to_gem_object(ring->private)); |
| 557 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 558 | cleanup_pipe_control(ring); |
| 559 | } |
| 560 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 561 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 562 | update_mboxes(struct intel_ring_buffer *ring, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 563 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 564 | { |
Chris Wilson | 1c8b46f | 2012-11-14 09:15:14 +0000 | [diff] [blame] | 565 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 566 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 567 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 568 | } |
| 569 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 570 | /** |
| 571 | * gen6_add_request - Update the semaphore mailbox registers |
| 572 | * |
| 573 | * @ring - ring that is adding a request |
| 574 | * @seqno - return seqno stuck into the ring |
| 575 | * |
| 576 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 577 | * This acts like a signal in the canonical semaphore. |
| 578 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 579 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 580 | gen6_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 581 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 582 | u32 mbox1_reg; |
| 583 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 584 | int ret; |
| 585 | |
| 586 | ret = intel_ring_begin(ring, 10); |
| 587 | if (ret) |
| 588 | return ret; |
| 589 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 590 | mbox1_reg = ring->signal_mbox[0]; |
| 591 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 592 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 593 | update_mboxes(ring, mbox1_reg); |
| 594 | update_mboxes(ring, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 595 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 596 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 597 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 598 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 599 | intel_ring_advance(ring); |
| 600 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 601 | return 0; |
| 602 | } |
| 603 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 604 | /** |
| 605 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 606 | * |
| 607 | * @waiter - ring that is waiting |
| 608 | * @signaller - ring which has, or will signal |
| 609 | * @seqno - seqno which the waiter will block on |
| 610 | */ |
| 611 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 612 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 613 | struct intel_ring_buffer *signaller, |
| 614 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 615 | { |
| 616 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 617 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 618 | MI_SEMAPHORE_COMPARE | |
| 619 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 620 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 621 | /* Throughout all of the GEM code, seqno passed implies our current |
| 622 | * seqno is >= the last seqno executed. However for hardware the |
| 623 | * comparison is strictly greater than. |
| 624 | */ |
| 625 | seqno -= 1; |
| 626 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 627 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 628 | MI_SEMAPHORE_SYNC_INVALID); |
| 629 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 630 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 631 | if (ret) |
| 632 | return ret; |
| 633 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 634 | intel_ring_emit(waiter, |
| 635 | dw1 | signaller->semaphore_register[waiter->id]); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 636 | intel_ring_emit(waiter, seqno); |
| 637 | intel_ring_emit(waiter, 0); |
| 638 | intel_ring_emit(waiter, MI_NOOP); |
| 639 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 640 | |
| 641 | return 0; |
| 642 | } |
| 643 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 644 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 645 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 646 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 647 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 648 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 649 | intel_ring_emit(ring__, 0); \ |
| 650 | intel_ring_emit(ring__, 0); \ |
| 651 | } while (0) |
| 652 | |
| 653 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 654 | pc_render_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 655 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 656 | struct pipe_control *pc = ring->private; |
| 657 | u32 scratch_addr = pc->gtt_offset + 128; |
| 658 | int ret; |
| 659 | |
| 660 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 661 | * incoherent with writes to memory, i.e. completely fubar, |
| 662 | * so we need to use PIPE_NOTIFY instead. |
| 663 | * |
| 664 | * However, we also need to workaround the qword write |
| 665 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 666 | * memory before requesting an interrupt. |
| 667 | */ |
| 668 | ret = intel_ring_begin(ring, 32); |
| 669 | if (ret) |
| 670 | return ret; |
| 671 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 672 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 673 | PIPE_CONTROL_WRITE_FLUSH | |
| 674 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 675 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 676 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 677 | intel_ring_emit(ring, 0); |
| 678 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 679 | scratch_addr += 128; /* write to separate cachelines */ |
| 680 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 681 | scratch_addr += 128; |
| 682 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 683 | scratch_addr += 128; |
| 684 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 685 | scratch_addr += 128; |
| 686 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 687 | scratch_addr += 128; |
| 688 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 689 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 690 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 691 | PIPE_CONTROL_WRITE_FLUSH | |
| 692 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 693 | PIPE_CONTROL_NOTIFY); |
| 694 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 695 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 696 | intel_ring_emit(ring, 0); |
| 697 | intel_ring_advance(ring); |
| 698 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 699 | return 0; |
| 700 | } |
| 701 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 702 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 703 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 704 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 705 | /* Workaround to force correct ordering between irq and seqno writes on |
| 706 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 707 | * ACTHD) before reading the status page. */ |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 708 | if (!lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 709 | intel_ring_get_active_head(ring); |
| 710 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 711 | } |
| 712 | |
| 713 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 714 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 715 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 716 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 717 | } |
| 718 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 719 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 720 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 721 | { |
| 722 | struct pipe_control *pc = ring->private; |
| 723 | return pc->cpu_page[0]; |
| 724 | } |
| 725 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 726 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 727 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 728 | { |
| 729 | struct drm_device *dev = ring->dev; |
| 730 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 731 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 732 | |
| 733 | if (!dev->irq_enabled) |
| 734 | return false; |
| 735 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 736 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 737 | if (ring->irq_refcount++ == 0) { |
| 738 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 739 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 740 | POSTING_READ(GTIMR); |
| 741 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 742 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 743 | |
| 744 | return true; |
| 745 | } |
| 746 | |
| 747 | static void |
| 748 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 749 | { |
| 750 | struct drm_device *dev = ring->dev; |
| 751 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 752 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 753 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 754 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 755 | if (--ring->irq_refcount == 0) { |
| 756 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 757 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 758 | POSTING_READ(GTIMR); |
| 759 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 760 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 764 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 765 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 766 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 767 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 768 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 769 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 770 | if (!dev->irq_enabled) |
| 771 | return false; |
| 772 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 773 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 774 | if (ring->irq_refcount++ == 0) { |
| 775 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 776 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 777 | POSTING_READ(IMR); |
| 778 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 779 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 780 | |
| 781 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 782 | } |
| 783 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 784 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 785 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 786 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 787 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 788 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 789 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 790 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 791 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 792 | if (--ring->irq_refcount == 0) { |
| 793 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 794 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 795 | POSTING_READ(IMR); |
| 796 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 797 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 798 | } |
| 799 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 800 | static bool |
| 801 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 802 | { |
| 803 | struct drm_device *dev = ring->dev; |
| 804 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 805 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 806 | |
| 807 | if (!dev->irq_enabled) |
| 808 | return false; |
| 809 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 810 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 811 | if (ring->irq_refcount++ == 0) { |
| 812 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 813 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 814 | POSTING_READ16(IMR); |
| 815 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 816 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 817 | |
| 818 | return true; |
| 819 | } |
| 820 | |
| 821 | static void |
| 822 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 823 | { |
| 824 | struct drm_device *dev = ring->dev; |
| 825 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 826 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 827 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 828 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 829 | if (--ring->irq_refcount == 0) { |
| 830 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 831 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 832 | POSTING_READ16(IMR); |
| 833 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 834 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 835 | } |
| 836 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 837 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 838 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 839 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 840 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 841 | u32 mmio = 0; |
| 842 | |
| 843 | /* The ring status page addresses are no longer next to the rest of |
| 844 | * the ring registers as of gen7. |
| 845 | */ |
| 846 | if (IS_GEN7(dev)) { |
| 847 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 848 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 849 | mmio = RENDER_HWS_PGA_GEN7; |
| 850 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 851 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 852 | mmio = BLT_HWS_PGA_GEN7; |
| 853 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 854 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 855 | mmio = BSD_HWS_PGA_GEN7; |
| 856 | break; |
| 857 | } |
| 858 | } else if (IS_GEN6(ring->dev)) { |
| 859 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 860 | } else { |
| 861 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 862 | } |
| 863 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 864 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 865 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 866 | } |
| 867 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 868 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 869 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 870 | u32 invalidate_domains, |
| 871 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 872 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 873 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 874 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 875 | ret = intel_ring_begin(ring, 2); |
| 876 | if (ret) |
| 877 | return ret; |
| 878 | |
| 879 | intel_ring_emit(ring, MI_FLUSH); |
| 880 | intel_ring_emit(ring, MI_NOOP); |
| 881 | intel_ring_advance(ring); |
| 882 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 883 | } |
| 884 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 885 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 886 | i9xx_add_request(struct intel_ring_buffer *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 887 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 888 | int ret; |
| 889 | |
| 890 | ret = intel_ring_begin(ring, 4); |
| 891 | if (ret) |
| 892 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 893 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 894 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 895 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 896 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 897 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 898 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 899 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 900 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 901 | } |
| 902 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 903 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 904 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 905 | { |
| 906 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 907 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 908 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 909 | |
| 910 | if (!dev->irq_enabled) |
| 911 | return false; |
| 912 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 913 | /* It looks like we need to prevent the gt from suspending while waiting |
| 914 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 915 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 916 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 917 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 918 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 919 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 920 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 921 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
| 922 | GEN6_RENDER_L3_PARITY_ERROR)); |
| 923 | else |
| 924 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 925 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 926 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 927 | POSTING_READ(GTIMR); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 928 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 929 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 930 | |
| 931 | return true; |
| 932 | } |
| 933 | |
| 934 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 935 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 936 | { |
| 937 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 938 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 939 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 940 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 941 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 942 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 943 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 944 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 945 | else |
| 946 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 947 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 948 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 949 | POSTING_READ(GTIMR); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 950 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 951 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 952 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 953 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 954 | } |
| 955 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 956 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 957 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 958 | u32 offset, u32 length, |
| 959 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 960 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 961 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 962 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 963 | ret = intel_ring_begin(ring, 2); |
| 964 | if (ret) |
| 965 | return ret; |
| 966 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 967 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 968 | MI_BATCH_BUFFER_START | |
| 969 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 970 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 971 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 972 | intel_ring_advance(ring); |
| 973 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 974 | return 0; |
| 975 | } |
| 976 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 977 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 978 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 979 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 980 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 981 | u32 offset, u32 len, |
| 982 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 983 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 984 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 985 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 986 | if (flags & I915_DISPATCH_PINNED) { |
| 987 | ret = intel_ring_begin(ring, 4); |
| 988 | if (ret) |
| 989 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 990 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 991 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 992 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 993 | intel_ring_emit(ring, offset + len - 8); |
| 994 | intel_ring_emit(ring, MI_NOOP); |
| 995 | intel_ring_advance(ring); |
| 996 | } else { |
| 997 | struct drm_i915_gem_object *obj = ring->private; |
| 998 | u32 cs_offset = obj->gtt_offset; |
| 999 | |
| 1000 | if (len > I830_BATCH_LIMIT) |
| 1001 | return -ENOSPC; |
| 1002 | |
| 1003 | ret = intel_ring_begin(ring, 9+3); |
| 1004 | if (ret) |
| 1005 | return ret; |
| 1006 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1007 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1008 | * invalidation bug) ... */ |
| 1009 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1010 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1011 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1012 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1013 | intel_ring_emit(ring, 0); |
| 1014 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1015 | intel_ring_emit(ring, cs_offset); |
| 1016 | intel_ring_emit(ring, 0); |
| 1017 | intel_ring_emit(ring, 4096); |
| 1018 | intel_ring_emit(ring, offset); |
| 1019 | intel_ring_emit(ring, MI_FLUSH); |
| 1020 | |
| 1021 | /* ... and execute it. */ |
| 1022 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1023 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1024 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1025 | intel_ring_advance(ring); |
| 1026 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1027 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1028 | return 0; |
| 1029 | } |
| 1030 | |
| 1031 | static int |
| 1032 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1033 | u32 offset, u32 len, |
| 1034 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1035 | { |
| 1036 | int ret; |
| 1037 | |
| 1038 | ret = intel_ring_begin(ring, 2); |
| 1039 | if (ret) |
| 1040 | return ret; |
| 1041 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1042 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1043 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1044 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1045 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1046 | return 0; |
| 1047 | } |
| 1048 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1049 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1050 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1051 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1052 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1053 | obj = ring->status_page.obj; |
| 1054 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1055 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1056 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1057 | kunmap(sg_page(obj->pages->sgl)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1058 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1059 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1060 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1061 | } |
| 1062 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1063 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1064 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1065 | struct drm_device *dev = ring->dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1066 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1067 | int ret; |
| 1068 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1069 | obj = i915_gem_alloc_object(dev, 4096); |
| 1070 | if (obj == NULL) { |
| 1071 | DRM_ERROR("Failed to allocate status page\n"); |
| 1072 | ret = -ENOMEM; |
| 1073 | goto err; |
| 1074 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1075 | |
| 1076 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1077 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1078 | ret = i915_gem_object_pin(obj, 4096, true, false); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1079 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1080 | goto err_unref; |
| 1081 | } |
| 1082 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1083 | ring->status_page.gfx_addr = obj->gtt_offset; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1084 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1085 | if (ring->status_page.page_addr == NULL) { |
Ben Widawsky | 2e6c21e | 2012-07-12 23:16:12 -0700 | [diff] [blame] | 1086 | ret = -ENOMEM; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1087 | goto err_unpin; |
| 1088 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1089 | ring->status_page.obj = obj; |
| 1090 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1091 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1092 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1093 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1094 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1095 | |
| 1096 | return 0; |
| 1097 | |
| 1098 | err_unpin: |
| 1099 | i915_gem_object_unpin(obj); |
| 1100 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1101 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1102 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1103 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1104 | } |
| 1105 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1106 | static int init_phys_hws_pga(struct intel_ring_buffer *ring) |
| 1107 | { |
| 1108 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1109 | u32 addr; |
| 1110 | |
| 1111 | if (!dev_priv->status_page_dmah) { |
| 1112 | dev_priv->status_page_dmah = |
| 1113 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1114 | if (!dev_priv->status_page_dmah) |
| 1115 | return -ENOMEM; |
| 1116 | } |
| 1117 | |
| 1118 | addr = dev_priv->status_page_dmah->busaddr; |
| 1119 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 1120 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 1121 | I915_WRITE(HWS_PGA, addr); |
| 1122 | |
| 1123 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1124 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1125 | |
| 1126 | return 0; |
| 1127 | } |
| 1128 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1129 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1130 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1131 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1132 | struct drm_i915_gem_object *obj; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1133 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1134 | int ret; |
| 1135 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1136 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1137 | INIT_LIST_HEAD(&ring->active_list); |
| 1138 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1139 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1140 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1141 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1142 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1143 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1144 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1145 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1146 | if (ret) |
| 1147 | return ret; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1148 | } else { |
| 1149 | BUG_ON(ring->id != RCS); |
| 1150 | ret = init_phys_hws_pga(ring); |
| 1151 | if (ret) |
| 1152 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1153 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1154 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1155 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1156 | if (obj == NULL) { |
| 1157 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1158 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1159 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1160 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1161 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1162 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1163 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1164 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1165 | if (ret) |
| 1166 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1167 | |
Chris Wilson | 3eef891 | 2012-06-04 17:05:40 +0100 | [diff] [blame] | 1168 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1169 | if (ret) |
| 1170 | goto err_unpin; |
| 1171 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1172 | ring->virtual_start = |
| 1173 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, |
| 1174 | ring->size); |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1175 | if (ring->virtual_start == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1176 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1177 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1178 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1179 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1180 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1181 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1182 | if (ret) |
| 1183 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1184 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1185 | /* Workaround an erratum on the i830 which causes a hang if |
| 1186 | * the TAIL pointer points to within the last 2 cachelines |
| 1187 | * of the buffer. |
| 1188 | */ |
| 1189 | ring->effective_size = ring->size; |
Chris Wilson | 27c1cbd | 2012-04-09 13:59:46 +0100 | [diff] [blame] | 1190 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1191 | ring->effective_size -= 128; |
| 1192 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1193 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1194 | |
| 1195 | err_unmap: |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1196 | iounmap(ring->virtual_start); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1197 | err_unpin: |
| 1198 | i915_gem_object_unpin(obj); |
| 1199 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1200 | drm_gem_object_unreference(&obj->base); |
| 1201 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1202 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1203 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1204 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1205 | } |
| 1206 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1207 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1208 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1209 | struct drm_i915_private *dev_priv; |
| 1210 | int ret; |
| 1211 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1212 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1213 | return; |
| 1214 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1215 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1216 | dev_priv = ring->dev->dev_private; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1217 | ret = intel_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1218 | if (ret) |
| 1219 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1220 | ring->name, ret); |
| 1221 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1222 | I915_WRITE_CTL(ring, 0); |
| 1223 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1224 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1225 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1226 | i915_gem_object_unpin(ring->obj); |
| 1227 | drm_gem_object_unreference(&ring->obj->base); |
| 1228 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1229 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1230 | if (ring->cleanup) |
| 1231 | ring->cleanup(ring); |
| 1232 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1233 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1234 | } |
| 1235 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1236 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1237 | { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1238 | int ret; |
| 1239 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1240 | ret = i915_wait_seqno(ring, seqno); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1241 | if (!ret) |
| 1242 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1243 | |
| 1244 | return ret; |
| 1245 | } |
| 1246 | |
| 1247 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1248 | { |
| 1249 | struct drm_i915_gem_request *request; |
| 1250 | u32 seqno = 0; |
| 1251 | int ret; |
| 1252 | |
| 1253 | i915_gem_retire_requests_ring(ring); |
| 1254 | |
| 1255 | if (ring->last_retired_head != -1) { |
| 1256 | ring->head = ring->last_retired_head; |
| 1257 | ring->last_retired_head = -1; |
| 1258 | ring->space = ring_space(ring); |
| 1259 | if (ring->space >= n) |
| 1260 | return 0; |
| 1261 | } |
| 1262 | |
| 1263 | list_for_each_entry(request, &ring->request_list, list) { |
| 1264 | int space; |
| 1265 | |
| 1266 | if (request->tail == -1) |
| 1267 | continue; |
| 1268 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 1269 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1270 | if (space < 0) |
| 1271 | space += ring->size; |
| 1272 | if (space >= n) { |
| 1273 | seqno = request->seqno; |
| 1274 | break; |
| 1275 | } |
| 1276 | |
| 1277 | /* Consume this request in case we need more space than |
| 1278 | * is available and so need to prevent a race between |
| 1279 | * updating last_retired_head and direct reads of |
| 1280 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1281 | */ |
| 1282 | request->tail = -1; |
| 1283 | } |
| 1284 | |
| 1285 | if (seqno == 0) |
| 1286 | return -ENOSPC; |
| 1287 | |
| 1288 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1289 | if (ret) |
| 1290 | return ret; |
| 1291 | |
| 1292 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1293 | return -ENOSPC; |
| 1294 | |
| 1295 | ring->head = ring->last_retired_head; |
| 1296 | ring->last_retired_head = -1; |
| 1297 | ring->space = ring_space(ring); |
| 1298 | if (WARN_ON(ring->space < n)) |
| 1299 | return -ENOSPC; |
| 1300 | |
| 1301 | return 0; |
| 1302 | } |
| 1303 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1304 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1305 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1306 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1307 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1308 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1309 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1310 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1311 | ret = intel_ring_wait_request(ring, n); |
| 1312 | if (ret != -ENOSPC) |
| 1313 | return ret; |
| 1314 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1315 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1316 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1317 | * leaving it early runs the risk of corrupting GEM state (due |
| 1318 | * to running on almost untested codepaths). But on resume |
| 1319 | * timers don't work yet, so prevent a complete hang in that |
| 1320 | * case by choosing an insanely large timeout. */ |
| 1321 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1322 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1323 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1324 | ring->head = I915_READ_HEAD(ring); |
| 1325 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1326 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1327 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1328 | return 0; |
| 1329 | } |
| 1330 | |
| 1331 | if (dev->primary->master) { |
| 1332 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1333 | if (master_priv->sarea_priv) |
| 1334 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1335 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1336 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1337 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1338 | |
| 1339 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
| 1340 | if (ret) |
| 1341 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1342 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1343 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1344 | return -EBUSY; |
| 1345 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1346 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1347 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1348 | { |
| 1349 | uint32_t __iomem *virt; |
| 1350 | int rem = ring->size - ring->tail; |
| 1351 | |
| 1352 | if (ring->space < rem) { |
| 1353 | int ret = ring_wait_for_space(ring, rem); |
| 1354 | if (ret) |
| 1355 | return ret; |
| 1356 | } |
| 1357 | |
| 1358 | virt = ring->virtual_start + ring->tail; |
| 1359 | rem /= 4; |
| 1360 | while (rem--) |
| 1361 | iowrite32(MI_NOOP, virt++); |
| 1362 | |
| 1363 | ring->tail = 0; |
| 1364 | ring->space = ring_space(ring); |
| 1365 | |
| 1366 | return 0; |
| 1367 | } |
| 1368 | |
| 1369 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1370 | { |
| 1371 | u32 seqno; |
| 1372 | int ret; |
| 1373 | |
| 1374 | /* We need to add any requests required to flush the objects and ring */ |
| 1375 | if (ring->outstanding_lazy_request) { |
| 1376 | ret = i915_add_request(ring, NULL, NULL); |
| 1377 | if (ret) |
| 1378 | return ret; |
| 1379 | } |
| 1380 | |
| 1381 | /* Wait upon the last request to be completed */ |
| 1382 | if (list_empty(&ring->request_list)) |
| 1383 | return 0; |
| 1384 | |
| 1385 | seqno = list_entry(ring->request_list.prev, |
| 1386 | struct drm_i915_gem_request, |
| 1387 | list)->seqno; |
| 1388 | |
| 1389 | return i915_wait_seqno(ring, seqno); |
| 1390 | } |
| 1391 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1392 | static int |
| 1393 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1394 | { |
| 1395 | if (ring->outstanding_lazy_request) |
| 1396 | return 0; |
| 1397 | |
| 1398 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request); |
| 1399 | } |
| 1400 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1401 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1402 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1403 | { |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1404 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 1405 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1406 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1407 | |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1408 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
| 1409 | if (ret) |
| 1410 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1411 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1412 | /* Preallocate the olr before touching the ring */ |
| 1413 | ret = intel_ring_alloc_seqno(ring); |
| 1414 | if (ret) |
| 1415 | return ret; |
| 1416 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1417 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1418 | ret = intel_wrap_ring_buffer(ring); |
| 1419 | if (unlikely(ret)) |
| 1420 | return ret; |
| 1421 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1422 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1423 | if (unlikely(ring->space < n)) { |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1424 | ret = ring_wait_for_space(ring, n); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1425 | if (unlikely(ret)) |
| 1426 | return ret; |
| 1427 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1428 | |
| 1429 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1430 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1431 | } |
| 1432 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1433 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1434 | { |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1435 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1436 | |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1437 | ring->tail &= ring->size - 1; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 1438 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
| 1439 | return; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1440 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1441 | } |
| 1442 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1443 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1444 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1445 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1446 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1447 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1448 | |
| 1449 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1450 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1451 | /* Disable notification that the ring is IDLE. The GT |
| 1452 | * will then assume that it is busy and bring it out of rc6. |
| 1453 | */ |
| 1454 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1455 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1456 | |
| 1457 | /* Clear the context id. Here be magic! */ |
| 1458 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1459 | |
| 1460 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1461 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1462 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1463 | 50)) |
| 1464 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1465 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1466 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1467 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1468 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1469 | |
| 1470 | /* Let the ring send IDLE messages to the GT again, |
| 1471 | * and so let it sleep to conserve power when idle. |
| 1472 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1473 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1474 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1475 | } |
| 1476 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1477 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1478 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1479 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1480 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1481 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1482 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1483 | ret = intel_ring_begin(ring, 4); |
| 1484 | if (ret) |
| 1485 | return ret; |
| 1486 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1487 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1488 | /* |
| 1489 | * Bspec vol 1c.5 - video engine command streamer: |
| 1490 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1491 | * operation is complete. This bit is only valid when the |
| 1492 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1493 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1494 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1495 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1496 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1497 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1498 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1499 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1500 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1501 | intel_ring_advance(ring); |
| 1502 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1503 | } |
| 1504 | |
| 1505 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1506 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1507 | u32 offset, u32 len, |
| 1508 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1509 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1510 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1511 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1512 | ret = intel_ring_begin(ring, 2); |
| 1513 | if (ret) |
| 1514 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1515 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1516 | intel_ring_emit(ring, |
| 1517 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1518 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1519 | /* bit0-7 is the length on GEN6+ */ |
| 1520 | intel_ring_emit(ring, offset); |
| 1521 | intel_ring_advance(ring); |
| 1522 | |
| 1523 | return 0; |
| 1524 | } |
| 1525 | |
| 1526 | static int |
| 1527 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1528 | u32 offset, u32 len, |
| 1529 | unsigned flags) |
| 1530 | { |
| 1531 | int ret; |
| 1532 | |
| 1533 | ret = intel_ring_begin(ring, 2); |
| 1534 | if (ret) |
| 1535 | return ret; |
| 1536 | |
| 1537 | intel_ring_emit(ring, |
| 1538 | MI_BATCH_BUFFER_START | |
| 1539 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1540 | /* bit0-7 is the length on GEN6+ */ |
| 1541 | intel_ring_emit(ring, offset); |
| 1542 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1543 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1544 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1545 | } |
| 1546 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1547 | /* Blitter support (SandyBridge+) */ |
| 1548 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1549 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1550 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1551 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1552 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1553 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1554 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1555 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1556 | if (ret) |
| 1557 | return ret; |
| 1558 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1559 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1560 | /* |
| 1561 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1562 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1563 | * operation is complete. This bit is only valid when the |
| 1564 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1565 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1566 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1567 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 1568 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1569 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1570 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1571 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1572 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1573 | intel_ring_advance(ring); |
| 1574 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1575 | } |
| 1576 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1577 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1578 | { |
| 1579 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1580 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1581 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1582 | ring->name = "render ring"; |
| 1583 | ring->id = RCS; |
| 1584 | ring->mmio_base = RENDER_RING_BASE; |
| 1585 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1586 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1587 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 1588 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 1589 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 1590 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1591 | ring->irq_get = gen6_ring_get_irq; |
| 1592 | ring->irq_put = gen6_ring_put_irq; |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 1593 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1594 | ring->get_seqno = gen6_ring_get_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1595 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1596 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
| 1597 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; |
| 1598 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; |
| 1599 | ring->signal_mbox[0] = GEN6_VRSYNC; |
| 1600 | ring->signal_mbox[1] = GEN6_BRSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1601 | } else if (IS_GEN5(dev)) { |
| 1602 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1603 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1604 | ring->get_seqno = pc_render_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1605 | ring->irq_get = gen5_ring_get_irq; |
| 1606 | ring->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1607 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1608 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1609 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1610 | if (INTEL_INFO(dev)->gen < 4) |
| 1611 | ring->flush = gen2_render_ring_flush; |
| 1612 | else |
| 1613 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1614 | ring->get_seqno = ring_get_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1615 | if (IS_GEN2(dev)) { |
| 1616 | ring->irq_get = i8xx_ring_get_irq; |
| 1617 | ring->irq_put = i8xx_ring_put_irq; |
| 1618 | } else { |
| 1619 | ring->irq_get = i9xx_ring_get_irq; |
| 1620 | ring->irq_put = i9xx_ring_put_irq; |
| 1621 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1622 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1623 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1624 | ring->write_tail = ring_write_tail; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1625 | if (IS_HASWELL(dev)) |
| 1626 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
| 1627 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1628 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1629 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1630 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1631 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1632 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1633 | else |
| 1634 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1635 | ring->init = init_render_ring; |
| 1636 | ring->cleanup = render_ring_cleanup; |
| 1637 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 1638 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1639 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1640 | struct drm_i915_gem_object *obj; |
| 1641 | int ret; |
| 1642 | |
| 1643 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1644 | if (obj == NULL) { |
| 1645 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1646 | return -ENOMEM; |
| 1647 | } |
| 1648 | |
| 1649 | ret = i915_gem_object_pin(obj, 0, true, false); |
| 1650 | if (ret != 0) { |
| 1651 | drm_gem_object_unreference(&obj->base); |
| 1652 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1653 | return ret; |
| 1654 | } |
| 1655 | |
| 1656 | ring->private = obj; |
| 1657 | } |
| 1658 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1659 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1660 | } |
| 1661 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1662 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1663 | { |
| 1664 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1665 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1666 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1667 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1668 | ring->name = "render ring"; |
| 1669 | ring->id = RCS; |
| 1670 | ring->mmio_base = RENDER_RING_BASE; |
| 1671 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1672 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 1673 | /* non-kms not supported on gen6+ */ |
| 1674 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1675 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1676 | |
| 1677 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 1678 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 1679 | * the special gen5 functions. */ |
| 1680 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1681 | if (INTEL_INFO(dev)->gen < 4) |
| 1682 | ring->flush = gen2_render_ring_flush; |
| 1683 | else |
| 1684 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1685 | ring->get_seqno = ring_get_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1686 | if (IS_GEN2(dev)) { |
| 1687 | ring->irq_get = i8xx_ring_get_irq; |
| 1688 | ring->irq_put = i8xx_ring_put_irq; |
| 1689 | } else { |
| 1690 | ring->irq_get = i9xx_ring_get_irq; |
| 1691 | ring->irq_put = i9xx_ring_put_irq; |
| 1692 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1693 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1694 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1695 | if (INTEL_INFO(dev)->gen >= 4) |
| 1696 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1697 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1698 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1699 | else |
| 1700 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1701 | ring->init = init_render_ring; |
| 1702 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1703 | |
| 1704 | ring->dev = dev; |
| 1705 | INIT_LIST_HEAD(&ring->active_list); |
| 1706 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1707 | |
| 1708 | ring->size = size; |
| 1709 | ring->effective_size = ring->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 1710 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1711 | ring->effective_size -= 128; |
| 1712 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1713 | ring->virtual_start = ioremap_wc(start, size); |
| 1714 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1715 | DRM_ERROR("can not ioremap virtual address for" |
| 1716 | " ring buffer\n"); |
| 1717 | return -ENOMEM; |
| 1718 | } |
| 1719 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1720 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1721 | ret = init_phys_hws_pga(ring); |
| 1722 | if (ret) |
| 1723 | return ret; |
| 1724 | } |
| 1725 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1726 | return 0; |
| 1727 | } |
| 1728 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1729 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1730 | { |
| 1731 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1732 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1733 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1734 | ring->name = "bsd ring"; |
| 1735 | ring->id = VCS; |
| 1736 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1737 | ring->write_tail = ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1738 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1739 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1740 | /* gen6 bsd needs a special wa for tail updates */ |
| 1741 | if (IS_GEN6(dev)) |
| 1742 | ring->write_tail = gen6_bsd_ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1743 | ring->flush = gen6_ring_flush; |
| 1744 | ring->add_request = gen6_add_request; |
| 1745 | ring->get_seqno = gen6_ring_get_seqno; |
| 1746 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; |
| 1747 | ring->irq_get = gen6_ring_get_irq; |
| 1748 | ring->irq_put = gen6_ring_put_irq; |
| 1749 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1750 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1751 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
| 1752 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; |
| 1753 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; |
| 1754 | ring->signal_mbox[0] = GEN6_RVSYNC; |
| 1755 | ring->signal_mbox[1] = GEN6_BVSYNC; |
| 1756 | } else { |
| 1757 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1758 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1759 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1760 | ring->get_seqno = ring_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1761 | if (IS_GEN5(dev)) { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1762 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1763 | ring->irq_get = gen5_ring_get_irq; |
| 1764 | ring->irq_put = gen5_ring_put_irq; |
| 1765 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1766 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1767 | ring->irq_get = i9xx_ring_get_irq; |
| 1768 | ring->irq_put = i9xx_ring_put_irq; |
| 1769 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1770 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1771 | } |
| 1772 | ring->init = init_ring_common; |
| 1773 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1774 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1775 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1776 | |
| 1777 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1778 | { |
| 1779 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1780 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1781 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1782 | ring->name = "blitter ring"; |
| 1783 | ring->id = BCS; |
| 1784 | |
| 1785 | ring->mmio_base = BLT_RING_BASE; |
| 1786 | ring->write_tail = ring_write_tail; |
| 1787 | ring->flush = blt_ring_flush; |
| 1788 | ring->add_request = gen6_add_request; |
| 1789 | ring->get_seqno = gen6_ring_get_seqno; |
| 1790 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; |
| 1791 | ring->irq_get = gen6_ring_get_irq; |
| 1792 | ring->irq_put = gen6_ring_put_irq; |
| 1793 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1794 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1795 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
| 1796 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; |
| 1797 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; |
| 1798 | ring->signal_mbox[0] = GEN6_RBSYNC; |
| 1799 | ring->signal_mbox[1] = GEN6_VBSYNC; |
| 1800 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1801 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1802 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1803 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1804 | |
| 1805 | int |
| 1806 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 1807 | { |
| 1808 | int ret; |
| 1809 | |
| 1810 | if (!ring->gpu_caches_dirty) |
| 1811 | return 0; |
| 1812 | |
| 1813 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1814 | if (ret) |
| 1815 | return ret; |
| 1816 | |
| 1817 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1818 | |
| 1819 | ring->gpu_caches_dirty = false; |
| 1820 | return 0; |
| 1821 | } |
| 1822 | |
| 1823 | int |
| 1824 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 1825 | { |
| 1826 | uint32_t flush_domains; |
| 1827 | int ret; |
| 1828 | |
| 1829 | flush_domains = 0; |
| 1830 | if (ring->gpu_caches_dirty) |
| 1831 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 1832 | |
| 1833 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1834 | if (ret) |
| 1835 | return ret; |
| 1836 | |
| 1837 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1838 | |
| 1839 | ring->gpu_caches_dirty = false; |
| 1840 | return 0; |
| 1841 | } |