Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 40 | |
| 41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 42 | bool pipelined); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 52 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 54 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 57 | struct drm_i915_gem_pwrite *args, |
| 58 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 60 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 61 | static int |
| 62 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 63 | gfp_t gfpmask); |
| 64 | |
| 65 | static void |
| 66 | i915_gem_object_put_pages(struct drm_gem_object *obj); |
| 67 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 68 | static LIST_HEAD(shrink_list); |
| 69 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
| 87 | size_t size) |
| 88 | { |
| 89 | dev_priv->mm.gtt_count++; |
| 90 | dev_priv->mm.gtt_memory += size; |
| 91 | } |
| 92 | |
| 93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
| 94 | size_t size) |
| 95 | { |
| 96 | dev_priv->mm.gtt_count--; |
| 97 | dev_priv->mm.gtt_memory -= size; |
| 98 | } |
| 99 | |
| 100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
| 101 | size_t size) |
| 102 | { |
| 103 | dev_priv->mm.pin_count++; |
| 104 | dev_priv->mm.pin_memory += size; |
| 105 | } |
| 106 | |
| 107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
| 108 | size_t size) |
| 109 | { |
| 110 | dev_priv->mm.pin_count--; |
| 111 | dev_priv->mm.pin_memory -= size; |
| 112 | } |
| 113 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | int |
| 115 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 116 | { |
| 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 118 | struct completion *x = &dev_priv->error_completion; |
| 119 | unsigned long flags; |
| 120 | int ret; |
| 121 | |
| 122 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 123 | return 0; |
| 124 | |
| 125 | ret = wait_for_completion_interruptible(x); |
| 126 | if (ret) |
| 127 | return ret; |
| 128 | |
| 129 | /* Success, we reset the GPU! */ |
| 130 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 131 | return 0; |
| 132 | |
| 133 | /* GPU is hung, bump the completion count to account for |
| 134 | * the token we just consumed so that we never hit zero and |
| 135 | * end up waiting upon a subsequent completion event that |
| 136 | * will never happen. |
| 137 | */ |
| 138 | spin_lock_irqsave(&x->wait.lock, flags); |
| 139 | x->done++; |
| 140 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 141 | return -EIO; |
| 142 | } |
| 143 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 145 | { |
| 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 147 | int ret; |
| 148 | |
| 149 | ret = i915_gem_check_is_wedged(dev); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 154 | if (ret) |
| 155 | return ret; |
| 156 | |
| 157 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 158 | mutex_unlock(&dev->struct_mutex); |
| 159 | return -EAGAIN; |
| 160 | } |
| 161 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 162 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 163 | return 0; |
| 164 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 165 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 166 | static inline bool |
| 167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 168 | { |
| 169 | return obj_priv->gtt_space && |
| 170 | !obj_priv->active && |
| 171 | obj_priv->pin_count == 0; |
| 172 | } |
| 173 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 174 | int i915_gem_do_init(struct drm_device *dev, |
| 175 | unsigned long start, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 176 | unsigned long end) |
| 177 | { |
| 178 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 179 | |
| 180 | if (start >= end || |
| 181 | (start & (PAGE_SIZE - 1)) != 0 || |
| 182 | (end & (PAGE_SIZE - 1)) != 0) { |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | |
| 186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 187 | end - start); |
| 188 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 189 | dev_priv->mm.gtt_total = end - start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 190 | |
| 191 | return 0; |
| 192 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 194 | int |
| 195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 196 | struct drm_file *file_priv) |
| 197 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 198 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 199 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 200 | |
| 201 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 203 | mutex_unlock(&dev->struct_mutex); |
| 204 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 205 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 206 | } |
| 207 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 208 | int |
| 209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 210 | struct drm_file *file_priv) |
| 211 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 213 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 214 | |
| 215 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 216 | return -ENODEV; |
| 217 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 218 | mutex_lock(&dev->struct_mutex); |
| 219 | args->aper_size = dev_priv->mm.gtt_total; |
| 220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 221 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 226 | |
| 227 | /** |
| 228 | * Creates a new mm object and returns a handle to it. |
| 229 | */ |
| 230 | int |
| 231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 232 | struct drm_file *file_priv) |
| 233 | { |
| 234 | struct drm_i915_gem_create *args = data; |
| 235 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 236 | int ret; |
| 237 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 238 | |
| 239 | args->size = roundup(args->size, PAGE_SIZE); |
| 240 | |
| 241 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 242 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 243 | if (obj == NULL) |
| 244 | return -ENOMEM; |
| 245 | |
| 246 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 247 | if (ret) { |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 248 | drm_gem_object_release(obj); |
| 249 | i915_gem_info_remove_obj(dev->dev_private, obj->size); |
| 250 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 251 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 252 | } |
| 253 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 254 | /* drop reference from allocate - handle holds it now */ |
| 255 | drm_gem_object_unreference(obj); |
| 256 | trace_i915_gem_object_create(obj); |
| 257 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 259 | return 0; |
| 260 | } |
| 261 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 262 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 263 | fast_shmem_read(struct page **pages, |
| 264 | loff_t page_base, int page_offset, |
| 265 | char __user *data, |
| 266 | int length) |
| 267 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 268 | char *vaddr; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 269 | int ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 270 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 271 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 272 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 273 | kunmap_atomic(vaddr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 274 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 275 | return ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 276 | } |
| 277 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 279 | { |
| 280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 282 | |
| 283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 284 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 285 | } |
| 286 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 287 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 288 | slow_shmem_copy(struct page *dst_page, |
| 289 | int dst_offset, |
| 290 | struct page *src_page, |
| 291 | int src_offset, |
| 292 | int length) |
| 293 | { |
| 294 | char *dst_vaddr, *src_vaddr; |
| 295 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 296 | dst_vaddr = kmap(dst_page); |
| 297 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 298 | |
| 299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 300 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 301 | kunmap(src_page); |
| 302 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 303 | } |
| 304 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 305 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 306 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 307 | int gpu_offset, |
| 308 | struct page *cpu_page, |
| 309 | int cpu_offset, |
| 310 | int length, |
| 311 | int is_read) |
| 312 | { |
| 313 | char *gpu_vaddr, *cpu_vaddr; |
| 314 | |
| 315 | /* Use the unswizzled path if this page isn't affected. */ |
| 316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 317 | if (is_read) |
| 318 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 319 | gpu_page, gpu_offset, length); |
| 320 | else |
| 321 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 322 | cpu_page, cpu_offset, length); |
| 323 | } |
| 324 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 325 | gpu_vaddr = kmap(gpu_page); |
| 326 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 327 | |
| 328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 330 | */ |
| 331 | while (length > 0) { |
| 332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 333 | int this_length = min(cacheline_end - gpu_offset, length); |
| 334 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 335 | |
| 336 | if (is_read) { |
| 337 | memcpy(cpu_vaddr + cpu_offset, |
| 338 | gpu_vaddr + swizzled_gpu_offset, |
| 339 | this_length); |
| 340 | } else { |
| 341 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 342 | cpu_vaddr + cpu_offset, |
| 343 | this_length); |
| 344 | } |
| 345 | cpu_offset += this_length; |
| 346 | gpu_offset += this_length; |
| 347 | length -= this_length; |
| 348 | } |
| 349 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 350 | kunmap(cpu_page); |
| 351 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 352 | } |
| 353 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 354 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 355 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 356 | * from the backing pages of the object to the user's address space. On a |
| 357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 358 | */ |
| 359 | static int |
| 360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 361 | struct drm_i915_gem_pread *args, |
| 362 | struct drm_file *file_priv) |
| 363 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 365 | ssize_t remain; |
| 366 | loff_t offset, page_base; |
| 367 | char __user *user_data; |
| 368 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 369 | |
| 370 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 371 | remain = args->size; |
| 372 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 373 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 374 | offset = args->offset; |
| 375 | |
| 376 | while (remain > 0) { |
| 377 | /* Operation in this page |
| 378 | * |
| 379 | * page_base = page offset within aperture |
| 380 | * page_offset = offset within page |
| 381 | * page_length = bytes to copy for this page |
| 382 | */ |
| 383 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 384 | page_offset = offset & (PAGE_SIZE-1); |
| 385 | page_length = remain; |
| 386 | if ((page_offset + remain) > PAGE_SIZE) |
| 387 | page_length = PAGE_SIZE - page_offset; |
| 388 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 389 | if (fast_shmem_read(obj_priv->pages, |
| 390 | page_base, page_offset, |
| 391 | user_data, page_length)) |
| 392 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 393 | |
| 394 | remain -= page_length; |
| 395 | user_data += page_length; |
| 396 | offset += page_length; |
| 397 | } |
| 398 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 399 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | } |
| 401 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 402 | static int |
| 403 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 404 | { |
| 405 | int ret; |
| 406 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 407 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 408 | |
| 409 | /* If we've insufficient memory to map in the pages, attempt |
| 410 | * to make some space by throwing out some old buffers. |
| 411 | */ |
| 412 | if (ret == -ENOMEM) { |
| 413 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 414 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 415 | ret = i915_gem_evict_something(dev, obj->size, |
| 416 | i915_gem_get_gtt_alignment(obj)); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 417 | if (ret) |
| 418 | return ret; |
| 419 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 420 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | return ret; |
| 424 | } |
| 425 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | /** |
| 427 | * This is the fallback shmem pread path, which allocates temporary storage |
| 428 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 429 | * can copy out of the object's backing pages while holding the struct mutex |
| 430 | * and not take page faults. |
| 431 | */ |
| 432 | static int |
| 433 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 434 | struct drm_i915_gem_pread *args, |
| 435 | struct drm_file *file_priv) |
| 436 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 437 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 438 | struct mm_struct *mm = current->mm; |
| 439 | struct page **user_pages; |
| 440 | ssize_t remain; |
| 441 | loff_t offset, pinned_pages, i; |
| 442 | loff_t first_data_page, last_data_page, num_pages; |
| 443 | int shmem_page_index, shmem_page_offset; |
| 444 | int data_page_index, data_page_offset; |
| 445 | int page_length; |
| 446 | int ret; |
| 447 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 448 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 449 | |
| 450 | remain = args->size; |
| 451 | |
| 452 | /* Pin the user pages containing the data. We can't fault while |
| 453 | * holding the struct mutex, yet we want to hold it while |
| 454 | * dereferencing the user data. |
| 455 | */ |
| 456 | first_data_page = data_ptr / PAGE_SIZE; |
| 457 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 458 | num_pages = last_data_page - first_data_page + 1; |
| 459 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 460 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 461 | if (user_pages == NULL) |
| 462 | return -ENOMEM; |
| 463 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 464 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | down_read(&mm->mmap_sem); |
| 466 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 467 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 468 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 469 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 470 | if (pinned_pages < num_pages) { |
| 471 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 472 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 473 | } |
| 474 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 475 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 476 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 477 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 478 | if (ret) |
| 479 | goto out; |
| 480 | |
| 481 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 482 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 483 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 484 | offset = args->offset; |
| 485 | |
| 486 | while (remain > 0) { |
| 487 | /* Operation in this page |
| 488 | * |
| 489 | * shmem_page_index = page number within shmem file |
| 490 | * shmem_page_offset = offset within page in shmem file |
| 491 | * data_page_index = page number in get_user_pages return |
| 492 | * data_page_offset = offset with data_page_index page. |
| 493 | * page_length = bytes to copy for this page |
| 494 | */ |
| 495 | shmem_page_index = offset / PAGE_SIZE; |
| 496 | shmem_page_offset = offset & ~PAGE_MASK; |
| 497 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 498 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 499 | |
| 500 | page_length = remain; |
| 501 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 502 | page_length = PAGE_SIZE - shmem_page_offset; |
| 503 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 504 | page_length = PAGE_SIZE - data_page_offset; |
| 505 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 506 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 507 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 508 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 509 | user_pages[data_page_index], |
| 510 | data_page_offset, |
| 511 | page_length, |
| 512 | 1); |
| 513 | } else { |
| 514 | slow_shmem_copy(user_pages[data_page_index], |
| 515 | data_page_offset, |
| 516 | obj_priv->pages[shmem_page_index], |
| 517 | shmem_page_offset, |
| 518 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 519 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 520 | |
| 521 | remain -= page_length; |
| 522 | data_ptr += page_length; |
| 523 | offset += page_length; |
| 524 | } |
| 525 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 526 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 527 | for (i = 0; i < pinned_pages; i++) { |
| 528 | SetPageDirty(user_pages[i]); |
| 529 | page_cache_release(user_pages[i]); |
| 530 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 531 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 532 | |
| 533 | return ret; |
| 534 | } |
| 535 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 536 | /** |
| 537 | * Reads data from the object referenced by handle. |
| 538 | * |
| 539 | * On error, the contents of *data are undefined. |
| 540 | */ |
| 541 | int |
| 542 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 543 | struct drm_file *file_priv) |
| 544 | { |
| 545 | struct drm_i915_gem_pread *args = data; |
| 546 | struct drm_gem_object *obj; |
| 547 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 548 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 549 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 550 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 551 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 552 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 553 | |
| 554 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 555 | if (obj == NULL) { |
| 556 | ret = -ENOENT; |
| 557 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 558 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 559 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 560 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 561 | /* Bounds check source. */ |
| 562 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 563 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 564 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 565 | } |
| 566 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 567 | if (args->size == 0) |
| 568 | goto out; |
| 569 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 570 | if (!access_ok(VERIFY_WRITE, |
| 571 | (char __user *)(uintptr_t)args->data_ptr, |
| 572 | args->size)) { |
| 573 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 574 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 575 | } |
| 576 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 577 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 578 | args->size); |
| 579 | if (ret) { |
| 580 | ret = -EFAULT; |
| 581 | goto out; |
| 582 | } |
| 583 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 584 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 585 | if (ret) |
| 586 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 588 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 589 | args->offset, |
| 590 | args->size); |
| 591 | if (ret) |
| 592 | goto out_put; |
| 593 | |
| 594 | ret = -EFAULT; |
| 595 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 596 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 597 | if (ret == -EFAULT) |
| 598 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 600 | out_put: |
| 601 | i915_gem_object_put_pages(obj); |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 602 | out: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 603 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 604 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 605 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 606 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 607 | } |
| 608 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 609 | /* This is the fast write path which cannot handle |
| 610 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 611 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 612 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 613 | static inline int |
| 614 | fast_user_write(struct io_mapping *mapping, |
| 615 | loff_t page_base, int page_offset, |
| 616 | char __user *user_data, |
| 617 | int length) |
| 618 | { |
| 619 | char *vaddr_atomic; |
| 620 | unsigned long unwritten; |
| 621 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 622 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 623 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 624 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 625 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 626 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | /* Here's the write path which can sleep for |
| 630 | * page faults |
| 631 | */ |
| 632 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 633 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 634 | slow_kernel_write(struct io_mapping *mapping, |
| 635 | loff_t gtt_base, int gtt_offset, |
| 636 | struct page *user_page, int user_offset, |
| 637 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 638 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 639 | char __iomem *dst_vaddr; |
| 640 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 641 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 642 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 643 | src_vaddr = kmap(user_page); |
| 644 | |
| 645 | memcpy_toio(dst_vaddr + gtt_offset, |
| 646 | src_vaddr + user_offset, |
| 647 | length); |
| 648 | |
| 649 | kunmap(user_page); |
| 650 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 651 | } |
| 652 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 653 | static inline int |
| 654 | fast_shmem_write(struct page **pages, |
| 655 | loff_t page_base, int page_offset, |
| 656 | char __user *data, |
| 657 | int length) |
| 658 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 659 | char *vaddr; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 660 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 661 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 662 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 663 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 664 | kunmap_atomic(vaddr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 665 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 666 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 667 | } |
| 668 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 669 | /** |
| 670 | * This is the fast pwrite path, where we copy the data directly from the |
| 671 | * user into the GTT, uncached. |
| 672 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 673 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 674 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 675 | struct drm_i915_gem_pwrite *args, |
| 676 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 677 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 678 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 679 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 680 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 681 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 682 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 683 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 684 | |
| 685 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 686 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 687 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 688 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 689 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 690 | |
| 691 | while (remain > 0) { |
| 692 | /* Operation in this page |
| 693 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 694 | * page_base = page offset within aperture |
| 695 | * page_offset = offset within page |
| 696 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 698 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 699 | page_offset = offset & (PAGE_SIZE-1); |
| 700 | page_length = remain; |
| 701 | if ((page_offset + remain) > PAGE_SIZE) |
| 702 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 704 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 705 | * source page isn't available. Return the error and we'll |
| 706 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 707 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 709 | page_offset, user_data, page_length)) |
| 710 | |
| 711 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 713 | remain -= page_length; |
| 714 | user_data += page_length; |
| 715 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 716 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 717 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 718 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 721 | /** |
| 722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 723 | * the memory and maps it using kmap_atomic for copying. |
| 724 | * |
| 725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 727 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 728 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 730 | struct drm_i915_gem_pwrite *args, |
| 731 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 732 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 733 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 734 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 735 | ssize_t remain; |
| 736 | loff_t gtt_page_base, offset; |
| 737 | loff_t first_data_page, last_data_page, num_pages; |
| 738 | loff_t pinned_pages, i; |
| 739 | struct page **user_pages; |
| 740 | struct mm_struct *mm = current->mm; |
| 741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 743 | uint64_t data_ptr = args->data_ptr; |
| 744 | |
| 745 | remain = args->size; |
| 746 | |
| 747 | /* Pin the user pages containing the data. We can't fault while |
| 748 | * holding the struct mutex, and all of the pwrite implementations |
| 749 | * want to hold it while dereferencing the user data. |
| 750 | */ |
| 751 | first_data_page = data_ptr / PAGE_SIZE; |
| 752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 753 | num_pages = last_data_page - first_data_page + 1; |
| 754 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 756 | if (user_pages == NULL) |
| 757 | return -ENOMEM; |
| 758 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 759 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 760 | down_read(&mm->mmap_sem); |
| 761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 762 | num_pages, 0, 0, user_pages, NULL); |
| 763 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 764 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 765 | if (pinned_pages < num_pages) { |
| 766 | ret = -EFAULT; |
| 767 | goto out_unpin_pages; |
| 768 | } |
| 769 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 771 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 772 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 773 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 774 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 775 | offset = obj_priv->gtt_offset + args->offset; |
| 776 | |
| 777 | while (remain > 0) { |
| 778 | /* Operation in this page |
| 779 | * |
| 780 | * gtt_page_base = page offset within aperture |
| 781 | * gtt_page_offset = offset within page in aperture |
| 782 | * data_page_index = page number in get_user_pages return |
| 783 | * data_page_offset = offset with data_page_index page. |
| 784 | * page_length = bytes to copy for this page |
| 785 | */ |
| 786 | gtt_page_base = offset & PAGE_MASK; |
| 787 | gtt_page_offset = offset & ~PAGE_MASK; |
| 788 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 789 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 790 | |
| 791 | page_length = remain; |
| 792 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 793 | page_length = PAGE_SIZE - gtt_page_offset; |
| 794 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 795 | page_length = PAGE_SIZE - data_page_offset; |
| 796 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 797 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 798 | gtt_page_base, gtt_page_offset, |
| 799 | user_pages[data_page_index], |
| 800 | data_page_offset, |
| 801 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 802 | |
| 803 | remain -= page_length; |
| 804 | offset += page_length; |
| 805 | data_ptr += page_length; |
| 806 | } |
| 807 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 808 | out_unpin_pages: |
| 809 | for (i = 0; i < pinned_pages; i++) |
| 810 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 811 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 812 | |
| 813 | return ret; |
| 814 | } |
| 815 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | /** |
| 817 | * This is the fast shmem pwrite path, which attempts to directly |
| 818 | * copy_from_user into the kmapped pages backing the object. |
| 819 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 820 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 821 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 822 | struct drm_i915_gem_pwrite *args, |
| 823 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 824 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 825 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | ssize_t remain; |
| 827 | loff_t offset, page_base; |
| 828 | char __user *user_data; |
| 829 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 830 | |
| 831 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 832 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 834 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 835 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 836 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 837 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 838 | while (remain > 0) { |
| 839 | /* Operation in this page |
| 840 | * |
| 841 | * page_base = page offset within aperture |
| 842 | * page_offset = offset within page |
| 843 | * page_length = bytes to copy for this page |
| 844 | */ |
| 845 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 846 | page_offset = offset & (PAGE_SIZE-1); |
| 847 | page_length = remain; |
| 848 | if ((page_offset + remain) > PAGE_SIZE) |
| 849 | page_length = PAGE_SIZE - page_offset; |
| 850 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 851 | if (fast_shmem_write(obj_priv->pages, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 852 | page_base, page_offset, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 853 | user_data, page_length)) |
| 854 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 855 | |
| 856 | remain -= page_length; |
| 857 | user_data += page_length; |
| 858 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 859 | } |
| 860 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 861 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | /** |
| 865 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 866 | * the memory and maps it using kmap_atomic for copying. |
| 867 | * |
| 868 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 869 | * struct_mutex is held. |
| 870 | */ |
| 871 | static int |
| 872 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 873 | struct drm_i915_gem_pwrite *args, |
| 874 | struct drm_file *file_priv) |
| 875 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 876 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 877 | struct mm_struct *mm = current->mm; |
| 878 | struct page **user_pages; |
| 879 | ssize_t remain; |
| 880 | loff_t offset, pinned_pages, i; |
| 881 | loff_t first_data_page, last_data_page, num_pages; |
| 882 | int shmem_page_index, shmem_page_offset; |
| 883 | int data_page_index, data_page_offset; |
| 884 | int page_length; |
| 885 | int ret; |
| 886 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 887 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 888 | |
| 889 | remain = args->size; |
| 890 | |
| 891 | /* Pin the user pages containing the data. We can't fault while |
| 892 | * holding the struct mutex, and all of the pwrite implementations |
| 893 | * want to hold it while dereferencing the user data. |
| 894 | */ |
| 895 | first_data_page = data_ptr / PAGE_SIZE; |
| 896 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 897 | num_pages = last_data_page - first_data_page + 1; |
| 898 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 899 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 900 | if (user_pages == NULL) |
| 901 | return -ENOMEM; |
| 902 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 903 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 904 | down_read(&mm->mmap_sem); |
| 905 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 906 | num_pages, 0, 0, user_pages, NULL); |
| 907 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 908 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 909 | if (pinned_pages < num_pages) { |
| 910 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 911 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 912 | } |
| 913 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 914 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 915 | if (ret) |
| 916 | goto out; |
| 917 | |
| 918 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 919 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 920 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 921 | offset = args->offset; |
| 922 | obj_priv->dirty = 1; |
| 923 | |
| 924 | while (remain > 0) { |
| 925 | /* Operation in this page |
| 926 | * |
| 927 | * shmem_page_index = page number within shmem file |
| 928 | * shmem_page_offset = offset within page in shmem file |
| 929 | * data_page_index = page number in get_user_pages return |
| 930 | * data_page_offset = offset with data_page_index page. |
| 931 | * page_length = bytes to copy for this page |
| 932 | */ |
| 933 | shmem_page_index = offset / PAGE_SIZE; |
| 934 | shmem_page_offset = offset & ~PAGE_MASK; |
| 935 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 936 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 937 | |
| 938 | page_length = remain; |
| 939 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 940 | page_length = PAGE_SIZE - shmem_page_offset; |
| 941 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 942 | page_length = PAGE_SIZE - data_page_offset; |
| 943 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 944 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 945 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 946 | shmem_page_offset, |
| 947 | user_pages[data_page_index], |
| 948 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 949 | page_length, |
| 950 | 0); |
| 951 | } else { |
| 952 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 953 | shmem_page_offset, |
| 954 | user_pages[data_page_index], |
| 955 | data_page_offset, |
| 956 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 957 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 958 | |
| 959 | remain -= page_length; |
| 960 | data_ptr += page_length; |
| 961 | offset += page_length; |
| 962 | } |
| 963 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 964 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 965 | for (i = 0; i < pinned_pages; i++) |
| 966 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 967 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 968 | |
| 969 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 970 | } |
| 971 | |
| 972 | /** |
| 973 | * Writes data to the object referenced by handle. |
| 974 | * |
| 975 | * On error, the contents of the buffer that were to be modified are undefined. |
| 976 | */ |
| 977 | int |
| 978 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 979 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | { |
| 981 | struct drm_i915_gem_pwrite *args = data; |
| 982 | struct drm_gem_object *obj; |
| 983 | struct drm_i915_gem_object *obj_priv; |
| 984 | int ret = 0; |
| 985 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 986 | ret = i915_mutex_lock_interruptible(dev); |
| 987 | if (ret) |
| 988 | return ret; |
| 989 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 990 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 991 | if (obj == NULL) { |
| 992 | ret = -ENOENT; |
| 993 | goto unlock; |
| 994 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 995 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 996 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 997 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 998 | /* Bounds check destination. */ |
| 999 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1000 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1001 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1002 | } |
| 1003 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1004 | if (args->size == 0) |
| 1005 | goto out; |
| 1006 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1007 | if (!access_ok(VERIFY_READ, |
| 1008 | (char __user *)(uintptr_t)args->data_ptr, |
| 1009 | args->size)) { |
| 1010 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1011 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | } |
| 1013 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 1014 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1015 | args->size); |
| 1016 | if (ret) { |
| 1017 | ret = -EFAULT; |
| 1018 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1019 | } |
| 1020 | |
| 1021 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1022 | * it would end up going through the fenced access, and we'll get |
| 1023 | * different detiling behavior between reading and writing. |
| 1024 | * pread/pwrite currently are reading and writing from the CPU |
| 1025 | * perspective, requiring manual detiling by the client. |
| 1026 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1027 | if (obj_priv->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1028 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1029 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1030 | obj_priv->gtt_space && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 1031 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1032 | ret = i915_gem_object_pin(obj, 0); |
| 1033 | if (ret) |
| 1034 | goto out; |
| 1035 | |
| 1036 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1037 | if (ret) |
| 1038 | goto out_unpin; |
| 1039 | |
| 1040 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1041 | if (ret == -EFAULT) |
| 1042 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1043 | |
| 1044 | out_unpin: |
| 1045 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1046 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1047 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 1048 | if (ret) |
| 1049 | goto out; |
| 1050 | |
| 1051 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1052 | if (ret) |
| 1053 | goto out_put; |
| 1054 | |
| 1055 | ret = -EFAULT; |
| 1056 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1057 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1058 | if (ret == -EFAULT) |
| 1059 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
| 1060 | |
| 1061 | out_put: |
| 1062 | i915_gem_object_put_pages(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1063 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1064 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1065 | out: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1066 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1067 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1068 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1069 | return ret; |
| 1070 | } |
| 1071 | |
| 1072 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1073 | * Called when user space prepares to use an object with the CPU, either |
| 1074 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1075 | */ |
| 1076 | int |
| 1077 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1078 | struct drm_file *file_priv) |
| 1079 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1080 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1081 | struct drm_i915_gem_set_domain *args = data; |
| 1082 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1083 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1084 | uint32_t read_domains = args->read_domains; |
| 1085 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1086 | int ret; |
| 1087 | |
| 1088 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1089 | return -ENODEV; |
| 1090 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1091 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1092 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1093 | return -EINVAL; |
| 1094 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1095 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1096 | return -EINVAL; |
| 1097 | |
| 1098 | /* Having something in the write domain implies it's in the read |
| 1099 | * domain, and only that read domain. Enforce that in the request. |
| 1100 | */ |
| 1101 | if (write_domain != 0 && read_domains != write_domain) |
| 1102 | return -EINVAL; |
| 1103 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1104 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1105 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1106 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1107 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1108 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1109 | if (obj == NULL) { |
| 1110 | ret = -ENOENT; |
| 1111 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1112 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1113 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1114 | |
| 1115 | intel_mark_busy(dev, obj); |
| 1116 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1117 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1118 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1119 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1120 | /* Update the LRU on the fence for the CPU access that's |
| 1121 | * about to occur. |
| 1122 | */ |
| 1123 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1124 | struct drm_i915_fence_reg *reg = |
| 1125 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1126 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1127 | &dev_priv->mm.fence_list); |
| 1128 | } |
| 1129 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1130 | /* Silently promote "you're not bound, there was nothing to do" |
| 1131 | * to success, since the client was just asking us to |
| 1132 | * make sure everything was done. |
| 1133 | */ |
| 1134 | if (ret == -EINVAL) |
| 1135 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1136 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1137 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1138 | } |
| 1139 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1140 | /* Maintain LRU order of "inactive" objects */ |
| 1141 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1142 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1144 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1145 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1146 | mutex_unlock(&dev->struct_mutex); |
| 1147 | return ret; |
| 1148 | } |
| 1149 | |
| 1150 | /** |
| 1151 | * Called when user space has done writes to this buffer |
| 1152 | */ |
| 1153 | int |
| 1154 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1155 | struct drm_file *file_priv) |
| 1156 | { |
| 1157 | struct drm_i915_gem_sw_finish *args = data; |
| 1158 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1159 | int ret = 0; |
| 1160 | |
| 1161 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1162 | return -ENODEV; |
| 1163 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1164 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1165 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1166 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1168 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1169 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1170 | ret = -ENOENT; |
| 1171 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1172 | } |
| 1173 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1174 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 1175 | if (to_intel_bo(obj)->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1176 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1177 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1178 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1179 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1180 | mutex_unlock(&dev->struct_mutex); |
| 1181 | return ret; |
| 1182 | } |
| 1183 | |
| 1184 | /** |
| 1185 | * Maps the contents of an object, returning the address it is mapped |
| 1186 | * into. |
| 1187 | * |
| 1188 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1189 | * imply a ref on the object itself. |
| 1190 | */ |
| 1191 | int |
| 1192 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1193 | struct drm_file *file_priv) |
| 1194 | { |
| 1195 | struct drm_i915_gem_mmap *args = data; |
| 1196 | struct drm_gem_object *obj; |
| 1197 | loff_t offset; |
| 1198 | unsigned long addr; |
| 1199 | |
| 1200 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1201 | return -ENODEV; |
| 1202 | |
| 1203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1204 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1205 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1206 | |
| 1207 | offset = args->offset; |
| 1208 | |
| 1209 | down_write(¤t->mm->mmap_sem); |
| 1210 | addr = do_mmap(obj->filp, 0, args->size, |
| 1211 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1212 | args->offset); |
| 1213 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1214 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1215 | if (IS_ERR((void *)addr)) |
| 1216 | return addr; |
| 1217 | |
| 1218 | args->addr_ptr = (uint64_t) addr; |
| 1219 | |
| 1220 | return 0; |
| 1221 | } |
| 1222 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1223 | /** |
| 1224 | * i915_gem_fault - fault a page into the GTT |
| 1225 | * vma: VMA in question |
| 1226 | * vmf: fault info |
| 1227 | * |
| 1228 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1229 | * from userspace. The fault handler takes care of binding the object to |
| 1230 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1231 | * only if needed based on whether the old reg is still valid or the object |
| 1232 | * is tiled) and inserting a new PTE into the faulting process. |
| 1233 | * |
| 1234 | * Note that the faulting process may involve evicting existing objects |
| 1235 | * from the GTT and/or fence registers to make room. So performance may |
| 1236 | * suffer if the GTT working set is large or there are few fence registers |
| 1237 | * left. |
| 1238 | */ |
| 1239 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1240 | { |
| 1241 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1242 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1243 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1244 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1245 | pgoff_t page_offset; |
| 1246 | unsigned long pfn; |
| 1247 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1248 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1249 | |
| 1250 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1251 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1252 | PAGE_SHIFT; |
| 1253 | |
| 1254 | /* Now bind it into the GTT if needed */ |
| 1255 | mutex_lock(&dev->struct_mutex); |
| 1256 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1257 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1258 | if (ret) |
| 1259 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1260 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1261 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1262 | if (ret) |
| 1263 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | } |
| 1265 | |
| 1266 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1267 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1268 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1269 | if (ret) |
| 1270 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1271 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1272 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1273 | if (i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1274 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1275 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1277 | page_offset; |
| 1278 | |
| 1279 | /* Finally, remap it using the new GTT offset */ |
| 1280 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1281 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1282 | mutex_unlock(&dev->struct_mutex); |
| 1283 | |
| 1284 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1285 | case 0: |
| 1286 | case -ERESTARTSYS: |
| 1287 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1288 | case -ENOMEM: |
| 1289 | case -EAGAIN: |
| 1290 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1291 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1292 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1293 | } |
| 1294 | } |
| 1295 | |
| 1296 | /** |
| 1297 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1298 | * @obj: obj in question |
| 1299 | * |
| 1300 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1301 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1302 | * up the object based on the offset and sets up the various memory mapping |
| 1303 | * structures. |
| 1304 | * |
| 1305 | * This routine allocates and attaches a fake offset for @obj. |
| 1306 | */ |
| 1307 | static int |
| 1308 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1309 | { |
| 1310 | struct drm_device *dev = obj->dev; |
| 1311 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1312 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1313 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1314 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1315 | int ret = 0; |
| 1316 | |
| 1317 | /* Set the object up for mmap'ing */ |
| 1318 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1319 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1320 | if (!list->map) |
| 1321 | return -ENOMEM; |
| 1322 | |
| 1323 | map = list->map; |
| 1324 | map->type = _DRM_GEM; |
| 1325 | map->size = obj->size; |
| 1326 | map->handle = obj; |
| 1327 | |
| 1328 | /* Get a DRM GEM mmap offset allocated... */ |
| 1329 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1330 | obj->size / PAGE_SIZE, 0, 0); |
| 1331 | if (!list->file_offset_node) { |
| 1332 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1333 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1334 | goto out_free_list; |
| 1335 | } |
| 1336 | |
| 1337 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1338 | obj->size / PAGE_SIZE, 0); |
| 1339 | if (!list->file_offset_node) { |
| 1340 | ret = -ENOMEM; |
| 1341 | goto out_free_list; |
| 1342 | } |
| 1343 | |
| 1344 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1345 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1346 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1347 | DRM_ERROR("failed to add to map hash\n"); |
| 1348 | goto out_free_mm; |
| 1349 | } |
| 1350 | |
| 1351 | /* By now we should be all set, any drm_mmap request on the offset |
| 1352 | * below will get to our mmap & fault handler */ |
| 1353 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1354 | |
| 1355 | return 0; |
| 1356 | |
| 1357 | out_free_mm: |
| 1358 | drm_mm_put_block(list->file_offset_node); |
| 1359 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1360 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1361 | |
| 1362 | return ret; |
| 1363 | } |
| 1364 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1365 | /** |
| 1366 | * i915_gem_release_mmap - remove physical page mappings |
| 1367 | * @obj: obj in question |
| 1368 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1369 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1370 | * relinquish ownership of the pages back to the system. |
| 1371 | * |
| 1372 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1373 | * object through the GTT and then lose the fence register due to |
| 1374 | * resource pressure. Similarly if the object has been moved out of the |
| 1375 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1376 | * mapping will then trigger a page fault on the next user access, allowing |
| 1377 | * fixup by i915_gem_fault(). |
| 1378 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1379 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1380 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1381 | { |
| 1382 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1383 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1384 | |
| 1385 | if (dev->dev_mapping) |
| 1386 | unmap_mapping_range(dev->dev_mapping, |
| 1387 | obj_priv->mmap_offset, obj->size, 1); |
| 1388 | } |
| 1389 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1390 | static void |
| 1391 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1392 | { |
| 1393 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1394 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1395 | struct drm_gem_mm *mm = dev->mm_private; |
| 1396 | struct drm_map_list *list; |
| 1397 | |
| 1398 | list = &obj->map_list; |
| 1399 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1400 | |
| 1401 | if (list->file_offset_node) { |
| 1402 | drm_mm_put_block(list->file_offset_node); |
| 1403 | list->file_offset_node = NULL; |
| 1404 | } |
| 1405 | |
| 1406 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1407 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1408 | list->map = NULL; |
| 1409 | } |
| 1410 | |
| 1411 | obj_priv->mmap_offset = 0; |
| 1412 | } |
| 1413 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1414 | /** |
| 1415 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1416 | * @obj: object to check |
| 1417 | * |
| 1418 | * Return the required GTT alignment for an object, taking into account |
| 1419 | * potential fence register mapping if needed. |
| 1420 | */ |
| 1421 | static uint32_t |
| 1422 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1423 | { |
| 1424 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1425 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1426 | int start, i; |
| 1427 | |
| 1428 | /* |
| 1429 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1430 | * if a fence register is needed for the object. |
| 1431 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1432 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1433 | return 4096; |
| 1434 | |
| 1435 | /* |
| 1436 | * Previous chips need to be aligned to the size of the smallest |
| 1437 | * fence register that can contain the object. |
| 1438 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1439 | if (INTEL_INFO(dev)->gen == 3) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1440 | start = 1024*1024; |
| 1441 | else |
| 1442 | start = 512*1024; |
| 1443 | |
| 1444 | for (i = start; i < obj->size; i <<= 1) |
| 1445 | ; |
| 1446 | |
| 1447 | return i; |
| 1448 | } |
| 1449 | |
| 1450 | /** |
| 1451 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1452 | * @dev: DRM device |
| 1453 | * @data: GTT mapping ioctl data |
| 1454 | * @file_priv: GEM object info |
| 1455 | * |
| 1456 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1457 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1458 | * up so we can get faults in the handler above. |
| 1459 | * |
| 1460 | * The fault handler will take care of binding the object into the GTT |
| 1461 | * (since it may have been evicted to make room for something), allocating |
| 1462 | * a fence register, and mapping the appropriate aperture address into |
| 1463 | * userspace. |
| 1464 | */ |
| 1465 | int |
| 1466 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1467 | struct drm_file *file_priv) |
| 1468 | { |
| 1469 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1470 | struct drm_gem_object *obj; |
| 1471 | struct drm_i915_gem_object *obj_priv; |
| 1472 | int ret; |
| 1473 | |
| 1474 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1475 | return -ENODEV; |
| 1476 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1477 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1478 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1479 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1480 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1481 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1482 | if (obj == NULL) { |
| 1483 | ret = -ENOENT; |
| 1484 | goto unlock; |
| 1485 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1486 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1487 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1488 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1489 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1490 | ret = -EINVAL; |
| 1491 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1492 | } |
| 1493 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1494 | if (!obj_priv->mmap_offset) { |
| 1495 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1496 | if (ret) |
| 1497 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1498 | } |
| 1499 | |
| 1500 | args->offset = obj_priv->mmap_offset; |
| 1501 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1502 | /* |
| 1503 | * Pull it into the GTT so that we have a page list (makes the |
| 1504 | * initial fault faster and any subsequent flushing possible). |
| 1505 | */ |
| 1506 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1507 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1508 | if (ret) |
| 1509 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1510 | } |
| 1511 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1512 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1513 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1514 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1515 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1516 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1517 | } |
| 1518 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1519 | static void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1520 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1521 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1523 | int page_count = obj->size / PAGE_SIZE; |
| 1524 | int i; |
| 1525 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1526 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1527 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1528 | |
| 1529 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1530 | return; |
| 1531 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1532 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1533 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1534 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1535 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1536 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1537 | |
| 1538 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1539 | if (obj_priv->dirty) |
| 1540 | set_page_dirty(obj_priv->pages[i]); |
| 1541 | |
| 1542 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1543 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1544 | |
| 1545 | page_cache_release(obj_priv->pages[i]); |
| 1546 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1547 | obj_priv->dirty = 0; |
| 1548 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1549 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1550 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1551 | } |
| 1552 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1553 | static uint32_t |
| 1554 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1555 | struct intel_ring_buffer *ring) |
| 1556 | { |
| 1557 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1558 | |
| 1559 | ring->outstanding_lazy_request = true; |
| 1560 | return dev_priv->next_seqno; |
| 1561 | } |
| 1562 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1563 | static void |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1564 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1565 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | { |
| 1567 | struct drm_device *dev = obj->dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1569 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1570 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1571 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1572 | BUG_ON(ring == NULL); |
| 1573 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1574 | |
| 1575 | /* Add a reference if we're newly entering the active list. */ |
| 1576 | if (!obj_priv->active) { |
| 1577 | drm_gem_object_reference(obj); |
| 1578 | obj_priv->active = 1; |
| 1579 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1580 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1581 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1582 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
| 1583 | list_move_tail(&obj_priv->ring_list, &ring->active_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1584 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1585 | } |
| 1586 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1587 | static void |
| 1588 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1589 | { |
| 1590 | struct drm_device *dev = obj->dev; |
| 1591 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1592 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1593 | |
| 1594 | BUG_ON(!obj_priv->active); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1595 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
| 1596 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1597 | obj_priv->last_rendering_seqno = 0; |
| 1598 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1599 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1600 | /* Immediately discard the backing storage */ |
| 1601 | static void |
| 1602 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1603 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1604 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1605 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1606 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1607 | /* Our goal here is to return as much of the memory as |
| 1608 | * is possible back to the system as we are called from OOM. |
| 1609 | * To do this we must instruct the shmfs to drop all of its |
| 1610 | * backing pages, *now*. Here we mirror the actions taken |
| 1611 | * when by shmem_delete_inode() to release the backing store. |
| 1612 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1613 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1614 | truncate_inode_pages(inode->i_mapping, 0); |
| 1615 | if (inode->i_op->truncate_range) |
| 1616 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1617 | |
| 1618 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1619 | } |
| 1620 | |
| 1621 | static inline int |
| 1622 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1623 | { |
| 1624 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1625 | } |
| 1626 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1627 | static void |
| 1628 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1629 | { |
| 1630 | struct drm_device *dev = obj->dev; |
| 1631 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1632 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1633 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1634 | if (obj_priv->pin_count != 0) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1635 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1636 | else |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1637 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
| 1638 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1639 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1640 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1641 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1642 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1643 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | if (obj_priv->active) { |
| 1645 | obj_priv->active = 0; |
| 1646 | drm_gem_object_unreference(obj); |
| 1647 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1648 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1649 | } |
| 1650 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1651 | static void |
| 1652 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1653 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1654 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1655 | { |
| 1656 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1657 | struct drm_i915_gem_object *obj_priv, *next; |
| 1658 | |
| 1659 | list_for_each_entry_safe(obj_priv, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1660 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1661 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1662 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1663 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1664 | if (obj->write_domain & flush_domains) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1665 | uint32_t old_write_domain = obj->write_domain; |
| 1666 | |
| 1667 | obj->write_domain = 0; |
| 1668 | list_del_init(&obj_priv->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1669 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1670 | |
| 1671 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1672 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1673 | struct drm_i915_fence_reg *reg = |
| 1674 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1675 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1676 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1677 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1678 | |
| 1679 | trace_i915_gem_object_change_domain(obj, |
| 1680 | obj->read_domains, |
| 1681 | old_write_domain); |
| 1682 | } |
| 1683 | } |
| 1684 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1685 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1686 | uint32_t |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1687 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1688 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1689 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1690 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1691 | { |
| 1692 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1693 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1694 | uint32_t seqno; |
| 1695 | int was_empty; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1696 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1697 | if (file != NULL) |
| 1698 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1699 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1700 | if (request == NULL) { |
| 1701 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1702 | if (request == NULL) |
| 1703 | return 0; |
| 1704 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1706 | seqno = ring->add_request(ring, 0); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1707 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1708 | |
| 1709 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1710 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1711 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1712 | was_empty = list_empty(&ring->request_list); |
| 1713 | list_add_tail(&request->list, &ring->request_list); |
| 1714 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1715 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1716 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1717 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1718 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1719 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1720 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1721 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1722 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1723 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1724 | mod_timer(&dev_priv->hangcheck_timer, |
| 1725 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1726 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1727 | queue_delayed_work(dev_priv->wq, |
| 1728 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1729 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | return seqno; |
| 1731 | } |
| 1732 | |
| 1733 | /** |
| 1734 | * Command execution barrier |
| 1735 | * |
| 1736 | * Ensures that all commands in the ring are finished |
| 1737 | * before signalling the CPU |
| 1738 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1739 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1740 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1741 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1743 | |
| 1744 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1745 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1746 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1747 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1748 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1749 | } |
| 1750 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1751 | static inline void |
| 1752 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1753 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1754 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1755 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1756 | if (!file_priv) |
| 1757 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1758 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1759 | spin_lock(&file_priv->mm.lock); |
| 1760 | list_del(&request->client_list); |
| 1761 | request->file_priv = NULL; |
| 1762 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1763 | } |
| 1764 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1765 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1766 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1767 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1768 | while (!list_empty(&ring->request_list)) { |
| 1769 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1770 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1771 | request = list_first_entry(&ring->request_list, |
| 1772 | struct drm_i915_gem_request, |
| 1773 | list); |
| 1774 | |
| 1775 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1776 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1777 | kfree(request); |
| 1778 | } |
| 1779 | |
| 1780 | while (!list_empty(&ring->active_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1781 | struct drm_i915_gem_object *obj_priv; |
| 1782 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1783 | obj_priv = list_first_entry(&ring->active_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1784 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1785 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1786 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1787 | obj_priv->base.write_domain = 0; |
| 1788 | list_del_init(&obj_priv->gpu_write_list); |
| 1789 | i915_gem_object_move_to_inactive(&obj_priv->base); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1790 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1791 | } |
| 1792 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1793 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1794 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1795 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1796 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1797 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1798 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1799 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1800 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1801 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1802 | |
| 1803 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1804 | * to be lost on reset along with the data, so simply move the |
| 1805 | * lost bo to the inactive list. |
| 1806 | */ |
| 1807 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1808 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1809 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1810 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1811 | |
| 1812 | obj_priv->base.write_domain = 0; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1813 | list_del_init(&obj_priv->gpu_write_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1814 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1815 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1816 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1817 | /* Move everything out of the GPU domains to ensure we do any |
| 1818 | * necessary invalidation upon reuse. |
| 1819 | */ |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1820 | list_for_each_entry(obj_priv, |
| 1821 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1822 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1823 | { |
| 1824 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 1825 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1826 | |
| 1827 | /* The fence registers are invalidated so clear them out */ |
| 1828 | for (i = 0; i < 16; i++) { |
| 1829 | struct drm_i915_fence_reg *reg; |
| 1830 | |
| 1831 | reg = &dev_priv->fence_regs[i]; |
| 1832 | if (!reg->obj) |
| 1833 | continue; |
| 1834 | |
| 1835 | i915_gem_clear_fence_reg(reg->obj); |
| 1836 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1837 | } |
| 1838 | |
| 1839 | /** |
| 1840 | * This function clears the request list as sequence numbers are passed. |
| 1841 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1842 | static void |
| 1843 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1844 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1845 | { |
| 1846 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1847 | uint32_t seqno; |
| 1848 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1849 | if (!ring->status_page.page_addr || |
| 1850 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1851 | return; |
| 1852 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1853 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1854 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1855 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1856 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1857 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1858 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1859 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1860 | struct drm_i915_gem_request, |
| 1861 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1862 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1863 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1864 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1865 | |
| 1866 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1867 | |
| 1868 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1869 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1870 | kfree(request); |
| 1871 | } |
| 1872 | |
| 1873 | /* Move any buffers on the active list that are no longer referenced |
| 1874 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1875 | */ |
| 1876 | while (!list_empty(&ring->active_list)) { |
| 1877 | struct drm_gem_object *obj; |
| 1878 | struct drm_i915_gem_object *obj_priv; |
| 1879 | |
| 1880 | obj_priv = list_first_entry(&ring->active_list, |
| 1881 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1882 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1883 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1884 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1885 | break; |
| 1886 | |
| 1887 | obj = &obj_priv->base; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1888 | if (obj->write_domain != 0) |
| 1889 | i915_gem_object_move_to_flushing(obj); |
| 1890 | else |
| 1891 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1892 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1893 | |
| 1894 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1895 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1896 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1897 | dev_priv->trace_irq_seqno = 0; |
| 1898 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1899 | |
| 1900 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1901 | } |
| 1902 | |
| 1903 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1904 | i915_gem_retire_requests(struct drm_device *dev) |
| 1905 | { |
| 1906 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1907 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1908 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 1909 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 1910 | |
| 1911 | /* We must be careful that during unbind() we do not |
| 1912 | * accidentally infinitely recurse into retire requests. |
| 1913 | * Currently: |
| 1914 | * retire -> free -> unbind -> wait -> retire_ring |
| 1915 | */ |
| 1916 | list_for_each_entry_safe(obj_priv, tmp, |
| 1917 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1918 | mm_list) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1919 | i915_gem_free_object_tail(&obj_priv->base); |
| 1920 | } |
| 1921 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1922 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1923 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1924 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1925 | } |
| 1926 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1927 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1928 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1929 | { |
| 1930 | drm_i915_private_t *dev_priv; |
| 1931 | struct drm_device *dev; |
| 1932 | |
| 1933 | dev_priv = container_of(work, drm_i915_private_t, |
| 1934 | mm.retire_work.work); |
| 1935 | dev = dev_priv->dev; |
| 1936 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1937 | /* Come back later if the device is busy... */ |
| 1938 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1939 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1940 | return; |
| 1941 | } |
| 1942 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1943 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1944 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1945 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1946 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1947 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 1948 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1949 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1950 | mutex_unlock(&dev->struct_mutex); |
| 1951 | } |
| 1952 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1953 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1954 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1955 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1956 | { |
| 1957 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1958 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1959 | int ret = 0; |
| 1960 | |
| 1961 | BUG_ON(seqno == 0); |
| 1962 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1963 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1964 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1965 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1966 | if (ring->outstanding_lazy_request) { |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1967 | seqno = i915_add_request(dev, NULL, NULL, ring); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1968 | if (seqno == 0) |
| 1969 | return -ENOMEM; |
| 1970 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1971 | BUG_ON(seqno == dev_priv->next_seqno); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1972 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1973 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1974 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1975 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1976 | else |
| 1977 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1978 | if (!ier) { |
| 1979 | DRM_ERROR("something (likely vbetool) disabled " |
| 1980 | "interrupts, re-enabling\n"); |
| 1981 | i915_driver_irq_preinstall(dev); |
| 1982 | i915_driver_irq_postinstall(dev); |
| 1983 | } |
| 1984 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1985 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1986 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1987 | ring->waiting_gem_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1988 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1989 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1990 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1991 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1992 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1993 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1994 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1995 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1996 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1997 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1998 | ring->user_irq_put(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1999 | ring->waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2000 | |
| 2001 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2002 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2003 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2004 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2005 | |
| 2006 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2007 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2008 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2009 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2010 | |
| 2011 | /* Directly dispatch request retiring. While we have the work queue |
| 2012 | * to handle this, the waiter on a request often wants an associated |
| 2013 | * buffer to have made it to the inactive list, and we would need |
| 2014 | * a separate wait queue to handle that. |
| 2015 | */ |
| 2016 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2017 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2018 | |
| 2019 | return ret; |
| 2020 | } |
| 2021 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2022 | /** |
| 2023 | * Waits for a sequence number to be signaled, and cleans up the |
| 2024 | * request and object lists appropriately for that event. |
| 2025 | */ |
| 2026 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2027 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2028 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2029 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2030 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2031 | } |
| 2032 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2033 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2034 | i915_gem_flush_ring(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2035 | struct drm_file *file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2036 | struct intel_ring_buffer *ring, |
| 2037 | uint32_t invalidate_domains, |
| 2038 | uint32_t flush_domains) |
| 2039 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2040 | ring->flush(ring, invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2041 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2042 | } |
| 2043 | |
| 2044 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2045 | i915_gem_flush(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2046 | struct drm_file *file_priv, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2047 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2048 | uint32_t flush_domains, |
| 2049 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2050 | { |
| 2051 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2052 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2053 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 2054 | drm_agp_chipset_flush(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2055 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2056 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2057 | if (flush_rings & RING_RENDER) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2058 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2059 | &dev_priv->render_ring, |
| 2060 | invalidate_domains, flush_domains); |
| 2061 | if (flush_rings & RING_BSD) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2062 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2063 | &dev_priv->bsd_ring, |
| 2064 | invalidate_domains, flush_domains); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2065 | if (flush_rings & RING_BLT) |
| 2066 | i915_gem_flush_ring(dev, file_priv, |
| 2067 | &dev_priv->blt_ring, |
| 2068 | invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2069 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2070 | } |
| 2071 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2072 | /** |
| 2073 | * Ensures that all rendering to the object has completed and the object is |
| 2074 | * safe to unbind from the GTT or access from the CPU. |
| 2075 | */ |
| 2076 | static int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2077 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 2078 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2079 | { |
| 2080 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2081 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2082 | int ret; |
| 2083 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2084 | /* This function only exists to support waiting for existing rendering, |
| 2085 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2086 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2087 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2088 | |
| 2089 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2090 | * it. |
| 2091 | */ |
| 2092 | if (obj_priv->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2093 | ret = i915_do_wait_request(dev, |
| 2094 | obj_priv->last_rendering_seqno, |
| 2095 | interruptible, |
| 2096 | obj_priv->ring); |
| 2097 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2098 | return ret; |
| 2099 | } |
| 2100 | |
| 2101 | return 0; |
| 2102 | } |
| 2103 | |
| 2104 | /** |
| 2105 | * Unbinds an object from the GTT aperture. |
| 2106 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2107 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2108 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 2109 | { |
| 2110 | struct drm_device *dev = obj->dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2112 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2113 | int ret = 0; |
| 2114 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | if (obj_priv->gtt_space == NULL) |
| 2116 | return 0; |
| 2117 | |
| 2118 | if (obj_priv->pin_count != 0) { |
| 2119 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2120 | return -EINVAL; |
| 2121 | } |
| 2122 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2123 | /* blow away mappings if mapped through GTT */ |
| 2124 | i915_gem_release_mmap(obj); |
| 2125 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2126 | /* Move the object to the CPU domain to ensure that |
| 2127 | * any possible CPU writes while it's not in the GTT |
| 2128 | * are flushed when we go to remap it. This will |
| 2129 | * also ensure that all pending GPU writes are finished |
| 2130 | * before we unbind. |
| 2131 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2132 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2133 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2134 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2135 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2136 | * should be safe and we need to cleanup or else we might |
| 2137 | * cause memory corruption through use-after-free. |
| 2138 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2139 | if (ret) { |
| 2140 | i915_gem_clflush_object(obj); |
| 2141 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2142 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2143 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2144 | /* release the fence reg _after_ flushing */ |
| 2145 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2146 | i915_gem_clear_fence_reg(obj); |
| 2147 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2148 | drm_unbind_agp(obj_priv->agp_mem); |
| 2149 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2150 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2151 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2152 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2153 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2154 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2155 | list_del_init(&obj_priv->mm_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2156 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2157 | drm_mm_put_block(obj_priv->gtt_space); |
| 2158 | obj_priv->gtt_space = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2159 | obj_priv->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2160 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2161 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2162 | i915_gem_object_truncate(obj); |
| 2163 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2164 | trace_i915_gem_object_unbind(obj); |
| 2165 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2166 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2167 | } |
| 2168 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2169 | static int i915_ring_idle(struct drm_device *dev, |
| 2170 | struct intel_ring_buffer *ring) |
| 2171 | { |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2172 | if (list_empty(&ring->gpu_write_list)) |
| 2173 | return 0; |
| 2174 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2175 | i915_gem_flush_ring(dev, NULL, ring, |
| 2176 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2177 | return i915_wait_request(dev, |
| 2178 | i915_gem_next_request_seqno(dev, ring), |
| 2179 | ring); |
| 2180 | } |
| 2181 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2182 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2183 | i915_gpu_idle(struct drm_device *dev) |
| 2184 | { |
| 2185 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2186 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2187 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2188 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2189 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2190 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2191 | list_empty(&dev_priv->bsd_ring.active_list) && |
| 2192 | list_empty(&dev_priv->blt_ring.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2193 | if (lists_empty) |
| 2194 | return 0; |
| 2195 | |
| 2196 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2197 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2198 | if (ret) |
| 2199 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2200 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2201 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2202 | if (ret) |
| 2203 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2204 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2205 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2206 | if (ret) |
| 2207 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2208 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2209 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2210 | } |
| 2211 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2212 | static int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2213 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2214 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2215 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2216 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2217 | int page_count, i; |
| 2218 | struct address_space *mapping; |
| 2219 | struct inode *inode; |
| 2220 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2221 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2222 | BUG_ON(obj_priv->pages_refcount |
| 2223 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2224 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2225 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2226 | return 0; |
| 2227 | |
| 2228 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2229 | * at this point until we release them. |
| 2230 | */ |
| 2231 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2232 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2233 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2234 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2235 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2236 | return -ENOMEM; |
| 2237 | } |
| 2238 | |
| 2239 | inode = obj->filp->f_path.dentry->d_inode; |
| 2240 | mapping = inode->i_mapping; |
| 2241 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2242 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2243 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2244 | __GFP_COLD | |
Linus Torvalds | cd9f040 | 2010-07-18 09:44:37 -0700 | [diff] [blame] | 2245 | __GFP_RECLAIMABLE | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2246 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2247 | if (IS_ERR(page)) |
| 2248 | goto err_pages; |
| 2249 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2250 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2251 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2252 | |
| 2253 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2254 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2255 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2256 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2257 | |
| 2258 | err_pages: |
| 2259 | while (i--) |
| 2260 | page_cache_release(obj_priv->pages[i]); |
| 2261 | |
| 2262 | drm_free_large(obj_priv->pages); |
| 2263 | obj_priv->pages = NULL; |
| 2264 | obj_priv->pages_refcount--; |
| 2265 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2266 | } |
| 2267 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2268 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2269 | { |
| 2270 | struct drm_gem_object *obj = reg->obj; |
| 2271 | struct drm_device *dev = obj->dev; |
| 2272 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2273 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2274 | int regnum = obj_priv->fence_reg; |
| 2275 | uint64_t val; |
| 2276 | |
| 2277 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2278 | 0xfffff000) << 32; |
| 2279 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2280 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2281 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2282 | |
| 2283 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2284 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2285 | val |= I965_FENCE_REG_VALID; |
| 2286 | |
| 2287 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2288 | } |
| 2289 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2290 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2291 | { |
| 2292 | struct drm_gem_object *obj = reg->obj; |
| 2293 | struct drm_device *dev = obj->dev; |
| 2294 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2295 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2296 | int regnum = obj_priv->fence_reg; |
| 2297 | uint64_t val; |
| 2298 | |
| 2299 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2300 | 0xfffff000) << 32; |
| 2301 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2302 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2303 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2304 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2305 | val |= I965_FENCE_REG_VALID; |
| 2306 | |
| 2307 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2308 | } |
| 2309 | |
| 2310 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2311 | { |
| 2312 | struct drm_gem_object *obj = reg->obj; |
| 2313 | struct drm_device *dev = obj->dev; |
| 2314 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2315 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2316 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2317 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2318 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2319 | uint32_t pitch_val; |
| 2320 | |
| 2321 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2322 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2323 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2324 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2325 | return; |
| 2326 | } |
| 2327 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2328 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2329 | HAS_128_BYTE_Y_TILING(dev)) |
| 2330 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2331 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2332 | tile_width = 512; |
| 2333 | |
| 2334 | /* Note: pitch better be a power of two tile widths */ |
| 2335 | pitch_val = obj_priv->stride / tile_width; |
| 2336 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2337 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2338 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2339 | HAS_128_BYTE_Y_TILING(dev)) |
| 2340 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2341 | else |
| 2342 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2343 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2344 | val = obj_priv->gtt_offset; |
| 2345 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2346 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2347 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2348 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2349 | val |= I830_FENCE_REG_VALID; |
| 2350 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2351 | if (regnum < 8) |
| 2352 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2353 | else |
| 2354 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2355 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2356 | } |
| 2357 | |
| 2358 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2359 | { |
| 2360 | struct drm_gem_object *obj = reg->obj; |
| 2361 | struct drm_device *dev = obj->dev; |
| 2362 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2363 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2364 | int regnum = obj_priv->fence_reg; |
| 2365 | uint32_t val; |
| 2366 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2367 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2368 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2369 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2370 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2371 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2372 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2373 | return; |
| 2374 | } |
| 2375 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2376 | pitch_val = obj_priv->stride / 128; |
| 2377 | pitch_val = ffs(pitch_val) - 1; |
| 2378 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2379 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2380 | val = obj_priv->gtt_offset; |
| 2381 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2382 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2383 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2384 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2385 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2386 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2387 | val |= I830_FENCE_REG_VALID; |
| 2388 | |
| 2389 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2390 | } |
| 2391 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2392 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2393 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2394 | { |
| 2395 | struct drm_i915_fence_reg *reg = NULL; |
| 2396 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2397 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2398 | struct drm_gem_object *obj = NULL; |
| 2399 | int i, avail, ret; |
| 2400 | |
| 2401 | /* First try to find a free reg */ |
| 2402 | avail = 0; |
| 2403 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2404 | reg = &dev_priv->fence_regs[i]; |
| 2405 | if (!reg->obj) |
| 2406 | return i; |
| 2407 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2408 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2409 | if (!obj_priv->pin_count) |
| 2410 | avail++; |
| 2411 | } |
| 2412 | |
| 2413 | if (avail == 0) |
| 2414 | return -ENOSPC; |
| 2415 | |
| 2416 | /* None available, try to steal one or wait for a user to finish */ |
| 2417 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2418 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2419 | lru_list) { |
| 2420 | obj = reg->obj; |
| 2421 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2422 | |
| 2423 | if (obj_priv->pin_count) |
| 2424 | continue; |
| 2425 | |
| 2426 | /* found one! */ |
| 2427 | i = obj_priv->fence_reg; |
| 2428 | break; |
| 2429 | } |
| 2430 | |
| 2431 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2432 | |
| 2433 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2434 | * might drop that one, causing a use-after-free in it. So hold a |
| 2435 | * private reference to obj like the other callers of put_fence_reg |
| 2436 | * (set_tiling ioctl) do. */ |
| 2437 | drm_gem_object_reference(obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2438 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2439 | drm_gem_object_unreference(obj); |
| 2440 | if (ret != 0) |
| 2441 | return ret; |
| 2442 | |
| 2443 | return i; |
| 2444 | } |
| 2445 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2446 | /** |
| 2447 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2448 | * @obj: object to map through a fence reg |
| 2449 | * |
| 2450 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2451 | * to them without having to worry about swizzling if the object is tiled. |
| 2452 | * |
| 2453 | * This function walks the fence regs looking for a free one for @obj, |
| 2454 | * stealing one if it can't find any. |
| 2455 | * |
| 2456 | * It then sets up the reg based on the object's properties: address, pitch |
| 2457 | * and tiling format. |
| 2458 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2459 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2460 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
| 2461 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2462 | { |
| 2463 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2464 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2465 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2466 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2467 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2468 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2469 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2470 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2471 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2472 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2473 | return 0; |
| 2474 | } |
| 2475 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2476 | switch (obj_priv->tiling_mode) { |
| 2477 | case I915_TILING_NONE: |
| 2478 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2479 | break; |
| 2480 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2481 | if (!obj_priv->stride) |
| 2482 | return -EINVAL; |
| 2483 | WARN((obj_priv->stride & (512 - 1)), |
| 2484 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2485 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2486 | break; |
| 2487 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2488 | if (!obj_priv->stride) |
| 2489 | return -EINVAL; |
| 2490 | WARN((obj_priv->stride & (128 - 1)), |
| 2491 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2492 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2493 | break; |
| 2494 | } |
| 2495 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2496 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2497 | if (ret < 0) |
| 2498 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2499 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2500 | obj_priv->fence_reg = ret; |
| 2501 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2502 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2503 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2504 | reg->obj = obj; |
| 2505 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2506 | switch (INTEL_INFO(dev)->gen) { |
| 2507 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2508 | sandybridge_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2509 | break; |
| 2510 | case 5: |
| 2511 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2512 | i965_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2513 | break; |
| 2514 | case 3: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2515 | i915_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2516 | break; |
| 2517 | case 2: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2518 | i830_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2519 | break; |
| 2520 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2521 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2522 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2523 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2524 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2525 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2526 | } |
| 2527 | |
| 2528 | /** |
| 2529 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2530 | * @obj: object to clear |
| 2531 | * |
| 2532 | * Zeroes out the fence register itself and clears out the associated |
| 2533 | * data structures in dev_priv and obj_priv. |
| 2534 | */ |
| 2535 | static void |
| 2536 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2537 | { |
| 2538 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2539 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2540 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2541 | struct drm_i915_fence_reg *reg = |
| 2542 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2543 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2544 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2545 | switch (INTEL_INFO(dev)->gen) { |
| 2546 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2547 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2548 | (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2549 | break; |
| 2550 | case 5: |
| 2551 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2552 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2553 | break; |
| 2554 | case 3: |
Chris Wilson | 9b74f73 | 2010-09-22 19:10:44 +0100 | [diff] [blame] | 2555 | if (obj_priv->fence_reg >= 8) |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2556 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2557 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2558 | case 2: |
| 2559 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2560 | |
| 2561 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2562 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2563 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2564 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2565 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2566 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2567 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2568 | } |
| 2569 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2570 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2571 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2572 | * to the buffer to finish, and then resets the fence register. |
| 2573 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2574 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2575 | * |
| 2576 | * Zeroes out the fence register itself and clears out the associated |
| 2577 | * data structures in dev_priv and obj_priv. |
| 2578 | */ |
| 2579 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2580 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
| 2581 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2582 | { |
| 2583 | struct drm_device *dev = obj->dev; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2584 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2585 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2586 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2587 | |
| 2588 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2589 | return 0; |
| 2590 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2591 | /* If we've changed tiling, GTT-mappings of the object |
| 2592 | * need to re-fault to ensure that the correct fence register |
| 2593 | * setup is in place. |
| 2594 | */ |
| 2595 | i915_gem_release_mmap(obj); |
| 2596 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2597 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2598 | * therefore we must wait for any outstanding access to complete |
| 2599 | * before clearing the fence. |
| 2600 | */ |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2601 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2602 | if (reg->gpu) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2603 | int ret; |
| 2604 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2605 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2606 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2607 | return ret; |
| 2608 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2609 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2610 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2611 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2612 | |
| 2613 | reg->gpu = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2614 | } |
| 2615 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2616 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2617 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2618 | |
| 2619 | return 0; |
| 2620 | } |
| 2621 | |
| 2622 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2623 | * Finds free space in the GTT aperture and binds the object there. |
| 2624 | */ |
| 2625 | static int |
| 2626 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2627 | { |
| 2628 | struct drm_device *dev = obj->dev; |
| 2629 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2630 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2631 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2632 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2633 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2634 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2635 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2636 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2637 | return -EINVAL; |
| 2638 | } |
| 2639 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2640 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2641 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2642 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2643 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2644 | return -EINVAL; |
| 2645 | } |
| 2646 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2647 | /* If the object is bigger than the entire aperture, reject it early |
| 2648 | * before evicting everything in a vain attempt to find space. |
| 2649 | */ |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2650 | if (obj->size > dev_priv->mm.gtt_total) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2651 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2652 | return -E2BIG; |
| 2653 | } |
| 2654 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2655 | search_free: |
| 2656 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2657 | obj->size, alignment, 0); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2658 | if (free_space != NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2659 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2660 | alignment); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2661 | if (obj_priv->gtt_space == NULL) { |
| 2662 | /* If the gtt is empty and we're still having trouble |
| 2663 | * fitting our object in, we're out of memory. |
| 2664 | */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2665 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2666 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2667 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2668 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2669 | goto search_free; |
| 2670 | } |
| 2671 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2672 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2673 | if (ret) { |
| 2674 | drm_mm_put_block(obj_priv->gtt_space); |
| 2675 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2676 | |
| 2677 | if (ret == -ENOMEM) { |
| 2678 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2679 | ret = i915_gem_evict_something(dev, obj->size, |
| 2680 | alignment); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2681 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2682 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2683 | if (gfpmask) { |
| 2684 | gfpmask = 0; |
| 2685 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2686 | } |
| 2687 | |
| 2688 | return ret; |
| 2689 | } |
| 2690 | |
| 2691 | goto search_free; |
| 2692 | } |
| 2693 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | return ret; |
| 2695 | } |
| 2696 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2697 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2698 | * into the GTT. |
| 2699 | */ |
| 2700 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2701 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2702 | obj->size >> PAGE_SHIFT, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2703 | obj_priv->gtt_space->start, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2704 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2705 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2706 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2707 | drm_mm_put_block(obj_priv->gtt_space); |
| 2708 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2709 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2710 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2711 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2712 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2713 | |
| 2714 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2715 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2716 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2717 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2718 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2719 | i915_gem_info_add_gtt(dev_priv, obj->size); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2720 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | /* Assert that the object is not currently in any GPU domain. As it |
| 2722 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2723 | * a GPU cache |
| 2724 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2725 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2726 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2728 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2729 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2730 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2731 | return 0; |
| 2732 | } |
| 2733 | |
| 2734 | void |
| 2735 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2736 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2737 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2738 | |
| 2739 | /* If we don't have a page list set up, then we're not pinned |
| 2740 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2741 | * again at bind time. |
| 2742 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2743 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2744 | return; |
| 2745 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2746 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2747 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2748 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2749 | } |
| 2750 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2751 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2752 | static int |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2753 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 2754 | bool pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2755 | { |
| 2756 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2757 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2758 | |
| 2759 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2760 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2761 | |
| 2762 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2763 | old_write_domain = obj->write_domain; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2764 | i915_gem_flush_ring(dev, NULL, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2765 | to_intel_bo(obj)->ring, |
| 2766 | 0, obj->write_domain); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2767 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2768 | |
| 2769 | trace_i915_gem_object_change_domain(obj, |
| 2770 | obj->read_domains, |
| 2771 | old_write_domain); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2772 | |
| 2773 | if (pipelined) |
| 2774 | return 0; |
| 2775 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2776 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2777 | } |
| 2778 | |
| 2779 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2780 | static void |
| 2781 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2782 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2783 | uint32_t old_write_domain; |
| 2784 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2785 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2786 | return; |
| 2787 | |
| 2788 | /* No actual flushing is required for the GTT write domain. Writes |
| 2789 | * to it immediately go to main memory as far as we know, so there's |
| 2790 | * no chipset flush. It also doesn't land in render cache. |
| 2791 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2792 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2793 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2794 | |
| 2795 | trace_i915_gem_object_change_domain(obj, |
| 2796 | obj->read_domains, |
| 2797 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2798 | } |
| 2799 | |
| 2800 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2801 | static void |
| 2802 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2803 | { |
| 2804 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2805 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2806 | |
| 2807 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2808 | return; |
| 2809 | |
| 2810 | i915_gem_clflush_object(obj); |
| 2811 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2812 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2813 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2814 | |
| 2815 | trace_i915_gem_object_change_domain(obj, |
| 2816 | obj->read_domains, |
| 2817 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2818 | } |
| 2819 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2820 | /** |
| 2821 | * Moves a single object to the GTT read, and possibly write domain. |
| 2822 | * |
| 2823 | * This function returns when the move is complete, including waiting on |
| 2824 | * flushes to occur. |
| 2825 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2826 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2827 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2828 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2829 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2830 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2831 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2832 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2833 | /* Not valid to be called on unbound objects. */ |
| 2834 | if (obj_priv->gtt_space == NULL) |
| 2835 | return -EINVAL; |
| 2836 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2837 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2838 | if (ret != 0) |
| 2839 | return ret; |
| 2840 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2841 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2842 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2843 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2844 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2845 | if (ret) |
| 2846 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2847 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2848 | |
| 2849 | old_write_domain = obj->write_domain; |
| 2850 | old_read_domains = obj->read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2851 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2852 | /* It should now be out of any other write domains, and we can update |
| 2853 | * the domain values for our changes. |
| 2854 | */ |
| 2855 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2856 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2857 | if (write) { |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2858 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2859 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2860 | obj_priv->dirty = 1; |
| 2861 | } |
| 2862 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2863 | trace_i915_gem_object_change_domain(obj, |
| 2864 | old_read_domains, |
| 2865 | old_write_domain); |
| 2866 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2867 | return 0; |
| 2868 | } |
| 2869 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2870 | /* |
| 2871 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2872 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2873 | */ |
| 2874 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2875 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
| 2876 | bool pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2877 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2878 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2879 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2880 | int ret; |
| 2881 | |
| 2882 | /* Not valid to be called on unbound objects. */ |
| 2883 | if (obj_priv->gtt_space == NULL) |
| 2884 | return -EINVAL; |
| 2885 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2886 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2887 | if (ret) |
| 2888 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2889 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2890 | /* Currently, we are always called from an non-interruptible context. */ |
| 2891 | if (!pipelined) { |
| 2892 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2893 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2894 | return ret; |
| 2895 | } |
| 2896 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2897 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2898 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2899 | old_read_domains = obj->read_domains; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2900 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2901 | |
| 2902 | trace_i915_gem_object_change_domain(obj, |
| 2903 | old_read_domains, |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2904 | obj->write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2905 | |
| 2906 | return 0; |
| 2907 | } |
| 2908 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2909 | /** |
| 2910 | * Moves a single object to the CPU read, and possibly write domain. |
| 2911 | * |
| 2912 | * This function returns when the move is complete, including waiting on |
| 2913 | * flushes to occur. |
| 2914 | */ |
| 2915 | static int |
| 2916 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2917 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2918 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2919 | int ret; |
| 2920 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2921 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2922 | if (ret != 0) |
| 2923 | return ret; |
| 2924 | |
| 2925 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2926 | |
| 2927 | /* If we have a partially-valid cache of the object in the CPU, |
| 2928 | * finish invalidating it and free the per-page flags. |
| 2929 | */ |
| 2930 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2931 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2932 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2933 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2934 | if (ret) |
| 2935 | return ret; |
| 2936 | } |
| 2937 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2938 | old_write_domain = obj->write_domain; |
| 2939 | old_read_domains = obj->read_domains; |
| 2940 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2941 | /* Flush the CPU cache if it's still invalid. */ |
| 2942 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2943 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2944 | |
| 2945 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2946 | } |
| 2947 | |
| 2948 | /* It should now be out of any other write domains, and we can update |
| 2949 | * the domain values for our changes. |
| 2950 | */ |
| 2951 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2952 | |
| 2953 | /* If we're writing through the CPU, then the GPU read domains will |
| 2954 | * need to be invalidated at next use. |
| 2955 | */ |
| 2956 | if (write) { |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2957 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2958 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2959 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2960 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2961 | trace_i915_gem_object_change_domain(obj, |
| 2962 | old_read_domains, |
| 2963 | old_write_domain); |
| 2964 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2965 | return 0; |
| 2966 | } |
| 2967 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2968 | /* |
| 2969 | * Set the next domain for the specified object. This |
| 2970 | * may not actually perform the necessary flushing/invaliding though, |
| 2971 | * as that may want to be batched with other set_domain operations |
| 2972 | * |
| 2973 | * This is (we hope) the only really tricky part of gem. The goal |
| 2974 | * is fairly simple -- track which caches hold bits of the object |
| 2975 | * and make sure they remain coherent. A few concrete examples may |
| 2976 | * help to explain how it works. For shorthand, we use the notation |
| 2977 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2978 | * a pair of read and write domain masks. |
| 2979 | * |
| 2980 | * Case 1: the batch buffer |
| 2981 | * |
| 2982 | * 1. Allocated |
| 2983 | * 2. Written by CPU |
| 2984 | * 3. Mapped to GTT |
| 2985 | * 4. Read by GPU |
| 2986 | * 5. Unmapped from GTT |
| 2987 | * 6. Freed |
| 2988 | * |
| 2989 | * Let's take these a step at a time |
| 2990 | * |
| 2991 | * 1. Allocated |
| 2992 | * Pages allocated from the kernel may still have |
| 2993 | * cache contents, so we set them to (CPU, CPU) always. |
| 2994 | * 2. Written by CPU (using pwrite) |
| 2995 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2996 | * this function does nothing (as nothing changes) |
| 2997 | * 3. Mapped by GTT |
| 2998 | * This function asserts that the object is not |
| 2999 | * currently in any GPU-based read or write domains |
| 3000 | * 4. Read by GPU |
| 3001 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3002 | * As write_domain is zero, this function adds in the |
| 3003 | * current read domains (CPU+COMMAND, 0). |
| 3004 | * flush_domains is set to CPU. |
| 3005 | * invalidate_domains is set to COMMAND |
| 3006 | * clflush is run to get data out of the CPU caches |
| 3007 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3008 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3009 | * 5. Unmapped from GTT |
| 3010 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3011 | * flush_domains and invalidate_domains end up both zero |
| 3012 | * so no flushing/invalidating happens |
| 3013 | * 6. Freed |
| 3014 | * yay, done |
| 3015 | * |
| 3016 | * Case 2: The shared render buffer |
| 3017 | * |
| 3018 | * 1. Allocated |
| 3019 | * 2. Mapped to GTT |
| 3020 | * 3. Read/written by GPU |
| 3021 | * 4. set_domain to (CPU,CPU) |
| 3022 | * 5. Read/written by CPU |
| 3023 | * 6. Read/written by GPU |
| 3024 | * |
| 3025 | * 1. Allocated |
| 3026 | * Same as last example, (CPU, CPU) |
| 3027 | * 2. Mapped to GTT |
| 3028 | * Nothing changes (assertions find that it is not in the GPU) |
| 3029 | * 3. Read/written by GPU |
| 3030 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3031 | * flush_domains gets CPU |
| 3032 | * invalidate_domains gets GPU |
| 3033 | * clflush (obj) |
| 3034 | * MI_FLUSH and drm_agp_chipset_flush |
| 3035 | * 4. set_domain (CPU, CPU) |
| 3036 | * flush_domains gets GPU |
| 3037 | * invalidate_domains gets CPU |
| 3038 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3039 | * This will include an MI_FLUSH to get the data from GPU |
| 3040 | * to memory |
| 3041 | * clflush (obj) to invalidate the CPU cache |
| 3042 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3043 | * 5. Read/written by CPU |
| 3044 | * cache lines are loaded and dirtied |
| 3045 | * 6. Read written by GPU |
| 3046 | * Same as last GPU access |
| 3047 | * |
| 3048 | * Case 3: The constant buffer |
| 3049 | * |
| 3050 | * 1. Allocated |
| 3051 | * 2. Written by CPU |
| 3052 | * 3. Read by GPU |
| 3053 | * 4. Updated (written) by CPU again |
| 3054 | * 5. Read by GPU |
| 3055 | * |
| 3056 | * 1. Allocated |
| 3057 | * (CPU, CPU) |
| 3058 | * 2. Written by CPU |
| 3059 | * (CPU, CPU) |
| 3060 | * 3. Read by GPU |
| 3061 | * (CPU+RENDER, 0) |
| 3062 | * flush_domains = CPU |
| 3063 | * invalidate_domains = RENDER |
| 3064 | * clflush (obj) |
| 3065 | * MI_FLUSH |
| 3066 | * drm_agp_chipset_flush |
| 3067 | * 4. Updated (written) by CPU again |
| 3068 | * (CPU, CPU) |
| 3069 | * flush_domains = 0 (no previous write domain) |
| 3070 | * invalidate_domains = 0 (no new read domains) |
| 3071 | * 5. Read by GPU |
| 3072 | * (CPU+RENDER, 0) |
| 3073 | * flush_domains = CPU |
| 3074 | * invalidate_domains = RENDER |
| 3075 | * clflush (obj) |
| 3076 | * MI_FLUSH |
| 3077 | * drm_agp_chipset_flush |
| 3078 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3079 | static void |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3080 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
| 3081 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3082 | { |
| 3083 | struct drm_device *dev = obj->dev; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3084 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3085 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3086 | uint32_t invalidate_domains = 0; |
| 3087 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3088 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3089 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3090 | intel_mark_busy(dev, obj); |
| 3091 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3092 | /* |
| 3093 | * If the object isn't moving to a new write domain, |
| 3094 | * let the object stay in multiple read domains |
| 3095 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3096 | if (obj->pending_write_domain == 0) |
| 3097 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3098 | else |
| 3099 | obj_priv->dirty = 1; |
| 3100 | |
| 3101 | /* |
| 3102 | * Flush the current write domain if |
| 3103 | * the new read domains don't match. Invalidate |
| 3104 | * any read domains which differ from the old |
| 3105 | * write domain |
| 3106 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3107 | if (obj->write_domain && |
| 3108 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3109 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3110 | invalidate_domains |= |
| 3111 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3112 | } |
| 3113 | /* |
| 3114 | * Invalidate any read caches which may have |
| 3115 | * stale data. That is, any new read domains. |
| 3116 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3117 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3118 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3119 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3120 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3121 | old_read_domains = obj->read_domains; |
| 3122 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3123 | /* The actual obj->write_domain will be updated with |
| 3124 | * pending_write_domain after we emit the accumulated flush for all |
| 3125 | * of our domain changes in execbuffers (which clears objects' |
| 3126 | * write_domains). So if we have a current write domain that we |
| 3127 | * aren't changing, set pending_write_domain to that. |
| 3128 | */ |
| 3129 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3130 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3131 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3132 | |
| 3133 | dev->invalidate_domains |= invalidate_domains; |
| 3134 | dev->flush_domains |= flush_domains; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3135 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3136 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3137 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
| 3138 | dev_priv->mm.flush_rings |= ring->id; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3139 | |
| 3140 | trace_i915_gem_object_change_domain(obj, |
| 3141 | old_read_domains, |
| 3142 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3143 | } |
| 3144 | |
| 3145 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3146 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3147 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3148 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3149 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3150 | */ |
| 3151 | static void |
| 3152 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3153 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3154 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3155 | |
| 3156 | if (!obj_priv->page_cpu_valid) |
| 3157 | return; |
| 3158 | |
| 3159 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3160 | */ |
| 3161 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3162 | int i; |
| 3163 | |
| 3164 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3165 | if (obj_priv->page_cpu_valid[i]) |
| 3166 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3167 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3168 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3169 | } |
| 3170 | |
| 3171 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3172 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3173 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3174 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3175 | obj_priv->page_cpu_valid = NULL; |
| 3176 | } |
| 3177 | |
| 3178 | /** |
| 3179 | * Set the CPU read domain on a range of the object. |
| 3180 | * |
| 3181 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3182 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3183 | * pages have been flushed, and will be respected by |
| 3184 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3185 | * of the whole object. |
| 3186 | * |
| 3187 | * This function returns when the move is complete, including waiting on |
| 3188 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3189 | */ |
| 3190 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3191 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3192 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3193 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3194 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3195 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3196 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3197 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3198 | if (offset == 0 && size == obj->size) |
| 3199 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3200 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3201 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3202 | if (ret != 0) |
| 3203 | return ret; |
| 3204 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3205 | |
| 3206 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3207 | if (obj_priv->page_cpu_valid == NULL && |
| 3208 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3209 | return 0; |
| 3210 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3211 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3212 | * newly adding I915_GEM_DOMAIN_CPU |
| 3213 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3214 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3215 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3216 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3217 | if (obj_priv->page_cpu_valid == NULL) |
| 3218 | return -ENOMEM; |
| 3219 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3220 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3221 | |
| 3222 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3223 | * perspective. |
| 3224 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3225 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3226 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3227 | if (obj_priv->page_cpu_valid[i]) |
| 3228 | continue; |
| 3229 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3230 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3231 | |
| 3232 | obj_priv->page_cpu_valid[i] = 1; |
| 3233 | } |
| 3234 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3235 | /* It should now be out of any other write domains, and we can update |
| 3236 | * the domain values for our changes. |
| 3237 | */ |
| 3238 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3239 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3240 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3241 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3242 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3243 | trace_i915_gem_object_change_domain(obj, |
| 3244 | old_read_domains, |
| 3245 | obj->write_domain); |
| 3246 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3247 | return 0; |
| 3248 | } |
| 3249 | |
| 3250 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3251 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3252 | */ |
| 3253 | static int |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3254 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
| 3255 | struct drm_file *file_priv, |
| 3256 | struct drm_i915_gem_exec_object2 *entry) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3257 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3258 | struct drm_device *dev = obj->base.dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3259 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3260 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3261 | struct drm_gem_object *target_obj = NULL; |
| 3262 | uint32_t target_handle = 0; |
| 3263 | int i, ret = 0; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3264 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3265 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3266 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3267 | struct drm_i915_gem_relocation_entry reloc; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3268 | uint32_t target_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3269 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3270 | if (__copy_from_user_inatomic(&reloc, |
| 3271 | user_relocs+i, |
| 3272 | sizeof(reloc))) { |
| 3273 | ret = -EFAULT; |
| 3274 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3275 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3276 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3277 | if (reloc.target_handle != target_handle) { |
| 3278 | drm_gem_object_unreference(target_obj); |
| 3279 | |
| 3280 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3281 | reloc.target_handle); |
| 3282 | if (target_obj == NULL) { |
| 3283 | ret = -ENOENT; |
| 3284 | break; |
| 3285 | } |
| 3286 | |
| 3287 | target_handle = reloc.target_handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3288 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3289 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3290 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3291 | #if WATCH_RELOC |
| 3292 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3293 | "read %08x write %08x gtt %08x " |
| 3294 | "presumed %08x delta %08x\n", |
| 3295 | __func__, |
| 3296 | obj, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3297 | (int) reloc.offset, |
| 3298 | (int) reloc.target_handle, |
| 3299 | (int) reloc.read_domains, |
| 3300 | (int) reloc.write_domain, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3301 | (int) target_offset, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3302 | (int) reloc.presumed_offset, |
| 3303 | reloc.delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3304 | #endif |
| 3305 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3306 | /* The target buffer should have appeared before us in the |
| 3307 | * exec_object list, so it should have a GTT space bound by now. |
| 3308 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3309 | if (target_offset == 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3310 | DRM_ERROR("No GTT space found for object %d\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3311 | reloc.target_handle); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3312 | ret = -EINVAL; |
| 3313 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3314 | } |
| 3315 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3316 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3317 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3318 | DRM_ERROR("reloc with multiple write domains: " |
| 3319 | "obj %p target %d offset %d " |
| 3320 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3321 | obj, reloc.target_handle, |
| 3322 | (int) reloc.offset, |
| 3323 | reloc.read_domains, |
| 3324 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3325 | ret = -EINVAL; |
| 3326 | break; |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3327 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3328 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 3329 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3330 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3331 | "obj %p target %d offset %d " |
| 3332 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3333 | obj, reloc.target_handle, |
| 3334 | (int) reloc.offset, |
| 3335 | reloc.read_domains, |
| 3336 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3337 | ret = -EINVAL; |
| 3338 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3339 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3340 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 3341 | reloc.write_domain != target_obj->pending_write_domain) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3342 | DRM_ERROR("Write domain conflict: " |
| 3343 | "obj %p target %d offset %d " |
| 3344 | "new %08x old %08x\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3345 | obj, reloc.target_handle, |
| 3346 | (int) reloc.offset, |
| 3347 | reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3348 | target_obj->pending_write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3349 | ret = -EINVAL; |
| 3350 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3351 | } |
| 3352 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3353 | target_obj->pending_read_domains |= reloc.read_domains; |
Chris Wilson | 878a3c3 | 2010-10-22 10:48:12 +0100 | [diff] [blame] | 3354 | target_obj->pending_write_domain |= reloc.write_domain; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3355 | |
| 3356 | /* If the relocation already has the right value in it, no |
| 3357 | * more work needs to be done. |
| 3358 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3359 | if (target_offset == reloc.presumed_offset) |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3360 | continue; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3361 | |
| 3362 | /* Check that the relocation address is valid... */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3363 | if (reloc.offset > obj->base.size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3364 | DRM_ERROR("Relocation beyond object bounds: " |
| 3365 | "obj %p target %d offset %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3366 | obj, reloc.target_handle, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3367 | (int) reloc.offset, (int) obj->base.size); |
| 3368 | ret = -EINVAL; |
| 3369 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3370 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3371 | if (reloc.offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3372 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3373 | "obj %p target %d offset %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3374 | obj, reloc.target_handle, |
| 3375 | (int) reloc.offset); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3376 | ret = -EINVAL; |
| 3377 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3378 | } |
| 3379 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3380 | /* and points to somewhere within the target object. */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3381 | if (reloc.delta >= target_obj->size) { |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3382 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3383 | "obj %p target %d delta %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3384 | obj, reloc.target_handle, |
| 3385 | (int) reloc.delta, (int) target_obj->size); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3386 | ret = -EINVAL; |
| 3387 | break; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3388 | } |
| 3389 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3390 | reloc.delta += target_offset; |
| 3391 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3392 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
| 3393 | char *vaddr; |
| 3394 | |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3395 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3396 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3397 | kunmap_atomic(vaddr); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3398 | } else { |
| 3399 | uint32_t __iomem *reloc_entry; |
| 3400 | void __iomem *reloc_page; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3401 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3402 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
| 3403 | if (ret) |
| 3404 | break; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3405 | |
| 3406 | /* Map the page containing the relocation we're going to perform. */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3407 | reloc.offset += obj->gtt_offset; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3408 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3409 | reloc.offset & PAGE_MASK); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3410 | reloc_entry = (uint32_t __iomem *) |
| 3411 | (reloc_page + (reloc.offset & ~PAGE_MASK)); |
| 3412 | iowrite32(reloc.delta, reloc_entry); |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3413 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3414 | } |
| 3415 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3416 | /* and update the user's relocation entry */ |
| 3417 | reloc.presumed_offset = target_offset; |
| 3418 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3419 | &reloc.presumed_offset, |
| 3420 | sizeof(reloc.presumed_offset))) { |
| 3421 | ret = -EFAULT; |
| 3422 | break; |
| 3423 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3424 | } |
| 3425 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3426 | drm_gem_object_unreference(target_obj); |
| 3427 | return ret; |
| 3428 | } |
| 3429 | |
| 3430 | static int |
| 3431 | i915_gem_execbuffer_pin(struct drm_device *dev, |
| 3432 | struct drm_file *file, |
| 3433 | struct drm_gem_object **object_list, |
| 3434 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3435 | int count) |
| 3436 | { |
| 3437 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3438 | int ret, i, retry; |
| 3439 | |
| 3440 | /* attempt to pin all of the buffers into the GTT */ |
| 3441 | for (retry = 0; retry < 2; retry++) { |
| 3442 | ret = 0; |
| 3443 | for (i = 0; i < count; i++) { |
| 3444 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
| 3445 | struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]); |
| 3446 | bool need_fence = |
| 3447 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3448 | obj->tiling_mode != I915_TILING_NONE; |
| 3449 | |
| 3450 | /* Check fence reg constraints and rebind if necessary */ |
| 3451 | if (need_fence && |
| 3452 | !i915_gem_object_fence_offset_ok(&obj->base, |
| 3453 | obj->tiling_mode)) { |
| 3454 | ret = i915_gem_object_unbind(&obj->base); |
| 3455 | if (ret) |
| 3456 | break; |
| 3457 | } |
| 3458 | |
| 3459 | ret = i915_gem_object_pin(&obj->base, entry->alignment); |
| 3460 | if (ret) |
| 3461 | break; |
| 3462 | |
| 3463 | /* |
| 3464 | * Pre-965 chips need a fence register set up in order |
| 3465 | * to properly handle blits to/from tiled surfaces. |
| 3466 | */ |
| 3467 | if (need_fence) { |
| 3468 | ret = i915_gem_object_get_fence_reg(&obj->base, true); |
| 3469 | if (ret) { |
| 3470 | i915_gem_object_unpin(&obj->base); |
| 3471 | break; |
| 3472 | } |
| 3473 | |
| 3474 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
| 3475 | } |
| 3476 | |
| 3477 | entry->offset = obj->gtt_offset; |
| 3478 | } |
| 3479 | |
| 3480 | while (i--) |
| 3481 | i915_gem_object_unpin(object_list[i]); |
| 3482 | |
| 3483 | if (ret == 0) |
| 3484 | break; |
| 3485 | |
| 3486 | if (ret != -ENOSPC || retry) |
| 3487 | return ret; |
| 3488 | |
| 3489 | ret = i915_gem_evict_everything(dev); |
| 3490 | if (ret) |
| 3491 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3492 | } |
| 3493 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3494 | return 0; |
| 3495 | } |
| 3496 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3497 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3498 | * emitted over 20 msec ago. |
| 3499 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3500 | * Note that if we were to use the current jiffies each time around the loop, |
| 3501 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3502 | * render a frame was over 20ms. |
| 3503 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3504 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3505 | * relatively low latency when blocking on a particular request to finish. |
| 3506 | */ |
| 3507 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3508 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3509 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3510 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3511 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3512 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3513 | struct drm_i915_gem_request *request; |
| 3514 | struct intel_ring_buffer *ring = NULL; |
| 3515 | u32 seqno = 0; |
| 3516 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3517 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3518 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3519 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3520 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3521 | break; |
| 3522 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3523 | ring = request->ring; |
| 3524 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3525 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3526 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3527 | |
| 3528 | if (seqno == 0) |
| 3529 | return 0; |
| 3530 | |
| 3531 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3532 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3533 | /* And wait for the seqno passing without holding any locks and |
| 3534 | * causing extra latency for others. This is safe as the irq |
| 3535 | * generation is designed to be run atomically and so is |
| 3536 | * lockless. |
| 3537 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3538 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3539 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3540 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3541 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3542 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3543 | |
| 3544 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3545 | ret = -EIO; |
| 3546 | } |
| 3547 | |
| 3548 | if (ret == 0) |
| 3549 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3550 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3551 | return ret; |
| 3552 | } |
| 3553 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3554 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3555 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3556 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3557 | { |
| 3558 | uint32_t exec_start, exec_len; |
| 3559 | |
| 3560 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3561 | exec_len = (uint32_t) exec->batch_len; |
| 3562 | |
| 3563 | if ((exec_start | exec_len) & 0x7) |
| 3564 | return -EINVAL; |
| 3565 | |
| 3566 | if (!exec_start) |
| 3567 | return -EINVAL; |
| 3568 | |
| 3569 | return 0; |
| 3570 | } |
| 3571 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3572 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3573 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3574 | int count) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3575 | { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3576 | int i; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3577 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3578 | for (i = 0; i < count; i++) { |
| 3579 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 3580 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3581 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3582 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3583 | return -EFAULT; |
| 3584 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3585 | /* we may also need to update the presumed offsets */ |
| 3586 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3587 | return -EFAULT; |
| 3588 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3589 | if (fault_in_pages_readable(ptr, length)) |
| 3590 | return -EFAULT; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3591 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3592 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3593 | return 0; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3594 | } |
| 3595 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3596 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3597 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3598 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3599 | struct drm_i915_gem_execbuffer2 *args, |
| 3600 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3601 | { |
| 3602 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3603 | struct drm_gem_object **object_list = NULL; |
| 3604 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3605 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3606 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3607 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3608 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3609 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3610 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3611 | struct intel_ring_buffer *ring = NULL; |
| 3612 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3613 | ret = i915_gem_check_is_wedged(dev); |
| 3614 | if (ret) |
| 3615 | return ret; |
| 3616 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3617 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3618 | if (ret) |
| 3619 | return ret; |
| 3620 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3621 | #if WATCH_EXEC |
| 3622 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3623 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3624 | #endif |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3625 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 3626 | case I915_EXEC_DEFAULT: |
| 3627 | case I915_EXEC_RENDER: |
| 3628 | ring = &dev_priv->render_ring; |
| 3629 | break; |
| 3630 | case I915_EXEC_BSD: |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3631 | if (!HAS_BSD(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3632 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3633 | return -EINVAL; |
| 3634 | } |
| 3635 | ring = &dev_priv->bsd_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3636 | break; |
| 3637 | case I915_EXEC_BLT: |
| 3638 | if (!HAS_BLT(dev)) { |
| 3639 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); |
| 3640 | return -EINVAL; |
| 3641 | } |
| 3642 | ring = &dev_priv->blt_ring; |
| 3643 | break; |
| 3644 | default: |
| 3645 | DRM_ERROR("execbuf with unknown ring: %d\n", |
| 3646 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 3647 | return -EINVAL; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3648 | } |
| 3649 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3650 | if (args->buffer_count < 1) { |
| 3651 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3652 | return -EINVAL; |
| 3653 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3654 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3655 | if (object_list == NULL) { |
| 3656 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3657 | args->buffer_count); |
| 3658 | ret = -ENOMEM; |
| 3659 | goto pre_mutex_err; |
| 3660 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3661 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3662 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3663 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3664 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3665 | if (cliprects == NULL) { |
| 3666 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3667 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3668 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3669 | |
| 3670 | ret = copy_from_user(cliprects, |
| 3671 | (struct drm_clip_rect __user *) |
| 3672 | (uintptr_t) args->cliprects_ptr, |
| 3673 | sizeof(*cliprects) * args->num_cliprects); |
| 3674 | if (ret != 0) { |
| 3675 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3676 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3677 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3678 | goto pre_mutex_err; |
| 3679 | } |
| 3680 | } |
| 3681 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3682 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3683 | if (request == NULL) { |
| 3684 | ret = -ENOMEM; |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3685 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3686 | } |
| 3687 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3688 | ret = i915_mutex_lock_interruptible(dev); |
| 3689 | if (ret) |
| 3690 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3691 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3692 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3693 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3694 | ret = -EBUSY; |
| 3695 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3696 | } |
| 3697 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3698 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3699 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3700 | object_list[i] = drm_gem_object_lookup(dev, file, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3701 | exec_list[i].handle); |
| 3702 | if (object_list[i] == NULL) { |
| 3703 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3704 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3705 | /* prevent error path from reading uninitialized data */ |
| 3706 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3707 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3708 | goto err; |
| 3709 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3710 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3711 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3712 | if (obj_priv->in_execbuffer) { |
| 3713 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3714 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3715 | /* prevent error path from reading uninitialized data */ |
| 3716 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3717 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3718 | goto err; |
| 3719 | } |
| 3720 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3721 | } |
| 3722 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3723 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
| 3724 | ret = i915_gem_execbuffer_pin(dev, file, |
| 3725 | object_list, exec_list, |
| 3726 | args->buffer_count); |
| 3727 | if (ret) |
| 3728 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3729 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3730 | /* The objects are in their final locations, apply the relocations. */ |
| 3731 | for (i = 0; i < args->buffer_count; i++) { |
| 3732 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
| 3733 | obj->base.pending_read_domains = 0; |
| 3734 | obj->base.pending_write_domain = 0; |
| 3735 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3736 | if (ret) |
| 3737 | goto err; |
| 3738 | } |
| 3739 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3740 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3741 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3742 | if (batch_obj->pending_write_domain) { |
| 3743 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3744 | ret = -EINVAL; |
| 3745 | goto err; |
| 3746 | } |
| 3747 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3748 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3749 | /* Sanity check the batch buffer */ |
| 3750 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; |
| 3751 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3752 | if (ret != 0) { |
| 3753 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3754 | goto err; |
| 3755 | } |
| 3756 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3757 | /* Zero the global flush/invalidate flags. These |
| 3758 | * will be modified as new domains are computed |
| 3759 | * for each object |
| 3760 | */ |
| 3761 | dev->invalidate_domains = 0; |
| 3762 | dev->flush_domains = 0; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3763 | dev_priv->mm.flush_rings = 0; |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3764 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | for (i = 0; i < args->buffer_count; i++) { |
| 3766 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3767 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3768 | /* Compute new gpu domains and update invalidate/flush */ |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3769 | i915_gem_object_set_to_gpu_domain(obj, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3770 | } |
| 3771 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3772 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3773 | #if WATCH_EXEC |
| 3774 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3775 | __func__, |
| 3776 | dev->invalidate_domains, |
| 3777 | dev->flush_domains); |
| 3778 | #endif |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3779 | i915_gem_flush(dev, file, |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3780 | dev->invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3781 | dev->flush_domains, |
| 3782 | dev_priv->mm.flush_rings); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3783 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3784 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3785 | for (i = 0; i < args->buffer_count; i++) { |
| 3786 | struct drm_gem_object *obj = object_list[i]; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3787 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3788 | obj->write_domain = obj->pending_write_domain; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3789 | trace_i915_gem_object_change_domain(obj, |
| 3790 | obj->read_domains, |
| 3791 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3792 | } |
| 3793 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3794 | #if WATCH_COHERENCY |
| 3795 | for (i = 0; i < args->buffer_count; i++) { |
| 3796 | i915_gem_object_check_coherency(object_list[i], |
| 3797 | exec_list[i].handle); |
| 3798 | } |
| 3799 | #endif |
| 3800 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3801 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3802 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3803 | args->batch_len, |
| 3804 | __func__, |
| 3805 | ~0); |
| 3806 | #endif |
| 3807 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3808 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 3809 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 3810 | * to executing the batch and avoid stalling the CPU. |
| 3811 | */ |
| 3812 | flips = 0; |
| 3813 | for (i = 0; i < args->buffer_count; i++) { |
| 3814 | if (object_list[i]->write_domain) |
| 3815 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); |
| 3816 | } |
| 3817 | if (flips) { |
| 3818 | int plane, flip_mask; |
| 3819 | |
| 3820 | for (plane = 0; flips >> plane; plane++) { |
| 3821 | if (((flips >> plane) & 1) == 0) |
| 3822 | continue; |
| 3823 | |
| 3824 | if (plane) |
| 3825 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 3826 | else |
| 3827 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 3828 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame^] | 3829 | ret = intel_ring_begin(ring, 2); |
| 3830 | if (ret) |
| 3831 | goto err; |
| 3832 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3833 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 3834 | intel_ring_emit(ring, MI_NOOP); |
| 3835 | intel_ring_advance(ring); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3836 | } |
| 3837 | } |
| 3838 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3839 | /* Exec the batchbuffer */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3840 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3841 | if (ret) { |
| 3842 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3843 | goto err; |
| 3844 | } |
| 3845 | |
| 3846 | /* |
| 3847 | * Ensure that the commands in the batch buffer are |
| 3848 | * finished before the interrupt fires |
| 3849 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3850 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3851 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3852 | for (i = 0; i < args->buffer_count; i++) { |
| 3853 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3854 | |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 3855 | i915_gem_object_move_to_active(obj, ring); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3856 | if (obj->write_domain) |
| 3857 | list_move_tail(&to_intel_bo(obj)->gpu_write_list, |
| 3858 | &ring->gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3859 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3860 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3861 | i915_add_request(dev, file, request, ring); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3862 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3863 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3864 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3865 | for (i = 0; i < args->buffer_count; i++) { |
| 3866 | if (object_list[i]) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3867 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3868 | obj_priv->in_execbuffer = false; |
| 3869 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3870 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3871 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3872 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3873 | mutex_unlock(&dev->struct_mutex); |
| 3874 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3875 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3876 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3877 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3878 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3879 | |
| 3880 | return ret; |
| 3881 | } |
| 3882 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3883 | /* |
| 3884 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3885 | * list array and passes it to the real function. |
| 3886 | */ |
| 3887 | int |
| 3888 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3889 | struct drm_file *file_priv) |
| 3890 | { |
| 3891 | struct drm_i915_gem_execbuffer *args = data; |
| 3892 | struct drm_i915_gem_execbuffer2 exec2; |
| 3893 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3894 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3895 | int ret, i; |
| 3896 | |
| 3897 | #if WATCH_EXEC |
| 3898 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3899 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3900 | #endif |
| 3901 | |
| 3902 | if (args->buffer_count < 1) { |
| 3903 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3904 | return -EINVAL; |
| 3905 | } |
| 3906 | |
| 3907 | /* Copy in the exec list from userland */ |
| 3908 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 3909 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3910 | if (exec_list == NULL || exec2_list == NULL) { |
| 3911 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3912 | args->buffer_count); |
| 3913 | drm_free_large(exec_list); |
| 3914 | drm_free_large(exec2_list); |
| 3915 | return -ENOMEM; |
| 3916 | } |
| 3917 | ret = copy_from_user(exec_list, |
| 3918 | (struct drm_i915_relocation_entry __user *) |
| 3919 | (uintptr_t) args->buffers_ptr, |
| 3920 | sizeof(*exec_list) * args->buffer_count); |
| 3921 | if (ret != 0) { |
| 3922 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3923 | args->buffer_count, ret); |
| 3924 | drm_free_large(exec_list); |
| 3925 | drm_free_large(exec2_list); |
| 3926 | return -EFAULT; |
| 3927 | } |
| 3928 | |
| 3929 | for (i = 0; i < args->buffer_count; i++) { |
| 3930 | exec2_list[i].handle = exec_list[i].handle; |
| 3931 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 3932 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 3933 | exec2_list[i].alignment = exec_list[i].alignment; |
| 3934 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3935 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3936 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 3937 | else |
| 3938 | exec2_list[i].flags = 0; |
| 3939 | } |
| 3940 | |
| 3941 | exec2.buffers_ptr = args->buffers_ptr; |
| 3942 | exec2.buffer_count = args->buffer_count; |
| 3943 | exec2.batch_start_offset = args->batch_start_offset; |
| 3944 | exec2.batch_len = args->batch_len; |
| 3945 | exec2.DR1 = args->DR1; |
| 3946 | exec2.DR4 = args->DR4; |
| 3947 | exec2.num_cliprects = args->num_cliprects; |
| 3948 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3949 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3950 | |
| 3951 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 3952 | if (!ret) { |
| 3953 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3954 | for (i = 0; i < args->buffer_count; i++) |
| 3955 | exec_list[i].offset = exec2_list[i].offset; |
| 3956 | /* ... and back out to userspace */ |
| 3957 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3958 | (uintptr_t) args->buffers_ptr, |
| 3959 | exec_list, |
| 3960 | sizeof(*exec_list) * args->buffer_count); |
| 3961 | if (ret) { |
| 3962 | ret = -EFAULT; |
| 3963 | DRM_ERROR("failed to copy %d exec entries " |
| 3964 | "back to user (%d)\n", |
| 3965 | args->buffer_count, ret); |
| 3966 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3967 | } |
| 3968 | |
| 3969 | drm_free_large(exec_list); |
| 3970 | drm_free_large(exec2_list); |
| 3971 | return ret; |
| 3972 | } |
| 3973 | |
| 3974 | int |
| 3975 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 3976 | struct drm_file *file_priv) |
| 3977 | { |
| 3978 | struct drm_i915_gem_execbuffer2 *args = data; |
| 3979 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3980 | int ret; |
| 3981 | |
| 3982 | #if WATCH_EXEC |
| 3983 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3984 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3985 | #endif |
| 3986 | |
| 3987 | if (args->buffer_count < 1) { |
| 3988 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 3989 | return -EINVAL; |
| 3990 | } |
| 3991 | |
| 3992 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3993 | if (exec2_list == NULL) { |
| 3994 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3995 | args->buffer_count); |
| 3996 | return -ENOMEM; |
| 3997 | } |
| 3998 | ret = copy_from_user(exec2_list, |
| 3999 | (struct drm_i915_relocation_entry __user *) |
| 4000 | (uintptr_t) args->buffers_ptr, |
| 4001 | sizeof(*exec2_list) * args->buffer_count); |
| 4002 | if (ret != 0) { |
| 4003 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4004 | args->buffer_count, ret); |
| 4005 | drm_free_large(exec2_list); |
| 4006 | return -EFAULT; |
| 4007 | } |
| 4008 | |
| 4009 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4010 | if (!ret) { |
| 4011 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4012 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4013 | (uintptr_t) args->buffers_ptr, |
| 4014 | exec2_list, |
| 4015 | sizeof(*exec2_list) * args->buffer_count); |
| 4016 | if (ret) { |
| 4017 | ret = -EFAULT; |
| 4018 | DRM_ERROR("failed to copy %d exec entries " |
| 4019 | "back to user (%d)\n", |
| 4020 | args->buffer_count, ret); |
| 4021 | } |
| 4022 | } |
| 4023 | |
| 4024 | drm_free_large(exec2_list); |
| 4025 | return ret; |
| 4026 | } |
| 4027 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4028 | int |
| 4029 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4030 | { |
| 4031 | struct drm_device *dev = obj->dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4032 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4033 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4034 | int ret; |
| 4035 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4036 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4037 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4038 | |
| 4039 | if (obj_priv->gtt_space != NULL) { |
| 4040 | if (alignment == 0) |
| 4041 | alignment = i915_gem_get_gtt_alignment(obj); |
| 4042 | if (obj_priv->gtt_offset & (alignment - 1)) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4043 | WARN(obj_priv->pin_count, |
| 4044 | "bo is already pinned with incorrect alignment:" |
| 4045 | " offset=%x, req.alignment=%x\n", |
| 4046 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4047 | ret = i915_gem_object_unbind(obj); |
| 4048 | if (ret) |
| 4049 | return ret; |
| 4050 | } |
| 4051 | } |
| 4052 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4053 | if (obj_priv->gtt_space == NULL) { |
| 4054 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4055 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4056 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4057 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4058 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4059 | obj_priv->pin_count++; |
| 4060 | |
| 4061 | /* If the object is not active and not pending a flush, |
| 4062 | * remove it from the inactive list |
| 4063 | */ |
| 4064 | if (obj_priv->pin_count == 1) { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4065 | i915_gem_info_add_pin(dev_priv, obj->size); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4066 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4067 | list_move_tail(&obj_priv->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4068 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4069 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4070 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4071 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4072 | return 0; |
| 4073 | } |
| 4074 | |
| 4075 | void |
| 4076 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4077 | { |
| 4078 | struct drm_device *dev = obj->dev; |
| 4079 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4080 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4081 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4082 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4083 | obj_priv->pin_count--; |
| 4084 | BUG_ON(obj_priv->pin_count < 0); |
| 4085 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4086 | |
| 4087 | /* If the object is no longer pinned, and is |
| 4088 | * neither active nor being flushed, then stick it on |
| 4089 | * the inactive list |
| 4090 | */ |
| 4091 | if (obj_priv->pin_count == 0) { |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4092 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4093 | list_move_tail(&obj_priv->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4094 | &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4095 | i915_gem_info_remove_pin(dev_priv, obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4096 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4097 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4098 | } |
| 4099 | |
| 4100 | int |
| 4101 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4102 | struct drm_file *file_priv) |
| 4103 | { |
| 4104 | struct drm_i915_gem_pin *args = data; |
| 4105 | struct drm_gem_object *obj; |
| 4106 | struct drm_i915_gem_object *obj_priv; |
| 4107 | int ret; |
| 4108 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4109 | ret = i915_mutex_lock_interruptible(dev); |
| 4110 | if (ret) |
| 4111 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4112 | |
| 4113 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4114 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4115 | ret = -ENOENT; |
| 4116 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4117 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4118 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4119 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4120 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4121 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4122 | ret = -EINVAL; |
| 4123 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4124 | } |
| 4125 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4126 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4127 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4128 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4129 | ret = -EINVAL; |
| 4130 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4131 | } |
| 4132 | |
| 4133 | obj_priv->user_pin_count++; |
| 4134 | obj_priv->pin_filp = file_priv; |
| 4135 | if (obj_priv->user_pin_count == 1) { |
| 4136 | ret = i915_gem_object_pin(obj, args->alignment); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4137 | if (ret) |
| 4138 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4139 | } |
| 4140 | |
| 4141 | /* XXX - flush the CPU caches for pinned objects |
| 4142 | * as the X server doesn't manage domains yet |
| 4143 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4144 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4145 | args->offset = obj_priv->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4146 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4147 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4148 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4149 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4150 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4151 | } |
| 4152 | |
| 4153 | int |
| 4154 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4155 | struct drm_file *file_priv) |
| 4156 | { |
| 4157 | struct drm_i915_gem_pin *args = data; |
| 4158 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4159 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4160 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4161 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4162 | ret = i915_mutex_lock_interruptible(dev); |
| 4163 | if (ret) |
| 4164 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4165 | |
| 4166 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4167 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4168 | ret = -ENOENT; |
| 4169 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4170 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4171 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4172 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4173 | if (obj_priv->pin_filp != file_priv) { |
| 4174 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4175 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4176 | ret = -EINVAL; |
| 4177 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4178 | } |
| 4179 | obj_priv->user_pin_count--; |
| 4180 | if (obj_priv->user_pin_count == 0) { |
| 4181 | obj_priv->pin_filp = NULL; |
| 4182 | i915_gem_object_unpin(obj); |
| 4183 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4184 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4185 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4186 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4187 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4188 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4189 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4190 | } |
| 4191 | |
| 4192 | int |
| 4193 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4194 | struct drm_file *file_priv) |
| 4195 | { |
| 4196 | struct drm_i915_gem_busy *args = data; |
| 4197 | struct drm_gem_object *obj; |
| 4198 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4199 | int ret; |
| 4200 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4201 | ret = i915_mutex_lock_interruptible(dev); |
| 4202 | if (ret) |
| 4203 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4204 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4205 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4206 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4207 | ret = -ENOENT; |
| 4208 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4209 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4210 | obj_priv = to_intel_bo(obj); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4211 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4212 | /* Count all active objects as busy, even if they are currently not used |
| 4213 | * by the gpu. Users of this interface expect objects to eventually |
| 4214 | * become non-busy without any further actions, therefore emit any |
| 4215 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4216 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4217 | args->busy = obj_priv->active; |
| 4218 | if (args->busy) { |
| 4219 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4220 | * object. Userspace calling this function indicates that it wants to |
| 4221 | * use this buffer rather sooner than later, so issuing the required |
| 4222 | * flush earlier is beneficial. |
| 4223 | */ |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 4224 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
| 4225 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 4226 | obj_priv->ring, |
| 4227 | 0, obj->write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4228 | |
| 4229 | /* Update the active list for the hardware's current position. |
| 4230 | * Otherwise this only updates on a delayed timer or when irqs |
| 4231 | * are actually unmasked, and our working set ends up being |
| 4232 | * larger than required. |
| 4233 | */ |
| 4234 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4235 | |
| 4236 | args->busy = obj_priv->active; |
| 4237 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4238 | |
| 4239 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4240 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4241 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4242 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4243 | } |
| 4244 | |
| 4245 | int |
| 4246 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4247 | struct drm_file *file_priv) |
| 4248 | { |
| 4249 | return i915_gem_ring_throttle(dev, file_priv); |
| 4250 | } |
| 4251 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4252 | int |
| 4253 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4254 | struct drm_file *file_priv) |
| 4255 | { |
| 4256 | struct drm_i915_gem_madvise *args = data; |
| 4257 | struct drm_gem_object *obj; |
| 4258 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4259 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4260 | |
| 4261 | switch (args->madv) { |
| 4262 | case I915_MADV_DONTNEED: |
| 4263 | case I915_MADV_WILLNEED: |
| 4264 | break; |
| 4265 | default: |
| 4266 | return -EINVAL; |
| 4267 | } |
| 4268 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4269 | ret = i915_mutex_lock_interruptible(dev); |
| 4270 | if (ret) |
| 4271 | return ret; |
| 4272 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4273 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4274 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4275 | ret = -ENOENT; |
| 4276 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4277 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4278 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4279 | |
| 4280 | if (obj_priv->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4281 | ret = -EINVAL; |
| 4282 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4283 | } |
| 4284 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4285 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4286 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4287 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4288 | /* if the object is no longer bound, discard its backing storage */ |
| 4289 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4290 | obj_priv->gtt_space == NULL) |
| 4291 | i915_gem_object_truncate(obj); |
| 4292 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4293 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4294 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4295 | out: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4296 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4297 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4298 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4299 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4300 | } |
| 4301 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4302 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4303 | size_t size) |
| 4304 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4305 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4306 | struct drm_i915_gem_object *obj; |
| 4307 | |
| 4308 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4309 | if (obj == NULL) |
| 4310 | return NULL; |
| 4311 | |
| 4312 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4313 | kfree(obj); |
| 4314 | return NULL; |
| 4315 | } |
| 4316 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4317 | i915_gem_info_add_obj(dev_priv, size); |
| 4318 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4319 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4320 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4321 | |
| 4322 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4323 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4324 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4325 | INIT_LIST_HEAD(&obj->mm_list); |
| 4326 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4327 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4328 | obj->madv = I915_MADV_WILLNEED; |
| 4329 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4330 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4331 | } |
| 4332 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4333 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4334 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4335 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4336 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4337 | return 0; |
| 4338 | } |
| 4339 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4340 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4341 | { |
| 4342 | struct drm_device *dev = obj->dev; |
| 4343 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4344 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4345 | int ret; |
| 4346 | |
| 4347 | ret = i915_gem_object_unbind(obj); |
| 4348 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4349 | list_move(&obj_priv->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4350 | &dev_priv->mm.deferred_free_list); |
| 4351 | return; |
| 4352 | } |
| 4353 | |
| 4354 | if (obj_priv->mmap_offset) |
| 4355 | i915_gem_free_mmap_offset(obj); |
| 4356 | |
| 4357 | drm_gem_object_release(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4358 | i915_gem_info_remove_obj(dev_priv, obj->size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4359 | |
| 4360 | kfree(obj_priv->page_cpu_valid); |
| 4361 | kfree(obj_priv->bit_17); |
| 4362 | kfree(obj_priv); |
| 4363 | } |
| 4364 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4365 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4366 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4367 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4368 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4369 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4370 | trace_i915_gem_object_destroy(obj); |
| 4371 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4372 | while (obj_priv->pin_count > 0) |
| 4373 | i915_gem_object_unpin(obj); |
| 4374 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4375 | if (obj_priv->phys_obj) |
| 4376 | i915_gem_detach_phys_object(dev, obj); |
| 4377 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4378 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4379 | } |
| 4380 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4381 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4382 | i915_gem_idle(struct drm_device *dev) |
| 4383 | { |
| 4384 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4385 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4386 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4387 | mutex_lock(&dev->struct_mutex); |
| 4388 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4389 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4390 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4391 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4392 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4393 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4394 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4395 | if (ret) { |
| 4396 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4397 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4398 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4399 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4400 | /* Under UMS, be paranoid and evict. */ |
| 4401 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4402 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4403 | if (ret) { |
| 4404 | mutex_unlock(&dev->struct_mutex); |
| 4405 | return ret; |
| 4406 | } |
| 4407 | } |
| 4408 | |
| 4409 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4410 | * We need to replace this with a semaphore, or something. |
| 4411 | * And not confound mm.suspended! |
| 4412 | */ |
| 4413 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4414 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4415 | |
| 4416 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4417 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4418 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4419 | mutex_unlock(&dev->struct_mutex); |
| 4420 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4421 | /* Cancel the retire work handler, which should be idle now. */ |
| 4422 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4423 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4424 | return 0; |
| 4425 | } |
| 4426 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4427 | /* |
| 4428 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4429 | * over cache flushing. |
| 4430 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4431 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4432 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4433 | { |
| 4434 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4435 | struct drm_gem_object *obj; |
| 4436 | struct drm_i915_gem_object *obj_priv; |
| 4437 | int ret; |
| 4438 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4439 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4440 | if (obj == NULL) { |
| 4441 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4442 | ret = -ENOMEM; |
| 4443 | goto err; |
| 4444 | } |
| 4445 | obj_priv = to_intel_bo(obj); |
| 4446 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4447 | |
| 4448 | ret = i915_gem_object_pin(obj, 4096); |
| 4449 | if (ret) |
| 4450 | goto err_unref; |
| 4451 | |
| 4452 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4453 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4454 | if (dev_priv->seqno_page == NULL) |
| 4455 | goto err_unpin; |
| 4456 | |
| 4457 | dev_priv->seqno_obj = obj; |
| 4458 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4459 | |
| 4460 | return 0; |
| 4461 | |
| 4462 | err_unpin: |
| 4463 | i915_gem_object_unpin(obj); |
| 4464 | err_unref: |
| 4465 | drm_gem_object_unreference(obj); |
| 4466 | err: |
| 4467 | return ret; |
| 4468 | } |
| 4469 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4470 | |
| 4471 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4472 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4473 | { |
| 4474 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4475 | struct drm_gem_object *obj; |
| 4476 | struct drm_i915_gem_object *obj_priv; |
| 4477 | |
| 4478 | obj = dev_priv->seqno_obj; |
| 4479 | obj_priv = to_intel_bo(obj); |
| 4480 | kunmap(obj_priv->pages[0]); |
| 4481 | i915_gem_object_unpin(obj); |
| 4482 | drm_gem_object_unreference(obj); |
| 4483 | dev_priv->seqno_obj = NULL; |
| 4484 | |
| 4485 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4486 | } |
| 4487 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4488 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4489 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4490 | { |
| 4491 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4492 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4493 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4494 | if (HAS_PIPE_CONTROL(dev)) { |
| 4495 | ret = i915_gem_init_pipe_control(dev); |
| 4496 | if (ret) |
| 4497 | return ret; |
| 4498 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4499 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4500 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4501 | if (ret) |
| 4502 | goto cleanup_pipe_control; |
| 4503 | |
| 4504 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4505 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4506 | if (ret) |
| 4507 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4508 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4509 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4510 | if (HAS_BLT(dev)) { |
| 4511 | ret = intel_init_blt_ring_buffer(dev); |
| 4512 | if (ret) |
| 4513 | goto cleanup_bsd_ring; |
| 4514 | } |
| 4515 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4516 | dev_priv->next_seqno = 1; |
| 4517 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4518 | return 0; |
| 4519 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4520 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4521 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4522 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4523 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4524 | cleanup_pipe_control: |
| 4525 | if (HAS_PIPE_CONTROL(dev)) |
| 4526 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4527 | return ret; |
| 4528 | } |
| 4529 | |
| 4530 | void |
| 4531 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4532 | { |
| 4533 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4534 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4535 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 4536 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 4537 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4538 | if (HAS_PIPE_CONTROL(dev)) |
| 4539 | i915_gem_cleanup_pipe_control(dev); |
| 4540 | } |
| 4541 | |
| 4542 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4543 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4544 | struct drm_file *file_priv) |
| 4545 | { |
| 4546 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4547 | int ret; |
| 4548 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4549 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4550 | return 0; |
| 4551 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4552 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4553 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4554 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4555 | } |
| 4556 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4557 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4558 | dev_priv->mm.suspended = 0; |
| 4559 | |
| 4560 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4561 | if (ret != 0) { |
| 4562 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4563 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4564 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4565 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4566 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4567 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4568 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4569 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4570 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4571 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4572 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4573 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4574 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4575 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4576 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4577 | ret = drm_irq_install(dev); |
| 4578 | if (ret) |
| 4579 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4580 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4581 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4582 | |
| 4583 | cleanup_ringbuffer: |
| 4584 | mutex_lock(&dev->struct_mutex); |
| 4585 | i915_gem_cleanup_ringbuffer(dev); |
| 4586 | dev_priv->mm.suspended = 1; |
| 4587 | mutex_unlock(&dev->struct_mutex); |
| 4588 | |
| 4589 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4590 | } |
| 4591 | |
| 4592 | int |
| 4593 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4594 | struct drm_file *file_priv) |
| 4595 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4596 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4597 | return 0; |
| 4598 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4599 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4600 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4601 | } |
| 4602 | |
| 4603 | void |
| 4604 | i915_gem_lastclose(struct drm_device *dev) |
| 4605 | { |
| 4606 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4607 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4608 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4609 | return; |
| 4610 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4611 | ret = i915_gem_idle(dev); |
| 4612 | if (ret) |
| 4613 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4614 | } |
| 4615 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4616 | static void |
| 4617 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4618 | { |
| 4619 | INIT_LIST_HEAD(&ring->active_list); |
| 4620 | INIT_LIST_HEAD(&ring->request_list); |
| 4621 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 4622 | } |
| 4623 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4624 | void |
| 4625 | i915_gem_load(struct drm_device *dev) |
| 4626 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4627 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4628 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4629 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4630 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4631 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4632 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4633 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4634 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4635 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4636 | init_ring_lists(&dev_priv->render_ring); |
| 4637 | init_ring_lists(&dev_priv->bsd_ring); |
| 4638 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4639 | for (i = 0; i < 16; i++) |
| 4640 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4641 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4642 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4643 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4644 | spin_lock(&shrink_list_lock); |
| 4645 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4646 | spin_unlock(&shrink_list_lock); |
| 4647 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4648 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4649 | if (IS_GEN3(dev)) { |
| 4650 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4651 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4652 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4653 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4654 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4655 | } |
| 4656 | } |
| 4657 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4658 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4659 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4660 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4661 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4662 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4663 | dev_priv->num_fence_regs = 16; |
| 4664 | else |
| 4665 | dev_priv->num_fence_regs = 8; |
| 4666 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4667 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4668 | switch (INTEL_INFO(dev)->gen) { |
| 4669 | case 6: |
| 4670 | for (i = 0; i < 16; i++) |
| 4671 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4672 | break; |
| 4673 | case 5: |
| 4674 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4675 | for (i = 0; i < 16; i++) |
| 4676 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4677 | break; |
| 4678 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4679 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4680 | for (i = 0; i < 8; i++) |
| 4681 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4682 | case 2: |
| 4683 | for (i = 0; i < 8; i++) |
| 4684 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4685 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4686 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4687 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4688 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4689 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4690 | |
| 4691 | /* |
| 4692 | * Create a physically contiguous memory object for this object |
| 4693 | * e.g. for cursor + overlay regs |
| 4694 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4695 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4696 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4697 | { |
| 4698 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4699 | struct drm_i915_gem_phys_object *phys_obj; |
| 4700 | int ret; |
| 4701 | |
| 4702 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4703 | return 0; |
| 4704 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4705 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4706 | if (!phys_obj) |
| 4707 | return -ENOMEM; |
| 4708 | |
| 4709 | phys_obj->id = id; |
| 4710 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4711 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4712 | if (!phys_obj->handle) { |
| 4713 | ret = -ENOMEM; |
| 4714 | goto kfree_obj; |
| 4715 | } |
| 4716 | #ifdef CONFIG_X86 |
| 4717 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4718 | #endif |
| 4719 | |
| 4720 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4721 | |
| 4722 | return 0; |
| 4723 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4724 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4725 | return ret; |
| 4726 | } |
| 4727 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4728 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4729 | { |
| 4730 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4731 | struct drm_i915_gem_phys_object *phys_obj; |
| 4732 | |
| 4733 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4734 | return; |
| 4735 | |
| 4736 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4737 | if (phys_obj->cur_obj) { |
| 4738 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4739 | } |
| 4740 | |
| 4741 | #ifdef CONFIG_X86 |
| 4742 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4743 | #endif |
| 4744 | drm_pci_free(dev, phys_obj->handle); |
| 4745 | kfree(phys_obj); |
| 4746 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4747 | } |
| 4748 | |
| 4749 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4750 | { |
| 4751 | int i; |
| 4752 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4753 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4754 | i915_gem_free_phys_object(dev, i); |
| 4755 | } |
| 4756 | |
| 4757 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4758 | struct drm_gem_object *obj) |
| 4759 | { |
| 4760 | struct drm_i915_gem_object *obj_priv; |
| 4761 | int i; |
| 4762 | int ret; |
| 4763 | int page_count; |
| 4764 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4765 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4766 | if (!obj_priv->phys_obj) |
| 4767 | return; |
| 4768 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4769 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4770 | if (ret) |
| 4771 | goto out; |
| 4772 | |
| 4773 | page_count = obj->size / PAGE_SIZE; |
| 4774 | |
| 4775 | for (i = 0; i < page_count; i++) { |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4776 | char *dst = kmap_atomic(obj_priv->pages[i]); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4777 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4778 | |
| 4779 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4780 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4781 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4782 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4783 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4784 | |
| 4785 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4786 | out: |
| 4787 | obj_priv->phys_obj->cur_obj = NULL; |
| 4788 | obj_priv->phys_obj = NULL; |
| 4789 | } |
| 4790 | |
| 4791 | int |
| 4792 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4793 | struct drm_gem_object *obj, |
| 4794 | int id, |
| 4795 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4796 | { |
| 4797 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4798 | struct drm_i915_gem_object *obj_priv; |
| 4799 | int ret = 0; |
| 4800 | int page_count; |
| 4801 | int i; |
| 4802 | |
| 4803 | if (id > I915_MAX_PHYS_OBJECT) |
| 4804 | return -EINVAL; |
| 4805 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4806 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4807 | |
| 4808 | if (obj_priv->phys_obj) { |
| 4809 | if (obj_priv->phys_obj->id == id) |
| 4810 | return 0; |
| 4811 | i915_gem_detach_phys_object(dev, obj); |
| 4812 | } |
| 4813 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4814 | /* create a new object */ |
| 4815 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4816 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4817 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4818 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4819 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4820 | goto out; |
| 4821 | } |
| 4822 | } |
| 4823 | |
| 4824 | /* bind to the object */ |
| 4825 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4826 | obj_priv->phys_obj->cur_obj = obj; |
| 4827 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4828 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4829 | if (ret) { |
| 4830 | DRM_ERROR("failed to get page list\n"); |
| 4831 | goto out; |
| 4832 | } |
| 4833 | |
| 4834 | page_count = obj->size / PAGE_SIZE; |
| 4835 | |
| 4836 | for (i = 0; i < page_count; i++) { |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4837 | char *src = kmap_atomic(obj_priv->pages[i]); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4838 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4839 | |
| 4840 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4841 | kunmap_atomic(src); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4842 | } |
| 4843 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4844 | i915_gem_object_put_pages(obj); |
| 4845 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4846 | return 0; |
| 4847 | out: |
| 4848 | return ret; |
| 4849 | } |
| 4850 | |
| 4851 | static int |
| 4852 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4853 | struct drm_i915_gem_pwrite *args, |
| 4854 | struct drm_file *file_priv) |
| 4855 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4856 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4857 | void *obj_addr; |
| 4858 | int ret; |
| 4859 | char __user *user_data; |
| 4860 | |
| 4861 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4862 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4863 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4864 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4865 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4866 | if (ret) |
| 4867 | return -EFAULT; |
| 4868 | |
| 4869 | drm_agp_chipset_flush(dev); |
| 4870 | return 0; |
| 4871 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4872 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4873 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4874 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4875 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4876 | |
| 4877 | /* Clean up our request list when the client is going away, so that |
| 4878 | * later retire_requests won't dereference our soon-to-be-gone |
| 4879 | * file_priv. |
| 4880 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4881 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4882 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4883 | struct drm_i915_gem_request *request; |
| 4884 | |
| 4885 | request = list_first_entry(&file_priv->mm.request_list, |
| 4886 | struct drm_i915_gem_request, |
| 4887 | client_list); |
| 4888 | list_del(&request->client_list); |
| 4889 | request->file_priv = NULL; |
| 4890 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4891 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4892 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4893 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4894 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4895 | i915_gpu_is_active(struct drm_device *dev) |
| 4896 | { |
| 4897 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4898 | int lists_empty; |
| 4899 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4900 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4901 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4902 | list_empty(&dev_priv->bsd_ring.active_list) && |
| 4903 | list_empty(&dev_priv->blt_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4904 | |
| 4905 | return !lists_empty; |
| 4906 | } |
| 4907 | |
| 4908 | static int |
Dave Chinner | 7f8275d | 2010-07-19 14:56:17 +1000 | [diff] [blame] | 4909 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4910 | { |
| 4911 | drm_i915_private_t *dev_priv, *next_dev; |
| 4912 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4913 | int cnt = 0; |
| 4914 | int would_deadlock = 1; |
| 4915 | |
| 4916 | /* "fast-path" to count number of available objects */ |
| 4917 | if (nr_to_scan == 0) { |
| 4918 | spin_lock(&shrink_list_lock); |
| 4919 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4920 | struct drm_device *dev = dev_priv->dev; |
| 4921 | |
| 4922 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4923 | list_for_each_entry(obj_priv, |
| 4924 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4925 | mm_list) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4926 | cnt++; |
| 4927 | mutex_unlock(&dev->struct_mutex); |
| 4928 | } |
| 4929 | } |
| 4930 | spin_unlock(&shrink_list_lock); |
| 4931 | |
| 4932 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4933 | } |
| 4934 | |
| 4935 | spin_lock(&shrink_list_lock); |
| 4936 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4937 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4938 | /* first scan for clean buffers */ |
| 4939 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4940 | &shrink_list, mm.shrink_list) { |
| 4941 | struct drm_device *dev = dev_priv->dev; |
| 4942 | |
| 4943 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4944 | continue; |
| 4945 | |
| 4946 | spin_unlock(&shrink_list_lock); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 4947 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4948 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4949 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4950 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4951 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4952 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4953 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4954 | if (--nr_to_scan <= 0) |
| 4955 | break; |
| 4956 | } |
| 4957 | } |
| 4958 | |
| 4959 | spin_lock(&shrink_list_lock); |
| 4960 | mutex_unlock(&dev->struct_mutex); |
| 4961 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4962 | would_deadlock = 0; |
| 4963 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4964 | if (nr_to_scan <= 0) |
| 4965 | break; |
| 4966 | } |
| 4967 | |
| 4968 | /* second pass, evict/count anything still on the inactive list */ |
| 4969 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4970 | &shrink_list, mm.shrink_list) { |
| 4971 | struct drm_device *dev = dev_priv->dev; |
| 4972 | |
| 4973 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4974 | continue; |
| 4975 | |
| 4976 | spin_unlock(&shrink_list_lock); |
| 4977 | |
| 4978 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4979 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4980 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4981 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4982 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4983 | nr_to_scan--; |
| 4984 | } else |
| 4985 | cnt++; |
| 4986 | } |
| 4987 | |
| 4988 | spin_lock(&shrink_list_lock); |
| 4989 | mutex_unlock(&dev->struct_mutex); |
| 4990 | |
| 4991 | would_deadlock = 0; |
| 4992 | } |
| 4993 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4994 | if (nr_to_scan) { |
| 4995 | int active = 0; |
| 4996 | |
| 4997 | /* |
| 4998 | * We are desperate for pages, so as a last resort, wait |
| 4999 | * for the GPU to finish and discard whatever we can. |
| 5000 | * This has a dramatic impact to reduce the number of |
| 5001 | * OOM-killer events whilst running the GPU aggressively. |
| 5002 | */ |
| 5003 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5004 | struct drm_device *dev = dev_priv->dev; |
| 5005 | |
| 5006 | if (!mutex_trylock(&dev->struct_mutex)) |
| 5007 | continue; |
| 5008 | |
| 5009 | spin_unlock(&shrink_list_lock); |
| 5010 | |
| 5011 | if (i915_gpu_is_active(dev)) { |
| 5012 | i915_gpu_idle(dev); |
| 5013 | active++; |
| 5014 | } |
| 5015 | |
| 5016 | spin_lock(&shrink_list_lock); |
| 5017 | mutex_unlock(&dev->struct_mutex); |
| 5018 | } |
| 5019 | |
| 5020 | if (active) |
| 5021 | goto rescan; |
| 5022 | } |
| 5023 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5024 | spin_unlock(&shrink_list_lock); |
| 5025 | |
| 5026 | if (would_deadlock) |
| 5027 | return -1; |
| 5028 | else if (cnt > 0) |
| 5029 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5030 | else |
| 5031 | return 0; |
| 5032 | } |
| 5033 | |
| 5034 | static struct shrinker shrinker = { |
| 5035 | .shrink = i915_gem_shrink, |
| 5036 | .seeks = DEFAULT_SEEKS, |
| 5037 | }; |
| 5038 | |
| 5039 | __init void |
| 5040 | i915_gem_shrinker_init(void) |
| 5041 | { |
| 5042 | register_shrinker(&shrinker); |
| 5043 | } |
| 5044 | |
| 5045 | __exit void |
| 5046 | i915_gem_shrinker_exit(void) |
| 5047 | { |
| 5048 | unregister_shrinker(&shrinker); |
| 5049 | } |