Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 2b5cdbb3de3c92faa2b63f33b8054060b5e363cd / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 987ff6cab2ccd29edc4878a2da595865f8589f1b [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]82
83 // A vector type of the same width with element type i32. This is used to
84 // create the canonical constant zero node ImmAllZerosV.
85 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
86 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]87}
88
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]89def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
90def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]91def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
92def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]93def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
94def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]95
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]96// "x" in v32i8x_info means RC = VR256X
97def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
98def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
99def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
100def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
101
102def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
103def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
104def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
105def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
106
107class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
108 X86VectorVTInfo i128> {
109 X86VectorVTInfo info512 = i512;
110 X86VectorVTInfo info256 = i256;
111 X86VectorVTInfo info128 = i128;
112}
113
114def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
115 v16i8x_info>;
116def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
117 v8i16x_info>;
118def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
119 v4i32x_info>;
120def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
121 v2i64x_info>;
122
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]123// This multiclass generates the masking variants from the non-masking
124// variant. It only provides the assembly pieces for the masking variants.
125// It assumes custom ISel patterns for masking which can be provided as
126// template arguments.
127multiclass AVX512_masking_custom<bits<8> O, Format F,
128 dag Outs,
129 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
130 string OpcodeStr,
131 string AttSrcAsm, string IntelSrcAsm,
132 list<dag> Pattern,
133 list<dag> MaskingPattern,
134 list<dag> ZeroMaskingPattern,
135 string MaskingConstraint = "",
136 InstrItinClass itin = NoItinerary,
137 bit IsCommutable = 0> {
138 let isCommutable = IsCommutable in
139 def NAME: AVX512<O, F, Outs, Ins,
140 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
141 "$dst, "#IntelSrcAsm#"}",
142 Pattern, itin>;
143
144 // Prefer over VMOV*rrk Pat<>
145 let AddedComplexity = 20 in
146 def NAME#k: AVX512<O, F, Outs, MaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
148 "$dst {${mask}}, "#IntelSrcAsm#"}",
149 MaskingPattern, itin>,
150 EVEX_K {
151 // In case of the 3src subclass this is overridden with a let.
152 string Constraints = MaskingConstraint;
153 }
154 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
155 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
156 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
157 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
158 ZeroMaskingPattern,
159 itin>,
160 EVEX_KZ;
161}
162
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]163
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]164// Common base class of AVX512_masking and AVX512_masking_3src.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]165multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
166 dag Outs,
167 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]168 string OpcodeStr,
169 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]170 dag RHS, dag MaskingRHS,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]171 string MaskingConstraint = "",
172 InstrItinClass itin = NoItinerary,
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]173 bit IsCommutable = 0> :
174 AVX512_masking_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
175 AttSrcAsm, IntelSrcAsm,
176 [(set _.RC:$dst, RHS)],
177 [(set _.RC:$dst, MaskingRHS)],
178 [(set _.RC:$dst,
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]179 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]180 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]181
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]182// This multiclass generates the unconditional/non-masking, the masking and
183// the zero-masking variant of the instruction. In the masking case, the
184// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]185multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
186 dag Outs, dag Ins, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]187 string AttSrcAsm, string IntelSrcAsm,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]188 dag RHS, InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]190 AVX512_masking_common<O, F, _, Outs, Ins,
191 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
192 !con((ins _.KRCWM:$mask), Ins),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]193 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]194 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]195 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]196
197// Similar to AVX512_masking but in this case one of the source operands
198// ($src1) is already tied to $dst so we just use that for the preserved
199// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
200// $src1.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]201multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag NonTiedIns, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]203 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]204 dag RHS> :
205 AVX512_masking_common<O, F, _, Outs,
206 !con((ins _.RC:$src1), NonTiedIns),
207 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
208 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]209 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]210 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]211
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame^]212
213multiclass AVX512_masking_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
214 dag Outs, dag Ins,
215 string OpcodeStr,
216 string AttSrcAsm, string IntelSrcAsm,
217 list<dag> Pattern> :
218 AVX512_masking_custom<O, F, Outs, Ins,
219 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
220 !con((ins _.KRCWM:$mask), Ins),
221 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
222 "$src0 = $dst">;
223
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]224// Bitcasts between 512-bit vector types. Return the original type since
225// no instruction is needed for the conversion
226let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]227 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]228 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]229 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
230 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
231 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]232 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]233 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
234 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
235 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]236 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]237 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]238 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
239 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]240 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]241 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
242 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]243 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]244 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
245 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]247 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
248 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
249 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
250 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
251 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
252 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
253 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
254 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
255 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
256 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
257 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]258
259 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
260 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
261 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
262 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
263 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
264 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
265 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
266 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
267 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
268 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
269 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
270 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
271 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
272 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
273 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
274 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
275 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
276 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
277 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
278 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
279 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
280 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
281 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
282 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
283 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
284 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
285 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
286 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
287 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
288 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
289
290// Bitcasts between 256-bit vector types. Return the original type since
291// no instruction is needed for the conversion
292 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
293 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
294 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
295 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
296 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
297 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
298 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
299 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
300 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
301 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
302 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
303 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
304 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
305 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
306 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
307 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
308 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
309 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
310 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
311 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
312 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
313 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
314 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
315 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
316 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
317 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
318 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
319 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
320 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
321 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
322}
323
324//
325// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
326//
327
328let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
329 isPseudo = 1, Predicates = [HasAVX512] in {
330def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
331 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
332}
333
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]334let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]335def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
336def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
337def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]338}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]339
340//===----------------------------------------------------------------------===//
341// AVX-512 - VECTOR INSERT
342//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]343
344multiclass vinsert_for_size<int Opcode,
345 X86VectorVTInfo From, X86VectorVTInfo To,
346 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
347 PatFrag vinsert_insert,
348 SDNodeXForm INSERT_get_vinsert_imm> {
349 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
350 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
351 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
352 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
353 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]354 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
355 (From.VT From.RC:$src2),
356 (iPTR imm)))]>,
357 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]358
359 let mayLoad = 1 in
360 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
361 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
362 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
363 "$dst, $src1, $src2, $src3}",
364 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
365 }
366
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]367 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
368 // vinserti32x4
369 def : Pat<(vinsert_insert:$ins
370 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
371 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
372 VR512:$src1, From.RC:$src2,
373 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]374}
375
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]376multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
377 ValueType EltVT64, int Opcode64> {
378 defm NAME # "32x4" : vinsert_for_size<Opcode32,
379 X86VectorVTInfo< 4, EltVT32, VR128X>,
380 X86VectorVTInfo<16, EltVT32, VR512>,
381 X86VectorVTInfo< 2, EltVT64, VR128X>,
382 X86VectorVTInfo< 8, EltVT64, VR512>,
383 vinsert128_insert,
384 INSERT_get_vinsert128_imm>;
385 defm NAME # "64x4" : vinsert_for_size<Opcode64,
386 X86VectorVTInfo< 4, EltVT64, VR256X>,
387 X86VectorVTInfo< 8, EltVT64, VR512>,
388 X86VectorVTInfo< 8, EltVT32, VR256>,
389 X86VectorVTInfo<16, EltVT32, VR512>,
390 vinsert256_insert,
391 INSERT_get_vinsert256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]392}
393
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]394defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
395defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]396
397// vinsertps - insert f32 to XMM
398def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]399 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]400 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]401 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]402 EVEX_4V;
403def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]404 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]405 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]406 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]407 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
408 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
409
410//===----------------------------------------------------------------------===//
411// AVX-512 VECTOR EXTRACT
412//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]413
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]414multiclass vextract_for_size<int Opcode,
415 X86VectorVTInfo From, X86VectorVTInfo To,
416 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
417 PatFrag vextract_extract,
418 SDNodeXForm EXTRACT_get_vextract_imm> {
419 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame^]420 defm rr : AVX512_masking_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
421 (ins VR512:$src1, i8imm:$idx),
422 "vextract" # To.EltTypeName # "x4",
423 "$idx, $src1", "$src1, $idx",
424 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
425 (iPTR imm)))]>,
426 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]427 let mayStore = 1 in
428 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
429 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
430 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
431 "$dst, $src1, $src2}",
432 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
433 }
434
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]435 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
436 // vextracti32x4
437 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
438 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
439 VR512:$src1,
440 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
441
442 // A 128/256-bit subvector extract from the first 512-bit vector position is
443 // a subregister copy that needs no instruction.
444 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
445 (To.VT
446 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
447
448 // And for the alternative types.
449 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
450 (AltTo.VT
451 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]452}
453
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]454multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
455 ValueType EltVT64, int Opcode64> {
456 defm NAME # "32x4" : vextract_for_size<Opcode32,
457 X86VectorVTInfo<16, EltVT32, VR512>,
458 X86VectorVTInfo< 4, EltVT32, VR128X>,
459 X86VectorVTInfo< 8, EltVT64, VR512>,
460 X86VectorVTInfo< 2, EltVT64, VR128X>,
461 vextract128_extract,
462 EXTRACT_get_vextract128_imm>;
463 defm NAME # "64x4" : vextract_for_size<Opcode64,
464 X86VectorVTInfo< 8, EltVT64, VR512>,
465 X86VectorVTInfo< 4, EltVT64, VR256X>,
466 X86VectorVTInfo<16, EltVT32, VR512>,
467 X86VectorVTInfo< 8, EltVT32, VR256>,
468 vextract256_extract,
469 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]470}
471
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]472defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
473defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]474
475// A 128-bit subvector insert to the first 512-bit vector position
476// is a subregister copy that needs no instruction.
477def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
478 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
479 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
480 sub_ymm)>;
481def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
482 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
483 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
484 sub_ymm)>;
485def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
486 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
487 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
488 sub_ymm)>;
489def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
490 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
491 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
492 sub_ymm)>;
493
494def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
495 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
496def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
497 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
498def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
499 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
500def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
501 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
502
503// vextractps - extract 32 bits from XMM
504def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]505 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]506 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]507 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
508 EVEX;
509
510def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]511 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]512 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]513 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]514 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]515
516//===---------------------------------------------------------------------===//
517// AVX-512 BROADCAST
518//---
519multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
520 RegisterClass DestRC,
521 RegisterClass SrcRC, X86MemOperand x86memop> {
522 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]523 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]524 []>, EVEX;
525 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]526 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]527}
528let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]529 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]530 VR128X, f32mem>,
531 EVEX_V512, EVEX_CD8<32, CD8VT1>;
532}
533
534let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]535 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]536 VR128X, f64mem>,
537 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
538}
539
540def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
541 (VBROADCASTSSZrm addr:$src)>;
542def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
543 (VBROADCASTSDZrm addr:$src)>;
544
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]545def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
546 (VBROADCASTSSZrm addr:$src)>;
547def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
548 (VBROADCASTSDZrm addr:$src)>;
549
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]550multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
551 RegisterClass SrcRC, RegisterClass KRC> {
552 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]553 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]554 []>, EVEX, EVEX_V512;
555 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
556 (ins KRC:$mask, SrcRC:$src),
557 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]558 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]559 []>, EVEX, EVEX_V512, EVEX_KZ;
560}
561
562defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
563defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
564 VEX_W;
565
566def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
567 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
568
569def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
570 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
571
572def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
573 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]574def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
575 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]576def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
577 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]578def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
579 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]580
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]581def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
582 (VPBROADCASTDrZrr GR32:$src)>;
583def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
584 (VPBROADCASTQrZrr GR64:$src)>;
585
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]586def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
587 (v16i32 immAllZerosV), (i16 GR16:$mask))),
588 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
589def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
590 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
591 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
592
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]593multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
594 X86MemOperand x86memop, PatFrag ld_frag,
595 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
596 RegisterClass KRC> {
597 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]598 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]599 [(set DstRC:$dst,
600 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
601 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
602 VR128X:$src),
603 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]604 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]605 [(set DstRC:$dst,
606 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
607 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]608 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]609 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]610 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]611 [(set DstRC:$dst,
612 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
613 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
614 x86memop:$src),
615 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]616 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]617 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
618 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]619 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]620}
621
622defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
623 loadi32, VR512, v16i32, v4i32, VK16WM>,
624 EVEX_V512, EVEX_CD8<32, CD8VT1>;
625defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
626 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
627 EVEX_CD8<64, CD8VT1>;
628
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]629multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
630 X86MemOperand x86memop, PatFrag ld_frag,
631 RegisterClass KRC> {
632 let mayLoad = 1 in {
633 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
634 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
635 []>, EVEX;
636 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
637 x86memop:$src),
638 !strconcat(OpcodeStr,
639 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
640 []>, EVEX, EVEX_KZ;
641 }
642}
643
644defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
645 i128mem, loadv2i64, VK16WM>,
646 EVEX_V512, EVEX_CD8<32, CD8VT4>;
647defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
648 i256mem, loadv4i64, VK16WM>, VEX_W,
649 EVEX_V512, EVEX_CD8<64, CD8VT4>;
650
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]651def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
652 (VPBROADCASTDZrr VR128X:$src)>;
653def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
654 (VPBROADCASTQZrr VR128X:$src)>;
655
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]656def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
657 (VBROADCASTSSZrr VR128X:$src)>;
658def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
659 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]660
661def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
662 (VBROADCASTSSZrr VR128X:$src)>;
663def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
664 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]665
666// Provide fallback in case the load node that is used in the patterns above
667// is used by additional users, which prevents the pattern selection.
668def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
669 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
670def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
671 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
672
673
674let Predicates = [HasAVX512] in {
675def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
676 (EXTRACT_SUBREG
677 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
678 addr:$src)), sub_ymm)>;
679}
680//===----------------------------------------------------------------------===//
681// AVX-512 BROADCAST MASK TO VECTOR REGISTER
682//---
683
684multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
685 RegisterClass DstRC, RegisterClass KRC,
686 ValueType OpVT, ValueType SrcVT> {
687def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]688 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]689 []>, EVEX;
690}
691
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]692let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]693defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
694 VK16, v16i32, v16i1>, EVEX_V512;
695defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
696 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]697}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]698
699//===----------------------------------------------------------------------===//
700// AVX-512 - VPERM
701//
702// -- immediate form --
703multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
704 SDNode OpNode, PatFrag mem_frag,
705 X86MemOperand x86memop, ValueType OpVT> {
706 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
707 (ins RC:$src1, i8imm:$src2),
708 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]709 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]710 [(set RC:$dst,
711 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
712 EVEX;
713 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
714 (ins x86memop:$src1, i8imm:$src2),
715 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]716 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]717 [(set RC:$dst,
718 (OpVT (OpNode (mem_frag addr:$src1),
719 (i8 imm:$src2))))]>, EVEX;
720}
721
722defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
723 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
724let ExeDomain = SSEPackedDouble in
725defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
726 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
727
728// -- VPERM - register form --
729multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
730 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
731
732 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
733 (ins RC:$src1, RC:$src2),
734 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]735 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]736 [(set RC:$dst,
737 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
738
739 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
740 (ins RC:$src1, x86memop:$src2),
741 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]742 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]743 [(set RC:$dst,
744 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
745 EVEX_4V;
746}
747
748defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
749 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
750defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
751 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
752let ExeDomain = SSEPackedSingle in
753defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
754 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
755let ExeDomain = SSEPackedDouble in
756defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
757 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
758
759// -- VPERM2I - 3 source operands form --
760multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
761 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]762 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]763let Constraints = "$src1 = $dst" in {
764 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
765 (ins RC:$src1, RC:$src2, RC:$src3),
766 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]767 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]768 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]769 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]770 EVEX_4V;
771
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]772 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
773 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
774 !strconcat(OpcodeStr,
775 " \t{$src3, $src2, $dst {${mask}}|"
776 "$dst {${mask}}, $src2, $src3}"),
777 [(set RC:$dst, (OpVT (vselect KRC:$mask,
778 (OpNode RC:$src1, RC:$src2,
779 RC:$src3),
780 RC:$src1)))]>,
781 EVEX_4V, EVEX_K;
782
783 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
784 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
785 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
786 !strconcat(OpcodeStr,
787 " \t{$src3, $src2, $dst {${mask}} {z} |",
788 "$dst {${mask}} {z}, $src2, $src3}"),
789 [(set RC:$dst, (OpVT (vselect KRC:$mask,
790 (OpNode RC:$src1, RC:$src2,
791 RC:$src3),
792 (OpVT (bitconvert
793 (v16i32 immAllZerosV))))))]>,
794 EVEX_4V, EVEX_KZ;
795
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]796 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
797 (ins RC:$src1, RC:$src2, x86memop:$src3),
798 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]799 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]800 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]801 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]802 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]803
804 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
805 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
806 !strconcat(OpcodeStr,
807 " \t{$src3, $src2, $dst {${mask}}|"
808 "$dst {${mask}}, $src2, $src3}"),
809 [(set RC:$dst,
810 (OpVT (vselect KRC:$mask,
811 (OpNode RC:$src1, RC:$src2,
812 (mem_frag addr:$src3)),
813 RC:$src1)))]>,
814 EVEX_4V, EVEX_K;
815
816 let AddedComplexity = 10 in // Prefer over the rrkz variant
817 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
818 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
819 !strconcat(OpcodeStr,
820 " \t{$src3, $src2, $dst {${mask}} {z}|"
821 "$dst {${mask}} {z}, $src2, $src3}"),
822 [(set RC:$dst,
823 (OpVT (vselect KRC:$mask,
824 (OpNode RC:$src1, RC:$src2,
825 (mem_frag addr:$src3)),
826 (OpVT (bitconvert
827 (v16i32 immAllZerosV))))))]>,
828 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]829 }
830}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]831defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
832 i512mem, X86VPermiv3, v16i32, VK16WM>,
833 EVEX_V512, EVEX_CD8<32, CD8VF>;
834defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
835 i512mem, X86VPermiv3, v8i64, VK8WM>,
836 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
837defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
838 i512mem, X86VPermiv3, v16f32, VK16WM>,
839 EVEX_V512, EVEX_CD8<32, CD8VF>;
840defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
841 i512mem, X86VPermiv3, v8f64, VK8WM>,
842 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]843
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]844multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
845 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]846 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
847 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]848 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
849 OpVT, KRC> {
850 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
851 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
852 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]853
854 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
855 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
856 (!cast<Instruction>(NAME#rrk) VR512:$src1,
857 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]858}
859
860defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]861 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
862 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]863defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]864 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
865 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]866defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]867 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
868 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]869defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]870 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
871 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]872
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]873//===----------------------------------------------------------------------===//
874// AVX-512 - BLEND using mask
875//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]876multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]877 RegisterClass KRC, RegisterClass RC,
878 X86MemOperand x86memop, PatFrag mem_frag,
879 SDNode OpNode, ValueType vt> {
880 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]881 (ins KRC:$mask, RC:$src1, RC:$src2),
882 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]883 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]884 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]885 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]886 let mayLoad = 1 in
887 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
888 (ins KRC:$mask, RC:$src1, x86memop:$src2),
889 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]890 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]891 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]892}
893
894let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]895defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]896 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]897 memopv16f32, vselect, v16f32>,
898 EVEX_CD8<32, CD8VF>, EVEX_V512;
899let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]900defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]901 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]902 memopv8f64, vselect, v8f64>,
903 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
904
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]905def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
906 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]907 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]908 VR512:$src1, VR512:$src2)>;
909
910def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
911 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]912 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]913 VR512:$src1, VR512:$src2)>;
914
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]915defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]916 VK16WM, VR512, f512mem,
917 memopv16i32, vselect, v16i32>,
918 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]919
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]920defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]921 VK8WM, VR512, f512mem,
922 memopv8i64, vselect, v8i64>,
923 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]924
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]925def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
926 (v16i32 VR512:$src2), (i16 GR16:$mask))),
927 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
928 VR512:$src1, VR512:$src2)>;
929
930def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
931 (v8i64 VR512:$src2), (i8 GR8:$mask))),
932 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
933 VR512:$src1, VR512:$src2)>;
934
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]935let Predicates = [HasAVX512] in {
936def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
937 (v8f32 VR256X:$src2))),
938 (EXTRACT_SUBREG
939 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
940 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
941 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
942
943def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
944 (v8i32 VR256X:$src2))),
945 (EXTRACT_SUBREG
946 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
947 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
948 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
949}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]950//===----------------------------------------------------------------------===//
951// Compare Instructions
952//===----------------------------------------------------------------------===//
953
954// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
955multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
956 Operand CC, SDNode OpNode, ValueType VT,
957 PatFrag ld_frag, string asm, string asm_alt> {
958 def rr : AVX512Ii8<0xC2, MRMSrcReg,
959 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
960 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
961 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
962 def rm : AVX512Ii8<0xC2, MRMSrcMem,
963 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
964 [(set VK1:$dst, (OpNode (VT RC:$src1),
965 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]966 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]967 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
968 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
969 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
970 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
971 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
972 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
973 }
974}
975
976let Predicates = [HasAVX512] in {
977defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
978 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
979 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
980 XS;
981defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
982 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
983 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
984 XD, VEX_W;
985}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]986
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]987multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
988 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]989 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]990 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
991 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
992 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]993 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]994 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]995 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]996 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
998 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
999 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1000 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1001 def rrk : AVX512BI<opc, MRMSrcReg,
1002 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1004 "$dst {${mask}}, $src1, $src2}"),
1005 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1006 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1007 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1008 let mayLoad = 1 in
1009 def rmk : AVX512BI<opc, MRMSrcMem,
1010 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1012 "$dst {${mask}}, $src1, $src2}"),
1013 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1014 (OpNode (_.VT _.RC:$src1),
1015 (_.VT (bitconvert
1016 (_.LdFrag addr:$src2))))))],
1017 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1018}
1019
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1020multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1021 X86VectorVTInfo _> :
1022 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1023 let mayLoad = 1 in {
1024 def rmb : AVX512BI<opc, MRMSrcMem,
1025 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1026 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1027 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1028 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1029 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1030 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1031 def rmbk : AVX512BI<opc, MRMSrcMem,
1032 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1033 _.ScalarMemOp:$src2),
1034 !strconcat(OpcodeStr,
1035 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1036 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1037 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1038 (OpNode (_.VT _.RC:$src1),
1039 (X86VBroadcast
1040 (_.ScalarLdFrag addr:$src2)))))],
1041 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1042 }
1043}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1044
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1045multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1046 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1047 let Predicates = [prd] in
1048 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1049 EVEX_V512;
1050
1051 let Predicates = [prd, HasVLX] in {
1052 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1053 EVEX_V256;
1054 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1055 EVEX_V128;
1056 }
1057}
1058
1059multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1060 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1061 Predicate prd> {
1062 let Predicates = [prd] in
1063 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1064 EVEX_V512;
1065
1066 let Predicates = [prd, HasVLX] in {
1067 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1068 EVEX_V256;
1069 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1070 EVEX_V128;
1071 }
1072}
1073
1074defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1075 avx512vl_i8_info, HasBWI>,
1076 EVEX_CD8<8, CD8VF>;
1077
1078defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1079 avx512vl_i16_info, HasBWI>,
1080 EVEX_CD8<16, CD8VF>;
1081
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1082defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1083 avx512vl_i32_info, HasAVX512>,
1084 EVEX_CD8<32, CD8VF>;
1085
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1086defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1087 avx512vl_i64_info, HasAVX512>,
1088 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1089
1090defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1091 avx512vl_i8_info, HasBWI>,
1092 EVEX_CD8<8, CD8VF>;
1093
1094defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1095 avx512vl_i16_info, HasBWI>,
1096 EVEX_CD8<16, CD8VF>;
1097
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1098defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1099 avx512vl_i32_info, HasAVX512>,
1100 EVEX_CD8<32, CD8VF>;
1101
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1102defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1103 avx512vl_i64_info, HasAVX512>,
1104 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1105
1106def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1107 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1108 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1109 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1110
1111def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1112 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1113 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1114 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1115
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1116multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1117 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1118 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1119 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1120 !strconcat("vpcmp${cc}", Suffix,
1121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1122 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1123 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1124 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1125 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1126 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1127 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1128 !strconcat("vpcmp${cc}", Suffix,
1129 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1130 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1131 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1132 imm:$cc))],
1133 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1134 def rrik : AVX512AIi8<opc, MRMSrcReg,
1135 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1136 AVXCC:$cc),
1137 !strconcat("vpcmp${cc}", Suffix,
1138 "\t{$src2, $src1, $dst {${mask}}|",
1139 "$dst {${mask}}, $src1, $src2}"),
1140 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1141 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1142 imm:$cc)))],
1143 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1144 let mayLoad = 1 in
1145 def rmik : AVX512AIi8<opc, MRMSrcMem,
1146 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1147 AVXCC:$cc),
1148 !strconcat("vpcmp${cc}", Suffix,
1149 "\t{$src2, $src1, $dst {${mask}}|",
1150 "$dst {${mask}}, $src1, $src2}"),
1151 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1152 (OpNode (_.VT _.RC:$src1),
1153 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1154 imm:$cc)))],
1155 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1156
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1157 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1158 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1159 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1160 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1161 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1162 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1163 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1164 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1165 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1166 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1167 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1168 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1169 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1170 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1171 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1172 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1173 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1174 "$dst {${mask}}, $src1, $src2, $cc}"),
1175 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1176 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1177 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1178 i8imm:$cc),
1179 !strconcat("vpcmp", Suffix,
1180 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1181 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1182 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1183 }
1184}
1185
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1186multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1187 X86VectorVTInfo _> :
1188 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1189 let mayLoad = 1 in {
1190 def rmib : AVX512AIi8<opc, MRMSrcMem,
1191 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1192 AVXCC:$cc),
1193 !strconcat("vpcmp${cc}", Suffix,
1194 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1195 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1196 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1197 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1198 imm:$cc))],
1199 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1200 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1201 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1202 _.ScalarMemOp:$src2, AVXCC:$cc),
1203 !strconcat("vpcmp${cc}", Suffix,
1204 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1205 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1206 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1207 (OpNode (_.VT _.RC:$src1),
1208 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1209 imm:$cc)))],
1210 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1211 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1212
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1213 // Accept explicit immediate argument form instead of comparison code.
1214 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1215 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1216 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1217 i8imm:$cc),
1218 !strconcat("vpcmp", Suffix,
1219 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1220 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1221 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1222 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1223 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1224 _.ScalarMemOp:$src2, i8imm:$cc),
1225 !strconcat("vpcmp", Suffix,
1226 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1227 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1228 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1229 }
1230}
1231
1232multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1233 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1234 let Predicates = [prd] in
1235 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1236
1237 let Predicates = [prd, HasVLX] in {
1238 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1239 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1240 }
1241}
1242
1243multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1244 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1245 let Predicates = [prd] in
1246 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1247 EVEX_V512;
1248
1249 let Predicates = [prd, HasVLX] in {
1250 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1251 EVEX_V256;
1252 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1253 EVEX_V128;
1254 }
1255}
1256
1257defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1258 HasBWI>, EVEX_CD8<8, CD8VF>;
1259defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1260 HasBWI>, EVEX_CD8<8, CD8VF>;
1261
1262defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1263 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1264defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1265 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1266
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1267defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1268 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1269defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1270 HasAVX512>, EVEX_CD8<32, CD8VF>;
1271
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1272defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1273 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1274defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1275 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1276
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1277// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1278multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1279 X86MemOperand x86memop, ValueType vt,
1280 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1281 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1282 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1283 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1284 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1285 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1286 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1287 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1288 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1289 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1290 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1291 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1292 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1293 !strconcat("vcmp${cc}", suffix,
1294 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1295 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1296 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1297
1298 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1299 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1300 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1301 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1302 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1303 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1304 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1305 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1306 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1307 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1308 }
1309}
1310
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1311defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1312 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1313 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1314defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1315 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1316 EVEX_CD8<64, CD8VF>;
1317
1318def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1319 (COPY_TO_REGCLASS (VCMPPSZrri
1320 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1321 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1322 imm:$cc), VK8)>;
1323def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1324 (COPY_TO_REGCLASS (VPCMPDZrri
1325 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1326 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1327 imm:$cc), VK8)>;
1328def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1329 (COPY_TO_REGCLASS (VPCMPUDZrri
1330 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1331 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1332 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1333
1334def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1335 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1336 FROUND_NO_EXC)),
1337 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1338 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1339
1340def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1341 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1342 FROUND_NO_EXC)),
1343 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1344 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1345
1346def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1347 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1348 FROUND_CURRENT)),
1349 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1350 (I8Imm imm:$cc)), GR16)>;
1351
1352def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1353 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1354 FROUND_CURRENT)),
1355 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1356 (I8Imm imm:$cc)), GR8)>;
1357
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1358// Mask register copy, including
1359// - copy between mask registers
1360// - load/store mask registers
1361// - copy from GPR to mask register and vice versa
1362//
1363multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1364 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1365 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1366 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1367 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1368 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1369 let mayLoad = 1 in
1370 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1371 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1372 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1373 let mayStore = 1 in
1374 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1375 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1376 }
1377}
1378
1379multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1380 string OpcodeStr,
1381 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1382 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1383 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1384 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1385 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1386 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1387 }
1388}
1389
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1390let Predicates = [HasDQI] in
1391 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1392 i8mem>,
1393 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1394 VEX, PD;
1395
1396let Predicates = [HasAVX512] in
1397 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1398 i16mem>,
1399 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1400 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1401
1402let Predicates = [HasBWI] in {
1403 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1404 i32mem>, VEX, PD, VEX_W;
1405 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1406 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1407}
1408
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1409let Predicates = [HasBWI] in {
1410 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1411 i64mem>, VEX, PS, VEX_W;
1412 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1413 VEX, XD, VEX_W;
1414}
1415
1416// GR from/to mask register
1417let Predicates = [HasDQI] in {
1418 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1419 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1420 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1421 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1422}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1423let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1424 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1425 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1426 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1427 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1428}
1429let Predicates = [HasBWI] in {
1430 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1431 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1432}
1433let Predicates = [HasBWI] in {
1434 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1435 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1436}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1437
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1438// Load/store kreg
1439let Predicates = [HasDQI] in {
1440 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1441 (KMOVBmk addr:$dst, VK8:$src)>;
1442}
1443let Predicates = [HasAVX512] in {
1444 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1445 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1446 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1447 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1448 def : Pat<(i1 (load addr:$src)),
1449 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1450 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1451 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1452}
1453let Predicates = [HasBWI] in {
1454 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1455 (KMOVDmk addr:$dst, VK32:$src)>;
1456}
1457let Predicates = [HasBWI] in {
1458 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1459 (KMOVQmk addr:$dst, VK64:$src)>;
1460}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1461
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1462let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1463 def : Pat<(i1 (trunc (i64 GR64:$src))),
1464 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1465 (i32 1))), VK1)>;
1466
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1467 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1468 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1469
1470 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1471 (COPY_TO_REGCLASS
1472 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1473 VK1)>;
1474 def : Pat<(i1 (trunc (i16 GR16:$src))),
1475 (COPY_TO_REGCLASS
1476 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1477 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1478
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1479 def : Pat<(i32 (zext VK1:$src)),
1480 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1481 def : Pat<(i8 (zext VK1:$src)),
1482 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1483 (AND32ri (KMOVWrk
1484 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1485 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1486 (AND64ri8 (SUBREG_TO_REG (i64 0),
1487 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1488 def : Pat<(i16 (zext VK1:$src)),
1489 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1490 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1491 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1492 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1493 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1494 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1495 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1496}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1497let Predicates = [HasBWI] in {
1498 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1499 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1500 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1501 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1502}
1503
1504
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1505// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1506let Predicates = [HasAVX512] in {
1507 // GR from/to 8-bit mask without native support
1508 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1509 (COPY_TO_REGCLASS
1510 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1511 VK8)>;
1512 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1513 (EXTRACT_SUBREG
1514 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1515 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1516
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1517 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1518 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1519 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1520 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1521}
1522let Predicates = [HasBWI] in {
1523 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1524 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1525 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1526 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1527}
1528
1529// Mask unary operation
1530// - KNOT
1531multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1532 RegisterClass KRC, SDPatternOperator OpNode,
1533 Predicate prd> {
1534 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1535 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1536 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1537 [(set KRC:$dst, (OpNode KRC:$src))]>;
1538}
1539
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1540multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1541 SDPatternOperator OpNode> {
1542 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1543 HasDQI>, VEX, PD;
1544 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1545 HasAVX512>, VEX, PS;
1546 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1547 HasBWI>, VEX, PD, VEX_W;
1548 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1549 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1550}
1551
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1552defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1553
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1554multiclass avx512_mask_unop_int<string IntName, string InstName> {
1555 let Predicates = [HasAVX512] in
1556 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1557 (i16 GR16:$src)),
1558 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1559 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1560}
1561defm : avx512_mask_unop_int<"knot", "KNOT">;
1562
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1563let Predicates = [HasDQI] in
1564def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1565let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1566def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1567let Predicates = [HasBWI] in
1568def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1569let Predicates = [HasBWI] in
1570def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1571
1572// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1573let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1574def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1575 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1576
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1577def : Pat<(not VK8:$src),
1578 (COPY_TO_REGCLASS
1579 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1580}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1581
1582// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1583// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1584multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1585 RegisterClass KRC, SDPatternOperator OpNode,
1586 Predicate prd> {
1587 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1588 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1589 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1590 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1591 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1592}
1593
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1594multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1595 SDPatternOperator OpNode> {
1596 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1597 HasDQI>, VEX_4V, VEX_L, PD;
1598 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1599 HasAVX512>, VEX_4V, VEX_L, PS;
1600 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1601 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1602 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1603 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1604}
1605
1606def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1607def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1608
1609let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1610 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1611 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1612 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1613 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1614}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1615let isCommutable = 0 in
1616 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1617
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1618def : Pat<(xor VK1:$src1, VK1:$src2),
1619 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1620 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1621
1622def : Pat<(or VK1:$src1, VK1:$src2),
1623 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1624 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1625
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1626def : Pat<(and VK1:$src1, VK1:$src2),
1627 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1628 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1629
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1630multiclass avx512_mask_binop_int<string IntName, string InstName> {
1631 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1632 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1633 (i16 GR16:$src1), (i16 GR16:$src2)),
1634 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1635 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1636 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1637}
1638
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1639defm : avx512_mask_binop_int<"kand", "KAND">;
1640defm : avx512_mask_binop_int<"kandn", "KANDN">;
1641defm : avx512_mask_binop_int<"kor", "KOR">;
1642defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1643defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1644
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1645// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1646multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1647 let Predicates = [HasAVX512] in
1648 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1649 (COPY_TO_REGCLASS
1650 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1651 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1652}
1653
1654defm : avx512_binop_pat<and, KANDWrr>;
1655defm : avx512_binop_pat<andn, KANDNWrr>;
1656defm : avx512_binop_pat<or, KORWrr>;
1657defm : avx512_binop_pat<xnor, KXNORWrr>;
1658defm : avx512_binop_pat<xor, KXORWrr>;
1659
1660// Mask unpacking
1661multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1662 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1663 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1664 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1665 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1666 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1667}
1668
1669multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1670 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1671 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1672}
1673
1674defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1675def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1676 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1677 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1678
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1679
1680multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1681 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1682 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1683 (i16 GR16:$src1), (i16 GR16:$src2)),
1684 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1685 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1686 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1687}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1688defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1689
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1690// Mask bit testing
1691multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1692 SDNode OpNode> {
1693 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1694 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1695 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1696 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1697}
1698
1699multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1700 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1701 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1702}
1703
1704defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1705
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1706def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1707 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1708 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1709
1710// Mask shift
1711multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1712 SDNode OpNode> {
1713 let Predicates = [HasAVX512] in
1714 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1715 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1716 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1717 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1718}
1719
1720multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1721 SDNode OpNode> {
1722 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1723 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1724}
1725
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1726defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1727defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1728
1729// Mask setting all 0s or 1s
1730multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1731 let Predicates = [HasAVX512] in
1732 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1733 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1734 [(set KRC:$dst, (VT Val))]>;
1735}
1736
1737multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1738 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1739 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1740}
1741
1742defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1743defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1744
1745// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1746let Predicates = [HasAVX512] in {
1747 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1748 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1749 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1750 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1751 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1752}
1753def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1754 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1755
1756def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1757 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1758
1759def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1760 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1761
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1762let Predicates = [HasVLX] in {
1763 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1764 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1765 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1766 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1767 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1768 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1769 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1770 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1771}
1772
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1773def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1774 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1775
1776def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1777 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1778//===----------------------------------------------------------------------===//
1779// AVX-512 - Aligned and unaligned load and store
1780//
1781
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1782multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1783 RegisterClass KRC, RegisterClass RC,
1784 ValueType vt, ValueType zvt, X86MemOperand memop,
1785 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1786let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1787 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1789 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1790 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1791 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1792 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1793 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1794 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1795 SchedRW = [WriteLoad] in
1796 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1798 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1799 d>, EVEX;
1800
1801 let AddedComplexity = 20 in {
1802 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1803 let hasSideEffects = 0 in
1804 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1805 (ins RC:$src0, KRC:$mask, RC:$src1),
1806 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1807 "${dst} {${mask}}, $src1}"),
1808 [(set RC:$dst, (vt (vselect KRC:$mask,
1809 (vt RC:$src1),
1810 (vt RC:$src0))))],
1811 d>, EVEX, EVEX_K;
1812 let mayLoad = 1, SchedRW = [WriteLoad] in
1813 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1814 (ins RC:$src0, KRC:$mask, memop:$src1),
1815 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1816 "${dst} {${mask}}, $src1}"),
1817 [(set RC:$dst, (vt
1818 (vselect KRC:$mask,
1819 (vt (bitconvert (ld_frag addr:$src1))),
1820 (vt RC:$src0))))],
1821 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1822 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1823 let mayLoad = 1, SchedRW = [WriteLoad] in
1824 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1825 (ins KRC:$mask, memop:$src),
1826 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1827 "${dst} {${mask}} {z}, $src}"),
1828 [(set RC:$dst, (vt
1829 (vselect KRC:$mask,
1830 (vt (bitconvert (ld_frag addr:$src))),
1831 (vt (bitconvert (zvt immAllZerosV))))))],
1832 d>, EVEX, EVEX_KZ;
1833 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1834}
1835
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1836multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1837 string elty, string elsz, string vsz512,
1838 string vsz256, string vsz128, Domain d,
1839 Predicate prd, bit IsReMaterializable = 1> {
1840 let Predicates = [prd] in
1841 defm Z : avx512_load<opc, OpcodeStr,
1842 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1843 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1844 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1845 !cast<X86MemOperand>(elty##"512mem"), d,
1846 IsReMaterializable>, EVEX_V512;
1847
1848 let Predicates = [prd, HasVLX] in {
1849 defm Z256 : avx512_load<opc, OpcodeStr,
1850 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1851 "v"##vsz256##elty##elsz, "v4i64")),
1852 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1853 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1854 !cast<X86MemOperand>(elty##"256mem"), d,
1855 IsReMaterializable>, EVEX_V256;
1856
1857 defm Z128 : avx512_load<opc, OpcodeStr,
1858 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1859 "v"##vsz128##elty##elsz, "v2i64")),
1860 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1861 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1862 !cast<X86MemOperand>(elty##"128mem"), d,
1863 IsReMaterializable>, EVEX_V128;
1864 }
1865}
1866
1867
1868multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1869 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1870 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1871 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1872 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1873 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1874 EVEX;
1875 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1876 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1877 (ins RC:$src1, KRC:$mask, RC:$src2),
1878 !strconcat(OpcodeStr,
1879 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1880 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1881 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1882 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1883 !strconcat(OpcodeStr,
1884 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1885 [], d>, EVEX, EVEX_KZ;
1886 }
1887 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1888 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1889 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1890 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1891 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1892 (ins memop:$dst, KRC:$mask, RC:$src),
1893 !strconcat(OpcodeStr,
1894 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1895 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1896 }
1897}
1898
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1899
1900multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1901 string st_suff_512, string st_suff_256,
1902 string st_suff_128, string elty, string elsz,
1903 string vsz512, string vsz256, string vsz128,
1904 Domain d, Predicate prd> {
1905 let Predicates = [prd] in
1906 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1907 !cast<ValueType>("v"##vsz512##elty##elsz),
1908 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1909 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1910
1911 let Predicates = [prd, HasVLX] in {
1912 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1913 !cast<ValueType>("v"##vsz256##elty##elsz),
1914 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1915 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1916
1917 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1918 !cast<ValueType>("v"##vsz128##elty##elsz),
1919 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1920 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1921 }
1922}
1923
1924defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1925 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1926 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1927 "512", "256", "", "f", "32", "16", "8", "4",
1928 SSEPackedSingle, HasAVX512>,
1929 PS, EVEX_CD8<32, CD8VF>;
1930
1931defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1932 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1933 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1934 "512", "256", "", "f", "64", "8", "4", "2",
1935 SSEPackedDouble, HasAVX512>,
1936 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1937
1938defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1939 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1940 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1941 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1942 PS, EVEX_CD8<32, CD8VF>;
1943
1944defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1945 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1946 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1947 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1948 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1949
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1950def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1951 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1952 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1953
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1954def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1955 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1956 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1957
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1958def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1959 GR16:$mask),
1960 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1961 VR512:$src)>;
1962def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1963 GR8:$mask),
1964 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1965 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1966
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1967defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1968 "16", "8", "4", SSEPackedInt, HasAVX512>,
1969 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1970 "512", "256", "", "i", "32", "16", "8", "4",
1971 SSEPackedInt, HasAVX512>,
1972 PD, EVEX_CD8<32, CD8VF>;
1973
1974defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1975 "8", "4", "2", SSEPackedInt, HasAVX512>,
1976 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1977 "512", "256", "", "i", "64", "8", "4", "2",
1978 SSEPackedInt, HasAVX512>,
1979 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1980
1981defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1982 "64", "32", "16", SSEPackedInt, HasBWI>,
1983 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1984 "i", "8", "64", "32", "16", SSEPackedInt,
1985 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1986
1987defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1988 "32", "16", "8", SSEPackedInt, HasBWI>,
1989 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1990 "i", "16", "32", "16", "8", SSEPackedInt,
1991 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1992
1993defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1994 "16", "8", "4", SSEPackedInt, HasAVX512>,
1995 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1996 "i", "32", "16", "8", "4", SSEPackedInt,
1997 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1998
1999defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2000 "8", "4", "2", SSEPackedInt, HasAVX512>,
2001 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2002 "i", "64", "8", "4", "2", SSEPackedInt,
2003 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2004
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2005def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2006 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2007 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2008
2009def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2010 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2011 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2012
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2013def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2014 GR16:$mask),
2015 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2016 VR512:$src)>;
2017def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2018 GR8:$mask),
2019 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2020 VR512:$src)>;
2021
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2022let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2023def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2024 (bc_v8i64 (v16i32 immAllZerosV)))),
2025 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2026
2027def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2028 (v8i64 VR512:$src))),
2029 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2030 VK8), VR512:$src)>;
2031
2032def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2033 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2034 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2035
2036def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2037 (v16i32 VR512:$src))),
2038 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2039}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2040
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2041// Move Int Doubleword to Packed Double Int
2042//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2043def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2044 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2045 [(set VR128X:$dst,
2046 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2047 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2048def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2049 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2050 [(set VR128X:$dst,
2051 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2052 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2053def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2054 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2055 [(set VR128X:$dst,
2056 (v2i64 (scalar_to_vector GR64:$src)))],
2057 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2058let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2059def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2060 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2061 [(set FR64:$dst, (bitconvert GR64:$src))],
2062 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2063def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2064 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2065 [(set GR64:$dst, (bitconvert FR64:$src))],
2066 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2067}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2068def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2069 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2070 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2071 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2072 EVEX_CD8<64, CD8VT1>;
2073
2074// Move Int Doubleword to Single Scalar
2075//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2076let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2077def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2078 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2079 [(set FR32X:$dst, (bitconvert GR32:$src))],
2080 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2081
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2082def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2083 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2084 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2085 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2086}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2087
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2088// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2089//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2090def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2091 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2092 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2093 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2094 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2095def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2096 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2097 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2098 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2099 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2100 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2101
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2102// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2103//
2104def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2105 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2106 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2107 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2108 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2109 Requires<[HasAVX512, In64BitMode]>;
2110
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2111def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2112 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2113 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2114 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2115 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2116 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2117 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2118
2119// Move Scalar Single to Double Int
2120//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2121let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2122def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2123 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2124 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2125 [(set GR32:$dst, (bitconvert FR32X:$src))],
2126 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2127def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2128 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2129 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2130 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2131 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2132}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2133
2134// Move Quadword Int to Packed Quadword Int
2135//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2136def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2137 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2138 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2139 [(set VR128X:$dst,
2140 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2141 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2142
2143//===----------------------------------------------------------------------===//
2144// AVX-512 MOVSS, MOVSD
2145//===----------------------------------------------------------------------===//
2146
2147multiclass avx512_move_scalar <string asm, RegisterClass RC,
2148 SDNode OpNode, ValueType vt,
2149 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2150 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2151 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2152 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2153 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2154 (scalar_to_vector RC:$src2))))],
2155 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2156 let Constraints = "$src1 = $dst" in
2157 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2158 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2159 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2160 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2161 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2162 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2163 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2164 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2165 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2166 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2167 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2168 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2169 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2170 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2171 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2172 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2173 [], IIC_SSE_MOV_S_MR>,
2174 EVEX, VEX_LIG, EVEX_K;
2175 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2176 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2177}
2178
2179let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2180defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2181 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2182
2183let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2184defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2185 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2186
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2187def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2188 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2189 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2190
2191def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2192 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2193 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2194
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2195def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2196 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2197 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2198
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2199// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2200let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2201 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2202 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2203 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2204 IIC_SSE_MOV_S_RR>,
2205 XS, EVEX_4V, VEX_LIG;
2206 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2207 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2208 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2209 IIC_SSE_MOV_S_RR>,
2210 XD, EVEX_4V, VEX_LIG, VEX_W;
2211}
2212
2213let Predicates = [HasAVX512] in {
2214 let AddedComplexity = 15 in {
2215 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2216 // MOVS{S,D} to the lower bits.
2217 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2218 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2219 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2220 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2221 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2222 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2223 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2224 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2225
2226 // Move low f32 and clear high bits.
2227 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2228 (SUBREG_TO_REG (i32 0),
2229 (VMOVSSZrr (v4f32 (V_SET0)),
2230 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2231 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2232 (SUBREG_TO_REG (i32 0),
2233 (VMOVSSZrr (v4i32 (V_SET0)),
2234 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2235 }
2236
2237 let AddedComplexity = 20 in {
2238 // MOVSSrm zeros the high parts of the register; represent this
2239 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2240 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2241 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2242 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2243 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2244 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2245 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2246
2247 // MOVSDrm zeros the high parts of the register; represent this
2248 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2249 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2250 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2251 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2252 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2253 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2254 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2255 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2256 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2257 def : Pat<(v2f64 (X86vzload addr:$src)),
2258 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2259
2260 // Represent the same patterns above but in the form they appear for
2261 // 256-bit types
2262 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2263 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2264 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2265 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2266 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2267 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2268 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2269 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2270 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2271 }
2272 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2273 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2274 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2275 FR32X:$src)), sub_xmm)>;
2276 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2277 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2278 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2279 FR64X:$src)), sub_xmm)>;
2280 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2281 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2282 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2283
2284 // Move low f64 and clear high bits.
2285 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2286 (SUBREG_TO_REG (i32 0),
2287 (VMOVSDZrr (v2f64 (V_SET0)),
2288 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2289
2290 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2291 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2292 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2293
2294 // Extract and store.
2295 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2296 addr:$dst),
2297 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2298 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2299 addr:$dst),
2300 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2301
2302 // Shuffle with VMOVSS
2303 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2304 (VMOVSSZrr (v4i32 VR128X:$src1),
2305 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2306 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2307 (VMOVSSZrr (v4f32 VR128X:$src1),
2308 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2309
2310 // 256-bit variants
2311 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2312 (SUBREG_TO_REG (i32 0),
2313 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2314 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2315 sub_xmm)>;
2316 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2317 (SUBREG_TO_REG (i32 0),
2318 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2319 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2320 sub_xmm)>;
2321
2322 // Shuffle with VMOVSD
2323 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2324 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2325 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2326 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2327 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2328 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2329 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2330 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2331
2332 // 256-bit variants
2333 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2334 (SUBREG_TO_REG (i32 0),
2335 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2336 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2337 sub_xmm)>;
2338 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2339 (SUBREG_TO_REG (i32 0),
2340 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2341 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2342 sub_xmm)>;
2343
2344 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2345 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2346 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2347 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2348 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2349 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2350 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2351 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2352}
2353
2354let AddedComplexity = 15 in
2355def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2356 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2357 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2358 [(set VR128X:$dst, (v2i64 (X86vzmovl
2359 (v2i64 VR128X:$src))))],
2360 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2361
2362let AddedComplexity = 20 in
2363def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2364 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2365 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2366 [(set VR128X:$dst, (v2i64 (X86vzmovl
2367 (loadv2i64 addr:$src))))],
2368 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2369 EVEX_CD8<8, CD8VT8>;
2370
2371let Predicates = [HasAVX512] in {
2372 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2373 let AddedComplexity = 20 in {
2374 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2375 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2376 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2377 (VMOV64toPQIZrr GR64:$src)>;
2378 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2379 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2380
2381 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2382 (VMOVDI2PDIZrm addr:$src)>;
2383 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2384 (VMOVDI2PDIZrm addr:$src)>;
2385 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2386 (VMOVZPQILo2PQIZrm addr:$src)>;
2387 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2388 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2389 def : Pat<(v2i64 (X86vzload addr:$src)),
2390 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2391 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2392
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2393 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2394 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2395 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2396 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2397 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2398 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2399 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2400}
2401
2402def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2403 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2404
2405def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2406 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2407
2408def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2409 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2410
2411def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2412 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2413
2414//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2415// AVX-512 - Non-temporals
2416//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2417let SchedRW = [WriteLoad] in {
2418 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2419 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2420 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2421 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2422 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2423
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2424 let Predicates = [HasAVX512, HasVLX] in {
2425 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2426 (ins i256mem:$src),
2427 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2428 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2429 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2430
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2431 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2432 (ins i128mem:$src),
2433 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2434 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2435 EVEX_CD8<64, CD8VF>;
2436 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2437}
2438
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2439multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2440 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2441 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2442 let SchedRW = [WriteStore], mayStore = 1,
2443 AddedComplexity = 400 in
2444 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2446 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2447}
2448
2449multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2450 string elty, string elsz, string vsz512,
2451 string vsz256, string vsz128, Domain d,
2452 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2453 let Predicates = [prd] in
2454 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2455 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2456 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2457 EVEX_V512;
2458
2459 let Predicates = [prd, HasVLX] in {
2460 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2461 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2462 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2463 EVEX_V256;
2464
2465 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2466 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2467 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2468 EVEX_V128;
2469 }
2470}
2471
2472defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2473 "i", "64", "8", "4", "2", SSEPackedInt,
2474 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2475
2476defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2477 "f", "64", "8", "4", "2", SSEPackedDouble,
2478 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2479
2480defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2481 "f", "32", "16", "8", "4", SSEPackedSingle,
2482 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2483
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2484//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2485// AVX-512 - Integer arithmetic
2486//
2487multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2488 X86VectorVTInfo _, OpndItins itins,
2489 bit IsCommutable = 0> {
2490 defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
2491 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2492 "$src2, $src1", "$src1, $src2",
2493 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2494 itins.rr, IsCommutable>,
2495 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2496
2497 let mayLoad = 1 in {
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2498 defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2499 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2500 "$src2, $src1", "$src1, $src2",
2501 (_.VT (OpNode _.RC:$src1,
2502 (bitconvert (_.LdFrag addr:$src2)))),
2503 itins.rm>,
2504 AVX512BIBase, EVEX_4V;
2505 defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2506 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2507 "${src2}"##_.BroadcastStr##", $src1",
2508 "$src1, ${src2}"##_.BroadcastStr,
2509 (_.VT (OpNode _.RC:$src1,
2510 (X86VBroadcast
2511 (_.ScalarLdFrag addr:$src2)))),
2512 itins.rm>,
2513 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2514 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2515}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2516
2517multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2518 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2519 PatFrag memop_frag, X86MemOperand x86memop,
2520 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2521 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2522 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2523 {
2524 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2525 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2526 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2527 []>, EVEX_4V;
2528 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2529 (ins KRC:$mask, RC:$src1, RC:$src2),
2530 !strconcat(OpcodeStr,
2531 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2532 [], itins.rr>, EVEX_4V, EVEX_K;
2533 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2534 (ins KRC:$mask, RC:$src1, RC:$src2),
2535 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2536 "|$dst {${mask}} {z}, $src1, $src2}"),
2537 [], itins.rr>, EVEX_4V, EVEX_KZ;
2538 }
2539 let mayLoad = 1 in {
2540 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2541 (ins RC:$src1, x86memop:$src2),
2542 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2543 []>, EVEX_4V;
2544 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2545 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2546 !strconcat(OpcodeStr,
2547 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2548 [], itins.rm>, EVEX_4V, EVEX_K;
2549 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2550 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2551 !strconcat(OpcodeStr,
2552 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2553 [], itins.rm>, EVEX_4V, EVEX_KZ;
2554 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2555 (ins RC:$src1, x86scalar_mop:$src2),
2556 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2557 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2558 [], itins.rm>, EVEX_4V, EVEX_B;
2559 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2560 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2561 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2562 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2563 BrdcstStr, "}"),
2564 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2565 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2566 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2567 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2568 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2569 BrdcstStr, "}"),
2570 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2571 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2572}
2573
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2574defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2575 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2576
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2577defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2578 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2579
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2580defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2581 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2582
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2583defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2584 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2585
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2586defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2587 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2588
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2589defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2590 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2591 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2592 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2593
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2594defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2595 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2596 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2597
2598def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2599 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2600
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2601def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2602 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2603 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2604def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2605 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2606 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2607
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2608defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2609 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2610 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2611defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2612 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2613 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2614
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2615defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2616 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2617 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2618defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2619 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2620 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2621
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2622defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2623 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2624 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2625defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2626 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2627 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2628
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2629defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2630 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2631 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2632defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2633 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2634 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2635
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2636def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2637 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2638 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2639def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2640 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2641 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2642def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2643 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2644 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2645def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2646 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2647 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2648def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2649 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2650 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2651def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2652 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2653 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2654def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2655 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2656 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2657def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2658 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2659 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2660//===----------------------------------------------------------------------===//
2661// AVX-512 - Unpack Instructions
2662//===----------------------------------------------------------------------===//
2663
2664multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2665 PatFrag mem_frag, RegisterClass RC,
2666 X86MemOperand x86memop, string asm,
2667 Domain d> {
2668 def rr : AVX512PI<opc, MRMSrcReg,
2669 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2670 asm, [(set RC:$dst,
2671 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2672 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2673 def rm : AVX512PI<opc, MRMSrcMem,
2674 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2675 asm, [(set RC:$dst,
2676 (vt (OpNode RC:$src1,
2677 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2678 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2679}
2680
2681defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2682 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2683 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2684defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2685 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2686 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2687defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2688 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2689 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2690defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2691 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2692 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2693
2694multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2695 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2696 X86MemOperand x86memop> {
2697 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2698 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2699 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2700 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2701 IIC_SSE_UNPCK>, EVEX_4V;
2702 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2703 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2704 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2705 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2706 (bitconvert (memop_frag addr:$src2)))))],
2707 IIC_SSE_UNPCK>, EVEX_4V;
2708}
2709defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2710 VR512, memopv16i32, i512mem>, EVEX_V512,
2711 EVEX_CD8<32, CD8VF>;
2712defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2713 VR512, memopv8i64, i512mem>, EVEX_V512,
2714 VEX_W, EVEX_CD8<64, CD8VF>;
2715defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2716 VR512, memopv16i32, i512mem>, EVEX_V512,
2717 EVEX_CD8<32, CD8VF>;
2718defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2719 VR512, memopv8i64, i512mem>, EVEX_V512,
2720 VEX_W, EVEX_CD8<64, CD8VF>;
2721//===----------------------------------------------------------------------===//
2722// AVX-512 - PSHUFD
2723//
2724
2725multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2726 SDNode OpNode, PatFrag mem_frag,
2727 X86MemOperand x86memop, ValueType OpVT> {
2728 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2729 (ins RC:$src1, i8imm:$src2),
2730 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2731 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2732 [(set RC:$dst,
2733 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2734 EVEX;
2735 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2736 (ins x86memop:$src1, i8imm:$src2),
2737 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2738 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2739 [(set RC:$dst,
2740 (OpVT (OpNode (mem_frag addr:$src1),
2741 (i8 imm:$src2))))]>, EVEX;
2742}
2743
2744defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2745 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2746
2747let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2748defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2749 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2750 EVEX_CD8<32, CD8VF>;
2751let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2752defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2753 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2754 VEX_W, EVEX_CD8<32, CD8VF>;
2755
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2756def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2757 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2758def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2759 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2760
2761//===----------------------------------------------------------------------===//
2762// AVX-512 Logical Instructions
2763//===----------------------------------------------------------------------===//
2764
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2765defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2766 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2767defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2769defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2770 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2771defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2773defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2774 EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2775defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2776 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2777defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2778 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2779defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2780 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2781
2782//===----------------------------------------------------------------------===//
2783// AVX-512 FP arithmetic
2784//===----------------------------------------------------------------------===//
2785
2786multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2787 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2788 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2789 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2790 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2791 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2792 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2793 EVEX_CD8<64, CD8VT1>;
2794}
2795
2796let isCommutable = 1 in {
2797defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2798defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2799defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2800defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2801}
2802let isCommutable = 0 in {
2803defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2804defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2805}
2806
2807multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2808 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2809 RegisterClass RC, ValueType vt,
2810 X86MemOperand x86memop, PatFrag mem_frag,
2811 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2812 string BrdcstStr,
2813 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2814 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2815 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2816 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2817 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2818 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2819
2820 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2821 !strconcat(OpcodeStr,
2822 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2823 [], itins.rr, d>, EVEX_4V, EVEX_K;
2824
2825 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2826 !strconcat(OpcodeStr,
2827 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2828 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2829 }
2830
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2831 let mayLoad = 1 in {
2832 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2833 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2834 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2835 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2836
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2837 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2838 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2839 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2840 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2841 [(set RC:$dst, (OpNode RC:$src1,
2842 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2843 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2844
2845 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2846 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2847 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2848 [], itins.rm, d>, EVEX_4V, EVEX_K;
2849
2850 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2851 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2852 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2853 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2854
2855 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2856 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2857 " \t{${src2}", BrdcstStr,
2858 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2859 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2860
2861 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2862 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2863 " \t{${src2}", BrdcstStr,
2864 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2865 BrdcstStr, "}"),
2866 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2867 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2868}
2869
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2870defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2871 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2872 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2873
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2874defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2875 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2876 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2877 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2878
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2879defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2881 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2882defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2883 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2884 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2885 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2886
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2887defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2888 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2889 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2890 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2891defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2892 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2893 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2894 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2895
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2896defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2897 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2898 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2899 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2900defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2901 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2902 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2903 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2904
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2905defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2906 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2907 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2908defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2909 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2910 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2911
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2912defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2913 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2914 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2915 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2916defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2917 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2918 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2919 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2920
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]2921def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2922 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2923 (i16 -1), FROUND_CURRENT)),
2924 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2925
2926def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2927 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2928 (i8 -1), FROUND_CURRENT)),
2929 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2930
2931def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2932 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2933 (i16 -1), FROUND_CURRENT)),
2934 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2935
2936def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2937 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2938 (i8 -1), FROUND_CURRENT)),
2939 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2940//===----------------------------------------------------------------------===//
2941// AVX-512 VPTESTM instructions
2942//===----------------------------------------------------------------------===//
2943
2944multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2945 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2946 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2947 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2948 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2949 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2950 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2951 SSEPackedInt>, EVEX_4V;
2952 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2953 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2954 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2955 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2956 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2957}
2958
2959defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2960 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2961 EVEX_CD8<32, CD8VF>;
2962defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2963 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2964 EVEX_CD8<64, CD8VF>;
2965
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2966let Predicates = [HasCDI] in {
2967defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2968 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2969 EVEX_CD8<32, CD8VF>;
2970defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2971 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2972 EVEX_CD8<64, CD8VF>;
2973}
2974
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]2975def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2976 (v16i32 VR512:$src2), (i16 -1))),
2977 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2978
2979def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2980 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]2981 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2982//===----------------------------------------------------------------------===//
2983// AVX-512 Shift instructions
2984//===----------------------------------------------------------------------===//
2985multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2986 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2987 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2988 RegisterClass KRC> {
2989 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2990 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2991 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2992 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2993 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2994 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]2995 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2996 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2997 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2998 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2999 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3000 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3001 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3002 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3003 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3004 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3005 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3006 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3007 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3008 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3009}
3010
3011multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3012 RegisterClass RC, ValueType vt, ValueType SrcVT,
3013 PatFrag bc_frag, RegisterClass KRC> {
3014 // src2 is always 128-bit
3015 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3016 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3017 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3018 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3019 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3020 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3021 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3022 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3023 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3024 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3025 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3026 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3027 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3028 [(set RC:$dst, (vt (OpNode RC:$src1,
3029 (bc_frag (memopv2i64 addr:$src2)))))],
3030 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3031 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3032 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3033 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3034 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3035 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3036}
3037
3038defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3039 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3040 EVEX_V512, EVEX_CD8<32, CD8VF>;
3041defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3042 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3043 EVEX_CD8<32, CD8VQ>;
3044
3045defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3046 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3047 EVEX_CD8<64, CD8VF>, VEX_W;
3048defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3049 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3050 EVEX_CD8<64, CD8VQ>, VEX_W;
3051
3052defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3053 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3054 EVEX_CD8<32, CD8VF>;
3055defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3056 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3057 EVEX_CD8<32, CD8VQ>;
3058
3059defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3060 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3061 EVEX_CD8<64, CD8VF>, VEX_W;
3062defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3063 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3064 EVEX_CD8<64, CD8VQ>, VEX_W;
3065
3066defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3067 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3068 EVEX_V512, EVEX_CD8<32, CD8VF>;
3069defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3070 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3071 EVEX_CD8<32, CD8VQ>;
3072
3073defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3074 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3075 EVEX_CD8<64, CD8VF>, VEX_W;
3076defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3077 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3078 EVEX_CD8<64, CD8VQ>, VEX_W;
3079
3080//===-------------------------------------------------------------------===//
3081// Variable Bit Shifts
3082//===-------------------------------------------------------------------===//
3083multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3084 RegisterClass RC, ValueType vt,
3085 X86MemOperand x86memop, PatFrag mem_frag> {
3086 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3087 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3088 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3089 [(set RC:$dst,
3090 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3091 EVEX_4V;
3092 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3093 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3094 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3095 [(set RC:$dst,
3096 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3097 EVEX_4V;
3098}
3099
3100defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3101 i512mem, memopv16i32>, EVEX_V512,
3102 EVEX_CD8<32, CD8VF>;
3103defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3104 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3105 EVEX_CD8<64, CD8VF>;
3106defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3107 i512mem, memopv16i32>, EVEX_V512,
3108 EVEX_CD8<32, CD8VF>;
3109defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3110 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3111 EVEX_CD8<64, CD8VF>;
3112defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3113 i512mem, memopv16i32>, EVEX_V512,
3114 EVEX_CD8<32, CD8VF>;
3115defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3116 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3117 EVEX_CD8<64, CD8VF>;
3118
3119//===----------------------------------------------------------------------===//
3120// AVX-512 - MOVDDUP
3121//===----------------------------------------------------------------------===//
3122
3123multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3124 X86MemOperand x86memop, PatFrag memop_frag> {
3125def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3126 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3127 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3128def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3129 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3130 [(set RC:$dst,
3131 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3132}
3133
3134defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3135 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3136def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3137 (VMOVDDUPZrm addr:$src)>;
3138
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3139//===---------------------------------------------------------------------===//
3140// Replicate Single FP - MOVSHDUP and MOVSLDUP
3141//===---------------------------------------------------------------------===//
3142multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3143 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3144 X86MemOperand x86memop> {
3145 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3146 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3147 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3148 let mayLoad = 1 in
3149 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3150 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3151 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3152}
3153
3154defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3155 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3156 EVEX_CD8<32, CD8VF>;
3157defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3158 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3159 EVEX_CD8<32, CD8VF>;
3160
3161def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3162def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3163 (VMOVSHDUPZrm addr:$src)>;
3164def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3165def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3166 (VMOVSLDUPZrm addr:$src)>;
3167
3168//===----------------------------------------------------------------------===//
3169// Move Low to High and High to Low packed FP Instructions
3170//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3171def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3172 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3173 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3174 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3175 IIC_SSE_MOV_LH>, EVEX_4V;
3176def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3177 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3178 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3179 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3180 IIC_SSE_MOV_LH>, EVEX_4V;
3181
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3182let Predicates = [HasAVX512] in {
3183 // MOVLHPS patterns
3184 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3185 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3186 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3187 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3188
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3189 // MOVHLPS patterns
3190 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3191 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3192}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3193
3194//===----------------------------------------------------------------------===//
3195// FMA - Fused Multiply Operations
3196//
3197let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3198multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3199 X86VectorVTInfo _> {
3200 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3201 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3202 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3203 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3204 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3205
3206 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3207 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3208 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3209 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3210 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3211 (_.MemOpFrag addr:$src3))))]>;
3212 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3213 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3214 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3215 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3216 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3217 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3218}
3219} // Constraints = "$src1 = $dst"
3220
3221let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3222 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3223 v16f32_info>,
3224 EVEX_V512, EVEX_CD8<32, CD8VF>;
3225 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3226 v16f32_info>,
3227 EVEX_V512, EVEX_CD8<32, CD8VF>;
3228 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3229 v16f32_info>,
3230 EVEX_V512, EVEX_CD8<32, CD8VF>;
3231 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3232 v16f32_info>,
3233 EVEX_V512, EVEX_CD8<32, CD8VF>;
3234 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3235 v16f32_info>,
3236 EVEX_V512, EVEX_CD8<32, CD8VF>;
3237 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3238 v16f32_info>,
3239 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3240}
3241let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3242 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3243 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3244 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3245 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3246 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3247 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3248 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3249 v8f64_info>,
3250 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3251 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3252 v8f64_info>,
3253 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3254 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3255 v8f64_info>,
3256 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3257 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3258 v8f64_info>,
3259 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3260}
3261
3262let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3263multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3264 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3265 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3266 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3267 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3268 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3269 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3270 _.RC:$src3)))]>;
3271 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3272 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3273 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3274 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3275 [(set _.RC:$dst,
3276 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3277 (_.ScalarLdFrag addr:$src2))),
3278 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3279}
3280} // Constraints = "$src1 = $dst"
3281
3282
3283let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3284 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3285 v16f32_info>,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3288 v16f32_info>,
3289 EVEX_V512, EVEX_CD8<32, CD8VF>;
3290 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3291 v16f32_info>,
3292 EVEX_V512, EVEX_CD8<32, CD8VF>;
3293 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3294 v16f32_info>,
3295 EVEX_V512, EVEX_CD8<32, CD8VF>;
3296 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3297 v16f32_info>,
3298 EVEX_V512, EVEX_CD8<32, CD8VF>;
3299 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3300 v16f32_info>,
3301 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3302}
3303let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3304 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3305 v8f64_info>,
3306 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3307 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3308 v8f64_info>,
3309 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3310 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3311 v8f64_info>,
3312 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3313 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3314 v8f64_info>,
3315 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3316 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3317 v8f64_info>,
3318 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3319 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3320 v8f64_info>,
3321 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3322}
3323
3324// Scalar FMA
3325let Constraints = "$src1 = $dst" in {
3326multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3327 RegisterClass RC, ValueType OpVT,
3328 X86MemOperand x86memop, Operand memop,
3329 PatFrag mem_frag> {
3330 let isCommutable = 1 in
3331 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3332 (ins RC:$src1, RC:$src2, RC:$src3),
3333 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3334 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3335 [(set RC:$dst,
3336 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3337 let mayLoad = 1 in
3338 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3339 (ins RC:$src1, RC:$src2, f128mem:$src3),
3340 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3341 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3342 [(set RC:$dst,
3343 (OpVT (OpNode RC:$src2, RC:$src1,
3344 (mem_frag addr:$src3))))]>;
3345}
3346
3347} // Constraints = "$src1 = $dst"
3348
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3349defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3350 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3351defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3352 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3353defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3354 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3355defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3356 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3357defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3358 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3359defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3360 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3361defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3362 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3363defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3364 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3365
3366//===----------------------------------------------------------------------===//
3367// AVX-512 Scalar convert from sign integer to float/double
3368//===----------------------------------------------------------------------===//
3369
3370multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3371 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3372let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3373 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3374 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3375 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3376 let mayLoad = 1 in
3377 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3378 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3379 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3380 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3381} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3382}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3383let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3384defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3385 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3386defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3387 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3388defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3389 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3390defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3391 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3392
3393def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3394 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3395def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3396 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3397def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3398 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3399def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3400 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3401
3402def : Pat<(f32 (sint_to_fp GR32:$src)),
3403 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3404def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3405 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3406def : Pat<(f64 (sint_to_fp GR32:$src)),
3407 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3408def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3409 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3410
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3411defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3412 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3413defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3414 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3415defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3416 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3417defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3418 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3419
3420def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3421 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3422def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3423 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3424def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3425 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3426def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3427 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3428
3429def : Pat<(f32 (uint_to_fp GR32:$src)),
3430 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3431def : Pat<(f32 (uint_to_fp GR64:$src)),
3432 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3433def : Pat<(f64 (uint_to_fp GR32:$src)),
3434 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3435def : Pat<(f64 (uint_to_fp GR64:$src)),
3436 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3437}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3438
3439//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3440// AVX-512 Scalar convert from float/double to integer
3441//===----------------------------------------------------------------------===//
3442multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3443 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3444 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3445let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3447 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3448 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3449 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3450 let mayLoad = 1 in
3451 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3452 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3453 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3454} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3455}
3456let Predicates = [HasAVX512] in {
3457// Convert float/double to signed/unsigned int 32/64
3458defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3459 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3460 XS, EVEX_CD8<32, CD8VT1>;
3461defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3462 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3463 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3464defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3465 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3466 XS, EVEX_CD8<32, CD8VT1>;
3467defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3468 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3469 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3470 EVEX_CD8<32, CD8VT1>;
3471defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3472 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3473 XD, EVEX_CD8<64, CD8VT1>;
3474defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3475 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3476 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3477defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3478 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3479 XD, EVEX_CD8<64, CD8VT1>;
3480defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3481 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3482 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3483 EVEX_CD8<64, CD8VT1>;
3484
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3485let isCodeGenOnly = 1 in {
3486 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3487 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3488 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3489 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3490 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3491 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3492 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3493 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3494 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3495 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3496 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3497 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3498
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3499 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3500 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3501 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3502 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3503 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3504 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3505 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3506 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3507 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3508 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3509 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3510 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3511} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3512
3513// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3514let isCodeGenOnly = 1 in {
3515 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3516 ssmem, sse_load_f32, "cvttss2si">,
3517 XS, EVEX_CD8<32, CD8VT1>;
3518 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3519 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3520 "cvttss2si">, XS, VEX_W,
3521 EVEX_CD8<32, CD8VT1>;
3522 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3523 sdmem, sse_load_f64, "cvttsd2si">, XD,
3524 EVEX_CD8<64, CD8VT1>;
3525 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3526 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3527 "cvttsd2si">, XD, VEX_W,
3528 EVEX_CD8<64, CD8VT1>;
3529 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3530 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3531 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3532 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3533 int_x86_avx512_cvttss2usi64, ssmem,
3534 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3535 EVEX_CD8<32, CD8VT1>;
3536 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3537 int_x86_avx512_cvttsd2usi,
3538 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3539 EVEX_CD8<64, CD8VT1>;
3540 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3541 int_x86_avx512_cvttsd2usi64, sdmem,
3542 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3543 EVEX_CD8<64, CD8VT1>;
3544} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3545
3546multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3547 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3548 string asm> {
3549 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3550 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3551 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3552 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3553 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3554 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3555}
3556
3557defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3558 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3559 EVEX_CD8<32, CD8VT1>;
3560defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3562 EVEX_CD8<32, CD8VT1>;
3563defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3564 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3565 EVEX_CD8<32, CD8VT1>;
3566defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3567 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3568 EVEX_CD8<32, CD8VT1>;
3569defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3570 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3571 EVEX_CD8<64, CD8VT1>;
3572defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3573 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3574 EVEX_CD8<64, CD8VT1>;
3575defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3576 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3577 EVEX_CD8<64, CD8VT1>;
3578defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3579 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3580 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3581} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3582//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3583// AVX-512 Convert form float to double and back
3584//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3585let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3586def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3587 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3588 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3589 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3590let mayLoad = 1 in
3591def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3592 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3593 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3594 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3595 EVEX_CD8<32, CD8VT1>;
3596
3597// Convert scalar double to scalar single
3598def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3599 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3600 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3601 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3602let mayLoad = 1 in
3603def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3604 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3605 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3606 []>, EVEX_4V, VEX_LIG, VEX_W,
3607 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3608}
3609
3610def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3611 Requires<[HasAVX512]>;
3612def : Pat<(fextend (loadf32 addr:$src)),
3613 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3614
3615def : Pat<(extloadf32 addr:$src),
3616 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3617 Requires<[HasAVX512, OptForSize]>;
3618
3619def : Pat<(extloadf32 addr:$src),
3620 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3621 Requires<[HasAVX512, OptForSpeed]>;
3622
3623def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3624 Requires<[HasAVX512]>;
3625
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3626multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3627 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3628 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3629 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3630let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3631 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3632 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3633 [(set DstRC:$dst,
3634 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3635 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3636 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3637 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3638 let mayLoad = 1 in
3639 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3640 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3641 [(set DstRC:$dst,
3642 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3643} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3644}
3645
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3646multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3647 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3648 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3649 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3650let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3651 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3652 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3653 [(set DstRC:$dst,
3654 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3655 let mayLoad = 1 in
3656 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3657 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3658 [(set DstRC:$dst,
3659 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3660} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3661}
3662
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3663defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3664 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3665 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3666 EVEX_CD8<64, CD8VF>;
3667
3668defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3669 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3670 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3671 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3672def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3673 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3674
3675def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3676 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3677 (VCVTPD2PSZrr VR512:$src)>;
3678
3679def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3680 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3681 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3682
3683//===----------------------------------------------------------------------===//
3684// AVX-512 Vector convert from sign integer to float/double
3685//===----------------------------------------------------------------------===//
3686
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3687defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3688 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3689 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3690 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3691
3692defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3693 memopv4i64, i256mem, v8f64, v8i32,
3694 SSEPackedDouble>, EVEX_V512, XS,
3695 EVEX_CD8<32, CD8VH>;
3696
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3697defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3698 memopv16f32, f512mem, v16i32, v16f32,
3699 SSEPackedSingle>, EVEX_V512, XS,
3700 EVEX_CD8<32, CD8VF>;
3701
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3702defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3703 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3704 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3705 EVEX_CD8<64, CD8VF>;
3706
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3707defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3708 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3709 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3710 EVEX_CD8<32, CD8VF>;
3711
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3712// cvttps2udq (src, 0, mask-all-ones, sae-current)
3713def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3714 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3715 (VCVTTPS2UDQZrr VR512:$src)>;
3716
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3717defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3718 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3719 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3720 EVEX_CD8<64, CD8VF>;
3721
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3722// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3723def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3724 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3725 (VCVTTPD2UDQZrr VR512:$src)>;
3726
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3727defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3728 memopv4i64, f256mem, v8f64, v8i32,
3729 SSEPackedDouble>, EVEX_V512, XS,
3730 EVEX_CD8<32, CD8VH>;
3731
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3732defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3733 memopv16i32, f512mem, v16f32, v16i32,
3734 SSEPackedSingle>, EVEX_V512, XD,
3735 EVEX_CD8<32, CD8VF>;
3736
3737def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3738 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3739 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3740
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3741def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3742 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3743 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3744
3745def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3746 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3747 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3748
3749def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3750 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3751 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3752
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3753def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3754 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3755 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3756
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3757def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3758 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3759 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3760def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3761 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3762 (VCVTDQ2PDZrr VR256X:$src)>;
3763def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3764 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3765 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3766def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3767 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3768 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3769
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3770multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3771 RegisterClass DstRC, PatFrag mem_frag,
3772 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3773let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3774 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3775 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3776 [], d>, EVEX;
3777 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3778 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3779 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3780 let mayLoad = 1 in
3781 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3782 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3783 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3784} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3785}
3786
3787defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3788 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3789 EVEX_V512, EVEX_CD8<32, CD8VF>;
3790defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3791 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3792 EVEX_V512, EVEX_CD8<64, CD8VF>;
3793
3794def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3795 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3796 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3797
3798def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3799 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3800 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3801
3802defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3803 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3804 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3805defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3806 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3807 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3808
3809def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3810 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3811 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3812
3813def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3814 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3815 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3816
3817let Predicates = [HasAVX512] in {
3818 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3819 (VCVTPD2PSZrm addr:$src)>;
3820 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3821 (VCVTPS2PDZrm addr:$src)>;
3822}
3823
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3824//===----------------------------------------------------------------------===//
3825// Half precision conversion instructions
3826//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3827multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3828 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3829 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3830 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3831 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3832 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3833 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3834 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3835}
3836
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3837multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3838 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3839 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3840 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3841 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3842 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3843 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3844 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3845 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3846 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3847}
3848
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3849defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3850 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3851defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3852 EVEX_CD8<32, CD8VH>;
3853
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3854def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3855 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3856 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3857
3858def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3859 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3860 (VCVTPH2PSZrr VR256X:$src)>;
3861
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3862let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3863 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3864 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3865 EVEX_CD8<32, CD8VT1>;
3866 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3867 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3868 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3869 let Pattern = []<dag> in {
3870 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3871 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3872 EVEX_CD8<32, CD8VT1>;
3873 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3874 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3875 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3876 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3877 let isCodeGenOnly = 1 in {
3878 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3879 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3880 EVEX_CD8<32, CD8VT1>;
3881 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3882 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3883 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3884
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3885 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3886 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3887 EVEX_CD8<32, CD8VT1>;
3888 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3889 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3890 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3891 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3892}
3893
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3894/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3895multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3896 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3897 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3898 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3899 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3900 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3901 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3902 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3903 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3904 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3905 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3906 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3907 }
3908}
3909}
3910
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3911defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3912 EVEX_CD8<32, CD8VT1>;
3913defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3914 VEX_W, EVEX_CD8<64, CD8VT1>;
3915defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3916 EVEX_CD8<32, CD8VT1>;
3917defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3918 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3919
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3920def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3921 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3922 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3923 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3924
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3925def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3926 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3927 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3928 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3929
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3930def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3931 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3932 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3933 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3934
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3935def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3936 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3937 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3938 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3939
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3940/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3941multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3942 RegisterClass RC, X86MemOperand x86memop,
3943 PatFrag mem_frag, ValueType OpVt> {
3944 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3945 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3946 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3947 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3948 EVEX;
3949 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3950 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3951 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3952 EVEX;
3953}
3954defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3955 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3956defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3957 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3958defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3959 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3960defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3961 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3962
3963def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3964 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3965 (VRSQRT14PSZr VR512:$src)>;
3966def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3967 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3968 (VRSQRT14PDZr VR512:$src)>;
3969
3970def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3971 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3972 (VRCP14PSZr VR512:$src)>;
3973def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3974 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3975 (VRCP14PDZr VR512:$src)>;
3976
3977/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3978multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3979 X86MemOperand x86memop> {
3980 let hasSideEffects = 0, Predicates = [HasERI] in {
3981 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3982 (ins RC:$src1, RC:$src2),
3983 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3984 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3985 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3986 (ins RC:$src1, RC:$src2),
3987 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3988 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3989 []>, EVEX_4V, EVEX_B;
3990 let mayLoad = 1 in {
3991 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3992 (ins RC:$src1, x86memop:$src2),
3993 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3994 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3995 }
3996}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3997}
3998
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3999defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4000 EVEX_CD8<32, CD8VT1>;
4001defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4002 VEX_W, EVEX_CD8<64, CD8VT1>;
4003defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4004 EVEX_CD8<32, CD8VT1>;
4005defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4006 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4007
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4008def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4009 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4010 FROUND_NO_EXC)),
4011 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4012 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4013
4014def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4015 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4016 FROUND_NO_EXC)),
4017 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4018 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4019
4020def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4021 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4022 FROUND_NO_EXC)),
4023 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4024 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4025
4026def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4027 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4028 FROUND_NO_EXC)),
4029 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4030 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4031
4032/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4033multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4034 RegisterClass RC, X86MemOperand x86memop> {
4035 let hasSideEffects = 0, Predicates = [HasERI] in {
4036 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4037 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4038 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4039 []>, EVEX;
4040 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4041 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4042 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4043 []>, EVEX, EVEX_B;
4044 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4045 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4046 []>, EVEX;
4047 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4048}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4049defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4050 EVEX_V512, EVEX_CD8<32, CD8VF>;
4051defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4052 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4053defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4054 EVEX_V512, EVEX_CD8<32, CD8VF>;
4055defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4056 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4057
4058def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4059 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4060 (VRSQRT28PSZrb VR512:$src)>;
4061def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4062 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4063 (VRSQRT28PDZrb VR512:$src)>;
4064
4065def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4066 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4067 (VRCP28PSZrb VR512:$src)>;
4068def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4069 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4070 (VRCP28PDZrb VR512:$src)>;
4071
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4072multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4073 OpndItins itins_s, OpndItins itins_d> {
4074 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4075 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4076 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4077 EVEX, EVEX_V512;
4078
4079 let mayLoad = 1 in
4080 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4081 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4082 [(set VR512:$dst,
4083 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4084 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4085
4086 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4087 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4088 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4089 EVEX, EVEX_V512;
4090
4091 let mayLoad = 1 in
4092 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4093 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4094 [(set VR512:$dst, (OpNode
4095 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4096 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4097
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4098}
4099
4100multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4101 Intrinsic F32Int, Intrinsic F64Int,
4102 OpndItins itins_s, OpndItins itins_d> {
4103 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4104 (ins FR32X:$src1, FR32X:$src2),
4105 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4106 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4107 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4108 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4109 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4110 (ins VR128X:$src1, VR128X:$src2),
4111 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4112 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4113 [(set VR128X:$dst,
4114 (F32Int VR128X:$src1, VR128X:$src2))],
4115 itins_s.rr>, XS, EVEX_4V;
4116 let mayLoad = 1 in {
4117 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4118 (ins FR32X:$src1, f32mem:$src2),
4119 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4120 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4121 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4122 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4123 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4124 (ins VR128X:$src1, ssmem:$src2),
4125 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4126 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4127 [(set VR128X:$dst,
4128 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4129 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4130 }
4131 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4132 (ins FR64X:$src1, FR64X:$src2),
4133 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4134 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4135 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4136 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4137 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4138 (ins VR128X:$src1, VR128X:$src2),
4139 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4140 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4141 [(set VR128X:$dst,
4142 (F64Int VR128X:$src1, VR128X:$src2))],
4143 itins_s.rr>, XD, EVEX_4V, VEX_W;
4144 let mayLoad = 1 in {
4145 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4146 (ins FR64X:$src1, f64mem:$src2),
4147 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4148 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4149 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4150 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4151 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4152 (ins VR128X:$src1, sdmem:$src2),
4153 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4154 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4155 [(set VR128X:$dst,
4156 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4157 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4158 }
4159}
4160
4161
4162defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4163 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4164 SSE_SQRTSS, SSE_SQRTSD>,
4165 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4166 SSE_SQRTPS, SSE_SQRTPD>;
4167
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4168let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4169 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4170 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4171 (VSQRTPSZrr VR512:$src1)>;
4172 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4173 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4174 (VSQRTPDZrr VR512:$src1)>;
4175
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4176 def : Pat<(f32 (fsqrt FR32X:$src)),
4177 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4178 def : Pat<(f32 (fsqrt (load addr:$src))),
4179 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4180 Requires<[OptForSize]>;
4181 def : Pat<(f64 (fsqrt FR64X:$src)),
4182 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4183 def : Pat<(f64 (fsqrt (load addr:$src))),
4184 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4185 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4186
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4187 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4188 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4189 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4190 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4191 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4192
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4193 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4194 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4195 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4196 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4197 Requires<[OptForSize]>;
4198
4199 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4200 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4201 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4202 VR128X)>;
4203 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4204 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4205
4206 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4207 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4208 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4209 VR128X)>;
4210 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4211 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4212}
4213
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4214
4215multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4216 X86MemOperand x86memop, RegisterClass RC,
4217 PatFrag mem_frag32, PatFrag mem_frag64,
4218 Intrinsic V4F32Int, Intrinsic V2F64Int,
4219 CD8VForm VForm> {
4220let ExeDomain = SSEPackedSingle in {
4221 // Intrinsic operation, reg.
4222 // Vector intrinsic operation, reg
4223 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4224 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4225 !strconcat(OpcodeStr,
4226 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4227 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4228
4229 // Vector intrinsic operation, mem
4230 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4231 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4232 !strconcat(OpcodeStr,
4233 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4234 [(set RC:$dst,
4235 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4236 EVEX_CD8<32, VForm>;
4237} // ExeDomain = SSEPackedSingle
4238
4239let ExeDomain = SSEPackedDouble in {
4240 // Vector intrinsic operation, reg
4241 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4242 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4243 !strconcat(OpcodeStr,
4244 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4245 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4246
4247 // Vector intrinsic operation, mem
4248 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4249 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4250 !strconcat(OpcodeStr,
4251 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4252 [(set RC:$dst,
4253 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4254 EVEX_CD8<64, VForm>;
4255} // ExeDomain = SSEPackedDouble
4256}
4257
4258multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4259 string OpcodeStr,
4260 Intrinsic F32Int,
4261 Intrinsic F64Int> {
4262let ExeDomain = GenericDomain in {
4263 // Operation, reg.
4264 let hasSideEffects = 0 in
4265 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4266 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4267 !strconcat(OpcodeStr,
4268 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4269 []>;
4270
4271 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4272 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4273 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4274 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4275 !strconcat(OpcodeStr,
4276 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4277 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4278
4279 // Intrinsic operation, mem.
4280 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4281 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4282 !strconcat(OpcodeStr,
4283 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4284 [(set VR128X:$dst, (F32Int VR128X:$src1,
4285 sse_load_f32:$src2, imm:$src3))]>,
4286 EVEX_CD8<32, CD8VT1>;
4287
4288 // Operation, reg.
4289 let hasSideEffects = 0 in
4290 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4291 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4292 !strconcat(OpcodeStr,
4293 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4294 []>, VEX_W;
4295
4296 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4297 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4298 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4299 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4300 !strconcat(OpcodeStr,
4301 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4302 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4303 VEX_W;
4304
4305 // Intrinsic operation, mem.
4306 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4307 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4308 !strconcat(OpcodeStr,
4309 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4310 [(set VR128X:$dst,
4311 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4312 VEX_W, EVEX_CD8<64, CD8VT1>;
4313} // ExeDomain = GenericDomain
4314}
4315
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4316multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4317 X86MemOperand x86memop, RegisterClass RC,
4318 PatFrag mem_frag, Domain d> {
4319let ExeDomain = d in {
4320 // Intrinsic operation, reg.
4321 // Vector intrinsic operation, reg
4322 def r : AVX512AIi8<opc, MRMSrcReg,
4323 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4324 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4325 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4326 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4327
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4328 // Vector intrinsic operation, mem
4329 def m : AVX512AIi8<opc, MRMSrcMem,
4330 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4331 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4332 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4333 []>, EVEX;
4334} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4335}
4336
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4337
4338defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4339 memopv16f32, SSEPackedSingle>, EVEX_V512,
4340 EVEX_CD8<32, CD8VF>;
4341
4342def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4343 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4344 FROUND_CURRENT)),
4345 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4346
4347
4348defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4349 memopv8f64, SSEPackedDouble>, EVEX_V512,
4350 VEX_W, EVEX_CD8<64, CD8VF>;
4351
4352def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4353 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4354 FROUND_CURRENT)),
4355 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4356
4357multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4358 Operand x86memop, RegisterClass RC, Domain d> {
4359let ExeDomain = d in {
4360 def r : AVX512AIi8<opc, MRMSrcReg,
4361 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4362 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4363 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4364 []>, EVEX_4V;
4365
4366 def m : AVX512AIi8<opc, MRMSrcMem,
4367 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4368 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4369 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4370 []>, EVEX_4V;
4371} // ExeDomain
4372}
4373
4374defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4375 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4376
4377defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4378 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4379
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4380def : Pat<(ffloor FR32X:$src),
4381 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4382def : Pat<(f64 (ffloor FR64X:$src)),
4383 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4384def : Pat<(f32 (fnearbyint FR32X:$src)),
4385 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4386def : Pat<(f64 (fnearbyint FR64X:$src)),
4387 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4388def : Pat<(f32 (fceil FR32X:$src)),
4389 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4390def : Pat<(f64 (fceil FR64X:$src)),
4391 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4392def : Pat<(f32 (frint FR32X:$src)),
4393 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4394def : Pat<(f64 (frint FR64X:$src)),
4395 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4396def : Pat<(f32 (ftrunc FR32X:$src)),
4397 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4398def : Pat<(f64 (ftrunc FR64X:$src)),
4399 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4400
4401def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4402 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4403def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4404 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4405def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4406 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4407def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4408 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4409def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4410 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4411
4412def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4413 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4414def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4415 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4416def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4417 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4418def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4419 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4420def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4421 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4422
4423//-------------------------------------------------
4424// Integer truncate and extend operations
4425//-------------------------------------------------
4426
4427multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4428 RegisterClass dstRC, RegisterClass srcRC,
4429 RegisterClass KRC, X86MemOperand x86memop> {
4430 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4431 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4432 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4433 []>, EVEX;
4434
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4435 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4436 (ins KRC:$mask, srcRC:$src),
4437 !strconcat(OpcodeStr,
4438 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4439 []>, EVEX, EVEX_K;
4440
4441 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4442 (ins KRC:$mask, srcRC:$src),
4443 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4444 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4445 []>, EVEX, EVEX_KZ;
4446
4447 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4449 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4450
4451 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4452 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4453 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4454 []>, EVEX, EVEX_K;
4455
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4456}
4457defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4458 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4459defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4460 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4461defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4462 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4463defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4464 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4465defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4466 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4467defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4468 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4469defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4470 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4471defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4472 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4473defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4474 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4475defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4476 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4477defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4478 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4479defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4480 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4481defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4482 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4483defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4484 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4485defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4486 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4487
4488def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4489def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4490def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4491def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4492def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4493
4494def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4495 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4496def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4497 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4498def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4499 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4500def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4501 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4502
4503
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4504multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4505 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4506 PatFrag mem_frag, X86MemOperand x86memop,
4507 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4508
4509 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4510 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4511 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4512 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4513
4514 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4515 (ins KRC:$mask, SrcRC:$src),
4516 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4517 []>, EVEX, EVEX_K;
4518
4519 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4520 (ins KRC:$mask, SrcRC:$src),
4521 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4522 []>, EVEX, EVEX_KZ;
4523
4524 let mayLoad = 1 in {
4525 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4526 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4527 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4528 [(set DstRC:$dst,
4529 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4530 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4531
4532 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4533 (ins KRC:$mask, x86memop:$src),
4534 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4535 []>,
4536 EVEX, EVEX_K;
4537
4538 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4539 (ins KRC:$mask, x86memop:$src),
4540 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4541 []>,
4542 EVEX, EVEX_KZ;
4543 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4544}
4545
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4546defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4547 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4548 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4549defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4550 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4551 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4552defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4553 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4554 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4555defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4556 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4557 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4558defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4559 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4560 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4561
4562defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4563 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4564 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4565defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4566 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4567 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4568defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4569 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4570 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4571defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4572 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4573 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4574defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4575 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4576 EVEX_CD8<32, CD8VH>;
4577
4578//===----------------------------------------------------------------------===//
4579// GATHER - SCATTER Operations
4580
4581multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4582 RegisterClass RC, X86MemOperand memop> {
4583let mayLoad = 1,
4584 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4585 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4586 (ins RC:$src1, KRC:$mask, memop:$src2),
4587 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4588 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4589 []>, EVEX, EVEX_K;
4590}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4591
4592let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4594 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4595defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4596 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4597}
4598
4599let ExeDomain = SSEPackedSingle in {
4600defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4601 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4602defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4603 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4604}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4605
4606defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4607 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4608defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4609 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4610
4611defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4612 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4613defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4614 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4615
4616multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4617 RegisterClass RC, X86MemOperand memop> {
4618let mayStore = 1, Constraints = "$mask = $mask_wb" in
4619 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4620 (ins memop:$dst, KRC:$mask, RC:$src2),
4621 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4622 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4623 []>, EVEX, EVEX_K;
4624}
4625
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4626let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4627defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4628 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4629defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4630 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4631}
4632
4633let ExeDomain = SSEPackedSingle in {
4634defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4635 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4636defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4637 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4638}
4639
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4640defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4641 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4642defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4643 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4644
4645defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4646 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4647defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4648 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4649
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4650// prefetch
4651multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4652 RegisterClass KRC, X86MemOperand memop> {
4653 let Predicates = [HasPFI], hasSideEffects = 1 in
4654 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4655 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4656 []>, EVEX, EVEX_K;
4657}
4658
4659defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4660 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4661
4662defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4663 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4664
4665defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4666 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4667
4668defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4669 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4670
4671defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4672 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4673
4674defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4675 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4676
4677defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4678 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4679
4680defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4681 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4682
4683defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4684 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4685
4686defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4687 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4688
4689defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4690 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4691
4692defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4693 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4694
4695defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4696 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4697
4698defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4699 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4700
4701defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4702 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4703
4704defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4705 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4706//===----------------------------------------------------------------------===//
4707// VSHUFPS - VSHUFPD Operations
4708
4709multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4710 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4711 Domain d> {
4712 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4713 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4714 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4715 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4716 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4717 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4718 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4719 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4720 (ins RC:$src1, RC:$src2, i8imm:$src3),
4721 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4722 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4723 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4724 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4725 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4726}
4727
4728defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4729 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4730defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4731 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4732
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4733def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4734 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4735def : Pat<(v16i32 (X86Shufp VR512:$src1,
4736 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4737 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4738
4739def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4740 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4741def : Pat<(v8i64 (X86Shufp VR512:$src1,
4742 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4743 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4744
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4745multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4746 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4747 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4748 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4749 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4750 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4751 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4752 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4753
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4754 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4755 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4756 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4757
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4758 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4759 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4760 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4761 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4762 " \t{$src3, $src2, $src1, $dst|"
4763 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4764 []>, EVEX_4V;
4765}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4766defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4767defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4768
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4769// Helper fragments to match sext vXi1 to vXiY.
4770def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4771def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4772
4773multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4774 RegisterClass KRC, RegisterClass RC,
4775 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4776 string BrdcstStr> {
4777 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4778 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4779 []>, EVEX;
4780 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4781 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4782 []>, EVEX, EVEX_K;
4783 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4784 !strconcat(OpcodeStr,
4785 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4786 []>, EVEX, EVEX_KZ;
4787 let mayLoad = 1 in {
4788 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4789 (ins x86memop:$src),
4790 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4791 []>, EVEX;
4792 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4793 (ins KRC:$mask, x86memop:$src),
4794 !strconcat(OpcodeStr,
4795 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4796 []>, EVEX, EVEX_K;
4797 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4798 (ins KRC:$mask, x86memop:$src),
4799 !strconcat(OpcodeStr,
4800 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4801 []>, EVEX, EVEX_KZ;
4802 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4803 (ins x86scalar_mop:$src),
4804 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4805 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4806 []>, EVEX, EVEX_B;
4807 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4808 (ins KRC:$mask, x86scalar_mop:$src),
4809 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4810 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4811 []>, EVEX, EVEX_B, EVEX_K;
4812 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4813 (ins KRC:$mask, x86scalar_mop:$src),
4814 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4815 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4816 BrdcstStr, "}"),
4817 []>, EVEX, EVEX_B, EVEX_KZ;
4818 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4819}
4820
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4821defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4822 i512mem, i32mem, "{1to16}">, EVEX_V512,
4823 EVEX_CD8<32, CD8VF>;
4824defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4825 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4826 EVEX_CD8<64, CD8VF>;
4827
4828def : Pat<(xor
4829 (bc_v16i32 (v16i1sextv16i32)),
4830 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4831 (VPABSDZrr VR512:$src)>;
4832def : Pat<(xor
4833 (bc_v8i64 (v8i1sextv8i64)),
4834 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4835 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4836
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4837def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4838 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4839 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4840def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4841 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4842 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4843
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4844multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4845 RegisterClass RC, RegisterClass KRC,
4846 X86MemOperand x86memop,
4847 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4848 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4849 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4850 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4851 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4852 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4853 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4854 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4855 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4856 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4857 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4858 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4859 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4860 []>, EVEX, EVEX_B;
4861 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4862 (ins KRC:$mask, RC:$src),
4863 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4864 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4865 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4866 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4867 (ins KRC:$mask, x86memop:$src),
4868 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4869 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4870 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4871 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4872 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4873 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4874 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4875 BrdcstStr, "}"),
4876 []>, EVEX, EVEX_KZ, EVEX_B;
4877
4878 let Constraints = "$src1 = $dst" in {
4879 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4880 (ins RC:$src1, KRC:$mask, RC:$src2),
4881 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4882 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4883 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4884 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4885 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4886 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4887 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4888 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4889 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4890 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4891 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4892 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4893 []>, EVEX, EVEX_K, EVEX_B;
4894 }
4895}
4896
4897let Predicates = [HasCDI] in {
4898defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4899 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4900 EVEX_V512, EVEX_CD8<32, CD8VF>;
4901
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4902
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4903defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4904 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4905 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4906
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4907}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4908
4909def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4910 GR16:$mask),
4911 (VPCONFLICTDrrk VR512:$src1,
4912 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4913
4914def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4915 GR8:$mask),
4916 (VPCONFLICTQrrk VR512:$src1,
4917 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4918
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4919let Predicates = [HasCDI] in {
4920defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4921 i512mem, i32mem, "{1to16}">,
4922 EVEX_V512, EVEX_CD8<32, CD8VF>;
4923
4924
4925defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4926 i512mem, i64mem, "{1to8}">,
4927 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4928
4929}
4930
4931def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4932 GR16:$mask),
4933 (VPLZCNTDrrk VR512:$src1,
4934 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4935
4936def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4937 GR8:$mask),
4938 (VPLZCNTQrrk VR512:$src1,
4939 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4940
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]4941def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4942 (VPLZCNTDrm addr:$src)>;
4943def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4944 (VPLZCNTDrr VR512:$src)>;
4945def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4946 (VPLZCNTQrm addr:$src)>;
4947def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4948 (VPLZCNTQrr VR512:$src)>;
4949
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4950def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4951def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4952def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]4953
4954def : Pat<(store VK1:$src, addr:$dst),
4955 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4956
4957def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4958 (truncstore node:$val, node:$ptr), [{
4959 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4960}]>;
4961
4962def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4963 (MOV8mr addr:$dst, GR8:$src)>;
4964
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]4965multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4966def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4967 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4968 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4969}
4970
4971multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4972 string OpcodeStr, Predicate prd> {
4973let Predicates = [prd] in
4974 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4975
4976 let Predicates = [prd, HasVLX] in {
4977 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
4978 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
4979 }
4980}
4981
4982multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
4983 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
4984 HasBWI>;
4985 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
4986 HasBWI>, VEX_W;
4987 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
4988 HasDQI>;
4989 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
4990 HasDQI>, VEX_W;
4991}
4992
4993defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;