Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2 | * |
Yuval Mintz | 247fa82 | 2013-01-14 05:11:50 +0000 | [diff] [blame] | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
Eilon Greenstein | 24e3fce | 2008-06-12 14:30:28 -0700 | [diff] [blame] | 9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
| 10 | * Written by: Eliezer Tamir |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11 | * Based on code from Michael Chan's bnx2 driver |
| 12 | * UDP CSUM errata workaround by Arik Gendelman |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
Eliezer Tamir | c14423f | 2008-02-28 11:49:42 -0800 | [diff] [blame] | 14 | * Statistics and Link management by Yitchak Gertner |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 15 | * |
| 16 | */ |
| 17 | |
Joe Perches | f1deab5 | 2011-08-14 12:16:21 +0000 | [diff] [blame] | 18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 19 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/moduleparam.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/device.h> /* for dev_info() */ |
| 24 | #include <linux/timer.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/ioport.h> |
| 27 | #include <linux/slab.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/pci.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/netdevice.h> |
| 32 | #include <linux/etherdevice.h> |
| 33 | #include <linux/skbuff.h> |
| 34 | #include <linux/dma-mapping.h> |
| 35 | #include <linux/bitops.h> |
| 36 | #include <linux/irq.h> |
| 37 | #include <linux/delay.h> |
| 38 | #include <asm/byteorder.h> |
| 39 | #include <linux/time.h> |
| 40 | #include <linux/ethtool.h> |
| 41 | #include <linux/mii.h> |
Eilon Greenstein | 0c6671b | 2009-01-14 21:26:51 -0800 | [diff] [blame] | 42 | #include <linux/if_vlan.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 43 | #include <net/ip.h> |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 44 | #include <net/ipv6.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 45 | #include <net/tcp.h> |
| 46 | #include <net/checksum.h> |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 47 | #include <net/ip6_checksum.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 48 | #include <linux/workqueue.h> |
| 49 | #include <linux/crc32.h> |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 50 | #include <linux/crc32c.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 51 | #include <linux/prefetch.h> |
| 52 | #include <linux/zlib.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 53 | #include <linux/io.h> |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 54 | #include <linux/semaphore.h> |
Ben Hutchings | 45229b4 | 2009-11-07 11:53:39 +0000 | [diff] [blame] | 55 | #include <linux/stringify.h> |
David S. Miller | 7ab24bf | 2011-06-29 05:48:41 -0700 | [diff] [blame] | 56 | #include <linux/vmalloc.h> |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 57 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 58 | #include "bnx2x.h" |
| 59 | #include "bnx2x_init.h" |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 60 | #include "bnx2x_init_ops.h" |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 61 | #include "bnx2x_cmn.h" |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 62 | #include "bnx2x_vfpf.h" |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 63 | #include "bnx2x_dcb.h" |
Vladislav Zolotarov | 042181f | 2011-06-14 01:33:39 +0000 | [diff] [blame] | 64 | #include "bnx2x_sp.h" |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 65 | |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 66 | #include <linux/firmware.h> |
| 67 | #include "bnx2x_fw_file_hdr.h" |
| 68 | /* FW files */ |
Ben Hutchings | 45229b4 | 2009-11-07 11:53:39 +0000 | [diff] [blame] | 69 | #define FW_FILE_VERSION \ |
| 70 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ |
| 71 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ |
| 72 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ |
| 73 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) |
Dmitry Kravkov | 560131f | 2010-10-06 03:18:47 +0000 | [diff] [blame] | 74 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
| 75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 77 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 78 | /* Time in jiffies before concluding the transmitter is hung */ |
| 79 | #define TX_TIMEOUT (5*HZ) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 80 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 81 | static char version[] = |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 82 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 83 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
| 84 | |
Eilon Greenstein | 24e3fce | 2008-06-12 14:30:28 -0700 | [diff] [blame] | 85 | MODULE_AUTHOR("Eliezer Tamir"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 86 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 87 | "BCM57710/57711/57711E/" |
| 88 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" |
| 89 | "57840/57840_MF Driver"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 90 | MODULE_LICENSE("GPL"); |
| 91 | MODULE_VERSION(DRV_MODULE_VERSION); |
Ben Hutchings | 45229b4 | 2009-11-07 11:53:39 +0000 | [diff] [blame] | 92 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
| 93 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 94 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 95 | |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 96 | int num_queues; |
Vladislav Zolotarov | 54b9dda | 2009-11-16 06:05:58 +0000 | [diff] [blame] | 97 | module_param(num_queues, int, 0); |
Dmitry Kravkov | 9630523 | 2012-04-03 18:41:30 +0000 | [diff] [blame] | 98 | MODULE_PARM_DESC(num_queues, |
| 99 | " Set number of queues (default is as a number of CPUs)"); |
Eilon Greenstein | 555f6c7 | 2009-02-12 08:36:11 +0000 | [diff] [blame] | 100 | |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 101 | static int disable_tpa; |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 102 | module_param(disable_tpa, int, 0); |
Eilon Greenstein | 9898f86 | 2009-02-12 08:38:27 +0000 | [diff] [blame] | 103 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 104 | |
Merav Sicron | 0e8d2ec | 2012-06-19 07:48:30 +0000 | [diff] [blame] | 105 | int int_mode; |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 106 | module_param(int_mode, int, 0); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 107 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 108 | "(1 INT#x; 2 MSI)"); |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 109 | |
Eilon Greenstein | a18f512 | 2009-08-12 08:23:26 +0000 | [diff] [blame] | 110 | static int dropless_fc; |
| 111 | module_param(dropless_fc, int, 0); |
| 112 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); |
| 113 | |
Eilon Greenstein | 8d5726c | 2009-02-12 08:37:19 +0000 | [diff] [blame] | 114 | static int mrrs = -1; |
| 115 | module_param(mrrs, int, 0); |
| 116 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); |
| 117 | |
Eilon Greenstein | 9898f86 | 2009-02-12 08:38:27 +0000 | [diff] [blame] | 118 | static int debug; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 119 | module_param(debug, int, 0); |
Eilon Greenstein | 9898f86 | 2009-02-12 08:38:27 +0000 | [diff] [blame] | 120 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
| 121 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 122 | struct workqueue_struct *bnx2x_wq; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 123 | |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 124 | struct bnx2x_mac_vals { |
| 125 | u32 xmac_addr; |
| 126 | u32 xmac_val; |
| 127 | u32 emac_addr; |
| 128 | u32 emac_val; |
| 129 | u32 umac_addr; |
| 130 | u32 umac_val; |
| 131 | u32 bmac_addr; |
| 132 | u32 bmac_val[2]; |
| 133 | }; |
| 134 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 135 | enum bnx2x_board_type { |
| 136 | BCM57710 = 0, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 137 | BCM57711, |
| 138 | BCM57711E, |
| 139 | BCM57712, |
| 140 | BCM57712_MF, |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 141 | BCM57712_VF, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 142 | BCM57800, |
| 143 | BCM57800_MF, |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 144 | BCM57800_VF, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 145 | BCM57810, |
| 146 | BCM57810_MF, |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 147 | BCM57810_VF, |
Yuval Mintz | c3def94 | 2012-07-23 10:25:43 +0300 | [diff] [blame] | 148 | BCM57840_4_10, |
| 149 | BCM57840_2_20, |
Barak Witkowski | 7e8e02d | 2012-04-03 18:41:28 +0000 | [diff] [blame] | 150 | BCM57840_MF, |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 151 | BCM57840_VF, |
Barak Witkowski | 7e8e02d | 2012-04-03 18:41:28 +0000 | [diff] [blame] | 152 | BCM57811, |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 153 | BCM57811_MF, |
| 154 | BCM57840_O, |
| 155 | BCM57840_MFO, |
| 156 | BCM57811_VF |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 157 | }; |
| 158 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 159 | /* indexed by board_type, above */ |
Andrew Morton | 53a1056 | 2008-02-09 23:16:41 -0800 | [diff] [blame] | 160 | static struct { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 161 | char *name; |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 162 | } board_info[] = { |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 163 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
| 164 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, |
| 165 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, |
| 166 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, |
| 167 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, |
| 168 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, |
| 169 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, |
| 170 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, |
| 171 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, |
| 172 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, |
| 173 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, |
| 174 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, |
| 175 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, |
| 176 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, |
| 177 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, |
| 178 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, |
| 179 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, |
| 180 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, |
| 181 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, |
| 182 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, |
| 183 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 184 | }; |
| 185 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 186 | #ifndef PCI_DEVICE_ID_NX2_57710 |
| 187 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 |
| 188 | #endif |
| 189 | #ifndef PCI_DEVICE_ID_NX2_57711 |
| 190 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 |
| 191 | #endif |
| 192 | #ifndef PCI_DEVICE_ID_NX2_57711E |
| 193 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E |
| 194 | #endif |
| 195 | #ifndef PCI_DEVICE_ID_NX2_57712 |
| 196 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 |
| 197 | #endif |
| 198 | #ifndef PCI_DEVICE_ID_NX2_57712_MF |
| 199 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF |
| 200 | #endif |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 201 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
| 202 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF |
| 203 | #endif |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 204 | #ifndef PCI_DEVICE_ID_NX2_57800 |
| 205 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 |
| 206 | #endif |
| 207 | #ifndef PCI_DEVICE_ID_NX2_57800_MF |
| 208 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF |
| 209 | #endif |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 210 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
| 211 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF |
| 212 | #endif |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 213 | #ifndef PCI_DEVICE_ID_NX2_57810 |
| 214 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 |
| 215 | #endif |
| 216 | #ifndef PCI_DEVICE_ID_NX2_57810_MF |
| 217 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF |
| 218 | #endif |
Yuval Mintz | c3def94 | 2012-07-23 10:25:43 +0300 | [diff] [blame] | 219 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
| 220 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE |
| 221 | #endif |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 222 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
| 223 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF |
| 224 | #endif |
Yuval Mintz | c3def94 | 2012-07-23 10:25:43 +0300 | [diff] [blame] | 225 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
| 226 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 |
| 227 | #endif |
| 228 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 |
| 229 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 |
| 230 | #endif |
| 231 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO |
| 232 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 233 | #endif |
| 234 | #ifndef PCI_DEVICE_ID_NX2_57840_MF |
| 235 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF |
| 236 | #endif |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 237 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
| 238 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF |
| 239 | #endif |
Barak Witkowski | 7e8e02d | 2012-04-03 18:41:28 +0000 | [diff] [blame] | 240 | #ifndef PCI_DEVICE_ID_NX2_57811 |
| 241 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 |
| 242 | #endif |
| 243 | #ifndef PCI_DEVICE_ID_NX2_57811_MF |
| 244 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF |
| 245 | #endif |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 246 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
| 247 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF |
| 248 | #endif |
| 249 | |
Alexey Dobriyan | a3aa188 | 2010-01-07 11:58:11 +0000 | [diff] [blame] | 250 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
Eilon Greenstein | e4ed711 | 2009-08-12 08:24:10 +0000 | [diff] [blame] | 251 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
| 252 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, |
| 253 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 254 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 255 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 256 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 257 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
| 258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
| 261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, |
Yuval Mintz | c3def94 | 2012-07-23 10:25:43 +0300 | [diff] [blame] | 262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
| 263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, |
| 264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
Yuval Mintz | c3def94 | 2012-07-23 10:25:43 +0300 | [diff] [blame] | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
Barak Witkowski | 7e8e02d | 2012-04-03 18:41:28 +0000 | [diff] [blame] | 269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
| 270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 272 | { 0 } |
| 273 | }; |
| 274 | |
| 275 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); |
| 276 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 277 | /* Global resources for unloading a previously loaded device */ |
| 278 | #define BNX2X_PREV_WAIT_NEEDED 1 |
| 279 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); |
| 280 | static LIST_HEAD(bnx2x_prev_list); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 281 | /**************************************************************************** |
| 282 | * General service functions |
| 283 | ****************************************************************************/ |
| 284 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 285 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 286 | u32 addr, dma_addr_t mapping) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 287 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 288 | REG_WR(bp, addr, U64_LO(mapping)); |
| 289 | REG_WR(bp, addr + 4, U64_HI(mapping)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 290 | } |
| 291 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 292 | static void storm_memset_spq_addr(struct bnx2x *bp, |
| 293 | dma_addr_t mapping, u16 abs_fid) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 294 | { |
| 295 | u32 addr = XSEM_REG_FAST_MEMORY + |
| 296 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); |
| 297 | |
| 298 | __storm_memset_dma_mapping(bp, addr, mapping); |
| 299 | } |
| 300 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 301 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
| 302 | u16 pf_id) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 303 | { |
| 304 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
| 305 | pf_id); |
| 306 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), |
| 307 | pf_id); |
| 308 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), |
| 309 | pf_id); |
| 310 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), |
| 311 | pf_id); |
| 312 | } |
| 313 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 314 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
| 315 | u8 enable) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 316 | { |
| 317 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), |
| 318 | enable); |
| 319 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), |
| 320 | enable); |
| 321 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), |
| 322 | enable); |
| 323 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), |
| 324 | enable); |
| 325 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 326 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 327 | static void storm_memset_eq_data(struct bnx2x *bp, |
| 328 | struct event_ring_data *eq_data, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 329 | u16 pfid) |
| 330 | { |
| 331 | size_t size = sizeof(struct event_ring_data); |
| 332 | |
| 333 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); |
| 334 | |
| 335 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); |
| 336 | } |
| 337 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 338 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
| 339 | u16 pfid) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 340 | { |
| 341 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); |
| 342 | REG_WR16(bp, addr, eq_prod); |
| 343 | } |
| 344 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 345 | /* used only at init |
| 346 | * locking is done by mcp |
| 347 | */ |
stephen hemminger | 8d96286 | 2010-10-21 07:50:56 +0000 | [diff] [blame] | 348 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 349 | { |
| 350 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); |
| 351 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); |
| 352 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, |
| 353 | PCICFG_VENDOR_ID_OFFSET); |
| 354 | } |
| 355 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 356 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
| 357 | { |
| 358 | u32 val; |
| 359 | |
| 360 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); |
| 361 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); |
| 362 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, |
| 363 | PCICFG_VENDOR_ID_OFFSET); |
| 364 | |
| 365 | return val; |
| 366 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 367 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 368 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
| 369 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" |
| 370 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" |
| 371 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" |
| 372 | #define DMAE_DP_DST_NONE "dst_addr [none]" |
| 373 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 374 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
| 375 | struct dmae_command *dmae, int msglvl) |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 376 | { |
| 377 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 378 | int i; |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 379 | |
| 380 | switch (dmae->opcode & DMAE_COMMAND_DST) { |
| 381 | case DMAE_CMD_DST_PCI: |
| 382 | if (src_type == DMAE_CMD_SRC_PCI) |
| 383 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 384 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" |
| 385 | "comp_addr [%x:%08x], comp_val 0x%08x\n", |
| 386 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, |
| 387 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, |
| 388 | dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 389 | dmae->comp_val); |
| 390 | else |
| 391 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 392 | "src [%08x], len [%d*4], dst [%x:%08x]\n" |
| 393 | "comp_addr [%x:%08x], comp_val 0x%08x\n", |
| 394 | dmae->opcode, dmae->src_addr_lo >> 2, |
| 395 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, |
| 396 | dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 397 | dmae->comp_val); |
| 398 | break; |
| 399 | case DMAE_CMD_DST_GRC: |
| 400 | if (src_type == DMAE_CMD_SRC_PCI) |
| 401 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 402 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" |
| 403 | "comp_addr [%x:%08x], comp_val 0x%08x\n", |
| 404 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, |
| 405 | dmae->len, dmae->dst_addr_lo >> 2, |
| 406 | dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 407 | dmae->comp_val); |
| 408 | else |
| 409 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 410 | "src [%08x], len [%d*4], dst [%08x]\n" |
| 411 | "comp_addr [%x:%08x], comp_val 0x%08x\n", |
| 412 | dmae->opcode, dmae->src_addr_lo >> 2, |
| 413 | dmae->len, dmae->dst_addr_lo >> 2, |
| 414 | dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 415 | dmae->comp_val); |
| 416 | break; |
| 417 | default: |
| 418 | if (src_type == DMAE_CMD_SRC_PCI) |
| 419 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 420 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" |
| 421 | "comp_addr [%x:%08x] comp_val 0x%08x\n", |
| 422 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, |
| 423 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 424 | dmae->comp_val); |
| 425 | else |
| 426 | DP(msglvl, "DMAE: opcode 0x%08x\n" |
| 427 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" |
| 428 | "comp_addr [%x:%08x] comp_val 0x%08x\n", |
| 429 | dmae->opcode, dmae->src_addr_lo >> 2, |
| 430 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, |
| 431 | dmae->comp_val); |
| 432 | break; |
| 433 | } |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 434 | |
| 435 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) |
| 436 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", |
| 437 | i, *(((u32 *)dmae) + i)); |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 438 | } |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 439 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 440 | /* copy command into DMAE command memory and set DMAE command go */ |
Dmitry Kravkov | 6c719d0 | 2010-07-27 12:36:15 +0000 | [diff] [blame] | 441 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 442 | { |
| 443 | u32 cmd_offset; |
| 444 | int i; |
| 445 | |
| 446 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); |
| 447 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { |
| 448 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 449 | } |
| 450 | REG_WR(bp, dmae_reg_go_c[idx], 1); |
| 451 | } |
| 452 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 453 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
| 454 | { |
| 455 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
| 456 | DMAE_CMD_C_ENABLE); |
| 457 | } |
| 458 | |
| 459 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
| 460 | { |
| 461 | return opcode & ~DMAE_CMD_SRC_RESET; |
| 462 | } |
| 463 | |
| 464 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
| 465 | bool with_comp, u8 comp_type) |
| 466 | { |
| 467 | u32 opcode = 0; |
| 468 | |
| 469 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | |
| 470 | (dst_type << DMAE_COMMAND_DST_SHIFT)); |
| 471 | |
| 472 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
| 473 | |
| 474 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 475 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
| 476 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 477 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
| 478 | |
| 479 | #ifdef __BIG_ENDIAN |
| 480 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
| 481 | #else |
| 482 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
| 483 | #endif |
| 484 | if (with_comp) |
| 485 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); |
| 486 | return opcode; |
| 487 | } |
| 488 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 489 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
stephen hemminger | 8d96286 | 2010-10-21 07:50:56 +0000 | [diff] [blame] | 490 | struct dmae_command *dmae, |
| 491 | u8 src_type, u8 dst_type) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 492 | { |
| 493 | memset(dmae, 0, sizeof(struct dmae_command)); |
| 494 | |
| 495 | /* set the opcode */ |
| 496 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, |
| 497 | true, DMAE_COMP_PCI); |
| 498 | |
| 499 | /* fill in the completion parameters */ |
| 500 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); |
| 501 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); |
| 502 | dmae->comp_val = DMAE_COMP_VAL; |
| 503 | } |
| 504 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 505 | /* issue a dmae command over the init-channel and wait for completion */ |
| 506 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 507 | { |
| 508 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); |
Dmitry Kravkov | 5e374b5 | 2011-05-22 10:09:19 +0000 | [diff] [blame] | 509 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 510 | int rc = 0; |
| 511 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 512 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
| 513 | |
| 514 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 515 | * as long as this code is called both from syscall context and |
| 516 | * from ndo_set_rx_mode() flow that may be called from BH. |
| 517 | */ |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 518 | spin_lock_bh(&bp->dmae_lock); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 519 | |
| 520 | /* reset completion */ |
| 521 | *wb_comp = 0; |
| 522 | |
| 523 | /* post the command on the channel used for initializations */ |
| 524 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); |
| 525 | |
| 526 | /* wait for completion */ |
| 527 | udelay(5); |
| 528 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 529 | |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 530 | if (!cnt || |
| 531 | (bp->recovery_state != BNX2X_RECOVERY_DONE && |
| 532 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 533 | BNX2X_ERR("DMAE timeout!\n"); |
| 534 | rc = DMAE_TIMEOUT; |
| 535 | goto unlock; |
| 536 | } |
| 537 | cnt--; |
| 538 | udelay(50); |
| 539 | } |
| 540 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
| 541 | BNX2X_ERR("DMAE PCI error!\n"); |
| 542 | rc = DMAE_PCI_ERROR; |
| 543 | } |
| 544 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 545 | unlock: |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 546 | spin_unlock_bh(&bp->dmae_lock); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 547 | return rc; |
| 548 | } |
| 549 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 550 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, |
| 551 | u32 len32) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 552 | { |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 553 | int rc; |
Eilon Greenstein | 5ff7b6d | 2009-08-12 08:23:44 +0000 | [diff] [blame] | 554 | struct dmae_command dmae; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 555 | |
| 556 | if (!bp->dmae_ready) { |
| 557 | u32 *data = bnx2x_sp(bp, wb_data[0]); |
| 558 | |
Ariel Elior | 127a425 | 2012-01-26 06:01:46 +0000 | [diff] [blame] | 559 | if (CHIP_IS_E1(bp)) |
| 560 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); |
| 561 | else |
| 562 | bnx2x_init_str_wr(bp, dst_addr, data, len32); |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 563 | return; |
| 564 | } |
| 565 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 566 | /* set opcode and fixed command fields */ |
| 567 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 568 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 569 | /* fill in addresses and len */ |
Eilon Greenstein | 5ff7b6d | 2009-08-12 08:23:44 +0000 | [diff] [blame] | 570 | dmae.src_addr_lo = U64_LO(dma_addr); |
| 571 | dmae.src_addr_hi = U64_HI(dma_addr); |
| 572 | dmae.dst_addr_lo = dst_addr >> 2; |
| 573 | dmae.dst_addr_hi = 0; |
| 574 | dmae.len = len32; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 575 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 576 | /* issue the command and wait for completion */ |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 577 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
| 578 | if (rc) { |
| 579 | BNX2X_ERR("DMAE returned failure %d\n", rc); |
| 580 | bnx2x_panic(); |
| 581 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 582 | } |
| 583 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 584 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 585 | { |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 586 | int rc; |
Eilon Greenstein | 5ff7b6d | 2009-08-12 08:23:44 +0000 | [diff] [blame] | 587 | struct dmae_command dmae; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 588 | |
| 589 | if (!bp->dmae_ready) { |
| 590 | u32 *data = bnx2x_sp(bp, wb_data[0]); |
| 591 | int i; |
| 592 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 593 | if (CHIP_IS_E1(bp)) |
Ariel Elior | 127a425 | 2012-01-26 06:01:46 +0000 | [diff] [blame] | 594 | for (i = 0; i < len32; i++) |
| 595 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 596 | else |
Ariel Elior | 127a425 | 2012-01-26 06:01:46 +0000 | [diff] [blame] | 597 | for (i = 0; i < len32; i++) |
| 598 | data[i] = REG_RD(bp, src_addr + i*4); |
| 599 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 600 | return; |
| 601 | } |
| 602 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 603 | /* set opcode and fixed command fields */ |
| 604 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 605 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 606 | /* fill in addresses and len */ |
Eilon Greenstein | 5ff7b6d | 2009-08-12 08:23:44 +0000 | [diff] [blame] | 607 | dmae.src_addr_lo = src_addr >> 2; |
| 608 | dmae.src_addr_hi = 0; |
| 609 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); |
| 610 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); |
| 611 | dmae.len = len32; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 612 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 613 | /* issue the command and wait for completion */ |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 614 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
| 615 | if (rc) { |
| 616 | BNX2X_ERR("DMAE returned failure %d\n", rc); |
| 617 | bnx2x_panic(); |
Yuval Mintz | c957d09 | 2013-06-25 08:50:11 +0300 | [diff] [blame] | 618 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 619 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 620 | |
stephen hemminger | 8d96286 | 2010-10-21 07:50:56 +0000 | [diff] [blame] | 621 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
| 622 | u32 addr, u32 len) |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 623 | { |
Vladislav Zolotarov | 02e3c6c | 2010-04-19 01:13:33 +0000 | [diff] [blame] | 624 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 625 | int offset = 0; |
| 626 | |
Vladislav Zolotarov | 02e3c6c | 2010-04-19 01:13:33 +0000 | [diff] [blame] | 627 | while (len > dmae_wr_max) { |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 628 | bnx2x_write_dmae(bp, phys_addr + offset, |
Vladislav Zolotarov | 02e3c6c | 2010-04-19 01:13:33 +0000 | [diff] [blame] | 629 | addr + offset, dmae_wr_max); |
| 630 | offset += dmae_wr_max * 4; |
| 631 | len -= dmae_wr_max; |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); |
| 635 | } |
| 636 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 637 | static int bnx2x_mc_assert(struct bnx2x *bp) |
| 638 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 639 | char last_idx; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 640 | int i, rc = 0; |
| 641 | u32 row0, row1, row2, row3; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 642 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 643 | /* XSTORM */ |
| 644 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + |
| 645 | XSTORM_ASSERT_LIST_INDEX_OFFSET); |
| 646 | if (last_idx) |
| 647 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 648 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 649 | /* print the asserts */ |
| 650 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 651 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 652 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + |
| 653 | XSTORM_ASSERT_LIST_OFFSET(i)); |
| 654 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + |
| 655 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); |
| 656 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + |
| 657 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); |
| 658 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + |
| 659 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 660 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 661 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 662 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 663 | i, row3, row2, row1, row0); |
| 664 | rc++; |
| 665 | } else { |
| 666 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 667 | } |
| 668 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 669 | |
| 670 | /* TSTORM */ |
| 671 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + |
| 672 | TSTORM_ASSERT_LIST_INDEX_OFFSET); |
| 673 | if (last_idx) |
| 674 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); |
| 675 | |
| 676 | /* print the asserts */ |
| 677 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { |
| 678 | |
| 679 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + |
| 680 | TSTORM_ASSERT_LIST_OFFSET(i)); |
| 681 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + |
| 682 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); |
| 683 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + |
| 684 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); |
| 685 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + |
| 686 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); |
| 687 | |
| 688 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 689 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 690 | i, row3, row2, row1, row0); |
| 691 | rc++; |
| 692 | } else { |
| 693 | break; |
| 694 | } |
| 695 | } |
| 696 | |
| 697 | /* CSTORM */ |
| 698 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + |
| 699 | CSTORM_ASSERT_LIST_INDEX_OFFSET); |
| 700 | if (last_idx) |
| 701 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); |
| 702 | |
| 703 | /* print the asserts */ |
| 704 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { |
| 705 | |
| 706 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 707 | CSTORM_ASSERT_LIST_OFFSET(i)); |
| 708 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 709 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); |
| 710 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 711 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); |
| 712 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 713 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); |
| 714 | |
| 715 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 716 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 717 | i, row3, row2, row1, row0); |
| 718 | rc++; |
| 719 | } else { |
| 720 | break; |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | /* USTORM */ |
| 725 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + |
| 726 | USTORM_ASSERT_LIST_INDEX_OFFSET); |
| 727 | if (last_idx) |
| 728 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); |
| 729 | |
| 730 | /* print the asserts */ |
| 731 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { |
| 732 | |
| 733 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + |
| 734 | USTORM_ASSERT_LIST_OFFSET(i)); |
| 735 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + |
| 736 | USTORM_ASSERT_LIST_OFFSET(i) + 4); |
| 737 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + |
| 738 | USTORM_ASSERT_LIST_OFFSET(i) + 8); |
| 739 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + |
| 740 | USTORM_ASSERT_LIST_OFFSET(i) + 12); |
| 741 | |
| 742 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 743 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 744 | i, row3, row2, row1, row0); |
| 745 | rc++; |
| 746 | } else { |
| 747 | break; |
| 748 | } |
| 749 | } |
| 750 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 751 | return rc; |
| 752 | } |
Eliezer Tamir | c14423f | 2008-02-28 11:49:42 -0800 | [diff] [blame] | 753 | |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 754 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 755 | { |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 756 | u32 addr, val; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 757 | u32 mark, offset; |
Eilon Greenstein | 4781bfa | 2009-02-12 08:38:17 +0000 | [diff] [blame] | 758 | __be32 data[9]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 759 | int word; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 760 | u32 trace_shmem_base; |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 761 | if (BP_NOMCP(bp)) { |
| 762 | BNX2X_ERR("NO MCP - can not dump\n"); |
| 763 | return; |
| 764 | } |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 765 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
| 766 | (bp->common.bc_ver & 0xff0000) >> 16, |
| 767 | (bp->common.bc_ver & 0xff00) >> 8, |
| 768 | (bp->common.bc_ver & 0xff)); |
| 769 | |
| 770 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); |
| 771 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 772 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 773 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 774 | if (BP_PATH(bp) == 0) |
| 775 | trace_shmem_base = bp->common.shmem_base; |
| 776 | else |
| 777 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); |
Dmitry Kravkov | de12880 | 2012-03-18 10:33:45 +0000 | [diff] [blame] | 778 | addr = trace_shmem_base - 0x800; |
| 779 | |
| 780 | /* validate TRCB signature */ |
| 781 | mark = REG_RD(bp, addr); |
| 782 | if (mark != MFW_TRACE_SIGNATURE) { |
| 783 | BNX2X_ERR("Trace buffer signature is missing."); |
| 784 | return ; |
| 785 | } |
| 786 | |
| 787 | /* read cyclic buffer pointer */ |
| 788 | addr += 4; |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 789 | mark = REG_RD(bp, addr); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 790 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
| 791 | + ((mark + 0x3) & ~0x3) - 0x08000000; |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 792 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 793 | |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 794 | printk("%s", lvl); |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 795 | |
| 796 | /* dump buffer after the mark */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 797 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 798 | for (word = 0; word < 8; word++) |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 799 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 800 | data[8] = 0x0; |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 801 | pr_cont("%s", (char *)data); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 802 | } |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 803 | |
| 804 | /* dump buffer before the mark */ |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 805 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 806 | for (word = 0; word < 8; word++) |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 807 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 808 | data[8] = 0x0; |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 809 | pr_cont("%s", (char *)data); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 810 | } |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 811 | printk("%s" "end of fw dump\n", lvl); |
| 812 | } |
| 813 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 814 | static void bnx2x_fw_dump(struct bnx2x *bp) |
Dmitry Kravkov | 7a25cc7 | 2011-06-14 01:33:25 +0000 | [diff] [blame] | 815 | { |
| 816 | bnx2x_fw_dump_lvl(bp, KERN_ERR); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 817 | } |
| 818 | |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 819 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
| 820 | { |
| 821 | int port = BP_PORT(bp); |
| 822 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
| 823 | u32 val = REG_RD(bp, addr); |
| 824 | |
| 825 | /* in E1 we must use only PCI configuration space to disable |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 826 | * MSI/MSIX capability |
| 827 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 828 | */ |
| 829 | if (CHIP_IS_E1(bp)) { |
| 830 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on |
| 831 | * Use mask register to prevent from HC sending interrupts |
| 832 | * after we exit the function |
| 833 | */ |
| 834 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); |
| 835 | |
| 836 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
| 837 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
| 838 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
| 839 | } else |
| 840 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
| 841 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
| 842 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
| 843 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
| 844 | |
| 845 | DP(NETIF_MSG_IFDOWN, |
| 846 | "write %x to HC %d (addr 0x%x)\n", |
| 847 | val, port, addr); |
| 848 | |
| 849 | /* flush all outstanding writes */ |
| 850 | mmiowb(); |
| 851 | |
| 852 | REG_WR(bp, addr, val); |
| 853 | if (REG_RD(bp, addr) != val) |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 854 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 855 | } |
| 856 | |
| 857 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
| 858 | { |
| 859 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); |
| 860 | |
| 861 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | |
| 862 | IGU_PF_CONF_INT_LINE_EN | |
| 863 | IGU_PF_CONF_ATTN_BIT_EN); |
| 864 | |
| 865 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
| 866 | |
| 867 | /* flush all outstanding writes */ |
| 868 | mmiowb(); |
| 869 | |
| 870 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); |
| 871 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 872 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 873 | } |
| 874 | |
| 875 | static void bnx2x_int_disable(struct bnx2x *bp) |
| 876 | { |
| 877 | if (bp->common.int_block == INT_BLOCK_HC) |
| 878 | bnx2x_hc_int_disable(bp); |
| 879 | else |
| 880 | bnx2x_igu_int_disable(bp); |
| 881 | } |
| 882 | |
| 883 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 884 | { |
| 885 | int i; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 886 | u16 j; |
| 887 | struct hc_sp_status_block_data sp_sb_data; |
| 888 | int func = BP_FUNC(bp); |
| 889 | #ifdef BNX2X_STOP_ON_ERROR |
| 890 | u16 start = 0, end = 0; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 891 | u8 cos; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 892 | #endif |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 893 | if (disable_int) |
| 894 | bnx2x_int_disable(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 895 | |
Yitchak Gertner | 66e855f | 2008-08-13 15:49:05 -0700 | [diff] [blame] | 896 | bp->stats_state = STATS_STATE_DISABLED; |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 897 | bp->eth_stats.unrecoverable_error++; |
Yitchak Gertner | 66e855f | 2008-08-13 15:49:05 -0700 | [diff] [blame] | 898 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
| 899 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 900 | BNX2X_ERR("begin crash dump -----------------\n"); |
| 901 | |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 902 | /* Indices */ |
| 903 | /* Common */ |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 904 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 905 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
| 906 | bp->spq_prod_idx, bp->stats_counter); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 907 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
| 908 | bp->def_status_blk->atten_status_block.attn_bits, |
| 909 | bp->def_status_blk->atten_status_block.attn_bits_ack, |
| 910 | bp->def_status_blk->atten_status_block.status_block_id, |
| 911 | bp->def_status_blk->atten_status_block.attn_bits_index); |
| 912 | BNX2X_ERR(" def ("); |
| 913 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) |
| 914 | pr_cont("0x%x%s", |
Joe Perches | f1deab5 | 2011-08-14 12:16:21 +0000 | [diff] [blame] | 915 | bp->def_status_blk->sp_sb.index_values[i], |
| 916 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 917 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 918 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) |
| 919 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 920 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + |
| 921 | i*sizeof(u32)); |
| 922 | |
Joe Perches | f1deab5 | 2011-08-14 12:16:21 +0000 | [diff] [blame] | 923 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 924 | sp_sb_data.igu_sb_id, |
| 925 | sp_sb_data.igu_seg_id, |
| 926 | sp_sb_data.p_func.pf_id, |
| 927 | sp_sb_data.p_func.vnic_id, |
| 928 | sp_sb_data.p_func.vf_id, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 929 | sp_sb_data.p_func.vf_valid, |
| 930 | sp_sb_data.state); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 931 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 932 | for_each_eth_queue(bp, i) { |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 933 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 934 | int loop; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 935 | struct hc_status_block_data_e2 sb_data_e2; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 936 | struct hc_status_block_data_e1x sb_data_e1x; |
| 937 | struct hc_status_block_sm *hc_sm_p = |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 938 | CHIP_IS_E1x(bp) ? |
| 939 | sb_data_e1x.common.state_machine : |
| 940 | sb_data_e2.common.state_machine; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 941 | struct hc_index_data *hc_index_p = |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 942 | CHIP_IS_E1x(bp) ? |
| 943 | sb_data_e1x.index_data : |
| 944 | sb_data_e2.index_data; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 945 | u8 data_size, cos; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 946 | u32 *sb_data_p; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 947 | struct bnx2x_fp_txdata txdata; |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 948 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 949 | /* Rx */ |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 950 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 951 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 952 | fp->rx_comp_prod, |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 953 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 954 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 955 | fp->rx_sge_prod, fp->last_max_sge, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 956 | le16_to_cpu(fp->fp_hc_idx)); |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 957 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 958 | /* Tx */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 959 | for_each_cos_in_tx_queue(fp, cos) |
| 960 | { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 961 | txdata = *fp->txdata_ptr[cos]; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 962 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 963 | i, txdata.tx_pkt_prod, |
| 964 | txdata.tx_pkt_cons, txdata.tx_bd_prod, |
| 965 | txdata.tx_bd_cons, |
| 966 | le16_to_cpu(*txdata.tx_cons_sb)); |
| 967 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 968 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 969 | loop = CHIP_IS_E1x(bp) ? |
| 970 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 971 | |
| 972 | /* host sb data */ |
| 973 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 974 | if (IS_FCOE_FP(fp)) |
| 975 | continue; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 976 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 977 | BNX2X_ERR(" run indexes ("); |
| 978 | for (j = 0; j < HC_SB_MAX_SM; j++) |
| 979 | pr_cont("0x%x%s", |
| 980 | fp->sb_running_index[j], |
| 981 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); |
| 982 | |
| 983 | BNX2X_ERR(" indexes ("); |
| 984 | for (j = 0; j < loop; j++) |
| 985 | pr_cont("0x%x%s", |
| 986 | fp->sb_index_values[j], |
| 987 | (j == loop - 1) ? ")" : " "); |
| 988 | /* fw sb data */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 989 | data_size = CHIP_IS_E1x(bp) ? |
| 990 | sizeof(struct hc_status_block_data_e1x) : |
| 991 | sizeof(struct hc_status_block_data_e2); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 992 | data_size /= sizeof(u32); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 993 | sb_data_p = CHIP_IS_E1x(bp) ? |
| 994 | (u32 *)&sb_data_e1x : |
| 995 | (u32 *)&sb_data_e2; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 996 | /* copy sb data in here */ |
| 997 | for (j = 0; j < data_size; j++) |
| 998 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + |
| 999 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + |
| 1000 | j * sizeof(u32)); |
| 1001 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1002 | if (!CHIP_IS_E1x(bp)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1003 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1004 | sb_data_e2.common.p_func.pf_id, |
| 1005 | sb_data_e2.common.p_func.vf_id, |
| 1006 | sb_data_e2.common.p_func.vf_valid, |
| 1007 | sb_data_e2.common.p_func.vnic_id, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1008 | sb_data_e2.common.same_igu_sb_1b, |
| 1009 | sb_data_e2.common.state); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1010 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1011 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1012 | sb_data_e1x.common.p_func.pf_id, |
| 1013 | sb_data_e1x.common.p_func.vf_id, |
| 1014 | sb_data_e1x.common.p_func.vf_valid, |
| 1015 | sb_data_e1x.common.p_func.vnic_id, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1016 | sb_data_e1x.common.same_igu_sb_1b, |
| 1017 | sb_data_e1x.common.state); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1018 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1019 | |
| 1020 | /* SB_SMs data */ |
| 1021 | for (j = 0; j < HC_SB_MAX_SM; j++) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1022 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
| 1023 | j, hc_sm_p[j].__flags, |
| 1024 | hc_sm_p[j].igu_sb_id, |
| 1025 | hc_sm_p[j].igu_seg_id, |
| 1026 | hc_sm_p[j].time_to_expire, |
| 1027 | hc_sm_p[j].timer_value); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 1030 | /* Indices data */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1031 | for (j = 0; j < loop; j++) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1032 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1033 | hc_index_p[j].flags, |
| 1034 | hc_index_p[j].timeout); |
| 1035 | } |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1036 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1037 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1038 | #ifdef BNX2X_STOP_ON_ERROR |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 1039 | |
| 1040 | /* event queue */ |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 1041 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 1042 | for (i = 0; i < NUM_EQ_DESC; i++) { |
| 1043 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; |
| 1044 | |
| 1045 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", |
| 1046 | i, bp->eq_ring[i].message.opcode, |
| 1047 | bp->eq_ring[i].message.error); |
| 1048 | BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]); |
| 1049 | } |
| 1050 | |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1051 | /* Rings */ |
| 1052 | /* Rx */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1053 | for_each_valid_rx_queue(bp, i) { |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1054 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1055 | |
| 1056 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); |
| 1057 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1058 | for (j = start; j != end; j = RX_BD(j + 1)) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1059 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
| 1060 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; |
| 1061 | |
Eilon Greenstein | c3eefaf | 2009-03-02 08:01:09 +0000 | [diff] [blame] | 1062 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
Yuval Mintz | 44151ac | 2012-01-23 07:31:56 +0000 | [diff] [blame] | 1063 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1064 | } |
| 1065 | |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1066 | start = RX_SGE(fp->rx_sge_prod); |
| 1067 | end = RX_SGE(fp->last_max_sge); |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1068 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 1069 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
| 1070 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; |
| 1071 | |
Eilon Greenstein | c3eefaf | 2009-03-02 08:01:09 +0000 | [diff] [blame] | 1072 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
| 1073 | i, j, rx_sge[1], rx_sge[0], sw_page->page); |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 1074 | } |
| 1075 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1076 | start = RCQ_BD(fp->rx_comp_cons - 10); |
| 1077 | end = RCQ_BD(fp->rx_comp_cons + 503); |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1078 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1079 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
| 1080 | |
Eilon Greenstein | c3eefaf | 2009-03-02 08:01:09 +0000 | [diff] [blame] | 1081 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
| 1082 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1083 | } |
| 1084 | } |
| 1085 | |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1086 | /* Tx */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1087 | for_each_valid_tx_queue(bp, i) { |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1088 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1089 | for_each_cos_in_tx_queue(fp, cos) { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 1090 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1091 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1092 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); |
| 1093 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); |
| 1094 | for (j = start; j != end; j = TX_BD(j + 1)) { |
| 1095 | struct sw_tx_bd *sw_bd = |
| 1096 | &txdata->tx_buf_ring[j]; |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1097 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1098 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1099 | i, cos, j, sw_bd->skb, |
| 1100 | sw_bd->first_bd); |
| 1101 | } |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1102 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1103 | start = TX_BD(txdata->tx_bd_cons - 10); |
| 1104 | end = TX_BD(txdata->tx_bd_cons + 254); |
| 1105 | for (j = start; j != end; j = TX_BD(j + 1)) { |
| 1106 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1107 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1108 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1109 | i, cos, j, tx_bd[0], tx_bd[1], |
| 1110 | tx_bd[2], tx_bd[3]); |
| 1111 | } |
Eilon Greenstein | 8440d2b | 2009-02-12 08:38:22 +0000 | [diff] [blame] | 1112 | } |
| 1113 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1114 | #endif |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1115 | bnx2x_fw_dump(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1116 | bnx2x_mc_assert(bp); |
| 1117 | BNX2X_ERR("end crash dump -----------------\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1118 | } |
| 1119 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1120 | /* |
| 1121 | * FLR Support for E2 |
| 1122 | * |
| 1123 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW |
| 1124 | * initialization. |
| 1125 | */ |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 1126 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1127 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
| 1128 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1129 | |
| 1130 | struct pbf_pN_buf_regs { |
| 1131 | int pN; |
| 1132 | u32 init_crd; |
| 1133 | u32 crd; |
| 1134 | u32 crd_freed; |
| 1135 | }; |
| 1136 | |
| 1137 | struct pbf_pN_cmd_regs { |
| 1138 | int pN; |
| 1139 | u32 lines_occup; |
| 1140 | u32 lines_freed; |
| 1141 | }; |
| 1142 | |
| 1143 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, |
| 1144 | struct pbf_pN_buf_regs *regs, |
| 1145 | u32 poll_count) |
| 1146 | { |
| 1147 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; |
| 1148 | u32 cur_cnt = poll_count; |
| 1149 | |
| 1150 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); |
| 1151 | crd = crd_start = REG_RD(bp, regs->crd); |
| 1152 | init_crd = REG_RD(bp, regs->init_crd); |
| 1153 | |
| 1154 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); |
| 1155 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); |
| 1156 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); |
| 1157 | |
| 1158 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < |
| 1159 | (init_crd - crd_start))) { |
| 1160 | if (cur_cnt--) { |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1161 | udelay(FLR_WAIT_INTERVAL); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1162 | crd = REG_RD(bp, regs->crd); |
| 1163 | crd_freed = REG_RD(bp, regs->crd_freed); |
| 1164 | } else { |
| 1165 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", |
| 1166 | regs->pN); |
| 1167 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", |
| 1168 | regs->pN, crd); |
| 1169 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", |
| 1170 | regs->pN, crd_freed); |
| 1171 | break; |
| 1172 | } |
| 1173 | } |
| 1174 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1175 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1176 | } |
| 1177 | |
| 1178 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, |
| 1179 | struct pbf_pN_cmd_regs *regs, |
| 1180 | u32 poll_count) |
| 1181 | { |
| 1182 | u32 occup, to_free, freed, freed_start; |
| 1183 | u32 cur_cnt = poll_count; |
| 1184 | |
| 1185 | occup = to_free = REG_RD(bp, regs->lines_occup); |
| 1186 | freed = freed_start = REG_RD(bp, regs->lines_freed); |
| 1187 | |
| 1188 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); |
| 1189 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); |
| 1190 | |
| 1191 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { |
| 1192 | if (cur_cnt--) { |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1193 | udelay(FLR_WAIT_INTERVAL); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1194 | occup = REG_RD(bp, regs->lines_occup); |
| 1195 | freed = REG_RD(bp, regs->lines_freed); |
| 1196 | } else { |
| 1197 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", |
| 1198 | regs->pN); |
| 1199 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", |
| 1200 | regs->pN, occup); |
| 1201 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", |
| 1202 | regs->pN, freed); |
| 1203 | break; |
| 1204 | } |
| 1205 | } |
| 1206 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1207 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1208 | } |
| 1209 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 1210 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
| 1211 | u32 expected, u32 poll_count) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1212 | { |
| 1213 | u32 cur_cnt = poll_count; |
| 1214 | u32 val; |
| 1215 | |
| 1216 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1217 | udelay(FLR_WAIT_INTERVAL); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1218 | |
| 1219 | return val; |
| 1220 | } |
| 1221 | |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 1222 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
| 1223 | char *msg, u32 poll_cnt) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1224 | { |
| 1225 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); |
| 1226 | if (val != 0) { |
| 1227 | BNX2X_ERR("%s usage count=%d\n", msg, val); |
| 1228 | return 1; |
| 1229 | } |
| 1230 | return 0; |
| 1231 | } |
| 1232 | |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 1233 | /* Common routines with VF FLR cleanup */ |
| 1234 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1235 | { |
| 1236 | /* adjust polling timeout */ |
| 1237 | if (CHIP_REV_IS_EMUL(bp)) |
| 1238 | return FLR_POLL_CNT * 2000; |
| 1239 | |
| 1240 | if (CHIP_REV_IS_FPGA(bp)) |
| 1241 | return FLR_POLL_CNT * 120; |
| 1242 | |
| 1243 | return FLR_POLL_CNT; |
| 1244 | } |
| 1245 | |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 1246 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1247 | { |
| 1248 | struct pbf_pN_cmd_regs cmd_regs[] = { |
| 1249 | {0, (CHIP_IS_E3B0(bp)) ? |
| 1250 | PBF_REG_TQ_OCCUPANCY_Q0 : |
| 1251 | PBF_REG_P0_TQ_OCCUPANCY, |
| 1252 | (CHIP_IS_E3B0(bp)) ? |
| 1253 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : |
| 1254 | PBF_REG_P0_TQ_LINES_FREED_CNT}, |
| 1255 | {1, (CHIP_IS_E3B0(bp)) ? |
| 1256 | PBF_REG_TQ_OCCUPANCY_Q1 : |
| 1257 | PBF_REG_P1_TQ_OCCUPANCY, |
| 1258 | (CHIP_IS_E3B0(bp)) ? |
| 1259 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : |
| 1260 | PBF_REG_P1_TQ_LINES_FREED_CNT}, |
| 1261 | {4, (CHIP_IS_E3B0(bp)) ? |
| 1262 | PBF_REG_TQ_OCCUPANCY_LB_Q : |
| 1263 | PBF_REG_P4_TQ_OCCUPANCY, |
| 1264 | (CHIP_IS_E3B0(bp)) ? |
| 1265 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : |
| 1266 | PBF_REG_P4_TQ_LINES_FREED_CNT} |
| 1267 | }; |
| 1268 | |
| 1269 | struct pbf_pN_buf_regs buf_regs[] = { |
| 1270 | {0, (CHIP_IS_E3B0(bp)) ? |
| 1271 | PBF_REG_INIT_CRD_Q0 : |
| 1272 | PBF_REG_P0_INIT_CRD , |
| 1273 | (CHIP_IS_E3B0(bp)) ? |
| 1274 | PBF_REG_CREDIT_Q0 : |
| 1275 | PBF_REG_P0_CREDIT, |
| 1276 | (CHIP_IS_E3B0(bp)) ? |
| 1277 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : |
| 1278 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, |
| 1279 | {1, (CHIP_IS_E3B0(bp)) ? |
| 1280 | PBF_REG_INIT_CRD_Q1 : |
| 1281 | PBF_REG_P1_INIT_CRD, |
| 1282 | (CHIP_IS_E3B0(bp)) ? |
| 1283 | PBF_REG_CREDIT_Q1 : |
| 1284 | PBF_REG_P1_CREDIT, |
| 1285 | (CHIP_IS_E3B0(bp)) ? |
| 1286 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : |
| 1287 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, |
| 1288 | {4, (CHIP_IS_E3B0(bp)) ? |
| 1289 | PBF_REG_INIT_CRD_LB_Q : |
| 1290 | PBF_REG_P4_INIT_CRD, |
| 1291 | (CHIP_IS_E3B0(bp)) ? |
| 1292 | PBF_REG_CREDIT_LB_Q : |
| 1293 | PBF_REG_P4_CREDIT, |
| 1294 | (CHIP_IS_E3B0(bp)) ? |
| 1295 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : |
| 1296 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, |
| 1297 | }; |
| 1298 | |
| 1299 | int i; |
| 1300 | |
| 1301 | /* Verify the command queues are flushed P0, P1, P4 */ |
| 1302 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) |
| 1303 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); |
| 1304 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1305 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
| 1306 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) |
| 1307 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); |
| 1308 | } |
| 1309 | |
| 1310 | #define OP_GEN_PARAM(param) \ |
| 1311 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) |
| 1312 | |
| 1313 | #define OP_GEN_TYPE(type) \ |
| 1314 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) |
| 1315 | |
| 1316 | #define OP_GEN_AGG_VECT(index) \ |
| 1317 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) |
| 1318 | |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 1319 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1320 | { |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 1321 | u32 op_gen_command = 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1322 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
| 1323 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); |
| 1324 | int ret = 0; |
| 1325 | |
| 1326 | if (REG_RD(bp, comp_addr)) { |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1327 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1328 | return 1; |
| 1329 | } |
| 1330 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 1331 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
| 1332 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); |
| 1333 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); |
| 1334 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1335 | |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1336 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 1337 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1338 | |
| 1339 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { |
| 1340 | BNX2X_ERR("FW final cleanup did not succeed\n"); |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1341 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
| 1342 | (REG_RD(bp, comp_addr))); |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 1343 | bnx2x_panic(); |
| 1344 | return 1; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1345 | } |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 1346 | /* Zero completion for next FLR */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1347 | REG_WR(bp, comp_addr, 0); |
| 1348 | |
| 1349 | return ret; |
| 1350 | } |
| 1351 | |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 1352 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1353 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1354 | u16 status; |
| 1355 | |
Jiang Liu | 2a80eeb | 2012-08-20 13:26:51 -0600 | [diff] [blame] | 1356 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1357 | return status & PCI_EXP_DEVSTA_TRPND; |
| 1358 | } |
| 1359 | |
| 1360 | /* PF FLR specific routines |
| 1361 | */ |
| 1362 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) |
| 1363 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1364 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
| 1365 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1366 | CFC_REG_NUM_LCIDS_INSIDE_PF, |
| 1367 | "CFC PF usage counter timed out", |
| 1368 | poll_cnt)) |
| 1369 | return 1; |
| 1370 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1371 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
| 1372 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1373 | DORQ_REG_PF_USAGE_CNT, |
| 1374 | "DQ PF usage counter timed out", |
| 1375 | poll_cnt)) |
| 1376 | return 1; |
| 1377 | |
| 1378 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ |
| 1379 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1380 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), |
| 1381 | "QM PF usage counter timed out", |
| 1382 | poll_cnt)) |
| 1383 | return 1; |
| 1384 | |
| 1385 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ |
| 1386 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1387 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), |
| 1388 | "Timers VNIC usage counter timed out", |
| 1389 | poll_cnt)) |
| 1390 | return 1; |
| 1391 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1392 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), |
| 1393 | "Timers NUM_SCANS usage counter timed out", |
| 1394 | poll_cnt)) |
| 1395 | return 1; |
| 1396 | |
| 1397 | /* Wait DMAE PF usage counter to zero */ |
| 1398 | if (bnx2x_flr_clnup_poll_hw_counter(bp, |
| 1399 | dmae_reg_go_c[INIT_DMAE_C(bp)], |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 1400 | "DMAE command register timed out", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1401 | poll_cnt)) |
| 1402 | return 1; |
| 1403 | |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
| 1407 | static void bnx2x_hw_enable_status(struct bnx2x *bp) |
| 1408 | { |
| 1409 | u32 val; |
| 1410 | |
| 1411 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); |
| 1412 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); |
| 1413 | |
| 1414 | val = REG_RD(bp, PBF_REG_DISABLE_PF); |
| 1415 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); |
| 1416 | |
| 1417 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); |
| 1418 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); |
| 1419 | |
| 1420 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); |
| 1421 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); |
| 1422 | |
| 1423 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); |
| 1424 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); |
| 1425 | |
| 1426 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); |
| 1427 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); |
| 1428 | |
| 1429 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); |
| 1430 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); |
| 1431 | |
| 1432 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); |
| 1433 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", |
| 1434 | val); |
| 1435 | } |
| 1436 | |
| 1437 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) |
| 1438 | { |
| 1439 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); |
| 1440 | |
| 1441 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); |
| 1442 | |
| 1443 | /* Re-enable PF target read access */ |
| 1444 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
| 1445 | |
| 1446 | /* Poll HW usage counters */ |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 1447 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1448 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
| 1449 | return -EBUSY; |
| 1450 | |
| 1451 | /* Zero the igu 'trailing edge' and 'leading edge' */ |
| 1452 | |
| 1453 | /* Send the FW cleanup command */ |
| 1454 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) |
| 1455 | return -EBUSY; |
| 1456 | |
| 1457 | /* ATC cleanup */ |
| 1458 | |
| 1459 | /* Verify TX hw is flushed */ |
| 1460 | bnx2x_tx_hw_flushed(bp, poll_cnt); |
| 1461 | |
| 1462 | /* Wait 100ms (not adjusted according to platform) */ |
| 1463 | msleep(100); |
| 1464 | |
| 1465 | /* Verify no pending pci transactions */ |
| 1466 | if (bnx2x_is_pcie_pending(bp->pdev)) |
| 1467 | BNX2X_ERR("PCIE Transactions still pending\n"); |
| 1468 | |
| 1469 | /* Debug */ |
| 1470 | bnx2x_hw_enable_status(bp); |
| 1471 | |
| 1472 | /* |
| 1473 | * Master enable - Due to WB DMAE writes performed before this |
| 1474 | * register is re-initialized as part of the regular function init |
| 1475 | */ |
| 1476 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
| 1477 | |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1481 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1482 | { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1483 | int port = BP_PORT(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1484 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
| 1485 | u32 val = REG_RD(bp, addr); |
Dmitry Kravkov | 69c326b | 2012-05-02 01:16:33 +0000 | [diff] [blame] | 1486 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
| 1487 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; |
| 1488 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1489 | |
| 1490 | if (msix) { |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 1491 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
| 1492 | HC_CONFIG_0_REG_INT_LINE_EN_0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1493 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
| 1494 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
Dmitry Kravkov | 69c326b | 2012-05-02 01:16:33 +0000 | [diff] [blame] | 1495 | if (single_msix) |
| 1496 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 1497 | } else if (msi) { |
| 1498 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; |
| 1499 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
| 1500 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
| 1501 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1502 | } else { |
| 1503 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
Eliezer Tamir | 615f8fd | 2008-02-28 11:54:54 -0800 | [diff] [blame] | 1504 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1505 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
| 1506 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
Eliezer Tamir | 615f8fd | 2008-02-28 11:54:54 -0800 | [diff] [blame] | 1507 | |
Dmitry Kravkov | a0fd065 | 2010-10-19 05:13:05 +0000 | [diff] [blame] | 1508 | if (!CHIP_IS_E1(bp)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1509 | DP(NETIF_MSG_IFUP, |
| 1510 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); |
Eliezer Tamir | 615f8fd | 2008-02-28 11:54:54 -0800 | [diff] [blame] | 1511 | |
Dmitry Kravkov | a0fd065 | 2010-10-19 05:13:05 +0000 | [diff] [blame] | 1512 | REG_WR(bp, addr, val); |
Eliezer Tamir | 615f8fd | 2008-02-28 11:54:54 -0800 | [diff] [blame] | 1513 | |
Dmitry Kravkov | a0fd065 | 2010-10-19 05:13:05 +0000 | [diff] [blame] | 1514 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
| 1515 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1516 | } |
| 1517 | |
Dmitry Kravkov | a0fd065 | 2010-10-19 05:13:05 +0000 | [diff] [blame] | 1518 | if (CHIP_IS_E1(bp)) |
| 1519 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); |
| 1520 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1521 | DP(NETIF_MSG_IFUP, |
| 1522 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, |
| 1523 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1524 | |
| 1525 | REG_WR(bp, addr, val); |
Eilon Greenstein | 37dbbf3 | 2009-07-21 05:47:33 +0000 | [diff] [blame] | 1526 | /* |
| 1527 | * Ensure that HC_CONFIG is written before leading/trailing edge config |
| 1528 | */ |
| 1529 | mmiowb(); |
| 1530 | barrier(); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1531 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1532 | if (!CHIP_IS_E1(bp)) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1533 | /* init leading/trailing edge */ |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 1534 | if (IS_MF(bp)) { |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 1535 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1536 | if (bp->port.pmf) |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 1537 | /* enable nig and gpio3 attention */ |
| 1538 | val |= 0x1100; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1539 | } else |
| 1540 | val = 0xffff; |
| 1541 | |
| 1542 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); |
| 1543 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); |
| 1544 | } |
Eilon Greenstein | 37dbbf3 | 2009-07-21 05:47:33 +0000 | [diff] [blame] | 1545 | |
| 1546 | /* Make sure that interrupts are indeed enabled from here on */ |
| 1547 | mmiowb(); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1548 | } |
| 1549 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1550 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
| 1551 | { |
| 1552 | u32 val; |
Dmitry Kravkov | 30a5de7 | 2012-04-03 18:41:26 +0000 | [diff] [blame] | 1553 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
| 1554 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; |
| 1555 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1556 | |
| 1557 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); |
| 1558 | |
| 1559 | if (msix) { |
| 1560 | val &= ~(IGU_PF_CONF_INT_LINE_EN | |
| 1561 | IGU_PF_CONF_SINGLE_ISR_EN); |
Yuval Mintz | ebe61d8 | 2013-01-14 05:11:48 +0000 | [diff] [blame] | 1562 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1563 | IGU_PF_CONF_ATTN_BIT_EN); |
Dmitry Kravkov | 30a5de7 | 2012-04-03 18:41:26 +0000 | [diff] [blame] | 1564 | |
| 1565 | if (single_msix) |
| 1566 | val |= IGU_PF_CONF_SINGLE_ISR_EN; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1567 | } else if (msi) { |
| 1568 | val &= ~IGU_PF_CONF_INT_LINE_EN; |
Yuval Mintz | ebe61d8 | 2013-01-14 05:11:48 +0000 | [diff] [blame] | 1569 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1570 | IGU_PF_CONF_ATTN_BIT_EN | |
| 1571 | IGU_PF_CONF_SINGLE_ISR_EN); |
| 1572 | } else { |
| 1573 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; |
Yuval Mintz | ebe61d8 | 2013-01-14 05:11:48 +0000 | [diff] [blame] | 1574 | val |= (IGU_PF_CONF_INT_LINE_EN | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1575 | IGU_PF_CONF_ATTN_BIT_EN | |
| 1576 | IGU_PF_CONF_SINGLE_ISR_EN); |
| 1577 | } |
| 1578 | |
Yuval Mintz | ebe61d8 | 2013-01-14 05:11:48 +0000 | [diff] [blame] | 1579 | /* Clean previous status - need to configure igu prior to ack*/ |
| 1580 | if ((!msix) || single_msix) { |
| 1581 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); |
| 1582 | bnx2x_ack_int(bp); |
| 1583 | } |
| 1584 | |
| 1585 | val |= IGU_PF_CONF_FUNC_EN; |
| 1586 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1587 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1588 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
| 1589 | |
| 1590 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); |
| 1591 | |
Yuval Mintz | 79a8557 | 2012-04-03 18:41:25 +0000 | [diff] [blame] | 1592 | if (val & IGU_PF_CONF_INT_LINE_EN) |
| 1593 | pci_intx(bp->pdev, true); |
| 1594 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1595 | barrier(); |
| 1596 | |
| 1597 | /* init leading/trailing edge */ |
| 1598 | if (IS_MF(bp)) { |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 1599 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 1600 | if (bp->port.pmf) |
| 1601 | /* enable nig and gpio3 attention */ |
| 1602 | val |= 0x1100; |
| 1603 | } else |
| 1604 | val = 0xffff; |
| 1605 | |
| 1606 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
| 1607 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); |
| 1608 | |
| 1609 | /* Make sure that interrupts are indeed enabled from here on */ |
| 1610 | mmiowb(); |
| 1611 | } |
| 1612 | |
| 1613 | void bnx2x_int_enable(struct bnx2x *bp) |
| 1614 | { |
| 1615 | if (bp->common.int_block == INT_BLOCK_HC) |
| 1616 | bnx2x_hc_int_enable(bp); |
| 1617 | else |
| 1618 | bnx2x_igu_int_enable(bp); |
| 1619 | } |
| 1620 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 1621 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1622 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1623 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 1624 | int i, offset; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1625 | |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 1626 | if (disable_hw) |
| 1627 | /* prevent the HW from sending interrupts */ |
| 1628 | bnx2x_int_disable(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1629 | |
| 1630 | /* make sure all ISRs are done */ |
| 1631 | if (msix) { |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 1632 | synchronize_irq(bp->msix_table[0].vector); |
| 1633 | offset = 1; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1634 | if (CNIC_SUPPORT(bp)) |
| 1635 | offset++; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1636 | for_each_eth_queue(bp, i) |
Dmitry Kravkov | 754a2f5 | 2011-06-14 01:34:02 +0000 | [diff] [blame] | 1637 | synchronize_irq(bp->msix_table[offset++].vector); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1638 | } else |
| 1639 | synchronize_irq(bp->pdev->irq); |
| 1640 | |
| 1641 | /* make sure sp_task is not running */ |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 1642 | cancel_delayed_work(&bp->sp_task); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 1643 | cancel_delayed_work(&bp->period_task); |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 1644 | flush_workqueue(bnx2x_wq); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1645 | } |
| 1646 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1647 | /* fast path */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1648 | |
| 1649 | /* |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1650 | * General service functions |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1651 | */ |
| 1652 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1653 | /* Return true if succeeded to acquire the lock */ |
| 1654 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) |
| 1655 | { |
| 1656 | u32 lock_status; |
| 1657 | u32 resource_bit = (1 << resource); |
| 1658 | int func = BP_FUNC(bp); |
| 1659 | u32 hw_lock_control_reg; |
| 1660 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1661 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
| 1662 | "Trying to take a lock on resource %d\n", resource); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1663 | |
| 1664 | /* Validating that the resource is within range */ |
| 1665 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1666 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1667 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
| 1668 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
Eric Dumazet | 0fdf4d0 | 2010-08-26 22:03:53 -0700 | [diff] [blame] | 1669 | return false; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1670 | } |
| 1671 | |
| 1672 | if (func <= 5) |
| 1673 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); |
| 1674 | else |
| 1675 | hw_lock_control_reg = |
| 1676 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); |
| 1677 | |
| 1678 | /* Try to acquire the lock */ |
| 1679 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
| 1680 | lock_status = REG_RD(bp, hw_lock_control_reg); |
| 1681 | if (lock_status & resource_bit) |
| 1682 | return true; |
| 1683 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1684 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
| 1685 | "Failed to get a lock on resource %d\n", resource); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 1686 | return false; |
| 1687 | } |
| 1688 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1689 | /** |
| 1690 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id |
| 1691 | * |
| 1692 | * @bp: driver handle |
| 1693 | * |
| 1694 | * Returns the recovery leader resource id according to the engine this function |
| 1695 | * belongs to. Currently only only 2 engines is supported. |
| 1696 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 1697 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1698 | { |
| 1699 | if (BP_PATH(bp)) |
| 1700 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; |
| 1701 | else |
| 1702 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; |
| 1703 | } |
| 1704 | |
| 1705 | /** |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 1706 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1707 | * |
| 1708 | * @bp: driver handle |
| 1709 | * |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 1710 | * Tries to acquire a leader lock for current engine. |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1711 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 1712 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1713 | { |
| 1714 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); |
| 1715 | } |
| 1716 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1717 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1718 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 1719 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
| 1720 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) |
| 1721 | { |
| 1722 | /* Set the interrupt occurred bit for the sp-task to recognize it |
| 1723 | * must ack the interrupt and transition according to the IGU |
| 1724 | * state machine. |
| 1725 | */ |
| 1726 | atomic_set(&bp->interrupt_occurred, 1); |
| 1727 | |
| 1728 | /* The sp_task must execute only after this bit |
| 1729 | * is set, otherwise we will get out of sync and miss all |
| 1730 | * further interrupts. Hence, the barrier. |
| 1731 | */ |
| 1732 | smp_wmb(); |
| 1733 | |
| 1734 | /* schedule sp_task to workqueue */ |
| 1735 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
| 1736 | } |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1737 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1738 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1739 | { |
| 1740 | struct bnx2x *bp = fp->bp; |
| 1741 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); |
| 1742 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1743 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 1744 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1745 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1746 | DP(BNX2X_MSG_SP, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1747 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
Eilon Greenstein | 0626b89 | 2009-02-12 08:38:14 +0000 | [diff] [blame] | 1748 | fp->index, cid, command, bp->state, |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1749 | rr_cqe->ramrod_cqe.ramrod_type); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1750 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 1751 | /* If cid is within VF range, replace the slowpath object with the |
| 1752 | * one corresponding to this VF |
| 1753 | */ |
| 1754 | if (cid >= BNX2X_FIRST_VF_CID && |
| 1755 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) |
| 1756 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); |
| 1757 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1758 | switch (command) { |
| 1759 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1760 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1761 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
| 1762 | break; |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1763 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1764 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1765 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1766 | drv_cmd = BNX2X_Q_CMD_SETUP; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1767 | break; |
| 1768 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1769 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1770 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1771 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
| 1772 | break; |
| 1773 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1774 | case (RAMROD_CMD_ID_ETH_HALT): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1775 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1776 | drv_cmd = BNX2X_Q_CMD_HALT; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1777 | break; |
| 1778 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1779 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 1780 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1781 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
| 1782 | break; |
| 1783 | |
| 1784 | case (RAMROD_CMD_ID_ETH_EMPTY): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1785 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1786 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
Eliezer Tamir | 49d6677 | 2008-02-28 11:53:13 -0800 | [diff] [blame] | 1787 | break; |
| 1788 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1789 | default: |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1790 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", |
| 1791 | command, fp->index); |
| 1792 | return; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1793 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1794 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1795 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
| 1796 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) |
| 1797 | /* q_obj->complete_cmd() failure means that this was |
| 1798 | * an unexpected completion. |
| 1799 | * |
| 1800 | * In this case we don't want to increase the bp->spq_left |
| 1801 | * because apparently we haven't sent this command the first |
| 1802 | * place. |
| 1803 | */ |
| 1804 | #ifdef BNX2X_STOP_ON_ERROR |
| 1805 | bnx2x_panic(); |
| 1806 | #else |
| 1807 | return; |
| 1808 | #endif |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 1809 | /* SRIOV: reschedule any 'in_progress' operations */ |
| 1810 | bnx2x_iov_sp_event(bp, cid, true); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1811 | |
Dmitry Kravkov | 8fe23fb | 2010-10-06 03:27:41 +0000 | [diff] [blame] | 1812 | smp_mb__before_atomic_inc(); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 1813 | atomic_inc(&bp->cq_spq_left); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1814 | /* push the change in bp->spq_left and towards the memory */ |
| 1815 | smp_mb__after_atomic_inc(); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1816 | |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 1817 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
| 1818 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 1819 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
| 1820 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { |
| 1821 | /* if Q update ramrod is completed for last Q in AFEX vif set |
| 1822 | * flow, then ACK MCP at the end |
| 1823 | * |
| 1824 | * mark pending ACK to MCP bit. |
| 1825 | * prevent case that both bits are cleared. |
| 1826 | * At the end of load/unload driver checks that |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 1827 | * sp_state is cleared, and this order prevents |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 1828 | * races |
| 1829 | */ |
| 1830 | smp_mb__before_clear_bit(); |
| 1831 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); |
| 1832 | wmb(); |
| 1833 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
| 1834 | smp_mb__after_clear_bit(); |
| 1835 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 1836 | /* schedule the sp task as mcp ack is required */ |
| 1837 | bnx2x_schedule_sp_task(bp); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 1838 | } |
| 1839 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1840 | return; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1841 | } |
| 1842 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 1843 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1844 | { |
Eilon Greenstein | 555f6c7 | 2009-02-12 08:36:11 +0000 | [diff] [blame] | 1845 | struct bnx2x *bp = netdev_priv(dev_instance); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1846 | u16 status = bnx2x_ack_int(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1847 | u16 mask; |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 1848 | int i; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1849 | u8 cos; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1850 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1851 | /* Return here if interrupt is shared and it's not for us */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1852 | if (unlikely(status == 0)) { |
| 1853 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); |
| 1854 | return IRQ_NONE; |
| 1855 | } |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 1856 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1857 | |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 1858 | #ifdef BNX2X_STOP_ON_ERROR |
| 1859 | if (unlikely(bp->panic)) |
| 1860 | return IRQ_HANDLED; |
| 1861 | #endif |
| 1862 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 1863 | for_each_eth_queue(bp, i) { |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 1864 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1865 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1866 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 1867 | if (status & mask) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1868 | /* Handle Rx or Tx according to SB id */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 1869 | for_each_cos_in_tx_queue(fp, cos) |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 1870 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 1871 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
Vladislav Zolotarov | 54b9dda | 2009-11-16 06:05:58 +0000 | [diff] [blame] | 1872 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 1873 | status &= ~mask; |
| 1874 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1875 | } |
| 1876 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1877 | if (CNIC_SUPPORT(bp)) { |
| 1878 | mask = 0x2; |
| 1879 | if (status & (mask | 0x1)) { |
| 1880 | struct cnic_ops *c_ops = NULL; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 1881 | |
Michael Chan | ad9b435 | 2013-01-23 03:21:52 +0000 | [diff] [blame] | 1882 | rcu_read_lock(); |
| 1883 | c_ops = rcu_dereference(bp->cnic_ops); |
| 1884 | if (c_ops && (bp->cnic_eth_dev.drv_state & |
| 1885 | CNIC_DRV_STATE_HANDLES_IRQ)) |
| 1886 | c_ops->cnic_handler(bp->cnic_data, NULL); |
| 1887 | rcu_read_unlock(); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 1888 | |
| 1889 | status &= ~mask; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 1890 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 1891 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1892 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1893 | if (unlikely(status & 0x1)) { |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 1894 | |
| 1895 | /* schedule sp task to perform default status block work, ack |
| 1896 | * attentions and enable interrupts. |
| 1897 | */ |
| 1898 | bnx2x_schedule_sp_task(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1899 | |
| 1900 | status &= ~0x1; |
| 1901 | if (!status) |
| 1902 | return IRQ_HANDLED; |
| 1903 | } |
| 1904 | |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 1905 | if (unlikely(status)) |
| 1906 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 1907 | status); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1908 | |
| 1909 | return IRQ_HANDLED; |
| 1910 | } |
| 1911 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 1912 | /* Link */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1913 | |
| 1914 | /* |
| 1915 | * General service functions |
| 1916 | */ |
| 1917 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 1918 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1919 | { |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1920 | u32 lock_status; |
| 1921 | u32 resource_bit = (1 << resource); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1922 | int func = BP_FUNC(bp); |
| 1923 | u32 hw_lock_control_reg; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 1924 | int cnt; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1925 | |
| 1926 | /* Validating that the resource is within range */ |
| 1927 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1928 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1929 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
| 1930 | return -EINVAL; |
| 1931 | } |
| 1932 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1933 | if (func <= 5) { |
| 1934 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); |
| 1935 | } else { |
| 1936 | hw_lock_control_reg = |
| 1937 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); |
| 1938 | } |
| 1939 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1940 | /* Validating that the resource is not already taken */ |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1941 | lock_status = REG_RD(bp, hw_lock_control_reg); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1942 | if (lock_status & resource_bit) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1943 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1944 | lock_status, resource_bit); |
| 1945 | return -EEXIST; |
| 1946 | } |
| 1947 | |
Eilon Greenstein | 46230476b | 2008-08-25 15:23:30 -0700 | [diff] [blame] | 1948 | /* Try for 5 second every 5ms */ |
| 1949 | for (cnt = 0; cnt < 1000; cnt++) { |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1950 | /* Try to acquire the lock */ |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1951 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
| 1952 | lock_status = REG_RD(bp, hw_lock_control_reg); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1953 | if (lock_status & resource_bit) |
| 1954 | return 0; |
| 1955 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 1956 | usleep_range(5000, 10000); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1957 | } |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1958 | BNX2X_ERR("Timeout\n"); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1959 | return -EAGAIN; |
| 1960 | } |
| 1961 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 1962 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
| 1963 | { |
| 1964 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); |
| 1965 | } |
| 1966 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 1967 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1968 | { |
| 1969 | u32 lock_status; |
| 1970 | u32 resource_bit = (1 << resource); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1971 | int func = BP_FUNC(bp); |
| 1972 | u32 hw_lock_control_reg; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1973 | |
| 1974 | /* Validating that the resource is within range */ |
| 1975 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 1976 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1977 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
| 1978 | return -EINVAL; |
| 1979 | } |
| 1980 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1981 | if (func <= 5) { |
| 1982 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); |
| 1983 | } else { |
| 1984 | hw_lock_control_reg = |
| 1985 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); |
| 1986 | } |
| 1987 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1988 | /* Validating that the resource is currently taken */ |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1989 | lock_status = REG_RD(bp, hw_lock_control_reg); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1990 | if (!(lock_status & resource_bit)) { |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 1991 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
| 1992 | lock_status, resource_bit); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1993 | return -EFAULT; |
| 1994 | } |
| 1995 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 1996 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 1997 | return 0; |
| 1998 | } |
| 1999 | |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 2000 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
| 2001 | { |
| 2002 | /* The GPIO should be swapped if swap register is set and active */ |
| 2003 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && |
| 2004 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
| 2005 | int gpio_shift = gpio_num + |
| 2006 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); |
| 2007 | u32 gpio_mask = (1 << gpio_shift); |
| 2008 | u32 gpio_reg; |
| 2009 | int value; |
| 2010 | |
| 2011 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
| 2012 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); |
| 2013 | return -EINVAL; |
| 2014 | } |
| 2015 | |
| 2016 | /* read GPIO value */ |
| 2017 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); |
| 2018 | |
| 2019 | /* get the requested pin value */ |
| 2020 | if ((gpio_reg & gpio_mask) == gpio_mask) |
| 2021 | value = 1; |
| 2022 | else |
| 2023 | value = 0; |
| 2024 | |
| 2025 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); |
| 2026 | |
| 2027 | return value; |
| 2028 | } |
| 2029 | |
Eilon Greenstein | 17de50b | 2008-08-13 15:56:59 -0700 | [diff] [blame] | 2030 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2031 | { |
| 2032 | /* The GPIO should be swapped if swap register is set and active */ |
| 2033 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && |
Eilon Greenstein | 17de50b | 2008-08-13 15:56:59 -0700 | [diff] [blame] | 2034 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2035 | int gpio_shift = gpio_num + |
| 2036 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); |
| 2037 | u32 gpio_mask = (1 << gpio_shift); |
| 2038 | u32 gpio_reg; |
| 2039 | |
| 2040 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
| 2041 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); |
| 2042 | return -EINVAL; |
| 2043 | } |
| 2044 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2045 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2046 | /* read GPIO and mask except the float bits */ |
| 2047 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); |
| 2048 | |
| 2049 | switch (mode) { |
| 2050 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2051 | DP(NETIF_MSG_LINK, |
| 2052 | "Set GPIO %d (shift %d) -> output low\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2053 | gpio_num, gpio_shift); |
| 2054 | /* clear FLOAT and set CLR */ |
| 2055 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); |
| 2056 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); |
| 2057 | break; |
| 2058 | |
| 2059 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2060 | DP(NETIF_MSG_LINK, |
| 2061 | "Set GPIO %d (shift %d) -> output high\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2062 | gpio_num, gpio_shift); |
| 2063 | /* clear FLOAT and set SET */ |
| 2064 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); |
| 2065 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); |
| 2066 | break; |
| 2067 | |
Eilon Greenstein | 17de50b | 2008-08-13 15:56:59 -0700 | [diff] [blame] | 2068 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2069 | DP(NETIF_MSG_LINK, |
| 2070 | "Set GPIO %d (shift %d) -> input\n", |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2071 | gpio_num, gpio_shift); |
| 2072 | /* set FLOAT */ |
| 2073 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); |
| 2074 | break; |
| 2075 | |
| 2076 | default: |
| 2077 | break; |
| 2078 | } |
| 2079 | |
| 2080 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2081 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2082 | |
| 2083 | return 0; |
| 2084 | } |
| 2085 | |
Yaniv Rosner | 0d40f0d | 2011-06-14 01:34:27 +0000 | [diff] [blame] | 2086 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
| 2087 | { |
| 2088 | u32 gpio_reg = 0; |
| 2089 | int rc = 0; |
| 2090 | |
| 2091 | /* Any port swapping should be handled by caller. */ |
| 2092 | |
| 2093 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
| 2094 | /* read GPIO and mask except the float bits */ |
| 2095 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); |
| 2096 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); |
| 2097 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); |
| 2098 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); |
| 2099 | |
| 2100 | switch (mode) { |
| 2101 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: |
| 2102 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); |
| 2103 | /* set CLR */ |
| 2104 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); |
| 2105 | break; |
| 2106 | |
| 2107 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
| 2108 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); |
| 2109 | /* set SET */ |
| 2110 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); |
| 2111 | break; |
| 2112 | |
| 2113 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
| 2114 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); |
| 2115 | /* set FLOAT */ |
| 2116 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); |
| 2117 | break; |
| 2118 | |
| 2119 | default: |
| 2120 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); |
| 2121 | rc = -EINVAL; |
| 2122 | break; |
| 2123 | } |
| 2124 | |
| 2125 | if (rc == 0) |
| 2126 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
| 2127 | |
| 2128 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
| 2129 | |
| 2130 | return rc; |
| 2131 | } |
| 2132 | |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 2133 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
| 2134 | { |
| 2135 | /* The GPIO should be swapped if swap register is set and active */ |
| 2136 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && |
| 2137 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
| 2138 | int gpio_shift = gpio_num + |
| 2139 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); |
| 2140 | u32 gpio_mask = (1 << gpio_shift); |
| 2141 | u32 gpio_reg; |
| 2142 | |
| 2143 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
| 2144 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); |
| 2145 | return -EINVAL; |
| 2146 | } |
| 2147 | |
| 2148 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
| 2149 | /* read GPIO int */ |
| 2150 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); |
| 2151 | |
| 2152 | switch (mode) { |
| 2153 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2154 | DP(NETIF_MSG_LINK, |
| 2155 | "Clear GPIO INT %d (shift %d) -> output low\n", |
| 2156 | gpio_num, gpio_shift); |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 2157 | /* clear SET and set CLR */ |
| 2158 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); |
| 2159 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); |
| 2160 | break; |
| 2161 | |
| 2162 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2163 | DP(NETIF_MSG_LINK, |
| 2164 | "Set GPIO INT %d (shift %d) -> output high\n", |
| 2165 | gpio_num, gpio_shift); |
Eilon Greenstein | 4acac6a | 2009-02-12 08:36:52 +0000 | [diff] [blame] | 2166 | /* clear CLR and set SET */ |
| 2167 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); |
| 2168 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); |
| 2169 | break; |
| 2170 | |
| 2171 | default: |
| 2172 | break; |
| 2173 | } |
| 2174 | |
| 2175 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); |
| 2176 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
| 2177 | |
| 2178 | return 0; |
| 2179 | } |
| 2180 | |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2181 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2182 | { |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2183 | u32 spio_reg; |
| 2184 | |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2185 | /* Only 2 SPIOs are configurable */ |
| 2186 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { |
| 2187 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2188 | return -EINVAL; |
| 2189 | } |
| 2190 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2192 | /* read SPIO and mask except the float bits */ |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2193 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2194 | |
| 2195 | switch (mode) { |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2196 | case MISC_SPIO_OUTPUT_LOW: |
| 2197 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2198 | /* clear FLOAT and set CLR */ |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2199 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
| 2200 | spio_reg |= (spio << MISC_SPIO_CLR_POS); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2201 | break; |
| 2202 | |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2203 | case MISC_SPIO_OUTPUT_HIGH: |
| 2204 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2205 | /* clear FLOAT and set SET */ |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2206 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
| 2207 | spio_reg |= (spio << MISC_SPIO_SET_POS); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2208 | break; |
| 2209 | |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2210 | case MISC_SPIO_INPUT_HI_Z: |
| 2211 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2212 | /* set FLOAT */ |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 2213 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2214 | break; |
| 2215 | |
| 2216 | default: |
| 2217 | break; |
| 2218 | } |
| 2219 | |
| 2220 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2221 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2222 | |
| 2223 | return 0; |
| 2224 | } |
| 2225 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 2226 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2227 | { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2228 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
Eilon Greenstein | ad33ea3 | 2009-01-14 21:24:57 -0800 | [diff] [blame] | 2229 | switch (bp->link_vars.ieee_fc & |
| 2230 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2231 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2232 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 2233 | ADVERTISED_Pause); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2234 | break; |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 2235 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2236 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2237 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 2238 | ADVERTISED_Pause); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2239 | break; |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 2240 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2241 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2242 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2243 | break; |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 2244 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2245 | default: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2246 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 2247 | ADVERTISED_Pause); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 2248 | break; |
| 2249 | } |
| 2250 | } |
| 2251 | |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 2252 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2253 | { |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 2254 | /* Initialize link parameters structure variables |
| 2255 | * It is recommended to turn off RX FC for jumbo frames |
| 2256 | * for better performance |
| 2257 | */ |
| 2258 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) |
| 2259 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; |
| 2260 | else |
| 2261 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; |
| 2262 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2263 | |
Dmitry Kravkov | 9156b30 | 2013-08-19 09:11:56 +0300 | [diff] [blame] | 2264 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
| 2265 | { |
| 2266 | u32 pause_enabled = 0; |
| 2267 | |
| 2268 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { |
| 2269 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) |
| 2270 | pause_enabled = 1; |
| 2271 | |
| 2272 | REG_WR(bp, BAR_USTRORM_INTMEM + |
| 2273 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), |
| 2274 | pause_enabled); |
| 2275 | } |
| 2276 | |
| 2277 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", |
| 2278 | pause_enabled ? "enabled" : "disabled"); |
| 2279 | } |
| 2280 | |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 2281 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
| 2282 | { |
| 2283 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); |
| 2284 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; |
| 2285 | |
| 2286 | if (!BP_NOMCP(bp)) { |
| 2287 | bnx2x_set_requested_fc(bp); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2288 | bnx2x_acquire_phy_lock(bp); |
Eilon Greenstein | b5bf906 | 2009-02-12 08:38:08 +0000 | [diff] [blame] | 2289 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2290 | if (load_mode == LOAD_DIAG) { |
Yaniv Rosner | 1cb0c78 | 2011-07-24 03:53:21 +0000 | [diff] [blame] | 2291 | struct link_params *lp = &bp->link_params; |
| 2292 | lp->loopback_mode = LOOPBACK_XGXS; |
| 2293 | /* do PHY loopback at 10G speed, if possible */ |
| 2294 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { |
| 2295 | if (lp->speed_cap_mask[cfx_idx] & |
| 2296 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
| 2297 | lp->req_line_speed[cfx_idx] = |
| 2298 | SPEED_10000; |
| 2299 | else |
| 2300 | lp->req_line_speed[cfx_idx] = |
| 2301 | SPEED_1000; |
| 2302 | } |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2303 | } |
Eilon Greenstein | b5bf906 | 2009-02-12 08:38:08 +0000 | [diff] [blame] | 2304 | |
Merav Sicron | 8970b2e | 2012-06-19 07:48:22 +0000 | [diff] [blame] | 2305 | if (load_mode == LOAD_LOOPBACK_EXT) { |
| 2306 | struct link_params *lp = &bp->link_params; |
| 2307 | lp->loopback_mode = LOOPBACK_EXT; |
| 2308 | } |
| 2309 | |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2310 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
Eilon Greenstein | b5bf906 | 2009-02-12 08:38:08 +0000 | [diff] [blame] | 2311 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2312 | bnx2x_release_phy_lock(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2313 | |
Dmitry Kravkov | 9156b30 | 2013-08-19 09:11:56 +0300 | [diff] [blame] | 2314 | bnx2x_init_dropless_fc(bp); |
| 2315 | |
Eilon Greenstein | 3c96c68 | 2009-01-14 21:25:31 -0800 | [diff] [blame] | 2316 | bnx2x_calc_fc_adv(bp); |
| 2317 | |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 2318 | if (bp->link_vars.link_up) { |
Eilon Greenstein | b5bf906 | 2009-02-12 08:38:08 +0000 | [diff] [blame] | 2319 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2320 | bnx2x_link_report(bp); |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 2321 | } |
| 2322 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2323 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2324 | return rc; |
| 2325 | } |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 2326 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2327 | return -EINVAL; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2328 | } |
| 2329 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 2330 | void bnx2x_link_set(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2331 | { |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2332 | if (!BP_NOMCP(bp)) { |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2333 | bnx2x_acquire_phy_lock(bp); |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2334 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2335 | bnx2x_release_phy_lock(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2336 | |
Dmitry Kravkov | 9156b30 | 2013-08-19 09:11:56 +0300 | [diff] [blame] | 2337 | bnx2x_init_dropless_fc(bp); |
| 2338 | |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2339 | bnx2x_calc_fc_adv(bp); |
| 2340 | } else |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 2341 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2342 | } |
| 2343 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2344 | static void bnx2x__link_reset(struct bnx2x *bp) |
| 2345 | { |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2346 | if (!BP_NOMCP(bp)) { |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2347 | bnx2x_acquire_phy_lock(bp); |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 2348 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 2349 | bnx2x_release_phy_lock(bp); |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 2350 | } else |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 2351 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2352 | } |
| 2353 | |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 2354 | void bnx2x_force_link_reset(struct bnx2x *bp) |
| 2355 | { |
| 2356 | bnx2x_acquire_phy_lock(bp); |
| 2357 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); |
| 2358 | bnx2x_release_phy_lock(bp); |
| 2359 | } |
| 2360 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2361 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2362 | { |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 2363 | u8 rc = 0; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2364 | |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 2365 | if (!BP_NOMCP(bp)) { |
| 2366 | bnx2x_acquire_phy_lock(bp); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2367 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
| 2368 | is_serdes); |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 2369 | bnx2x_release_phy_lock(bp); |
| 2370 | } else |
| 2371 | BNX2X_ERR("Bootcode is missing - can not test link\n"); |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2372 | |
| 2373 | return rc; |
| 2374 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2375 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2376 | /* Calculates the sum of vn_min_rates. |
| 2377 | It's needed for further normalizing of the min_rates. |
| 2378 | Returns: |
| 2379 | sum of vn_min_rates. |
| 2380 | or |
| 2381 | 0 - if all the min_rates are 0. |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 2382 | In the later case fairness algorithm should be deactivated. |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2383 | If not all min_rates are zero then those that are zeroes will be set to 1. |
| 2384 | */ |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2385 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
| 2386 | struct cmng_init_input *input) |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2387 | { |
| 2388 | int all_zero = 1; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2389 | int vn; |
| 2390 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 2391 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2392 | u32 vn_cfg = bp->mf_config[vn]; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2393 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
| 2394 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; |
| 2395 | |
| 2396 | /* Skip hidden vns */ |
| 2397 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2398 | vn_min_rate = 0; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2399 | /* If min rate is zero - set it to 1 */ |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2400 | else if (!vn_min_rate) |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2401 | vn_min_rate = DEF_MIN_RATE; |
| 2402 | else |
| 2403 | all_zero = 0; |
| 2404 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2405 | input->vnic_min_rate[vn] = vn_min_rate; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2406 | } |
| 2407 | |
Dmitry Kravkov | 30ae438b | 2011-06-14 01:33:13 +0000 | [diff] [blame] | 2408 | /* if ETS or all min rates are zeros - disable fairness */ |
| 2409 | if (BNX2X_IS_ETS_ENABLED(bp)) { |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2410 | input->flags.cmng_enables &= |
Dmitry Kravkov | 30ae438b | 2011-06-14 01:33:13 +0000 | [diff] [blame] | 2411 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
| 2412 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); |
| 2413 | } else if (all_zero) { |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2414 | input->flags.cmng_enables &= |
Eilon Greenstein | b015e3d | 2009-10-15 00:17:20 -0700 | [diff] [blame] | 2415 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2416 | DP(NETIF_MSG_IFUP, |
| 2417 | "All MIN values are zeroes fairness will be disabled\n"); |
Eilon Greenstein | b015e3d | 2009-10-15 00:17:20 -0700 | [diff] [blame] | 2418 | } else |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2419 | input->flags.cmng_enables |= |
Eilon Greenstein | b015e3d | 2009-10-15 00:17:20 -0700 | [diff] [blame] | 2420 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2421 | } |
| 2422 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2423 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
| 2424 | struct cmng_init_input *input) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2425 | { |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2426 | u16 vn_max_rate; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2427 | u32 vn_cfg = bp->mf_config[vn]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2428 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2429 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2430 | vn_max_rate = 0; |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2431 | else { |
Dmitry Kravkov | faa6fcb | 2011-02-28 03:37:20 +0000 | [diff] [blame] | 2432 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
| 2433 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2434 | if (IS_MF_SI(bp)) { |
Dmitry Kravkov | faa6fcb | 2011-02-28 03:37:20 +0000 | [diff] [blame] | 2435 | /* maxCfg in percents of linkspeed */ |
| 2436 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2437 | } else /* SD modes */ |
Dmitry Kravkov | faa6fcb | 2011-02-28 03:37:20 +0000 | [diff] [blame] | 2438 | /* maxCfg is absolute in 100Mb units */ |
| 2439 | vn_max_rate = maxCfg * 100; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2440 | } |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 2441 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2442 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2443 | |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2444 | input->vnic_max_rate[vn] = vn_max_rate; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2445 | } |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 2446 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2447 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
| 2448 | { |
| 2449 | if (CHIP_REV_IS_SLOW(bp)) |
| 2450 | return CMNG_FNS_NONE; |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 2451 | if (IS_MF(bp)) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2452 | return CMNG_FNS_MINMAX; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2453 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2454 | return CMNG_FNS_NONE; |
| 2455 | } |
| 2456 | |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 2457 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2458 | { |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 2459 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2460 | |
| 2461 | if (BP_NOMCP(bp)) |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 2462 | return; /* what should be the default value in this case */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2463 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 2464 | /* For 2 port configuration the absolute function number formula |
| 2465 | * is: |
| 2466 | * abs_func = 2 * vn + BP_PORT + BP_PATH |
| 2467 | * |
| 2468 | * and there are 4 functions per port |
| 2469 | * |
| 2470 | * For 4 port configuration it is |
| 2471 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH |
| 2472 | * |
| 2473 | * and there are 2 functions per port |
| 2474 | */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 2475 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 2476 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
| 2477 | |
| 2478 | if (func >= E1H_FUNC_MAX) |
| 2479 | break; |
| 2480 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2481 | bp->mf_config[vn] = |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2482 | MF_CFG_RD(bp, func_mf_config[func].config); |
| 2483 | } |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 2484 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
| 2485 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); |
| 2486 | bp->flags |= MF_FUNC_DIS; |
| 2487 | } else { |
| 2488 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); |
| 2489 | bp->flags &= ~MF_FUNC_DIS; |
| 2490 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2491 | } |
| 2492 | |
| 2493 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) |
| 2494 | { |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2495 | struct cmng_init_input input; |
| 2496 | memset(&input, 0, sizeof(struct cmng_init_input)); |
| 2497 | |
| 2498 | input.port_rate = bp->link_vars.line_speed; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2499 | |
Dmitry Kravkov | 568e242 | 2013-08-13 02:25:00 +0300 | [diff] [blame] | 2500 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2501 | int vn; |
| 2502 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2503 | /* read mf conf from shmem */ |
| 2504 | if (read_cfg) |
| 2505 | bnx2x_read_mf_cfg(bp); |
| 2506 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2507 | /* vn_weight_sum and enable fairness if not 0 */ |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2508 | bnx2x_calc_vn_min(bp, &input); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2509 | |
| 2510 | /* calculate and set min-max rate for each vn */ |
Dmitry Kravkov | c4154f2 | 2011-03-06 10:49:25 +0000 | [diff] [blame] | 2511 | if (bp->port.pmf) |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 2512 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2513 | bnx2x_calc_vn_max(bp, vn, &input); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2514 | |
| 2515 | /* always enable rate shaping and fairness */ |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2516 | input.flags.cmng_enables |= |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2517 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
Yuval Mintz | b475d78 | 2012-04-03 18:41:29 +0000 | [diff] [blame] | 2518 | |
| 2519 | bnx2x_init_cmng(&input, &bp->cmng); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2520 | return; |
| 2521 | } |
| 2522 | |
| 2523 | /* rate shaping and fairness are disabled */ |
| 2524 | DP(NETIF_MSG_IFUP, |
| 2525 | "rate shaping and fairness are disabled\n"); |
| 2526 | } |
| 2527 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 2528 | static void storm_memset_cmng(struct bnx2x *bp, |
| 2529 | struct cmng_init *cmng, |
| 2530 | u8 port) |
| 2531 | { |
| 2532 | int vn; |
| 2533 | size_t size = sizeof(struct cmng_struct_per_port); |
| 2534 | |
| 2535 | u32 addr = BAR_XSTRORM_INTMEM + |
| 2536 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); |
| 2537 | |
| 2538 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); |
| 2539 | |
| 2540 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
| 2541 | int func = func_by_vn(bp, vn); |
| 2542 | |
| 2543 | addr = BAR_XSTRORM_INTMEM + |
| 2544 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); |
| 2545 | size = sizeof(struct rate_shaping_vars_per_vn); |
| 2546 | __storm_memset_struct(bp, addr, size, |
| 2547 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); |
| 2548 | |
| 2549 | addr = BAR_XSTRORM_INTMEM + |
| 2550 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); |
| 2551 | size = sizeof(struct fairness_vars_per_vn); |
| 2552 | __storm_memset_struct(bp, addr, size, |
| 2553 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); |
| 2554 | } |
| 2555 | } |
| 2556 | |
Dmitry Kravkov | 568e242 | 2013-08-13 02:25:00 +0300 | [diff] [blame] | 2557 | /* init cmng mode in HW according to local configuration */ |
| 2558 | void bnx2x_set_local_cmng(struct bnx2x *bp) |
| 2559 | { |
| 2560 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); |
| 2561 | |
| 2562 | if (cmng_fns != CMNG_FNS_NONE) { |
| 2563 | bnx2x_cmng_fns_init(bp, false, cmng_fns); |
| 2564 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); |
| 2565 | } else { |
| 2566 | /* rate shaping and fairness are disabled */ |
| 2567 | DP(NETIF_MSG_IFUP, |
| 2568 | "single function mode without fairness\n"); |
| 2569 | } |
| 2570 | } |
| 2571 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2572 | /* This function is called upon link interrupt */ |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2573 | static void bnx2x_link_attn(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2574 | { |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2575 | /* Make sure that we are synced with the current statistics */ |
| 2576 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); |
| 2577 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2578 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2579 | |
Dmitry Kravkov | 9156b30 | 2013-08-19 09:11:56 +0300 | [diff] [blame] | 2580 | bnx2x_init_dropless_fc(bp); |
| 2581 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2582 | if (bp->link_vars.link_up) { |
| 2583 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2584 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2585 | struct host_port_stats *pstats; |
| 2586 | |
| 2587 | pstats = bnx2x_sp(bp, port_stats); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2588 | /* reset old mac stats */ |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2589 | memset(&(pstats->mac_stx[0]), 0, |
| 2590 | sizeof(struct mac_stx)); |
| 2591 | } |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 2592 | if (bp->state == BNX2X_STATE_OPEN) |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2593 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
| 2594 | } |
| 2595 | |
Dmitry Kravkov | 568e242 | 2013-08-13 02:25:00 +0300 | [diff] [blame] | 2596 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
| 2597 | bnx2x_set_local_cmng(bp); |
Dmitry Kravkov | 9fdc3e9 | 2011-03-06 10:49:15 +0000 | [diff] [blame] | 2598 | |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 2599 | __bnx2x_link_report(bp); |
| 2600 | |
Dmitry Kravkov | 9fdc3e9 | 2011-03-06 10:49:15 +0000 | [diff] [blame] | 2601 | if (IS_MF(bp)) |
| 2602 | bnx2x_link_sync_notify(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2603 | } |
| 2604 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 2605 | void bnx2x__link_status_update(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2606 | { |
Vladislav Zolotarov | 2ae17f6 | 2011-05-04 23:48:23 +0000 | [diff] [blame] | 2607 | if (bp->state != BNX2X_STATE_OPEN) |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2608 | return; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2609 | |
Dmitry Kravkov | 00253a8 | 2011-11-13 04:34:25 +0000 | [diff] [blame] | 2610 | /* read updated dcb configuration */ |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 2611 | if (IS_PF(bp)) { |
| 2612 | bnx2x_dcbx_pmf_update(bp); |
| 2613 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); |
| 2614 | if (bp->link_vars.link_up) |
| 2615 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
| 2616 | else |
| 2617 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); |
| 2618 | /* indicate link status */ |
| 2619 | bnx2x_link_report(bp); |
Dmitry Kravkov | 00253a8 | 2011-11-13 04:34:25 +0000 | [diff] [blame] | 2620 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 2621 | } else { /* VF */ |
| 2622 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | |
| 2623 | SUPPORTED_10baseT_Full | |
| 2624 | SUPPORTED_100baseT_Half | |
| 2625 | SUPPORTED_100baseT_Full | |
| 2626 | SUPPORTED_1000baseT_Full | |
| 2627 | SUPPORTED_2500baseX_Full | |
| 2628 | SUPPORTED_10000baseT_Full | |
| 2629 | SUPPORTED_TP | |
| 2630 | SUPPORTED_FIBRE | |
| 2631 | SUPPORTED_Autoneg | |
| 2632 | SUPPORTED_Pause | |
| 2633 | SUPPORTED_Asym_Pause); |
| 2634 | bp->port.advertising[0] = bp->port.supported[0]; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2635 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 2636 | bp->link_params.bp = bp; |
| 2637 | bp->link_params.port = BP_PORT(bp); |
| 2638 | bp->link_params.req_duplex[0] = DUPLEX_FULL; |
| 2639 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; |
| 2640 | bp->link_params.req_line_speed[0] = SPEED_10000; |
| 2641 | bp->link_params.speed_cap_mask[0] = 0x7f0000; |
| 2642 | bp->link_params.switch_cfg = SWITCH_CFG_10G; |
| 2643 | bp->link_vars.mac_type = MAC_TYPE_BMAC; |
| 2644 | bp->link_vars.line_speed = SPEED_10000; |
| 2645 | bp->link_vars.link_status = |
| 2646 | (LINK_STATUS_LINK_UP | |
| 2647 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); |
| 2648 | bp->link_vars.link_up = 1; |
| 2649 | bp->link_vars.duplex = DUPLEX_FULL; |
| 2650 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
| 2651 | __bnx2x_link_report(bp); |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2652 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 2653 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2654 | } |
| 2655 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 2656 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
| 2657 | u16 vlan_val, u8 allowed_prio) |
| 2658 | { |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 2659 | struct bnx2x_func_state_params func_params = {NULL}; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 2660 | struct bnx2x_func_afex_update_params *f_update_params = |
| 2661 | &func_params.params.afex_update; |
| 2662 | |
| 2663 | func_params.f_obj = &bp->func_obj; |
| 2664 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; |
| 2665 | |
| 2666 | /* no need to wait for RAMROD completion, so don't |
| 2667 | * set RAMROD_COMP_WAIT flag |
| 2668 | */ |
| 2669 | |
| 2670 | f_update_params->vif_id = vifid; |
| 2671 | f_update_params->afex_default_vlan = vlan_val; |
| 2672 | f_update_params->allowed_priorities = allowed_prio; |
| 2673 | |
| 2674 | /* if ramrod can not be sent, response to MCP immediately */ |
| 2675 | if (bnx2x_func_state_change(bp, &func_params) < 0) |
| 2676 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); |
| 2677 | |
| 2678 | return 0; |
| 2679 | } |
| 2680 | |
| 2681 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, |
| 2682 | u16 vif_index, u8 func_bit_map) |
| 2683 | { |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 2684 | struct bnx2x_func_state_params func_params = {NULL}; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 2685 | struct bnx2x_func_afex_viflists_params *update_params = |
| 2686 | &func_params.params.afex_viflists; |
| 2687 | int rc; |
| 2688 | u32 drv_msg_code; |
| 2689 | |
| 2690 | /* validate only LIST_SET and LIST_GET are received from switch */ |
| 2691 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) |
| 2692 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", |
| 2693 | cmd_type); |
| 2694 | |
| 2695 | func_params.f_obj = &bp->func_obj; |
| 2696 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; |
| 2697 | |
| 2698 | /* set parameters according to cmd_type */ |
| 2699 | update_params->afex_vif_list_command = cmd_type; |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 2700 | update_params->vif_list_index = vif_index; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 2701 | update_params->func_bit_map = |
| 2702 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; |
| 2703 | update_params->func_to_clear = 0; |
| 2704 | drv_msg_code = |
| 2705 | (cmd_type == VIF_LIST_RULE_GET) ? |
| 2706 | DRV_MSG_CODE_AFEX_LISTGET_ACK : |
| 2707 | DRV_MSG_CODE_AFEX_LISTSET_ACK; |
| 2708 | |
| 2709 | /* if ramrod can not be sent, respond to MCP immediately for |
| 2710 | * SET and GET requests (other are not triggered from MCP) |
| 2711 | */ |
| 2712 | rc = bnx2x_func_state_change(bp, &func_params); |
| 2713 | if (rc < 0) |
| 2714 | bnx2x_fw_command(bp, drv_msg_code, 0); |
| 2715 | |
| 2716 | return 0; |
| 2717 | } |
| 2718 | |
| 2719 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) |
| 2720 | { |
| 2721 | struct afex_stats afex_stats; |
| 2722 | u32 func = BP_ABS_FUNC(bp); |
| 2723 | u32 mf_config; |
| 2724 | u16 vlan_val; |
| 2725 | u32 vlan_prio; |
| 2726 | u16 vif_id; |
| 2727 | u8 allowed_prio; |
| 2728 | u8 vlan_mode; |
| 2729 | u32 addr_to_write, vifid, addrs, stats_type, i; |
| 2730 | |
| 2731 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { |
| 2732 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); |
| 2733 | DP(BNX2X_MSG_MCP, |
| 2734 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); |
| 2735 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); |
| 2736 | } |
| 2737 | |
| 2738 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { |
| 2739 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); |
| 2740 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); |
| 2741 | DP(BNX2X_MSG_MCP, |
| 2742 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", |
| 2743 | vifid, addrs); |
| 2744 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, |
| 2745 | addrs); |
| 2746 | } |
| 2747 | |
| 2748 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { |
| 2749 | addr_to_write = SHMEM2_RD(bp, |
| 2750 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); |
| 2751 | stats_type = SHMEM2_RD(bp, |
| 2752 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); |
| 2753 | |
| 2754 | DP(BNX2X_MSG_MCP, |
| 2755 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", |
| 2756 | addr_to_write); |
| 2757 | |
| 2758 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); |
| 2759 | |
| 2760 | /* write response to scratchpad, for MCP */ |
| 2761 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) |
| 2762 | REG_WR(bp, addr_to_write + i*sizeof(u32), |
| 2763 | *(((u32 *)(&afex_stats))+i)); |
| 2764 | |
| 2765 | /* send ack message to MCP */ |
| 2766 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); |
| 2767 | } |
| 2768 | |
| 2769 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { |
| 2770 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); |
| 2771 | bp->mf_config[BP_VN(bp)] = mf_config; |
| 2772 | DP(BNX2X_MSG_MCP, |
| 2773 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", |
| 2774 | mf_config); |
| 2775 | |
| 2776 | /* if VIF_SET is "enabled" */ |
| 2777 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { |
| 2778 | /* set rate limit directly to internal RAM */ |
| 2779 | struct cmng_init_input cmng_input; |
| 2780 | struct rate_shaping_vars_per_vn m_rs_vn; |
| 2781 | size_t size = sizeof(struct rate_shaping_vars_per_vn); |
| 2782 | u32 addr = BAR_XSTRORM_INTMEM + |
| 2783 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); |
| 2784 | |
| 2785 | bp->mf_config[BP_VN(bp)] = mf_config; |
| 2786 | |
| 2787 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); |
| 2788 | m_rs_vn.vn_counter.rate = |
| 2789 | cmng_input.vnic_max_rate[BP_VN(bp)]; |
| 2790 | m_rs_vn.vn_counter.quota = |
| 2791 | (m_rs_vn.vn_counter.rate * |
| 2792 | RS_PERIODIC_TIMEOUT_USEC) / 8; |
| 2793 | |
| 2794 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); |
| 2795 | |
| 2796 | /* read relevant values from mf_cfg struct in shmem */ |
| 2797 | vif_id = |
| 2798 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & |
| 2799 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> |
| 2800 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; |
| 2801 | vlan_val = |
| 2802 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & |
| 2803 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> |
| 2804 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; |
| 2805 | vlan_prio = (mf_config & |
| 2806 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> |
| 2807 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; |
| 2808 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); |
| 2809 | vlan_mode = |
| 2810 | (MF_CFG_RD(bp, |
| 2811 | func_mf_config[func].afex_config) & |
| 2812 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> |
| 2813 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; |
| 2814 | allowed_prio = |
| 2815 | (MF_CFG_RD(bp, |
| 2816 | func_mf_config[func].afex_config) & |
| 2817 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> |
| 2818 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; |
| 2819 | |
| 2820 | /* send ramrod to FW, return in case of failure */ |
| 2821 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, |
| 2822 | allowed_prio)) |
| 2823 | return; |
| 2824 | |
| 2825 | bp->afex_def_vlan_tag = vlan_val; |
| 2826 | bp->afex_vlan_mode = vlan_mode; |
| 2827 | } else { |
| 2828 | /* notify link down because BP->flags is disabled */ |
| 2829 | bnx2x_link_report(bp); |
| 2830 | |
| 2831 | /* send INVALID VIF ramrod to FW */ |
| 2832 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); |
| 2833 | |
| 2834 | /* Reset the default afex VLAN */ |
| 2835 | bp->afex_def_vlan_tag = -1; |
| 2836 | } |
| 2837 | } |
| 2838 | } |
| 2839 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2840 | static void bnx2x_pmf_update(struct bnx2x *bp) |
| 2841 | { |
| 2842 | int port = BP_PORT(bp); |
| 2843 | u32 val; |
| 2844 | |
| 2845 | bp->port.pmf = 1; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 2846 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2847 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 2848 | /* |
| 2849 | * We need the mb() to ensure the ordering between the writing to |
| 2850 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). |
| 2851 | */ |
| 2852 | smp_mb(); |
| 2853 | |
| 2854 | /* queue a periodic task */ |
| 2855 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); |
| 2856 | |
Dmitry Kravkov | ef01854 | 2011-06-14 01:33:57 +0000 | [diff] [blame] | 2857 | bnx2x_dcbx_pmf_update(bp); |
| 2858 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2859 | /* enable nig attention */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 2860 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2861 | if (bp->common.int_block == INT_BLOCK_HC) { |
| 2862 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); |
| 2863 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2864 | } else if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2865 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
| 2866 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); |
| 2867 | } |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 2868 | |
| 2869 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 2870 | } |
| 2871 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 2872 | /* end of Link */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 2873 | |
| 2874 | /* slow path */ |
| 2875 | |
| 2876 | /* |
| 2877 | * General service functions |
| 2878 | */ |
| 2879 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2880 | /* send the MCP a request, block until there is a reply */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 2881 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2882 | { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2883 | int mb_idx = BP_FW_MB_IDX(bp); |
Dmitry Kravkov | a5971d4 | 2011-05-25 04:55:51 +0000 | [diff] [blame] | 2884 | u32 seq; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2885 | u32 rc = 0; |
| 2886 | u32 cnt = 1; |
| 2887 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; |
| 2888 | |
Eilon Greenstein | c4ff7cb | 2009-10-15 00:18:27 -0700 | [diff] [blame] | 2889 | mutex_lock(&bp->fw_mb_mutex); |
Dmitry Kravkov | a5971d4 | 2011-05-25 04:55:51 +0000 | [diff] [blame] | 2890 | seq = ++bp->fw_seq; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2891 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
| 2892 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); |
| 2893 | |
Dmitry Kravkov | 754a2f5 | 2011-06-14 01:34:02 +0000 | [diff] [blame] | 2894 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
| 2895 | (command | seq), param); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2896 | |
| 2897 | do { |
| 2898 | /* let the FW do it's magic ... */ |
| 2899 | msleep(delay); |
| 2900 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 2901 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2902 | |
Eilon Greenstein | c4ff7cb | 2009-10-15 00:18:27 -0700 | [diff] [blame] | 2903 | /* Give the FW up to 5 second (500*10ms) */ |
| 2904 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2905 | |
| 2906 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", |
| 2907 | cnt*delay, rc, seq); |
| 2908 | |
| 2909 | /* is this a reply to our command? */ |
| 2910 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) |
| 2911 | rc &= FW_MSG_CODE_MASK; |
| 2912 | else { |
| 2913 | /* FW BUG! */ |
| 2914 | BNX2X_ERR("FW failed to respond!\n"); |
| 2915 | bnx2x_fw_dump(bp); |
| 2916 | rc = 0; |
| 2917 | } |
Eilon Greenstein | c4ff7cb | 2009-10-15 00:18:27 -0700 | [diff] [blame] | 2918 | mutex_unlock(&bp->fw_mb_mutex); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 2919 | |
| 2920 | return rc; |
| 2921 | } |
| 2922 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 2923 | static void storm_memset_func_cfg(struct bnx2x *bp, |
| 2924 | struct tstorm_eth_function_common_config *tcfg, |
| 2925 | u16 abs_fid) |
| 2926 | { |
| 2927 | size_t size = sizeof(struct tstorm_eth_function_common_config); |
| 2928 | |
| 2929 | u32 addr = BAR_TSTRORM_INTMEM + |
| 2930 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); |
| 2931 | |
| 2932 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); |
| 2933 | } |
| 2934 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2935 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2936 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2937 | if (CHIP_IS_E1x(bp)) { |
| 2938 | struct tstorm_eth_function_common_config tcfg = {0}; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2939 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2940 | storm_memset_func_cfg(bp, &tcfg, p->func_id); |
| 2941 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 2942 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2943 | /* Enable the function in the FW */ |
| 2944 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); |
| 2945 | storm_memset_func_en(bp, p->func_id, 1); |
| 2946 | |
| 2947 | /* spq */ |
| 2948 | if (p->func_flgs & FUNC_FLG_SPQ) { |
| 2949 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); |
| 2950 | REG_WR(bp, XSEM_REG_FAST_MEMORY + |
| 2951 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); |
| 2952 | } |
| 2953 | } |
| 2954 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2955 | /** |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 2956 | * bnx2x_get_common_flags - Return common flags |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2957 | * |
| 2958 | * @bp device handle |
| 2959 | * @fp queue handle |
| 2960 | * @zero_stats TRUE if statistics zeroing is needed |
| 2961 | * |
| 2962 | * Return the flags that are common for the Tx-only and not normal connections. |
| 2963 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 2964 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
| 2965 | struct bnx2x_fastpath *fp, |
| 2966 | bool zero_stats) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2967 | { |
| 2968 | unsigned long flags = 0; |
| 2969 | |
| 2970 | /* PF driver will always initialize the Queue to an ACTIVE state */ |
| 2971 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); |
| 2972 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2973 | /* tx only connections collect statistics (on the same index as the |
Dmitry Kravkov | 9122679 | 2013-03-11 05:17:52 +0000 | [diff] [blame] | 2974 | * parent connection). The statistics are zeroed when the parent |
| 2975 | * connection is initialized. |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2976 | */ |
Barak Witkowski | 50f0a56 | 2011-12-05 21:52:23 +0000 | [diff] [blame] | 2977 | |
| 2978 | __set_bit(BNX2X_Q_FLG_STATS, &flags); |
| 2979 | if (zero_stats) |
| 2980 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); |
| 2981 | |
Dmitry Kravkov | 9122679 | 2013-03-11 05:17:52 +0000 | [diff] [blame] | 2982 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
Dmitry Kravkov | e287a75 | 2013-03-21 15:38:24 +0000 | [diff] [blame] | 2983 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2984 | |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 2985 | #ifdef BNX2X_STOP_ON_ERROR |
| 2986 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); |
| 2987 | #endif |
| 2988 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2989 | return flags; |
| 2990 | } |
| 2991 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 2992 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
| 2993 | struct bnx2x_fastpath *fp, |
| 2994 | bool leading) |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 2995 | { |
| 2996 | unsigned long flags = 0; |
| 2997 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 2998 | /* calculate other queue flags */ |
| 2999 | if (IS_MF_SD(bp)) |
| 3000 | __set_bit(BNX2X_Q_FLG_OV, &flags); |
| 3001 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 3002 | if (IS_FCOE_FP(fp)) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3003 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 3004 | /* For FCoE - force usage of default priority (for afex) */ |
| 3005 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); |
| 3006 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3007 | |
Vladislav Zolotarov | f5219d8 | 2011-07-19 01:44:11 +0000 | [diff] [blame] | 3008 | if (!fp->disable_tpa) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3009 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
Vladislav Zolotarov | f5219d8 | 2011-07-19 01:44:11 +0000 | [diff] [blame] | 3010 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
Dmitry Kravkov | 621b4d6 | 2012-02-20 09:59:08 +0000 | [diff] [blame] | 3011 | if (fp->mode == TPA_MODE_GRO) |
| 3012 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); |
Vladislav Zolotarov | f5219d8 | 2011-07-19 01:44:11 +0000 | [diff] [blame] | 3013 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3014 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3015 | if (leading) { |
| 3016 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); |
| 3017 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); |
| 3018 | } |
| 3019 | |
| 3020 | /* Always set HW VLAN stripping */ |
| 3021 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3022 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 3023 | /* configure silent vlan removal */ |
| 3024 | if (IS_MF_AFEX(bp)) |
| 3025 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); |
| 3026 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3027 | return flags | bnx2x_get_common_flags(bp, fp, true); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3028 | } |
| 3029 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3030 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3031 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
| 3032 | u8 cos) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3033 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3034 | gen_init->stat_id = bnx2x_stats_id(fp); |
| 3035 | gen_init->spcl_id = fp->cl_id; |
| 3036 | |
| 3037 | /* Always use mini-jumbo MTU for FCoE L2 ring */ |
| 3038 | if (IS_FCOE_FP(fp)) |
| 3039 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; |
| 3040 | else |
| 3041 | gen_init->mtu = bp->dev->mtu; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3042 | |
| 3043 | gen_init->cos = cos; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3044 | } |
| 3045 | |
| 3046 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, |
| 3047 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
| 3048 | struct bnx2x_rxq_setup_params *rxq_init) |
| 3049 | { |
| 3050 | u8 max_sge = 0; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3051 | u16 sge_sz = 0; |
| 3052 | u16 tpa_agg_size = 0; |
| 3053 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3054 | if (!fp->disable_tpa) { |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 3055 | pause->sge_th_lo = SGE_TH_LO(bp); |
| 3056 | pause->sge_th_hi = SGE_TH_HI(bp); |
| 3057 | |
| 3058 | /* validate SGE ring has enough to cross high threshold */ |
| 3059 | WARN_ON(bp->dropless_fc && |
| 3060 | pause->sge_th_hi + FW_PREFETCH_CNT > |
| 3061 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); |
| 3062 | |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 3063 | tpa_agg_size = TPA_AGG_SIZE; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3064 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
| 3065 | SGE_PAGE_SHIFT; |
| 3066 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & |
| 3067 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 3068 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3069 | } |
| 3070 | |
| 3071 | /* pause - not for e1 */ |
| 3072 | if (!CHIP_IS_E1(bp)) { |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 3073 | pause->bd_th_lo = BD_TH_LO(bp); |
| 3074 | pause->bd_th_hi = BD_TH_HI(bp); |
| 3075 | |
| 3076 | pause->rcq_th_lo = RCQ_TH_LO(bp); |
| 3077 | pause->rcq_th_hi = RCQ_TH_HI(bp); |
| 3078 | /* |
| 3079 | * validate that rings have enough entries to cross |
| 3080 | * high thresholds |
| 3081 | */ |
| 3082 | WARN_ON(bp->dropless_fc && |
| 3083 | pause->bd_th_hi + FW_PREFETCH_CNT > |
| 3084 | bp->rx_ring_size); |
| 3085 | WARN_ON(bp->dropless_fc && |
| 3086 | pause->rcq_th_hi + FW_PREFETCH_CNT > |
| 3087 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3088 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3089 | pause->pri_map = 1; |
| 3090 | } |
| 3091 | |
| 3092 | /* rxq setup */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3093 | rxq_init->dscr_map = fp->rx_desc_mapping; |
| 3094 | rxq_init->sge_map = fp->rx_sge_mapping; |
| 3095 | rxq_init->rcq_map = fp->rx_comp_mapping; |
| 3096 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; |
Vladislav Zolotarov | a8c94b9 | 2011-02-06 11:21:02 -0800 | [diff] [blame] | 3097 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3098 | /* This should be a maximum number of data bytes that may be |
| 3099 | * placed on the BD (not including paddings). |
| 3100 | */ |
Eric Dumazet | e52fcb2 | 2011-11-14 06:05:34 +0000 | [diff] [blame] | 3101 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 3102 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
Vladislav Zolotarov | a8c94b9 | 2011-02-06 11:21:02 -0800 | [diff] [blame] | 3103 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3104 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3105 | rxq_init->tpa_agg_sz = tpa_agg_size; |
| 3106 | rxq_init->sge_buf_sz = sge_sz; |
| 3107 | rxq_init->max_sges_pkt = max_sge; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3108 | rxq_init->rss_engine_id = BP_FUNC(bp); |
Yuval Mintz | 259afa1 | 2012-03-12 08:53:10 +0000 | [diff] [blame] | 3109 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3110 | |
| 3111 | /* Maximum number or simultaneous TPA aggregation for this Queue. |
| 3112 | * |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 3113 | * For PF Clients it should be the maximum available number. |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3114 | * VF driver(s) may want to define it to a smaller value. |
| 3115 | */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 3116 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3117 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3118 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
| 3119 | rxq_init->fw_sb_id = fp->fw_sb_id; |
| 3120 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 3121 | if (IS_FCOE_FP(fp)) |
| 3122 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; |
| 3123 | else |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3124 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 3125 | /* configure silent vlan removal |
| 3126 | * if multi function mode is afex, then mask default vlan |
| 3127 | */ |
| 3128 | if (IS_MF_AFEX(bp)) { |
| 3129 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; |
| 3130 | rxq_init->silent_removal_mask = VLAN_VID_MASK; |
| 3131 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3132 | } |
| 3133 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3134 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3135 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
| 3136 | u8 cos) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3137 | { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 3138 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3139 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3140 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
| 3141 | txq_init->fw_sb_id = fp->fw_sb_id; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 3142 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3143 | /* |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 3144 | * set the tss leading client id for TX classification == |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3145 | * leading RSS client id |
| 3146 | */ |
| 3147 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); |
| 3148 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 3149 | if (IS_FCOE_FP(fp)) { |
| 3150 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; |
| 3151 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; |
| 3152 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3153 | } |
| 3154 | |
stephen hemminger | 8d96286 | 2010-10-21 07:50:56 +0000 | [diff] [blame] | 3155 | static void bnx2x_pf_init(struct bnx2x *bp) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3156 | { |
| 3157 | struct bnx2x_func_init_params func_init = {0}; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3158 | struct event_ring_data eq_data = { {0} }; |
| 3159 | u16 flags; |
| 3160 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3161 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3162 | /* reset IGU PF statistics: MSIX + ATTN */ |
| 3163 | /* PF */ |
| 3164 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + |
| 3165 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + |
| 3166 | (CHIP_MODE_IS_4_PORT(bp) ? |
| 3167 | BP_FUNC(bp) : BP_VN(bp))*4, 0); |
| 3168 | /* ATTN */ |
| 3169 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + |
| 3170 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + |
| 3171 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + |
| 3172 | (CHIP_MODE_IS_4_PORT(bp) ? |
| 3173 | BP_FUNC(bp) : BP_VN(bp))*4, 0); |
| 3174 | } |
| 3175 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3176 | /* function setup flags */ |
| 3177 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); |
| 3178 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3179 | /* This flag is relevant for E1x only. |
| 3180 | * E2 doesn't have a TPA configuration in a function level. |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3181 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3182 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3183 | |
| 3184 | func_init.func_flgs = flags; |
| 3185 | func_init.pf_id = BP_FUNC(bp); |
| 3186 | func_init.func_id = BP_FUNC(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3187 | func_init.spq_map = bp->spq_mapping; |
| 3188 | func_init.spq_prod = bp->spq_prod_idx; |
| 3189 | |
| 3190 | bnx2x_func_init(bp, &func_init); |
| 3191 | |
| 3192 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); |
| 3193 | |
| 3194 | /* |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3195 | * Congestion management values depend on the link rate |
| 3196 | * There is no active link so initial link rate is set to 10 Gbps. |
| 3197 | * When the link comes up The congestion management values are |
| 3198 | * re-calculated according to the actual link rate. |
| 3199 | */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3200 | bp->link_vars.line_speed = SPEED_10000; |
| 3201 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); |
| 3202 | |
| 3203 | /* Only the PMF sets the HW */ |
| 3204 | if (bp->port.pmf) |
| 3205 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); |
| 3206 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3207 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3208 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
| 3209 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); |
| 3210 | eq_data.producer = bp->eq_prod; |
| 3211 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; |
| 3212 | eq_data.sb_id = DEF_SB_ID; |
| 3213 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); |
| 3214 | } |
| 3215 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3216 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
| 3217 | { |
| 3218 | int port = BP_PORT(bp); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3219 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3220 | bnx2x_tx_disable(bp); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3221 | |
| 3222 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3223 | } |
| 3224 | |
| 3225 | static void bnx2x_e1h_enable(struct bnx2x *bp) |
| 3226 | { |
| 3227 | int port = BP_PORT(bp); |
| 3228 | |
| 3229 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
| 3230 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 3231 | /* Tx queue should be only re-enabled */ |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3232 | netif_tx_wake_all_queues(bp->dev); |
| 3233 | |
Eilon Greenstein | 061bc70 | 2009-10-15 00:18:47 -0700 | [diff] [blame] | 3234 | /* |
| 3235 | * Should not call netif_carrier_on since it will be called if the link |
| 3236 | * is up when checking for link state |
| 3237 | */ |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3238 | } |
| 3239 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3240 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
| 3241 | |
| 3242 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) |
| 3243 | { |
| 3244 | struct eth_stats_info *ether_stat = |
| 3245 | &bp->slowpath->drv_info_to_mcp.ether_stat; |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 3246 | struct bnx2x_vlan_mac_obj *mac_obj = |
| 3247 | &bp->sp_objs->mac_obj; |
| 3248 | int i; |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3249 | |
Dan Carpenter | 786fdf0 | 2012-10-02 01:47:46 +0000 | [diff] [blame] | 3250 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
| 3251 | ETH_STAT_INFO_VERSION_LEN); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3252 | |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 3253 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
| 3254 | * mac_local field in ether_stat struct. The base address is offset by 2 |
| 3255 | * bytes to account for the field being 8 bytes but a mac address is |
| 3256 | * only 6 bytes. Likewise, the stride for the get_n_elements function is |
| 3257 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes |
| 3258 | * allocated by the ether_stat struct, so the macs will land in their |
| 3259 | * proper positions. |
| 3260 | */ |
| 3261 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) |
| 3262 | memset(ether_stat->mac_local + i, 0, |
| 3263 | sizeof(ether_stat->mac_local[0])); |
| 3264 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, |
| 3265 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, |
| 3266 | ether_stat->mac_local + MAC_PAD, MAC_PAD, |
| 3267 | ETH_ALEN); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3268 | ether_stat->mtu_size = bp->dev->mtu; |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3269 | if (bp->dev->features & NETIF_F_RXCSUM) |
| 3270 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; |
| 3271 | if (bp->dev->features & NETIF_F_TSO) |
| 3272 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; |
| 3273 | ether_stat->feature_flags |= bp->common.boot_mode; |
| 3274 | |
| 3275 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; |
| 3276 | |
| 3277 | ether_stat->txq_size = bp->tx_ring_size; |
| 3278 | ether_stat->rxq_size = bp->rx_ring_size; |
| 3279 | } |
| 3280 | |
| 3281 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) |
| 3282 | { |
| 3283 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
| 3284 | struct fcoe_stats_info *fcoe_stat = |
| 3285 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; |
| 3286 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 3287 | if (!CNIC_LOADED(bp)) |
| 3288 | return; |
| 3289 | |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 3290 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3291 | |
| 3292 | fcoe_stat->qos_priority = |
| 3293 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; |
| 3294 | |
| 3295 | /* insert FCoE stats from ramrod response */ |
| 3296 | if (!NO_FCOE(bp)) { |
| 3297 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 3298 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3299 | tstorm_queue_statistics; |
| 3300 | |
| 3301 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 3302 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3303 | xstorm_queue_statistics; |
| 3304 | |
| 3305 | struct fcoe_statistics_params *fw_fcoe_stat = |
| 3306 | &bp->fw_stats_data->fcoe; |
| 3307 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3308 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
| 3309 | fcoe_stat->rx_bytes_lo, |
| 3310 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3311 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3312 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
| 3313 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, |
| 3314 | fcoe_stat->rx_bytes_lo, |
| 3315 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3316 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3317 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
| 3318 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, |
| 3319 | fcoe_stat->rx_bytes_lo, |
| 3320 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3321 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3322 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
| 3323 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, |
| 3324 | fcoe_stat->rx_bytes_lo, |
| 3325 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3326 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3327 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
| 3328 | fcoe_stat->rx_frames_lo, |
| 3329 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3330 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3331 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
| 3332 | fcoe_stat->rx_frames_lo, |
| 3333 | fcoe_q_tstorm_stats->rcv_ucast_pkts); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3334 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3335 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
| 3336 | fcoe_stat->rx_frames_lo, |
| 3337 | fcoe_q_tstorm_stats->rcv_bcast_pkts); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3338 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3339 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
| 3340 | fcoe_stat->rx_frames_lo, |
| 3341 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3342 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3343 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
| 3344 | fcoe_stat->tx_bytes_lo, |
| 3345 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3346 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3347 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
| 3348 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, |
| 3349 | fcoe_stat->tx_bytes_lo, |
| 3350 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3351 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3352 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
| 3353 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, |
| 3354 | fcoe_stat->tx_bytes_lo, |
| 3355 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3356 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3357 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
| 3358 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, |
| 3359 | fcoe_stat->tx_bytes_lo, |
| 3360 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3361 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3362 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
| 3363 | fcoe_stat->tx_frames_lo, |
| 3364 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3365 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3366 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
| 3367 | fcoe_stat->tx_frames_lo, |
| 3368 | fcoe_q_xstorm_stats->ucast_pkts_sent); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3369 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3370 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
| 3371 | fcoe_stat->tx_frames_lo, |
| 3372 | fcoe_q_xstorm_stats->bcast_pkts_sent); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3373 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 3374 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
| 3375 | fcoe_stat->tx_frames_lo, |
| 3376 | fcoe_q_xstorm_stats->mcast_pkts_sent); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3377 | } |
| 3378 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3379 | /* ask L5 driver to add data to the struct */ |
| 3380 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3381 | } |
| 3382 | |
| 3383 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) |
| 3384 | { |
| 3385 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; |
| 3386 | struct iscsi_stats_info *iscsi_stat = |
| 3387 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; |
| 3388 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 3389 | if (!CNIC_LOADED(bp)) |
| 3390 | return; |
| 3391 | |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 3392 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
| 3393 | ETH_ALEN); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3394 | |
| 3395 | iscsi_stat->qos_priority = |
| 3396 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; |
| 3397 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3398 | /* ask L5 driver to add data to the struct */ |
| 3399 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3400 | } |
| 3401 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 3402 | /* called due to MCP event (on pmf): |
| 3403 | * reread new bandwidth configuration |
| 3404 | * configure FW |
| 3405 | * notify others function about the change |
| 3406 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3407 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 3408 | { |
| 3409 | if (bp->link_vars.link_up) { |
| 3410 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); |
| 3411 | bnx2x_link_sync_notify(bp); |
| 3412 | } |
| 3413 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); |
| 3414 | } |
| 3415 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3416 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 3417 | { |
| 3418 | bnx2x_config_mf_bw(bp); |
| 3419 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); |
| 3420 | } |
| 3421 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 3422 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
| 3423 | { |
| 3424 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); |
| 3425 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); |
| 3426 | } |
| 3427 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3428 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
| 3429 | { |
| 3430 | enum drv_info_opcode op_code; |
| 3431 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); |
| 3432 | |
| 3433 | /* if drv_info version supported by MFW doesn't match - send NACK */ |
| 3434 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { |
| 3435 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); |
| 3436 | return; |
| 3437 | } |
| 3438 | |
| 3439 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> |
| 3440 | DRV_INFO_CONTROL_OP_CODE_SHIFT; |
| 3441 | |
| 3442 | memset(&bp->slowpath->drv_info_to_mcp, 0, |
| 3443 | sizeof(union drv_info_to_mcp)); |
| 3444 | |
| 3445 | switch (op_code) { |
| 3446 | case ETH_STATS_OPCODE: |
| 3447 | bnx2x_drv_info_ether_stat(bp); |
| 3448 | break; |
| 3449 | case FCOE_STATS_OPCODE: |
| 3450 | bnx2x_drv_info_fcoe_stat(bp); |
| 3451 | break; |
| 3452 | case ISCSI_STATS_OPCODE: |
| 3453 | bnx2x_drv_info_iscsi_stat(bp); |
| 3454 | break; |
| 3455 | default: |
| 3456 | /* if op code isn't supported - send NACK */ |
| 3457 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); |
| 3458 | return; |
| 3459 | } |
| 3460 | |
| 3461 | /* if we got drv_info attn from MFW then these fields are defined in |
| 3462 | * shmem2 for sure |
| 3463 | */ |
| 3464 | SHMEM2_WR(bp, drv_info_host_addr_lo, |
| 3465 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); |
| 3466 | SHMEM2_WR(bp, drv_info_host_addr_hi, |
| 3467 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); |
| 3468 | |
| 3469 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); |
| 3470 | } |
| 3471 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3472 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
| 3473 | { |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3474 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3475 | |
| 3476 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { |
| 3477 | |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 3478 | /* |
| 3479 | * This is the only place besides the function initialization |
| 3480 | * where the bp->flags can change so it is done without any |
| 3481 | * locks |
| 3482 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3483 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3484 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 3485 | bp->flags |= MF_FUNC_DIS; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3486 | |
| 3487 | bnx2x_e1h_disable(bp); |
| 3488 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3489 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 3490 | bp->flags &= ~MF_FUNC_DIS; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3491 | |
| 3492 | bnx2x_e1h_enable(bp); |
| 3493 | } |
| 3494 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; |
| 3495 | } |
| 3496 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 3497 | bnx2x_config_mf_bw(bp); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3498 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
| 3499 | } |
| 3500 | |
| 3501 | /* Report results to MCP */ |
| 3502 | if (dcc_event) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 3503 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3504 | else |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 3505 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3506 | } |
| 3507 | |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3508 | /* must be called under the spq lock */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3509 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3510 | { |
| 3511 | struct eth_spe *next_spe = bp->spq_prod_bd; |
| 3512 | |
| 3513 | if (bp->spq_prod_bd == bp->spq_last_bd) { |
| 3514 | bp->spq_prod_bd = bp->spq; |
| 3515 | bp->spq_prod_idx = 0; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3516 | DP(BNX2X_MSG_SP, "end of spq\n"); |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3517 | } else { |
| 3518 | bp->spq_prod_bd++; |
| 3519 | bp->spq_prod_idx++; |
| 3520 | } |
| 3521 | return next_spe; |
| 3522 | } |
| 3523 | |
| 3524 | /* must be called under the spq lock */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3525 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3526 | { |
| 3527 | int func = BP_FUNC(bp); |
| 3528 | |
Vladislav Zolotarov | 53e51e2 | 2011-07-19 01:45:02 +0000 | [diff] [blame] | 3529 | /* |
| 3530 | * Make sure that BD data is updated before writing the producer: |
| 3531 | * BD data is written to the memory, the producer is read from the |
| 3532 | * memory, thus we need a full memory barrier to ensure the ordering. |
| 3533 | */ |
| 3534 | mb(); |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3535 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3536 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 3537 | bp->spq_prod_idx); |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3538 | mmiowb(); |
| 3539 | } |
| 3540 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3541 | /** |
| 3542 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ |
| 3543 | * |
| 3544 | * @cmd: command to check |
| 3545 | * @cmd_type: command type |
| 3546 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3547 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3548 | { |
| 3549 | if ((cmd_type == NONE_CONNECTION_TYPE) || |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 3550 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3551 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
| 3552 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || |
| 3553 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || |
| 3554 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || |
| 3555 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) |
| 3556 | return true; |
| 3557 | else |
| 3558 | return false; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3559 | } |
| 3560 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3561 | /** |
| 3562 | * bnx2x_sp_post - place a single command on an SP ring |
| 3563 | * |
| 3564 | * @bp: driver handle |
| 3565 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) |
| 3566 | * @cid: SW CID the command is related to |
| 3567 | * @data_hi: command private data address (high 32 bits) |
| 3568 | * @data_lo: command private data address (low 32 bits) |
| 3569 | * @cmd_type: command type (e.g. NONE, ETH) |
| 3570 | * |
| 3571 | * SP data is handled as if it's always an address pair, thus data fields are |
| 3572 | * not swapped to little endian in upper functions. Instead this function swaps |
| 3573 | * data as if it's two u32 fields. |
| 3574 | */ |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 3575 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3576 | u32 data_hi, u32 data_lo, int cmd_type) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3577 | { |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3578 | struct eth_spe *spe; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3579 | u16 type; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3580 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3581 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3582 | #ifdef BNX2X_STOP_ON_ERROR |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3583 | if (unlikely(bp->panic)) { |
| 3584 | BNX2X_ERR("Can't post SP when there is panic\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3585 | return -EIO; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3586 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3587 | #endif |
| 3588 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3589 | spin_lock_bh(&bp->spq_lock); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3590 | |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 3591 | if (common) { |
| 3592 | if (!atomic_read(&bp->eq_spq_left)) { |
| 3593 | BNX2X_ERR("BUG! EQ ring full!\n"); |
| 3594 | spin_unlock_bh(&bp->spq_lock); |
| 3595 | bnx2x_panic(); |
| 3596 | return -EBUSY; |
| 3597 | } |
| 3598 | } else if (!atomic_read(&bp->cq_spq_left)) { |
| 3599 | BNX2X_ERR("BUG! SPQ ring full!\n"); |
| 3600 | spin_unlock_bh(&bp->spq_lock); |
| 3601 | bnx2x_panic(); |
| 3602 | return -EBUSY; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3603 | } |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 3604 | |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3605 | spe = bnx2x_sp_get_next(bp); |
| 3606 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3607 | /* CID needs port number to be encoded int it */ |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3608 | spe->hdr.conn_and_cmd_data = |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 3609 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
| 3610 | HW_CID(bp, cid)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3611 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3612 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3613 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3614 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
| 3615 | SPE_HDR_FUNCTION_ID); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3616 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3617 | spe->hdr.type = cpu_to_le16(type); |
| 3618 | |
| 3619 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); |
| 3620 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); |
| 3621 | |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 3622 | /* |
| 3623 | * It's ok if the actual decrement is issued towards the memory |
| 3624 | * somewhere between the spin_lock and spin_unlock. Thus no |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 3625 | * more explicit memory barrier is needed. |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 3626 | */ |
| 3627 | if (common) |
| 3628 | atomic_dec(&bp->eq_spq_left); |
| 3629 | else |
| 3630 | atomic_dec(&bp->cq_spq_left); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 3631 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3632 | DP(BNX2X_MSG_SP, |
| 3633 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 3634 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
| 3635 | (u32)(U64_LO(bp->spq_mapping) + |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 3636 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 3637 | HW_CID(bp, cid), data_hi, data_lo, type, |
| 3638 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 3639 | |
Michael Chan | 2891290 | 2009-10-10 13:46:53 +0000 | [diff] [blame] | 3640 | bnx2x_sp_prod_update(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3641 | spin_unlock_bh(&bp->spq_lock); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3642 | return 0; |
| 3643 | } |
| 3644 | |
| 3645 | /* acquire split MCP access lock register */ |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 3646 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3647 | { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 3648 | u32 j, val; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3649 | int rc = 0; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3650 | |
| 3651 | might_sleep(); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 3652 | for (j = 0; j < 1000; j++) { |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 3653 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
| 3654 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); |
| 3655 | if (val & MCPR_ACCESS_LOCK_LOCK) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3656 | break; |
| 3657 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 3658 | usleep_range(5000, 10000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3659 | } |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 3660 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
Eilon Greenstein | 19680c4 | 2008-08-13 15:47:33 -0700 | [diff] [blame] | 3661 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3662 | rc = -EBUSY; |
| 3663 | } |
| 3664 | |
| 3665 | return rc; |
| 3666 | } |
| 3667 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 3668 | /* release split MCP access lock register */ |
| 3669 | static void bnx2x_release_alr(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3670 | { |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 3671 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3672 | } |
| 3673 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3674 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
| 3675 | #define BNX2X_DEF_SB_IDX 0x0002 |
| 3676 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3677 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3678 | { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3679 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3680 | u16 rc = 0; |
| 3681 | |
| 3682 | barrier(); /* status block is written to by the chip */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3683 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
| 3684 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3685 | rc |= BNX2X_DEF_SB_ATT_IDX; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3686 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3687 | |
| 3688 | if (bp->def_idx != def_sb->sp_sb.running_index) { |
| 3689 | bp->def_idx = def_sb->sp_sb.running_index; |
| 3690 | rc |= BNX2X_DEF_SB_IDX; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3691 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3692 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 3693 | /* Do not reorder: indices reading should complete before handling */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 3694 | barrier(); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3695 | return rc; |
| 3696 | } |
| 3697 | |
| 3698 | /* |
| 3699 | * slow path service functions |
| 3700 | */ |
| 3701 | |
| 3702 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) |
| 3703 | { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3704 | int port = BP_PORT(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3705 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
| 3706 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3707 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
| 3708 | NIG_REG_MASK_INTERRUPT_PORT0; |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3709 | u32 aeu_mask; |
Eilon Greenstein | 87942b4 | 2009-02-12 08:36:49 +0000 | [diff] [blame] | 3710 | u32 nig_mask = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3711 | u32 reg_addr; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3712 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3713 | if (bp->attn_state & asserted) |
| 3714 | BNX2X_ERR("IGU ERROR\n"); |
| 3715 | |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3716 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
| 3717 | aeu_mask = REG_RD(bp, aeu_addr); |
| 3718 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3719 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3720 | aeu_mask, asserted); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 3721 | aeu_mask &= ~(asserted & 0x3ff); |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3722 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3723 | |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3724 | REG_WR(bp, aeu_addr, aeu_mask); |
| 3725 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3726 | |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3727 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3728 | bp->attn_state |= asserted; |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 3729 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3730 | |
| 3731 | if (asserted & ATTN_HARD_WIRED_MASK) { |
| 3732 | if (asserted & ATTN_NIG_FOR_FUNC) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3733 | |
Eilon Greenstein | a5e9a7c | 2009-01-14 21:26:01 -0800 | [diff] [blame] | 3734 | bnx2x_acquire_phy_lock(bp); |
| 3735 | |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3736 | /* save nig interrupt mask */ |
Eilon Greenstein | 87942b4 | 2009-02-12 08:36:49 +0000 | [diff] [blame] | 3737 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3738 | |
Yaniv Rosner | 361c391 | 2011-06-14 01:33:19 +0000 | [diff] [blame] | 3739 | /* If nig_mask is not set, no need to call the update |
| 3740 | * function. |
| 3741 | */ |
| 3742 | if (nig_mask) { |
| 3743 | REG_WR(bp, nig_int_mask_addr, 0); |
| 3744 | |
| 3745 | bnx2x_link_attn(bp); |
| 3746 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3747 | |
| 3748 | /* handle unicore attn? */ |
| 3749 | } |
| 3750 | if (asserted & ATTN_SW_TIMER_4_FUNC) |
| 3751 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); |
| 3752 | |
| 3753 | if (asserted & GPIO_2_FUNC) |
| 3754 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); |
| 3755 | |
| 3756 | if (asserted & GPIO_3_FUNC) |
| 3757 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); |
| 3758 | |
| 3759 | if (asserted & GPIO_4_FUNC) |
| 3760 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); |
| 3761 | |
| 3762 | if (port == 0) { |
| 3763 | if (asserted & ATTN_GENERAL_ATTN_1) { |
| 3764 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); |
| 3765 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); |
| 3766 | } |
| 3767 | if (asserted & ATTN_GENERAL_ATTN_2) { |
| 3768 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); |
| 3769 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); |
| 3770 | } |
| 3771 | if (asserted & ATTN_GENERAL_ATTN_3) { |
| 3772 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); |
| 3773 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); |
| 3774 | } |
| 3775 | } else { |
| 3776 | if (asserted & ATTN_GENERAL_ATTN_4) { |
| 3777 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); |
| 3778 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); |
| 3779 | } |
| 3780 | if (asserted & ATTN_GENERAL_ATTN_5) { |
| 3781 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); |
| 3782 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); |
| 3783 | } |
| 3784 | if (asserted & ATTN_GENERAL_ATTN_6) { |
| 3785 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); |
| 3786 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); |
| 3787 | } |
| 3788 | } |
| 3789 | |
| 3790 | } /* if hardwired */ |
| 3791 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3792 | if (bp->common.int_block == INT_BLOCK_HC) |
| 3793 | reg_addr = (HC_REG_COMMAND_REG + port*32 + |
| 3794 | COMMAND_REG_ATTN_BITS_SET); |
| 3795 | else |
| 3796 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); |
| 3797 | |
| 3798 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, |
| 3799 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); |
| 3800 | REG_WR(bp, reg_addr, asserted); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 3801 | |
| 3802 | /* now set back the mask */ |
Eilon Greenstein | a5e9a7c | 2009-01-14 21:26:01 -0800 | [diff] [blame] | 3803 | if (asserted & ATTN_NIG_FOR_FUNC) { |
Yaniv Rosner | 27c1151 | 2012-12-02 04:05:54 +0000 | [diff] [blame] | 3804 | /* Verify that IGU ack through BAR was written before restoring |
| 3805 | * NIG mask. This loop should exit after 2-3 iterations max. |
| 3806 | */ |
| 3807 | if (bp->common.int_block != INT_BLOCK_HC) { |
| 3808 | u32 cnt = 0, igu_acked; |
| 3809 | do { |
| 3810 | igu_acked = REG_RD(bp, |
| 3811 | IGU_REG_ATTENTION_ACK_BITS); |
| 3812 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && |
| 3813 | (++cnt < MAX_IGU_ATTN_ACK_TO)); |
| 3814 | if (!igu_acked) |
| 3815 | DP(NETIF_MSG_HW, |
| 3816 | "Failed to verify IGU ack on time\n"); |
| 3817 | barrier(); |
| 3818 | } |
Eilon Greenstein | 87942b4 | 2009-02-12 08:36:49 +0000 | [diff] [blame] | 3819 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
Eilon Greenstein | a5e9a7c | 2009-01-14 21:26:01 -0800 | [diff] [blame] | 3820 | bnx2x_release_phy_lock(bp); |
| 3821 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3822 | } |
| 3823 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3824 | static void bnx2x_fan_failure(struct bnx2x *bp) |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3825 | { |
| 3826 | int port = BP_PORT(bp); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 3827 | u32 ext_phy_config; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3828 | /* mark the failure */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 3829 | ext_phy_config = |
| 3830 | SHMEM_RD(bp, |
| 3831 | dev_info.port_hw_config[port].external_phy_config); |
| 3832 | |
| 3833 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; |
| 3834 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3835 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 3836 | ext_phy_config); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3837 | |
| 3838 | /* log the failure */ |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 3839 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
| 3840 | "Please contact OEM Support for assistance\n"); |
Ariel Elior | 8304859 | 2011-11-13 04:34:29 +0000 | [diff] [blame] | 3841 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 3842 | /* Schedule device reset (unload) |
Ariel Elior | 8304859 | 2011-11-13 04:34:29 +0000 | [diff] [blame] | 3843 | * This is due to some boards consuming sufficient power when driver is |
| 3844 | * up to overheat if fan fails. |
| 3845 | */ |
| 3846 | smp_mb__before_clear_bit(); |
| 3847 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); |
| 3848 | smp_mb__after_clear_bit(); |
| 3849 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3850 | } |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 3851 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3852 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3853 | { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3854 | int port = BP_PORT(bp); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3855 | int reg_offset; |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 3856 | u32 val; |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3857 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3858 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
| 3859 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3860 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3861 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3862 | |
| 3863 | val = REG_RD(bp, reg_offset); |
| 3864 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; |
| 3865 | REG_WR(bp, reg_offset, val); |
| 3866 | |
| 3867 | BNX2X_ERR("SPIO5 hw attention\n"); |
| 3868 | |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3869 | /* Fan failure attention */ |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 3870 | bnx2x_hw_reset_phy(&bp->link_params); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 3871 | bnx2x_fan_failure(bp); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3872 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3873 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 3874 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 3875 | bnx2x_acquire_phy_lock(bp); |
| 3876 | bnx2x_handle_module_detect_int(&bp->link_params); |
| 3877 | bnx2x_release_phy_lock(bp); |
| 3878 | } |
| 3879 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3880 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
| 3881 | |
| 3882 | val = REG_RD(bp, reg_offset); |
| 3883 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); |
| 3884 | REG_WR(bp, reg_offset, val); |
| 3885 | |
| 3886 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", |
Eilon Greenstein | 0fc5d00 | 2009-08-12 08:24:05 +0000 | [diff] [blame] | 3887 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3888 | bnx2x_panic(); |
| 3889 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3890 | } |
| 3891 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3892 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3893 | { |
| 3894 | u32 val; |
| 3895 | |
Eilon Greenstein | 0626b89 | 2009-02-12 08:38:14 +0000 | [diff] [blame] | 3896 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3897 | |
| 3898 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); |
| 3899 | BNX2X_ERR("DB hw attention 0x%x\n", val); |
| 3900 | /* DORQ discard attention */ |
| 3901 | if (val & 0x2) |
| 3902 | BNX2X_ERR("FATAL error from DORQ\n"); |
| 3903 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3904 | |
| 3905 | if (attn & HW_INTERRUT_ASSERT_SET_1) { |
| 3906 | |
| 3907 | int port = BP_PORT(bp); |
| 3908 | int reg_offset; |
| 3909 | |
| 3910 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : |
| 3911 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); |
| 3912 | |
| 3913 | val = REG_RD(bp, reg_offset); |
| 3914 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); |
| 3915 | REG_WR(bp, reg_offset, val); |
| 3916 | |
| 3917 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", |
Eilon Greenstein | 0fc5d00 | 2009-08-12 08:24:05 +0000 | [diff] [blame] | 3918 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3919 | bnx2x_panic(); |
| 3920 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3921 | } |
| 3922 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3923 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3924 | { |
| 3925 | u32 val; |
| 3926 | |
| 3927 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { |
| 3928 | |
| 3929 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); |
| 3930 | BNX2X_ERR("CFC hw attention 0x%x\n", val); |
| 3931 | /* CFC error attention */ |
| 3932 | if (val & 0x2) |
| 3933 | BNX2X_ERR("FATAL error from CFC\n"); |
| 3934 | } |
| 3935 | |
| 3936 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3937 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3938 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3939 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
| 3940 | if (val & 0x18000) |
| 3941 | BNX2X_ERR("FATAL error from PXP\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 3942 | |
| 3943 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3944 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
| 3945 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); |
| 3946 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3947 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3948 | |
| 3949 | if (attn & HW_INTERRUT_ASSERT_SET_2) { |
| 3950 | |
| 3951 | int port = BP_PORT(bp); |
| 3952 | int reg_offset; |
| 3953 | |
| 3954 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : |
| 3955 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); |
| 3956 | |
| 3957 | val = REG_RD(bp, reg_offset); |
| 3958 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); |
| 3959 | REG_WR(bp, reg_offset, val); |
| 3960 | |
| 3961 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", |
Eilon Greenstein | 0fc5d00 | 2009-08-12 08:24:05 +0000 | [diff] [blame] | 3962 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3963 | bnx2x_panic(); |
| 3964 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3965 | } |
| 3966 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 3967 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3968 | { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3969 | u32 val; |
| 3970 | |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 3971 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
| 3972 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3973 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
| 3974 | int func = BP_FUNC(bp); |
| 3975 | |
| 3976 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 3977 | bnx2x_read_mf_cfg(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 3978 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
| 3979 | func_mf_config[BP_ABS_FUNC(bp)].config); |
| 3980 | val = SHMEM_RD(bp, |
| 3981 | func_mb[BP_FW_MB_IDX(bp)].drv_status); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3982 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
| 3983 | bnx2x_dcc_event(bp, |
| 3984 | (val & DRV_STATUS_DCC_EVENT_MASK)); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 3985 | |
| 3986 | if (val & DRV_STATUS_SET_MF_BW) |
| 3987 | bnx2x_set_mf_bw(bp); |
| 3988 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 3989 | if (val & DRV_STATUS_DRV_INFO_REQ) |
| 3990 | bnx2x_handle_drv_info_req(bp); |
Ariel Elior | d16132c | 2013-01-01 05:22:42 +0000 | [diff] [blame] | 3991 | |
| 3992 | if (val & DRV_STATUS_VF_DISABLED) |
| 3993 | bnx2x_vf_handle_flr_event(bp); |
| 3994 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 3995 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 3996 | bnx2x_pmf_update(bp); |
| 3997 | |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 3998 | if (bp->port.pmf && |
Shmulik Ravid | 785b9b1 | 2010-12-30 06:27:03 +0000 | [diff] [blame] | 3999 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
| 4000 | bp->dcbx_enabled > 0) |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 4001 | /* start dcbx state machine */ |
| 4002 | bnx2x_dcbx_set_params(bp, |
| 4003 | BNX2X_DCBX_STATE_NEG_RECEIVED); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 4004 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
| 4005 | bnx2x_handle_afex_cmd(bp, |
| 4006 | val & DRV_STATUS_AFEX_EVENT_MASK); |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 4007 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
| 4008 | bnx2x_handle_eee_event(bp); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 4009 | if (bp->link_vars.periodic_flags & |
| 4010 | PERIODIC_FLAGS_LINK_EVENT) { |
| 4011 | /* sync with link */ |
| 4012 | bnx2x_acquire_phy_lock(bp); |
| 4013 | bp->link_vars.periodic_flags &= |
| 4014 | ~PERIODIC_FLAGS_LINK_EVENT; |
| 4015 | bnx2x_release_phy_lock(bp); |
| 4016 | if (IS_MF(bp)) |
| 4017 | bnx2x_link_sync_notify(bp); |
| 4018 | bnx2x_link_report(bp); |
| 4019 | } |
| 4020 | /* Always call it here: bnx2x_link_report() will |
| 4021 | * prevent the link indication duplication. |
| 4022 | */ |
| 4023 | bnx2x__link_status_update(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4024 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4025 | |
| 4026 | BNX2X_ERR("MC assert!\n"); |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 4027 | bnx2x_mc_assert(bp); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4028 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
| 4029 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); |
| 4030 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); |
| 4031 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); |
| 4032 | bnx2x_panic(); |
| 4033 | |
| 4034 | } else if (attn & BNX2X_MCP_ASSERT) { |
| 4035 | |
| 4036 | BNX2X_ERR("MCP assert!\n"); |
| 4037 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4038 | bnx2x_fw_dump(bp); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4039 | |
| 4040 | } else |
| 4041 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); |
| 4042 | } |
| 4043 | |
| 4044 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4045 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
| 4046 | if (attn & BNX2X_GRC_TIMEOUT) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4047 | val = CHIP_IS_E1(bp) ? 0 : |
| 4048 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4049 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
| 4050 | } |
| 4051 | if (attn & BNX2X_GRC_RSV) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4052 | val = CHIP_IS_E1(bp) ? 0 : |
| 4053 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4054 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
| 4055 | } |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4056 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4057 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4058 | } |
| 4059 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4060 | /* |
| 4061 | * Bits map: |
| 4062 | * 0-7 - Engine0 load counter. |
| 4063 | * 8-15 - Engine1 load counter. |
| 4064 | * 16 - Engine0 RESET_IN_PROGRESS bit. |
| 4065 | * 17 - Engine1 RESET_IN_PROGRESS bit. |
| 4066 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function |
| 4067 | * on the engine |
| 4068 | * 19 - Engine1 ONE_IS_LOADED. |
| 4069 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines |
| 4070 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for |
| 4071 | * just the one belonging to its engine). |
| 4072 | * |
| 4073 | */ |
| 4074 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 |
| 4075 | |
| 4076 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff |
| 4077 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 |
| 4078 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 |
| 4079 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 |
| 4080 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 |
| 4081 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 |
| 4082 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 4083 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4084 | /* |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4085 | * Set the GLOBAL_RESET bit. |
| 4086 | * |
| 4087 | * Should be run under rtnl lock |
| 4088 | */ |
| 4089 | void bnx2x_set_reset_global(struct bnx2x *bp) |
| 4090 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4091 | u32 val; |
| 4092 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4093 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4094 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4095 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4096 | } |
| 4097 | |
| 4098 | /* |
| 4099 | * Clear the GLOBAL_RESET bit. |
| 4100 | * |
| 4101 | * Should be run under rtnl lock |
| 4102 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4103 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4104 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4105 | u32 val; |
| 4106 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4107 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4108 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4109 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4110 | } |
| 4111 | |
| 4112 | /* |
| 4113 | * Checks the GLOBAL_RESET bit. |
| 4114 | * |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4115 | * should be run under rtnl lock |
| 4116 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4117 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4118 | { |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 4119 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4120 | |
| 4121 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); |
| 4122 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; |
| 4123 | } |
| 4124 | |
| 4125 | /* |
| 4126 | * Clear RESET_IN_PROGRESS bit for the current engine. |
| 4127 | * |
| 4128 | * Should be run under rtnl lock |
| 4129 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4130 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4131 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4132 | u32 val; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4133 | u32 bit = BP_PATH(bp) ? |
| 4134 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4135 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4136 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4137 | |
| 4138 | /* Clear the bit */ |
| 4139 | val &= ~bit; |
| 4140 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4141 | |
| 4142 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4143 | } |
| 4144 | |
| 4145 | /* |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4146 | * Set RESET_IN_PROGRESS for the current engine. |
| 4147 | * |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4148 | * should be run under rtnl lock |
| 4149 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4150 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4151 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4152 | u32 val; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4153 | u32 bit = BP_PATH(bp) ? |
| 4154 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4155 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4156 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4157 | |
| 4158 | /* Set the bit */ |
| 4159 | val |= bit; |
| 4160 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4161 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4162 | } |
| 4163 | |
| 4164 | /* |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4165 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4166 | * should be run under rtnl lock |
| 4167 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4168 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4169 | { |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 4170 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4171 | u32 bit = engine ? |
| 4172 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; |
| 4173 | |
| 4174 | /* return false if bit is set */ |
| 4175 | return (val & bit) ? false : true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4176 | } |
| 4177 | |
| 4178 | /* |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4179 | * set pf load for the current pf. |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4180 | * |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4181 | * should be run under rtnl lock |
| 4182 | */ |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4183 | void bnx2x_set_pf_load(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4184 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4185 | u32 val1, val; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4186 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
| 4187 | BNX2X_PATH0_LOAD_CNT_MASK; |
| 4188 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : |
| 4189 | BNX2X_PATH0_LOAD_CNT_SHIFT; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4190 | |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4192 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
| 4193 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4194 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4195 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4196 | /* get the current counter value */ |
| 4197 | val1 = (val & mask) >> shift; |
| 4198 | |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4199 | /* set bit of that PF */ |
| 4200 | val1 |= (1 << bp->pf_num); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4201 | |
| 4202 | /* clear the old value */ |
| 4203 | val &= ~mask; |
| 4204 | |
| 4205 | /* set the new one */ |
| 4206 | val |= ((val1 << shift) & mask); |
| 4207 | |
| 4208 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4209 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4210 | } |
| 4211 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4212 | /** |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4213 | * bnx2x_clear_pf_load - clear pf load mark |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4214 | * |
| 4215 | * @bp: driver handle |
| 4216 | * |
| 4217 | * Should be run under rtnl lock. |
| 4218 | * Decrements the load counter for the current engine. Returns |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4219 | * whether other functions are still loaded |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4220 | */ |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4221 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4222 | { |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4223 | u32 val1, val; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4224 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
| 4225 | BNX2X_PATH0_LOAD_CNT_MASK; |
| 4226 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : |
| 4227 | BNX2X_PATH0_LOAD_CNT_SHIFT; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4228 | |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4229 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4230 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4231 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4232 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4233 | /* get the current counter value */ |
| 4234 | val1 = (val & mask) >> shift; |
| 4235 | |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4236 | /* clear bit of that PF */ |
| 4237 | val1 &= ~(1 << bp->pf_num); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4238 | |
| 4239 | /* clear the old value */ |
| 4240 | val &= ~mask; |
| 4241 | |
| 4242 | /* set the new one */ |
| 4243 | val |= ((val1 << shift) & mask); |
| 4244 | |
| 4245 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 4246 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
| 4247 | return val1 != 0; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4248 | } |
| 4249 | |
| 4250 | /* |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4251 | * Read the load status for the current engine. |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4252 | * |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4253 | * should be run under rtnl lock |
| 4254 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4255 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4256 | { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4257 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
| 4258 | BNX2X_PATH0_LOAD_CNT_MASK); |
| 4259 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : |
| 4260 | BNX2X_PATH0_LOAD_CNT_SHIFT); |
| 4261 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
| 4262 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4263 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4264 | |
| 4265 | val = (val & mask) >> shift; |
| 4266 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4267 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
| 4268 | engine, val); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4269 | |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 4270 | return val != 0; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4271 | } |
| 4272 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4273 | static void _print_parity(struct bnx2x *bp, u32 reg) |
| 4274 | { |
| 4275 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); |
| 4276 | } |
| 4277 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4278 | static void _print_next_block(int idx, const char *blk) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4279 | { |
Joe Perches | f1deab5 | 2011-08-14 12:16:21 +0000 | [diff] [blame] | 4280 | pr_cont("%s%s", idx ? ", " : "", blk); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4281 | } |
| 4282 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4283 | static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
| 4284 | int par_num, bool print) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4285 | { |
| 4286 | int i = 0; |
| 4287 | u32 cur_bit = 0; |
| 4288 | for (i = 0; sig; i++) { |
| 4289 | cur_bit = ((u32)0x1 << i); |
| 4290 | if (sig & cur_bit) { |
| 4291 | switch (cur_bit) { |
| 4292 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4293 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4294 | _print_next_block(par_num++, "BRB"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4295 | _print_parity(bp, |
| 4296 | BRB1_REG_BRB1_PRTY_STS); |
| 4297 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4298 | break; |
| 4299 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4300 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4301 | _print_next_block(par_num++, "PARSER"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4302 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
| 4303 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4304 | break; |
| 4305 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4306 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4307 | _print_next_block(par_num++, "TSDM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4308 | _print_parity(bp, |
| 4309 | TSDM_REG_TSDM_PRTY_STS); |
| 4310 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4311 | break; |
| 4312 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4313 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4314 | _print_next_block(par_num++, |
| 4315 | "SEARCHER"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4316 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
| 4317 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4318 | break; |
| 4319 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4320 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4321 | _print_next_block(par_num++, "TCM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4322 | _print_parity(bp, |
| 4323 | TCM_REG_TCM_PRTY_STS); |
| 4324 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4325 | break; |
| 4326 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4327 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4328 | _print_next_block(par_num++, "TSEMI"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4329 | _print_parity(bp, |
| 4330 | TSEM_REG_TSEM_PRTY_STS_0); |
| 4331 | _print_parity(bp, |
| 4332 | TSEM_REG_TSEM_PRTY_STS_1); |
| 4333 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4334 | break; |
| 4335 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4336 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4337 | _print_next_block(par_num++, "XPB"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4338 | _print_parity(bp, GRCBASE_XPB + |
| 4339 | PB_REG_PB_PRTY_STS); |
| 4340 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4341 | break; |
| 4342 | } |
| 4343 | |
| 4344 | /* Clear the bit */ |
| 4345 | sig &= ~cur_bit; |
| 4346 | } |
| 4347 | } |
| 4348 | |
| 4349 | return par_num; |
| 4350 | } |
| 4351 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4352 | static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
| 4353 | int par_num, bool *global, |
| 4354 | bool print) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4355 | { |
| 4356 | int i = 0; |
| 4357 | u32 cur_bit = 0; |
| 4358 | for (i = 0; sig; i++) { |
| 4359 | cur_bit = ((u32)0x1 << i); |
| 4360 | if (sig & cur_bit) { |
| 4361 | switch (cur_bit) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4362 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4363 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4364 | _print_next_block(par_num++, "PBF"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4365 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
| 4366 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4367 | break; |
| 4368 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4369 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4370 | _print_next_block(par_num++, "QM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4371 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
| 4372 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4373 | break; |
| 4374 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4375 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4376 | _print_next_block(par_num++, "TM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4377 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
| 4378 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4379 | break; |
| 4380 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4381 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4382 | _print_next_block(par_num++, "XSDM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4383 | _print_parity(bp, |
| 4384 | XSDM_REG_XSDM_PRTY_STS); |
| 4385 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4386 | break; |
| 4387 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4388 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4389 | _print_next_block(par_num++, "XCM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4390 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
| 4391 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4392 | break; |
| 4393 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4394 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4395 | _print_next_block(par_num++, "XSEMI"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4396 | _print_parity(bp, |
| 4397 | XSEM_REG_XSEM_PRTY_STS_0); |
| 4398 | _print_parity(bp, |
| 4399 | XSEM_REG_XSEM_PRTY_STS_1); |
| 4400 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4401 | break; |
| 4402 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4403 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4404 | _print_next_block(par_num++, |
| 4405 | "DOORBELLQ"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4406 | _print_parity(bp, |
| 4407 | DORQ_REG_DORQ_PRTY_STS); |
| 4408 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4409 | break; |
| 4410 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4411 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4412 | _print_next_block(par_num++, "NIG"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4413 | if (CHIP_IS_E1x(bp)) { |
| 4414 | _print_parity(bp, |
| 4415 | NIG_REG_NIG_PRTY_STS); |
| 4416 | } else { |
| 4417 | _print_parity(bp, |
| 4418 | NIG_REG_NIG_PRTY_STS_0); |
| 4419 | _print_parity(bp, |
| 4420 | NIG_REG_NIG_PRTY_STS_1); |
| 4421 | } |
| 4422 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4423 | break; |
| 4424 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4425 | if (print) |
| 4426 | _print_next_block(par_num++, |
| 4427 | "VAUX PCI CORE"); |
| 4428 | *global = true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4429 | break; |
| 4430 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4431 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4432 | _print_next_block(par_num++, "DEBUG"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4433 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
| 4434 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4435 | break; |
| 4436 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4437 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4438 | _print_next_block(par_num++, "USDM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4439 | _print_parity(bp, |
| 4440 | USDM_REG_USDM_PRTY_STS); |
| 4441 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4442 | break; |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4443 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4444 | if (print) { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4445 | _print_next_block(par_num++, "UCM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4446 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
| 4447 | } |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4448 | break; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4449 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4450 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4451 | _print_next_block(par_num++, "USEMI"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4452 | _print_parity(bp, |
| 4453 | USEM_REG_USEM_PRTY_STS_0); |
| 4454 | _print_parity(bp, |
| 4455 | USEM_REG_USEM_PRTY_STS_1); |
| 4456 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4457 | break; |
| 4458 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4459 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4460 | _print_next_block(par_num++, "UPB"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4461 | _print_parity(bp, GRCBASE_UPB + |
| 4462 | PB_REG_PB_PRTY_STS); |
| 4463 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4464 | break; |
| 4465 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4466 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4467 | _print_next_block(par_num++, "CSDM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4468 | _print_parity(bp, |
| 4469 | CSDM_REG_CSDM_PRTY_STS); |
| 4470 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4471 | break; |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4472 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4473 | if (print) { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4474 | _print_next_block(par_num++, "CCM"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4475 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
| 4476 | } |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4477 | break; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4478 | } |
| 4479 | |
| 4480 | /* Clear the bit */ |
| 4481 | sig &= ~cur_bit; |
| 4482 | } |
| 4483 | } |
| 4484 | |
| 4485 | return par_num; |
| 4486 | } |
| 4487 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4488 | static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
| 4489 | int par_num, bool print) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4490 | { |
| 4491 | int i = 0; |
| 4492 | u32 cur_bit = 0; |
| 4493 | for (i = 0; sig; i++) { |
| 4494 | cur_bit = ((u32)0x1 << i); |
| 4495 | if (sig & cur_bit) { |
| 4496 | switch (cur_bit) { |
| 4497 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4498 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4499 | _print_next_block(par_num++, "CSEMI"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4500 | _print_parity(bp, |
| 4501 | CSEM_REG_CSEM_PRTY_STS_0); |
| 4502 | _print_parity(bp, |
| 4503 | CSEM_REG_CSEM_PRTY_STS_1); |
| 4504 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4505 | break; |
| 4506 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4507 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4508 | _print_next_block(par_num++, "PXP"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4509 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
| 4510 | _print_parity(bp, |
| 4511 | PXP2_REG_PXP2_PRTY_STS_0); |
| 4512 | _print_parity(bp, |
| 4513 | PXP2_REG_PXP2_PRTY_STS_1); |
| 4514 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4515 | break; |
| 4516 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4517 | if (print) |
| 4518 | _print_next_block(par_num++, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4519 | "PXPPCICLOCKCLIENT"); |
| 4520 | break; |
| 4521 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4522 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4523 | _print_next_block(par_num++, "CFC"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4524 | _print_parity(bp, |
| 4525 | CFC_REG_CFC_PRTY_STS); |
| 4526 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4527 | break; |
| 4528 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4529 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4530 | _print_next_block(par_num++, "CDU"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4531 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
| 4532 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4533 | break; |
| 4534 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4535 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4536 | _print_next_block(par_num++, "DMAE"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4537 | _print_parity(bp, |
| 4538 | DMAE_REG_DMAE_PRTY_STS); |
| 4539 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4540 | break; |
| 4541 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4542 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4543 | _print_next_block(par_num++, "IGU"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4544 | if (CHIP_IS_E1x(bp)) |
| 4545 | _print_parity(bp, |
| 4546 | HC_REG_HC_PRTY_STS); |
| 4547 | else |
| 4548 | _print_parity(bp, |
| 4549 | IGU_REG_IGU_PRTY_STS); |
| 4550 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4551 | break; |
| 4552 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4553 | if (print) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4554 | _print_next_block(par_num++, "MISC"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4555 | _print_parity(bp, |
| 4556 | MISC_REG_MISC_PRTY_STS); |
| 4557 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4558 | break; |
| 4559 | } |
| 4560 | |
| 4561 | /* Clear the bit */ |
| 4562 | sig &= ~cur_bit; |
| 4563 | } |
| 4564 | } |
| 4565 | |
| 4566 | return par_num; |
| 4567 | } |
| 4568 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4569 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
| 4570 | bool *global, bool print) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4571 | { |
| 4572 | int i = 0; |
| 4573 | u32 cur_bit = 0; |
| 4574 | for (i = 0; sig; i++) { |
| 4575 | cur_bit = ((u32)0x1 << i); |
| 4576 | if (sig & cur_bit) { |
| 4577 | switch (cur_bit) { |
| 4578 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4579 | if (print) |
| 4580 | _print_next_block(par_num++, "MCP ROM"); |
| 4581 | *global = true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4582 | break; |
| 4583 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4584 | if (print) |
| 4585 | _print_next_block(par_num++, |
| 4586 | "MCP UMP RX"); |
| 4587 | *global = true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4588 | break; |
| 4589 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4590 | if (print) |
| 4591 | _print_next_block(par_num++, |
| 4592 | "MCP UMP TX"); |
| 4593 | *global = true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4594 | break; |
| 4595 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4596 | if (print) |
| 4597 | _print_next_block(par_num++, |
| 4598 | "MCP SCPAD"); |
| 4599 | *global = true; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4600 | break; |
| 4601 | } |
| 4602 | |
| 4603 | /* Clear the bit */ |
| 4604 | sig &= ~cur_bit; |
| 4605 | } |
| 4606 | } |
| 4607 | |
| 4608 | return par_num; |
| 4609 | } |
| 4610 | |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4611 | static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
| 4612 | int par_num, bool print) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4613 | { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4614 | int i = 0; |
| 4615 | u32 cur_bit = 0; |
| 4616 | for (i = 0; sig; i++) { |
| 4617 | cur_bit = ((u32)0x1 << i); |
| 4618 | if (sig & cur_bit) { |
| 4619 | switch (cur_bit) { |
| 4620 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4621 | if (print) { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4622 | _print_next_block(par_num++, "PGLUE_B"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4623 | _print_parity(bp, |
| 4624 | PGLUE_B_REG_PGLUE_B_PRTY_STS); |
| 4625 | } |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4626 | break; |
| 4627 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4628 | if (print) { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4629 | _print_next_block(par_num++, "ATC"); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4630 | _print_parity(bp, |
| 4631 | ATC_REG_ATC_PRTY_STS); |
| 4632 | } |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4633 | break; |
| 4634 | } |
| 4635 | |
| 4636 | /* Clear the bit */ |
| 4637 | sig &= ~cur_bit; |
| 4638 | } |
| 4639 | } |
| 4640 | |
| 4641 | return par_num; |
| 4642 | } |
| 4643 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4644 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
| 4645 | u32 *sig) |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4646 | { |
| 4647 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
| 4648 | (sig[1] & HW_PRTY_ASSERT_SET_1) || |
| 4649 | (sig[2] & HW_PRTY_ASSERT_SET_2) || |
| 4650 | (sig[3] & HW_PRTY_ASSERT_SET_3) || |
| 4651 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4652 | int par_num = 0; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4653 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
| 4654 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4655 | sig[0] & HW_PRTY_ASSERT_SET_0, |
| 4656 | sig[1] & HW_PRTY_ASSERT_SET_1, |
| 4657 | sig[2] & HW_PRTY_ASSERT_SET_2, |
| 4658 | sig[3] & HW_PRTY_ASSERT_SET_3, |
| 4659 | sig[4] & HW_PRTY_ASSERT_SET_4); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4660 | if (print) |
| 4661 | netdev_err(bp->dev, |
| 4662 | "Parity errors detected in blocks: "); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4663 | par_num = bnx2x_check_blocks_with_parity0(bp, |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4664 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4665 | par_num = bnx2x_check_blocks_with_parity1(bp, |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4666 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4667 | par_num = bnx2x_check_blocks_with_parity2(bp, |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4668 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4669 | par_num = bnx2x_check_blocks_with_parity3( |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4670 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 4671 | par_num = bnx2x_check_blocks_with_parity4(bp, |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4672 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); |
| 4673 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4674 | if (print) |
| 4675 | pr_cont("\n"); |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4676 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4677 | return true; |
| 4678 | } else |
| 4679 | return false; |
| 4680 | } |
| 4681 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4682 | /** |
| 4683 | * bnx2x_chk_parity_attn - checks for parity attentions. |
| 4684 | * |
| 4685 | * @bp: driver handle |
| 4686 | * @global: true if there was a global attention |
| 4687 | * @print: show parity attention in syslog |
| 4688 | */ |
| 4689 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4690 | { |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4691 | struct attn_route attn = { {0} }; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4692 | int port = BP_PORT(bp); |
| 4693 | |
| 4694 | attn.sig[0] = REG_RD(bp, |
| 4695 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + |
| 4696 | port*4); |
| 4697 | attn.sig[1] = REG_RD(bp, |
| 4698 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + |
| 4699 | port*4); |
| 4700 | attn.sig[2] = REG_RD(bp, |
| 4701 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + |
| 4702 | port*4); |
| 4703 | attn.sig[3] = REG_RD(bp, |
| 4704 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + |
| 4705 | port*4); |
| 4706 | |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 4707 | if (!CHIP_IS_E1x(bp)) |
| 4708 | attn.sig[4] = REG_RD(bp, |
| 4709 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + |
| 4710 | port*4); |
| 4711 | |
| 4712 | return bnx2x_parity_attn(bp, global, print, attn.sig); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4713 | } |
| 4714 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4715 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4716 | { |
| 4717 | u32 val; |
| 4718 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { |
| 4719 | |
| 4720 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); |
| 4721 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); |
| 4722 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4723 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4724 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4725 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4726 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4727 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4728 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4729 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4730 | if (val & |
| 4731 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4732 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4733 | if (val & |
| 4734 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4735 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4736 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4737 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4738 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4739 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4740 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4741 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4742 | } |
| 4743 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { |
| 4744 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); |
| 4745 | BNX2X_ERR("ATC hw attention 0x%x\n", val); |
| 4746 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) |
| 4747 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); |
| 4748 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4749 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4750 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4751 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4752 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4753 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4754 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
| 4755 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); |
| 4756 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4757 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4758 | } |
| 4759 | |
| 4760 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | |
| 4761 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { |
| 4762 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", |
| 4763 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | |
| 4764 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); |
| 4765 | } |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4766 | } |
| 4767 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4768 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
| 4769 | { |
| 4770 | struct attn_route attn, *group_mask; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4771 | int port = BP_PORT(bp); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4772 | int index; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4773 | u32 reg_addr; |
| 4774 | u32 val; |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 4775 | u32 aeu_mask; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4776 | bool global = false; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4777 | |
| 4778 | /* need to take HW lock because MCP or other port might also |
| 4779 | try to handle this event */ |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 4780 | bnx2x_acquire_alr(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4781 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4782 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
| 4783 | #ifndef BNX2X_STOP_ON_ERROR |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4784 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 4785 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4786 | /* Disable HW interrupts */ |
| 4787 | bnx2x_int_disable(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4788 | /* In case of parity errors don't handle attentions so that |
| 4789 | * other function would "see" parity errors. |
| 4790 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 4791 | #else |
| 4792 | bnx2x_panic(); |
| 4793 | #endif |
| 4794 | bnx2x_release_alr(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4795 | return; |
| 4796 | } |
| 4797 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4798 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
| 4799 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); |
| 4800 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); |
| 4801 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4802 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4803 | attn.sig[4] = |
| 4804 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); |
| 4805 | else |
| 4806 | attn.sig[4] = 0; |
| 4807 | |
| 4808 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", |
| 4809 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4810 | |
| 4811 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
| 4812 | if (deasserted & (1 << index)) { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4813 | group_mask = &bp->attn_group[index]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4814 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4815 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4816 | index, |
| 4817 | group_mask->sig[0], group_mask->sig[1], |
| 4818 | group_mask->sig[2], group_mask->sig[3], |
| 4819 | group_mask->sig[4]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4820 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4821 | bnx2x_attn_int_deasserted4(bp, |
| 4822 | attn.sig[4] & group_mask->sig[4]); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4823 | bnx2x_attn_int_deasserted3(bp, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4824 | attn.sig[3] & group_mask->sig[3]); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4825 | bnx2x_attn_int_deasserted1(bp, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4826 | attn.sig[1] & group_mask->sig[1]); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4827 | bnx2x_attn_int_deasserted2(bp, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4828 | attn.sig[2] & group_mask->sig[2]); |
Eliezer Tamir | 877e9aa | 2008-02-28 11:55:53 -0800 | [diff] [blame] | 4829 | bnx2x_attn_int_deasserted0(bp, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4830 | attn.sig[0] & group_mask->sig[0]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4831 | } |
| 4832 | } |
| 4833 | |
Yitchak Gertner | 4a37fb6 | 2008-08-13 15:50:23 -0700 | [diff] [blame] | 4834 | bnx2x_release_alr(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4835 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4836 | if (bp->common.int_block == INT_BLOCK_HC) |
| 4837 | reg_addr = (HC_REG_COMMAND_REG + port*32 + |
| 4838 | COMMAND_REG_ATTN_BITS_CLR); |
| 4839 | else |
| 4840 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4841 | |
| 4842 | val = ~deasserted; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 4843 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
| 4844 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); |
Eilon Greenstein | 5c86284 | 2008-08-13 15:51:48 -0700 | [diff] [blame] | 4845 | REG_WR(bp, reg_addr, val); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4846 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4847 | if (~bp->attn_state & deasserted) |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 4848 | BNX2X_ERR("IGU ERROR\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4849 | |
| 4850 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
| 4851 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
| 4852 | |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 4853 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
| 4854 | aeu_mask = REG_RD(bp, reg_addr); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4855 | |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 4856 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", |
| 4857 | aeu_mask, deasserted); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 4858 | aeu_mask |= (deasserted & 0x3ff); |
Eilon Greenstein | 3fcaf2e | 2008-08-13 15:50:45 -0700 | [diff] [blame] | 4859 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
| 4860 | |
| 4861 | REG_WR(bp, reg_addr, aeu_mask); |
| 4862 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4863 | |
| 4864 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
| 4865 | bp->attn_state &= ~deasserted; |
| 4866 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
| 4867 | } |
| 4868 | |
| 4869 | static void bnx2x_attn_int(struct bnx2x *bp) |
| 4870 | { |
| 4871 | /* read local copy of bits */ |
Eilon Greenstein | 68d5948 | 2009-01-14 21:27:36 -0800 | [diff] [blame] | 4872 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
| 4873 | attn_bits); |
| 4874 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. |
| 4875 | attn_bits_ack); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4876 | u32 attn_state = bp->attn_state; |
| 4877 | |
| 4878 | /* look for changed bits */ |
| 4879 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; |
| 4880 | u32 deasserted = ~attn_bits & attn_ack & attn_state; |
| 4881 | |
| 4882 | DP(NETIF_MSG_HW, |
| 4883 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", |
| 4884 | attn_bits, attn_ack, asserted, deasserted); |
| 4885 | |
| 4886 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 4887 | BNX2X_ERR("BAD attention state\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4888 | |
| 4889 | /* handle bits that were raised */ |
| 4890 | if (asserted) |
| 4891 | bnx2x_attn_int_asserted(bp, asserted); |
| 4892 | |
| 4893 | if (deasserted) |
| 4894 | bnx2x_attn_int_deasserted(bp, deasserted); |
| 4895 | } |
| 4896 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4897 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
| 4898 | u16 index, u8 op, u8 update) |
| 4899 | { |
Ariel Elior | dc1ba59 | 2013-01-01 05:22:30 +0000 | [diff] [blame] | 4900 | u32 igu_addr = bp->igu_base_addr; |
| 4901 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4902 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
| 4903 | igu_addr); |
| 4904 | } |
| 4905 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4906 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4907 | { |
| 4908 | /* No memory barriers */ |
| 4909 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); |
| 4910 | mmiowb(); /* keep prod updates ordered */ |
| 4911 | } |
| 4912 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4913 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
| 4914 | union event_ring_elem *elem) |
| 4915 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4916 | u8 err = elem->message.error; |
| 4917 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4918 | if (!bp->cnic_eth_dev.starting_cid || |
Vladislav Zolotarov | c3a8ce6 | 2011-05-22 10:08:09 +0000 | [diff] [blame] | 4919 | (cid < bp->cnic_eth_dev.starting_cid && |
| 4920 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4921 | return 1; |
| 4922 | |
| 4923 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); |
| 4924 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4925 | if (unlikely(err)) { |
| 4926 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4927 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
| 4928 | cid); |
Yuval Mintz | 823e1d9 | 2013-01-14 05:11:47 +0000 | [diff] [blame] | 4929 | bnx2x_panic_dump(bp, false); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4930 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4931 | bnx2x_cnic_cfc_comp(bp, cid, err); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4932 | return 0; |
| 4933 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 4934 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4935 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4936 | { |
| 4937 | struct bnx2x_mcast_ramrod_params rparam; |
| 4938 | int rc; |
| 4939 | |
| 4940 | memset(&rparam, 0, sizeof(rparam)); |
| 4941 | |
| 4942 | rparam.mcast_obj = &bp->mcast_obj; |
| 4943 | |
| 4944 | netif_addr_lock_bh(bp->dev); |
| 4945 | |
| 4946 | /* Clear pending state for the last command */ |
| 4947 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); |
| 4948 | |
| 4949 | /* If there are pending mcast commands - send them */ |
| 4950 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { |
| 4951 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); |
| 4952 | if (rc < 0) |
| 4953 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", |
| 4954 | rc); |
| 4955 | } |
| 4956 | |
| 4957 | netif_addr_unlock_bh(bp->dev); |
| 4958 | } |
| 4959 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 4960 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
| 4961 | union event_ring_elem *elem) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4962 | { |
| 4963 | unsigned long ramrod_flags = 0; |
| 4964 | int rc = 0; |
| 4965 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; |
| 4966 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; |
| 4967 | |
| 4968 | /* Always push next commands out, don't wait here */ |
| 4969 | __set_bit(RAMROD_CONT, &ramrod_flags); |
| 4970 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 4971 | switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) |
| 4972 | >> BNX2X_SWCID_SHIFT) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4973 | case BNX2X_FILTER_MAC_PENDING: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4974 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 4975 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4976 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
| 4977 | else |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 4978 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4979 | |
| 4980 | break; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4981 | case BNX2X_FILTER_MCAST_PENDING: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 4982 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 4983 | /* This is only relevant for 57710 where multicast MACs are |
| 4984 | * configured as unicast MACs using the same ramrod. |
| 4985 | */ |
| 4986 | bnx2x_handle_mcast_eqe(bp); |
| 4987 | return; |
| 4988 | default: |
| 4989 | BNX2X_ERR("Unsupported classification command: %d\n", |
| 4990 | elem->message.data.eth_event.echo); |
| 4991 | return; |
| 4992 | } |
| 4993 | |
| 4994 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); |
| 4995 | |
| 4996 | if (rc < 0) |
| 4997 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); |
| 4998 | else if (rc > 0) |
| 4999 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5000 | } |
| 5001 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5002 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5003 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5004 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5005 | { |
| 5006 | netif_addr_lock_bh(bp->dev); |
| 5007 | |
| 5008 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); |
| 5009 | |
| 5010 | /* Send rx_mode command again if was requested */ |
| 5011 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) |
| 5012 | bnx2x_set_storm_rx_mode(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5013 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
| 5014 | &bp->sp_state)) |
| 5015 | bnx2x_set_iscsi_eth_rx_mode(bp, true); |
| 5016 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, |
| 5017 | &bp->sp_state)) |
| 5018 | bnx2x_set_iscsi_eth_rx_mode(bp, false); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5019 | |
| 5020 | netif_addr_unlock_bh(bp->dev); |
| 5021 | } |
| 5022 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5023 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5024 | union event_ring_elem *elem) |
| 5025 | { |
| 5026 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { |
| 5027 | DP(BNX2X_MSG_SP, |
| 5028 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", |
| 5029 | elem->message.data.vif_list_event.func_bit_map); |
| 5030 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, |
| 5031 | elem->message.data.vif_list_event.func_bit_map); |
| 5032 | } else if (elem->message.data.vif_list_event.echo == |
| 5033 | VIF_LIST_RULE_SET) { |
| 5034 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); |
| 5035 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); |
| 5036 | } |
| 5037 | } |
| 5038 | |
| 5039 | /* called with rtnl_lock */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5040 | static void bnx2x_after_function_update(struct bnx2x *bp) |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5041 | { |
| 5042 | int q, rc; |
| 5043 | struct bnx2x_fastpath *fp; |
| 5044 | struct bnx2x_queue_state_params queue_params = {NULL}; |
| 5045 | struct bnx2x_queue_update_params *q_update_params = |
| 5046 | &queue_params.params.update; |
| 5047 | |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 5048 | /* Send Q update command with afex vlan removal values for all Qs */ |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5049 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
| 5050 | |
| 5051 | /* set silent vlan removal values according to vlan mode */ |
| 5052 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, |
| 5053 | &q_update_params->update_flags); |
| 5054 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, |
| 5055 | &q_update_params->update_flags); |
| 5056 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); |
| 5057 | |
| 5058 | /* in access mode mark mask and value are 0 to strip all vlans */ |
| 5059 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { |
| 5060 | q_update_params->silent_removal_value = 0; |
| 5061 | q_update_params->silent_removal_mask = 0; |
| 5062 | } else { |
| 5063 | q_update_params->silent_removal_value = |
| 5064 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); |
| 5065 | q_update_params->silent_removal_mask = VLAN_VID_MASK; |
| 5066 | } |
| 5067 | |
| 5068 | for_each_eth_queue(bp, q) { |
| 5069 | /* Set the appropriate Queue object */ |
| 5070 | fp = &bp->fp[q]; |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 5071 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5072 | |
| 5073 | /* send the ramrod */ |
| 5074 | rc = bnx2x_queue_state_change(bp, &queue_params); |
| 5075 | if (rc < 0) |
| 5076 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", |
| 5077 | q); |
| 5078 | } |
| 5079 | |
Yuval Mintz | fea7564 | 2013-04-10 13:34:39 +0300 | [diff] [blame] | 5080 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 5081 | fp = &bp->fp[FCOE_IDX(bp)]; |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 5082 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5083 | |
| 5084 | /* clear pending completion bit */ |
| 5085 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); |
| 5086 | |
| 5087 | /* mark latest Q bit */ |
| 5088 | smp_mb__before_clear_bit(); |
| 5089 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); |
| 5090 | smp_mb__after_clear_bit(); |
| 5091 | |
| 5092 | /* send Q update ramrod for FCoE Q */ |
| 5093 | rc = bnx2x_queue_state_change(bp, &queue_params); |
| 5094 | if (rc < 0) |
| 5095 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", |
| 5096 | q); |
| 5097 | } else { |
| 5098 | /* If no FCoE ring - ACK MCP now */ |
| 5099 | bnx2x_link_report(bp); |
| 5100 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); |
| 5101 | } |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5102 | } |
| 5103 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5104 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5105 | struct bnx2x *bp, u32 cid) |
| 5106 | { |
Joe Perches | 94f05b0 | 2011-08-14 12:16:20 +0000 | [diff] [blame] | 5107 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5108 | |
| 5109 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 5110 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5111 | else |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 5112 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5113 | } |
| 5114 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5115 | static void bnx2x_eq_int(struct bnx2x *bp) |
| 5116 | { |
| 5117 | u16 hw_cons, sw_cons, sw_prod; |
| 5118 | union event_ring_elem *elem; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5119 | u8 echo; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5120 | u32 cid; |
| 5121 | u8 opcode; |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5122 | int rc, spqe_cnt = 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5123 | struct bnx2x_queue_sp_obj *q_obj; |
| 5124 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; |
| 5125 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5126 | |
| 5127 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); |
| 5128 | |
| 5129 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 5130 | * when we get the next-page we need to adjust so the loop |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5131 | * condition below will be met. The next element is the size of a |
| 5132 | * regular element and hence incrementing by 1 |
| 5133 | */ |
| 5134 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) |
| 5135 | hw_cons++; |
| 5136 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 5137 | /* This function may never run in parallel with itself for a |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5138 | * specific bp, thus there is no need in "paired" read memory |
| 5139 | * barrier here. |
| 5140 | */ |
| 5141 | sw_cons = bp->eq_cons; |
| 5142 | sw_prod = bp->eq_prod; |
| 5143 | |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5144 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 5145 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5146 | |
| 5147 | for (; sw_cons != hw_cons; |
| 5148 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { |
| 5149 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5150 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
| 5151 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5152 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
| 5153 | if (!rc) { |
| 5154 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", |
| 5155 | rc); |
| 5156 | goto next_spqe; |
| 5157 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5158 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 5159 | /* elem CID originates from FW; actually LE */ |
| 5160 | cid = SW_CID((__force __le32) |
| 5161 | elem->message.data.cfc_del_event.cid); |
| 5162 | opcode = elem->message.opcode; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5163 | |
| 5164 | /* handle eq element */ |
| 5165 | switch (opcode) { |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5166 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
| 5167 | DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); |
| 5168 | bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); |
| 5169 | continue; |
| 5170 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5171 | case EVENT_RING_OPCODE_STAT_QUERY: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5172 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
| 5173 | "got statistics comp event %d\n", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5174 | bp->stats_comp++); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5175 | /* nothing to do with stats comp */ |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5176 | goto next_spqe; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5177 | |
| 5178 | case EVENT_RING_OPCODE_CFC_DEL: |
| 5179 | /* handle according to cid range */ |
| 5180 | /* |
| 5181 | * we may want to verify here that the bp state is |
| 5182 | * HALTING |
| 5183 | */ |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5184 | DP(BNX2X_MSG_SP, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5185 | "got delete ramrod for MULTI[%d]\n", cid); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5186 | |
| 5187 | if (CNIC_LOADED(bp) && |
| 5188 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5189 | goto next_spqe; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5190 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5191 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
| 5192 | |
| 5193 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) |
| 5194 | break; |
| 5195 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5196 | goto next_spqe; |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 5197 | |
| 5198 | case EVENT_RING_OPCODE_STOP_TRAFFIC: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5199 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 5200 | if (f_obj->complete_cmd(bp, f_obj, |
| 5201 | BNX2X_F_CMD_TX_STOP)) |
| 5202 | break; |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 5203 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
| 5204 | goto next_spqe; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5205 | |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 5206 | case EVENT_RING_OPCODE_START_TRAFFIC: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5207 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 5208 | if (f_obj->complete_cmd(bp, f_obj, |
| 5209 | BNX2X_F_CMD_TX_START)) |
| 5210 | break; |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 5211 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
| 5212 | goto next_spqe; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5213 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5214 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5215 | echo = elem->message.data.function_update_event.echo; |
| 5216 | if (echo == SWITCH_UPDATE) { |
| 5217 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
| 5218 | "got FUNC_SWITCH_UPDATE ramrod\n"); |
| 5219 | if (f_obj->complete_cmd( |
| 5220 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) |
| 5221 | break; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5222 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5223 | } else { |
| 5224 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, |
| 5225 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); |
| 5226 | f_obj->complete_cmd(bp, f_obj, |
| 5227 | BNX2X_F_CMD_AFEX_UPDATE); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5228 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5229 | /* We will perform the Queues update from |
| 5230 | * sp_rtnl task as all Queue SP operations |
| 5231 | * should run under rtnl_lock. |
| 5232 | */ |
| 5233 | smp_mb__before_clear_bit(); |
| 5234 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, |
| 5235 | &bp->sp_rtnl_state); |
| 5236 | smp_mb__after_clear_bit(); |
| 5237 | |
| 5238 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
| 5239 | } |
| 5240 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5241 | goto next_spqe; |
| 5242 | |
| 5243 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: |
| 5244 | f_obj->complete_cmd(bp, f_obj, |
| 5245 | BNX2X_F_CMD_AFEX_VIFLISTS); |
| 5246 | bnx2x_after_afex_vif_lists(bp, elem); |
| 5247 | goto next_spqe; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5248 | case EVENT_RING_OPCODE_FUNCTION_START: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5249 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
| 5250 | "got FUNC_START ramrod\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5251 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
| 5252 | break; |
| 5253 | |
| 5254 | goto next_spqe; |
| 5255 | |
| 5256 | case EVENT_RING_OPCODE_FUNCTION_STOP: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5257 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
| 5258 | "got FUNC_STOP ramrod\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5259 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
| 5260 | break; |
| 5261 | |
| 5262 | goto next_spqe; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5263 | } |
| 5264 | |
| 5265 | switch (opcode | bp->state) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5266 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
| 5267 | BNX2X_STATE_OPEN): |
| 5268 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5269 | BNX2X_STATE_OPENING_WAIT4_PORT): |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5270 | cid = elem->message.data.eth_event.echo & |
| 5271 | BNX2X_SWCID_MASK; |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5272 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5273 | cid); |
| 5274 | rss_raw->clear_pending(rss_raw); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5275 | break; |
| 5276 | |
| 5277 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
| 5278 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5279 | case (EVENT_RING_OPCODE_SET_MAC | |
| 5280 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5281 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
| 5282 | BNX2X_STATE_OPEN): |
| 5283 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
| 5284 | BNX2X_STATE_DIAG): |
| 5285 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
| 5286 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5287 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5288 | bnx2x_handle_classification_eqe(bp, elem); |
| 5289 | break; |
| 5290 | |
| 5291 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
| 5292 | BNX2X_STATE_OPEN): |
| 5293 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
| 5294 | BNX2X_STATE_DIAG): |
| 5295 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
| 5296 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5297 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5298 | bnx2x_handle_mcast_eqe(bp); |
| 5299 | break; |
| 5300 | |
| 5301 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
| 5302 | BNX2X_STATE_OPEN): |
| 5303 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
| 5304 | BNX2X_STATE_DIAG): |
| 5305 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
| 5306 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
Vladislav Zolotarov | d6cae23 | 2011-07-24 03:54:17 +0000 | [diff] [blame] | 5307 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5308 | bnx2x_handle_rx_mode_eqe(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5309 | break; |
| 5310 | default: |
| 5311 | /* unknown event log error and continue */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5312 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
| 5313 | elem->message.opcode, bp->state); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5314 | } |
| 5315 | next_spqe: |
| 5316 | spqe_cnt++; |
| 5317 | } /* for */ |
| 5318 | |
Dmitry Kravkov | 8fe23fb | 2010-10-06 03:27:41 +0000 | [diff] [blame] | 5319 | smp_mb__before_atomic_inc(); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 5320 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5321 | |
| 5322 | bp->eq_cons = sw_cons; |
| 5323 | bp->eq_prod = sw_prod; |
| 5324 | /* Make sure that above mem writes were issued towards the memory */ |
| 5325 | smp_wmb(); |
| 5326 | |
| 5327 | /* update producer */ |
| 5328 | bnx2x_update_eq_prod(bp, bp->eq_prod); |
| 5329 | } |
| 5330 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5331 | static void bnx2x_sp_task(struct work_struct *work) |
| 5332 | { |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 5333 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5334 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5335 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5336 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 5337 | /* make sure the atomic interrupt_occurred has been written */ |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5338 | smp_rmb(); |
| 5339 | if (atomic_read(&bp->interrupt_occurred)) { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5340 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5341 | /* what work needs to be performed? */ |
| 5342 | u16 status = bnx2x_update_dsb_idx(bp); |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 5343 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5344 | DP(BNX2X_MSG_SP, "status %x\n", status); |
| 5345 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); |
| 5346 | atomic_set(&bp->interrupt_occurred, 0); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5347 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5348 | /* HW attentions */ |
| 5349 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
| 5350 | bnx2x_attn_int(bp); |
| 5351 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
Vladislav Zolotarov | 019dbb4 | 2011-07-19 01:43:25 +0000 | [diff] [blame] | 5352 | } |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5353 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5354 | /* SP events: STAT_QUERY and others */ |
| 5355 | if (status & BNX2X_DEF_SB_IDX) { |
| 5356 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5357 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5358 | if (FCOE_INIT(bp) && |
| 5359 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
| 5360 | /* Prevent local bottom-halves from running as |
| 5361 | * we are going to change the local NAPI list. |
| 5362 | */ |
| 5363 | local_bh_disable(); |
| 5364 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
| 5365 | local_bh_enable(); |
| 5366 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5367 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5368 | /* Handle EQ completions */ |
| 5369 | bnx2x_eq_int(bp); |
| 5370 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, |
| 5371 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); |
| 5372 | |
| 5373 | status &= ~BNX2X_DEF_SB_IDX; |
| 5374 | } |
| 5375 | |
| 5376 | /* if status is non zero then perhaps something went wrong */ |
| 5377 | if (unlikely(status)) |
| 5378 | DP(BNX2X_MSG_SP, |
| 5379 | "got an unknown interrupt! (status 0x%x)\n", status); |
| 5380 | |
| 5381 | /* ack status block only if something was actually handled */ |
| 5382 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
| 5383 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 5384 | } |
| 5385 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5386 | /* must be called after the EQ processing (since eq leads to sriov |
| 5387 | * ramrod completion flows). |
| 5388 | * This flow may have been scheduled by the arrival of a ramrod |
| 5389 | * completion, or by the sriov code rescheduling itself. |
| 5390 | */ |
| 5391 | bnx2x_iov_sp_task(bp); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 5392 | |
| 5393 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ |
| 5394 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, |
| 5395 | &bp->sp_state)) { |
| 5396 | bnx2x_link_report(bp); |
| 5397 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); |
| 5398 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5399 | } |
| 5400 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 5401 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5402 | { |
| 5403 | struct net_device *dev = dev_instance; |
| 5404 | struct bnx2x *bp = netdev_priv(dev); |
| 5405 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5406 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
| 5407 | IGU_INT_DISABLE, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5408 | |
| 5409 | #ifdef BNX2X_STOP_ON_ERROR |
| 5410 | if (unlikely(bp->panic)) |
| 5411 | return IRQ_HANDLED; |
| 5412 | #endif |
| 5413 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5414 | if (CNIC_LOADED(bp)) { |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 5415 | struct cnic_ops *c_ops; |
| 5416 | |
| 5417 | rcu_read_lock(); |
| 5418 | c_ops = rcu_dereference(bp->cnic_ops); |
| 5419 | if (c_ops) |
| 5420 | c_ops->cnic_handler(bp->cnic_data, NULL); |
| 5421 | rcu_read_unlock(); |
| 5422 | } |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 5423 | |
Ariel Elior | fd1fc79 | 2013-01-01 05:22:33 +0000 | [diff] [blame] | 5424 | /* schedule sp task to perform default status block work, ack |
| 5425 | * attentions and enable interrupts. |
| 5426 | */ |
| 5427 | bnx2x_schedule_sp_task(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5428 | |
| 5429 | return IRQ_HANDLED; |
| 5430 | } |
| 5431 | |
| 5432 | /* end of slow path */ |
| 5433 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5434 | void bnx2x_drv_pulse(struct bnx2x *bp) |
| 5435 | { |
| 5436 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, |
| 5437 | bp->fw_drv_pulse_wr_seq); |
| 5438 | } |
| 5439 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5440 | static void bnx2x_timer(unsigned long data) |
| 5441 | { |
| 5442 | struct bnx2x *bp = (struct bnx2x *) data; |
| 5443 | |
| 5444 | if (!netif_running(bp->dev)) |
| 5445 | return; |
| 5446 | |
Ariel Elior | 67c431a | 2013-01-01 05:22:36 +0000 | [diff] [blame] | 5447 | if (IS_PF(bp) && |
| 5448 | !BP_NOMCP(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5449 | int mb_idx = BP_FW_MB_IDX(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5450 | u32 drv_pulse; |
| 5451 | u32 mcp_pulse; |
| 5452 | |
| 5453 | ++bp->fw_drv_pulse_wr_seq; |
| 5454 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; |
| 5455 | /* TBD - add SYSTEM_TIME */ |
| 5456 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5457 | bnx2x_drv_pulse(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5458 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5459 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5460 | MCP_PULSE_SEQ_MASK); |
| 5461 | /* The delta between driver pulse and mcp response |
| 5462 | * should be 1 (before mcp response) or 0 (after mcp response) |
| 5463 | */ |
| 5464 | if ((drv_pulse != mcp_pulse) && |
| 5465 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { |
| 5466 | /* someone lost a heartbeat... */ |
| 5467 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", |
| 5468 | drv_pulse, mcp_pulse); |
| 5469 | } |
| 5470 | } |
| 5471 | |
Eilon Greenstein | f34d28e | 2009-10-15 00:18:08 -0700 | [diff] [blame] | 5472 | if (bp->state == BNX2X_STATE_OPEN) |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 5473 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5474 | |
Ariel Elior | abc5a02 | 2013-01-01 05:22:43 +0000 | [diff] [blame] | 5475 | /* sample pf vf bulletin board for new posts from pf */ |
Yuval Mintz | 37173488 | 2013-06-24 11:04:10 +0300 | [diff] [blame] | 5476 | if (IS_VF(bp)) |
| 5477 | bnx2x_timer_sriov(bp); |
Ariel Elior | 78c3bcc | 2013-06-20 17:39:08 +0300 | [diff] [blame] | 5478 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5479 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
| 5480 | } |
| 5481 | |
| 5482 | /* end of Statistics */ |
| 5483 | |
| 5484 | /* nic init */ |
| 5485 | |
| 5486 | /* |
| 5487 | * nic init service functions |
| 5488 | */ |
| 5489 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5490 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5491 | { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5492 | u32 i; |
| 5493 | if (!(len%4) && !(addr%4)) |
| 5494 | for (i = 0; i < len; i += 4) |
| 5495 | REG_WR(bp, addr + i, fill); |
| 5496 | else |
| 5497 | for (i = 0; i < len; i++) |
| 5498 | REG_WR8(bp, addr + i, fill); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5499 | } |
| 5500 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5501 | /* helper: writes FP SP data to FW - data_size in dwords */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5502 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
| 5503 | int fw_sb_id, |
| 5504 | u32 *sb_data_p, |
| 5505 | u32 data_size) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5506 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5507 | int index; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5508 | for (index = 0; index < data_size; index++) |
| 5509 | REG_WR(bp, BAR_CSTRORM_INTMEM + |
| 5510 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + |
| 5511 | sizeof(u32)*index, |
| 5512 | *(sb_data_p + index)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5513 | } |
| 5514 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5515 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5516 | { |
| 5517 | u32 *sb_data_p; |
| 5518 | u32 data_size = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5519 | struct hc_status_block_data_e2 sb_data_e2; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5520 | struct hc_status_block_data_e1x sb_data_e1x; |
| 5521 | |
| 5522 | /* disable the function first */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5523 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5524 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5525 | sb_data_e2.common.state = SB_DISABLED; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5526 | sb_data_e2.common.p_func.vf_valid = false; |
| 5527 | sb_data_p = (u32 *)&sb_data_e2; |
| 5528 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); |
| 5529 | } else { |
| 5530 | memset(&sb_data_e1x, 0, |
| 5531 | sizeof(struct hc_status_block_data_e1x)); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5532 | sb_data_e1x.common.state = SB_DISABLED; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5533 | sb_data_e1x.common.p_func.vf_valid = false; |
| 5534 | sb_data_p = (u32 *)&sb_data_e1x; |
| 5535 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); |
| 5536 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5537 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
| 5538 | |
| 5539 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
| 5540 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, |
| 5541 | CSTORM_STATUS_BLOCK_SIZE); |
| 5542 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
| 5543 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, |
| 5544 | CSTORM_SYNC_BLOCK_SIZE); |
| 5545 | } |
| 5546 | |
| 5547 | /* helper: writes SP SB data to FW */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5548 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5549 | struct hc_sp_status_block_data *sp_sb_data) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5550 | { |
| 5551 | int func = BP_FUNC(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5552 | int i; |
| 5553 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) |
| 5554 | REG_WR(bp, BAR_CSTRORM_INTMEM + |
| 5555 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + |
| 5556 | i*sizeof(u32), |
| 5557 | *((u32 *)sp_sb_data + i)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5558 | } |
| 5559 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5560 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5561 | { |
| 5562 | int func = BP_FUNC(bp); |
| 5563 | struct hc_sp_status_block_data sp_sb_data; |
| 5564 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); |
| 5565 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5566 | sp_sb_data.state = SB_DISABLED; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5567 | sp_sb_data.p_func.vf_valid = false; |
| 5568 | |
| 5569 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
| 5570 | |
| 5571 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
| 5572 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, |
| 5573 | CSTORM_SP_STATUS_BLOCK_SIZE); |
| 5574 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
| 5575 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, |
| 5576 | CSTORM_SP_SYNC_BLOCK_SIZE); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5577 | } |
| 5578 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5579 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5580 | int igu_sb_id, int igu_seg_id) |
| 5581 | { |
| 5582 | hc_sm->igu_sb_id = igu_sb_id; |
| 5583 | hc_sm->igu_seg_id = igu_seg_id; |
| 5584 | hc_sm->timer_value = 0xFF; |
| 5585 | hc_sm->time_to_expire = 0xFFFFFFFF; |
| 5586 | } |
| 5587 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 5588 | /* allocates state machine ids. */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 5589 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 5590 | { |
| 5591 | /* zero out state machine indices */ |
| 5592 | /* rx indices */ |
| 5593 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; |
| 5594 | |
| 5595 | /* tx indices */ |
| 5596 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; |
| 5597 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; |
| 5598 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; |
| 5599 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; |
| 5600 | |
| 5601 | /* map indices */ |
| 5602 | /* rx indices */ |
| 5603 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= |
| 5604 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; |
| 5605 | |
| 5606 | /* tx indices */ |
| 5607 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= |
| 5608 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; |
| 5609 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= |
| 5610 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; |
| 5611 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= |
| 5612 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; |
| 5613 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= |
| 5614 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; |
| 5615 | } |
| 5616 | |
Ariel Elior | b93288d | 2013-01-01 05:22:35 +0000 | [diff] [blame] | 5617 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5618 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
| 5619 | { |
| 5620 | int igu_seg_id; |
| 5621 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5622 | struct hc_status_block_data_e2 sb_data_e2; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5623 | struct hc_status_block_data_e1x sb_data_e1x; |
| 5624 | struct hc_status_block_sm *hc_sm_p; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5625 | int data_size; |
| 5626 | u32 *sb_data_p; |
| 5627 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5628 | if (CHIP_INT_MODE_IS_BC(bp)) |
| 5629 | igu_seg_id = HC_SEG_ACCESS_NORM; |
| 5630 | else |
| 5631 | igu_seg_id = IGU_SEG_ACCESS_NORM; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5632 | |
| 5633 | bnx2x_zero_fp_sb(bp, fw_sb_id); |
| 5634 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5635 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5636 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5637 | sb_data_e2.common.state = SB_ENABLED; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5638 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
| 5639 | sb_data_e2.common.p_func.vf_id = vfid; |
| 5640 | sb_data_e2.common.p_func.vf_valid = vf_valid; |
| 5641 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); |
| 5642 | sb_data_e2.common.same_igu_sb_1b = true; |
| 5643 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); |
| 5644 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); |
| 5645 | hc_sm_p = sb_data_e2.common.state_machine; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5646 | sb_data_p = (u32 *)&sb_data_e2; |
| 5647 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 5648 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5649 | } else { |
| 5650 | memset(&sb_data_e1x, 0, |
| 5651 | sizeof(struct hc_status_block_data_e1x)); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5652 | sb_data_e1x.common.state = SB_ENABLED; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5653 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
| 5654 | sb_data_e1x.common.p_func.vf_id = 0xff; |
| 5655 | sb_data_e1x.common.p_func.vf_valid = false; |
| 5656 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); |
| 5657 | sb_data_e1x.common.same_igu_sb_1b = true; |
| 5658 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); |
| 5659 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); |
| 5660 | hc_sm_p = sb_data_e1x.common.state_machine; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5661 | sb_data_p = (u32 *)&sb_data_e1x; |
| 5662 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 5663 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5664 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5665 | |
| 5666 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], |
| 5667 | igu_sb_id, igu_seg_id); |
| 5668 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], |
| 5669 | igu_sb_id, igu_seg_id); |
| 5670 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 5671 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5672 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 5673 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5674 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
| 5675 | } |
| 5676 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5677 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5678 | u16 tx_usec, u16 rx_usec) |
| 5679 | { |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 5680 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5681 | false, rx_usec); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 5682 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
| 5683 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, |
| 5684 | tx_usec); |
| 5685 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
| 5686 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, |
| 5687 | tx_usec); |
| 5688 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
| 5689 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, |
| 5690 | tx_usec); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5691 | } |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5692 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5693 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
| 5694 | { |
| 5695 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
| 5696 | dma_addr_t mapping = bp->def_status_blk_mapping; |
| 5697 | int igu_sp_sb_index; |
| 5698 | int igu_seg_id; |
| 5699 | int port = BP_PORT(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5700 | int func = BP_FUNC(bp); |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 5701 | int reg_offset, reg_offset_en5; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5702 | u64 section; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5703 | int index; |
| 5704 | struct hc_sp_status_block_data sp_sb_data; |
| 5705 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); |
| 5706 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5707 | if (CHIP_INT_MODE_IS_BC(bp)) { |
| 5708 | igu_sp_sb_index = DEF_SB_IGU_ID; |
| 5709 | igu_seg_id = HC_SEG_ACCESS_DEF; |
| 5710 | } else { |
| 5711 | igu_sp_sb_index = bp->igu_dsb_id; |
| 5712 | igu_seg_id = IGU_SEG_ACCESS_DEF; |
| 5713 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5714 | |
| 5715 | /* ATTN */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5716 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5717 | atten_status_block); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5718 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5719 | |
Eliezer Tamir | 49d6677 | 2008-02-28 11:53:13 -0800 | [diff] [blame] | 5720 | bp->attn_state = 0; |
| 5721 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5722 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
| 5723 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 5724 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
| 5725 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 5726 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5727 | int sindex; |
| 5728 | /* take care of sig[0]..sig[4] */ |
| 5729 | for (sindex = 0; sindex < 4; sindex++) |
| 5730 | bp->attn_group[index].sig[sindex] = |
| 5731 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5732 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5733 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5734 | /* |
| 5735 | * enable5 is separate from the rest of the registers, |
| 5736 | * and therefore the address skip is 4 |
| 5737 | * and not 16 between the different groups |
| 5738 | */ |
| 5739 | bp->attn_group[index].sig[4] = REG_RD(bp, |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 5740 | reg_offset_en5 + 0x4*index); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5741 | else |
| 5742 | bp->attn_group[index].sig[4] = 0; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5743 | } |
| 5744 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5745 | if (bp->common.int_block == INT_BLOCK_HC) { |
| 5746 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : |
| 5747 | HC_REG_ATTN_MSG0_ADDR_L); |
| 5748 | |
| 5749 | REG_WR(bp, reg_offset, U64_LO(section)); |
| 5750 | REG_WR(bp, reg_offset + 4, U64_HI(section)); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5751 | } else if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5752 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
| 5753 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); |
| 5754 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5755 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5756 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
| 5757 | sp_sb); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5758 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5759 | bnx2x_zero_sp_sb(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5760 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 5761 | /* PCI guarantees endianity of regpairs */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5762 | sp_sb_data.state = SB_ENABLED; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5763 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
| 5764 | sp_sb_data.host_sb_addr.hi = U64_HI(section); |
| 5765 | sp_sb_data.igu_sb_id = igu_sp_sb_index; |
| 5766 | sp_sb_data.igu_seg_id = igu_seg_id; |
| 5767 | sp_sb_data.p_func.pf_id = func; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5768 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5769 | sp_sb_data.p_func.vf_id = 0xff; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5770 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5771 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5772 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5773 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5774 | } |
| 5775 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 5776 | void bnx2x_update_coalesce(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5777 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5778 | int i; |
| 5779 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 5780 | for_each_eth_queue(bp, i) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5781 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
Ariel Elior | 423cfa7e | 2011-03-14 13:43:22 -0700 | [diff] [blame] | 5782 | bp->tx_ticks, bp->rx_ticks); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5783 | } |
| 5784 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5785 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
| 5786 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5787 | spin_lock_init(&bp->spq_lock); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 5788 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5789 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5790 | bp->spq_prod_idx = 0; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5791 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
| 5792 | bp->spq_prod_bd = bp->spq; |
| 5793 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5794 | } |
| 5795 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5796 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5797 | { |
| 5798 | int i; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5799 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
| 5800 | union event_ring_elem *elem = |
| 5801 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5802 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5803 | elem->next_page.addr.hi = |
| 5804 | cpu_to_le32(U64_HI(bp->eq_mapping + |
| 5805 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); |
| 5806 | elem->next_page.addr.lo = |
| 5807 | cpu_to_le32(U64_LO(bp->eq_mapping + |
| 5808 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5809 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5810 | bp->eq_cons = 0; |
| 5811 | bp->eq_prod = NUM_EQ_DESC; |
| 5812 | bp->eq_cons_sb = BNX2X_EQ_INDEX; |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 5813 | /* we want a warning message before it gets wrought... */ |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 5814 | atomic_set(&bp->eq_spq_left, |
| 5815 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5816 | } |
| 5817 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5818 | /* called with netif_addr_lock_bh() */ |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5819 | int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
| 5820 | unsigned long rx_mode_flags, |
| 5821 | unsigned long rx_accept_flags, |
| 5822 | unsigned long tx_accept_flags, |
| 5823 | unsigned long ramrod_flags) |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 5824 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5825 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
| 5826 | int rc; |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 5827 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5828 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 5829 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5830 | /* Prepare ramrod parameters */ |
| 5831 | ramrod_param.cid = 0; |
| 5832 | ramrod_param.cl_id = cl_id; |
| 5833 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; |
| 5834 | ramrod_param.func_id = BP_FUNC(bp); |
| 5835 | |
| 5836 | ramrod_param.pstate = &bp->sp_state; |
| 5837 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; |
| 5838 | |
| 5839 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
| 5840 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); |
| 5841 | |
| 5842 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); |
| 5843 | |
| 5844 | ramrod_param.ramrod_flags = ramrod_flags; |
| 5845 | ramrod_param.rx_mode_flags = rx_mode_flags; |
| 5846 | |
| 5847 | ramrod_param.rx_accept_flags = rx_accept_flags; |
| 5848 | ramrod_param.tx_accept_flags = tx_accept_flags; |
| 5849 | |
| 5850 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); |
| 5851 | if (rc < 0) { |
| 5852 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5853 | return rc; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5854 | } |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5855 | |
| 5856 | return 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5857 | } |
| 5858 | |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 5859 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
| 5860 | unsigned long *rx_accept_flags, |
| 5861 | unsigned long *tx_accept_flags) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5862 | { |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5863 | /* Clear the flags first */ |
| 5864 | *rx_accept_flags = 0; |
| 5865 | *tx_accept_flags = 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5866 | |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5867 | switch (rx_mode) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5868 | case BNX2X_RX_MODE_NONE: |
| 5869 | /* |
| 5870 | * 'drop all' supersedes any accept flags that may have been |
| 5871 | * passed to the function. |
| 5872 | */ |
| 5873 | break; |
| 5874 | case BNX2X_RX_MODE_NORMAL: |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5875 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
| 5876 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); |
| 5877 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5878 | |
| 5879 | /* internal switching mode */ |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5880 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
| 5881 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); |
| 5882 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5883 | |
| 5884 | break; |
| 5885 | case BNX2X_RX_MODE_ALLMULTI: |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5886 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
| 5887 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); |
| 5888 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5889 | |
| 5890 | /* internal switching mode */ |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5891 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
| 5892 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
| 5893 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5894 | |
| 5895 | break; |
| 5896 | case BNX2X_RX_MODE_PROMISC: |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 5897 | /* According to definition of SI mode, iface in promisc mode |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5898 | * should receive matched and unmatched (in resolution of port) |
| 5899 | * unicast packets. |
| 5900 | */ |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5901 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
| 5902 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
| 5903 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); |
| 5904 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5905 | |
| 5906 | /* internal switching mode */ |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5907 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
| 5908 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5909 | |
| 5910 | if (IS_MF_SI(bp)) |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5911 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5912 | else |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5913 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5914 | |
| 5915 | break; |
| 5916 | default: |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5917 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
| 5918 | return -EINVAL; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5919 | } |
| 5920 | |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5921 | /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5922 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5923 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
| 5924 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5925 | } |
| 5926 | |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5927 | return 0; |
| 5928 | } |
| 5929 | |
| 5930 | /* called with netif_addr_lock_bh() */ |
| 5931 | int bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
| 5932 | { |
| 5933 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
| 5934 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; |
| 5935 | int rc; |
| 5936 | |
| 5937 | if (!NO_FCOE(bp)) |
| 5938 | /* Configure rx_mode of FCoE Queue */ |
| 5939 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); |
| 5940 | |
| 5941 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, |
| 5942 | &tx_accept_flags); |
| 5943 | if (rc) |
| 5944 | return rc; |
| 5945 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5946 | __set_bit(RAMROD_RX, &ramrod_flags); |
| 5947 | __set_bit(RAMROD_TX, &ramrod_flags); |
| 5948 | |
Yuval Mintz | 924d75a | 2013-01-23 03:21:44 +0000 | [diff] [blame] | 5949 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
| 5950 | rx_accept_flags, tx_accept_flags, |
| 5951 | ramrod_flags); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 5952 | } |
| 5953 | |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5954 | static void bnx2x_init_internal_common(struct bnx2x *bp) |
| 5955 | { |
| 5956 | int i; |
| 5957 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 5958 | if (IS_MF_SI(bp)) |
| 5959 | /* |
| 5960 | * In switch independent mode, the TSTORM needs to accept |
| 5961 | * packets that failed classification, since approximate match |
| 5962 | * mac addresses aren't written to NIG LLH |
| 5963 | */ |
| 5964 | REG_WR8(bp, BAR_TSTRORM_INTMEM + |
| 5965 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5966 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
| 5967 | REG_WR8(bp, BAR_TSTRORM_INTMEM + |
| 5968 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 5969 | |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5970 | /* Zero this manually as its initialization is |
| 5971 | currently missing in the initTool */ |
| 5972 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) |
| 5973 | REG_WR(bp, BAR_USTRORM_INTMEM + |
| 5974 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5975 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5976 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
| 5977 | CHIP_INT_MODE_IS_BC(bp) ? |
| 5978 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); |
| 5979 | } |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5980 | } |
| 5981 | |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5982 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
| 5983 | { |
| 5984 | switch (load_code) { |
| 5985 | case FW_MSG_CODE_DRV_LOAD_COMMON: |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 5986 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5987 | bnx2x_init_internal_common(bp); |
| 5988 | /* no break */ |
| 5989 | |
| 5990 | case FW_MSG_CODE_DRV_LOAD_PORT: |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 5991 | /* nothing to do */ |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5992 | /* no break */ |
| 5993 | |
| 5994 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 5995 | /* internal memory per function is |
| 5996 | initialized inside bnx2x_pf_init */ |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 5997 | break; |
| 5998 | |
| 5999 | default: |
| 6000 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); |
| 6001 | break; |
| 6002 | } |
| 6003 | } |
| 6004 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6005 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
| 6006 | { |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6007 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6008 | } |
| 6009 | |
| 6010 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
| 6011 | { |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6012 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6013 | } |
| 6014 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6015 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6016 | { |
| 6017 | if (CHIP_IS_E1x(fp->bp)) |
| 6018 | return BP_L_ID(fp->bp) + fp->index; |
| 6019 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ |
| 6020 | return bnx2x_fp_igu_sb_id(fp); |
| 6021 | } |
| 6022 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6023 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6024 | { |
| 6025 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6026 | u8 cos; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6027 | unsigned long q_type = 0; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6028 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
Dmitry Kravkov | f233caf | 2011-11-13 04:34:22 +0000 | [diff] [blame] | 6029 | fp->rx_queue = fp_idx; |
Dmitry Kravkov | b3b83c3 | 2011-05-04 23:50:33 +0000 | [diff] [blame] | 6030 | fp->cid = fp_idx; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6031 | fp->cl_id = bnx2x_fp_cl_id(fp); |
| 6032 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); |
| 6033 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6034 | /* qZone id equals to FW (per path) client id */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6035 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
| 6036 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6037 | /* init shortcut */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6038 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 6039 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 6040 | /* Setup SB indices */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6041 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6042 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6043 | /* Configure Queue State object */ |
| 6044 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); |
| 6045 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6046 | |
| 6047 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); |
| 6048 | |
| 6049 | /* init tx data */ |
| 6050 | for_each_cos_in_tx_queue(fp, cos) { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 6051 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
| 6052 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), |
| 6053 | FP_COS_TO_TXQ(fp, cos, bp), |
| 6054 | BNX2X_TX_SB_INDEX_BASE + cos, fp); |
| 6055 | cids[cos] = fp->txdata_ptr[cos]->cid; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6056 | } |
| 6057 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 6058 | /* nothing more for vf to do here */ |
| 6059 | if (IS_VF(bp)) |
| 6060 | return; |
| 6061 | |
| 6062 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, |
| 6063 | fp->fw_sb_id, fp->igu_sb_id); |
| 6064 | bnx2x_update_fpsb_idx(fp); |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 6065 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
| 6066 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6067 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6068 | |
| 6069 | /** |
| 6070 | * Configure classification DBs: Always enable Tx switching |
| 6071 | */ |
| 6072 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); |
| 6073 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 6074 | DP(NETIF_MSG_IFUP, |
| 6075 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", |
| 6076 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
| 6077 | fp->igu_sb_id); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6078 | } |
| 6079 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6080 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
| 6081 | { |
| 6082 | int i; |
| 6083 | |
| 6084 | for (i = 1; i <= NUM_TX_RINGS; i++) { |
| 6085 | struct eth_tx_next_bd *tx_next_bd = |
| 6086 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; |
| 6087 | |
| 6088 | tx_next_bd->addr_hi = |
| 6089 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + |
| 6090 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); |
| 6091 | tx_next_bd->addr_lo = |
| 6092 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + |
| 6093 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); |
| 6094 | } |
| 6095 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 6096 | *txdata->tx_cons_sb = cpu_to_le16(0); |
| 6097 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6098 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
| 6099 | txdata->tx_db.data.zero_fill1 = 0; |
| 6100 | txdata->tx_db.data.prod = 0; |
| 6101 | |
| 6102 | txdata->tx_pkt_prod = 0; |
| 6103 | txdata->tx_pkt_cons = 0; |
| 6104 | txdata->tx_bd_prod = 0; |
| 6105 | txdata->tx_bd_cons = 0; |
| 6106 | txdata->tx_pkt = 0; |
| 6107 | } |
| 6108 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6109 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
| 6110 | { |
| 6111 | int i; |
| 6112 | |
| 6113 | for_each_tx_queue_cnic(bp, i) |
| 6114 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); |
| 6115 | } |
Yuval Mintz | d76a611 | 2013-06-02 00:06:17 +0000 | [diff] [blame] | 6116 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6117 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
| 6118 | { |
| 6119 | int i; |
| 6120 | u8 cos; |
| 6121 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6122 | for_each_eth_queue(bp, i) |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6123 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 6124 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6125 | } |
| 6126 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6127 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
| 6128 | { |
| 6129 | if (!NO_FCOE(bp)) |
| 6130 | bnx2x_init_fcoe_fp(bp); |
| 6131 | |
| 6132 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, |
| 6133 | BNX2X_VF_ID_INVALID, false, |
| 6134 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
| 6135 | |
| 6136 | /* ensure status block indices were read */ |
| 6137 | rmb(); |
| 6138 | bnx2x_init_rx_rings_cnic(bp); |
| 6139 | bnx2x_init_tx_rings_cnic(bp); |
| 6140 | |
| 6141 | /* flush all */ |
| 6142 | mb(); |
| 6143 | mmiowb(); |
| 6144 | } |
| 6145 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6146 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6147 | { |
| 6148 | int i; |
| 6149 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6150 | /* Setup NIC internals and enable interrupts */ |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 6151 | for_each_eth_queue(bp, i) |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 6152 | bnx2x_init_eth_fp(bp, i); |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 6153 | |
| 6154 | /* ensure status block indices were read */ |
| 6155 | rmb(); |
| 6156 | bnx2x_init_rx_rings(bp); |
| 6157 | bnx2x_init_tx_rings(bp); |
| 6158 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6159 | if (IS_PF(bp)) { |
| 6160 | /* Initialize MOD_ABS interrupts */ |
| 6161 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, |
| 6162 | bp->common.shmem_base, |
| 6163 | bp->common.shmem2_base, BP_PORT(bp)); |
Eilon Greenstein | 1611978 | 2009-03-02 07:59:27 +0000 | [diff] [blame] | 6164 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6165 | /* initialize the default status block and sp ring */ |
| 6166 | bnx2x_init_def_sb(bp); |
| 6167 | bnx2x_update_dsb_idx(bp); |
| 6168 | bnx2x_init_sp_ring(bp); |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 6169 | } else { |
| 6170 | bnx2x_memset_stats(bp); |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6171 | } |
| 6172 | } |
Eilon Greenstein | 1611978 | 2009-03-02 07:59:27 +0000 | [diff] [blame] | 6173 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6174 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
| 6175 | { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6176 | bnx2x_init_eq_ring(bp); |
Eilon Greenstein | 471de71 | 2008-08-13 15:49:35 -0700 | [diff] [blame] | 6177 | bnx2x_init_internal(bp, load_code); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6178 | bnx2x_pf_init(bp); |
Eilon Greenstein | 0ef0045 | 2009-01-14 21:31:08 -0800 | [diff] [blame] | 6179 | bnx2x_stats_init(bp); |
| 6180 | |
Eilon Greenstein | 0ef0045 | 2009-01-14 21:31:08 -0800 | [diff] [blame] | 6181 | /* flush all before enabling interrupts */ |
| 6182 | mb(); |
| 6183 | mmiowb(); |
| 6184 | |
Eliezer Tamir | 615f8fd | 2008-02-28 11:54:54 -0800 | [diff] [blame] | 6185 | bnx2x_int_enable(bp); |
Eilon Greenstein | eb8da20 | 2009-07-21 05:47:30 +0000 | [diff] [blame] | 6186 | |
| 6187 | /* Check for SPIO5 */ |
| 6188 | bnx2x_attn_int_deasserted0(bp, |
| 6189 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & |
| 6190 | AEU_INPUTS_ATTN_BITS_SPIO5); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6191 | } |
| 6192 | |
Yuval Mintz | ecf01c2 | 2013-04-22 02:53:03 +0000 | [diff] [blame] | 6193 | /* gzip service functions */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6194 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
| 6195 | { |
FUJITA Tomonori | 1a98314 | 2010-04-04 01:51:03 +0000 | [diff] [blame] | 6196 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
| 6197 | &bp->gunzip_mapping, GFP_KERNEL); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6198 | if (bp->gunzip_buf == NULL) |
| 6199 | goto gunzip_nomem1; |
| 6200 | |
| 6201 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); |
| 6202 | if (bp->strm == NULL) |
| 6203 | goto gunzip_nomem2; |
| 6204 | |
David S. Miller | 7ab24bf | 2011-06-29 05:48:41 -0700 | [diff] [blame] | 6205 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6206 | if (bp->strm->workspace == NULL) |
| 6207 | goto gunzip_nomem3; |
| 6208 | |
| 6209 | return 0; |
| 6210 | |
| 6211 | gunzip_nomem3: |
| 6212 | kfree(bp->strm); |
| 6213 | bp->strm = NULL; |
| 6214 | |
| 6215 | gunzip_nomem2: |
FUJITA Tomonori | 1a98314 | 2010-04-04 01:51:03 +0000 | [diff] [blame] | 6216 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
| 6217 | bp->gunzip_mapping); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6218 | bp->gunzip_buf = NULL; |
| 6219 | |
| 6220 | gunzip_nomem1: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 6221 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6222 | return -ENOMEM; |
| 6223 | } |
| 6224 | |
| 6225 | static void bnx2x_gunzip_end(struct bnx2x *bp) |
| 6226 | { |
Dmitry Kravkov | b3b83c3 | 2011-05-04 23:50:33 +0000 | [diff] [blame] | 6227 | if (bp->strm) { |
David S. Miller | 7ab24bf | 2011-06-29 05:48:41 -0700 | [diff] [blame] | 6228 | vfree(bp->strm->workspace); |
Dmitry Kravkov | b3b83c3 | 2011-05-04 23:50:33 +0000 | [diff] [blame] | 6229 | kfree(bp->strm); |
| 6230 | bp->strm = NULL; |
| 6231 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6232 | |
| 6233 | if (bp->gunzip_buf) { |
FUJITA Tomonori | 1a98314 | 2010-04-04 01:51:03 +0000 | [diff] [blame] | 6234 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
| 6235 | bp->gunzip_mapping); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6236 | bp->gunzip_buf = NULL; |
| 6237 | } |
| 6238 | } |
| 6239 | |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 6240 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6241 | { |
| 6242 | int n, rc; |
| 6243 | |
| 6244 | /* check gzip header */ |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 6245 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
| 6246 | BNX2X_ERR("Bad gzip header\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6247 | return -EINVAL; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 6248 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6249 | |
| 6250 | n = 10; |
| 6251 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6252 | #define FNAME 0x8 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6253 | |
| 6254 | if (zbuf[3] & FNAME) |
| 6255 | while ((zbuf[n++] != 0) && (n < len)); |
| 6256 | |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 6257 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6258 | bp->strm->avail_in = len - n; |
| 6259 | bp->strm->next_out = bp->gunzip_buf; |
| 6260 | bp->strm->avail_out = FW_BUF_SIZE; |
| 6261 | |
| 6262 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); |
| 6263 | if (rc != Z_OK) |
| 6264 | return rc; |
| 6265 | |
| 6266 | rc = zlib_inflate(bp->strm, Z_FINISH); |
| 6267 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 6268 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
| 6269 | bp->strm->msg); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6270 | |
| 6271 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); |
| 6272 | if (bp->gunzip_outlen & 0x3) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 6273 | netdev_err(bp->dev, |
| 6274 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 6275 | bp->gunzip_outlen); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6276 | bp->gunzip_outlen >>= 2; |
| 6277 | |
| 6278 | zlib_inflateEnd(bp->strm); |
| 6279 | |
| 6280 | if (rc == Z_STREAM_END) |
| 6281 | return 0; |
| 6282 | |
| 6283 | return rc; |
| 6284 | } |
| 6285 | |
| 6286 | /* nic load/unload */ |
| 6287 | |
| 6288 | /* |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6289 | * General service functions |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6290 | */ |
| 6291 | |
| 6292 | /* send a NIG loopback debug packet */ |
| 6293 | static void bnx2x_lb_pckt(struct bnx2x *bp) |
| 6294 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6295 | u32 wb_write[3]; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6296 | |
| 6297 | /* Ethernet source and destination addresses */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6298 | wb_write[0] = 0x55555555; |
| 6299 | wb_write[1] = 0x55555555; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6300 | wb_write[2] = 0x20; /* SOP */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6301 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6302 | |
| 6303 | /* NON-IP protocol */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6304 | wb_write[0] = 0x09000000; |
| 6305 | wb_write[1] = 0x55555555; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6306 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6307 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6308 | } |
| 6309 | |
| 6310 | /* some of the internal memories |
| 6311 | * are not directly readable from the driver |
| 6312 | * to test them we send debug packets |
| 6313 | */ |
| 6314 | static int bnx2x_int_mem_test(struct bnx2x *bp) |
| 6315 | { |
| 6316 | int factor; |
| 6317 | int count, i; |
| 6318 | u32 val = 0; |
| 6319 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 6320 | if (CHIP_REV_IS_FPGA(bp)) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6321 | factor = 120; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 6322 | else if (CHIP_REV_IS_EMUL(bp)) |
| 6323 | factor = 200; |
| 6324 | else |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6325 | factor = 1; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6326 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6327 | /* Disable inputs of parser neighbor blocks */ |
| 6328 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); |
| 6329 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); |
| 6330 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 6331 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6332 | |
| 6333 | /* Write 0 to parser credits for CFC search request */ |
| 6334 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); |
| 6335 | |
| 6336 | /* send Ethernet packet */ |
| 6337 | bnx2x_lb_pckt(bp); |
| 6338 | |
| 6339 | /* TODO do i reset NIG statistic? */ |
| 6340 | /* Wait until NIG register shows 1 packet of size 0x10 */ |
| 6341 | count = 1000 * factor; |
| 6342 | while (count) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6343 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6344 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
| 6345 | val = *bnx2x_sp(bp, wb_data[0]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6346 | if (val == 0x10) |
| 6347 | break; |
| 6348 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 6349 | usleep_range(10000, 20000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6350 | count--; |
| 6351 | } |
| 6352 | if (val != 0x10) { |
| 6353 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); |
| 6354 | return -1; |
| 6355 | } |
| 6356 | |
| 6357 | /* Wait until PRS register shows 1 packet */ |
| 6358 | count = 1000 * factor; |
| 6359 | while (count) { |
| 6360 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6361 | if (val == 1) |
| 6362 | break; |
| 6363 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 6364 | usleep_range(10000, 20000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6365 | count--; |
| 6366 | } |
| 6367 | if (val != 0x1) { |
| 6368 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); |
| 6369 | return -2; |
| 6370 | } |
| 6371 | |
| 6372 | /* Reset and init BRB, PRS */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6373 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6374 | msleep(50); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6375 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6376 | msleep(50); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6377 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
| 6378 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6379 | |
| 6380 | DP(NETIF_MSG_HW, "part2\n"); |
| 6381 | |
| 6382 | /* Disable inputs of parser neighbor blocks */ |
| 6383 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); |
| 6384 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); |
| 6385 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 6386 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6387 | |
| 6388 | /* Write 0 to parser credits for CFC search request */ |
| 6389 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); |
| 6390 | |
| 6391 | /* send 10 Ethernet packets */ |
| 6392 | for (i = 0; i < 10; i++) |
| 6393 | bnx2x_lb_pckt(bp); |
| 6394 | |
| 6395 | /* Wait until NIG register shows 10 + 1 |
| 6396 | packets of size 11*0x10 = 0xb0 */ |
| 6397 | count = 1000 * factor; |
| 6398 | while (count) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6399 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6400 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
| 6401 | val = *bnx2x_sp(bp, wb_data[0]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6402 | if (val == 0xb0) |
| 6403 | break; |
| 6404 | |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 6405 | usleep_range(10000, 20000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6406 | count--; |
| 6407 | } |
| 6408 | if (val != 0xb0) { |
| 6409 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); |
| 6410 | return -3; |
| 6411 | } |
| 6412 | |
| 6413 | /* Wait until PRS register shows 2 packets */ |
| 6414 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); |
| 6415 | if (val != 2) |
| 6416 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); |
| 6417 | |
| 6418 | /* Write 1 to parser credits for CFC search request */ |
| 6419 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); |
| 6420 | |
| 6421 | /* Wait until PRS register shows 3 packets */ |
| 6422 | msleep(10 * factor); |
| 6423 | /* Wait until NIG register shows 1 packet of size 0x10 */ |
| 6424 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); |
| 6425 | if (val != 3) |
| 6426 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); |
| 6427 | |
| 6428 | /* clear NIG EOP FIFO */ |
| 6429 | for (i = 0; i < 11; i++) |
| 6430 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); |
| 6431 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); |
| 6432 | if (val != 1) { |
| 6433 | BNX2X_ERR("clear of NIG failed\n"); |
| 6434 | return -4; |
| 6435 | } |
| 6436 | |
| 6437 | /* Reset and init BRB, PRS, NIG */ |
| 6438 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
| 6439 | msleep(50); |
| 6440 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
| 6441 | msleep(50); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6442 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
| 6443 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6444 | if (!CNIC_SUPPORT(bp)) |
| 6445 | /* set NIC mode */ |
| 6446 | REG_WR(bp, PRS_REG_NIC_MODE, 1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6447 | |
| 6448 | /* Enable inputs of parser neighbor blocks */ |
| 6449 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); |
| 6450 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); |
| 6451 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 6452 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6453 | |
| 6454 | DP(NETIF_MSG_HW, "done\n"); |
| 6455 | |
| 6456 | return 0; /* OK */ |
| 6457 | } |
| 6458 | |
Vladislav Zolotarov | 4a33bc0 | 2011-01-09 02:20:04 +0000 | [diff] [blame] | 6459 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6460 | { |
Yuval Mintz | b343d00 | 2012-12-02 04:05:53 +0000 | [diff] [blame] | 6461 | u32 val; |
| 6462 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6463 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6464 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6465 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
| 6466 | else |
| 6467 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6468 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
| 6469 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6470 | /* |
| 6471 | * mask read length error interrupts in brb for parser |
| 6472 | * (parsing unit and 'checksum and crc' unit) |
| 6473 | * these errors are legal (PU reads fixed length and CAC can cause |
| 6474 | * read length error on truncated packets) |
| 6475 | */ |
| 6476 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6477 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
| 6478 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); |
| 6479 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); |
| 6480 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); |
| 6481 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6482 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
| 6483 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6484 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
| 6485 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); |
| 6486 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6487 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
| 6488 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6489 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
| 6490 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); |
| 6491 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); |
| 6492 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6493 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
| 6494 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 6495 | |
Yuval Mintz | b343d00 | 2012-12-02 04:05:53 +0000 | [diff] [blame] | 6496 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
| 6497 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | |
| 6498 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; |
| 6499 | if (!CHIP_IS_E1x(bp)) |
| 6500 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | |
| 6501 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; |
| 6502 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); |
| 6503 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6504 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
| 6505 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); |
| 6506 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6507 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6508 | |
| 6509 | if (!CHIP_IS_E1x(bp)) |
| 6510 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ |
| 6511 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); |
| 6512 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6513 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
| 6514 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6515 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
Vladislav Zolotarov | 4a33bc0 | 2011-01-09 02:20:04 +0000 | [diff] [blame] | 6516 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6517 | } |
| 6518 | |
Eilon Greenstein | 81f75bb | 2009-01-22 03:37:31 +0000 | [diff] [blame] | 6519 | static void bnx2x_reset_common(struct bnx2x *bp) |
| 6520 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6521 | u32 val = 0x1400; |
| 6522 | |
Eilon Greenstein | 81f75bb | 2009-01-22 03:37:31 +0000 | [diff] [blame] | 6523 | /* reset_common */ |
| 6524 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
| 6525 | 0xd3ffff7f); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6526 | |
| 6527 | if (CHIP_IS_E3(bp)) { |
| 6528 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; |
| 6529 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; |
| 6530 | } |
| 6531 | |
| 6532 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); |
| 6533 | } |
| 6534 | |
| 6535 | static void bnx2x_setup_dmae(struct bnx2x *bp) |
| 6536 | { |
| 6537 | bp->dmae_ready = 0; |
| 6538 | spin_lock_init(&bp->dmae_lock); |
Eilon Greenstein | 81f75bb | 2009-01-22 03:37:31 +0000 | [diff] [blame] | 6539 | } |
| 6540 | |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 6541 | static void bnx2x_init_pxp(struct bnx2x *bp) |
| 6542 | { |
| 6543 | u16 devctl; |
| 6544 | int r_order, w_order; |
| 6545 | |
Jiang Liu | 2a80eeb | 2012-08-20 13:26:51 -0600 | [diff] [blame] | 6546 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 6547 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
| 6548 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
| 6549 | if (bp->mrrs == -1) |
| 6550 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
| 6551 | else { |
| 6552 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); |
| 6553 | r_order = bp->mrrs; |
| 6554 | } |
| 6555 | |
| 6556 | bnx2x_init_pxp_arb(bp, r_order, w_order); |
| 6557 | } |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6558 | |
| 6559 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) |
| 6560 | { |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 6561 | int is_required; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6562 | u32 val; |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 6563 | int port; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6564 | |
Vladislav Zolotarov | 2145a92 | 2010-04-19 01:13:49 +0000 | [diff] [blame] | 6565 | if (BP_NOMCP(bp)) |
| 6566 | return; |
| 6567 | |
| 6568 | is_required = 0; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6569 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
| 6570 | SHARED_HW_CFG_FAN_FAILURE_MASK; |
| 6571 | |
| 6572 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) |
| 6573 | is_required = 1; |
| 6574 | |
| 6575 | /* |
| 6576 | * The fan failure mechanism is usually related to the PHY type since |
| 6577 | * the power consumption of the board is affected by the PHY. Currently, |
| 6578 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. |
| 6579 | */ |
| 6580 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) |
| 6581 | for (port = PORT_0; port < PORT_MAX; port++) { |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6582 | is_required |= |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 6583 | bnx2x_fan_failure_det_req( |
| 6584 | bp, |
| 6585 | bp->common.shmem_base, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 6586 | bp->common.shmem2_base, |
Yaniv Rosner | d90d96b | 2010-09-07 11:41:04 +0000 | [diff] [blame] | 6587 | port); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6588 | } |
| 6589 | |
| 6590 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); |
| 6591 | |
| 6592 | if (is_required == 0) |
| 6593 | return; |
| 6594 | |
| 6595 | /* Fan failure is indicated by SPIO 5 */ |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 6596 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6597 | |
| 6598 | /* set to active low mode */ |
| 6599 | val = REG_RD(bp, MISC_REG_SPIO_INT); |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 6600 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6601 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
| 6602 | |
| 6603 | /* enable interrupt to signal the IGU */ |
| 6604 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 6605 | val |= MISC_SPIO_SPIO5; |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 6606 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
| 6607 | } |
| 6608 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 6609 | void bnx2x_pf_disable(struct bnx2x *bp) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6610 | { |
| 6611 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); |
| 6612 | val &= ~IGU_PF_CONF_FUNC_EN; |
| 6613 | |
| 6614 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); |
| 6615 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); |
| 6616 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); |
| 6617 | } |
| 6618 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 6619 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6620 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6621 | u32 shmem_base[2], shmem2_base[2]; |
Yaniv Rosner | b884d95 | 2012-11-27 03:46:28 +0000 | [diff] [blame] | 6622 | /* Avoid common init in case MFW supports LFA */ |
| 6623 | if (SHMEM2_RD(bp, size) > |
| 6624 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) |
| 6625 | return; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6626 | shmem_base[0] = bp->common.shmem_base; |
| 6627 | shmem2_base[0] = bp->common.shmem2_base; |
| 6628 | if (!CHIP_IS_E1x(bp)) { |
| 6629 | shmem_base[1] = |
| 6630 | SHMEM2_RD(bp, other_shmem_base_addr); |
| 6631 | shmem2_base[1] = |
| 6632 | SHMEM2_RD(bp, other_shmem2_base_addr); |
| 6633 | } |
| 6634 | bnx2x_acquire_phy_lock(bp); |
| 6635 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, |
| 6636 | bp->common.chip_id); |
| 6637 | bnx2x_release_phy_lock(bp); |
| 6638 | } |
| 6639 | |
| 6640 | /** |
| 6641 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. |
| 6642 | * |
| 6643 | * @bp: driver handle |
| 6644 | */ |
| 6645 | static int bnx2x_init_hw_common(struct bnx2x *bp) |
| 6646 | { |
| 6647 | u32 val; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6648 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 6649 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6650 | |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 6651 | /* |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 6652 | * take the RESET lock to protect undi_unload flow from accessing |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 6653 | * registers while we're resetting the chip |
| 6654 | */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 6655 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 6656 | |
Eilon Greenstein | 81f75bb | 2009-01-22 03:37:31 +0000 | [diff] [blame] | 6657 | bnx2x_reset_common(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6658 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6659 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6660 | val = 0xfffc; |
| 6661 | if (CHIP_IS_E3(bp)) { |
| 6662 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; |
| 6663 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; |
| 6664 | } |
| 6665 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6666 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 6667 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 6668 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6669 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
| 6670 | |
| 6671 | if (!CHIP_IS_E1x(bp)) { |
| 6672 | u8 abs_func_id; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6673 | |
| 6674 | /** |
| 6675 | * 4-port mode or 2-port mode we need to turn of master-enable |
| 6676 | * for everyone, after that, turn it back on for self. |
| 6677 | * so, we disregard multi-function or not, and always disable |
| 6678 | * for all functions on the given path, this means 0,2,4,6 for |
| 6679 | * path 0 and 1,3,5,7 for path 1 |
| 6680 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6681 | for (abs_func_id = BP_PATH(bp); |
| 6682 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { |
| 6683 | if (abs_func_id == BP_ABS_FUNC(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6684 | REG_WR(bp, |
| 6685 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, |
| 6686 | 1); |
| 6687 | continue; |
| 6688 | } |
| 6689 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6690 | bnx2x_pretend_func(bp, abs_func_id); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6691 | /* clear pf enable */ |
| 6692 | bnx2x_pf_disable(bp); |
| 6693 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); |
| 6694 | } |
| 6695 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6696 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6697 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6698 | if (CHIP_IS_E1(bp)) { |
| 6699 | /* enable HW interrupt from PXP on USDM overflow |
| 6700 | bit 16 on INT_MASK_0 */ |
| 6701 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6702 | } |
| 6703 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6704 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6705 | bnx2x_init_pxp(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6706 | |
| 6707 | #ifdef __BIG_ENDIAN |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6708 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
| 6709 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); |
| 6710 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); |
| 6711 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); |
| 6712 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 6713 | /* make sure this value is 0 */ |
| 6714 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6715 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6716 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ |
| 6717 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); |
| 6718 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); |
| 6719 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); |
| 6720 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6721 | #endif |
| 6722 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6723 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
| 6724 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6725 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
| 6726 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6727 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6728 | /* let the HW do it's magic ... */ |
| 6729 | msleep(100); |
| 6730 | /* finish PXP init */ |
| 6731 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); |
| 6732 | if (val != 1) { |
| 6733 | BNX2X_ERR("PXP2 CFG failed\n"); |
| 6734 | return -EBUSY; |
| 6735 | } |
| 6736 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); |
| 6737 | if (val != 1) { |
| 6738 | BNX2X_ERR("PXP2 RD_INIT failed\n"); |
| 6739 | return -EBUSY; |
| 6740 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6741 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6742 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
| 6743 | * have entries with value "0" and valid bit on. |
| 6744 | * This needs to be done by the first PF that is loaded in a path |
| 6745 | * (i.e. common phase) |
| 6746 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6747 | if (!CHIP_IS_E1x(bp)) { |
| 6748 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 |
| 6749 | * (i.e. vnic3) to start even if it is marked as "scan-off". |
| 6750 | * This occurs when a different function (func2,3) is being marked |
| 6751 | * as "scan-off". Real-life scenario for example: if a driver is being |
| 6752 | * load-unloaded while func6,7 are down. This will cause the timer to access |
| 6753 | * the ilt, translate to a logical address and send a request to read/write. |
| 6754 | * Since the ilt for the function that is down is not valid, this will cause |
| 6755 | * a translation error which is unrecoverable. |
| 6756 | * The Workaround is intended to make sure that when this happens nothing fatal |
| 6757 | * will occur. The workaround: |
| 6758 | * 1. First PF driver which loads on a path will: |
| 6759 | * a. After taking the chip out of reset, by using pretend, |
| 6760 | * it will write "0" to the following registers of |
| 6761 | * the other vnics. |
| 6762 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); |
| 6763 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); |
| 6764 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); |
| 6765 | * And for itself it will write '1' to |
| 6766 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable |
| 6767 | * dmae-operations (writing to pram for example.) |
| 6768 | * note: can be done for only function 6,7 but cleaner this |
| 6769 | * way. |
| 6770 | * b. Write zero+valid to the entire ILT. |
| 6771 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of |
| 6772 | * VNIC3 (of that port). The range allocated will be the |
| 6773 | * entire ILT. This is needed to prevent ILT range error. |
| 6774 | * 2. Any PF driver load flow: |
| 6775 | * a. ILT update with the physical addresses of the allocated |
| 6776 | * logical pages. |
| 6777 | * b. Wait 20msec. - note that this timeout is needed to make |
| 6778 | * sure there are no requests in one of the PXP internal |
| 6779 | * queues with "old" ILT addresses. |
| 6780 | * c. PF enable in the PGLC. |
| 6781 | * d. Clear the was_error of the PF in the PGLC. (could have |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 6782 | * occurred while driver was down) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6783 | * e. PF enable in the CFC (WEAK + STRONG) |
| 6784 | * f. Timers scan enable |
| 6785 | * 3. PF driver unload flow: |
| 6786 | * a. Clear the Timers scan_en. |
| 6787 | * b. Polling for scan_on=0 for that PF. |
| 6788 | * c. Clear the PF enable bit in the PXP. |
| 6789 | * d. Clear the PF enable in the CFC (WEAK + STRONG) |
| 6790 | * e. Write zero+valid to all ILT entries (The valid bit must |
| 6791 | * stay set) |
| 6792 | * f. If this is VNIC 3 of a port then also init |
| 6793 | * first_timers_ilt_entry to zero and last_timers_ilt_entry |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 6794 | * to the last entry in the ILT. |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6795 | * |
| 6796 | * Notes: |
| 6797 | * Currently the PF error in the PGLC is non recoverable. |
| 6798 | * In the future the there will be a recovery routine for this error. |
| 6799 | * Currently attention is masked. |
| 6800 | * Having an MCP lock on the load/unload process does not guarantee that |
| 6801 | * there is no Timer disable during Func6/7 enable. This is because the |
| 6802 | * Timers scan is currently being cleared by the MCP on FLR. |
| 6803 | * Step 2.d can be done only for PF6/7 and the driver can also check if |
| 6804 | * there is error before clearing it. But the flow above is simpler and |
| 6805 | * more general. |
| 6806 | * All ILT entries are written by zero+valid and not just PF6/7 |
| 6807 | * ILT entries since in the future the ILT entries allocation for |
| 6808 | * PF-s might be dynamic. |
| 6809 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6810 | struct ilt_client_info ilt_cli; |
| 6811 | struct bnx2x_ilt ilt; |
| 6812 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); |
| 6813 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); |
| 6814 | |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 6815 | /* initialize dummy TM client */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6816 | ilt_cli.start = 0; |
| 6817 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; |
| 6818 | ilt_cli.client_num = ILT_CLIENT_TM; |
| 6819 | |
| 6820 | /* Step 1: set zeroes to all ilt page entries with valid bit on |
| 6821 | * Step 2: set the timers first/last ilt entry to point |
| 6822 | * to the entire range to prevent ILT range error for 3rd/4th |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 6823 | * vnic (this code assumes existence of the vnic) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6824 | * |
| 6825 | * both steps performed by call to bnx2x_ilt_client_init_op() |
| 6826 | * with dummy TM client |
| 6827 | * |
| 6828 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT |
| 6829 | * and his brother are split registers |
| 6830 | */ |
| 6831 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); |
| 6832 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); |
| 6833 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); |
| 6834 | |
| 6835 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); |
| 6836 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); |
| 6837 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); |
| 6838 | } |
| 6839 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6840 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
| 6841 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6842 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6843 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6844 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
| 6845 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6846 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6847 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6848 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6849 | |
| 6850 | /* let the HW do it's magic ... */ |
| 6851 | do { |
| 6852 | msleep(200); |
| 6853 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); |
| 6854 | } while (factor-- && (val != 1)); |
| 6855 | |
| 6856 | if (val != 1) { |
| 6857 | BNX2X_ERR("ATC_INIT failed\n"); |
| 6858 | return -EBUSY; |
| 6859 | } |
| 6860 | } |
| 6861 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6862 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6863 | |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 6864 | bnx2x_iov_init_dmae(bp); |
| 6865 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6866 | /* clean the DMAE memory */ |
| 6867 | bp->dmae_ready = 1; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6868 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6869 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6870 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); |
| 6871 | |
| 6872 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); |
| 6873 | |
| 6874 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); |
| 6875 | |
| 6876 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6877 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6878 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
| 6879 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); |
| 6880 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); |
| 6881 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); |
| 6882 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6883 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 6884 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 6885 | /* QM queues pointers table */ |
| 6886 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 6887 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6888 | /* soft reset pulse */ |
| 6889 | REG_WR(bp, QM_REG_SOFT_RESET, 1); |
| 6890 | REG_WR(bp, QM_REG_SOFT_RESET, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6891 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6892 | if (CNIC_SUPPORT(bp)) |
| 6893 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6894 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6895 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
Ariel Elior | b9871bc | 2013-09-04 14:09:21 +0300 | [diff] [blame] | 6896 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6897 | if (!CHIP_REV_IS_SLOW(bp)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6898 | /* enable hw interrupt from doorbell Q */ |
| 6899 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6900 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6901 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6902 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6903 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
Eilon Greenstein | 26c8fa4 | 2009-01-14 21:29:55 -0800 | [diff] [blame] | 6904 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 6905 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6906 | if (!CHIP_IS_E1(bp)) |
| 6907 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
| 6908 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 6909 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
| 6910 | if (IS_MF_AFEX(bp)) { |
| 6911 | /* configure that VNTag and VLAN headers must be |
| 6912 | * received in afex mode |
| 6913 | */ |
| 6914 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); |
| 6915 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); |
| 6916 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); |
| 6917 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); |
| 6918 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); |
| 6919 | } else { |
| 6920 | /* Bit-map indicating which L2 hdrs may appear |
| 6921 | * after the basic Ethernet header |
| 6922 | */ |
| 6923 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, |
| 6924 | bp->path_has_ovlan ? 7 : 6); |
| 6925 | } |
| 6926 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6927 | |
| 6928 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
| 6929 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); |
| 6930 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); |
| 6931 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); |
| 6932 | |
| 6933 | if (!CHIP_IS_E1x(bp)) { |
| 6934 | /* reset VFC memories */ |
| 6935 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, |
| 6936 | VFC_MEMORIES_RST_REG_CAM_RST | |
| 6937 | VFC_MEMORIES_RST_REG_RAM_RST); |
| 6938 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, |
| 6939 | VFC_MEMORIES_RST_REG_CAM_RST | |
| 6940 | VFC_MEMORIES_RST_REG_RAM_RST); |
| 6941 | |
| 6942 | msleep(20); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6943 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6944 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6945 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
| 6946 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); |
| 6947 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); |
| 6948 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6949 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6950 | /* sync semi rtc */ |
| 6951 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
| 6952 | 0x80000000); |
| 6953 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, |
| 6954 | 0x80000000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6955 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6956 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
| 6957 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); |
| 6958 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6959 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 6960 | if (!CHIP_IS_E1x(bp)) { |
| 6961 | if (IS_MF_AFEX(bp)) { |
| 6962 | /* configure that VNTag and VLAN headers must be |
| 6963 | * sent in afex mode |
| 6964 | */ |
| 6965 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); |
| 6966 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); |
| 6967 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); |
| 6968 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); |
| 6969 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); |
| 6970 | } else { |
| 6971 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, |
| 6972 | bp->path_has_ovlan ? 7 : 6); |
| 6973 | } |
| 6974 | } |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 6975 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6976 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 6977 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 6978 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
| 6979 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 6980 | if (CNIC_SUPPORT(bp)) { |
| 6981 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); |
| 6982 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); |
| 6983 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); |
| 6984 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); |
| 6985 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); |
| 6986 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); |
| 6987 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); |
| 6988 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); |
| 6989 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); |
| 6990 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); |
| 6991 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6992 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6993 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 6994 | if (sizeof(union cdu_context) != 1024) |
| 6995 | /* we currently assume that a context is 1024 bytes */ |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 6996 | dev_alert(&bp->pdev->dev, |
| 6997 | "please adjust the size of cdu_context(%ld)\n", |
| 6998 | (long)sizeof(union cdu_context)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 6999 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7000 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7001 | val = (4 << 24) + (0 << 12) + 1024; |
| 7002 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7003 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7004 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7005 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
Eilon Greenstein | 8d9c5f3 | 2009-02-15 23:24:08 -0800 | [diff] [blame] | 7006 | /* enable context validation interrupt from CFC */ |
| 7007 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); |
| 7008 | |
| 7009 | /* set the thresholds to prevent CFC/CDU race */ |
| 7010 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7011 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7012 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7013 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7014 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7015 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
| 7016 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7017 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
| 7018 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7019 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7020 | /* Reset PCIE errors for debug */ |
| 7021 | REG_WR(bp, 0x2814, 0xffffffff); |
| 7022 | REG_WR(bp, 0x3820, 0xffffffff); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7023 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7024 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7025 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
| 7026 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | |
| 7027 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); |
| 7028 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, |
| 7029 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | |
| 7030 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | |
| 7031 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); |
| 7032 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, |
| 7033 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | |
| 7034 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | |
| 7035 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); |
| 7036 | } |
| 7037 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7038 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7039 | if (!CHIP_IS_E1(bp)) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7040 | /* in E3 this done in per-port section */ |
| 7041 | if (!CHIP_IS_E3(bp)) |
| 7042 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); |
| 7043 | } |
| 7044 | if (CHIP_IS_E1H(bp)) |
| 7045 | /* not applicable for E2 (and above ...) */ |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 7046 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7047 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7048 | if (CHIP_REV_IS_SLOW(bp)) |
| 7049 | msleep(200); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7050 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7051 | /* finish CFC init */ |
| 7052 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); |
| 7053 | if (val != 1) { |
| 7054 | BNX2X_ERR("CFC LL_INIT failed\n"); |
| 7055 | return -EBUSY; |
| 7056 | } |
| 7057 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); |
| 7058 | if (val != 1) { |
| 7059 | BNX2X_ERR("CFC AC_INIT failed\n"); |
| 7060 | return -EBUSY; |
| 7061 | } |
| 7062 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); |
| 7063 | if (val != 1) { |
| 7064 | BNX2X_ERR("CFC CAM_INIT failed\n"); |
| 7065 | return -EBUSY; |
| 7066 | } |
| 7067 | REG_WR(bp, CFC_REG_DEBUG0, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7068 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7069 | if (CHIP_IS_E1(bp)) { |
| 7070 | /* read NIG statistic |
| 7071 | to see if this is our first up since powerup */ |
| 7072 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
| 7073 | val = *bnx2x_sp(bp, wb_data[0]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7074 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7075 | /* do internal memory self test */ |
| 7076 | if ((val == 0) && bnx2x_int_mem_test(bp)) { |
| 7077 | BNX2X_ERR("internal mem self test failed\n"); |
| 7078 | return -EBUSY; |
| 7079 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7080 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7081 | |
Eilon Greenstein | fd4ef40 | 2009-07-21 05:47:27 +0000 | [diff] [blame] | 7082 | bnx2x_setup_fan_failure_detection(bp); |
| 7083 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7084 | /* clear PXP2 attentions */ |
| 7085 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7086 | |
Vladislav Zolotarov | 4a33bc0 | 2011-01-09 02:20:04 +0000 | [diff] [blame] | 7087 | bnx2x_enable_blocks_attention(bp); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 7088 | bnx2x_enable_blocks_parity(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7089 | |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 7090 | if (!BP_NOMCP(bp)) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7091 | if (CHIP_IS_E1x(bp)) |
| 7092 | bnx2x__common_init_phy(bp); |
Yaniv Rosner | 6bbca91 | 2008-08-13 15:57:28 -0700 | [diff] [blame] | 7093 | } else |
| 7094 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
| 7095 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7096 | return 0; |
| 7097 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7098 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7099 | /** |
| 7100 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. |
| 7101 | * |
| 7102 | * @bp: driver handle |
| 7103 | */ |
| 7104 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) |
| 7105 | { |
| 7106 | int rc = bnx2x_init_hw_common(bp); |
| 7107 | |
| 7108 | if (rc) |
| 7109 | return rc; |
| 7110 | |
| 7111 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ |
| 7112 | if (!BP_NOMCP(bp)) |
| 7113 | bnx2x__common_init_phy(bp); |
| 7114 | |
| 7115 | return 0; |
| 7116 | } |
| 7117 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7118 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7119 | { |
| 7120 | int port = BP_PORT(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7121 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
Eilon Greenstein | 1c06328 | 2009-02-12 08:36:43 +0000 | [diff] [blame] | 7122 | u32 low, high; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7123 | u32 val; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7124 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 7125 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7126 | |
| 7127 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7128 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7129 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
| 7130 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
| 7131 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 7132 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7133 | /* Timers bug workaround: disables the pf_master bit in pglue at |
| 7134 | * common phase, we need to enable it here before any dmae access are |
| 7135 | * attempted. Therefore we manually added the enable-master to the |
| 7136 | * port phase (it also happens in the function phase) |
| 7137 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7138 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7139 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
| 7140 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7141 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
| 7142 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); |
| 7143 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
| 7144 | bnx2x_init_block(bp, BLOCK_QM, init_phase); |
| 7145 | |
| 7146 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); |
| 7147 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); |
| 7148 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); |
| 7149 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7150 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7151 | /* QM cid (connection) count */ |
| 7152 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7153 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7154 | if (CNIC_SUPPORT(bp)) { |
| 7155 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
| 7156 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); |
| 7157 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); |
| 7158 | } |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 7159 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7160 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
Eilon Greenstein | 1c06328 | 2009-02-12 08:36:43 +0000 | [diff] [blame] | 7161 | |
Dmitry Kravkov | 2b67404 | 2012-10-28 21:59:04 +0000 | [diff] [blame] | 7162 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
| 7163 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7164 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7165 | |
| 7166 | if (IS_MF(bp)) |
| 7167 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); |
| 7168 | else if (bp->dev->mtu > 4096) { |
| 7169 | if (bp->flags & ONE_PORT_FLAG) |
| 7170 | low = 160; |
| 7171 | else { |
| 7172 | val = bp->dev->mtu; |
| 7173 | /* (24*1024 + val*4)/256 */ |
| 7174 | low = 96 + (val/64) + |
| 7175 | ((val % 64) ? 1 : 0); |
| 7176 | } |
| 7177 | } else |
| 7178 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); |
| 7179 | high = low + 56; /* 14*1024/256 */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7180 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
| 7181 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); |
| 7182 | } |
| 7183 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7184 | if (CHIP_MODE_IS_4_PORT(bp)) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7185 | REG_WR(bp, (BP_PORT(bp) ? |
| 7186 | BRB1_REG_MAC_GUARANTIED_1 : |
| 7187 | BRB1_REG_MAC_GUARANTIED_0), 40); |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 7188 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7189 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 7190 | if (CHIP_IS_E3B0(bp)) { |
| 7191 | if (IS_MF_AFEX(bp)) { |
| 7192 | /* configure headers for AFEX mode */ |
| 7193 | REG_WR(bp, BP_PORT(bp) ? |
| 7194 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : |
| 7195 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); |
| 7196 | REG_WR(bp, BP_PORT(bp) ? |
| 7197 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : |
| 7198 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); |
| 7199 | REG_WR(bp, BP_PORT(bp) ? |
| 7200 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : |
| 7201 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); |
| 7202 | } else { |
| 7203 | /* Ovlan exists only if we are in multi-function + |
| 7204 | * switch-dependent mode, in switch-independent there |
| 7205 | * is no ovlan headers |
| 7206 | */ |
| 7207 | REG_WR(bp, BP_PORT(bp) ? |
| 7208 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : |
| 7209 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, |
| 7210 | (bp->path_has_ovlan ? 7 : 6)); |
| 7211 | } |
| 7212 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7213 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7214 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
| 7215 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); |
| 7216 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); |
| 7217 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); |
| 7218 | |
| 7219 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
| 7220 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); |
| 7221 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); |
| 7222 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); |
| 7223 | |
| 7224 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
| 7225 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); |
| 7226 | |
| 7227 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
| 7228 | |
| 7229 | if (CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7230 | /* configure PBF to work without PAUSE mtu 9000 */ |
| 7231 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7232 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7233 | /* update threshold */ |
| 7234 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); |
| 7235 | /* update init credit */ |
| 7236 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7237 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7238 | /* probe changes */ |
| 7239 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); |
| 7240 | udelay(50); |
| 7241 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); |
| 7242 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7243 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7244 | if (CNIC_SUPPORT(bp)) |
| 7245 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
| 7246 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7247 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
| 7248 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7249 | |
| 7250 | if (CHIP_IS_E1(bp)) { |
| 7251 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); |
| 7252 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); |
| 7253 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7254 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7255 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7256 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7257 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7258 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7259 | /* init aeu_mask_attn_func_0/1: |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 7260 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
| 7261 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7262 | * bits 4-7 are used for "per vn group attention" */ |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 7263 | val = IS_MF(bp) ? 0xF7 : 0x7; |
| 7264 | /* Enable DCBX attention for all but E1 */ |
| 7265 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; |
| 7266 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7267 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7268 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 7269 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7270 | if (!CHIP_IS_E1x(bp)) { |
| 7271 | /* Bit-map indicating which L2 hdrs may appear after the |
| 7272 | * basic Ethernet header |
| 7273 | */ |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 7274 | if (IS_MF_AFEX(bp)) |
| 7275 | REG_WR(bp, BP_PORT(bp) ? |
| 7276 | NIG_REG_P1_HDRS_AFTER_BASIC : |
| 7277 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); |
| 7278 | else |
| 7279 | REG_WR(bp, BP_PORT(bp) ? |
| 7280 | NIG_REG_P1_HDRS_AFTER_BASIC : |
| 7281 | NIG_REG_P0_HDRS_AFTER_BASIC, |
| 7282 | IS_MF_SD(bp) ? 7 : 6); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7283 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7284 | if (CHIP_IS_E3(bp)) |
| 7285 | REG_WR(bp, BP_PORT(bp) ? |
| 7286 | NIG_REG_LLH1_MF_MODE : |
| 7287 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); |
| 7288 | } |
| 7289 | if (!CHIP_IS_E3(bp)) |
| 7290 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7291 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7292 | if (!CHIP_IS_E1(bp)) { |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 7293 | /* 0x2 disable mf_ov, 0x1 enable */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7294 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 7295 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7296 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7297 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7298 | val = 0; |
| 7299 | switch (bp->mf_mode) { |
| 7300 | case MULTI_FUNCTION_SD: |
| 7301 | val = 1; |
| 7302 | break; |
| 7303 | case MULTI_FUNCTION_SI: |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 7304 | case MULTI_FUNCTION_AFEX: |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7305 | val = 2; |
| 7306 | break; |
| 7307 | } |
| 7308 | |
| 7309 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : |
| 7310 | NIG_REG_LLH0_CLS_TYPE), val); |
| 7311 | } |
Eilon Greenstein | 1c06328 | 2009-02-12 08:36:43 +0000 | [diff] [blame] | 7312 | { |
| 7313 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); |
| 7314 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); |
| 7315 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); |
| 7316 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7317 | } |
| 7318 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7319 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
| 7320 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); |
Yuval Mintz | d6d99a3 | 2012-12-02 04:05:45 +0000 | [diff] [blame] | 7321 | if (val & MISC_SPIO_SPIO5) { |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 7322 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
| 7323 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); |
| 7324 | val = REG_RD(bp, reg_addr); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 7325 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 7326 | REG_WR(bp, reg_addr, val); |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 7327 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7328 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7329 | return 0; |
| 7330 | } |
| 7331 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7332 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
| 7333 | { |
| 7334 | int reg; |
Yuval Mintz | 32d68de | 2012-04-03 18:41:24 +0000 | [diff] [blame] | 7335 | u32 wb_write[2]; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7336 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7337 | if (CHIP_IS_E1(bp)) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7338 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7339 | else |
| 7340 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7341 | |
Yuval Mintz | 32d68de | 2012-04-03 18:41:24 +0000 | [diff] [blame] | 7342 | wb_write[0] = ONCHIP_ADDR1(addr); |
| 7343 | wb_write[1] = ONCHIP_ADDR2(addr); |
| 7344 | REG_WR_DMAE(bp, reg, wb_write, 2); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7345 | } |
| 7346 | |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 7347 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 7348 | { |
| 7349 | u32 data, ctl, cnt = 100; |
| 7350 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; |
| 7351 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; |
| 7352 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; |
| 7353 | u32 sb_bit = 1 << (idu_sb_id%32); |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 7354 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 7355 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
| 7356 | |
| 7357 | /* Not supported in BC mode */ |
| 7358 | if (CHIP_INT_MODE_IS_BC(bp)) |
| 7359 | return; |
| 7360 | |
| 7361 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup |
| 7362 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | |
| 7363 | IGU_REGULAR_CLEANUP_SET | |
| 7364 | IGU_REGULAR_BCLEANUP; |
| 7365 | |
| 7366 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | |
| 7367 | func_encode << IGU_CTRL_REG_FID_SHIFT | |
| 7368 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; |
| 7369 | |
| 7370 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
| 7371 | data, igu_addr_data); |
| 7372 | REG_WR(bp, igu_addr_data, data); |
| 7373 | mmiowb(); |
| 7374 | barrier(); |
| 7375 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
| 7376 | ctl, igu_addr_ctl); |
| 7377 | REG_WR(bp, igu_addr_ctl, ctl); |
| 7378 | mmiowb(); |
| 7379 | barrier(); |
| 7380 | |
| 7381 | /* wait for clean up to finish */ |
| 7382 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) |
| 7383 | msleep(20); |
| 7384 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 7385 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
| 7386 | DP(NETIF_MSG_HW, |
| 7387 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", |
| 7388 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); |
| 7389 | } |
| 7390 | } |
| 7391 | |
| 7392 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7393 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7394 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7395 | } |
| 7396 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 7397 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7398 | { |
| 7399 | u32 i, base = FUNC_ILT_BASE(func); |
| 7400 | for (i = base; i < base + ILT_PER_FUNC; i++) |
| 7401 | bnx2x_ilt_wr(bp, i, 0); |
| 7402 | } |
| 7403 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 7404 | static void bnx2x_init_searcher(struct bnx2x *bp) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7405 | { |
| 7406 | int port = BP_PORT(bp); |
| 7407 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); |
| 7408 | /* T1 hash bits value determines the T1 number of entries */ |
| 7409 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); |
| 7410 | } |
| 7411 | |
| 7412 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) |
| 7413 | { |
| 7414 | int rc; |
| 7415 | struct bnx2x_func_state_params func_params = {NULL}; |
| 7416 | struct bnx2x_func_switch_update_params *switch_update_params = |
| 7417 | &func_params.params.switch_update; |
| 7418 | |
| 7419 | /* Prepare parameters for function state transitions */ |
| 7420 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); |
| 7421 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); |
| 7422 | |
| 7423 | func_params.f_obj = &bp->func_obj; |
| 7424 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; |
| 7425 | |
| 7426 | /* Function parameters */ |
| 7427 | switch_update_params->suspend = suspend; |
| 7428 | |
| 7429 | rc = bnx2x_func_state_change(bp, &func_params); |
| 7430 | |
| 7431 | return rc; |
| 7432 | } |
| 7433 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 7434 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7435 | { |
| 7436 | int rc, i, port = BP_PORT(bp); |
| 7437 | int vlan_en = 0, mac_en[NUM_MACS]; |
| 7438 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7439 | /* Close input from network */ |
| 7440 | if (bp->mf_mode == SINGLE_FUNCTION) { |
| 7441 | bnx2x_set_rx_filter(&bp->link_params, 0); |
| 7442 | } else { |
| 7443 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : |
| 7444 | NIG_REG_LLH0_FUNC_EN); |
| 7445 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : |
| 7446 | NIG_REG_LLH0_FUNC_EN, 0); |
| 7447 | for (i = 0; i < NUM_MACS; i++) { |
| 7448 | mac_en[i] = REG_RD(bp, port ? |
| 7449 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + |
| 7450 | 4 * i) : |
| 7451 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + |
| 7452 | 4 * i)); |
| 7453 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + |
| 7454 | 4 * i) : |
| 7455 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); |
| 7456 | } |
| 7457 | } |
| 7458 | |
| 7459 | /* Close BMC to host */ |
| 7460 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : |
| 7461 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); |
| 7462 | |
| 7463 | /* Suspend Tx switching to the PF. Completion of this ramrod |
| 7464 | * further guarantees that all the packets of that PF / child |
| 7465 | * VFs in BRB were processed by the Parser, so it is safe to |
| 7466 | * change the NIC_MODE register. |
| 7467 | */ |
| 7468 | rc = bnx2x_func_switch_update(bp, 1); |
| 7469 | if (rc) { |
| 7470 | BNX2X_ERR("Can't suspend tx-switching!\n"); |
| 7471 | return rc; |
| 7472 | } |
| 7473 | |
| 7474 | /* Change NIC_MODE register */ |
| 7475 | REG_WR(bp, PRS_REG_NIC_MODE, 0); |
| 7476 | |
| 7477 | /* Open input from network */ |
| 7478 | if (bp->mf_mode == SINGLE_FUNCTION) { |
| 7479 | bnx2x_set_rx_filter(&bp->link_params, 1); |
| 7480 | } else { |
| 7481 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : |
| 7482 | NIG_REG_LLH0_FUNC_EN, vlan_en); |
| 7483 | for (i = 0; i < NUM_MACS; i++) { |
| 7484 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + |
| 7485 | 4 * i) : |
| 7486 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), |
| 7487 | mac_en[i]); |
| 7488 | } |
| 7489 | } |
| 7490 | |
| 7491 | /* Enable BMC to host */ |
| 7492 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : |
| 7493 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); |
| 7494 | |
| 7495 | /* Resume Tx switching to the PF */ |
| 7496 | rc = bnx2x_func_switch_update(bp, 0); |
| 7497 | if (rc) { |
| 7498 | BNX2X_ERR("Can't resume tx-switching!\n"); |
| 7499 | return rc; |
| 7500 | } |
| 7501 | |
| 7502 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); |
| 7503 | return 0; |
| 7504 | } |
| 7505 | |
| 7506 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) |
| 7507 | { |
| 7508 | int rc; |
| 7509 | |
| 7510 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); |
| 7511 | |
| 7512 | if (CONFIGURE_NIC_MODE(bp)) { |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 7513 | /* Configure searcher as part of function hw init */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7514 | bnx2x_init_searcher(bp); |
| 7515 | |
| 7516 | /* Reset NIC mode */ |
| 7517 | rc = bnx2x_reset_nic_mode(bp); |
| 7518 | if (rc) |
| 7519 | BNX2X_ERR("Can't change NIC mode!\n"); |
| 7520 | return rc; |
| 7521 | } |
| 7522 | |
| 7523 | return 0; |
| 7524 | } |
| 7525 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7526 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7527 | { |
| 7528 | int port = BP_PORT(bp); |
| 7529 | int func = BP_FUNC(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7530 | int init_phase = PHASE_PF0 + func; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7531 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
| 7532 | u16 cdu_ilt_start; |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 7533 | u32 addr, val; |
Vladislav Zolotarov | f4a6689 | 2010-10-19 05:13:09 +0000 | [diff] [blame] | 7534 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 7535 | int i, main_mem_width, rc; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7536 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 7537 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7538 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7539 | /* FLR cleanup - hmmm */ |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 7540 | if (!CHIP_IS_E1x(bp)) { |
| 7541 | rc = bnx2x_pf_flr_clnup(bp); |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 7542 | if (rc) { |
| 7543 | bnx2x_fw_dump(bp); |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 7544 | return rc; |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 7545 | } |
Ariel Elior | 89db4ad | 2012-01-26 06:01:48 +0000 | [diff] [blame] | 7546 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7547 | |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 7548 | /* set MSI reconfigure capability */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7549 | if (bp->common.int_block == INT_BLOCK_HC) { |
| 7550 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); |
| 7551 | val = REG_RD(bp, addr); |
| 7552 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; |
| 7553 | REG_WR(bp, addr, val); |
| 7554 | } |
Eilon Greenstein | 8badd27 | 2009-02-12 08:36:15 +0000 | [diff] [blame] | 7555 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7556 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
| 7557 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); |
| 7558 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7559 | ilt = BP_ILT(bp); |
| 7560 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7561 | |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 7562 | if (IS_SRIOV(bp)) |
| 7563 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; |
| 7564 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); |
| 7565 | |
| 7566 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes |
| 7567 | * those of the VFs, so start line should be reset |
| 7568 | */ |
| 7569 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7570 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7571 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7572 | ilt->lines[cdu_ilt_start + i].page_mapping = |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7573 | bp->context[i].cxt_mapping; |
| 7574 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7575 | } |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 7576 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7577 | bnx2x_ilt_init_op(bp, INITOP_SET); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 7578 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7579 | if (!CONFIGURE_NIC_MODE(bp)) { |
| 7580 | bnx2x_init_searcher(bp); |
| 7581 | REG_WR(bp, PRS_REG_NIC_MODE, 0); |
| 7582 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); |
| 7583 | } else { |
| 7584 | /* Set NIC mode */ |
| 7585 | REG_WR(bp, PRS_REG_NIC_MODE, 1); |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 7586 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7587 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7588 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7589 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7590 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
| 7591 | |
| 7592 | /* Turn on a single ISR mode in IGU if driver is going to use |
| 7593 | * INT#x or MSI |
| 7594 | */ |
| 7595 | if (!(bp->flags & USING_MSIX_FLAG)) |
| 7596 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; |
| 7597 | /* |
| 7598 | * Timers workaround bug: function init part. |
| 7599 | * Need to wait 20msec after initializing ILT, |
| 7600 | * needed to make sure there are no requests in |
| 7601 | * one of the PXP internal queues with "old" ILT addresses |
| 7602 | */ |
| 7603 | msleep(20); |
| 7604 | /* |
| 7605 | * Master enable - Due to WB DMAE writes performed before this |
| 7606 | * register is re-initialized as part of the regular function |
| 7607 | * init |
| 7608 | */ |
| 7609 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
| 7610 | /* Enable the function in IGU */ |
| 7611 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); |
| 7612 | } |
| 7613 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7614 | bp->dmae_ready = 1; |
| 7615 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7616 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7617 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7618 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7619 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
| 7620 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7621 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
| 7622 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); |
| 7623 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
| 7624 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); |
| 7625 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
| 7626 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); |
| 7627 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); |
| 7628 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); |
| 7629 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); |
| 7630 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
| 7631 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); |
| 7632 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); |
| 7633 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7634 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7635 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7636 | REG_WR(bp, QM_REG_PF_EN, 1); |
| 7637 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7638 | if (!CHIP_IS_E1x(bp)) { |
| 7639 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); |
| 7640 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); |
| 7641 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); |
| 7642 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); |
| 7643 | } |
| 7644 | bnx2x_init_block(bp, BLOCK_QM, init_phase); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7645 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7646 | bnx2x_init_block(bp, BLOCK_TM, init_phase); |
| 7647 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
Ariel Elior | c19d65c | 2013-09-09 14:51:27 +0300 | [diff] [blame] | 7648 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 7649 | |
| 7650 | bnx2x_iov_init_dq(bp); |
| 7651 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7652 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
| 7653 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
| 7654 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
| 7655 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); |
| 7656 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); |
| 7657 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); |
| 7658 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
| 7659 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); |
| 7660 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
| 7661 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7662 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
| 7663 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7664 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7665 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7666 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7667 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7668 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7669 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
| 7670 | |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 7671 | if (IS_MF(bp)) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7672 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 7673 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7674 | } |
| 7675 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7676 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7677 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7678 | /* HC init per function */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7679 | if (bp->common.int_block == INT_BLOCK_HC) { |
| 7680 | if (CHIP_IS_E1H(bp)) { |
| 7681 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
| 7682 | |
| 7683 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); |
| 7684 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); |
| 7685 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7686 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7687 | |
| 7688 | } else { |
| 7689 | int num_segs, sb_idx, prod_offset; |
| 7690 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7691 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
| 7692 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7693 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7694 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
| 7695 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); |
| 7696 | } |
| 7697 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7698 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7699 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7700 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7701 | int dsb_idx = 0; |
| 7702 | /** |
| 7703 | * Producer memory: |
| 7704 | * E2 mode: address 0-135 match to the mapping memory; |
| 7705 | * 136 - PF0 default prod; 137 - PF1 default prod; |
| 7706 | * 138 - PF2 default prod; 139 - PF3 default prod; |
| 7707 | * 140 - PF0 attn prod; 141 - PF1 attn prod; |
| 7708 | * 142 - PF2 attn prod; 143 - PF3 attn prod; |
| 7709 | * 144-147 reserved. |
| 7710 | * |
| 7711 | * E1.5 mode - In backward compatible mode; |
| 7712 | * for non default SB; each even line in the memory |
| 7713 | * holds the U producer and each odd line hold |
| 7714 | * the C producer. The first 128 producers are for |
| 7715 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 |
| 7716 | * producers are for the DSB for each PF. |
| 7717 | * Each PF has five segments: (the order inside each |
| 7718 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; |
| 7719 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; |
| 7720 | * 144-147 attn prods; |
| 7721 | */ |
| 7722 | /* non-default-status-blocks */ |
| 7723 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? |
| 7724 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; |
| 7725 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { |
| 7726 | prod_offset = (bp->igu_base_sb + sb_idx) * |
| 7727 | num_segs; |
| 7728 | |
| 7729 | for (i = 0; i < num_segs; i++) { |
| 7730 | addr = IGU_REG_PROD_CONS_MEMORY + |
| 7731 | (prod_offset + i) * 4; |
| 7732 | REG_WR(bp, addr, 0); |
| 7733 | } |
| 7734 | /* send consumer update with value 0 */ |
| 7735 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, |
| 7736 | USTORM_ID, 0, IGU_INT_NOP, 1); |
| 7737 | bnx2x_igu_clear_sb(bp, |
| 7738 | bp->igu_base_sb + sb_idx); |
| 7739 | } |
| 7740 | |
| 7741 | /* default-status-blocks */ |
| 7742 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? |
| 7743 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; |
| 7744 | |
| 7745 | if (CHIP_MODE_IS_4_PORT(bp)) |
| 7746 | dsb_idx = BP_FUNC(bp); |
| 7747 | else |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 7748 | dsb_idx = BP_VN(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7749 | |
| 7750 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? |
| 7751 | IGU_BC_BASE_DSB_PROD + dsb_idx : |
| 7752 | IGU_NORM_BASE_DSB_PROD + dsb_idx); |
| 7753 | |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 7754 | /* |
| 7755 | * igu prods come in chunks of E1HVN_MAX (4) - |
| 7756 | * does not matters what is the current chip mode |
| 7757 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7758 | for (i = 0; i < (num_segs * E1HVN_MAX); |
| 7759 | i += E1HVN_MAX) { |
| 7760 | addr = IGU_REG_PROD_CONS_MEMORY + |
| 7761 | (prod_offset + i)*4; |
| 7762 | REG_WR(bp, addr, 0); |
| 7763 | } |
| 7764 | /* send consumer update with 0 */ |
| 7765 | if (CHIP_INT_MODE_IS_BC(bp)) { |
| 7766 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7767 | USTORM_ID, 0, IGU_INT_NOP, 1); |
| 7768 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7769 | CSTORM_ID, 0, IGU_INT_NOP, 1); |
| 7770 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7771 | XSTORM_ID, 0, IGU_INT_NOP, 1); |
| 7772 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7773 | TSTORM_ID, 0, IGU_INT_NOP, 1); |
| 7774 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7775 | ATTENTION_ID, 0, IGU_INT_NOP, 1); |
| 7776 | } else { |
| 7777 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7778 | USTORM_ID, 0, IGU_INT_NOP, 1); |
| 7779 | bnx2x_ack_sb(bp, bp->igu_dsb_id, |
| 7780 | ATTENTION_ID, 0, IGU_INT_NOP, 1); |
| 7781 | } |
| 7782 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); |
| 7783 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 7784 | /* !!! These should become driver const once |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7785 | rf-tool supports split-68 const */ |
| 7786 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); |
| 7787 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); |
| 7788 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); |
| 7789 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); |
| 7790 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); |
| 7791 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); |
| 7792 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7793 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7794 | |
Eliezer Tamir | c14423f | 2008-02-28 11:49:42 -0800 | [diff] [blame] | 7795 | /* Reset PCIE errors for debug */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7796 | REG_WR(bp, 0x2114, 0xffffffff); |
| 7797 | REG_WR(bp, 0x2120, 0xffffffff); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7798 | |
Vladislav Zolotarov | f4a6689 | 2010-10-19 05:13:09 +0000 | [diff] [blame] | 7799 | if (CHIP_IS_E1x(bp)) { |
| 7800 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ |
| 7801 | main_mem_base = HC_REG_MAIN_MEMORY + |
| 7802 | BP_PORT(bp) * (main_mem_size * 4); |
| 7803 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; |
| 7804 | main_mem_width = 8; |
| 7805 | |
| 7806 | val = REG_RD(bp, main_mem_prty_clr); |
| 7807 | if (val) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 7808 | DP(NETIF_MSG_HW, |
| 7809 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", |
| 7810 | val); |
Vladislav Zolotarov | f4a6689 | 2010-10-19 05:13:09 +0000 | [diff] [blame] | 7811 | |
| 7812 | /* Clear "false" parity errors in MSI-X table */ |
| 7813 | for (i = main_mem_base; |
| 7814 | i < main_mem_base + main_mem_size * 4; |
| 7815 | i += main_mem_width) { |
| 7816 | bnx2x_read_dmae(bp, i, main_mem_width / 4); |
| 7817 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), |
| 7818 | i, main_mem_width / 4); |
| 7819 | } |
| 7820 | /* Clear HC parity attention */ |
| 7821 | REG_RD(bp, main_mem_prty_clr); |
| 7822 | } |
| 7823 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7824 | #ifdef BNX2X_STOP_ON_ERROR |
| 7825 | /* Enable STORMs SP logging */ |
| 7826 | REG_WR8(bp, BAR_USTRORM_INTMEM + |
| 7827 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); |
| 7828 | REG_WR8(bp, BAR_TSTRORM_INTMEM + |
| 7829 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); |
| 7830 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
| 7831 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); |
| 7832 | REG_WR8(bp, BAR_XSTRORM_INTMEM + |
| 7833 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); |
| 7834 | #endif |
| 7835 | |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 7836 | bnx2x_phy_probe(&bp->link_params); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 7837 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7838 | return 0; |
| 7839 | } |
| 7840 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7841 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
| 7842 | { |
| 7843 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); |
| 7844 | |
| 7845 | if (!CHIP_IS_E1x(bp)) |
| 7846 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, |
| 7847 | sizeof(struct host_hc_status_block_e2)); |
| 7848 | else |
| 7849 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, |
| 7850 | sizeof(struct host_hc_status_block_e1x)); |
| 7851 | |
| 7852 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
| 7853 | } |
| 7854 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 7855 | void bnx2x_free_mem(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7856 | { |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7857 | int i; |
| 7858 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7859 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
| 7860 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); |
| 7861 | |
Ariel Elior | b4cddbd | 2013-08-28 01:13:03 +0300 | [diff] [blame] | 7862 | if (IS_VF(bp)) |
| 7863 | return; |
| 7864 | |
| 7865 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, |
| 7866 | sizeof(struct host_sp_status_block)); |
| 7867 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7868 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 7869 | sizeof(struct bnx2x_slowpath)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7870 | |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7871 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
| 7872 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, |
| 7873 | bp->context[i].size); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7874 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
| 7875 | |
| 7876 | BNX2X_FREE(bp->ilt->lines); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 7877 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 7878 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7879 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7880 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
| 7881 | BCM_PAGE_SIZE * NUM_EQ_PAGES); |
Yuval Mintz | 580d9d0 | 2013-01-23 03:21:51 +0000 | [diff] [blame] | 7882 | |
Yuval Mintz | 0595224 | 2013-05-01 04:27:58 +0000 | [diff] [blame] | 7883 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
| 7884 | |
Yuval Mintz | 580d9d0 | 2013-01-23 03:21:51 +0000 | [diff] [blame] | 7885 | bnx2x_iov_free_mem(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7886 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7887 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7888 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7889 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7890 | if (!CHIP_IS_E1x(bp)) |
| 7891 | /* size = the status block + ramrod buffers */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 7892 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
| 7893 | sizeof(struct host_hc_status_block_e2)); |
| 7894 | else |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7895 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, |
| 7896 | &bp->cnic_sb_mapping, |
| 7897 | sizeof(struct |
| 7898 | host_hc_status_block_e1x)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7899 | |
Yuval Mintz | 2f7a312 | 2013-04-24 01:45:01 +0000 | [diff] [blame] | 7900 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 7901 | /* allocate searcher T2 table, as it wasn't allocated before */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7902 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7903 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7904 | /* write address to which L5 should insert its values */ |
| 7905 | bp->cnic_eth_dev.addr_drv_info_to_mcp = |
| 7906 | &bp->slowpath->drv_info_to_mcp; |
| 7907 | |
| 7908 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) |
| 7909 | goto alloc_mem_err; |
| 7910 | |
| 7911 | return 0; |
| 7912 | |
| 7913 | alloc_mem_err: |
| 7914 | bnx2x_free_mem_cnic(bp); |
| 7915 | BNX2X_ERR("Can't allocate memory\n"); |
| 7916 | return -ENOMEM; |
| 7917 | } |
| 7918 | |
| 7919 | int bnx2x_alloc_mem(struct bnx2x *bp) |
| 7920 | { |
| 7921 | int i, allocated, context_size; |
| 7922 | |
Yuval Mintz | 2f7a312 | 2013-04-24 01:45:01 +0000 | [diff] [blame] | 7923 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 7924 | /* allocate searcher T2 table */ |
| 7925 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7926 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7927 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7928 | sizeof(struct host_sp_status_block)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7929 | |
| 7930 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
| 7931 | sizeof(struct bnx2x_slowpath)); |
| 7932 | |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7933 | /* Allocate memory for CDU context: |
| 7934 | * This memory is allocated separately and not in the generic ILT |
| 7935 | * functions because CDU differs in few aspects: |
| 7936 | * 1. There are multiple entities allocating memory for context - |
| 7937 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls |
| 7938 | * its own ILT lines. |
| 7939 | * 2. Since CDU page-size is not a single 4KB page (which is the case |
| 7940 | * for the other ILT clients), to be efficient we want to support |
| 7941 | * allocation of sub-page-size in the last entry. |
| 7942 | * 3. Context pointers are used by the driver to pass to FW / update |
| 7943 | * the context (for the other ILT clients the pointers are used just to |
| 7944 | * free the memory during unload). |
| 7945 | */ |
| 7946 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 7947 | |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 7948 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
| 7949 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, |
| 7950 | (context_size - allocated)); |
| 7951 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, |
| 7952 | &bp->context[i].cxt_mapping, |
| 7953 | bp->context[i].size); |
| 7954 | allocated += bp->context[i].size; |
| 7955 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7956 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7957 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7958 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
| 7959 | goto alloc_mem_err; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7960 | |
Ariel Elior | 67c431a | 2013-01-01 05:22:36 +0000 | [diff] [blame] | 7961 | if (bnx2x_iov_alloc_mem(bp)) |
| 7962 | goto alloc_mem_err; |
| 7963 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7964 | /* Slow path ring */ |
| 7965 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); |
| 7966 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 7967 | /* EQ */ |
| 7968 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, |
| 7969 | BCM_PAGE_SIZE * NUM_EQ_PAGES); |
Tom Herbert | ab532cf | 2011-02-16 10:27:02 +0000 | [diff] [blame] | 7970 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7971 | return 0; |
| 7972 | |
| 7973 | alloc_mem_err: |
| 7974 | bnx2x_free_mem(bp); |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 7975 | BNX2X_ERR("Can't allocate memory\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7976 | return -ENOMEM; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7977 | } |
| 7978 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7979 | /* |
| 7980 | * Init service functions |
| 7981 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7982 | |
| 7983 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
| 7984 | struct bnx2x_vlan_mac_obj *obj, bool set, |
| 7985 | int mac_type, unsigned long *ramrod_flags) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7986 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7987 | int rc; |
| 7988 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7989 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7990 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7991 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7992 | /* Fill general parameters */ |
| 7993 | ramrod_param.vlan_mac_obj = obj; |
| 7994 | ramrod_param.ramrod_flags = *ramrod_flags; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7995 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 7996 | /* Fill a user request section if needed */ |
| 7997 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { |
| 7998 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 7999 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8000 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8001 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8002 | /* Set the command: ADD or DEL */ |
| 8003 | if (set) |
| 8004 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; |
| 8005 | else |
| 8006 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8007 | } |
| 8008 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8009 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
Yuval Mintz | 7b5342d | 2012-09-11 04:34:14 +0000 | [diff] [blame] | 8010 | |
| 8011 | if (rc == -EEXIST) { |
| 8012 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); |
| 8013 | /* do not treat adding same MAC as error */ |
| 8014 | rc = 0; |
| 8015 | } else if (rc < 0) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8016 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
Yuval Mintz | 7b5342d | 2012-09-11 04:34:14 +0000 | [diff] [blame] | 8017 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8018 | return rc; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8019 | } |
| 8020 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8021 | int bnx2x_del_all_macs(struct bnx2x *bp, |
| 8022 | struct bnx2x_vlan_mac_obj *mac_obj, |
| 8023 | int mac_type, bool wait_for_comp) |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 8024 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8025 | int rc; |
| 8026 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; |
| 8027 | |
| 8028 | /* Wait for completion of requested */ |
| 8029 | if (wait_for_comp) |
| 8030 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
| 8031 | |
| 8032 | /* Set the mac type of addresses we want to clear */ |
| 8033 | __set_bit(mac_type, &vlan_mac_flags); |
| 8034 | |
| 8035 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
| 8036 | if (rc < 0) |
| 8037 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); |
| 8038 | |
| 8039 | return rc; |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 8040 | } |
| 8041 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8042 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 8043 | { |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 8044 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
| 8045 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8046 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
| 8047 | "Ignoring Zero MAC for STORAGE SD mode\n"); |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 8048 | return 0; |
| 8049 | } |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 8050 | |
Dmitry Kravkov | f8f4f61 | 2013-04-24 01:45:00 +0000 | [diff] [blame] | 8051 | if (IS_PF(bp)) { |
| 8052 | unsigned long ramrod_flags = 0; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 8053 | |
Dmitry Kravkov | f8f4f61 | 2013-04-24 01:45:00 +0000 | [diff] [blame] | 8054 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
| 8055 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
| 8056 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, |
| 8057 | &bp->sp_objs->mac_obj, set, |
| 8058 | BNX2X_ETH_MAC, &ramrod_flags); |
| 8059 | } else { /* vf */ |
| 8060 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, |
| 8061 | bp->fp->index, true); |
| 8062 | } |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 8063 | } |
| 8064 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8065 | int bnx2x_setup_leading(struct bnx2x *bp) |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 8066 | { |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 8067 | if (IS_PF(bp)) |
| 8068 | return bnx2x_setup_queue(bp, &bp->fp[0], true); |
| 8069 | else /* VF */ |
| 8070 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8071 | } |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 8072 | |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 8073 | /** |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 8074 | * bnx2x_set_int_mode - configure interrupt mode |
| 8075 | * |
| 8076 | * @bp: driver handle |
| 8077 | * |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 8078 | * In case of MSI-X it will also try to enable MSI-X. |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 8079 | */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8080 | int bnx2x_set_int_mode(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8081 | { |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8082 | int rc = 0; |
| 8083 | |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 8084 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
| 8085 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8086 | return -EINVAL; |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 8087 | } |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8088 | |
Dmitry Kravkov | 9ee3d37 | 2011-06-14 01:33:34 +0000 | [diff] [blame] | 8089 | switch (int_mode) { |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8090 | case BNX2X_INT_MODE_MSIX: |
| 8091 | /* attempt to enable msix */ |
| 8092 | rc = bnx2x_enable_msix(bp); |
| 8093 | |
| 8094 | /* msix attained */ |
| 8095 | if (!rc) |
| 8096 | return 0; |
| 8097 | |
| 8098 | /* vfs use only msix */ |
| 8099 | if (rc && IS_VF(bp)) |
| 8100 | return rc; |
| 8101 | |
| 8102 | /* failed to enable multiple MSI-X */ |
| 8103 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", |
| 8104 | bp->num_queues, |
| 8105 | 1 + bp->num_cnic_queues); |
| 8106 | |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 8107 | /* falling through... */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8108 | case BNX2X_INT_MODE_MSI: |
| 8109 | bnx2x_enable_msi(bp); |
| 8110 | |
| 8111 | /* falling through... */ |
| 8112 | case BNX2X_INT_MODE_INTX: |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8113 | bp->num_ethernet_queues = 1; |
| 8114 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8115 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 8116 | break; |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 8117 | default: |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8118 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
| 8119 | return -EINVAL; |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 8120 | } |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8121 | return 0; |
Eilon Greenstein | ca00392 | 2009-08-12 22:53:28 -0700 | [diff] [blame] | 8122 | } |
| 8123 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 8124 | /* must be called prior to any HW initializations */ |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 8125 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
| 8126 | { |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 8127 | if (IS_SRIOV(bp)) |
| 8128 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 8129 | return L2_ILT_LINES(bp); |
| 8130 | } |
| 8131 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8132 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8133 | { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8134 | struct ilt_client_info *ilt_client; |
| 8135 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
| 8136 | u16 line = 0; |
| 8137 | |
| 8138 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); |
| 8139 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); |
| 8140 | |
| 8141 | /* CDU */ |
| 8142 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; |
| 8143 | ilt_client->client_num = ILT_CLIENT_CDU; |
| 8144 | ilt_client->page_size = CDU_ILT_PAGE_SZ; |
| 8145 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; |
| 8146 | ilt_client->start = line; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8147 | line += bnx2x_cid_ilt_lines(bp); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8148 | |
| 8149 | if (CNIC_SUPPORT(bp)) |
| 8150 | line += CNIC_ILT_LINES; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8151 | ilt_client->end = line - 1; |
| 8152 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8153 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8154 | ilt_client->start, |
| 8155 | ilt_client->end, |
| 8156 | ilt_client->page_size, |
| 8157 | ilt_client->flags, |
| 8158 | ilog2(ilt_client->page_size >> 12)); |
| 8159 | |
| 8160 | /* QM */ |
| 8161 | if (QM_INIT(bp->qm_cid_count)) { |
| 8162 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; |
| 8163 | ilt_client->client_num = ILT_CLIENT_QM; |
| 8164 | ilt_client->page_size = QM_ILT_PAGE_SZ; |
| 8165 | ilt_client->flags = 0; |
| 8166 | ilt_client->start = line; |
| 8167 | |
| 8168 | /* 4 bytes for each cid */ |
| 8169 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, |
| 8170 | QM_ILT_PAGE_SZ); |
| 8171 | |
| 8172 | ilt_client->end = line - 1; |
| 8173 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8174 | DP(NETIF_MSG_IFUP, |
| 8175 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8176 | ilt_client->start, |
| 8177 | ilt_client->end, |
| 8178 | ilt_client->page_size, |
| 8179 | ilt_client->flags, |
| 8180 | ilog2(ilt_client->page_size >> 12)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8181 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8182 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8183 | if (CNIC_SUPPORT(bp)) { |
| 8184 | /* SRC */ |
| 8185 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; |
| 8186 | ilt_client->client_num = ILT_CLIENT_SRC; |
| 8187 | ilt_client->page_size = SRC_ILT_PAGE_SZ; |
| 8188 | ilt_client->flags = 0; |
| 8189 | ilt_client->start = line; |
| 8190 | line += SRC_ILT_LINES; |
| 8191 | ilt_client->end = line - 1; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8192 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8193 | DP(NETIF_MSG_IFUP, |
| 8194 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
| 8195 | ilt_client->start, |
| 8196 | ilt_client->end, |
| 8197 | ilt_client->page_size, |
| 8198 | ilt_client->flags, |
| 8199 | ilog2(ilt_client->page_size >> 12)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8200 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8201 | /* TM */ |
| 8202 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; |
| 8203 | ilt_client->client_num = ILT_CLIENT_TM; |
| 8204 | ilt_client->page_size = TM_ILT_PAGE_SZ; |
| 8205 | ilt_client->flags = 0; |
| 8206 | ilt_client->start = line; |
| 8207 | line += TM_ILT_LINES; |
| 8208 | ilt_client->end = line - 1; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8209 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8210 | DP(NETIF_MSG_IFUP, |
| 8211 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
| 8212 | ilt_client->start, |
| 8213 | ilt_client->end, |
| 8214 | ilt_client->page_size, |
| 8215 | ilt_client->flags, |
| 8216 | ilog2(ilt_client->page_size >> 12)); |
| 8217 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8218 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8219 | BUG_ON(line > ILT_MAX_LINES); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8220 | } |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 8221 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8222 | /** |
| 8223 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters |
| 8224 | * |
| 8225 | * @bp: driver handle |
| 8226 | * @fp: pointer to fastpath |
| 8227 | * @init_params: pointer to parameters structure |
| 8228 | * |
| 8229 | * parameters configured: |
| 8230 | * - HC configuration |
| 8231 | * - Queue's CDU context |
| 8232 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 8233 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8234 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8235 | { |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8236 | u8 cos; |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 8237 | int cxt_index, cxt_offset; |
| 8238 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8239 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
| 8240 | if (!IS_FCOE_FP(fp)) { |
| 8241 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); |
| 8242 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); |
| 8243 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 8244 | /* If HC is supported, enable host coalescing in the transition |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8245 | * to INIT state. |
| 8246 | */ |
| 8247 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); |
| 8248 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); |
| 8249 | |
| 8250 | /* HC rate */ |
| 8251 | init_params->rx.hc_rate = bp->rx_ticks ? |
| 8252 | (1000000 / bp->rx_ticks) : 0; |
| 8253 | init_params->tx.hc_rate = bp->tx_ticks ? |
| 8254 | (1000000 / bp->tx_ticks) : 0; |
| 8255 | |
| 8256 | /* FW SB ID */ |
| 8257 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = |
| 8258 | fp->fw_sb_id; |
| 8259 | |
| 8260 | /* |
| 8261 | * CQ index among the SB indices: FCoE clients uses the default |
| 8262 | * SB, therefore it's different. |
| 8263 | */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8264 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
| 8265 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8266 | } |
| 8267 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8268 | /* set maximum number of COSs supported by this queue */ |
| 8269 | init_params->max_cos = fp->max_cos; |
| 8270 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8271 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8272 | fp->index, init_params->max_cos); |
| 8273 | |
| 8274 | /* set the context pointers queue object */ |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 8275 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 8276 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
| 8277 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 8278 | ILT_PAGE_CIDS); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8279 | init_params->cxts[cos] = |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 8280 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
| 8281 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8282 | } |
| 8283 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 8284 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8285 | struct bnx2x_queue_state_params *q_params, |
| 8286 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, |
| 8287 | int tx_index, bool leading) |
| 8288 | { |
| 8289 | memset(tx_only_params, 0, sizeof(*tx_only_params)); |
| 8290 | |
| 8291 | /* Set the command */ |
| 8292 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
| 8293 | |
| 8294 | /* Set tx-only QUEUE flags: don't zero statistics */ |
| 8295 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); |
| 8296 | |
| 8297 | /* choose the index of the cid to send the slow path on */ |
| 8298 | tx_only_params->cid_index = tx_index; |
| 8299 | |
| 8300 | /* Set general TX_ONLY_SETUP parameters */ |
| 8301 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); |
| 8302 | |
| 8303 | /* Set Tx TX_ONLY_SETUP parameters */ |
| 8304 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); |
| 8305 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8306 | DP(NETIF_MSG_IFUP, |
| 8307 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8308 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
| 8309 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, |
| 8310 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); |
| 8311 | |
| 8312 | /* send the ramrod */ |
| 8313 | return bnx2x_queue_state_change(bp, q_params); |
| 8314 | } |
| 8315 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8316 | /** |
| 8317 | * bnx2x_setup_queue - setup queue |
| 8318 | * |
| 8319 | * @bp: driver handle |
| 8320 | * @fp: pointer to fastpath |
| 8321 | * @leading: is leading |
| 8322 | * |
| 8323 | * This function performs 2 steps in a Queue state machine |
| 8324 | * actually: 1) RESET->INIT 2) INIT->SETUP |
| 8325 | */ |
| 8326 | |
| 8327 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
| 8328 | bool leading) |
| 8329 | { |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8330 | struct bnx2x_queue_state_params q_params = {NULL}; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8331 | struct bnx2x_queue_setup_params *setup_params = |
| 8332 | &q_params.params.setup; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8333 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
| 8334 | &q_params.params.tx_only; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8335 | int rc; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8336 | u8 tx_index; |
| 8337 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8338 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8339 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8340 | /* reset IGU state skip FCoE L2 queue */ |
| 8341 | if (!IS_FCOE_FP(fp)) |
| 8342 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8343 | IGU_INT_ENABLE, 0); |
| 8344 | |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 8345 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8346 | /* We want to wait for completion in this context */ |
| 8347 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8348 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8349 | /* Prepare the INIT parameters */ |
| 8350 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8351 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8352 | /* Set the command */ |
| 8353 | q_params.cmd = BNX2X_Q_CMD_INIT; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8354 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8355 | /* Change the state to INIT */ |
| 8356 | rc = bnx2x_queue_state_change(bp, &q_params); |
| 8357 | if (rc) { |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8358 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8359 | return rc; |
| 8360 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8361 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8362 | DP(NETIF_MSG_IFUP, "init complete\n"); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8363 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8364 | /* Now move the Queue to the SETUP state... */ |
| 8365 | memset(setup_params, 0, sizeof(*setup_params)); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8366 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8367 | /* Set QUEUE flags */ |
| 8368 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8369 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8370 | /* Set general SETUP parameters */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8371 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
| 8372 | FIRST_TX_COS_INDEX); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8373 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8374 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8375 | &setup_params->rxq_params); |
| 8376 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8377 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
| 8378 | FIRST_TX_COS_INDEX); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8379 | |
| 8380 | /* Set the command */ |
| 8381 | q_params.cmd = BNX2X_Q_CMD_SETUP; |
| 8382 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8383 | if (IS_FCOE_FP(fp)) |
| 8384 | bp->fcoe_init = true; |
| 8385 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8386 | /* Change the state to SETUP */ |
| 8387 | rc = bnx2x_queue_state_change(bp, &q_params); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8388 | if (rc) { |
| 8389 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); |
| 8390 | return rc; |
| 8391 | } |
| 8392 | |
| 8393 | /* loop through the relevant tx-only indices */ |
| 8394 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; |
| 8395 | tx_index < fp->max_cos; |
| 8396 | tx_index++) { |
| 8397 | |
| 8398 | /* prepare and send tx-only ramrod*/ |
| 8399 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, |
| 8400 | tx_only_params, tx_index, leading); |
| 8401 | if (rc) { |
| 8402 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", |
| 8403 | fp->index, tx_index); |
| 8404 | return rc; |
| 8405 | } |
| 8406 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8407 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8408 | return rc; |
| 8409 | } |
| 8410 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8411 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8412 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8413 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8414 | struct bnx2x_fp_txdata *txdata; |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8415 | struct bnx2x_queue_state_params q_params = {NULL}; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8416 | int rc, tx_index; |
| 8417 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8418 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8419 | |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 8420 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8421 | /* We want to wait for completion in this context */ |
| 8422 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8423 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8424 | /* close tx-only connections */ |
| 8425 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; |
| 8426 | tx_index < fp->max_cos; |
| 8427 | tx_index++){ |
| 8428 | |
| 8429 | /* ascertain this is a normal queue*/ |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 8430 | txdata = fp->txdata_ptr[tx_index]; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8431 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8432 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8433 | txdata->txq_index); |
| 8434 | |
| 8435 | /* send halt terminate on tx-only connection */ |
| 8436 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
| 8437 | memset(&q_params.params.terminate, 0, |
| 8438 | sizeof(q_params.params.terminate)); |
| 8439 | q_params.params.terminate.cid_index = tx_index; |
| 8440 | |
| 8441 | rc = bnx2x_queue_state_change(bp, &q_params); |
| 8442 | if (rc) |
| 8443 | return rc; |
| 8444 | |
| 8445 | /* send halt terminate on tx-only connection */ |
| 8446 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
| 8447 | memset(&q_params.params.cfc_del, 0, |
| 8448 | sizeof(q_params.params.cfc_del)); |
| 8449 | q_params.params.cfc_del.cid_index = tx_index; |
| 8450 | rc = bnx2x_queue_state_change(bp, &q_params); |
| 8451 | if (rc) |
| 8452 | return rc; |
| 8453 | } |
| 8454 | /* Stop the primary connection: */ |
| 8455 | /* ...halt the connection */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8456 | q_params.cmd = BNX2X_Q_CMD_HALT; |
| 8457 | rc = bnx2x_queue_state_change(bp, &q_params); |
| 8458 | if (rc) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8459 | return rc; |
| 8460 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8461 | /* ...terminate the connection */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8462 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8463 | memset(&q_params.params.terminate, 0, |
| 8464 | sizeof(q_params.params.terminate)); |
| 8465 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8466 | rc = bnx2x_queue_state_change(bp, &q_params); |
| 8467 | if (rc) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8468 | return rc; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8469 | /* ...delete cfc entry */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8470 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8471 | memset(&q_params.params.cfc_del, 0, |
| 8472 | sizeof(q_params.params.cfc_del)); |
| 8473 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8474 | return bnx2x_queue_state_change(bp, &q_params); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8475 | } |
| 8476 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8477 | static void bnx2x_reset_func(struct bnx2x *bp) |
| 8478 | { |
| 8479 | int port = BP_PORT(bp); |
| 8480 | int func = BP_FUNC(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 8481 | int i; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8482 | |
| 8483 | /* Disable the function in the FW */ |
| 8484 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); |
| 8485 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); |
| 8486 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); |
| 8487 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); |
| 8488 | |
| 8489 | /* FP SBs */ |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8490 | for_each_eth_queue(bp, i) { |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8491 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8492 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8493 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
| 8494 | SB_DISABLED); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8495 | } |
| 8496 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8497 | if (CNIC_LOADED(bp)) |
| 8498 | /* CNIC SB */ |
| 8499 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
| 8500 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET |
| 8501 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); |
| 8502 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8503 | /* SP SB */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8504 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 8505 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
| 8506 | SB_DISABLED); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8507 | |
| 8508 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) |
| 8509 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), |
| 8510 | 0); |
Eliezer Tamir | 49d6677 | 2008-02-28 11:53:13 -0800 | [diff] [blame] | 8511 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8512 | /* Configure IGU */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 8513 | if (bp->common.int_block == INT_BLOCK_HC) { |
| 8514 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); |
| 8515 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); |
| 8516 | } else { |
| 8517 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
| 8518 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); |
| 8519 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8520 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8521 | if (CNIC_LOADED(bp)) { |
| 8522 | /* Disable Timer scan */ |
| 8523 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); |
| 8524 | /* |
| 8525 | * Wait for at least 10ms and up to 2 second for the timers |
| 8526 | * scan to complete |
| 8527 | */ |
| 8528 | for (i = 0; i < 200; i++) { |
Yuval Mintz | 639d65b | 2013-06-02 00:06:21 +0000 | [diff] [blame] | 8529 | usleep_range(10000, 20000); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8530 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
| 8531 | break; |
| 8532 | } |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 8533 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8534 | /* Clear ILT */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 8535 | bnx2x_clear_func_ilt(bp, func); |
| 8536 | |
| 8537 | /* Timers workaround bug for E2: if this is vnic-3, |
| 8538 | * we need to set the entire ilt range for this timers. |
| 8539 | */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8540 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 8541 | struct ilt_client_info ilt_cli; |
| 8542 | /* use dummy TM client */ |
| 8543 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); |
| 8544 | ilt_cli.start = 0; |
| 8545 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; |
| 8546 | ilt_cli.client_num = ILT_CLIENT_TM; |
| 8547 | |
| 8548 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); |
| 8549 | } |
| 8550 | |
| 8551 | /* this assumes that reset_port() called before reset_func()*/ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8552 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 8553 | bnx2x_pf_disable(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8554 | |
| 8555 | bp->dmae_ready = 0; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8556 | } |
| 8557 | |
| 8558 | static void bnx2x_reset_port(struct bnx2x *bp) |
| 8559 | { |
| 8560 | int port = BP_PORT(bp); |
| 8561 | u32 val; |
| 8562 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8563 | /* Reset physical Link */ |
| 8564 | bnx2x__link_reset(bp); |
| 8565 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8566 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
| 8567 | |
| 8568 | /* Do not rcv packets to BRB */ |
| 8569 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); |
| 8570 | /* Do not direct rcv packets that are not for MCP to the BRB */ |
| 8571 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : |
| 8572 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); |
| 8573 | |
| 8574 | /* Configure AEU */ |
| 8575 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); |
| 8576 | |
| 8577 | msleep(100); |
| 8578 | /* Check for BRB port occupancy */ |
| 8579 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); |
| 8580 | if (val) |
| 8581 | DP(NETIF_MSG_IFDOWN, |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 8582 | "BRB1 is not empty %d blocks are occupied\n", val); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8583 | |
| 8584 | /* TODO: Close Doorbell port? */ |
| 8585 | } |
| 8586 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 8587 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8588 | { |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8589 | struct bnx2x_func_state_params func_params = {NULL}; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8590 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8591 | /* Prepare parameters for function state transitions */ |
| 8592 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8593 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8594 | func_params.f_obj = &bp->func_obj; |
| 8595 | func_params.cmd = BNX2X_F_CMD_HW_RESET; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8596 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8597 | func_params.params.hw_init.load_phase = load_code; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8598 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8599 | return bnx2x_func_state_change(bp, &func_params); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8600 | } |
| 8601 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 8602 | static int bnx2x_func_stop(struct bnx2x *bp) |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8603 | { |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8604 | struct bnx2x_func_state_params func_params = {NULL}; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8605 | int rc; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8606 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8607 | /* Prepare parameters for function state transitions */ |
| 8608 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); |
| 8609 | func_params.f_obj = &bp->func_obj; |
| 8610 | func_params.cmd = BNX2X_F_CMD_STOP; |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 8611 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8612 | /* |
| 8613 | * Try to stop the function the 'good way'. If fails (in case |
| 8614 | * of a parity error during bnx2x_chip_cleanup()) and we are |
| 8615 | * not in a debug mode, perform a state transaction in order to |
| 8616 | * enable further HW_RESET transaction. |
| 8617 | */ |
| 8618 | rc = bnx2x_func_state_change(bp, &func_params); |
| 8619 | if (rc) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8620 | #ifdef BNX2X_STOP_ON_ERROR |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8621 | return rc; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8622 | #else |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8623 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8624 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
| 8625 | return bnx2x_func_state_change(bp, &func_params); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8626 | #endif |
Yitchak Gertner | 65abd74 | 2008-08-25 15:26:24 -0700 | [diff] [blame] | 8627 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8628 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8629 | return 0; |
| 8630 | } |
Yitchak Gertner | 65abd74 | 2008-08-25 15:26:24 -0700 | [diff] [blame] | 8631 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8632 | /** |
| 8633 | * bnx2x_send_unload_req - request unload mode from the MCP. |
| 8634 | * |
| 8635 | * @bp: driver handle |
| 8636 | * @unload_mode: requested function's unload mode |
| 8637 | * |
| 8638 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. |
| 8639 | */ |
| 8640 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) |
| 8641 | { |
| 8642 | u32 reset_code = 0; |
| 8643 | int port = BP_PORT(bp); |
| 8644 | |
| 8645 | /* Select the UNLOAD request mode */ |
Vladislav Zolotarov | da5a662 | 2008-08-13 15:50:00 -0700 | [diff] [blame] | 8646 | if (unload_mode == UNLOAD_NORMAL) |
| 8647 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; |
Eliezer Tamir | 228241e | 2008-02-28 11:56:57 -0800 | [diff] [blame] | 8648 | |
Eilon Greenstein | 7d0446c | 2009-07-29 00:20:10 +0000 | [diff] [blame] | 8649 | else if (bp->flags & NO_WOL_FLAG) |
Vladislav Zolotarov | da5a662 | 2008-08-13 15:50:00 -0700 | [diff] [blame] | 8650 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
Vladislav Zolotarov | da5a662 | 2008-08-13 15:50:00 -0700 | [diff] [blame] | 8651 | |
Eilon Greenstein | 7d0446c | 2009-07-29 00:20:10 +0000 | [diff] [blame] | 8652 | else if (bp->wol) { |
Vladislav Zolotarov | da5a662 | 2008-08-13 15:50:00 -0700 | [diff] [blame] | 8653 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8654 | u8 *mac_addr = bp->dev->dev_addr; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8655 | u32 val; |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 8656 | u16 pmc; |
| 8657 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8658 | /* The mac address is written to entries 1-4 to |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 8659 | * preserve entry 0 which is used by the PMF |
| 8660 | */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 8661 | u8 entry = (BP_VN(bp) + 1)*8; |
Vladislav Zolotarov | da5a662 | 2008-08-13 15:50:00 -0700 | [diff] [blame] | 8662 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8663 | val = (mac_addr[0] << 8) | mac_addr[1]; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 8664 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8665 | |
| 8666 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | |
| 8667 | (mac_addr[4] << 8) | mac_addr[5]; |
Eilon Greenstein | 3196a88 | 2008-08-13 15:58:49 -0700 | [diff] [blame] | 8668 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8669 | |
David S. Miller | 88c5100 | 2011-10-07 13:38:43 -0400 | [diff] [blame] | 8670 | /* Enable the PME and clear the status */ |
| 8671 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); |
| 8672 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
| 8673 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); |
| 8674 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8675 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
Eliezer Tamir | 228241e | 2008-02-28 11:56:57 -0800 | [diff] [blame] | 8676 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8677 | } else |
| 8678 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; |
| 8679 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8680 | /* Send the request to the MCP */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8681 | if (!BP_NOMCP(bp)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 8682 | reset_code = bnx2x_fw_command(bp, reset_code, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8683 | else { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8684 | int path = BP_PATH(bp); |
| 8685 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8686 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8687 | path, load_count[path][0], load_count[path][1], |
| 8688 | load_count[path][2]); |
| 8689 | load_count[path][0]--; |
| 8690 | load_count[path][1 + port]--; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8691 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8692 | path, load_count[path][0], load_count[path][1], |
| 8693 | load_count[path][2]); |
| 8694 | if (load_count[path][0] == 0) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8695 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8696 | else if (load_count[path][1 + port] == 0) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 8697 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; |
| 8698 | else |
| 8699 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; |
| 8700 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8701 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8702 | return reset_code; |
| 8703 | } |
| 8704 | |
| 8705 | /** |
| 8706 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. |
| 8707 | * |
| 8708 | * @bp: driver handle |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8709 | * @keep_link: true iff link should be kept up |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8710 | */ |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8711 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8712 | { |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8713 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
| 8714 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8715 | /* Report UNLOAD_DONE to MCP */ |
| 8716 | if (!BP_NOMCP(bp)) |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8717 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8718 | } |
| 8719 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 8720 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8721 | { |
| 8722 | int tout = 50; |
| 8723 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
| 8724 | |
| 8725 | if (!bp->port.pmf) |
| 8726 | return 0; |
| 8727 | |
| 8728 | /* |
| 8729 | * (assumption: No Attention from MCP at this stage) |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 8730 | * PMF probably in the middle of TX disable/enable transaction |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8731 | * 1. Sync IRS for default SB |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 8732 | * 2. Sync SP queue - this guarantees us that attention handling started |
| 8733 | * 3. Wait, that TX disable/enable transaction completes |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8734 | * |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 8735 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
| 8736 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already |
| 8737 | * received completion for the transaction the state is TX_STOPPED. |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8738 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
| 8739 | * transaction. |
| 8740 | */ |
| 8741 | |
| 8742 | /* make sure default SB ISR is done */ |
| 8743 | if (msix) |
| 8744 | synchronize_irq(bp->msix_table[0].vector); |
| 8745 | else |
| 8746 | synchronize_irq(bp->pdev->irq); |
| 8747 | |
| 8748 | flush_workqueue(bnx2x_wq); |
| 8749 | |
| 8750 | while (bnx2x_func_get_state(bp, &bp->func_obj) != |
| 8751 | BNX2X_F_STATE_STARTED && tout--) |
| 8752 | msleep(20); |
| 8753 | |
| 8754 | if (bnx2x_func_get_state(bp, &bp->func_obj) != |
| 8755 | BNX2X_F_STATE_STARTED) { |
| 8756 | #ifdef BNX2X_STOP_ON_ERROR |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8757 | BNX2X_ERR("Wrong function state\n"); |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8758 | return -EBUSY; |
| 8759 | #else |
| 8760 | /* |
| 8761 | * Failed to complete the transaction in a "good way" |
| 8762 | * Force both transactions with CLR bit |
| 8763 | */ |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8764 | struct bnx2x_func_state_params func_params = {NULL}; |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8765 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8766 | DP(NETIF_MSG_IFDOWN, |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 8767 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8768 | |
| 8769 | func_params.f_obj = &bp->func_obj; |
| 8770 | __set_bit(RAMROD_DRV_CLR_ONLY, |
| 8771 | &func_params.ramrod_flags); |
| 8772 | |
| 8773 | /* STARTED-->TX_ST0PPED */ |
| 8774 | func_params.cmd = BNX2X_F_CMD_TX_STOP; |
| 8775 | bnx2x_func_state_change(bp, &func_params); |
| 8776 | |
| 8777 | /* TX_ST0PPED-->STARTED */ |
| 8778 | func_params.cmd = BNX2X_F_CMD_TX_START; |
| 8779 | return bnx2x_func_state_change(bp, &func_params); |
| 8780 | #endif |
| 8781 | } |
| 8782 | |
| 8783 | return 0; |
| 8784 | } |
| 8785 | |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8786 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8787 | { |
| 8788 | int port = BP_PORT(bp); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8789 | int i, rc = 0; |
| 8790 | u8 cos; |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 8791 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8792 | u32 reset_code; |
| 8793 | |
| 8794 | /* Wait until tx fastpath tasks complete */ |
| 8795 | for_each_tx_queue(bp, i) { |
| 8796 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
| 8797 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 8798 | for_each_cos_in_tx_queue(fp, cos) |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 8799 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8800 | #ifdef BNX2X_STOP_ON_ERROR |
| 8801 | if (rc) |
| 8802 | return; |
| 8803 | #endif |
| 8804 | } |
| 8805 | |
| 8806 | /* Give HW time to discard old tx messages */ |
Yuval Mintz | 0926d49 | 2013-01-23 03:21:45 +0000 | [diff] [blame] | 8807 | usleep_range(1000, 2000); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8808 | |
| 8809 | /* Clean all ETH MACs */ |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 8810 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
| 8811 | false); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8812 | if (rc < 0) |
| 8813 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); |
| 8814 | |
| 8815 | /* Clean up UC list */ |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 8816 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8817 | true); |
| 8818 | if (rc < 0) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8819 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
| 8820 | rc); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8821 | |
| 8822 | /* Disable LLH */ |
| 8823 | if (!CHIP_IS_E1(bp)) |
| 8824 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); |
| 8825 | |
| 8826 | /* Set "drop all" (stop Rx). |
| 8827 | * We need to take a netif_addr_lock() here in order to prevent |
| 8828 | * a race between the completion code and this code. |
| 8829 | */ |
| 8830 | netif_addr_lock_bh(bp->dev); |
| 8831 | /* Schedule the rx_mode command */ |
| 8832 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) |
| 8833 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); |
| 8834 | else |
| 8835 | bnx2x_set_storm_rx_mode(bp); |
| 8836 | |
| 8837 | /* Cleanup multicast configuration */ |
| 8838 | rparam.mcast_obj = &bp->mcast_obj; |
| 8839 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); |
| 8840 | if (rc < 0) |
| 8841 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); |
| 8842 | |
| 8843 | netif_addr_unlock_bh(bp->dev); |
| 8844 | |
Ariel Elior | f1929b0 | 2013-01-01 05:22:41 +0000 | [diff] [blame] | 8845 | bnx2x_iov_chip_cleanup(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8846 | |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8847 | /* |
| 8848 | * Send the UNLOAD_REQUEST to the MCP. This will return if |
| 8849 | * this function should perform FUNC, PORT or COMMON HW |
| 8850 | * reset. |
| 8851 | */ |
| 8852 | reset_code = bnx2x_send_unload_req(bp, unload_mode); |
| 8853 | |
| 8854 | /* |
| 8855 | * (assumption: No Attention from MCP at this stage) |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 8856 | * PMF probably in the middle of TX disable/enable transaction |
Dmitry Kravkov | 6debea8 | 2011-07-19 01:42:04 +0000 | [diff] [blame] | 8857 | */ |
| 8858 | rc = bnx2x_func_wait_started(bp); |
| 8859 | if (rc) { |
| 8860 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); |
| 8861 | #ifdef BNX2X_STOP_ON_ERROR |
| 8862 | return; |
| 8863 | #endif |
| 8864 | } |
| 8865 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8866 | /* Close multi and leading connections |
| 8867 | * Completions for ramrods are collected in a synchronous way |
| 8868 | */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8869 | for_each_eth_queue(bp, i) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8870 | if (bnx2x_stop_queue(bp, i)) |
| 8871 | #ifdef BNX2X_STOP_ON_ERROR |
| 8872 | return; |
| 8873 | #else |
| 8874 | goto unload_error; |
| 8875 | #endif |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8876 | |
| 8877 | if (CNIC_LOADED(bp)) { |
| 8878 | for_each_cnic_queue(bp, i) |
| 8879 | if (bnx2x_stop_queue(bp, i)) |
| 8880 | #ifdef BNX2X_STOP_ON_ERROR |
| 8881 | return; |
| 8882 | #else |
| 8883 | goto unload_error; |
| 8884 | #endif |
| 8885 | } |
| 8886 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8887 | /* If SP settings didn't get completed so far - something |
| 8888 | * very wrong has happen. |
| 8889 | */ |
| 8890 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) |
| 8891 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); |
| 8892 | |
| 8893 | #ifndef BNX2X_STOP_ON_ERROR |
| 8894 | unload_error: |
| 8895 | #endif |
| 8896 | rc = bnx2x_func_stop(bp); |
| 8897 | if (rc) { |
| 8898 | BNX2X_ERR("Function stop failed!\n"); |
| 8899 | #ifdef BNX2X_STOP_ON_ERROR |
| 8900 | return; |
| 8901 | #endif |
| 8902 | } |
| 8903 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8904 | /* Disable HW interrupts, NAPI */ |
| 8905 | bnx2x_netif_stop(bp, 1); |
Merav Sicron | 26614ba | 2012-08-27 03:26:19 +0000 | [diff] [blame] | 8906 | /* Delete all NAPI objects */ |
| 8907 | bnx2x_del_all_napi(bp); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 8908 | if (CNIC_LOADED(bp)) |
| 8909 | bnx2x_del_all_napi_cnic(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8910 | |
| 8911 | /* Release IRQs */ |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 8912 | bnx2x_free_irq(bp); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 8913 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8914 | /* Reset the chip */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8915 | rc = bnx2x_reset_hw(bp, reset_code); |
| 8916 | if (rc) |
| 8917 | BNX2X_ERR("HW_RESET failed\n"); |
| 8918 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 8919 | /* Report UNLOAD_DONE to MCP */ |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 8920 | bnx2x_send_unload_done(bp, keep_link); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8921 | } |
| 8922 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 8923 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8924 | { |
| 8925 | u32 val; |
| 8926 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8927 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8928 | |
| 8929 | if (CHIP_IS_E1(bp)) { |
| 8930 | int port = BP_PORT(bp); |
| 8931 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
| 8932 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
| 8933 | |
| 8934 | val = REG_RD(bp, addr); |
| 8935 | val &= ~(0x300); |
| 8936 | REG_WR(bp, addr, val); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 8937 | } else { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8938 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
| 8939 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | |
| 8940 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); |
| 8941 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); |
| 8942 | } |
| 8943 | } |
| 8944 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8945 | /* Close gates #2, #3 and #4: */ |
| 8946 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) |
| 8947 | { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 8948 | u32 val; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8949 | |
| 8950 | /* Gates #2 and #4a are closed/opened for "not E1" only */ |
| 8951 | if (!CHIP_IS_E1(bp)) { |
| 8952 | /* #4 */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 8953 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8954 | /* #2 */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 8955 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8956 | } |
| 8957 | |
| 8958 | /* #3 */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 8959 | if (CHIP_IS_E1x(bp)) { |
| 8960 | /* Prevent interrupts from HC on both ports */ |
| 8961 | val = REG_RD(bp, HC_REG_CONFIG_1); |
| 8962 | REG_WR(bp, HC_REG_CONFIG_1, |
| 8963 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : |
| 8964 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); |
| 8965 | |
| 8966 | val = REG_RD(bp, HC_REG_CONFIG_0); |
| 8967 | REG_WR(bp, HC_REG_CONFIG_0, |
| 8968 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : |
| 8969 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); |
| 8970 | } else { |
Jorrit Schippers | d82603c | 2012-12-27 17:33:02 +0100 | [diff] [blame] | 8971 | /* Prevent incoming interrupts in IGU */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 8972 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
| 8973 | |
| 8974 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, |
| 8975 | (!close) ? |
| 8976 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : |
| 8977 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); |
| 8978 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8979 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 8980 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8981 | close ? "closing" : "opening"); |
| 8982 | mmiowb(); |
| 8983 | } |
| 8984 | |
| 8985 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ |
| 8986 | |
| 8987 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) |
| 8988 | { |
| 8989 | /* Do some magic... */ |
| 8990 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
| 8991 | *magic_val = val & SHARED_MF_CLP_MAGIC; |
| 8992 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); |
| 8993 | } |
| 8994 | |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 8995 | /** |
| 8996 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 8997 | * |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 8998 | * @bp: driver handle |
| 8999 | * @magic_val: old value of the `magic' bit. |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9000 | */ |
| 9001 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) |
| 9002 | { |
| 9003 | /* Restore the `magic' bit value... */ |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9004 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
| 9005 | MF_CFG_WR(bp, shared_mf_config.clp_mb, |
| 9006 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); |
| 9007 | } |
| 9008 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 9009 | /** |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 9010 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9011 | * |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 9012 | * @bp: driver handle |
| 9013 | * @magic_val: old value of 'magic' bit. |
| 9014 | * |
| 9015 | * Takes care of CLP configurations. |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9016 | */ |
| 9017 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) |
| 9018 | { |
| 9019 | u32 shmem; |
| 9020 | u32 validity_offset; |
| 9021 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 9022 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9023 | |
| 9024 | /* Set `magic' bit in order to save MF config */ |
| 9025 | if (!CHIP_IS_E1(bp)) |
| 9026 | bnx2x_clp_reset_prep(bp, magic_val); |
| 9027 | |
| 9028 | /* Get shmem offset */ |
| 9029 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); |
Barak Witkowski | c55e771 | 2012-12-02 04:05:46 +0000 | [diff] [blame] | 9030 | validity_offset = |
| 9031 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9032 | |
| 9033 | /* Clear validity map flags */ |
| 9034 | if (shmem > 0) |
| 9035 | REG_WR(bp, shmem + validity_offset, 0); |
| 9036 | } |
| 9037 | |
| 9038 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ |
| 9039 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ |
| 9040 | |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 9041 | /** |
| 9042 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9043 | * |
Dmitry Kravkov | e892067 | 2011-05-04 23:52:40 +0000 | [diff] [blame] | 9044 | * @bp: driver handle |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9045 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 9046 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9047 | { |
| 9048 | /* special handling for emulation and FPGA, |
| 9049 | wait 10 times longer */ |
| 9050 | if (CHIP_REV_IS_SLOW(bp)) |
| 9051 | msleep(MCP_ONE_TIMEOUT*10); |
| 9052 | else |
| 9053 | msleep(MCP_ONE_TIMEOUT); |
| 9054 | } |
| 9055 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9056 | /* |
| 9057 | * initializes bp->common.shmem_base and waits for validity signature to appear |
| 9058 | */ |
| 9059 | static int bnx2x_init_shmem(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9060 | { |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9061 | int cnt = 0; |
| 9062 | u32 val = 0; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9063 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9064 | do { |
| 9065 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); |
| 9066 | if (bp->common.shmem_base) { |
| 9067 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); |
| 9068 | if (val & SHR_MEM_VALIDITY_MB) |
| 9069 | return 0; |
| 9070 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9071 | |
| 9072 | bnx2x_mcp_wait_one(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9073 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9074 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9075 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9076 | BNX2X_ERR("BAD MCP validity signature\n"); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9077 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 9078 | return -ENODEV; |
| 9079 | } |
| 9080 | |
| 9081 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
| 9082 | { |
| 9083 | int rc = bnx2x_init_shmem(bp); |
| 9084 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9085 | /* Restore the `magic' bit value */ |
| 9086 | if (!CHIP_IS_E1(bp)) |
| 9087 | bnx2x_clp_reset_done(bp, magic_val); |
| 9088 | |
| 9089 | return rc; |
| 9090 | } |
| 9091 | |
| 9092 | static void bnx2x_pxp_prep(struct bnx2x *bp) |
| 9093 | { |
| 9094 | if (!CHIP_IS_E1(bp)) { |
| 9095 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); |
| 9096 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9097 | mmiowb(); |
| 9098 | } |
| 9099 | } |
| 9100 | |
| 9101 | /* |
| 9102 | * Reset the whole chip except for: |
| 9103 | * - PCIE core |
| 9104 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by |
| 9105 | * one reset bit) |
| 9106 | * - IGU |
| 9107 | * - MISC (including AEU) |
| 9108 | * - GRC |
| 9109 | * - RBCN, RBCP |
| 9110 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9111 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9112 | { |
| 9113 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9114 | u32 global_bits2, stay_reset2; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9115 | |
| 9116 | /* |
| 9117 | * Bits that have to be set in reset_mask2 if we want to reset 'global' |
| 9118 | * (per chip) blocks. |
| 9119 | */ |
| 9120 | global_bits2 = |
| 9121 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | |
| 9122 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9123 | |
Barak Witkowski | c55e771 | 2012-12-02 04:05:46 +0000 | [diff] [blame] | 9124 | /* Don't reset the following blocks. |
| 9125 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be |
| 9126 | * reset, as in 4 port device they might still be owned |
| 9127 | * by the MCP (there is only one leader per path). |
| 9128 | */ |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9129 | not_reset_mask1 = |
| 9130 | MISC_REGISTERS_RESET_REG_1_RST_HC | |
| 9131 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | |
| 9132 | MISC_REGISTERS_RESET_REG_1_RST_PXP; |
| 9133 | |
| 9134 | not_reset_mask2 = |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9135 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9136 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
| 9137 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | |
| 9138 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | |
| 9139 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | |
| 9140 | MISC_REGISTERS_RESET_REG_2_RST_GRC | |
| 9141 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9142 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
| 9143 | MISC_REGISTERS_RESET_REG_2_RST_ATC | |
Barak Witkowski | c55e771 | 2012-12-02 04:05:46 +0000 | [diff] [blame] | 9144 | MISC_REGISTERS_RESET_REG_2_PGLC | |
| 9145 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | |
| 9146 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | |
| 9147 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | |
| 9148 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | |
| 9149 | MISC_REGISTERS_RESET_REG_2_UMAC0 | |
| 9150 | MISC_REGISTERS_RESET_REG_2_UMAC1; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9151 | |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9152 | /* |
| 9153 | * Keep the following blocks in reset: |
| 9154 | * - all xxMACs are handled by the bnx2x_link code. |
| 9155 | */ |
| 9156 | stay_reset2 = |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9157 | MISC_REGISTERS_RESET_REG_2_XMAC | |
| 9158 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; |
| 9159 | |
| 9160 | /* Full reset masks according to the chip */ |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9161 | reset_mask1 = 0xffffffff; |
| 9162 | |
| 9163 | if (CHIP_IS_E1(bp)) |
| 9164 | reset_mask2 = 0xffff; |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9165 | else if (CHIP_IS_E1H(bp)) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9166 | reset_mask2 = 0x1ffff; |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9167 | else if (CHIP_IS_E2(bp)) |
| 9168 | reset_mask2 = 0xfffff; |
| 9169 | else /* CHIP_IS_E3 */ |
| 9170 | reset_mask2 = 0x3ffffff; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9171 | |
| 9172 | /* Don't reset global blocks unless we need to */ |
| 9173 | if (!global) |
| 9174 | reset_mask2 &= ~global_bits2; |
| 9175 | |
| 9176 | /* |
| 9177 | * In case of attention in the QM, we need to reset PXP |
| 9178 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM |
| 9179 | * because otherwise QM reset would release 'close the gates' shortly |
| 9180 | * before resetting the PXP, then the PSWRQ would send a write |
| 9181 | * request to PGLUE. Then when PXP is reset, PGLUE would try to |
| 9182 | * read the payload data from PSWWR, but PSWWR would not |
| 9183 | * respond. The write queue in PGLUE would stuck, dmae commands |
| 9184 | * would not return. Therefore it's important to reset the second |
| 9185 | * reset register (containing the |
| 9186 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the |
| 9187 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM |
| 9188 | * bit). |
| 9189 | */ |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9190 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
| 9191 | reset_mask2 & (~not_reset_mask2)); |
| 9192 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9193 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
| 9194 | reset_mask1 & (~not_reset_mask1)); |
| 9195 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9196 | barrier(); |
| 9197 | mmiowb(); |
| 9198 | |
Vladislav Zolotarov | 8736c82 | 2011-07-21 07:58:36 +0000 | [diff] [blame] | 9199 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
| 9200 | reset_mask2 & (~stay_reset2)); |
| 9201 | |
| 9202 | barrier(); |
| 9203 | mmiowb(); |
| 9204 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9205 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9206 | mmiowb(); |
| 9207 | } |
| 9208 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9209 | /** |
| 9210 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. |
| 9211 | * It should get cleared in no more than 1s. |
| 9212 | * |
| 9213 | * @bp: driver handle |
| 9214 | * |
| 9215 | * It should get cleared in no more than 1s. Returns 0 if |
| 9216 | * pending writes bit gets cleared. |
| 9217 | */ |
| 9218 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) |
| 9219 | { |
| 9220 | u32 cnt = 1000; |
| 9221 | u32 pend_bits = 0; |
| 9222 | |
| 9223 | do { |
| 9224 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); |
| 9225 | |
| 9226 | if (pend_bits == 0) |
| 9227 | break; |
| 9228 | |
Yuval Mintz | 0926d49 | 2013-01-23 03:21:45 +0000 | [diff] [blame] | 9229 | usleep_range(1000, 2000); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9230 | } while (cnt-- > 0); |
| 9231 | |
| 9232 | if (cnt <= 0) { |
| 9233 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", |
| 9234 | pend_bits); |
| 9235 | return -EBUSY; |
| 9236 | } |
| 9237 | |
| 9238 | return 0; |
| 9239 | } |
| 9240 | |
| 9241 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9242 | { |
| 9243 | int cnt = 1000; |
| 9244 | u32 val = 0; |
| 9245 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 9246 | u32 tags_63_32 = 0; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9247 | |
| 9248 | /* Empty the Tetris buffer, wait for 1s */ |
| 9249 | do { |
| 9250 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); |
| 9251 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); |
| 9252 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); |
| 9253 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); |
| 9254 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); |
Barak Witkowski | c55e771 | 2012-12-02 04:05:46 +0000 | [diff] [blame] | 9255 | if (CHIP_IS_E3(bp)) |
| 9256 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); |
| 9257 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9258 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
| 9259 | ((port_is_idle_0 & 0x1) == 0x1) && |
| 9260 | ((port_is_idle_1 & 0x1) == 0x1) && |
Barak Witkowski | c55e771 | 2012-12-02 04:05:46 +0000 | [diff] [blame] | 9261 | (pgl_exp_rom2 == 0xffffffff) && |
| 9262 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9263 | break; |
Yuval Mintz | 0926d49 | 2013-01-23 03:21:45 +0000 | [diff] [blame] | 9264 | usleep_range(1000, 2000); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9265 | } while (cnt-- > 0); |
| 9266 | |
| 9267 | if (cnt <= 0) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 9268 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
| 9269 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9270 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
| 9271 | pgl_exp_rom2); |
| 9272 | return -EAGAIN; |
| 9273 | } |
| 9274 | |
| 9275 | barrier(); |
| 9276 | |
| 9277 | /* Close gates #2, #3 and #4 */ |
| 9278 | bnx2x_set_234_gates(bp, true); |
| 9279 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9280 | /* Poll for IGU VQs for 57712 and newer chips */ |
| 9281 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) |
| 9282 | return -EAGAIN; |
| 9283 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9284 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
| 9285 | |
| 9286 | /* Clear "unprepared" bit */ |
| 9287 | REG_WR(bp, MISC_REG_UNPREPARED, 0); |
| 9288 | barrier(); |
| 9289 | |
| 9290 | /* Make sure all is written to the chip before the reset */ |
| 9291 | mmiowb(); |
| 9292 | |
| 9293 | /* Wait for 1ms to empty GLUE and PCI-E core queues, |
| 9294 | * PSWHST, GRC and PSWRD Tetris buffer. |
| 9295 | */ |
Yuval Mintz | 0926d49 | 2013-01-23 03:21:45 +0000 | [diff] [blame] | 9296 | usleep_range(1000, 2000); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9297 | |
| 9298 | /* Prepare to chip reset: */ |
| 9299 | /* MCP */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9300 | if (global) |
| 9301 | bnx2x_reset_mcp_prep(bp, &val); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9302 | |
| 9303 | /* PXP */ |
| 9304 | bnx2x_pxp_prep(bp); |
| 9305 | barrier(); |
| 9306 | |
| 9307 | /* reset the chip */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9308 | bnx2x_process_kill_chip_reset(bp, global); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9309 | barrier(); |
| 9310 | |
| 9311 | /* Recover after reset: */ |
| 9312 | /* MCP */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9313 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9314 | return -EAGAIN; |
| 9315 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9316 | /* TBD: Add resetting the NO_MCP mode DB here */ |
| 9317 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9318 | /* Open the gates #2, #3 and #4 */ |
| 9319 | bnx2x_set_234_gates(bp, false); |
| 9320 | |
| 9321 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a |
| 9322 | * reset state, re-enable attentions. */ |
| 9323 | |
| 9324 | return 0; |
| 9325 | } |
| 9326 | |
Merav Sicron | 910cc72 | 2012-11-11 03:56:08 +0000 | [diff] [blame] | 9327 | static int bnx2x_leader_reset(struct bnx2x *bp) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9328 | { |
| 9329 | int rc = 0; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9330 | bool global = bnx2x_reset_is_global(bp); |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9331 | u32 load_code; |
| 9332 | |
| 9333 | /* if not going to reset MCP - load "fake" driver to reset HW while |
| 9334 | * driver is owner of the HW |
| 9335 | */ |
| 9336 | if (!global && !BP_NOMCP(bp)) { |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 9337 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
| 9338 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9339 | if (!load_code) { |
| 9340 | BNX2X_ERR("MCP response failure, aborting\n"); |
| 9341 | rc = -EAGAIN; |
| 9342 | goto exit_leader_reset; |
| 9343 | } |
| 9344 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && |
| 9345 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { |
| 9346 | BNX2X_ERR("MCP unexpected resp, aborting\n"); |
| 9347 | rc = -EAGAIN; |
| 9348 | goto exit_leader_reset2; |
| 9349 | } |
| 9350 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); |
| 9351 | if (!load_code) { |
| 9352 | BNX2X_ERR("MCP response failure, aborting\n"); |
| 9353 | rc = -EAGAIN; |
| 9354 | goto exit_leader_reset2; |
| 9355 | } |
| 9356 | } |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9357 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9358 | /* Try to recover after the failure */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9359 | if (bnx2x_process_kill(bp, global)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 9360 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
| 9361 | BP_PATH(bp)); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9362 | rc = -EAGAIN; |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9363 | goto exit_leader_reset2; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9364 | } |
| 9365 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9366 | /* |
| 9367 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver |
| 9368 | * state. |
| 9369 | */ |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9370 | bnx2x_set_reset_done(bp); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9371 | if (global) |
| 9372 | bnx2x_clear_reset_global(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9373 | |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9374 | exit_leader_reset2: |
| 9375 | /* unload "fake driver" if it was loaded */ |
| 9376 | if (!global && !BP_NOMCP(bp)) { |
| 9377 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); |
| 9378 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); |
| 9379 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9380 | exit_leader_reset: |
| 9381 | bp->is_leader = 0; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9382 | bnx2x_release_leader_lock(bp); |
| 9383 | smp_mb(); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9384 | return rc; |
| 9385 | } |
| 9386 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 9387 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9388 | { |
| 9389 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); |
| 9390 | |
| 9391 | /* Disconnect this device */ |
| 9392 | netif_device_detach(bp->dev); |
| 9393 | |
| 9394 | /* |
| 9395 | * Block ifup for all function on this engine until "process kill" |
| 9396 | * or power cycle. |
| 9397 | */ |
| 9398 | bnx2x_set_reset_in_progress(bp); |
| 9399 | |
| 9400 | /* Shut down the power */ |
| 9401 | bnx2x_set_power_state(bp, PCI_D3hot); |
| 9402 | |
| 9403 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
| 9404 | |
| 9405 | smp_mb(); |
| 9406 | } |
| 9407 | |
| 9408 | /* |
| 9409 | * Assumption: runs under rtnl lock. This together with the fact |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 9410 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9411 | * will never be called when netif_running(bp->dev) is false. |
| 9412 | */ |
| 9413 | static void bnx2x_parity_recover(struct bnx2x *bp) |
| 9414 | { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9415 | bool global = false; |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 9416 | u32 error_recovered, error_unrecovered; |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9417 | bool is_parity; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9418 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9419 | DP(NETIF_MSG_HW, "Handling parity\n"); |
| 9420 | while (1) { |
| 9421 | switch (bp->recovery_state) { |
| 9422 | case BNX2X_RECOVERY_INIT: |
| 9423 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9424 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
| 9425 | WARN_ON(!is_parity); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9426 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9427 | /* Try to get a LEADER_LOCK HW lock */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9428 | if (bnx2x_trylock_leader_lock(bp)) { |
| 9429 | bnx2x_set_reset_in_progress(bp); |
| 9430 | /* |
| 9431 | * Check if there is a global attention and if |
| 9432 | * there was a global attention, set the global |
| 9433 | * reset bit. |
| 9434 | */ |
| 9435 | |
| 9436 | if (global) |
| 9437 | bnx2x_set_reset_global(bp); |
| 9438 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9439 | bp->is_leader = 1; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9440 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9441 | |
| 9442 | /* Stop the driver */ |
| 9443 | /* If interface has been removed - break */ |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 9444 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9445 | return; |
| 9446 | |
| 9447 | bp->recovery_state = BNX2X_RECOVERY_WAIT; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9448 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9449 | /* Ensure "is_leader", MCP command sequence and |
| 9450 | * "recovery_state" update values are seen on other |
| 9451 | * CPUs. |
| 9452 | */ |
| 9453 | smp_mb(); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9454 | break; |
| 9455 | |
| 9456 | case BNX2X_RECOVERY_WAIT: |
| 9457 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); |
| 9458 | if (bp->is_leader) { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9459 | int other_engine = BP_PATH(bp) ? 0 : 1; |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 9460 | bool other_load_status = |
| 9461 | bnx2x_get_load_status(bp, other_engine); |
| 9462 | bool load_status = |
| 9463 | bnx2x_get_load_status(bp, BP_PATH(bp)); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9464 | global = bnx2x_reset_is_global(bp); |
| 9465 | |
| 9466 | /* |
| 9467 | * In case of a parity in a global block, let |
| 9468 | * the first leader that performs a |
| 9469 | * leader_reset() reset the global blocks in |
| 9470 | * order to clear global attentions. Otherwise |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 9471 | * the gates will remain closed for that |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9472 | * engine. |
| 9473 | */ |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 9474 | if (load_status || |
| 9475 | (global && other_load_status)) { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9476 | /* Wait until all other functions get |
| 9477 | * down. |
| 9478 | */ |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9479 | schedule_delayed_work(&bp->sp_rtnl_task, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9480 | HZ/10); |
| 9481 | return; |
| 9482 | } else { |
| 9483 | /* If all other functions got down - |
| 9484 | * try to bring the chip back to |
| 9485 | * normal. In any case it's an exit |
| 9486 | * point for a leader. |
| 9487 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9488 | if (bnx2x_leader_reset(bp)) { |
| 9489 | bnx2x_recovery_failed(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9490 | return; |
| 9491 | } |
| 9492 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9493 | /* If we are here, means that the |
| 9494 | * leader has succeeded and doesn't |
| 9495 | * want to be a leader any more. Try |
| 9496 | * to continue as a none-leader. |
| 9497 | */ |
| 9498 | break; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9499 | } |
| 9500 | } else { /* non-leader */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9501 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9502 | /* Try to get a LEADER_LOCK HW lock as |
| 9503 | * long as a former leader may have |
| 9504 | * been unloaded by the user or |
| 9505 | * released a leadership by another |
| 9506 | * reason. |
| 9507 | */ |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9508 | if (bnx2x_trylock_leader_lock(bp)) { |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9509 | /* I'm a leader now! Restart a |
| 9510 | * switch case. |
| 9511 | */ |
| 9512 | bp->is_leader = 1; |
| 9513 | break; |
| 9514 | } |
| 9515 | |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9516 | schedule_delayed_work(&bp->sp_rtnl_task, |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9517 | HZ/10); |
| 9518 | return; |
| 9519 | |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9520 | } else { |
| 9521 | /* |
| 9522 | * If there was a global attention, wait |
| 9523 | * for it to be cleared. |
| 9524 | */ |
| 9525 | if (bnx2x_reset_is_global(bp)) { |
| 9526 | schedule_delayed_work( |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9527 | &bp->sp_rtnl_task, |
| 9528 | HZ/10); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9529 | return; |
| 9530 | } |
| 9531 | |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 9532 | error_recovered = |
| 9533 | bp->eth_stats.recoverable_error; |
| 9534 | error_unrecovered = |
| 9535 | bp->eth_stats.unrecoverable_error; |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9536 | bp->recovery_state = |
| 9537 | BNX2X_RECOVERY_NIC_LOADING; |
| 9538 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 9539 | error_unrecovered++; |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9540 | netdev_err(bp->dev, |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 9541 | "Recovery failed. Power cycle needed\n"); |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 9542 | /* Disconnect this device */ |
| 9543 | netif_device_detach(bp->dev); |
| 9544 | /* Shut down the power */ |
| 9545 | bnx2x_set_power_state( |
| 9546 | bp, PCI_D3hot); |
| 9547 | smp_mb(); |
| 9548 | } else { |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9549 | bp->recovery_state = |
| 9550 | BNX2X_RECOVERY_DONE; |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 9551 | error_recovered++; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9552 | smp_mb(); |
| 9553 | } |
Ariel Elior | 7a75299 | 2012-01-26 06:01:53 +0000 | [diff] [blame] | 9554 | bp->eth_stats.recoverable_error = |
| 9555 | error_recovered; |
| 9556 | bp->eth_stats.unrecoverable_error = |
| 9557 | error_unrecovered; |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 9558 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9559 | return; |
| 9560 | } |
| 9561 | } |
| 9562 | default: |
| 9563 | return; |
| 9564 | } |
| 9565 | } |
| 9566 | } |
| 9567 | |
Michal Schmidt | 56ad315 | 2012-02-16 02:38:48 +0000 | [diff] [blame] | 9568 | static int bnx2x_close(struct net_device *dev); |
| 9569 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9570 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
| 9571 | * scheduled on a general queue in order to prevent a dead lock. |
| 9572 | */ |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9573 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9574 | { |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9575 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9576 | |
| 9577 | rtnl_lock(); |
| 9578 | |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9579 | if (!netif_running(bp->dev)) { |
| 9580 | rtnl_unlock(); |
| 9581 | return; |
| 9582 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9583 | |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9584 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 9585 | #ifdef BNX2X_STOP_ON_ERROR |
| 9586 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
| 9587 | "you will need to reboot when done\n"); |
| 9588 | goto sp_rtnl_not_reset; |
| 9589 | #endif |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9590 | /* |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9591 | * Clear all pending SP commands as we are going to reset the |
| 9592 | * function anyway. |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 9593 | */ |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9594 | bp->sp_rtnl_state = 0; |
| 9595 | smp_mb(); |
| 9596 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9597 | bnx2x_parity_recover(bp); |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9598 | |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9599 | rtnl_unlock(); |
| 9600 | return; |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9601 | } |
| 9602 | |
| 9603 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { |
Yuval Mintz | 6bf07b8 | 2013-06-02 00:06:20 +0000 | [diff] [blame] | 9604 | #ifdef BNX2X_STOP_ON_ERROR |
| 9605 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
| 9606 | "you will need to reboot when done\n"); |
| 9607 | goto sp_rtnl_not_reset; |
| 9608 | #endif |
| 9609 | |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9610 | /* |
| 9611 | * Clear all pending SP commands as we are going to reset the |
| 9612 | * function anyway. |
| 9613 | */ |
| 9614 | bp->sp_rtnl_state = 0; |
| 9615 | smp_mb(); |
| 9616 | |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 9617 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9618 | bnx2x_nic_load(bp, LOAD_NORMAL); |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9619 | |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9620 | rtnl_unlock(); |
| 9621 | return; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 9622 | } |
Vladislav Zolotarov | b1fb874 | 2011-07-24 03:57:46 +0000 | [diff] [blame] | 9623 | #ifdef BNX2X_STOP_ON_ERROR |
| 9624 | sp_rtnl_not_reset: |
| 9625 | #endif |
| 9626 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) |
| 9627 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 9628 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
| 9629 | bnx2x_after_function_update(bp); |
Ariel Elior | 8304859 | 2011-11-13 04:34:29 +0000 | [diff] [blame] | 9630 | /* |
| 9631 | * in case of fan failure we need to reset id if the "stop on error" |
| 9632 | * debug flag is set, since we trying to prevent permanent overheating |
| 9633 | * damage |
| 9634 | */ |
| 9635 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 9636 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
Ariel Elior | 8304859 | 2011-11-13 04:34:29 +0000 | [diff] [blame] | 9637 | netif_device_detach(bp->dev); |
| 9638 | bnx2x_close(bp->dev); |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9639 | rtnl_unlock(); |
| 9640 | return; |
Ariel Elior | 8304859 | 2011-11-13 04:34:29 +0000 | [diff] [blame] | 9641 | } |
| 9642 | |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 9643 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
| 9644 | DP(BNX2X_MSG_SP, |
| 9645 | "sending set mcast vf pf channel message from rtnl sp-task\n"); |
| 9646 | bnx2x_vfpf_set_mcast(bp->dev); |
| 9647 | } |
Ariel Elior | 78c3bcc | 2013-06-20 17:39:08 +0300 | [diff] [blame] | 9648 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
| 9649 | &bp->sp_rtnl_state)){ |
| 9650 | if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { |
| 9651 | bnx2x_tx_disable(bp); |
| 9652 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); |
| 9653 | } |
| 9654 | } |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 9655 | |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 9656 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
| 9657 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); |
| 9658 | bnx2x_set_rx_mode_inner(bp); |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 9659 | } |
| 9660 | |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 9661 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
| 9662 | &bp->sp_rtnl_state)) |
| 9663 | bnx2x_pf_set_vfs_vlan(bp); |
| 9664 | |
Dmitry Kravkov | 07b4eb3 | 2013-08-19 09:11:57 +0300 | [diff] [blame] | 9665 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) |
| 9666 | bnx2x_dcbx_stop_hw_tx(bp); |
| 9667 | |
| 9668 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state)) |
| 9669 | bnx2x_dcbx_resume_hw_tx(bp); |
| 9670 | |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9671 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
| 9672 | * can be called from other contexts as well) |
| 9673 | */ |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9674 | rtnl_unlock(); |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9675 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 9676 | /* enable SR-IOV if applicable */ |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 9677 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
Ariel Elior | 3c76fef | 2013-03-11 05:17:46 +0000 | [diff] [blame] | 9678 | &bp->sp_rtnl_state)) { |
| 9679 | bnx2x_disable_sriov(bp); |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 9680 | bnx2x_enable_sriov(bp); |
Ariel Elior | 3c76fef | 2013-03-11 05:17:46 +0000 | [diff] [blame] | 9681 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9682 | } |
| 9683 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 9684 | static void bnx2x_period_task(struct work_struct *work) |
| 9685 | { |
| 9686 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); |
| 9687 | |
| 9688 | if (!netif_running(bp->dev)) |
| 9689 | goto period_task_exit; |
| 9690 | |
| 9691 | if (CHIP_REV_IS_SLOW(bp)) { |
| 9692 | BNX2X_ERR("period task called on emulation, ignoring\n"); |
| 9693 | goto period_task_exit; |
| 9694 | } |
| 9695 | |
| 9696 | bnx2x_acquire_phy_lock(bp); |
| 9697 | /* |
| 9698 | * The barrier is needed to ensure the ordering between the writing to |
| 9699 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and |
| 9700 | * the reading here. |
| 9701 | */ |
| 9702 | smp_mb(); |
| 9703 | if (bp->port.pmf) { |
| 9704 | bnx2x_period_func(&bp->link_params, &bp->link_vars); |
| 9705 | |
| 9706 | /* Re-queue task in 1 sec */ |
| 9707 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); |
| 9708 | } |
| 9709 | |
| 9710 | bnx2x_release_phy_lock(bp); |
| 9711 | period_task_exit: |
| 9712 | return; |
| 9713 | } |
| 9714 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 9715 | /* |
| 9716 | * Init service functions |
| 9717 | */ |
| 9718 | |
Ariel Elior | b56e967 | 2013-01-01 05:22:32 +0000 | [diff] [blame] | 9719 | u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
Eilon Greenstein | f1ef27e | 2009-02-12 08:36:23 +0000 | [diff] [blame] | 9720 | { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 9721 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; |
| 9722 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; |
| 9723 | return base + (BP_ABS_FUNC(bp)) * stride; |
Eilon Greenstein | f1ef27e | 2009-02-12 08:36:23 +0000 | [diff] [blame] | 9724 | } |
| 9725 | |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9726 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
| 9727 | struct bnx2x_mac_vals *vals) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 9728 | { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9729 | u32 val, base_addr, offset, mask, reset_reg; |
| 9730 | bool mac_stopped = false; |
| 9731 | u8 port = BP_PORT(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9732 | |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9733 | /* reset addresses as they also mark which values were changed */ |
| 9734 | vals->bmac_addr = 0; |
| 9735 | vals->umac_addr = 0; |
| 9736 | vals->xmac_addr = 0; |
| 9737 | vals->emac_addr = 0; |
| 9738 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9739 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 9740 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9741 | if (!CHIP_IS_E3(bp)) { |
| 9742 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); |
| 9743 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; |
| 9744 | if ((mask & reset_reg) && val) { |
| 9745 | u32 wb_data[2]; |
| 9746 | BNX2X_DEV_INFO("Disable bmac Rx\n"); |
| 9747 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM |
| 9748 | : NIG_REG_INGRESS_BMAC0_MEM; |
| 9749 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL |
| 9750 | : BIGMAC_REGISTER_BMAC_CONTROL; |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 9751 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9752 | /* |
| 9753 | * use rd/wr since we cannot use dmae. This is safe |
| 9754 | * since MCP won't access the bus due to the request |
| 9755 | * to unload, and no function on the path can be |
| 9756 | * loaded at this time. |
| 9757 | */ |
| 9758 | wb_data[0] = REG_RD(bp, base_addr + offset); |
| 9759 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9760 | vals->bmac_addr = base_addr + offset; |
| 9761 | vals->bmac_val[0] = wb_data[0]; |
| 9762 | vals->bmac_val[1] = wb_data[1]; |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9763 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9764 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
| 9765 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9766 | } |
| 9767 | BNX2X_DEV_INFO("Disable emac Rx\n"); |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9768 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
| 9769 | vals->emac_val = REG_RD(bp, vals->emac_addr); |
| 9770 | REG_WR(bp, vals->emac_addr, 0); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9771 | mac_stopped = true; |
| 9772 | } else { |
| 9773 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { |
| 9774 | BNX2X_DEV_INFO("Disable xmac Rx\n"); |
| 9775 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
| 9776 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); |
| 9777 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, |
| 9778 | val & ~(1 << 1)); |
| 9779 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, |
| 9780 | val | (1 << 1)); |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9781 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
| 9782 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); |
| 9783 | REG_WR(bp, vals->xmac_addr, 0); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9784 | mac_stopped = true; |
| 9785 | } |
| 9786 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; |
| 9787 | if (mask & reset_reg) { |
| 9788 | BNX2X_DEV_INFO("Disable umac Rx\n"); |
| 9789 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 9790 | vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; |
| 9791 | vals->umac_val = REG_RD(bp, vals->umac_addr); |
| 9792 | REG_WR(bp, vals->umac_addr, 0); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9793 | mac_stopped = true; |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 9794 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 9795 | } |
Ariel Elior | f16da43 | 2012-01-26 06:01:50 +0000 | [diff] [blame] | 9796 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9797 | if (mac_stopped) |
| 9798 | msleep(20); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9799 | } |
| 9800 | |
| 9801 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) |
| 9802 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) |
| 9803 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) |
| 9804 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) |
| 9805 | |
Greg Kroah-Hartman | 1dd06ae | 2012-12-06 14:30:56 +0000 | [diff] [blame] | 9806 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9807 | { |
| 9808 | u16 rcq, bd; |
| 9809 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); |
| 9810 | |
| 9811 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; |
| 9812 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; |
| 9813 | |
| 9814 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); |
| 9815 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); |
| 9816 | |
| 9817 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", |
| 9818 | port, bd, rcq); |
| 9819 | } |
| 9820 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 9821 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9822 | { |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 9823 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
| 9824 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9825 | if (!rc) { |
| 9826 | BNX2X_ERR("MCP response failure, aborting\n"); |
| 9827 | return -EBUSY; |
| 9828 | } |
| 9829 | |
| 9830 | return 0; |
| 9831 | } |
| 9832 | |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 9833 | static struct bnx2x_prev_path_list * |
| 9834 | bnx2x_prev_path_get_entry(struct bnx2x *bp) |
| 9835 | { |
| 9836 | struct bnx2x_prev_path_list *tmp_list; |
| 9837 | |
| 9838 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) |
| 9839 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && |
| 9840 | bp->pdev->bus->number == tmp_list->bus && |
| 9841 | BP_PATH(bp) == tmp_list->path) |
| 9842 | return tmp_list; |
| 9843 | |
| 9844 | return NULL; |
| 9845 | } |
| 9846 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 9847 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
| 9848 | { |
| 9849 | struct bnx2x_prev_path_list *tmp_list; |
| 9850 | int rc; |
| 9851 | |
| 9852 | rc = down_interruptible(&bnx2x_prev_sem); |
| 9853 | if (rc) { |
| 9854 | BNX2X_ERR("Received %d when tried to take lock\n", rc); |
| 9855 | return rc; |
| 9856 | } |
| 9857 | |
| 9858 | tmp_list = bnx2x_prev_path_get_entry(bp); |
| 9859 | if (tmp_list) { |
| 9860 | tmp_list->aer = 1; |
| 9861 | rc = 0; |
| 9862 | } else { |
| 9863 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", |
| 9864 | BP_PATH(bp)); |
| 9865 | } |
| 9866 | |
| 9867 | up(&bnx2x_prev_sem); |
| 9868 | |
| 9869 | return rc; |
| 9870 | } |
| 9871 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 9872 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9873 | { |
| 9874 | struct bnx2x_prev_path_list *tmp_list; |
| 9875 | int rc = false; |
| 9876 | |
| 9877 | if (down_trylock(&bnx2x_prev_sem)) |
| 9878 | return false; |
| 9879 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 9880 | tmp_list = bnx2x_prev_path_get_entry(bp); |
| 9881 | if (tmp_list) { |
| 9882 | if (tmp_list->aer) { |
| 9883 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", |
| 9884 | BP_PATH(bp)); |
| 9885 | } else { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9886 | rc = true; |
| 9887 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", |
| 9888 | BP_PATH(bp)); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9889 | } |
| 9890 | } |
| 9891 | |
| 9892 | up(&bnx2x_prev_sem); |
| 9893 | |
| 9894 | return rc; |
| 9895 | } |
| 9896 | |
Dmitry Kravkov | 178135c | 2013-05-22 21:21:50 +0000 | [diff] [blame] | 9897 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
| 9898 | { |
| 9899 | struct bnx2x_prev_path_list *entry; |
| 9900 | bool val; |
| 9901 | |
| 9902 | down(&bnx2x_prev_sem); |
| 9903 | |
| 9904 | entry = bnx2x_prev_path_get_entry(bp); |
| 9905 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); |
| 9906 | |
| 9907 | up(&bnx2x_prev_sem); |
| 9908 | |
| 9909 | return val; |
| 9910 | } |
| 9911 | |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 9912 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9913 | { |
| 9914 | struct bnx2x_prev_path_list *tmp_list; |
| 9915 | int rc; |
| 9916 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 9917 | rc = down_interruptible(&bnx2x_prev_sem); |
| 9918 | if (rc) { |
| 9919 | BNX2X_ERR("Received %d when tried to take lock\n", rc); |
| 9920 | return rc; |
| 9921 | } |
| 9922 | |
| 9923 | /* Check whether the entry for this path already exists */ |
| 9924 | tmp_list = bnx2x_prev_path_get_entry(bp); |
| 9925 | if (tmp_list) { |
| 9926 | if (!tmp_list->aer) { |
| 9927 | BNX2X_ERR("Re-Marking the path.\n"); |
| 9928 | } else { |
| 9929 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", |
| 9930 | BP_PATH(bp)); |
| 9931 | tmp_list->aer = 0; |
| 9932 | } |
| 9933 | up(&bnx2x_prev_sem); |
| 9934 | return 0; |
| 9935 | } |
| 9936 | up(&bnx2x_prev_sem); |
| 9937 | |
| 9938 | /* Create an entry for this path and add it */ |
Devendra Naga | ea4b385 | 2012-07-29 03:19:23 +0000 | [diff] [blame] | 9939 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9940 | if (!tmp_list) { |
| 9941 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); |
| 9942 | return -ENOMEM; |
| 9943 | } |
| 9944 | |
| 9945 | tmp_list->bus = bp->pdev->bus->number; |
| 9946 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); |
| 9947 | tmp_list->path = BP_PATH(bp); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 9948 | tmp_list->aer = 0; |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 9949 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9950 | |
| 9951 | rc = down_interruptible(&bnx2x_prev_sem); |
| 9952 | if (rc) { |
| 9953 | BNX2X_ERR("Received %d when tried to take lock\n", rc); |
| 9954 | kfree(tmp_list); |
| 9955 | } else { |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 9956 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
| 9957 | BP_PATH(bp)); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9958 | list_add(&tmp_list->list, &bnx2x_prev_list); |
| 9959 | up(&bnx2x_prev_sem); |
| 9960 | } |
| 9961 | |
| 9962 | return rc; |
| 9963 | } |
| 9964 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 9965 | static int bnx2x_do_flr(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9966 | { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9967 | struct pci_dev *dev = bp->pdev; |
| 9968 | |
Yuval Mintz | 8eee694 | 2012-08-09 04:37:25 +0000 | [diff] [blame] | 9969 | if (CHIP_IS_E1x(bp)) { |
| 9970 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); |
| 9971 | return -EINVAL; |
| 9972 | } |
| 9973 | |
| 9974 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ |
| 9975 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { |
| 9976 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", |
| 9977 | bp->common.bc_ver); |
| 9978 | return -EINVAL; |
| 9979 | } |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9980 | |
Casey Leedom | 8903b9e | 2013-08-06 15:48:38 +0530 | [diff] [blame] | 9981 | if (!pci_wait_for_pending_transaction(dev)) |
| 9982 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9983 | |
Yuval Mintz | 8eee694 | 2012-08-09 04:37:25 +0000 | [diff] [blame] | 9984 | BNX2X_DEV_INFO("Initiating FLR\n"); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9985 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
| 9986 | |
| 9987 | return 0; |
| 9988 | } |
| 9989 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 9990 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 9991 | { |
| 9992 | int rc; |
| 9993 | |
| 9994 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); |
| 9995 | |
| 9996 | /* Test if previous unload process was already finished for this path */ |
| 9997 | if (bnx2x_prev_is_path_marked(bp)) |
| 9998 | return bnx2x_prev_mcp_done(bp); |
| 9999 | |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 10000 | BNX2X_DEV_INFO("Path is unmarked\n"); |
| 10001 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10002 | /* If function has FLR capabilities, and existing FW version matches |
| 10003 | * the one required, then FLR will be sufficient to clean any residue |
| 10004 | * left by previous driver |
| 10005 | */ |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 10006 | rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); |
Yuval Mintz | 8eee694 | 2012-08-09 04:37:25 +0000 | [diff] [blame] | 10007 | |
| 10008 | if (!rc) { |
| 10009 | /* fw version is good */ |
| 10010 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); |
| 10011 | rc = bnx2x_do_flr(bp); |
| 10012 | } |
| 10013 | |
| 10014 | if (!rc) { |
| 10015 | /* FLR was performed */ |
| 10016 | BNX2X_DEV_INFO("FLR successful\n"); |
| 10017 | return 0; |
| 10018 | } |
| 10019 | |
| 10020 | BNX2X_DEV_INFO("Could not FLR\n"); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10021 | |
| 10022 | /* Close the MCP request, return failure*/ |
| 10023 | rc = bnx2x_prev_mcp_done(bp); |
| 10024 | if (!rc) |
| 10025 | rc = BNX2X_PREV_WAIT_NEEDED; |
| 10026 | |
| 10027 | return rc; |
| 10028 | } |
| 10029 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10030 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10031 | { |
| 10032 | u32 reset_reg, tmp_reg = 0, rc; |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 10033 | bool prev_undi = false; |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 10034 | struct bnx2x_mac_vals mac_vals; |
| 10035 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10036 | /* It is possible a previous function received 'common' answer, |
| 10037 | * but hasn't loaded yet, therefore creating a scenario of |
| 10038 | * multiple functions receiving 'common' on the same path. |
| 10039 | */ |
| 10040 | BNX2X_DEV_INFO("Common unload Flow\n"); |
| 10041 | |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 10042 | memset(&mac_vals, 0, sizeof(mac_vals)); |
| 10043 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10044 | if (bnx2x_prev_is_path_marked(bp)) |
| 10045 | return bnx2x_prev_mcp_done(bp); |
| 10046 | |
| 10047 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
| 10048 | |
| 10049 | /* Reset should be performed after BRB is emptied */ |
| 10050 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { |
| 10051 | u32 timer_count = 1000; |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10052 | |
| 10053 | /* Close the MAC Rx to prevent BRB from filling up */ |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 10054 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
| 10055 | |
| 10056 | /* close LLH filters towards the BRB */ |
| 10057 | bnx2x_set_rx_filter(&bp->link_params, 0); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10058 | |
| 10059 | /* Check if the UNDI driver was previously loaded |
| 10060 | * UNDI driver initializes CID offset for normal bell to 0x7 |
| 10061 | */ |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10062 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { |
| 10063 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); |
| 10064 | if (tmp_reg == 0x7) { |
| 10065 | BNX2X_DEV_INFO("UNDI previously loaded\n"); |
| 10066 | prev_undi = true; |
| 10067 | /* clear the UNDI indication */ |
| 10068 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); |
Yuval Mintz | a74801c | 2013-01-14 05:11:41 +0000 | [diff] [blame] | 10069 | /* clear possible idle check errors */ |
| 10070 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10071 | } |
| 10072 | } |
Dmitry Kravkov | d46f7c4 | 2013-04-17 22:49:05 +0000 | [diff] [blame] | 10073 | if (!CHIP_IS_E1x(bp)) |
| 10074 | /* block FW from writing to host */ |
| 10075 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); |
| 10076 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10077 | /* wait until BRB is empty */ |
| 10078 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
| 10079 | while (timer_count) { |
| 10080 | u32 prev_brb = tmp_reg; |
| 10081 | |
| 10082 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
| 10083 | if (!tmp_reg) |
| 10084 | break; |
| 10085 | |
| 10086 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
| 10087 | |
| 10088 | /* reset timer as long as BRB actually gets emptied */ |
| 10089 | if (prev_brb > tmp_reg) |
| 10090 | timer_count = 1000; |
| 10091 | else |
| 10092 | timer_count--; |
| 10093 | |
| 10094 | /* If UNDI resides in memory, manually increment it */ |
| 10095 | if (prev_undi) |
| 10096 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); |
| 10097 | |
| 10098 | udelay(10); |
| 10099 | } |
| 10100 | |
| 10101 | if (!timer_count) |
| 10102 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10103 | } |
| 10104 | |
| 10105 | /* No packets are in the pipeline, path is ready for reset */ |
| 10106 | bnx2x_reset_common(bp); |
| 10107 | |
Barak Witkowski | 1ef1d45 | 2013-01-10 04:53:40 +0000 | [diff] [blame] | 10108 | if (mac_vals.xmac_addr) |
| 10109 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); |
| 10110 | if (mac_vals.umac_addr) |
| 10111 | REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val); |
| 10112 | if (mac_vals.emac_addr) |
| 10113 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); |
| 10114 | if (mac_vals.bmac_addr) { |
| 10115 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); |
| 10116 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); |
| 10117 | } |
| 10118 | |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 10119 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10120 | if (rc) { |
| 10121 | bnx2x_prev_mcp_done(bp); |
| 10122 | return rc; |
| 10123 | } |
| 10124 | |
| 10125 | return bnx2x_prev_mcp_done(bp); |
| 10126 | } |
| 10127 | |
Ariel Elior | 24f0671 | 2012-05-06 07:05:57 +0000 | [diff] [blame] | 10128 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
| 10129 | * and boot began, or when kdump kernel was loaded. Either case would invalidate |
| 10130 | * the addresses of the transaction, resulting in was-error bit set in the pci |
| 10131 | * causing all hw-to-host pcie transactions to timeout. If this happened we want |
| 10132 | * to clear the interrupt which detected this from the pglueb and the was done |
| 10133 | * bit |
| 10134 | */ |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10135 | static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) |
Ariel Elior | 24f0671 | 2012-05-06 07:05:57 +0000 | [diff] [blame] | 10136 | { |
Ariel Elior | 4a25417 | 2012-11-22 07:16:17 +0000 | [diff] [blame] | 10137 | if (!CHIP_IS_E1x(bp)) { |
| 10138 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); |
| 10139 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 10140 | DP(BNX2X_MSG_SP, |
| 10141 | "'was error' bit was found to be set in pglueb upon startup. Clearing\n"); |
Ariel Elior | 4a25417 | 2012-11-22 07:16:17 +0000 | [diff] [blame] | 10142 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, |
| 10143 | 1 << BP_FUNC(bp)); |
| 10144 | } |
Ariel Elior | 24f0671 | 2012-05-06 07:05:57 +0000 | [diff] [blame] | 10145 | } |
| 10146 | } |
| 10147 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10148 | static int bnx2x_prev_unload(struct bnx2x *bp) |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10149 | { |
| 10150 | int time_counter = 10; |
| 10151 | u32 rc, fw, hw_lock_reg, hw_lock_val; |
| 10152 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); |
| 10153 | |
Ariel Elior | 24f0671 | 2012-05-06 07:05:57 +0000 | [diff] [blame] | 10154 | /* clear hw from errors which may have resulted from an interrupted |
| 10155 | * dmae transaction. |
| 10156 | */ |
| 10157 | bnx2x_prev_interrupted_dmae(bp); |
| 10158 | |
| 10159 | /* Release previously held locks */ |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10160 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
| 10161 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : |
| 10162 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); |
| 10163 | |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 10164 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10165 | if (hw_lock_val) { |
| 10166 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { |
| 10167 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); |
| 10168 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, |
| 10169 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); |
| 10170 | } |
| 10171 | |
| 10172 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); |
| 10173 | REG_WR(bp, hw_lock_reg, 0xffffffff); |
| 10174 | } else |
| 10175 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); |
| 10176 | |
| 10177 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { |
| 10178 | BNX2X_DEV_INFO("Release previously held alr\n"); |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 10179 | bnx2x_release_alr(bp); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10180 | } |
| 10181 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10182 | do { |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 10183 | int aer = 0; |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10184 | /* Lock MCP using an unload request */ |
| 10185 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); |
| 10186 | if (!fw) { |
| 10187 | BNX2X_ERR("MCP response failure, aborting\n"); |
| 10188 | rc = -EBUSY; |
| 10189 | break; |
| 10190 | } |
| 10191 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 10192 | rc = down_interruptible(&bnx2x_prev_sem); |
| 10193 | if (rc) { |
| 10194 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", |
| 10195 | rc); |
| 10196 | } else { |
| 10197 | /* If Path is marked by EEH, ignore unload status */ |
| 10198 | aer = !!(bnx2x_prev_path_get_entry(bp) && |
| 10199 | bnx2x_prev_path_get_entry(bp)->aer); |
Yuval Mintz | 60cde81 | 2013-03-26 23:28:03 +0000 | [diff] [blame] | 10200 | up(&bnx2x_prev_sem); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 10201 | } |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 10202 | |
| 10203 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10204 | rc = bnx2x_prev_unload_common(bp); |
| 10205 | break; |
| 10206 | } |
| 10207 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 10208 | /* non-common reply from MCP might require looping */ |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10209 | rc = bnx2x_prev_unload_uncommon(bp); |
| 10210 | if (rc != BNX2X_PREV_WAIT_NEEDED) |
| 10211 | break; |
| 10212 | |
| 10213 | msleep(20); |
| 10214 | } while (--time_counter); |
| 10215 | |
| 10216 | if (!time_counter || rc) { |
| 10217 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); |
| 10218 | rc = -EBUSY; |
| 10219 | } |
| 10220 | |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 10221 | /* Mark function if its port was used to boot from SAN */ |
Dmitry Kravkov | 178135c | 2013-05-22 21:21:50 +0000 | [diff] [blame] | 10222 | if (bnx2x_port_after_undi(bp)) |
Barak Witkowski | c63da99 | 2012-12-05 23:04:03 +0000 | [diff] [blame] | 10223 | bp->link_params.feature_config_flags |= |
| 10224 | FEATURE_CONFIG_BOOT_FROM_SAN; |
| 10225 | |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 10226 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
| 10227 | |
| 10228 | return rc; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10229 | } |
| 10230 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10231 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10232 | { |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 10233 | u32 val, val2, val3, val4, id, boot_mode; |
Eilon Greenstein | 72ce58c | 2008-08-13 15:52:46 -0700 | [diff] [blame] | 10234 | u16 pmc; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10235 | |
| 10236 | /* Get the chip revision id and number. */ |
| 10237 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
| 10238 | val = REG_RD(bp, MISC_REG_CHIP_NUM); |
| 10239 | id = ((val & 0xffff) << 16); |
| 10240 | val = REG_RD(bp, MISC_REG_CHIP_REV); |
| 10241 | id |= ((val & 0xf) << 12); |
Yuval Mintz | f22fdf2 | 2013-03-11 05:17:43 +0000 | [diff] [blame] | 10242 | |
| 10243 | /* Metal is read from PCI regs, but we can't access >=0x400 from |
| 10244 | * the configuration space (so we need to reg_rd) |
| 10245 | */ |
| 10246 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); |
| 10247 | id |= (((val >> 24) & 0xf) << 4); |
Eilon Greenstein | 5a40e08 | 2009-01-14 06:44:04 +0000 | [diff] [blame] | 10248 | val = REG_RD(bp, MISC_REG_BOND_ID); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10249 | id |= (val & 0xf); |
| 10250 | bp->common.chip_id = id; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 10251 | |
Barak Witkowski | 7e8e02d | 2012-04-03 18:41:28 +0000 | [diff] [blame] | 10252 | /* force 57811 according to MISC register */ |
| 10253 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { |
| 10254 | if (CHIP_IS_57810(bp)) |
| 10255 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | |
| 10256 | (bp->common.chip_id & 0x0000FFFF); |
| 10257 | else if (CHIP_IS_57810_MF(bp)) |
| 10258 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | |
| 10259 | (bp->common.chip_id & 0x0000FFFF); |
| 10260 | bp->common.chip_id |= 0x1; |
| 10261 | } |
| 10262 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 10263 | /* Set doorbell size */ |
| 10264 | bp->db_size = (1 << BNX2X_DB_SHIFT); |
| 10265 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10266 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10267 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
| 10268 | if ((val & 1) == 0) |
| 10269 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); |
| 10270 | else |
| 10271 | val = (val >> 1) & 1; |
| 10272 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : |
| 10273 | "2_PORT_MODE"); |
| 10274 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : |
| 10275 | CHIP_2_PORT_MODE; |
| 10276 | |
| 10277 | if (CHIP_MODE_IS_4_PORT(bp)) |
| 10278 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ |
| 10279 | else |
| 10280 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ |
| 10281 | } else { |
| 10282 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ |
| 10283 | bp->pfid = bp->pf_num; /* 0..7 */ |
| 10284 | } |
| 10285 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10286 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
| 10287 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10288 | bp->link_params.chip_id = bp->common.chip_id; |
| 10289 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 10290 | |
Eilon Greenstein | 1c06328 | 2009-02-12 08:36:43 +0000 | [diff] [blame] | 10291 | val = (REG_RD(bp, 0x2874) & 0x55); |
| 10292 | if ((bp->common.chip_id & 0x1) || |
| 10293 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { |
| 10294 | bp->flags |= ONE_PORT_FLAG; |
| 10295 | BNX2X_DEV_INFO("single port device\n"); |
| 10296 | } |
| 10297 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10298 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
Dmitry Kravkov | 754a2f5 | 2011-06-14 01:34:02 +0000 | [diff] [blame] | 10299 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10300 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
| 10301 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", |
| 10302 | bp->common.flash_size, bp->common.flash_size); |
| 10303 | |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 10304 | bnx2x_init_shmem(bp); |
| 10305 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10306 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
| 10307 | MISC_REG_GENERIC_CR_1 : |
| 10308 | MISC_REG_GENERIC_CR_0)); |
Dmitry Kravkov | 1b6e2ce | 2011-05-22 10:11:26 +0000 | [diff] [blame] | 10309 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10310 | bp->link_params.shmem_base = bp->common.shmem_base; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10311 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
Yaniv Rosner | b884d95 | 2012-11-27 03:46:28 +0000 | [diff] [blame] | 10312 | if (SHMEM2_RD(bp, size) > |
| 10313 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) |
| 10314 | bp->link_params.lfa_base = |
| 10315 | REG_RD(bp, bp->common.shmem2_base + |
| 10316 | (u32)offsetof(struct shmem2_region, |
| 10317 | lfa_host_addr[BP_PORT(bp)])); |
| 10318 | else |
| 10319 | bp->link_params.lfa_base = 0; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 10320 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
| 10321 | bp->common.shmem_base, bp->common.shmem2_base); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10322 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10323 | if (!bp->common.shmem_base) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10324 | BNX2X_DEV_INFO("MCP not active\n"); |
| 10325 | bp->flags |= NO_MCP_FLAG; |
| 10326 | return; |
| 10327 | } |
| 10328 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10329 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
Eilon Greenstein | 35b19ba | 2009-02-12 08:36:47 +0000 | [diff] [blame] | 10330 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10331 | |
| 10332 | bp->link_params.hw_led_mode = ((bp->common.hw_config & |
| 10333 | SHARED_HW_CFG_LED_MODE_MASK) >> |
| 10334 | SHARED_HW_CFG_LED_MODE_SHIFT); |
| 10335 | |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 10336 | bp->link_params.feature_config_flags = 0; |
| 10337 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); |
| 10338 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) |
| 10339 | bp->link_params.feature_config_flags |= |
| 10340 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; |
| 10341 | else |
| 10342 | bp->link_params.feature_config_flags &= |
| 10343 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; |
| 10344 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10345 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
| 10346 | bp->common.bc_ver = val; |
| 10347 | BNX2X_DEV_INFO("bc_ver %X\n", val); |
| 10348 | if (val < BNX2X_BC_VER) { |
| 10349 | /* for now only warn |
| 10350 | * later we might need to enforce this */ |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10351 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
| 10352 | BNX2X_BC_VER, val); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10353 | } |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 10354 | bp->link_params.feature_config_flags |= |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10355 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10356 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
| 10357 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10358 | bp->link_params.feature_config_flags |= |
| 10359 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? |
| 10360 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 10361 | bp->link_params.feature_config_flags |= |
| 10362 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? |
| 10363 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 10364 | bp->link_params.feature_config_flags |= |
| 10365 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? |
| 10366 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; |
Yaniv Rosner | 55386fe8 | 2012-11-27 03:46:30 +0000 | [diff] [blame] | 10367 | |
| 10368 | bp->link_params.feature_config_flags |= |
| 10369 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? |
| 10370 | FEATURE_CONFIG_MT_SUPPORT : 0; |
| 10371 | |
Barak Witkowski | 0e898dd | 2011-12-05 21:52:22 +0000 | [diff] [blame] | 10372 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
| 10373 | BC_SUPPORTS_PFC_STATS : 0; |
Yaniv Rosner | 85242ee | 2011-07-05 01:06:53 +0000 | [diff] [blame] | 10374 | |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 10375 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
| 10376 | BC_SUPPORTS_FCOE_FEATURES : 0; |
| 10377 | |
Barak Witkowski | 9876879 | 2012-06-19 07:48:31 +0000 | [diff] [blame] | 10378 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
| 10379 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; |
Barak Witkowsky | a6d3a5b | 2013-08-13 02:25:02 +0300 | [diff] [blame] | 10380 | |
| 10381 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? |
| 10382 | BC_SUPPORTS_RMMOD_CMD : 0; |
| 10383 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 10384 | boot_mode = SHMEM_RD(bp, |
| 10385 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & |
| 10386 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; |
| 10387 | switch (boot_mode) { |
| 10388 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: |
| 10389 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; |
| 10390 | break; |
| 10391 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: |
| 10392 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; |
| 10393 | break; |
| 10394 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: |
| 10395 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; |
| 10396 | break; |
| 10397 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: |
| 10398 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; |
| 10399 | break; |
| 10400 | } |
| 10401 | |
Dmitry Kravkov | f9a3ebb | 2011-05-04 23:49:11 +0000 | [diff] [blame] | 10402 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
| 10403 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
| 10404 | |
Eilon Greenstein | 72ce58c | 2008-08-13 15:52:46 -0700 | [diff] [blame] | 10405 | BNX2X_DEV_INFO("%sWoL capable\n", |
Eilon Greenstein | f537225 | 2009-02-12 08:38:30 +0000 | [diff] [blame] | 10406 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10407 | |
| 10408 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); |
| 10409 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); |
| 10410 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); |
| 10411 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); |
| 10412 | |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 10413 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
| 10414 | val, val2, val3, val4); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10415 | } |
| 10416 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10417 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
| 10418 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) |
| 10419 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10420 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10421 | { |
| 10422 | int pfid = BP_FUNC(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10423 | int igu_sb_id; |
| 10424 | u32 val; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 10425 | u8 fid, igu_sb_cnt = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10426 | |
| 10427 | bp->igu_base_sb = 0xff; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10428 | if (CHIP_INT_MODE_IS_BC(bp)) { |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 10429 | int vn = BP_VN(bp); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 10430 | igu_sb_cnt = bp->igu_sb_cnt; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10431 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
| 10432 | FP_SB_MAX_E1x; |
| 10433 | |
| 10434 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + |
| 10435 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); |
| 10436 | |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 10437 | return 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10438 | } |
| 10439 | |
| 10440 | /* IGU in normal mode - read CAM */ |
| 10441 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; |
| 10442 | igu_sb_id++) { |
| 10443 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); |
| 10444 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) |
| 10445 | continue; |
| 10446 | fid = IGU_FID(val); |
| 10447 | if ((fid & IGU_FID_ENCODE_IS_PF)) { |
| 10448 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) |
| 10449 | continue; |
| 10450 | if (IGU_VEC(val) == 0) |
| 10451 | /* default status block */ |
| 10452 | bp->igu_dsb_id = igu_sb_id; |
| 10453 | else { |
| 10454 | if (bp->igu_base_sb == 0xff) |
| 10455 | bp->igu_base_sb = igu_sb_id; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 10456 | igu_sb_cnt++; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10457 | } |
| 10458 | } |
| 10459 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10460 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 10461 | #ifdef CONFIG_PCI_MSI |
Ariel Elior | 185d4c8 | 2012-09-20 05:26:41 +0000 | [diff] [blame] | 10462 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
| 10463 | * optional that number of CAM entries will not be equal to the value |
| 10464 | * advertised in PCI. |
| 10465 | * Driver should use the minimal value of both as the actual status |
| 10466 | * block count |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10467 | */ |
Ariel Elior | 185d4c8 | 2012-09-20 05:26:41 +0000 | [diff] [blame] | 10468 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 10469 | #endif |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10470 | |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 10471 | if (igu_sb_cnt == 0) { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10472 | BNX2X_ERR("CAM configuration error\n"); |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 10473 | return -EINVAL; |
| 10474 | } |
| 10475 | |
| 10476 | return 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 10477 | } |
| 10478 | |
Greg Kroah-Hartman | 1dd06ae | 2012-12-06 14:30:56 +0000 | [diff] [blame] | 10479 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10480 | { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10481 | int cfg_size = 0, idx, port = BP_PORT(bp); |
| 10482 | |
| 10483 | /* Aggregation of supported attributes of all external phys */ |
| 10484 | bp->port.supported[0] = 0; |
| 10485 | bp->port.supported[1] = 0; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10486 | switch (bp->link_params.num_phys) { |
| 10487 | case 1: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10488 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
| 10489 | cfg_size = 1; |
| 10490 | break; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10491 | case 2: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10492 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
| 10493 | cfg_size = 1; |
| 10494 | break; |
| 10495 | case 3: |
| 10496 | if (bp->link_params.multi_phy_config & |
| 10497 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { |
| 10498 | bp->port.supported[1] = |
| 10499 | bp->link_params.phy[EXT_PHY1].supported; |
| 10500 | bp->port.supported[0] = |
| 10501 | bp->link_params.phy[EXT_PHY2].supported; |
| 10502 | } else { |
| 10503 | bp->port.supported[0] = |
| 10504 | bp->link_params.phy[EXT_PHY1].supported; |
| 10505 | bp->port.supported[1] = |
| 10506 | bp->link_params.phy[EXT_PHY2].supported; |
| 10507 | } |
| 10508 | cfg_size = 2; |
| 10509 | break; |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10510 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10511 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10512 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10513 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10514 | SHMEM_RD(bp, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10515 | dev_info.port_hw_config[port].external_phy_config), |
| 10516 | SHMEM_RD(bp, |
| 10517 | dev_info.port_hw_config[port].external_phy_config2)); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10518 | return; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10519 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10520 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10521 | if (CHIP_IS_E3(bp)) |
| 10522 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); |
| 10523 | else { |
| 10524 | switch (switch_cfg) { |
| 10525 | case SWITCH_CFG_1G: |
| 10526 | bp->port.phy_addr = REG_RD( |
| 10527 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); |
| 10528 | break; |
| 10529 | case SWITCH_CFG_10G: |
| 10530 | bp->port.phy_addr = REG_RD( |
| 10531 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); |
| 10532 | break; |
| 10533 | default: |
| 10534 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", |
| 10535 | bp->port.link_config[0]); |
| 10536 | return; |
| 10537 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10538 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 10539 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10540 | /* mask what we support according to speed_cap_mask per configuration */ |
| 10541 | for (idx = 0; idx < cfg_size; idx++) { |
| 10542 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10543 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10544 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10545 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10546 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10547 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10548 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10549 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10550 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10551 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10552 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10553 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10554 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10555 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10556 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10557 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10558 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10559 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10560 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10561 | SUPPORTED_1000baseT_Full); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10562 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10563 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10564 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10565 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10566 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10567 | if (!(bp->link_params.speed_cap_mask[idx] & |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10568 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10569 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
Yaniv Rosner | b8e0d88 | 2013-06-20 17:39:11 +0300 | [diff] [blame] | 10570 | |
| 10571 | if (!(bp->link_params.speed_cap_mask[idx] & |
| 10572 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) |
| 10573 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10574 | } |
| 10575 | |
| 10576 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
| 10577 | bp->port.supported[1]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10578 | } |
| 10579 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10580 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10581 | { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10582 | u32 link_config, idx, cfg_size = 0; |
| 10583 | bp->port.advertising[0] = 0; |
| 10584 | bp->port.advertising[1] = 0; |
| 10585 | switch (bp->link_params.num_phys) { |
| 10586 | case 1: |
| 10587 | case 2: |
| 10588 | cfg_size = 1; |
| 10589 | break; |
| 10590 | case 3: |
| 10591 | cfg_size = 2; |
| 10592 | break; |
| 10593 | } |
| 10594 | for (idx = 0; idx < cfg_size; idx++) { |
| 10595 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; |
| 10596 | link_config = bp->port.link_config[idx]; |
| 10597 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10598 | case PORT_FEATURE_LINK_SPEED_AUTO: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10599 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
| 10600 | bp->link_params.req_line_speed[idx] = |
| 10601 | SPEED_AUTO_NEG; |
| 10602 | bp->port.advertising[idx] |= |
| 10603 | bp->port.supported[idx]; |
Mintz Yuval | 10bd1f2 | 2012-02-15 02:10:30 +0000 | [diff] [blame] | 10604 | if (bp->link_params.phy[EXT_PHY1].type == |
| 10605 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
| 10606 | bp->port.advertising[idx] |= |
| 10607 | (SUPPORTED_100baseT_Half | |
| 10608 | SUPPORTED_100baseT_Full); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10609 | } else { |
| 10610 | /* force 10G, no AN */ |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10611 | bp->link_params.req_line_speed[idx] = |
| 10612 | SPEED_10000; |
| 10613 | bp->port.advertising[idx] |= |
| 10614 | (ADVERTISED_10000baseT_Full | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10615 | ADVERTISED_FIBRE); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10616 | continue; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10617 | } |
| 10618 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10619 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10620 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10621 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
| 10622 | bp->link_params.req_line_speed[idx] = |
| 10623 | SPEED_10; |
| 10624 | bp->port.advertising[idx] |= |
| 10625 | (ADVERTISED_10baseT_Full | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10626 | ADVERTISED_TP); |
| 10627 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10628 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10629 | link_config, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10630 | bp->link_params.speed_cap_mask[idx]); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10631 | return; |
| 10632 | } |
| 10633 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10634 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10635 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10636 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
| 10637 | bp->link_params.req_line_speed[idx] = |
| 10638 | SPEED_10; |
| 10639 | bp->link_params.req_duplex[idx] = |
| 10640 | DUPLEX_HALF; |
| 10641 | bp->port.advertising[idx] |= |
| 10642 | (ADVERTISED_10baseT_Half | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10643 | ADVERTISED_TP); |
| 10644 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10645 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10646 | link_config, |
| 10647 | bp->link_params.speed_cap_mask[idx]); |
| 10648 | return; |
| 10649 | } |
| 10650 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10651 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10652 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
| 10653 | if (bp->port.supported[idx] & |
| 10654 | SUPPORTED_100baseT_Full) { |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10655 | bp->link_params.req_line_speed[idx] = |
| 10656 | SPEED_100; |
| 10657 | bp->port.advertising[idx] |= |
| 10658 | (ADVERTISED_100baseT_Full | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10659 | ADVERTISED_TP); |
| 10660 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10661 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10662 | link_config, |
| 10663 | bp->link_params.speed_cap_mask[idx]); |
| 10664 | return; |
| 10665 | } |
| 10666 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10667 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10668 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
| 10669 | if (bp->port.supported[idx] & |
| 10670 | SUPPORTED_100baseT_Half) { |
| 10671 | bp->link_params.req_line_speed[idx] = |
| 10672 | SPEED_100; |
| 10673 | bp->link_params.req_duplex[idx] = |
| 10674 | DUPLEX_HALF; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10675 | bp->port.advertising[idx] |= |
| 10676 | (ADVERTISED_100baseT_Half | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10677 | ADVERTISED_TP); |
| 10678 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10679 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10680 | link_config, |
| 10681 | bp->link_params.speed_cap_mask[idx]); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10682 | return; |
| 10683 | } |
| 10684 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10685 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10686 | case PORT_FEATURE_LINK_SPEED_1G: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10687 | if (bp->port.supported[idx] & |
| 10688 | SUPPORTED_1000baseT_Full) { |
| 10689 | bp->link_params.req_line_speed[idx] = |
| 10690 | SPEED_1000; |
| 10691 | bp->port.advertising[idx] |= |
| 10692 | (ADVERTISED_1000baseT_Full | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10693 | ADVERTISED_TP); |
| 10694 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10695 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10696 | link_config, |
| 10697 | bp->link_params.speed_cap_mask[idx]); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10698 | return; |
| 10699 | } |
| 10700 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10701 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10702 | case PORT_FEATURE_LINK_SPEED_2_5G: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10703 | if (bp->port.supported[idx] & |
| 10704 | SUPPORTED_2500baseX_Full) { |
| 10705 | bp->link_params.req_line_speed[idx] = |
| 10706 | SPEED_2500; |
| 10707 | bp->port.advertising[idx] |= |
| 10708 | (ADVERTISED_2500baseX_Full | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10709 | ADVERTISED_TP); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10710 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10711 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10712 | link_config, |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10713 | bp->link_params.speed_cap_mask[idx]); |
| 10714 | return; |
| 10715 | } |
| 10716 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10717 | |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10718 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10719 | if (bp->port.supported[idx] & |
| 10720 | SUPPORTED_10000baseT_Full) { |
| 10721 | bp->link_params.req_line_speed[idx] = |
| 10722 | SPEED_10000; |
| 10723 | bp->port.advertising[idx] |= |
| 10724 | (ADVERTISED_10000baseT_Full | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10725 | ADVERTISED_FIBRE); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10726 | } else { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10727 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10728 | link_config, |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10729 | bp->link_params.speed_cap_mask[idx]); |
| 10730 | return; |
| 10731 | } |
| 10732 | break; |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 10733 | case PORT_FEATURE_LINK_SPEED_20G: |
| 10734 | bp->link_params.req_line_speed[idx] = SPEED_20000; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10735 | |
Yaniv Rosner | 3c9ada2 | 2011-06-14 01:34:12 +0000 | [diff] [blame] | 10736 | break; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10737 | default: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10738 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
Dmitry Kravkov | 754a2f5 | 2011-06-14 01:34:02 +0000 | [diff] [blame] | 10739 | link_config); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10740 | bp->link_params.req_line_speed[idx] = |
| 10741 | SPEED_AUTO_NEG; |
| 10742 | bp->port.advertising[idx] = |
| 10743 | bp->port.supported[idx]; |
| 10744 | break; |
| 10745 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10746 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10747 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10748 | PORT_FEATURE_FLOW_CONTROL_MASK); |
Yuval Mintz | cd1dfce | 2012-12-02 04:05:56 +0000 | [diff] [blame] | 10749 | if (bp->link_params.req_flow_ctrl[idx] == |
| 10750 | BNX2X_FLOW_CTRL_AUTO) { |
| 10751 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) |
| 10752 | bp->link_params.req_flow_ctrl[idx] = |
| 10753 | BNX2X_FLOW_CTRL_NONE; |
| 10754 | else |
| 10755 | bnx2x_set_requested_fc(bp); |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10756 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10757 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10758 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10759 | bp->link_params.req_line_speed[idx], |
| 10760 | bp->link_params.req_duplex[idx], |
| 10761 | bp->link_params.req_flow_ctrl[idx], |
| 10762 | bp->port.advertising[idx]); |
| 10763 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10764 | } |
| 10765 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10766 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 10767 | { |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 10768 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
| 10769 | __be32 mac_lo_be = cpu_to_be32(mac_lo); |
| 10770 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); |
| 10771 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); |
Michael Chan | e665bfd | 2009-10-10 13:46:54 +0000 | [diff] [blame] | 10772 | } |
| 10773 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10774 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10775 | { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10776 | int port = BP_PORT(bp); |
Eilon Greenstein | 589abe3 | 2009-02-12 08:36:55 +0000 | [diff] [blame] | 10777 | u32 config; |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10778 | u32 ext_phy_type, ext_phy_config, eee_mode; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10779 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10780 | bp->link_params.bp = bp; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 10781 | bp->link_params.port = port; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10782 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10783 | bp->link_params.lane_config = |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10784 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 10785 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10786 | bp->link_params.speed_cap_mask[0] = |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10787 | SHMEM_RD(bp, |
Yaniv Rosner | b026192 | 2013-05-01 04:27:57 +0000 | [diff] [blame] | 10788 | dev_info.port_hw_config[port].speed_capability_mask) & |
| 10789 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10790 | bp->link_params.speed_cap_mask[1] = |
| 10791 | SHMEM_RD(bp, |
Yaniv Rosner | b026192 | 2013-05-01 04:27:57 +0000 | [diff] [blame] | 10792 | dev_info.port_hw_config[port].speed_capability_mask2) & |
| 10793 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10794 | bp->port.link_config[0] = |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10795 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
| 10796 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10797 | bp->port.link_config[1] = |
| 10798 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); |
Eilon Greenstein | c2c8b03 | 2009-02-12 08:37:14 +0000 | [diff] [blame] | 10799 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10800 | bp->link_params.multi_phy_config = |
| 10801 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); |
Eilon Greenstein | 3ce2c3f | 2009-02-12 08:37:52 +0000 | [diff] [blame] | 10802 | /* If the device is capable of WoL, set the default state according |
| 10803 | * to the HW |
| 10804 | */ |
Eilon Greenstein | 4d295db | 2009-07-21 05:47:47 +0000 | [diff] [blame] | 10805 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
Eilon Greenstein | 3ce2c3f | 2009-02-12 08:37:52 +0000 | [diff] [blame] | 10806 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
| 10807 | (config & PORT_FEATURE_WOL_ENABLED)); |
| 10808 | |
Yuval Mintz | 4ba7699 | 2013-01-14 05:11:45 +0000 | [diff] [blame] | 10809 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
| 10810 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) |
| 10811 | bp->flags |= NO_ISCSI_FLAG; |
| 10812 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
| 10813 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) |
| 10814 | bp->flags |= NO_FCOE_FLAG; |
| 10815 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 10816 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10817 | bp->link_params.lane_config, |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10818 | bp->link_params.speed_cap_mask[0], |
| 10819 | bp->port.link_config[0]); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10820 | |
Yaniv Rosner | a22f078 | 2010-09-07 11:41:20 +0000 | [diff] [blame] | 10821 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 10822 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10823 | bnx2x_phy_probe(&bp->link_params); |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 10824 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 10825 | |
| 10826 | bnx2x_link_settings_requested(bp); |
| 10827 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 10828 | /* |
| 10829 | * If connected directly, work with the internal PHY, otherwise, work |
| 10830 | * with the external PHY |
| 10831 | */ |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10832 | ext_phy_config = |
| 10833 | SHMEM_RD(bp, |
| 10834 | dev_info.port_hw_config[port].external_phy_config); |
| 10835 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 10836 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10837 | bp->mdio.prtad = bp->port.phy_addr; |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 10838 | |
| 10839 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && |
| 10840 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) |
| 10841 | bp->mdio.prtad = |
Yaniv Rosner | b7737c9 | 2010-09-07 11:40:54 +0000 | [diff] [blame] | 10842 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
Yaniv Rosner | 5866df6 | 2011-01-30 04:15:07 +0000 | [diff] [blame] | 10843 | |
Yuval Mintz | c8c60d8 | 2012-06-06 17:13:07 +0000 | [diff] [blame] | 10844 | /* Configure link feature according to nvram value */ |
| 10845 | eee_mode = (((SHMEM_RD(bp, dev_info. |
| 10846 | port_feature_config[port].eee_power_mode)) & |
| 10847 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> |
| 10848 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); |
| 10849 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { |
| 10850 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | |
| 10851 | EEE_MODE_ENABLE_LPI | |
| 10852 | EEE_MODE_OUTPUT_TIME; |
| 10853 | } else { |
| 10854 | bp->link_params.eee_mode = 0; |
| 10855 | } |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 10856 | } |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 10857 | |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10858 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 10859 | { |
Dmitry Kravkov | 9e62e91 | 2012-03-18 10:33:43 +0000 | [diff] [blame] | 10860 | u32 no_flags = NO_ISCSI_FLAG; |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10861 | int port = BP_PORT(bp); |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 10862 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10863 | drv_lic_key[port].max_iscsi_conn); |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 10864 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 10865 | if (!CNIC_SUPPORT(bp)) { |
| 10866 | bp->flags |= no_flags; |
| 10867 | return; |
| 10868 | } |
| 10869 | |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10870 | /* Get the number of maximum allowed iSCSI connections */ |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 10871 | bp->cnic_eth_dev.max_iscsi_conn = |
| 10872 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> |
| 10873 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; |
| 10874 | |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10875 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
| 10876 | bp->cnic_eth_dev.max_iscsi_conn); |
| 10877 | |
| 10878 | /* |
| 10879 | * If maximum allowed number of connections is zero - |
| 10880 | * disable the feature. |
| 10881 | */ |
| 10882 | if (!bp->cnic_eth_dev.max_iscsi_conn) |
Dmitry Kravkov | 9e62e91 | 2012-03-18 10:33:43 +0000 | [diff] [blame] | 10883 | bp->flags |= no_flags; |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10884 | } |
| 10885 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10886 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
Dmitry Kravkov | 9e62e91 | 2012-03-18 10:33:43 +0000 | [diff] [blame] | 10887 | { |
| 10888 | /* Port info */ |
| 10889 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = |
| 10890 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); |
| 10891 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = |
| 10892 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); |
| 10893 | |
| 10894 | /* Node info */ |
| 10895 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = |
| 10896 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); |
| 10897 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = |
| 10898 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); |
| 10899 | } |
Dmitry Kravkov | 8680019 | 2013-05-27 04:08:29 +0000 | [diff] [blame] | 10900 | |
| 10901 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) |
| 10902 | { |
| 10903 | u8 count = 0; |
| 10904 | |
| 10905 | if (IS_MF(bp)) { |
| 10906 | u8 fid; |
| 10907 | |
| 10908 | /* iterate over absolute function ids for this path: */ |
| 10909 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { |
| 10910 | if (IS_MF_SD(bp)) { |
| 10911 | u32 cfg = MF_CFG_RD(bp, |
| 10912 | func_mf_config[fid].config); |
| 10913 | |
| 10914 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && |
| 10915 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == |
| 10916 | FUNC_MF_CFG_PROTOCOL_FCOE)) |
| 10917 | count++; |
| 10918 | } else { |
| 10919 | u32 cfg = MF_CFG_RD(bp, |
| 10920 | func_ext_config[fid]. |
| 10921 | func_cfg); |
| 10922 | |
| 10923 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && |
| 10924 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) |
| 10925 | count++; |
| 10926 | } |
| 10927 | } |
| 10928 | } else { /* SF */ |
| 10929 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; |
| 10930 | |
| 10931 | for (port = 0; port < port_cnt; port++) { |
| 10932 | u32 lic = SHMEM_RD(bp, |
| 10933 | drv_lic_key[port].max_fcoe_conn) ^ |
| 10934 | FW_ENCODE_32BIT_PATTERN; |
| 10935 | if (lic) |
| 10936 | count++; |
| 10937 | } |
| 10938 | } |
| 10939 | |
| 10940 | return count; |
| 10941 | } |
| 10942 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 10943 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10944 | { |
| 10945 | int port = BP_PORT(bp); |
| 10946 | int func = BP_ABS_FUNC(bp); |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10947 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
| 10948 | drv_lic_key[port].max_fcoe_conn); |
Dmitry Kravkov | 8680019 | 2013-05-27 04:08:29 +0000 | [diff] [blame] | 10949 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10950 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 10951 | if (!CNIC_SUPPORT(bp)) { |
| 10952 | bp->flags |= NO_FCOE_FLAG; |
| 10953 | return; |
| 10954 | } |
| 10955 | |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 10956 | /* Get the number of maximum allowed FCoE connections */ |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 10957 | bp->cnic_eth_dev.max_fcoe_conn = |
| 10958 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> |
| 10959 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; |
| 10960 | |
Bhanu Prakash Gollapudi | 0eb43b4 | 2013-04-22 19:22:30 +0000 | [diff] [blame] | 10961 | /* Calculate the number of maximum allowed FCoE tasks */ |
| 10962 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; |
Dmitry Kravkov | 8680019 | 2013-05-27 04:08:29 +0000 | [diff] [blame] | 10963 | |
| 10964 | /* check if FCoE resources must be shared between different functions */ |
| 10965 | if (num_fcoe_func) |
| 10966 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; |
Bhanu Prakash Gollapudi | 0eb43b4 | 2013-04-22 19:22:30 +0000 | [diff] [blame] | 10967 | |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10968 | /* Read the WWN: */ |
| 10969 | if (!IS_MF(bp)) { |
| 10970 | /* Port info */ |
| 10971 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = |
| 10972 | SHMEM_RD(bp, |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 10973 | dev_info.port_hw_config[port]. |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10974 | fcoe_wwn_port_name_upper); |
| 10975 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = |
| 10976 | SHMEM_RD(bp, |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 10977 | dev_info.port_hw_config[port]. |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10978 | fcoe_wwn_port_name_lower); |
| 10979 | |
| 10980 | /* Node info */ |
| 10981 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = |
| 10982 | SHMEM_RD(bp, |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 10983 | dev_info.port_hw_config[port]. |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10984 | fcoe_wwn_node_name_upper); |
| 10985 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = |
| 10986 | SHMEM_RD(bp, |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 10987 | dev_info.port_hw_config[port]. |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10988 | fcoe_wwn_node_name_lower); |
| 10989 | } else if (!IS_MF_SD(bp)) { |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10990 | /* |
| 10991 | * Read the WWN info only if the FCoE feature is enabled for |
| 10992 | * this function. |
| 10993 | */ |
Yuval Mintz | 7b5342d | 2012-09-11 04:34:14 +0000 | [diff] [blame] | 10994 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
Dmitry Kravkov | 9e62e91 | 2012-03-18 10:33:43 +0000 | [diff] [blame] | 10995 | bnx2x_get_ext_wwn_info(bp, func); |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 10996 | |
Yuval Mintz | 382e513 | 2012-12-02 04:05:51 +0000 | [diff] [blame] | 10997 | } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | 9e62e91 | 2012-03-18 10:33:43 +0000 | [diff] [blame] | 10998 | bnx2x_get_ext_wwn_info(bp, func); |
Yuval Mintz | 382e513 | 2012-12-02 04:05:51 +0000 | [diff] [blame] | 10999 | } |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 11000 | |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 11001 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11002 | |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 11003 | /* |
| 11004 | * If maximum allowed number of connections is zero - |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11005 | * disable the feature. |
| 11006 | */ |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11007 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
| 11008 | bp->flags |= NO_FCOE_FLAG; |
| 11009 | } |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 11010 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11011 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
Dmitry Kravkov | b306f5e | 2011-11-13 04:34:24 +0000 | [diff] [blame] | 11012 | { |
| 11013 | /* |
| 11014 | * iSCSI may be dynamically disabled but reading |
| 11015 | * info here we will decrease memory usage by driver |
| 11016 | * if the feature is disabled for good |
| 11017 | */ |
| 11018 | bnx2x_get_iscsi_info(bp); |
| 11019 | bnx2x_get_fcoe_info(bp); |
| 11020 | } |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11021 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11022 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11023 | { |
| 11024 | u32 val, val2; |
| 11025 | int func = BP_ABS_FUNC(bp); |
| 11026 | int port = BP_PORT(bp); |
| 11027 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
| 11028 | u8 *fip_mac = bp->fip_mac; |
| 11029 | |
| 11030 | if (IS_MF(bp)) { |
| 11031 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or |
| 11032 | * FCoE MAC then the appropriate feature should be disabled. |
| 11033 | * In non SD mode features configuration comes from struct |
| 11034 | * func_ext_config. |
| 11035 | */ |
| 11036 | if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { |
| 11037 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
| 11038 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { |
| 11039 | val2 = MF_CFG_RD(bp, func_ext_config[func]. |
| 11040 | iscsi_mac_addr_upper); |
| 11041 | val = MF_CFG_RD(bp, func_ext_config[func]. |
| 11042 | iscsi_mac_addr_lower); |
| 11043 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
| 11044 | BNX2X_DEV_INFO |
| 11045 | ("Read iSCSI MAC: %pM\n", iscsi_mac); |
| 11046 | } else { |
| 11047 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
| 11048 | } |
| 11049 | |
| 11050 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { |
| 11051 | val2 = MF_CFG_RD(bp, func_ext_config[func]. |
| 11052 | fcoe_mac_addr_upper); |
| 11053 | val = MF_CFG_RD(bp, func_ext_config[func]. |
| 11054 | fcoe_mac_addr_lower); |
| 11055 | bnx2x_set_mac_buf(fip_mac, val, val2); |
| 11056 | BNX2X_DEV_INFO |
| 11057 | ("Read FCoE L2 MAC: %pM\n", fip_mac); |
| 11058 | } else { |
| 11059 | bp->flags |= NO_FCOE_FLAG; |
| 11060 | } |
| 11061 | |
| 11062 | bp->mf_ext_config = cfg; |
| 11063 | |
| 11064 | } else { /* SD MODE */ |
| 11065 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
| 11066 | /* use primary mac as iscsi mac */ |
| 11067 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); |
| 11068 | |
| 11069 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); |
| 11070 | BNX2X_DEV_INFO |
| 11071 | ("Read iSCSI MAC: %pM\n", iscsi_mac); |
| 11072 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { |
| 11073 | /* use primary mac as fip mac */ |
| 11074 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); |
| 11075 | BNX2X_DEV_INFO("SD FCoE MODE\n"); |
| 11076 | BNX2X_DEV_INFO |
| 11077 | ("Read FIP MAC: %pM\n", fip_mac); |
| 11078 | } |
| 11079 | } |
| 11080 | |
Yuval Mintz | 82594f8 | 2013-03-11 05:17:51 +0000 | [diff] [blame] | 11081 | /* If this is a storage-only interface, use SAN mac as |
| 11082 | * primary MAC. Notice that for SD this is already the case, |
| 11083 | * as the SAN mac was copied from the primary MAC. |
| 11084 | */ |
| 11085 | if (IS_MF_FCOE_AFEX(bp)) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11086 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11087 | } else { |
| 11088 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
| 11089 | iscsi_mac_upper); |
| 11090 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
| 11091 | iscsi_mac_lower); |
| 11092 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
| 11093 | |
| 11094 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
| 11095 | fcoe_fip_mac_upper); |
| 11096 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
| 11097 | fcoe_fip_mac_lower); |
| 11098 | bnx2x_set_mac_buf(fip_mac, val, val2); |
| 11099 | } |
| 11100 | |
| 11101 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
| 11102 | if (!is_valid_ether_addr(iscsi_mac)) { |
| 11103 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
| 11104 | memset(iscsi_mac, 0, ETH_ALEN); |
| 11105 | } |
| 11106 | |
| 11107 | /* Disable FCoE if MAC configuration is invalid. */ |
| 11108 | if (!is_valid_ether_addr(fip_mac)) { |
| 11109 | bp->flags |= NO_FCOE_FLAG; |
| 11110 | memset(bp->fip_mac, 0, ETH_ALEN); |
| 11111 | } |
| 11112 | } |
| 11113 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11114 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11115 | { |
| 11116 | u32 val, val2; |
| 11117 | int func = BP_ABS_FUNC(bp); |
| 11118 | int port = BP_PORT(bp); |
| 11119 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11120 | /* Zero primary MAC configuration */ |
| 11121 | memset(bp->dev->dev_addr, 0, ETH_ALEN); |
| 11122 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11123 | if (BP_NOMCP(bp)) { |
| 11124 | BNX2X_ERROR("warning: random MAC workaround active\n"); |
Danny Kukawka | 7ce5d22 | 2012-02-15 06:45:40 +0000 | [diff] [blame] | 11125 | eth_hw_addr_random(bp->dev); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11126 | } else if (IS_MF(bp)) { |
| 11127 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); |
| 11128 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); |
| 11129 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && |
| 11130 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) |
| 11131 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); |
| 11132 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11133 | if (CNIC_SUPPORT(bp)) |
| 11134 | bnx2x_get_cnic_mac_hwinfo(bp); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11135 | } else { |
| 11136 | /* in SF read MACs from port configuration */ |
| 11137 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); |
| 11138 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); |
| 11139 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); |
| 11140 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11141 | if (CNIC_SUPPORT(bp)) |
| 11142 | bnx2x_get_cnic_mac_hwinfo(bp); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11143 | } |
| 11144 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 11145 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); |
Michael Chan | 37b091b | 2009-10-10 13:46:55 +0000 | [diff] [blame] | 11146 | |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 11147 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11148 | dev_err(&bp->pdev->dev, |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11149 | "bad Ethernet MAC address configuration: %pM\n" |
| 11150 | "change it manually before bringing up the appropriate network interface\n", |
Joe Perches | 0f9dad1 | 2011-08-14 12:16:19 +0000 | [diff] [blame] | 11151 | bp->dev->dev_addr); |
Yuval Mintz | 7964211 | 2012-12-02 04:05:50 +0000 | [diff] [blame] | 11152 | } |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11153 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11154 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
Yuval Mintz | 7964211 | 2012-12-02 04:05:50 +0000 | [diff] [blame] | 11155 | { |
| 11156 | int tmp; |
| 11157 | u32 cfg; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11158 | |
Yuval Mintz | aeeddb8 | 2013-08-19 09:11:59 +0300 | [diff] [blame] | 11159 | if (IS_VF(bp)) |
| 11160 | return 0; |
| 11161 | |
Yuval Mintz | 7964211 | 2012-12-02 04:05:50 +0000 | [diff] [blame] | 11162 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
| 11163 | /* Take function: tmp = func */ |
| 11164 | tmp = BP_ABS_FUNC(bp); |
| 11165 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); |
| 11166 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); |
| 11167 | } else { |
| 11168 | /* Take port: tmp = port */ |
| 11169 | tmp = BP_PORT(bp); |
| 11170 | cfg = SHMEM_RD(bp, |
| 11171 | dev_info.port_hw_config[tmp].generic_features); |
| 11172 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); |
| 11173 | } |
| 11174 | return cfg; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11175 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11176 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11177 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11178 | { |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11179 | int /*abs*/func = BP_ABS_FUNC(bp); |
David S. Miller | b8ee832 | 2011-04-17 16:56:12 -0700 | [diff] [blame] | 11180 | int vn; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11181 | u32 val = 0; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11182 | int rc = 0; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11183 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11184 | bnx2x_get_common_hwinfo(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11185 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11186 | /* |
| 11187 | * initialize IGU parameters |
| 11188 | */ |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11189 | if (CHIP_IS_E1x(bp)) { |
| 11190 | bp->common.int_block = INT_BLOCK_HC; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11191 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11192 | bp->igu_dsb_id = DEF_SB_IGU_ID; |
| 11193 | bp->igu_base_sb = 0; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11194 | } else { |
| 11195 | bp->common.int_block = INT_BLOCK_IGU; |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 11196 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 11197 | /* do not allow device reset during IGU info processing */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 11198 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
| 11199 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11200 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11201 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11202 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11203 | int tout = 5000; |
| 11204 | |
| 11205 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); |
| 11206 | |
| 11207 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); |
| 11208 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); |
| 11209 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); |
| 11210 | |
| 11211 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { |
| 11212 | tout--; |
Yuval Mintz | 0926d49 | 2013-01-23 03:21:45 +0000 | [diff] [blame] | 11213 | usleep_range(1000, 2000); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11214 | } |
| 11215 | |
| 11216 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { |
| 11217 | dev_err(&bp->pdev->dev, |
| 11218 | "FORCING Normal Mode failed!!!\n"); |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 11219 | bnx2x_release_hw_lock(bp, |
| 11220 | HW_LOCK_RESOURCE_RESET); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11221 | return -EPERM; |
| 11222 | } |
| 11223 | } |
| 11224 | |
| 11225 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
| 11226 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11227 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
| 11228 | } else |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11229 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11230 | |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 11231 | rc = bnx2x_get_igu_cam_info(bp); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 11232 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
Barak Witkowski | 9b341bb | 2012-12-02 04:05:52 +0000 | [diff] [blame] | 11233 | if (rc) |
| 11234 | return rc; |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11235 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11236 | |
| 11237 | /* |
| 11238 | * set base FW non-default (fast path) status block id, this value is |
| 11239 | * used to initialize the fw_sb_id saved on the fp/queue structure to |
| 11240 | * determine the id used by the FW. |
| 11241 | */ |
| 11242 | if (CHIP_IS_E1x(bp)) |
| 11243 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); |
| 11244 | else /* |
| 11245 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of |
| 11246 | * the same queue are indicated on the same IGU SB). So we prefer |
| 11247 | * FW and IGU SBs to be the same value. |
| 11248 | */ |
| 11249 | bp->base_fw_ndsb = bp->igu_base_sb; |
| 11250 | |
| 11251 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" |
| 11252 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, |
| 11253 | bp->igu_sb_cnt, bp->base_fw_ndsb); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11254 | |
| 11255 | /* |
| 11256 | * Initialize MF configuration |
| 11257 | */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11258 | |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 11259 | bp->mf_ov = 0; |
| 11260 | bp->mf_mode = 0; |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 11261 | vn = BP_VN(bp); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11262 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11263 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11264 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
| 11265 | bp->common.shmem2_base, SHMEM2_RD(bp, size), |
| 11266 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); |
| 11267 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11268 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
| 11269 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); |
| 11270 | else |
| 11271 | bp->common.mf_cfg_base = bp->common.shmem_base + |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11272 | offsetof(struct shmem_region, func_mb) + |
| 11273 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11274 | /* |
| 11275 | * get mf configuration: |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 11276 | * 1. Existence of MF configuration |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11277 | * 2. MAC address must be legal (check only upper bytes) |
| 11278 | * for Switch-Independent mode; |
| 11279 | * OVLAN must be legal for Switch-Dependent mode |
| 11280 | * 3. SF_MODE configures specific MF mode |
| 11281 | */ |
| 11282 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { |
| 11283 | /* get mf configuration */ |
| 11284 | val = SHMEM_RD(bp, |
| 11285 | dev_info.shared_feature_config.config); |
| 11286 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11287 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11288 | switch (val) { |
| 11289 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: |
| 11290 | val = MF_CFG_RD(bp, func_mf_config[func]. |
| 11291 | mac_upper); |
| 11292 | /* check for legal mac (upper bytes)*/ |
| 11293 | if (val != 0xffff) { |
| 11294 | bp->mf_mode = MULTI_FUNCTION_SI; |
| 11295 | bp->mf_config[vn] = MF_CFG_RD(bp, |
| 11296 | func_mf_config[func].config); |
| 11297 | } else |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11298 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11299 | break; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 11300 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
| 11301 | if ((!CHIP_IS_E1x(bp)) && |
| 11302 | (MF_CFG_RD(bp, func_mf_config[func]. |
| 11303 | mac_upper) != 0xffff) && |
| 11304 | (SHMEM2_HAS(bp, |
| 11305 | afex_driver_support))) { |
| 11306 | bp->mf_mode = MULTI_FUNCTION_AFEX; |
| 11307 | bp->mf_config[vn] = MF_CFG_RD(bp, |
| 11308 | func_mf_config[func].config); |
| 11309 | } else { |
| 11310 | BNX2X_DEV_INFO("can not configure afex mode\n"); |
| 11311 | } |
| 11312 | break; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11313 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
| 11314 | /* get OV configuration */ |
| 11315 | val = MF_CFG_RD(bp, |
| 11316 | func_mf_config[FUNC_0].e1hov_tag); |
| 11317 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; |
| 11318 | |
| 11319 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
| 11320 | bp->mf_mode = MULTI_FUNCTION_SD; |
| 11321 | bp->mf_config[vn] = MF_CFG_RD(bp, |
| 11322 | func_mf_config[func].config); |
| 11323 | } else |
Dmitry Kravkov | 754a2f5 | 2011-06-14 01:34:02 +0000 | [diff] [blame] | 11324 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11325 | break; |
Ariel Elior | 3786b94 | 2013-03-11 05:17:44 +0000 | [diff] [blame] | 11326 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
| 11327 | bp->mf_config[vn] = 0; |
| 11328 | break; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11329 | default: |
| 11330 | /* Unknown configuration: reset mf_config */ |
| 11331 | bp->mf_config[vn] = 0; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11332 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11333 | } |
| 11334 | } |
| 11335 | |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 11336 | BNX2X_DEV_INFO("%s function mode\n", |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 11337 | IS_MF(bp) ? "multi" : "single"); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 11338 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11339 | switch (bp->mf_mode) { |
| 11340 | case MULTI_FUNCTION_SD: |
| 11341 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & |
| 11342 | FUNC_MF_CFG_E1HOV_TAG_MASK; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 11343 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
Dmitry Kravkov | fb3bff1 | 2010-10-06 03:26:40 +0000 | [diff] [blame] | 11344 | bp->mf_ov = val; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11345 | bp->path_has_ovlan = true; |
| 11346 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11347 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
| 11348 | func, bp->mf_ov, bp->mf_ov); |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 11349 | } else { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11350 | dev_err(&bp->pdev->dev, |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11351 | "No valid MF OV for func %d, aborting\n", |
| 11352 | func); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11353 | return -EPERM; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11354 | } |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11355 | break; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 11356 | case MULTI_FUNCTION_AFEX: |
| 11357 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); |
| 11358 | break; |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11359 | case MULTI_FUNCTION_SI: |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11360 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
| 11361 | func); |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11362 | break; |
| 11363 | default: |
| 11364 | if (vn) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11365 | dev_err(&bp->pdev->dev, |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11366 | "VN %d is in a single function mode, aborting\n", |
| 11367 | vn); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11368 | return -EPERM; |
Eilon Greenstein | 2691d51 | 2009-08-12 08:22:08 +0000 | [diff] [blame] | 11369 | } |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11370 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11371 | } |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11372 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11373 | /* check if other port on the path needs ovlan: |
| 11374 | * Since MF configuration is shared between ports |
| 11375 | * Possible mixed modes are only |
| 11376 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} |
| 11377 | */ |
| 11378 | if (CHIP_MODE_IS_4_PORT(bp) && |
| 11379 | !bp->path_has_ovlan && |
| 11380 | !IS_MF(bp) && |
| 11381 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { |
| 11382 | u8 other_port = !BP_PORT(bp); |
| 11383 | u8 other_func = BP_PATH(bp) + 2*other_port; |
| 11384 | val = MF_CFG_RD(bp, |
| 11385 | func_mf_config[other_func].e1hov_tag); |
| 11386 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) |
| 11387 | bp->path_has_ovlan = true; |
| 11388 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11389 | } |
| 11390 | |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11391 | /* adjust igu_sb_cnt to MF for E1x */ |
| 11392 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11393 | bp->igu_sb_cnt /= E1HVN_MAX; |
| 11394 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11395 | /* port info */ |
| 11396 | bnx2x_get_port_hwinfo(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11397 | |
Dmitry Kravkov | 0793f83f | 2010-12-01 12:39:28 -0800 | [diff] [blame] | 11398 | /* Get MAC addresses */ |
| 11399 | bnx2x_get_mac_hwinfo(bp); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11400 | |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11401 | bnx2x_get_cnic_info(bp); |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 11402 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11403 | return rc; |
| 11404 | } |
| 11405 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11406 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11407 | { |
| 11408 | int cnt, i, block_end, rodi; |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11409 | char vpd_start[BNX2X_VPD_LEN+1]; |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11410 | char str_id_reg[VENDOR_ID_LEN+1]; |
| 11411 | char str_id_cap[VENDOR_ID_LEN+1]; |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11412 | char *vpd_data; |
| 11413 | char *vpd_extended_data = NULL; |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11414 | u8 len; |
| 11415 | |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11416 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11417 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
| 11418 | |
| 11419 | if (cnt < BNX2X_VPD_LEN) |
| 11420 | goto out_not_found; |
| 11421 | |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11422 | /* VPD RO tag should be first tag after identifier string, hence |
| 11423 | * we should be able to find it in first BNX2X_VPD_LEN chars |
| 11424 | */ |
| 11425 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11426 | PCI_VPD_LRDT_RO_DATA); |
| 11427 | if (i < 0) |
| 11428 | goto out_not_found; |
| 11429 | |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11430 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11431 | pci_vpd_lrdt_size(&vpd_start[i]); |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11432 | |
| 11433 | i += PCI_VPD_LRDT_TAG_SIZE; |
| 11434 | |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11435 | if (block_end > BNX2X_VPD_LEN) { |
| 11436 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); |
| 11437 | if (vpd_extended_data == NULL) |
| 11438 | goto out_not_found; |
| 11439 | |
| 11440 | /* read rest of vpd image into vpd_extended_data */ |
| 11441 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); |
| 11442 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, |
| 11443 | block_end - BNX2X_VPD_LEN, |
| 11444 | vpd_extended_data + BNX2X_VPD_LEN); |
| 11445 | if (cnt < (block_end - BNX2X_VPD_LEN)) |
| 11446 | goto out_not_found; |
| 11447 | vpd_data = vpd_extended_data; |
| 11448 | } else |
| 11449 | vpd_data = vpd_start; |
| 11450 | |
| 11451 | /* now vpd_data holds full vpd content in both cases */ |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11452 | |
| 11453 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, |
| 11454 | PCI_VPD_RO_KEYWORD_MFR_ID); |
| 11455 | if (rodi < 0) |
| 11456 | goto out_not_found; |
| 11457 | |
| 11458 | len = pci_vpd_info_field_size(&vpd_data[rodi]); |
| 11459 | |
| 11460 | if (len != VENDOR_ID_LEN) |
| 11461 | goto out_not_found; |
| 11462 | |
| 11463 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 11464 | |
| 11465 | /* vendor specific info */ |
| 11466 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); |
| 11467 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); |
| 11468 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || |
| 11469 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { |
| 11470 | |
| 11471 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, |
| 11472 | PCI_VPD_RO_KEYWORD_VENDOR0); |
| 11473 | if (rodi >= 0) { |
| 11474 | len = pci_vpd_info_field_size(&vpd_data[rodi]); |
| 11475 | |
| 11476 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 11477 | |
| 11478 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { |
| 11479 | memcpy(bp->fw_ver, &vpd_data[rodi], len); |
| 11480 | bp->fw_ver[len] = ' '; |
| 11481 | } |
| 11482 | } |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11483 | kfree(vpd_extended_data); |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11484 | return; |
| 11485 | } |
| 11486 | out_not_found: |
Barak Witkowski | fcdf95c | 2011-12-14 00:14:53 +0000 | [diff] [blame] | 11487 | kfree(vpd_extended_data); |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11488 | return; |
| 11489 | } |
| 11490 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11491 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11492 | { |
| 11493 | u32 flags = 0; |
| 11494 | |
| 11495 | if (CHIP_REV_IS_FPGA(bp)) |
| 11496 | SET_FLAGS(flags, MODE_FPGA); |
| 11497 | else if (CHIP_REV_IS_EMUL(bp)) |
| 11498 | SET_FLAGS(flags, MODE_EMUL); |
| 11499 | else |
| 11500 | SET_FLAGS(flags, MODE_ASIC); |
| 11501 | |
| 11502 | if (CHIP_MODE_IS_4_PORT(bp)) |
| 11503 | SET_FLAGS(flags, MODE_PORT4); |
| 11504 | else |
| 11505 | SET_FLAGS(flags, MODE_PORT2); |
| 11506 | |
| 11507 | if (CHIP_IS_E2(bp)) |
| 11508 | SET_FLAGS(flags, MODE_E2); |
| 11509 | else if (CHIP_IS_E3(bp)) { |
| 11510 | SET_FLAGS(flags, MODE_E3); |
| 11511 | if (CHIP_REV(bp) == CHIP_REV_Ax) |
| 11512 | SET_FLAGS(flags, MODE_E3_A0); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11513 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
| 11514 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11515 | } |
| 11516 | |
| 11517 | if (IS_MF(bp)) { |
| 11518 | SET_FLAGS(flags, MODE_MF); |
| 11519 | switch (bp->mf_mode) { |
| 11520 | case MULTI_FUNCTION_SD: |
| 11521 | SET_FLAGS(flags, MODE_MF_SD); |
| 11522 | break; |
| 11523 | case MULTI_FUNCTION_SI: |
| 11524 | SET_FLAGS(flags, MODE_MF_SI); |
| 11525 | break; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 11526 | case MULTI_FUNCTION_AFEX: |
| 11527 | SET_FLAGS(flags, MODE_MF_AFEX); |
| 11528 | break; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11529 | } |
| 11530 | } else |
| 11531 | SET_FLAGS(flags, MODE_SF); |
| 11532 | |
| 11533 | #if defined(__LITTLE_ENDIAN) |
| 11534 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); |
| 11535 | #else /*(__BIG_ENDIAN)*/ |
| 11536 | SET_FLAGS(flags, MODE_BIG_ENDIAN); |
| 11537 | #endif |
| 11538 | INIT_MODE_FLAGS(bp) = flags; |
| 11539 | } |
| 11540 | |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 11541 | static int bnx2x_init_bp(struct bnx2x *bp) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11542 | { |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11543 | int func; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11544 | int rc; |
| 11545 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11546 | mutex_init(&bp->port.phy_mutex); |
Eilon Greenstein | c4ff7cb | 2009-10-15 00:18:27 -0700 | [diff] [blame] | 11547 | mutex_init(&bp->fw_mb_mutex); |
David S. Miller | bb7e95c | 2010-07-27 21:01:35 -0700 | [diff] [blame] | 11548 | spin_lock_init(&bp->stats_lock); |
Dmitry Kravkov | 507393e | 2013-08-13 02:24:59 +0300 | [diff] [blame] | 11549 | sema_init(&bp->stats_sema, 1); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11550 | |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 11551 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 11552 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 11553 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11554 | if (IS_PF(bp)) { |
| 11555 | rc = bnx2x_get_hwinfo(bp); |
| 11556 | if (rc) |
| 11557 | return rc; |
| 11558 | } else { |
Ariel Elior | e09b74d | 2013-05-27 04:08:26 +0000 | [diff] [blame] | 11559 | eth_zero_addr(bp->dev->dev_addr); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11560 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11561 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11562 | bnx2x_set_modes_bitmap(bp); |
| 11563 | |
| 11564 | rc = bnx2x_alloc_mem_bp(bp); |
| 11565 | if (rc) |
| 11566 | return rc; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11567 | |
Vladislav Zolotarov | 34f24c7 | 2010-04-19 01:13:23 +0000 | [diff] [blame] | 11568 | bnx2x_read_fwinfo(bp); |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 11569 | |
| 11570 | func = BP_FUNC(bp); |
| 11571 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11572 | /* need to reset chip if undi was active */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11573 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 11574 | /* init fw_seq */ |
| 11575 | bp->fw_seq = |
| 11576 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
| 11577 | DRV_MSG_SEQ_NUMBER_MASK; |
| 11578 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); |
| 11579 | |
| 11580 | bnx2x_prev_unload(bp); |
| 11581 | } |
| 11582 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11583 | if (CHIP_REV_IS_FPGA(bp)) |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 11584 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11585 | |
| 11586 | if (BP_NOMCP(bp) && (func == 0)) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11587 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11588 | |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 11589 | bp->disable_tpa = disable_tpa; |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 11590 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 11591 | |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 11592 | /* Set TPA flags */ |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 11593 | if (bp->disable_tpa) { |
Dmitry Kravkov | 621b4d6 | 2012-02-20 09:59:08 +0000 | [diff] [blame] | 11594 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 11595 | bp->dev->features &= ~NETIF_F_LRO; |
| 11596 | } else { |
Dmitry Kravkov | 621b4d6 | 2012-02-20 09:59:08 +0000 | [diff] [blame] | 11597 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 11598 | bp->dev->features |= NETIF_F_LRO; |
| 11599 | } |
| 11600 | |
Eilon Greenstein | a18f512 | 2009-08-12 08:23:26 +0000 | [diff] [blame] | 11601 | if (CHIP_IS_E1(bp)) |
| 11602 | bp->dropless_fc = 0; |
| 11603 | else |
Yuval Mintz | 7964211 | 2012-12-02 04:05:50 +0000 | [diff] [blame] | 11604 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
Eilon Greenstein | a18f512 | 2009-08-12 08:23:26 +0000 | [diff] [blame] | 11605 | |
Eilon Greenstein | 8d5726c | 2009-02-12 08:37:19 +0000 | [diff] [blame] | 11606 | bp->mrrs = mrrs; |
Vladislav Zolotarov | 7a9b255 | 2008-06-23 20:34:36 -0700 | [diff] [blame] | 11607 | |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 11608 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11609 | if (IS_VF(bp)) |
| 11610 | bp->rx_ring_size = MAX_RX_AVAIL; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11611 | |
Eilon Greenstein | 7d323bf | 2009-11-09 06:09:35 +0000 | [diff] [blame] | 11612 | /* make sure that the numbers are in the right granularity */ |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 11613 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
| 11614 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11615 | |
Michal Schmidt | fc54363 | 2012-02-14 09:05:46 +0000 | [diff] [blame] | 11616 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11617 | |
| 11618 | init_timer(&bp->timer); |
| 11619 | bp->timer.expires = jiffies + bp->current_interval; |
| 11620 | bp->timer.data = (unsigned long) bp; |
| 11621 | bp->timer.function = bnx2x_timer; |
| 11622 | |
Barak Witkowski | 0370cf9 | 2012-12-02 04:05:55 +0000 | [diff] [blame] | 11623 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
| 11624 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && |
| 11625 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && |
| 11626 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { |
| 11627 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); |
| 11628 | bnx2x_dcbx_init_params(bp); |
| 11629 | } else { |
| 11630 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); |
| 11631 | } |
Vladislav Zolotarov | e4901dd | 2010-12-13 05:44:18 +0000 | [diff] [blame] | 11632 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11633 | if (CHIP_IS_E1x(bp)) |
| 11634 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; |
| 11635 | else |
| 11636 | bp->cnic_base_cl_id = FP_SB_MAX_E2; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11637 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11638 | /* multiple tx priority */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11639 | if (IS_VF(bp)) |
| 11640 | bp->max_cos = 1; |
| 11641 | else if (CHIP_IS_E1x(bp)) |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11642 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11643 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11644 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11645 | else if (CHIP_IS_E3B0(bp)) |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11646 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 11647 | else |
| 11648 | BNX2X_ERR("unknown chip %x revision %x\n", |
| 11649 | CHIP_NUM(bp), CHIP_REV(bp)); |
| 11650 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 11651 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11652 | /* We need at least one default status block for slow-path events, |
| 11653 | * second status block for the L2 queue, and a third status block for |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 11654 | * CNIC if supported. |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11655 | */ |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 11656 | if (IS_VF(bp)) |
| 11657 | bp->min_msix_vec_cnt = 1; |
| 11658 | else if (CNIC_SUPPORT(bp)) |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11659 | bp->min_msix_vec_cnt = 3; |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 11660 | else /* PF w/o cnic */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 11661 | bp->min_msix_vec_cnt = 2; |
| 11662 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); |
| 11663 | |
Michal Schmidt | 5bb680d | 2013-07-01 17:23:06 +0200 | [diff] [blame] | 11664 | bp->dump_preset_idx = 1; |
| 11665 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11666 | return rc; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11667 | } |
| 11668 | |
Dmitry Kravkov | de0c62d | 2010-07-27 12:35:24 +0000 | [diff] [blame] | 11669 | /**************************************************************************** |
| 11670 | * General service functions |
| 11671 | ****************************************************************************/ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11672 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11673 | /* |
| 11674 | * net_device service functions |
| 11675 | */ |
| 11676 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 11677 | /* called with rtnl_lock */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11678 | static int bnx2x_open(struct net_device *dev) |
| 11679 | { |
| 11680 | struct bnx2x *bp = netdev_priv(dev); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 11681 | bool global = false; |
| 11682 | int other_engine = BP_PATH(bp) ? 0 : 1; |
Ariel Elior | 889b9af | 2012-01-26 06:01:51 +0000 | [diff] [blame] | 11683 | bool other_load_status, load_status; |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 11684 | int rc; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11685 | |
Mintz Yuval | 1355b70 | 2012-02-15 02:10:22 +0000 | [diff] [blame] | 11686 | bp->stats_init = true; |
| 11687 | |
Eilon Greenstein | 6eccabb | 2009-01-22 03:37:48 +0000 | [diff] [blame] | 11688 | netif_carrier_off(dev); |
| 11689 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11690 | bnx2x_set_power_state(bp, PCI_D0); |
| 11691 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11692 | /* If parity had happen during the unload, then attentions |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 11693 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
| 11694 | * want the first function loaded on the current engine to |
| 11695 | * complete the recovery. |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11696 | * Parity recovery is only relevant for PF driver. |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 11697 | */ |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11698 | if (IS_PF(bp)) { |
| 11699 | other_load_status = bnx2x_get_load_status(bp, other_engine); |
| 11700 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); |
| 11701 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || |
| 11702 | bnx2x_chk_parity_attn(bp, &global, true)) { |
| 11703 | do { |
| 11704 | /* If there are attentions and they are in a |
| 11705 | * global blocks, set the GLOBAL_RESET bit |
| 11706 | * regardless whether it will be this function |
| 11707 | * that will complete the recovery or not. |
| 11708 | */ |
| 11709 | if (global) |
| 11710 | bnx2x_set_reset_global(bp); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 11711 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11712 | /* Only the first function on the current |
| 11713 | * engine should try to recover in open. In case |
| 11714 | * of attentions in global blocks only the first |
| 11715 | * in the chip should try to recover. |
| 11716 | */ |
| 11717 | if ((!load_status && |
| 11718 | (!global || !other_load_status)) && |
| 11719 | bnx2x_trylock_leader_lock(bp) && |
| 11720 | !bnx2x_leader_reset(bp)) { |
| 11721 | netdev_info(bp->dev, |
| 11722 | "Recovered in open\n"); |
| 11723 | break; |
| 11724 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 11725 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11726 | /* recovery has failed... */ |
| 11727 | bnx2x_set_power_state(bp, PCI_D3hot); |
| 11728 | bp->recovery_state = BNX2X_RECOVERY_FAILED; |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 11729 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11730 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
| 11731 | "If you still see this message after a few retries then power cycle is required.\n"); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 11732 | |
Ariel Elior | ad5afc8 | 2013-01-01 05:22:26 +0000 | [diff] [blame] | 11733 | return -EAGAIN; |
| 11734 | } while (0); |
| 11735 | } |
| 11736 | } |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 11737 | |
| 11738 | bp->recovery_state = BNX2X_RECOVERY_DONE; |
Ariel Elior | 8395be5 | 2013-01-01 05:22:44 +0000 | [diff] [blame] | 11739 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
| 11740 | if (rc) |
| 11741 | return rc; |
| 11742 | return bnx2x_open_epilog(bp); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11743 | } |
| 11744 | |
Yitchak Gertner | bb2a0f7 | 2008-06-23 20:33:36 -0700 | [diff] [blame] | 11745 | /* called with rtnl_lock */ |
Michal Schmidt | 56ad315 | 2012-02-16 02:38:48 +0000 | [diff] [blame] | 11746 | static int bnx2x_close(struct net_device *dev) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11747 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11748 | struct bnx2x *bp = netdev_priv(dev); |
| 11749 | |
| 11750 | /* Unload the driver, release IRQs */ |
Yuval Mintz | 5d07d86 | 2012-09-13 02:56:21 +0000 | [diff] [blame] | 11751 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
Vladislav Zolotarov | c9ee920 | 2011-06-14 01:33:51 +0000 | [diff] [blame] | 11752 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11753 | return 0; |
| 11754 | } |
| 11755 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 11756 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
| 11757 | struct bnx2x_mcast_ramrod_params *p) |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11758 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11759 | int mc_count = netdev_mc_count(bp->dev); |
| 11760 | struct bnx2x_mcast_list_elem *mc_mac = |
| 11761 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11762 | struct netdev_hw_addr *ha; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11763 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11764 | if (!mc_mac) |
| 11765 | return -ENOMEM; |
| 11766 | |
| 11767 | INIT_LIST_HEAD(&p->mcast_list); |
| 11768 | |
| 11769 | netdev_for_each_mc_addr(ha, bp->dev) { |
| 11770 | mc_mac->mac = bnx2x_mc_addr(ha); |
| 11771 | list_add_tail(&mc_mac->link, &p->mcast_list); |
| 11772 | mc_mac++; |
| 11773 | } |
| 11774 | |
| 11775 | p->mcast_list_len = mc_count; |
| 11776 | |
| 11777 | return 0; |
| 11778 | } |
| 11779 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 11780 | static void bnx2x_free_mcast_macs_list( |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11781 | struct bnx2x_mcast_ramrod_params *p) |
| 11782 | { |
| 11783 | struct bnx2x_mcast_list_elem *mc_mac = |
| 11784 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, |
| 11785 | link); |
| 11786 | |
| 11787 | WARN_ON(!mc_mac); |
| 11788 | kfree(mc_mac); |
| 11789 | } |
| 11790 | |
| 11791 | /** |
| 11792 | * bnx2x_set_uc_list - configure a new unicast MACs list. |
| 11793 | * |
| 11794 | * @bp: driver handle |
| 11795 | * |
| 11796 | * We will use zero (0) as a MAC type for these MACs. |
| 11797 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 11798 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11799 | { |
| 11800 | int rc; |
| 11801 | struct net_device *dev = bp->dev; |
| 11802 | struct netdev_hw_addr *ha; |
Barak Witkowski | 15192a8 | 2012-06-19 07:48:28 +0000 | [diff] [blame] | 11803 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11804 | unsigned long ramrod_flags = 0; |
| 11805 | |
| 11806 | /* First schedule a cleanup up of old configuration */ |
| 11807 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); |
| 11808 | if (rc < 0) { |
| 11809 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); |
| 11810 | return rc; |
| 11811 | } |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11812 | |
| 11813 | netdev_for_each_uc_addr(ha, dev) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11814 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
| 11815 | BNX2X_UC_LIST_MAC, &ramrod_flags); |
Yuval Mintz | 7b5342d | 2012-09-11 04:34:14 +0000 | [diff] [blame] | 11816 | if (rc == -EEXIST) { |
| 11817 | DP(BNX2X_MSG_SP, |
| 11818 | "Failed to schedule ADD operations: %d\n", rc); |
| 11819 | /* do not treat adding same MAC as error */ |
| 11820 | rc = 0; |
| 11821 | |
| 11822 | } else if (rc < 0) { |
| 11823 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11824 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
| 11825 | rc); |
| 11826 | return rc; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11827 | } |
| 11828 | } |
| 11829 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11830 | /* Execute the pending commands */ |
| 11831 | __set_bit(RAMROD_CONT, &ramrod_flags); |
| 11832 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, |
| 11833 | BNX2X_UC_LIST_MAC, &ramrod_flags); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11834 | } |
| 11835 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 11836 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11837 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11838 | struct net_device *dev = bp->dev; |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 11839 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11840 | int rc = 0; |
| 11841 | |
| 11842 | rparam.mcast_obj = &bp->mcast_obj; |
| 11843 | |
| 11844 | /* first, clear all configured multicast MACs */ |
| 11845 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); |
| 11846 | if (rc < 0) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11847 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11848 | return rc; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11849 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11850 | |
| 11851 | /* then, configure a new MACs list */ |
| 11852 | if (netdev_mc_count(dev)) { |
| 11853 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); |
| 11854 | if (rc) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11855 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
| 11856 | rc); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11857 | return rc; |
| 11858 | } |
| 11859 | |
| 11860 | /* Now add the new MACs */ |
| 11861 | rc = bnx2x_config_mcast(bp, &rparam, |
| 11862 | BNX2X_MCAST_CMD_ADD); |
| 11863 | if (rc < 0) |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11864 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
| 11865 | rc); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11866 | |
| 11867 | bnx2x_free_mcast_macs_list(&rparam); |
| 11868 | } |
| 11869 | |
| 11870 | return rc; |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 11871 | } |
| 11872 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11873 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 11874 | void bnx2x_set_rx_mode(struct net_device *dev) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11875 | { |
| 11876 | struct bnx2x *bp = netdev_priv(dev); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11877 | |
| 11878 | if (bp->state != BNX2X_STATE_OPEN) { |
| 11879 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); |
| 11880 | return; |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11881 | } else { |
| 11882 | /* Schedule an SP task to handle rest of change */ |
| 11883 | DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n"); |
| 11884 | smp_mb__before_clear_bit(); |
| 11885 | set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state); |
| 11886 | smp_mb__after_clear_bit(); |
| 11887 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11888 | } |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11889 | } |
| 11890 | |
| 11891 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) |
| 11892 | { |
| 11893 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11894 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11895 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11896 | |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11897 | netif_addr_lock_bh(bp->dev); |
| 11898 | |
| 11899 | if (bp->dev->flags & IFF_PROMISC) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11900 | rx_mode = BNX2X_RX_MODE_PROMISC; |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11901 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
| 11902 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && |
| 11903 | CHIP_IS_E1(bp))) { |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11904 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11905 | } else { |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11906 | if (IS_PF(bp)) { |
| 11907 | /* some multicasts */ |
| 11908 | if (bnx2x_set_mc_list(bp) < 0) |
| 11909 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11910 | |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11911 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
| 11912 | netif_addr_unlock_bh(bp->dev); |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11913 | if (bnx2x_set_uc_list(bp) < 0) |
| 11914 | rx_mode = BNX2X_RX_MODE_PROMISC; |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11915 | netif_addr_lock_bh(bp->dev); |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11916 | } else { |
| 11917 | /* configuring mcast to a vf involves sleeping (when we |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11918 | * wait for the pf's response). |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11919 | */ |
| 11920 | smp_mb__before_clear_bit(); |
| 11921 | set_bit(BNX2X_SP_RTNL_VFPF_MCAST, |
| 11922 | &bp->sp_rtnl_state); |
| 11923 | smp_mb__after_clear_bit(); |
| 11924 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
| 11925 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11926 | } |
| 11927 | |
| 11928 | bp->rx_mode = rx_mode; |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 11929 | /* handle ISCSI SD mode */ |
| 11930 | if (IS_MF_ISCSI_SD(bp)) |
| 11931 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11932 | |
| 11933 | /* Schedule the rx_mode command */ |
| 11934 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { |
| 11935 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11936 | netif_addr_unlock_bh(bp->dev); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 11937 | return; |
| 11938 | } |
| 11939 | |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11940 | if (IS_PF(bp)) { |
| 11941 | bnx2x_set_storm_rx_mode(bp); |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11942 | netif_addr_unlock_bh(bp->dev); |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11943 | } else { |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11944 | /* VF will need to request the PF to make this change, and so |
| 11945 | * the VF needs to release the bottom-half lock prior to the |
| 11946 | * request (as it will likely require sleep on the VF side) |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11947 | */ |
Yuval Mintz | 8b09be5 | 2013-08-01 17:30:59 +0300 | [diff] [blame] | 11948 | netif_addr_unlock_bh(bp->dev); |
| 11949 | bnx2x_vfpf_storm_rx_mode(bp); |
Ariel Elior | 381ac16 | 2013-01-01 05:22:29 +0000 | [diff] [blame] | 11950 | } |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 11951 | } |
| 11952 | |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 11953 | /* called with rtnl_lock */ |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11954 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
| 11955 | int devad, u16 addr) |
| 11956 | { |
| 11957 | struct bnx2x *bp = netdev_priv(netdev); |
| 11958 | u16 value; |
| 11959 | int rc; |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11960 | |
| 11961 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
| 11962 | prtad, devad, addr); |
| 11963 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11964 | /* The HW expects different devad if CL22 is used */ |
| 11965 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; |
| 11966 | |
| 11967 | bnx2x_acquire_phy_lock(bp); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11968 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11969 | bnx2x_release_phy_lock(bp); |
| 11970 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); |
| 11971 | |
| 11972 | if (!rc) |
| 11973 | rc = value; |
| 11974 | return rc; |
| 11975 | } |
| 11976 | |
| 11977 | /* called with rtnl_lock */ |
| 11978 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, |
| 11979 | u16 addr, u16 value) |
| 11980 | { |
| 11981 | struct bnx2x *bp = netdev_priv(netdev); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11982 | int rc; |
| 11983 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 11984 | DP(NETIF_MSG_LINK, |
| 11985 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", |
| 11986 | prtad, devad, addr, value); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11987 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11988 | /* The HW expects different devad if CL22 is used */ |
| 11989 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; |
| 11990 | |
| 11991 | bnx2x_acquire_phy_lock(bp); |
Yaniv Rosner | e10bc84 | 2010-09-07 11:40:50 +0000 | [diff] [blame] | 11992 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 11993 | bnx2x_release_phy_lock(bp); |
| 11994 | return rc; |
| 11995 | } |
| 11996 | |
| 11997 | /* called with rtnl_lock */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11998 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 11999 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12000 | struct bnx2x *bp = netdev_priv(dev); |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 12001 | struct mii_ioctl_data *mdio = if_mii(ifr); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12002 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 12003 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
| 12004 | mdio->phy_id, mdio->reg_num, mdio->val_in); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12005 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 12006 | if (!netif_running(dev)) |
| 12007 | return -EAGAIN; |
Yaniv Rosner | c18487e | 2008-06-23 20:27:52 -0700 | [diff] [blame] | 12008 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 12009 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12010 | } |
| 12011 | |
Alexey Dobriyan | 257ddbd | 2010-01-27 10:17:41 +0000 | [diff] [blame] | 12012 | #ifdef CONFIG_NET_POLL_CONTROLLER |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12013 | static void poll_bnx2x(struct net_device *dev) |
| 12014 | { |
| 12015 | struct bnx2x *bp = netdev_priv(dev); |
Merav Sicron | 14a15d6 | 2012-08-27 03:26:20 +0000 | [diff] [blame] | 12016 | int i; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12017 | |
Merav Sicron | 14a15d6 | 2012-08-27 03:26:20 +0000 | [diff] [blame] | 12018 | for_each_eth_queue(bp, i) { |
| 12019 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
| 12020 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
| 12021 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12022 | } |
| 12023 | #endif |
| 12024 | |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 12025 | static int bnx2x_validate_addr(struct net_device *dev) |
| 12026 | { |
| 12027 | struct bnx2x *bp = netdev_priv(dev); |
| 12028 | |
Ariel Elior | e09b74d | 2013-05-27 04:08:26 +0000 | [diff] [blame] | 12029 | /* query the bulletin board for mac address configured by the PF */ |
| 12030 | if (IS_VF(bp)) |
| 12031 | bnx2x_sample_bulletin(bp); |
| 12032 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12033 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
| 12034 | BNX2X_ERR("Non-valid Ethernet address\n"); |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 12035 | return -EADDRNOTAVAIL; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12036 | } |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 12037 | return 0; |
| 12038 | } |
| 12039 | |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12040 | static const struct net_device_ops bnx2x_netdev_ops = { |
| 12041 | .ndo_open = bnx2x_open, |
| 12042 | .ndo_stop = bnx2x_close, |
| 12043 | .ndo_start_xmit = bnx2x_start_xmit, |
Vladislav Zolotarov | 8307fa3 | 2010-12-13 05:44:09 +0000 | [diff] [blame] | 12044 | .ndo_select_queue = bnx2x_select_queue, |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 12045 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12046 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
Dmitry Kravkov | 614c76d | 2011-11-28 12:31:49 +0000 | [diff] [blame] | 12047 | .ndo_validate_addr = bnx2x_validate_addr, |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12048 | .ndo_do_ioctl = bnx2x_ioctl, |
| 12049 | .ndo_change_mtu = bnx2x_change_mtu, |
Michał Mirosław | 66371c4 | 2011-04-12 09:38:23 +0000 | [diff] [blame] | 12050 | .ndo_fix_features = bnx2x_fix_features, |
| 12051 | .ndo_set_features = bnx2x_set_features, |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12052 | .ndo_tx_timeout = bnx2x_tx_timeout, |
Alexey Dobriyan | 257ddbd | 2010-01-27 10:17:41 +0000 | [diff] [blame] | 12053 | #ifdef CONFIG_NET_POLL_CONTROLLER |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12054 | .ndo_poll_controller = poll_bnx2x, |
| 12055 | #endif |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12056 | .ndo_setup_tc = bnx2x_setup_tc, |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 12057 | #ifdef CONFIG_BNX2X_SRIOV |
Ariel Elior | abc5a02 | 2013-01-01 05:22:43 +0000 | [diff] [blame] | 12058 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
Yuval Mintz | 3cdeec2 | 2013-06-02 00:06:19 +0000 | [diff] [blame] | 12059 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
Ariel Elior | 3ec9f9c | 2013-03-11 05:17:45 +0000 | [diff] [blame] | 12060 | .ndo_get_vf_config = bnx2x_get_vf_config, |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 12061 | #endif |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12062 | #ifdef NETDEV_FCOE_WWNN |
Vladislav Zolotarov | bf61ee1 | 2011-07-21 07:56:51 +0000 | [diff] [blame] | 12063 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
| 12064 | #endif |
Dmitry Kravkov | 8f20aa5 | 2013-06-19 01:36:04 +0300 | [diff] [blame] | 12065 | |
Cong Wang | e0d1095 | 2013-08-01 11:10:25 +0800 | [diff] [blame] | 12066 | #ifdef CONFIG_NET_RX_BUSY_POLL |
Eliezer Tamir | 8b80cda | 2013-07-10 17:13:26 +0300 | [diff] [blame] | 12067 | .ndo_busy_poll = bnx2x_low_latency_recv, |
Dmitry Kravkov | 8f20aa5 | 2013-06-19 01:36:04 +0300 | [diff] [blame] | 12068 | #endif |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12069 | }; |
| 12070 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12071 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12072 | { |
| 12073 | struct device *dev = &bp->pdev->dev; |
| 12074 | |
Russell King | 1bfa2c4 | 2013-06-26 20:02:30 +0100 | [diff] [blame^] | 12075 | if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) == 0) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12076 | bp->flags |= USING_DAC_FLAG; |
Russell King | 1bfa2c4 | 2013-06-26 20:02:30 +0100 | [diff] [blame^] | 12077 | } else if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12078 | dev_err(dev, "System does not support DMA, aborting\n"); |
| 12079 | return -EIO; |
| 12080 | } |
| 12081 | |
| 12082 | return 0; |
| 12083 | } |
| 12084 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12085 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
| 12086 | struct net_device *dev, unsigned long board_type) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12087 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12088 | int rc; |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12089 | u32 pci_cfg_dword; |
Ariel Elior | 65087cf | 2012-01-23 07:31:55 +0000 | [diff] [blame] | 12090 | bool chip_is_e1x = (board_type == BCM57710 || |
| 12091 | board_type == BCM57711 || |
| 12092 | board_type == BCM57711E); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12093 | |
| 12094 | SET_NETDEV_DEV(dev, &pdev->dev); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12095 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12096 | bp->dev = dev; |
| 12097 | bp->pdev = pdev; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12098 | |
| 12099 | rc = pci_enable_device(pdev); |
| 12100 | if (rc) { |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 12101 | dev_err(&bp->pdev->dev, |
| 12102 | "Cannot enable PCI device, aborting\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12103 | goto err_out; |
| 12104 | } |
| 12105 | |
| 12106 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 12107 | dev_err(&bp->pdev->dev, |
| 12108 | "Cannot find PCI device base address, aborting\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12109 | rc = -ENODEV; |
| 12110 | goto err_out_disable; |
| 12111 | } |
| 12112 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12113 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
| 12114 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12115 | rc = -ENODEV; |
| 12116 | goto err_out_disable; |
| 12117 | } |
| 12118 | |
Yaniv Rosner | 092a5fc9 | 2012-12-02 23:56:49 +0000 | [diff] [blame] | 12119 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
| 12120 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == |
| 12121 | PCICFG_REVESION_ID_ERROR_VAL) { |
| 12122 | pr_err("PCI device error, probably due to fan failure, aborting\n"); |
| 12123 | rc = -ENODEV; |
| 12124 | goto err_out_disable; |
| 12125 | } |
| 12126 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12127 | if (atomic_read(&pdev->enable_cnt) == 1) { |
| 12128 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); |
| 12129 | if (rc) { |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 12130 | dev_err(&bp->pdev->dev, |
| 12131 | "Cannot obtain PCI resources, aborting\n"); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12132 | goto err_out_disable; |
| 12133 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12134 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12135 | pci_set_master(pdev); |
| 12136 | pci_save_state(pdev); |
| 12137 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12138 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12139 | if (IS_PF(bp)) { |
Yijing Wang | b8a39dd | 2013-06-18 16:05:39 +0800 | [diff] [blame] | 12140 | bp->pm_cap = pdev->pm_cap; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12141 | if (bp->pm_cap == 0) { |
| 12142 | dev_err(&bp->pdev->dev, |
| 12143 | "Cannot find power management capability, aborting\n"); |
| 12144 | rc = -EIO; |
| 12145 | goto err_out_release; |
| 12146 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12147 | } |
| 12148 | |
Jon Mason | 77c98e6 | 2011-06-27 07:45:12 +0000 | [diff] [blame] | 12149 | if (!pci_is_pcie(pdev)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12150 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12151 | rc = -EIO; |
| 12152 | goto err_out_release; |
| 12153 | } |
| 12154 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12155 | rc = bnx2x_set_coherency_mask(bp); |
| 12156 | if (rc) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12157 | goto err_out_release; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12158 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12159 | dev->mem_start = pci_resource_start(pdev, 0); |
| 12160 | dev->base_addr = dev->mem_start; |
| 12161 | dev->mem_end = pci_resource_end(pdev, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12162 | |
| 12163 | dev->irq = pdev->irq; |
| 12164 | |
Arjan van de Ven | 275f165 | 2008-10-20 21:42:39 -0700 | [diff] [blame] | 12165 | bp->regview = pci_ioremap_bar(pdev, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12166 | if (!bp->regview) { |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 12167 | dev_err(&bp->pdev->dev, |
| 12168 | "Cannot map register space, aborting\n"); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12169 | rc = -ENOMEM; |
| 12170 | goto err_out_release; |
| 12171 | } |
| 12172 | |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12173 | /* In E1/E1H use pci device function given by kernel. |
| 12174 | * In E2/E3 read physical function from ME register since these chips |
| 12175 | * support Physical Device Assignment where kernel BDF maybe arbitrary |
| 12176 | * (depending on hypervisor). |
| 12177 | */ |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 12178 | if (chip_is_e1x) { |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12179 | bp->pf_num = PCI_FUNC(pdev->devfn); |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 12180 | } else { |
| 12181 | /* chip is E2/3*/ |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12182 | pci_read_config_dword(bp->pdev, |
| 12183 | PCICFG_ME_REGISTER, &pci_cfg_dword); |
| 12184 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 12185 | ME_REG_ABS_PF_NUM_SHIFT); |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12186 | } |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12187 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
Ariel Elior | c22610d0 | 2012-01-26 06:01:47 +0000 | [diff] [blame] | 12188 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12189 | /* clean indirect addresses */ |
| 12190 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, |
| 12191 | PCICFG_VENDOR_ID_OFFSET); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 12192 | /* |
| 12193 | * Clean the following indirect addresses for all functions since it |
David S. Miller | 823dcd2 | 2011-08-20 10:39:12 -0700 | [diff] [blame] | 12194 | * is not used by the driver. |
| 12195 | */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12196 | if (IS_PF(bp)) { |
| 12197 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); |
| 12198 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); |
| 12199 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); |
| 12200 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 12201 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12202 | if (chip_is_e1x) { |
| 12203 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
| 12204 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); |
| 12205 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); |
| 12206 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); |
| 12207 | } |
| 12208 | |
| 12209 | /* Enable internal target-read (in case we are probed after PF |
| 12210 | * FLR). Must be done prior to any BAR read access. Only for |
| 12211 | * 57712 and up |
| 12212 | */ |
| 12213 | if (!chip_is_e1x) |
| 12214 | REG_WR(bp, |
| 12215 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 12216 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12217 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12218 | dev->watchdog_timeo = TX_TIMEOUT; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12219 | |
Stephen Hemminger | c64213c | 2008-11-21 17:36:04 -0800 | [diff] [blame] | 12220 | dev->netdev_ops = &bnx2x_netdev_ops; |
Ariel Elior | 005a07ba | 2013-03-11 05:17:42 +0000 | [diff] [blame] | 12221 | bnx2x_set_ethtool_ops(bp, dev); |
Michał Mirosław | 66371c4 | 2011-04-12 09:38:23 +0000 | [diff] [blame] | 12222 | |
Jiri Pirko | 0178934 | 2011-08-16 06:29:00 +0000 | [diff] [blame] | 12223 | dev->priv_flags |= IFF_UNICAST_FLT; |
| 12224 | |
Michał Mirosław | 66371c4 | 2011-04-12 09:38:23 +0000 | [diff] [blame] | 12225 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
Dmitry Kravkov | 621b4d6 | 2012-02-20 09:59:08 +0000 | [diff] [blame] | 12226 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
| 12227 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | |
Patrick McHardy | f646968 | 2013-04-19 02:04:27 +0000 | [diff] [blame] | 12228 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
Dmitry Kravkov | a848ade | 2013-03-18 06:51:03 +0000 | [diff] [blame] | 12229 | if (!CHIP_IS_E1x(bp)) { |
Dmitry Kravkov | 65bc0cf | 2013-04-28 08:16:02 +0000 | [diff] [blame] | 12230 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
Dmitry Kravkov | a848ade | 2013-03-18 06:51:03 +0000 | [diff] [blame] | 12231 | dev->hw_enc_features = |
| 12232 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
| 12233 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
Dmitry Kravkov | 65bc0cf | 2013-04-28 08:16:02 +0000 | [diff] [blame] | 12234 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
Dmitry Kravkov | a848ade | 2013-03-18 06:51:03 +0000 | [diff] [blame] | 12235 | } |
Michał Mirosław | 66371c4 | 2011-04-12 09:38:23 +0000 | [diff] [blame] | 12236 | |
| 12237 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 12238 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; |
| 12239 | |
Patrick McHardy | f646968 | 2013-04-19 02:04:27 +0000 | [diff] [blame] | 12240 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12241 | if (bp->flags & USING_DAC_FLAG) |
| 12242 | dev->features |= NETIF_F_HIGHDMA; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12243 | |
Mahesh Bandewar | 538dd2e | 2011-05-13 15:08:49 +0000 | [diff] [blame] | 12244 | /* Add Loopback capability to the device */ |
| 12245 | dev->hw_features |= NETIF_F_LOOPBACK; |
| 12246 | |
Shmulik Ravid | 9850767 | 2011-02-28 12:19:55 -0800 | [diff] [blame] | 12247 | #ifdef BCM_DCBNL |
Shmulik Ravid | 785b9b1 | 2010-12-30 06:27:03 +0000 | [diff] [blame] | 12248 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
| 12249 | #endif |
| 12250 | |
Eilon Greenstein | 01cd452 | 2009-08-12 08:23:08 +0000 | [diff] [blame] | 12251 | /* get_port_hwinfo() will set prtad and mmds properly */ |
| 12252 | bp->mdio.prtad = MDIO_PRTAD_NONE; |
| 12253 | bp->mdio.mmds = 0; |
| 12254 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; |
| 12255 | bp->mdio.dev = dev; |
| 12256 | bp->mdio.mdio_read = bnx2x_mdio_read; |
| 12257 | bp->mdio.mdio_write = bnx2x_mdio_write; |
| 12258 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12259 | return 0; |
| 12260 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12261 | err_out_release: |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12262 | if (atomic_read(&pdev->enable_cnt) == 1) |
| 12263 | pci_release_regions(pdev); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12264 | |
| 12265 | err_out_disable: |
| 12266 | pci_disable_device(pdev); |
| 12267 | pci_set_drvdata(pdev, NULL); |
| 12268 | |
| 12269 | err_out: |
| 12270 | return rc; |
| 12271 | } |
| 12272 | |
Dmitry Kravkov | ca1ee4b | 2013-05-27 04:08:27 +0000 | [diff] [blame] | 12273 | static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, |
| 12274 | enum bnx2x_pci_bus_speed *speed) |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 12275 | { |
Dmitry Kravkov | ca1ee4b | 2013-05-27 04:08:27 +0000 | [diff] [blame] | 12276 | u32 link_speed, val = 0; |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 12277 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12278 | pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); |
Eilon Greenstein | 37f9ce6 | 2009-08-12 08:23:34 +0000 | [diff] [blame] | 12279 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
| 12280 | |
Dmitry Kravkov | ca1ee4b | 2013-05-27 04:08:27 +0000 | [diff] [blame] | 12281 | link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; |
| 12282 | |
| 12283 | switch (link_speed) { |
| 12284 | case 3: |
| 12285 | *speed = BNX2X_PCI_LINK_SPEED_8000; |
| 12286 | break; |
| 12287 | case 2: |
| 12288 | *speed = BNX2X_PCI_LINK_SPEED_5000; |
| 12289 | break; |
| 12290 | default: |
| 12291 | *speed = BNX2X_PCI_LINK_SPEED_2500; |
| 12292 | } |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 12293 | } |
| 12294 | |
Dmitry Kravkov | 6891dd2 | 2010-08-03 21:49:40 +0000 | [diff] [blame] | 12295 | static int bnx2x_check_firmware(struct bnx2x *bp) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12296 | { |
Eilon Greenstein | 37f9ce6 | 2009-08-12 08:23:34 +0000 | [diff] [blame] | 12297 | const struct firmware *firmware = bp->firmware; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12298 | struct bnx2x_fw_file_hdr *fw_hdr; |
| 12299 | struct bnx2x_fw_file_section *sections; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12300 | u32 offset, len, num_ops; |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 12301 | __be16 *ops_offsets; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12302 | int i; |
Eilon Greenstein | 37f9ce6 | 2009-08-12 08:23:34 +0000 | [diff] [blame] | 12303 | const u8 *fw_ver; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12304 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12305 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
| 12306 | BNX2X_ERR("Wrong FW size\n"); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12307 | return -EINVAL; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12308 | } |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12309 | |
| 12310 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; |
| 12311 | sections = (struct bnx2x_fw_file_section *)fw_hdr; |
| 12312 | |
| 12313 | /* Make sure none of the offsets and sizes make us read beyond |
| 12314 | * the end of the firmware data */ |
| 12315 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { |
| 12316 | offset = be32_to_cpu(sections[i].offset); |
| 12317 | len = be32_to_cpu(sections[i].len); |
| 12318 | if (offset + len > firmware->size) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12319 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12320 | return -EINVAL; |
| 12321 | } |
| 12322 | } |
| 12323 | |
| 12324 | /* Likewise for the init_ops offsets */ |
| 12325 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); |
Yuval Mintz | 86564c3 | 2013-01-23 03:21:50 +0000 | [diff] [blame] | 12326 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12327 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
| 12328 | |
| 12329 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { |
| 12330 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12331 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12332 | return -EINVAL; |
| 12333 | } |
| 12334 | } |
| 12335 | |
| 12336 | /* Check FW version */ |
| 12337 | offset = be32_to_cpu(fw_hdr->fw_version.offset); |
| 12338 | fw_ver = firmware->data + offset; |
| 12339 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || |
| 12340 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || |
| 12341 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || |
| 12342 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 12343 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
| 12344 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], |
| 12345 | BCM_5710_FW_MAJOR_VERSION, |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12346 | BCM_5710_FW_MINOR_VERSION, |
| 12347 | BCM_5710_FW_REVISION_VERSION, |
| 12348 | BCM_5710_FW_ENGINEERING_VERSION); |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12349 | return -EINVAL; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12350 | } |
| 12351 | |
| 12352 | return 0; |
| 12353 | } |
| 12354 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12355 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12356 | { |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12357 | const __be32 *source = (const __be32 *)_source; |
| 12358 | u32 *target = (u32 *)_target; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12359 | u32 i; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12360 | |
| 12361 | for (i = 0; i < n/4; i++) |
| 12362 | target[i] = be32_to_cpu(source[i]); |
| 12363 | } |
| 12364 | |
| 12365 | /* |
| 12366 | Ops array is stored in the following format: |
| 12367 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} |
| 12368 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12369 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12370 | { |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12371 | const __be32 *source = (const __be32 *)_source; |
| 12372 | struct raw_op *target = (struct raw_op *)_target; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12373 | u32 i, j, tmp; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12374 | |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12375 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12376 | tmp = be32_to_cpu(source[j]); |
| 12377 | target[i].op = (tmp >> 24) & 0xff; |
Vladislav Zolotarov | cdaa7cb | 2010-04-19 01:13:57 +0000 | [diff] [blame] | 12378 | target[i].offset = tmp & 0xffffff; |
| 12379 | target[i].raw_data = be32_to_cpu(source[j + 1]); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12380 | } |
| 12381 | } |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12382 | |
Ben Hutchings | 1aa8b47 | 2012-07-10 10:56:59 +0000 | [diff] [blame] | 12383 | /* IRO array is stored in the following format: |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12384 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
| 12385 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12386 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12387 | { |
| 12388 | const __be32 *source = (const __be32 *)_source; |
| 12389 | struct iro *target = (struct iro *)_target; |
| 12390 | u32 i, j, tmp; |
| 12391 | |
| 12392 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { |
| 12393 | target[i].base = be32_to_cpu(source[j]); |
| 12394 | j++; |
| 12395 | tmp = be32_to_cpu(source[j]); |
| 12396 | target[i].m1 = (tmp >> 16) & 0xffff; |
| 12397 | target[i].m2 = tmp & 0xffff; |
| 12398 | j++; |
| 12399 | tmp = be32_to_cpu(source[j]); |
| 12400 | target[i].m3 = (tmp >> 16) & 0xffff; |
| 12401 | target[i].size = tmp & 0xffff; |
| 12402 | j++; |
| 12403 | } |
| 12404 | } |
| 12405 | |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12406 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12407 | { |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12408 | const __be16 *source = (const __be16 *)_source; |
| 12409 | u16 *target = (u16 *)_target; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12410 | u32 i; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12411 | |
| 12412 | for (i = 0; i < n/2; i++) |
| 12413 | target[i] = be16_to_cpu(source[i]); |
| 12414 | } |
| 12415 | |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 12416 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
| 12417 | do { \ |
| 12418 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ |
| 12419 | bp->arr = kmalloc(len, GFP_KERNEL); \ |
Joe Perches | e404dec | 2012-01-29 12:56:23 +0000 | [diff] [blame] | 12420 | if (!bp->arr) \ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 12421 | goto lbl; \ |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 12422 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
| 12423 | (u8 *)bp->arr, len); \ |
| 12424 | } while (0) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12425 | |
Yuval Mintz | 3b60306 | 2012-03-18 10:33:39 +0000 | [diff] [blame] | 12426 | static int bnx2x_init_firmware(struct bnx2x *bp) |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12427 | { |
Michal Schmidt | c0ea452 | 2012-03-15 14:08:29 +0000 | [diff] [blame] | 12428 | const char *fw_file_name; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12429 | struct bnx2x_fw_file_hdr *fw_hdr; |
Ben Hutchings | 45229b4 | 2009-11-07 11:53:39 +0000 | [diff] [blame] | 12430 | int rc; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12431 | |
Michal Schmidt | c0ea452 | 2012-03-15 14:08:29 +0000 | [diff] [blame] | 12432 | if (bp->firmware) |
| 12433 | return 0; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12434 | |
Michal Schmidt | c0ea452 | 2012-03-15 14:08:29 +0000 | [diff] [blame] | 12435 | if (CHIP_IS_E1(bp)) |
| 12436 | fw_file_name = FW_FILE_NAME_E1; |
| 12437 | else if (CHIP_IS_E1H(bp)) |
| 12438 | fw_file_name = FW_FILE_NAME_E1H; |
| 12439 | else if (!CHIP_IS_E1x(bp)) |
| 12440 | fw_file_name = FW_FILE_NAME_E2; |
| 12441 | else { |
| 12442 | BNX2X_ERR("Unsupported chip revision\n"); |
| 12443 | return -EINVAL; |
| 12444 | } |
| 12445 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12446 | |
Michal Schmidt | c0ea452 | 2012-03-15 14:08:29 +0000 | [diff] [blame] | 12447 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
| 12448 | if (rc) { |
| 12449 | BNX2X_ERR("Can't load firmware file %s\n", |
| 12450 | fw_file_name); |
| 12451 | goto request_firmware_exit; |
| 12452 | } |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12453 | |
Michal Schmidt | c0ea452 | 2012-03-15 14:08:29 +0000 | [diff] [blame] | 12454 | rc = bnx2x_check_firmware(bp); |
| 12455 | if (rc) { |
| 12456 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); |
| 12457 | goto request_firmware_exit; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12458 | } |
| 12459 | |
| 12460 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; |
| 12461 | |
| 12462 | /* Initialize the pointers to the init arrays */ |
| 12463 | /* Blob */ |
| 12464 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); |
| 12465 | |
| 12466 | /* Opcodes */ |
| 12467 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); |
| 12468 | |
| 12469 | /* Offsets */ |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12470 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
| 12471 | be16_to_cpu_n); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12472 | |
| 12473 | /* STORMs firmware */ |
Eilon Greenstein | 573f203 | 2009-08-12 08:24:14 +0000 | [diff] [blame] | 12474 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
| 12475 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); |
| 12476 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + |
| 12477 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); |
| 12478 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
| 12479 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); |
| 12480 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + |
| 12481 | be32_to_cpu(fw_hdr->usem_pram_data.offset); |
| 12482 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
| 12483 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); |
| 12484 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + |
| 12485 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); |
| 12486 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
| 12487 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); |
| 12488 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + |
| 12489 | be32_to_cpu(fw_hdr->csem_pram_data.offset); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12490 | /* IRO */ |
| 12491 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12492 | |
| 12493 | return 0; |
Eilon Greenstein | ab6ad5a | 2009-08-12 08:24:29 +0000 | [diff] [blame] | 12494 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12495 | iro_alloc_err: |
| 12496 | kfree(bp->init_ops_offsets); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12497 | init_offsets_alloc_err: |
| 12498 | kfree(bp->init_ops); |
| 12499 | init_ops_alloc_err: |
| 12500 | kfree(bp->init_data); |
| 12501 | request_firmware_exit: |
| 12502 | release_firmware(bp->firmware); |
Michal Schmidt | 127d0a1 | 2012-03-15 14:08:28 +0000 | [diff] [blame] | 12503 | bp->firmware = NULL; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12504 | |
| 12505 | return rc; |
| 12506 | } |
| 12507 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12508 | static void bnx2x_release_firmware(struct bnx2x *bp) |
| 12509 | { |
| 12510 | kfree(bp->init_ops_offsets); |
| 12511 | kfree(bp->init_ops); |
| 12512 | kfree(bp->init_data); |
| 12513 | release_firmware(bp->firmware); |
Dmitry Kravkov | eb2afd4 | 2011-11-15 12:07:33 +0000 | [diff] [blame] | 12514 | bp->firmware = NULL; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12515 | } |
| 12516 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12517 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
| 12518 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, |
| 12519 | .init_hw_cmn = bnx2x_init_hw_common, |
| 12520 | .init_hw_port = bnx2x_init_hw_port, |
| 12521 | .init_hw_func = bnx2x_init_hw_func, |
| 12522 | |
| 12523 | .reset_hw_cmn = bnx2x_reset_common, |
| 12524 | .reset_hw_port = bnx2x_reset_port, |
| 12525 | .reset_hw_func = bnx2x_reset_func, |
| 12526 | |
| 12527 | .gunzip_init = bnx2x_gunzip_init, |
| 12528 | .gunzip_end = bnx2x_gunzip_end, |
| 12529 | |
| 12530 | .init_fw = bnx2x_init_firmware, |
| 12531 | .release_fw = bnx2x_release_firmware, |
| 12532 | }; |
| 12533 | |
| 12534 | void bnx2x__init_func_obj(struct bnx2x *bp) |
| 12535 | { |
| 12536 | /* Prepare DMAE related driver resources */ |
| 12537 | bnx2x_setup_dmae(bp); |
| 12538 | |
| 12539 | bnx2x_init_func_obj(bp, &bp->func_obj, |
| 12540 | bnx2x_sp(bp, func_rdata), |
| 12541 | bnx2x_sp_mapping(bp, func_rdata), |
Barak Witkowski | a334872 | 2012-04-23 03:04:46 +0000 | [diff] [blame] | 12542 | bnx2x_sp(bp, func_afex_rdata), |
| 12543 | bnx2x_sp_mapping(bp, func_afex_rdata), |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12544 | &bnx2x_func_sp_drv); |
| 12545 | } |
| 12546 | |
| 12547 | /* must be called after sriov-enable */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 12548 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12549 | { |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 12550 | int cid_count = BNX2X_L2_MAX_CID(bp); |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 12551 | |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 12552 | if (IS_SRIOV(bp)) |
| 12553 | cid_count += BNX2X_VF_CIDS; |
| 12554 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12555 | if (CNIC_SUPPORT(bp)) |
| 12556 | cid_count += CNIC_CID_MAX; |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 12557 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12558 | return roundup(cid_count, QM_CID_ROUND); |
| 12559 | } |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 12560 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12561 | /** |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12562 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12563 | * |
| 12564 | * @dev: pci device |
| 12565 | * |
| 12566 | */ |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 12567 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12568 | { |
Yijing Wang | ae2104b | 2013-08-08 21:02:36 +0800 | [diff] [blame] | 12569 | int index; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12570 | u16 control = 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12571 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12572 | /* |
| 12573 | * If MSI-X is not supported - return number of SBs needed to support |
| 12574 | * one fast path queue: one FP queue + SB for CNIC |
| 12575 | */ |
Yijing Wang | ae2104b | 2013-08-08 21:02:36 +0800 | [diff] [blame] | 12576 | if (!pdev->msix_cap) { |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12577 | dev_info(&pdev->dev, "no msix capability found\n"); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12578 | return 1 + cnic_cnt; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12579 | } |
| 12580 | dev_info(&pdev->dev, "msix capability found\n"); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12581 | |
| 12582 | /* |
| 12583 | * The value in the PCI configuration space is the index of the last |
| 12584 | * entry, namely one less than the actual size of the table, which is |
| 12585 | * exactly what we want to return from this function: number of all SBs |
| 12586 | * without the default SB. |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12587 | * For VFs there is no default SB, then we return (index+1). |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12588 | */ |
Yijing Wang | ae2104b | 2013-08-08 21:02:36 +0800 | [diff] [blame] | 12589 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12590 | |
| 12591 | index = control & PCI_MSIX_FLAGS_QSIZE; |
| 12592 | |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 12593 | return index; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12594 | } |
| 12595 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12596 | static int set_max_cos_est(int chip_id) |
| 12597 | { |
| 12598 | switch (chip_id) { |
| 12599 | case BCM57710: |
| 12600 | case BCM57711: |
| 12601 | case BCM57711E: |
| 12602 | return BNX2X_MULTI_TX_COS_E1X; |
| 12603 | case BCM57712: |
| 12604 | case BCM57712_MF: |
| 12605 | case BCM57712_VF: |
| 12606 | return BNX2X_MULTI_TX_COS_E2_E3A0; |
| 12607 | case BCM57800: |
| 12608 | case BCM57800_MF: |
| 12609 | case BCM57800_VF: |
| 12610 | case BCM57810: |
| 12611 | case BCM57810_MF: |
| 12612 | case BCM57840_4_10: |
| 12613 | case BCM57840_2_20: |
| 12614 | case BCM57840_O: |
| 12615 | case BCM57840_MFO: |
| 12616 | case BCM57810_VF: |
| 12617 | case BCM57840_MF: |
| 12618 | case BCM57840_VF: |
| 12619 | case BCM57811: |
| 12620 | case BCM57811_MF: |
| 12621 | case BCM57811_VF: |
| 12622 | return BNX2X_MULTI_TX_COS_E3B0; |
| 12623 | return 1; |
| 12624 | default: |
| 12625 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
| 12626 | return -ENODEV; |
| 12627 | } |
| 12628 | } |
Michael Chan | 4bd9b0ff | 2012-12-06 10:33:12 +0000 | [diff] [blame] | 12629 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12630 | static int set_is_vf(int chip_id) |
| 12631 | { |
| 12632 | switch (chip_id) { |
| 12633 | case BCM57712_VF: |
| 12634 | case BCM57800_VF: |
| 12635 | case BCM57810_VF: |
| 12636 | case BCM57840_VF: |
| 12637 | case BCM57811_VF: |
| 12638 | return true; |
| 12639 | default: |
| 12640 | return false; |
| 12641 | } |
| 12642 | } |
| 12643 | |
| 12644 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); |
| 12645 | |
| 12646 | static int bnx2x_init_one(struct pci_dev *pdev, |
| 12647 | const struct pci_device_id *ent) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12648 | { |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12649 | struct net_device *dev = NULL; |
| 12650 | struct bnx2x *bp; |
Dmitry Kravkov | ca1ee4b | 2013-05-27 04:08:27 +0000 | [diff] [blame] | 12651 | int pcie_width; |
| 12652 | enum bnx2x_pci_bus_speed pcie_speed; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12653 | int rc, max_non_def_sbs; |
Merav Sicron | 6556588 | 2012-06-19 07:48:26 +0000 | [diff] [blame] | 12654 | int rx_count, tx_count, rss_count, doorbell_size; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12655 | int max_cos_est; |
| 12656 | bool is_vf; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12657 | int cnic_cnt; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12658 | |
| 12659 | /* An estimated maximum supported CoS number according to the chip |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12660 | * version. |
| 12661 | * We will try to roughly estimate the maximum number of CoSes this chip |
| 12662 | * may support in order to minimize the memory allocated for Tx |
| 12663 | * netdev_queue's. This number will be accurately calculated during the |
| 12664 | * initialization of bp->max_cos based on the chip versions AND chip |
| 12665 | * revision in the bnx2x_init_bp(). |
| 12666 | */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12667 | max_cos_est = set_max_cos_est(ent->driver_data); |
| 12668 | if (max_cos_est < 0) |
| 12669 | return max_cos_est; |
| 12670 | is_vf = set_is_vf(ent->driver_data); |
| 12671 | cnic_cnt = is_vf ? 0 : 1; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12672 | |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 12673 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
| 12674 | |
| 12675 | /* add another SB for VF as it has no default SB */ |
| 12676 | max_non_def_sbs += is_vf ? 1 : 0; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12677 | |
| 12678 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ |
Ariel Elior | 60cad4e | 2013-09-04 14:09:22 +0300 | [diff] [blame] | 12679 | rss_count = max_non_def_sbs - cnic_cnt; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12680 | |
| 12681 | if (rss_count < 1) |
| 12682 | return -EINVAL; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12683 | |
| 12684 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12685 | rx_count = rss_count + cnic_cnt; |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12686 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12687 | /* Maximum number of netdev Tx queues: |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 12688 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12689 | */ |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12690 | tx_count = rss_count * max_cos_est + cnic_cnt; |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 12691 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12692 | /* dev zeroed in init_etherdev */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12693 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
Joe Perches | 41de8d4 | 2012-01-29 13:47:52 +0000 | [diff] [blame] | 12694 | if (!dev) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12695 | return -ENOMEM; |
| 12696 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12697 | bp = netdev_priv(dev); |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12698 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12699 | bp->flags = 0; |
| 12700 | if (is_vf) |
| 12701 | bp->flags |= IS_VF_FLAG; |
| 12702 | |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12703 | bp->igu_sb_cnt = max_non_def_sbs; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12704 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 12705 | bp->msg_enable = debug; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12706 | bp->cnic_support = cnic_cnt; |
Michael Chan | 4bd9b0ff | 2012-12-06 10:33:12 +0000 | [diff] [blame] | 12707 | bp->cnic_probe = bnx2x_cnic_probe; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12708 | |
Eilon Greenstein | df4770de | 2009-08-12 08:23:28 +0000 | [diff] [blame] | 12709 | pci_set_drvdata(pdev, dev); |
| 12710 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12711 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12712 | if (rc < 0) { |
| 12713 | free_netdev(dev); |
| 12714 | return rc; |
| 12715 | } |
| 12716 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12717 | BNX2X_DEV_INFO("This is a %s function\n", |
| 12718 | IS_PF(bp) ? "physical" : "virtual"); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12719 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12720 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
Merav Sicron | 60aa050 | 2012-06-19 07:48:29 +0000 | [diff] [blame] | 12721 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
Yuval Mintz | 2de6743 | 2013-01-23 03:21:43 +0000 | [diff] [blame] | 12722 | tx_count, rx_count); |
Merav Sicron | 60aa050 | 2012-06-19 07:48:29 +0000 | [diff] [blame] | 12723 | |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12724 | rc = bnx2x_init_bp(bp); |
Eilon Greenstein | 693fc0d | 2009-01-14 06:43:52 +0000 | [diff] [blame] | 12725 | if (rc) |
| 12726 | goto init_one_exit; |
| 12727 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12728 | /* Map doorbells here as we need the real value of bp->max_cos which |
| 12729 | * is initialized in bnx2x_init_bp() to determine the number of |
| 12730 | * l2 connections. |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12731 | */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12732 | if (IS_VF(bp)) { |
Dmitry Kravkov | 1d6f3cd | 2013-03-27 01:05:17 +0000 | [diff] [blame] | 12733 | bp->doorbells = bnx2x_vf_doorbells(bp); |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 12734 | rc = bnx2x_vf_pci_alloc(bp); |
| 12735 | if (rc) |
| 12736 | goto init_one_exit; |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12737 | } else { |
| 12738 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); |
| 12739 | if (doorbell_size > pci_resource_len(pdev, 2)) { |
| 12740 | dev_err(&bp->pdev->dev, |
| 12741 | "Cannot map doorbells, bar size too small, aborting\n"); |
| 12742 | rc = -ENOMEM; |
| 12743 | goto init_one_exit; |
| 12744 | } |
| 12745 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), |
| 12746 | doorbell_size); |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 12747 | } |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12748 | if (!bp->doorbells) { |
| 12749 | dev_err(&bp->pdev->dev, |
| 12750 | "Cannot map doorbell space, aborting\n"); |
| 12751 | rc = -ENOMEM; |
| 12752 | goto init_one_exit; |
| 12753 | } |
| 12754 | |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 12755 | if (IS_VF(bp)) { |
| 12756 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); |
| 12757 | if (rc) |
| 12758 | goto init_one_exit; |
| 12759 | } |
| 12760 | |
Ariel Elior | 3c76fef | 2013-03-11 05:17:46 +0000 | [diff] [blame] | 12761 | /* Enable SRIOV if capability found in configuration space */ |
| 12762 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 12763 | if (rc) |
| 12764 | goto init_one_exit; |
| 12765 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12766 | /* calc qm_cid_count */ |
Ariel Elior | 6383c0b | 2011-07-14 08:31:57 +0000 | [diff] [blame] | 12767 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12768 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12769 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12770 | /* disable FCOE L2 queue for E1x*/ |
Dmitry Kravkov | 62ac0dc | 2011-11-13 04:34:21 +0000 | [diff] [blame] | 12771 | if (CHIP_IS_E1x(bp)) |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 12772 | bp->flags |= NO_FCOE_FLAG; |
| 12773 | |
Merav Sicron | 0e8d2ec | 2012-06-19 07:48:30 +0000 | [diff] [blame] | 12774 | /* Set bp->num_queues for MSI-X mode*/ |
| 12775 | bnx2x_set_num_queues(bp); |
| 12776 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 12777 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
Merav Sicron | 0e8d2ec | 2012-06-19 07:48:30 +0000 | [diff] [blame] | 12778 | * needed. |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 12779 | */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12780 | rc = bnx2x_set_int_mode(bp); |
| 12781 | if (rc) { |
| 12782 | dev_err(&pdev->dev, "Cannot set interrupts\n"); |
| 12783 | goto init_one_exit; |
| 12784 | } |
Yuval Mintz | 04c4673 | 2013-01-23 03:21:46 +0000 | [diff] [blame] | 12785 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 12786 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12787 | /* register the net device */ |
Vladislav Zolotarov | b340007 | 2010-11-24 11:09:50 -0800 | [diff] [blame] | 12788 | rc = register_netdev(dev); |
| 12789 | if (rc) { |
| 12790 | dev_err(&pdev->dev, "Cannot register net device\n"); |
| 12791 | goto init_one_exit; |
| 12792 | } |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12793 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
Vladislav Zolotarov | b340007 | 2010-11-24 11:09:50 -0800 | [diff] [blame] | 12794 | |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 12795 | if (!NO_FCOE(bp)) { |
| 12796 | /* Add storage MAC address */ |
| 12797 | rtnl_lock(); |
| 12798 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); |
| 12799 | rtnl_unlock(); |
| 12800 | } |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 12801 | |
Eilon Greenstein | 37f9ce6 | 2009-08-12 08:23:34 +0000 | [diff] [blame] | 12802 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12803 | BNX2X_DEV_INFO("got pcie width %d and speed %d\n", |
| 12804 | pcie_width, pcie_speed); |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 12805 | |
Dmitry Kravkov | ca1ee4b | 2013-05-27 04:08:27 +0000 | [diff] [blame] | 12806 | BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", |
| 12807 | board_info[ent->driver_data].name, |
| 12808 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), |
| 12809 | pcie_width, |
| 12810 | pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" : |
| 12811 | pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" : |
| 12812 | pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" : |
| 12813 | "Unknown", |
| 12814 | dev->base_addr, bp->pdev->irq, dev->dev_addr); |
Eilon Greenstein | c016201 | 2009-03-02 08:01:05 +0000 | [diff] [blame] | 12815 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12816 | return 0; |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12817 | |
| 12818 | init_one_exit: |
| 12819 | if (bp->regview) |
| 12820 | iounmap(bp->regview); |
| 12821 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12822 | if (IS_PF(bp) && bp->doorbells) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12823 | iounmap(bp->doorbells); |
| 12824 | |
| 12825 | free_netdev(dev); |
| 12826 | |
| 12827 | if (atomic_read(&pdev->enable_cnt) == 1) |
| 12828 | pci_release_regions(pdev); |
| 12829 | |
| 12830 | pci_disable_device(pdev); |
| 12831 | pci_set_drvdata(pdev, NULL); |
| 12832 | |
| 12833 | return rc; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12834 | } |
| 12835 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12836 | static void __bnx2x_remove(struct pci_dev *pdev, |
| 12837 | struct net_device *dev, |
| 12838 | struct bnx2x *bp, |
| 12839 | bool remove_netdev) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12840 | { |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 12841 | /* Delete storage MAC address */ |
| 12842 | if (!NO_FCOE(bp)) { |
| 12843 | rtnl_lock(); |
| 12844 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); |
| 12845 | rtnl_unlock(); |
| 12846 | } |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 12847 | |
Shmulik Ravid | 9850767 | 2011-02-28 12:19:55 -0800 | [diff] [blame] | 12848 | #ifdef BCM_DCBNL |
| 12849 | /* Delete app tlvs from dcbnl */ |
| 12850 | bnx2x_dcbnl_update_applist(bp, true); |
| 12851 | #endif |
| 12852 | |
Barak Witkowsky | a6d3a5b | 2013-08-13 02:25:02 +0300 | [diff] [blame] | 12853 | if (IS_PF(bp) && |
| 12854 | !BP_NOMCP(bp) && |
| 12855 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) |
| 12856 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); |
| 12857 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12858 | /* Close the interface - either directly or implicitly */ |
| 12859 | if (remove_netdev) { |
| 12860 | unregister_netdev(dev); |
| 12861 | } else { |
| 12862 | rtnl_lock(); |
Yuval Mintz | 6ef5a92 | 2013-08-13 02:25:03 +0300 | [diff] [blame] | 12863 | dev_close(dev); |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12864 | rtnl_unlock(); |
| 12865 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12866 | |
Ariel Elior | 78c3bcc | 2013-06-20 17:39:08 +0300 | [diff] [blame] | 12867 | bnx2x_iov_remove_one(bp); |
| 12868 | |
Vladislav Zolotarov | 084d6cb | 2011-01-09 02:20:19 +0000 | [diff] [blame] | 12869 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12870 | if (IS_PF(bp)) |
| 12871 | bnx2x_set_power_state(bp, PCI_D0); |
Vladislav Zolotarov | 084d6cb | 2011-01-09 02:20:19 +0000 | [diff] [blame] | 12872 | |
Dmitry Kravkov | d6214d7 | 2010-10-06 03:32:10 +0000 | [diff] [blame] | 12873 | /* Disable MSI/MSI-X */ |
| 12874 | bnx2x_disable_msi(bp); |
Dmitry Kravkov | f85582f | 2010-10-06 03:34:21 +0000 | [diff] [blame] | 12875 | |
Vladislav Zolotarov | 084d6cb | 2011-01-09 02:20:19 +0000 | [diff] [blame] | 12876 | /* Power off */ |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12877 | if (IS_PF(bp)) |
| 12878 | bnx2x_set_power_state(bp, PCI_D3hot); |
Vladislav Zolotarov | 084d6cb | 2011-01-09 02:20:19 +0000 | [diff] [blame] | 12879 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 12880 | /* Make sure RESET task is not scheduled before continuing */ |
Ariel Elior | 7be08a7 | 2011-07-14 08:31:19 +0000 | [diff] [blame] | 12881 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
Ariel Elior | 290ca2b | 2013-01-01 05:22:31 +0000 | [diff] [blame] | 12882 | |
Ariel Elior | 4513f92 | 2013-01-01 05:22:25 +0000 | [diff] [blame] | 12883 | /* send message via vfpf channel to release the resources of this vf */ |
| 12884 | if (IS_VF(bp)) |
| 12885 | bnx2x_vfpf_release(bp); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 12886 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12887 | /* Assumes no further PCIe PM changes will occur */ |
| 12888 | if (system_state == SYSTEM_POWER_OFF) { |
| 12889 | pci_wake_from_d3(pdev, bp->wol); |
| 12890 | pci_set_power_state(pdev, PCI_D3hot); |
| 12891 | } |
| 12892 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12893 | if (bp->regview) |
| 12894 | iounmap(bp->regview); |
| 12895 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12896 | /* for vf doorbells are part of the regview and were unmapped along with |
| 12897 | * it. FW is only loaded by PF. |
| 12898 | */ |
| 12899 | if (IS_PF(bp)) { |
| 12900 | if (bp->doorbells) |
| 12901 | iounmap(bp->doorbells); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12902 | |
Ariel Elior | 1ab4434 | 2013-01-01 05:22:23 +0000 | [diff] [blame] | 12903 | bnx2x_release_firmware(bp); |
| 12904 | } |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 12905 | bnx2x_free_mem_bp(bp); |
| 12906 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12907 | if (remove_netdev) |
| 12908 | free_netdev(dev); |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 12909 | |
| 12910 | if (atomic_read(&pdev->enable_cnt) == 1) |
| 12911 | pci_release_regions(pdev); |
| 12912 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 12913 | pci_disable_device(pdev); |
| 12914 | pci_set_drvdata(pdev, NULL); |
| 12915 | } |
| 12916 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 12917 | static void bnx2x_remove_one(struct pci_dev *pdev) |
| 12918 | { |
| 12919 | struct net_device *dev = pci_get_drvdata(pdev); |
| 12920 | struct bnx2x *bp; |
| 12921 | |
| 12922 | if (!dev) { |
| 12923 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
| 12924 | return; |
| 12925 | } |
| 12926 | bp = netdev_priv(dev); |
| 12927 | |
| 12928 | __bnx2x_remove(pdev, dev, bp, true); |
| 12929 | } |
| 12930 | |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12931 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
| 12932 | { |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12933 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12934 | |
| 12935 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
| 12936 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12937 | if (CNIC_LOADED(bp)) |
| 12938 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); |
| 12939 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12940 | /* Stop Tx */ |
| 12941 | bnx2x_tx_disable(bp); |
Merav Sicron | 26614ba | 2012-08-27 03:26:19 +0000 | [diff] [blame] | 12942 | /* Delete all NAPI objects */ |
| 12943 | bnx2x_del_all_napi(bp); |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 12944 | if (CNIC_LOADED(bp)) |
| 12945 | bnx2x_del_all_napi_cnic(bp); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12946 | netdev_reset_tc(bp->dev); |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12947 | |
| 12948 | del_timer_sync(&bp->timer); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12949 | cancel_delayed_work(&bp->sp_task); |
| 12950 | cancel_delayed_work(&bp->period_task); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12951 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12952 | spin_lock_bh(&bp->stats_lock); |
| 12953 | bp->stats_state = STATS_STATE_DISABLED; |
| 12954 | spin_unlock_bh(&bp->stats_lock); |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12955 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12956 | bnx2x_save_statistics(bp); |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12957 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 12958 | netif_carrier_off(bp->dev); |
| 12959 | |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12960 | return 0; |
| 12961 | } |
| 12962 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 12963 | /** |
| 12964 | * bnx2x_io_error_detected - called when PCI error is detected |
| 12965 | * @pdev: Pointer to PCI device |
| 12966 | * @state: The current pci connection state |
| 12967 | * |
| 12968 | * This function is called after a PCI bus error affecting |
| 12969 | * this device has been detected. |
| 12970 | */ |
| 12971 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, |
| 12972 | pci_channel_state_t state) |
| 12973 | { |
| 12974 | struct net_device *dev = pci_get_drvdata(pdev); |
| 12975 | struct bnx2x *bp = netdev_priv(dev); |
| 12976 | |
| 12977 | rtnl_lock(); |
| 12978 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12979 | BNX2X_ERR("IO error detected\n"); |
| 12980 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 12981 | netif_device_detach(dev); |
| 12982 | |
Dean Nelson | 07ce50e | 2009-07-31 09:13:25 +0000 | [diff] [blame] | 12983 | if (state == pci_channel_io_perm_failure) { |
| 12984 | rtnl_unlock(); |
| 12985 | return PCI_ERS_RESULT_DISCONNECT; |
| 12986 | } |
| 12987 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 12988 | if (netif_running(dev)) |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 12989 | bnx2x_eeh_nic_unload(bp); |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 12990 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 12991 | bnx2x_prev_path_mark_eeh(bp); |
| 12992 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 12993 | pci_disable_device(pdev); |
| 12994 | |
| 12995 | rtnl_unlock(); |
| 12996 | |
| 12997 | /* Request a slot reset */ |
| 12998 | return PCI_ERS_RESULT_NEED_RESET; |
| 12999 | } |
| 13000 | |
| 13001 | /** |
| 13002 | * bnx2x_io_slot_reset - called after the PCI bus has been reset |
| 13003 | * @pdev: Pointer to PCI device |
| 13004 | * |
| 13005 | * Restart the card from scratch, as if from a cold-boot. |
| 13006 | */ |
| 13007 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) |
| 13008 | { |
| 13009 | struct net_device *dev = pci_get_drvdata(pdev); |
| 13010 | struct bnx2x *bp = netdev_priv(dev); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13011 | int i; |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13012 | |
| 13013 | rtnl_lock(); |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13014 | BNX2X_ERR("IO slot reset initializing...\n"); |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13015 | if (pci_enable_device(pdev)) { |
| 13016 | dev_err(&pdev->dev, |
| 13017 | "Cannot re-enable PCI device after reset\n"); |
| 13018 | rtnl_unlock(); |
| 13019 | return PCI_ERS_RESULT_DISCONNECT; |
| 13020 | } |
| 13021 | |
| 13022 | pci_set_master(pdev); |
| 13023 | pci_restore_state(pdev); |
Yuval Mintz | 70632d0 | 2013-04-24 01:45:02 +0000 | [diff] [blame] | 13024 | pci_save_state(pdev); |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13025 | |
| 13026 | if (netif_running(dev)) |
| 13027 | bnx2x_set_power_state(bp, PCI_D0); |
| 13028 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13029 | if (netif_running(dev)) { |
| 13030 | BNX2X_ERR("IO slot reset --> driver unload\n"); |
Yuval Mintz | e68072e | 2013-05-22 21:21:51 +0000 | [diff] [blame] | 13031 | |
| 13032 | /* MCP should have been reset; Need to wait for validity */ |
| 13033 | bnx2x_init_shmem(bp); |
| 13034 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13035 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
| 13036 | u32 v; |
| 13037 | |
| 13038 | v = SHMEM2_RD(bp, |
| 13039 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); |
| 13040 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], |
| 13041 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); |
| 13042 | } |
| 13043 | bnx2x_drain_tx_queues(bp); |
| 13044 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); |
| 13045 | bnx2x_netif_stop(bp, 1); |
| 13046 | bnx2x_free_irq(bp); |
| 13047 | |
| 13048 | /* Report UNLOAD_DONE to MCP */ |
| 13049 | bnx2x_send_unload_done(bp, true); |
| 13050 | |
| 13051 | bp->sp_state = 0; |
| 13052 | bp->port.pmf = 0; |
| 13053 | |
| 13054 | bnx2x_prev_unload(bp); |
| 13055 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 13056 | /* We should have reseted the engine, so It's fair to |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13057 | * assume the FW will no longer write to the bnx2x driver. |
| 13058 | */ |
| 13059 | bnx2x_squeeze_objects(bp); |
| 13060 | bnx2x_free_skbs(bp); |
| 13061 | for_each_rx_queue(bp, i) |
| 13062 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
| 13063 | bnx2x_free_fp_mem(bp); |
| 13064 | bnx2x_free_mem(bp); |
| 13065 | |
| 13066 | bp->state = BNX2X_STATE_CLOSED; |
| 13067 | } |
| 13068 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13069 | rtnl_unlock(); |
| 13070 | |
| 13071 | return PCI_ERS_RESULT_RECOVERED; |
| 13072 | } |
| 13073 | |
| 13074 | /** |
| 13075 | * bnx2x_io_resume - called when traffic can start flowing again |
| 13076 | * @pdev: Pointer to PCI device |
| 13077 | * |
| 13078 | * This callback is called when the error recovery driver tells us that |
| 13079 | * its OK to resume normal operation. |
| 13080 | */ |
| 13081 | static void bnx2x_io_resume(struct pci_dev *pdev) |
| 13082 | { |
| 13083 | struct net_device *dev = pci_get_drvdata(pdev); |
| 13084 | struct bnx2x *bp = netdev_priv(dev); |
| 13085 | |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 13086 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13087 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
Vladislav Zolotarov | 72fd071 | 2010-04-19 01:13:12 +0000 | [diff] [blame] | 13088 | return; |
| 13089 | } |
| 13090 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13091 | rtnl_lock(); |
| 13092 | |
Yuval Mintz | 7fa6f340 | 2013-03-20 05:21:28 +0000 | [diff] [blame] | 13093 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
| 13094 | DRV_MSG_SEQ_NUMBER_MASK; |
| 13095 | |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13096 | if (netif_running(dev)) |
Yitchak Gertner | f8ef6e4 | 2008-09-09 05:07:25 -0700 | [diff] [blame] | 13097 | bnx2x_nic_load(bp, LOAD_NORMAL); |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13098 | |
| 13099 | netif_device_attach(dev); |
| 13100 | |
| 13101 | rtnl_unlock(); |
| 13102 | } |
| 13103 | |
Stephen Hemminger | 3646f0e | 2012-09-07 09:33:15 -0700 | [diff] [blame] | 13104 | static const struct pci_error_handlers bnx2x_err_handler = { |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13105 | .error_detected = bnx2x_io_error_detected, |
Eilon Greenstein | 356e238 | 2009-02-12 08:38:32 +0000 | [diff] [blame] | 13106 | .slot_reset = bnx2x_io_slot_reset, |
| 13107 | .resume = bnx2x_io_resume, |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13108 | }; |
| 13109 | |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 13110 | static void bnx2x_shutdown(struct pci_dev *pdev) |
| 13111 | { |
| 13112 | struct net_device *dev = pci_get_drvdata(pdev); |
| 13113 | struct bnx2x *bp; |
| 13114 | |
| 13115 | if (!dev) |
| 13116 | return; |
| 13117 | |
| 13118 | bp = netdev_priv(dev); |
| 13119 | if (!bp) |
| 13120 | return; |
| 13121 | |
| 13122 | rtnl_lock(); |
| 13123 | netif_device_detach(dev); |
| 13124 | rtnl_unlock(); |
| 13125 | |
| 13126 | /* Don't remove the netdevice, as there are scenarios which will cause |
| 13127 | * the kernel to hang, e.g., when trying to remove bnx2i while the |
| 13128 | * rootfs is mounted from SAN. |
| 13129 | */ |
| 13130 | __bnx2x_remove(pdev, dev, bp, false); |
| 13131 | } |
| 13132 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13133 | static struct pci_driver bnx2x_pci_driver = { |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13134 | .name = DRV_MODULE_NAME, |
| 13135 | .id_table = bnx2x_pci_tbl, |
| 13136 | .probe = bnx2x_init_one, |
Bill Pemberton | 0329aba | 2012-12-03 09:24:24 -0500 | [diff] [blame] | 13137 | .remove = bnx2x_remove_one, |
Wendy Xiong | 493adb1 | 2008-06-23 20:36:22 -0700 | [diff] [blame] | 13138 | .suspend = bnx2x_suspend, |
| 13139 | .resume = bnx2x_resume, |
| 13140 | .err_handler = &bnx2x_err_handler, |
Ariel Elior | 3c76fef | 2013-03-11 05:17:46 +0000 | [diff] [blame] | 13141 | #ifdef CONFIG_BNX2X_SRIOV |
| 13142 | .sriov_configure = bnx2x_sriov_configure, |
| 13143 | #endif |
Yuval Mintz | b030ed2 | 2013-05-27 04:08:30 +0000 | [diff] [blame] | 13144 | .shutdown = bnx2x_shutdown, |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13145 | }; |
| 13146 | |
| 13147 | static int __init bnx2x_init(void) |
| 13148 | { |
Stanislaw Gruszka | dd21ca6 | 2009-05-05 23:22:01 +0000 | [diff] [blame] | 13149 | int ret; |
| 13150 | |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 13151 | pr_info("%s", version); |
Eilon Greenstein | 938cf54 | 2009-08-12 08:23:37 +0000 | [diff] [blame] | 13152 | |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 13153 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
| 13154 | if (bnx2x_wq == NULL) { |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 13155 | pr_err("Cannot create workqueue\n"); |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 13156 | return -ENOMEM; |
| 13157 | } |
| 13158 | |
Stanislaw Gruszka | dd21ca6 | 2009-05-05 23:22:01 +0000 | [diff] [blame] | 13159 | ret = pci_register_driver(&bnx2x_pci_driver); |
| 13160 | if (ret) { |
Joe Perches | 7995c64 | 2010-02-17 15:01:52 +0000 | [diff] [blame] | 13161 | pr_err("Cannot register driver\n"); |
Stanislaw Gruszka | dd21ca6 | 2009-05-05 23:22:01 +0000 | [diff] [blame] | 13162 | destroy_workqueue(bnx2x_wq); |
| 13163 | } |
| 13164 | return ret; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13165 | } |
| 13166 | |
| 13167 | static void __exit bnx2x_cleanup(void) |
| 13168 | { |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 13169 | struct list_head *pos, *q; |
Yuval Mintz | d76a611 | 2013-06-02 00:06:17 +0000 | [diff] [blame] | 13170 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13171 | pci_unregister_driver(&bnx2x_pci_driver); |
Eilon Greenstein | 1cf167f | 2009-01-14 21:22:18 -0800 | [diff] [blame] | 13172 | |
| 13173 | destroy_workqueue(bnx2x_wq); |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 13174 | |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 13175 | /* Free globally allocated resources */ |
Yuval Mintz | 452427b | 2012-03-26 20:47:07 +0000 | [diff] [blame] | 13176 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
| 13177 | struct bnx2x_prev_path_list *tmp = |
| 13178 | list_entry(pos, struct bnx2x_prev_path_list, list); |
| 13179 | list_del(pos); |
| 13180 | kfree(tmp); |
| 13181 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13182 | } |
| 13183 | |
Yaniv Rosner | 3deb816 | 2011-06-14 01:34:33 +0000 | [diff] [blame] | 13184 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
| 13185 | { |
| 13186 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); |
| 13187 | } |
| 13188 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 13189 | module_init(bnx2x_init); |
| 13190 | module_exit(bnx2x_cleanup); |
| 13191 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13192 | /** |
| 13193 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). |
| 13194 | * |
| 13195 | * @bp: driver handle |
| 13196 | * @set: set or clear the CAM entry |
| 13197 | * |
Yuval Mintz | 16a5fd9 | 2013-06-02 00:06:18 +0000 | [diff] [blame] | 13198 | * This function will wait until the ramrod completion returns. |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13199 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
| 13200 | */ |
Eric Dumazet | 1191cb8 | 2012-04-27 21:39:21 +0000 | [diff] [blame] | 13201 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13202 | { |
| 13203 | unsigned long ramrod_flags = 0; |
| 13204 | |
| 13205 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
| 13206 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, |
| 13207 | &bp->iscsi_l2_mac_obj, true, |
| 13208 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); |
| 13209 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13210 | |
| 13211 | /* count denotes the number of new completions we have seen */ |
| 13212 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) |
| 13213 | { |
| 13214 | struct eth_spe *spe; |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 13215 | int cxt_index, cxt_offset; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13216 | |
| 13217 | #ifdef BNX2X_STOP_ON_ERROR |
| 13218 | if (unlikely(bp->panic)) |
| 13219 | return; |
| 13220 | #endif |
| 13221 | |
| 13222 | spin_lock_bh(&bp->spq_lock); |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13223 | BUG_ON(bp->cnic_spq_pending < count); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13224 | bp->cnic_spq_pending -= count; |
| 13225 | |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13226 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
| 13227 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) |
| 13228 | & SPE_HDR_CONN_TYPE) >> |
| 13229 | SPE_HDR_CONN_TYPE_SHIFT; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13230 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
| 13231 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13232 | |
| 13233 | /* Set validation for iSCSI L2 client before sending SETUP |
| 13234 | * ramrod |
| 13235 | */ |
| 13236 | if (type == ETH_CONNECTION_TYPE) { |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 13237 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13238 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 13239 | ILT_PAGE_CIDS; |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13240 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 13241 | (cxt_index * ILT_PAGE_CIDS); |
| 13242 | bnx2x_set_ctx_validation(bp, |
| 13243 | &bp->context[cxt_index]. |
| 13244 | vcxt[cxt_offset].eth, |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13245 | BNX2X_ISCSI_ETH_CID(bp)); |
Merav Sicron | a052997 | 2012-06-19 07:48:25 +0000 | [diff] [blame] | 13246 | } |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13247 | } |
| 13248 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13249 | /* |
| 13250 | * There may be not more than 8 L2, not more than 8 L5 SPEs |
| 13251 | * and in the air. We also check that number of outstanding |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 13252 | * COMMON ramrods is not more than the EQ and SPQ can |
| 13253 | * accommodate. |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13254 | */ |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 13255 | if (type == ETH_CONNECTION_TYPE) { |
| 13256 | if (!atomic_read(&bp->cq_spq_left)) |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13257 | break; |
| 13258 | else |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 13259 | atomic_dec(&bp->cq_spq_left); |
| 13260 | } else if (type == NONE_CONNECTION_TYPE) { |
| 13261 | if (!atomic_read(&bp->eq_spq_left)) |
| 13262 | break; |
| 13263 | else |
| 13264 | atomic_dec(&bp->eq_spq_left); |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 13265 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
| 13266 | (type == FCOE_CONNECTION_TYPE)) { |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13267 | if (bp->cnic_spq_pending >= |
| 13268 | bp->cnic_eth_dev.max_kwqe_pending) |
| 13269 | break; |
| 13270 | else |
| 13271 | bp->cnic_spq_pending++; |
| 13272 | } else { |
| 13273 | BNX2X_ERR("Unknown SPE type: %d\n", type); |
| 13274 | bnx2x_panic(); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13275 | break; |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13276 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13277 | |
| 13278 | spe = bnx2x_sp_get_next(bp); |
| 13279 | *spe = *bp->cnic_kwq_cons; |
| 13280 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13281 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13282 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
| 13283 | |
| 13284 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) |
| 13285 | bp->cnic_kwq_cons = bp->cnic_kwq; |
| 13286 | else |
| 13287 | bp->cnic_kwq_cons++; |
| 13288 | } |
| 13289 | bnx2x_sp_prod_update(bp); |
| 13290 | spin_unlock_bh(&bp->spq_lock); |
| 13291 | } |
| 13292 | |
| 13293 | static int bnx2x_cnic_sp_queue(struct net_device *dev, |
| 13294 | struct kwqe_16 *kwqes[], u32 count) |
| 13295 | { |
| 13296 | struct bnx2x *bp = netdev_priv(dev); |
| 13297 | int i; |
| 13298 | |
| 13299 | #ifdef BNX2X_STOP_ON_ERROR |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13300 | if (unlikely(bp->panic)) { |
| 13301 | BNX2X_ERR("Can't post to SP queue while panic\n"); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13302 | return -EIO; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13303 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13304 | #endif |
| 13305 | |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 13306 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
| 13307 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13308 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
Ariel Elior | 95c6c616 | 2012-01-26 06:01:52 +0000 | [diff] [blame] | 13309 | return -EAGAIN; |
| 13310 | } |
| 13311 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13312 | spin_lock_bh(&bp->spq_lock); |
| 13313 | |
| 13314 | for (i = 0; i < count; i++) { |
| 13315 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; |
| 13316 | |
| 13317 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) |
| 13318 | break; |
| 13319 | |
| 13320 | *bp->cnic_kwq_prod = *spe; |
| 13321 | |
| 13322 | bp->cnic_kwq_pending++; |
| 13323 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13324 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13325 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13326 | spe->data.update_data_addr.hi, |
| 13327 | spe->data.update_data_addr.lo, |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13328 | bp->cnic_kwq_pending); |
| 13329 | |
| 13330 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) |
| 13331 | bp->cnic_kwq_prod = bp->cnic_kwq; |
| 13332 | else |
| 13333 | bp->cnic_kwq_prod++; |
| 13334 | } |
| 13335 | |
| 13336 | spin_unlock_bh(&bp->spq_lock); |
| 13337 | |
| 13338 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) |
| 13339 | bnx2x_cnic_sp_post(bp, 0); |
| 13340 | |
| 13341 | return i; |
| 13342 | } |
| 13343 | |
| 13344 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) |
| 13345 | { |
| 13346 | struct cnic_ops *c_ops; |
| 13347 | int rc = 0; |
| 13348 | |
| 13349 | mutex_lock(&bp->cnic_mutex); |
Eric Dumazet | 13707f9 | 2011-01-26 19:28:23 +0000 | [diff] [blame] | 13350 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
| 13351 | lockdep_is_held(&bp->cnic_mutex)); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13352 | if (c_ops) |
| 13353 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); |
| 13354 | mutex_unlock(&bp->cnic_mutex); |
| 13355 | |
| 13356 | return rc; |
| 13357 | } |
| 13358 | |
| 13359 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) |
| 13360 | { |
| 13361 | struct cnic_ops *c_ops; |
| 13362 | int rc = 0; |
| 13363 | |
| 13364 | rcu_read_lock(); |
| 13365 | c_ops = rcu_dereference(bp->cnic_ops); |
| 13366 | if (c_ops) |
| 13367 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); |
| 13368 | rcu_read_unlock(); |
| 13369 | |
| 13370 | return rc; |
| 13371 | } |
| 13372 | |
| 13373 | /* |
| 13374 | * for commands that have no data |
| 13375 | */ |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 13376 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13377 | { |
| 13378 | struct cnic_ctl_info ctl = {0}; |
| 13379 | |
| 13380 | ctl.cmd = cmd; |
| 13381 | |
| 13382 | return bnx2x_cnic_ctl_send(bp, &ctl); |
| 13383 | } |
| 13384 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13385 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13386 | { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13387 | struct cnic_ctl_info ctl = {0}; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13388 | |
| 13389 | /* first we tell CNIC and only then we count this as a completion */ |
| 13390 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; |
| 13391 | ctl.data.comp.cid = cid; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13392 | ctl.data.comp.error = err; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13393 | |
| 13394 | bnx2x_cnic_ctl_send_bh(bp, &ctl); |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13395 | bnx2x_cnic_sp_post(bp, 0); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13396 | } |
| 13397 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13398 | /* Called with netif_addr_lock_bh() taken. |
| 13399 | * Sets an rx_mode config for an iSCSI ETH client. |
| 13400 | * Doesn't block. |
| 13401 | * Completion should be checked outside. |
| 13402 | */ |
| 13403 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) |
| 13404 | { |
| 13405 | unsigned long accept_flags = 0, ramrod_flags = 0; |
| 13406 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); |
| 13407 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; |
| 13408 | |
| 13409 | if (start) { |
| 13410 | /* Start accepting on iSCSI L2 ring. Accept all multicasts |
| 13411 | * because it's the only way for UIO Queue to accept |
| 13412 | * multicasts (in non-promiscuous mode only one Queue per |
| 13413 | * function will receive multicast packets (leading in our |
| 13414 | * case). |
| 13415 | */ |
| 13416 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); |
| 13417 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); |
| 13418 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); |
| 13419 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); |
| 13420 | |
| 13421 | /* Clear STOP_PENDING bit if START is requested */ |
| 13422 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); |
| 13423 | |
| 13424 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; |
| 13425 | } else |
| 13426 | /* Clear START_PENDING bit if STOP is requested */ |
| 13427 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); |
| 13428 | |
| 13429 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) |
| 13430 | set_bit(sched_state, &bp->sp_state); |
| 13431 | else { |
| 13432 | __set_bit(RAMROD_RX, &ramrod_flags); |
| 13433 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, |
| 13434 | ramrod_flags); |
| 13435 | } |
| 13436 | } |
| 13437 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13438 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
| 13439 | { |
| 13440 | struct bnx2x *bp = netdev_priv(dev); |
| 13441 | int rc = 0; |
| 13442 | |
| 13443 | switch (ctl->cmd) { |
| 13444 | case DRV_CTL_CTXTBL_WR_CMD: { |
| 13445 | u32 index = ctl->data.io.offset; |
| 13446 | dma_addr_t addr = ctl->data.io.dma_addr; |
| 13447 | |
| 13448 | bnx2x_ilt_wr(bp, index, addr); |
| 13449 | break; |
| 13450 | } |
| 13451 | |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13452 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
| 13453 | int count = ctl->data.credit.credit_count; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13454 | |
| 13455 | bnx2x_cnic_sp_post(bp, count); |
| 13456 | break; |
| 13457 | } |
| 13458 | |
| 13459 | /* rtnl_lock is held. */ |
| 13460 | case DRV_CTL_START_L2_CMD: { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13461 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| 13462 | unsigned long sp_bits = 0; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13463 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13464 | /* Configure the iSCSI classification object */ |
| 13465 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, |
| 13466 | cp->iscsi_l2_client_id, |
| 13467 | cp->iscsi_l2_cid, BP_FUNC(bp), |
| 13468 | bnx2x_sp(bp, mac_rdata), |
| 13469 | bnx2x_sp_mapping(bp, mac_rdata), |
| 13470 | BNX2X_FILTER_MAC_PENDING, |
| 13471 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, |
| 13472 | &bp->macs_pool); |
Vladislav Zolotarov | ec6ba94 | 2010-12-13 05:44:01 +0000 | [diff] [blame] | 13473 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13474 | /* Set iSCSI MAC address */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13475 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
| 13476 | if (rc) |
| 13477 | break; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13478 | |
| 13479 | mmiowb(); |
| 13480 | barrier(); |
| 13481 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13482 | /* Start accepting on iSCSI L2 ring */ |
| 13483 | |
| 13484 | netif_addr_lock_bh(dev); |
| 13485 | bnx2x_set_iscsi_eth_rx_mode(bp, true); |
| 13486 | netif_addr_unlock_bh(dev); |
| 13487 | |
| 13488 | /* bits to wait on */ |
| 13489 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); |
| 13490 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); |
| 13491 | |
| 13492 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) |
| 13493 | BNX2X_ERR("rx_mode completion timed out!\n"); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13494 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13495 | break; |
| 13496 | } |
| 13497 | |
| 13498 | /* rtnl_lock is held. */ |
| 13499 | case DRV_CTL_STOP_L2_CMD: { |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13500 | unsigned long sp_bits = 0; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13501 | |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13502 | /* Stop accepting on iSCSI L2 ring */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13503 | netif_addr_lock_bh(dev); |
| 13504 | bnx2x_set_iscsi_eth_rx_mode(bp, false); |
| 13505 | netif_addr_unlock_bh(dev); |
| 13506 | |
| 13507 | /* bits to wait on */ |
| 13508 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); |
| 13509 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); |
| 13510 | |
| 13511 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) |
| 13512 | BNX2X_ERR("rx_mode completion timed out!\n"); |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13513 | |
| 13514 | mmiowb(); |
| 13515 | barrier(); |
| 13516 | |
| 13517 | /* Unset iSCSI L2 MAC */ |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13518 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
| 13519 | BNX2X_ISCSI_ETH_MAC, true); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13520 | break; |
| 13521 | } |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13522 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
| 13523 | int count = ctl->data.credit.credit_count; |
| 13524 | |
| 13525 | smp_mb__before_atomic_inc(); |
Vladislav Zolotarov | 6e30dd4 | 2011-02-06 11:25:41 -0800 | [diff] [blame] | 13526 | atomic_add(count, &bp->cq_spq_left); |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13527 | smp_mb__after_atomic_inc(); |
| 13528 | break; |
| 13529 | } |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13530 | case DRV_CTL_ULP_REGISTER_CMD: { |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 13531 | int ulp_type = ctl->data.register_data.ulp_type; |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13532 | |
| 13533 | if (CHIP_IS_E3(bp)) { |
| 13534 | int idx = BP_FW_MB_IDX(bp); |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 13535 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
| 13536 | int path = BP_PATH(bp); |
| 13537 | int port = BP_PORT(bp); |
| 13538 | int i; |
| 13539 | u32 scratch_offset; |
| 13540 | u32 *host_addr; |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13541 | |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 13542 | /* first write capability to shmem2 */ |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13543 | if (ulp_type == CNIC_ULP_ISCSI) |
| 13544 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; |
| 13545 | else if (ulp_type == CNIC_ULP_FCOE) |
| 13546 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; |
| 13547 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 13548 | |
| 13549 | if ((ulp_type != CNIC_ULP_FCOE) || |
| 13550 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || |
| 13551 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) |
| 13552 | break; |
| 13553 | |
| 13554 | /* if reached here - should write fcoe capabilities */ |
| 13555 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); |
| 13556 | if (!scratch_offset) |
| 13557 | break; |
| 13558 | scratch_offset += offsetof(struct glob_ncsi_oem_data, |
| 13559 | fcoe_features[path][port]); |
| 13560 | host_addr = (u32 *) &(ctl->data.register_data. |
| 13561 | fcoe_features); |
| 13562 | for (i = 0; i < sizeof(struct fcoe_capabilities); |
| 13563 | i += 4) |
| 13564 | REG_WR(bp, scratch_offset + i, |
| 13565 | *(host_addr + i/4)); |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13566 | } |
| 13567 | break; |
| 13568 | } |
Barak Witkowski | 2e499d3 | 2012-06-26 01:31:19 +0000 | [diff] [blame] | 13569 | |
Barak Witkowski | 1d187b3 | 2011-12-05 22:41:50 +0000 | [diff] [blame] | 13570 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
| 13571 | int ulp_type = ctl->data.ulp_type; |
| 13572 | |
| 13573 | if (CHIP_IS_E3(bp)) { |
| 13574 | int idx = BP_FW_MB_IDX(bp); |
| 13575 | u32 cap; |
| 13576 | |
| 13577 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
| 13578 | if (ulp_type == CNIC_ULP_ISCSI) |
| 13579 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; |
| 13580 | else if (ulp_type == CNIC_ULP_FCOE) |
| 13581 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; |
| 13582 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); |
| 13583 | } |
| 13584 | break; |
| 13585 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13586 | |
| 13587 | default: |
| 13588 | BNX2X_ERR("unknown command %x\n", ctl->cmd); |
| 13589 | rc = -EINVAL; |
| 13590 | } |
| 13591 | |
| 13592 | return rc; |
| 13593 | } |
| 13594 | |
Dmitry Kravkov | 9f6c925 | 2010-07-27 12:34:34 +0000 | [diff] [blame] | 13595 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13596 | { |
| 13597 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| 13598 | |
| 13599 | if (bp->flags & USING_MSIX_FLAG) { |
| 13600 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; |
| 13601 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; |
| 13602 | cp->irq_arr[0].vector = bp->msix_table[1].vector; |
| 13603 | } else { |
| 13604 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; |
| 13605 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; |
| 13606 | } |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13607 | if (!CHIP_IS_E1x(bp)) |
Dmitry Kravkov | f2e0899 | 2010-10-06 03:28:26 +0000 | [diff] [blame] | 13608 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
| 13609 | else |
| 13610 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; |
| 13611 | |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13612 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
| 13613 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13614 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
| 13615 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13616 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13617 | |
| 13618 | cp->num_irq = 2; |
| 13619 | } |
| 13620 | |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13621 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
| 13622 | { |
| 13623 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| 13624 | |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13625 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
| 13626 | bnx2x_cid_ilt_lines(bp); |
| 13627 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
| 13628 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
| 13629 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
| 13630 | |
| 13631 | if (NO_ISCSI_OOO(bp)) |
| 13632 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; |
| 13633 | } |
| 13634 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13635 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
| 13636 | void *data) |
| 13637 | { |
| 13638 | struct bnx2x *bp = netdev_priv(dev); |
| 13639 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 13640 | int rc; |
| 13641 | |
| 13642 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13643 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13644 | if (ops == NULL) { |
| 13645 | BNX2X_ERR("NULL ops received\n"); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13646 | return -EINVAL; |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13647 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13648 | |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 13649 | if (!CNIC_SUPPORT(bp)) { |
| 13650 | BNX2X_ERR("Can't register CNIC when not supported\n"); |
| 13651 | return -EOPNOTSUPP; |
| 13652 | } |
| 13653 | |
| 13654 | if (!CNIC_LOADED(bp)) { |
| 13655 | rc = bnx2x_load_cnic(bp); |
| 13656 | if (rc) { |
| 13657 | BNX2X_ERR("CNIC-related load failed\n"); |
| 13658 | return rc; |
| 13659 | } |
Merav Sicron | 55c1194 | 2012-11-07 00:45:48 +0000 | [diff] [blame] | 13660 | } |
| 13661 | |
| 13662 | bp->cnic_enabled = true; |
| 13663 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13664 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
| 13665 | if (!bp->cnic_kwq) |
| 13666 | return -ENOMEM; |
| 13667 | |
| 13668 | bp->cnic_kwq_cons = bp->cnic_kwq; |
| 13669 | bp->cnic_kwq_prod = bp->cnic_kwq; |
| 13670 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; |
| 13671 | |
| 13672 | bp->cnic_spq_pending = 0; |
| 13673 | bp->cnic_kwq_pending = 0; |
| 13674 | |
| 13675 | bp->cnic_data = data; |
| 13676 | |
| 13677 | cp->num_irq = 0; |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13678 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13679 | cp->iro_arr = bp->iro_arr; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13680 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13681 | bnx2x_setup_cnic_irq_info(bp); |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13682 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13683 | rcu_assign_pointer(bp->cnic_ops, ops); |
| 13684 | |
| 13685 | return 0; |
| 13686 | } |
| 13687 | |
| 13688 | static int bnx2x_unregister_cnic(struct net_device *dev) |
| 13689 | { |
| 13690 | struct bnx2x *bp = netdev_priv(dev); |
| 13691 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| 13692 | |
| 13693 | mutex_lock(&bp->cnic_mutex); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13694 | cp->drv_state = 0; |
Eric Dumazet | 2cfa5a0 | 2011-11-23 07:09:32 +0000 | [diff] [blame] | 13695 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13696 | mutex_unlock(&bp->cnic_mutex); |
| 13697 | synchronize_rcu(); |
Yuval Mintz | fea7564 | 2013-04-10 13:34:39 +0300 | [diff] [blame] | 13698 | bp->cnic_enabled = false; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13699 | kfree(bp->cnic_kwq); |
| 13700 | bp->cnic_kwq = NULL; |
| 13701 | |
| 13702 | return 0; |
| 13703 | } |
| 13704 | |
| 13705 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) |
| 13706 | { |
| 13707 | struct bnx2x *bp = netdev_priv(dev); |
| 13708 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
| 13709 | |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 13710 | /* If both iSCSI and FCoE are disabled - return NULL in |
| 13711 | * order to indicate CNIC that it should not try to work |
| 13712 | * with this device. |
| 13713 | */ |
| 13714 | if (NO_ISCSI(bp) && NO_FCOE(bp)) |
| 13715 | return NULL; |
| 13716 | |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13717 | cp->drv_owner = THIS_MODULE; |
| 13718 | cp->chip_id = CHIP_ID(bp); |
| 13719 | cp->pdev = bp->pdev; |
| 13720 | cp->io_base = bp->regview; |
| 13721 | cp->io_base2 = bp->doorbells; |
| 13722 | cp->max_kwqe_pending = 8; |
Dmitry Kravkov | 523224a | 2010-10-06 03:23:26 +0000 | [diff] [blame] | 13723 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13724 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
| 13725 | bnx2x_cid_ilt_lines(bp); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13726 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13727 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13728 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
| 13729 | cp->drv_ctl = bnx2x_drv_ctl; |
| 13730 | cp->drv_register_cnic = bnx2x_register_cnic; |
| 13731 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13732 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
Vlad Zolotarov | 619c5cb | 2011-06-14 14:33:44 +0300 | [diff] [blame] | 13733 | cp->iscsi_l2_client_id = |
| 13734 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); |
Merav Sicron | 37ae41a | 2012-06-19 07:48:27 +0000 | [diff] [blame] | 13735 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13736 | |
Vladislav Zolotarov | 2ba4514 | 2011-01-31 14:39:17 +0000 | [diff] [blame] | 13737 | if (NO_ISCSI_OOO(bp)) |
| 13738 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; |
| 13739 | |
| 13740 | if (NO_ISCSI(bp)) |
| 13741 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; |
| 13742 | |
| 13743 | if (NO_FCOE(bp)) |
| 13744 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; |
| 13745 | |
Merav Sicron | 51c1a58 | 2012-03-18 10:33:38 +0000 | [diff] [blame] | 13746 | BNX2X_DEV_INFO( |
| 13747 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", |
Dmitry Kravkov | c2bff63 | 2010-10-06 03:33:18 +0000 | [diff] [blame] | 13748 | cp->ctx_blk_size, |
| 13749 | cp->ctx_tbl_offset, |
| 13750 | cp->ctx_tbl_len, |
| 13751 | cp->starting_cid); |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13752 | return cp; |
| 13753 | } |
Michael Chan | 993ac7b | 2009-10-10 13:46:56 +0000 | [diff] [blame] | 13754 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13755 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13756 | { |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13757 | struct bnx2x *bp = fp->bp; |
| 13758 | u32 offset = BAR_USTRORM_INTMEM; |
Vladislav Zolotarov | 94a78b7 | 2009-04-27 03:27:43 -0700 | [diff] [blame] | 13759 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13760 | if (IS_VF(bp)) |
| 13761 | return bnx2x_vf_ustorm_prods_offset(bp, fp); |
| 13762 | else if (!CHIP_IS_E1x(bp)) |
| 13763 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); |
| 13764 | else |
| 13765 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13766 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13767 | return offset; |
| 13768 | } |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13769 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13770 | /* called only on E1H or E2. |
| 13771 | * When pretending to be PF, the pretend value is the function number 0...7 |
| 13772 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID |
| 13773 | * combination |
| 13774 | */ |
| 13775 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) |
| 13776 | { |
| 13777 | u32 pretend_reg; |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13778 | |
Ariel Elior | 2382685 | 2013-01-09 07:04:35 +0000 | [diff] [blame] | 13779 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13780 | return -1; |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13781 | |
Ariel Elior | 6411280 | 2013-01-07 00:50:23 +0000 | [diff] [blame] | 13782 | /* get my own pretend register */ |
| 13783 | pretend_reg = bnx2x_get_pretend_reg(bp); |
| 13784 | REG_WR(bp, pretend_reg, pretend_func_val); |
| 13785 | REG_RD(bp, pretend_reg); |
Ariel Elior | be1f1ffa | 2013-01-01 05:22:24 +0000 | [diff] [blame] | 13786 | return 0; |
| 13787 | } |