Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "drmP.h" |
| 36 | #include "intel_drv.h" |
| 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 39 | #include "i915_trace.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 40 | #include "drm_dp_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 41 | #include "drm_crtc_helper.h" |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 42 | #include <linux/dma_remapping.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
| 45 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 49 | |
| 50 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 51 | /* given values */ |
| 52 | int n; |
| 53 | int m1, m2; |
| 54 | int p1, p2; |
| 55 | /* derived values */ |
| 56 | int dot; |
| 57 | int vco; |
| 58 | int m; |
| 59 | int p; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 60 | } intel_clock_t; |
| 61 | |
| 62 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 63 | int min, max; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 64 | } intel_range_t; |
| 65 | |
| 66 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 67 | int dot_limit; |
| 68 | int p2_slow, p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 69 | } intel_p2_t; |
| 70 | |
| 71 | #define INTEL_P2_NUM 2 |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 72 | typedef struct intel_limit intel_limit_t; |
| 73 | struct intel_limit { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 74 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 75 | intel_p2_t p2; |
| 76 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 77 | int, int, intel_clock_t *, intel_clock_t *); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 78 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 79 | |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 80 | /* FDI */ |
| 81 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ |
| 82 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 83 | static bool |
| 84 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 85 | int target, int refclk, intel_clock_t *match_clock, |
| 86 | intel_clock_t *best_clock); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 87 | static bool |
| 88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 89 | int target, int refclk, intel_clock_t *match_clock, |
| 90 | intel_clock_t *best_clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 91 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 92 | static bool |
| 93 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 94 | int target, int refclk, intel_clock_t *match_clock, |
| 95 | intel_clock_t *best_clock); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 96 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 97 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 98 | int target, int refclk, intel_clock_t *match_clock, |
| 99 | intel_clock_t *best_clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 100 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 101 | static inline u32 /* units of 100MHz */ |
| 102 | intel_fdi_link_freq(struct drm_device *dev) |
| 103 | { |
Chris Wilson | 8b99e68 | 2010-10-13 09:59:17 +0100 | [diff] [blame] | 104 | if (IS_GEN5(dev)) { |
| 105 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 106 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 107 | } else |
| 108 | return 27; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 109 | } |
| 110 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 112 | .dot = { .min = 25000, .max = 350000 }, |
| 113 | .vco = { .min = 930000, .max = 1400000 }, |
| 114 | .n = { .min = 3, .max = 16 }, |
| 115 | .m = { .min = 96, .max = 140 }, |
| 116 | .m1 = { .min = 18, .max = 26 }, |
| 117 | .m2 = { .min = 6, .max = 16 }, |
| 118 | .p = { .min = 4, .max = 128 }, |
| 119 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 120 | .p2 = { .dot_limit = 165000, |
| 121 | .p2_slow = 4, .p2_fast = 2 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 122 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 126 | .dot = { .min = 25000, .max = 350000 }, |
| 127 | .vco = { .min = 930000, .max = 1400000 }, |
| 128 | .n = { .min = 3, .max = 16 }, |
| 129 | .m = { .min = 96, .max = 140 }, |
| 130 | .m1 = { .min = 18, .max = 26 }, |
| 131 | .m2 = { .min = 6, .max = 16 }, |
| 132 | .p = { .min = 4, .max = 128 }, |
| 133 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 134 | .p2 = { .dot_limit = 165000, |
| 135 | .p2_slow = 14, .p2_fast = 7 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 136 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 137 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 138 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 139 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 140 | .dot = { .min = 20000, .max = 400000 }, |
| 141 | .vco = { .min = 1400000, .max = 2800000 }, |
| 142 | .n = { .min = 1, .max = 6 }, |
| 143 | .m = { .min = 70, .max = 120 }, |
| 144 | .m1 = { .min = 10, .max = 22 }, |
| 145 | .m2 = { .min = 5, .max = 9 }, |
| 146 | .p = { .min = 5, .max = 80 }, |
| 147 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 148 | .p2 = { .dot_limit = 200000, |
| 149 | .p2_slow = 10, .p2_fast = 5 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 150 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 154 | .dot = { .min = 20000, .max = 400000 }, |
| 155 | .vco = { .min = 1400000, .max = 2800000 }, |
| 156 | .n = { .min = 1, .max = 6 }, |
| 157 | .m = { .min = 70, .max = 120 }, |
| 158 | .m1 = { .min = 10, .max = 22 }, |
| 159 | .m2 = { .min = 5, .max = 9 }, |
| 160 | .p = { .min = 7, .max = 98 }, |
| 161 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 162 | .p2 = { .dot_limit = 112000, |
| 163 | .p2_slow = 14, .p2_fast = 7 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 164 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 165 | }; |
| 166 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 167 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 168 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 169 | .dot = { .min = 25000, .max = 270000 }, |
| 170 | .vco = { .min = 1750000, .max = 3500000}, |
| 171 | .n = { .min = 1, .max = 4 }, |
| 172 | .m = { .min = 104, .max = 138 }, |
| 173 | .m1 = { .min = 17, .max = 23 }, |
| 174 | .m2 = { .min = 5, .max = 11 }, |
| 175 | .p = { .min = 10, .max = 30 }, |
| 176 | .p1 = { .min = 1, .max = 3}, |
| 177 | .p2 = { .dot_limit = 270000, |
| 178 | .p2_slow = 10, |
| 179 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 180 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 181 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 185 | .dot = { .min = 22000, .max = 400000 }, |
| 186 | .vco = { .min = 1750000, .max = 3500000}, |
| 187 | .n = { .min = 1, .max = 4 }, |
| 188 | .m = { .min = 104, .max = 138 }, |
| 189 | .m1 = { .min = 16, .max = 23 }, |
| 190 | .m2 = { .min = 5, .max = 11 }, |
| 191 | .p = { .min = 5, .max = 80 }, |
| 192 | .p1 = { .min = 1, .max = 8}, |
| 193 | .p2 = { .dot_limit = 165000, |
| 194 | .p2_slow = 10, .p2_fast = 5 }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 195 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 199 | .dot = { .min = 20000, .max = 115000 }, |
| 200 | .vco = { .min = 1750000, .max = 3500000 }, |
| 201 | .n = { .min = 1, .max = 3 }, |
| 202 | .m = { .min = 104, .max = 138 }, |
| 203 | .m1 = { .min = 17, .max = 23 }, |
| 204 | .m2 = { .min = 5, .max = 11 }, |
| 205 | .p = { .min = 28, .max = 112 }, |
| 206 | .p1 = { .min = 2, .max = 8 }, |
| 207 | .p2 = { .dot_limit = 0, |
| 208 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 209 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 210 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 214 | .dot = { .min = 80000, .max = 224000 }, |
| 215 | .vco = { .min = 1750000, .max = 3500000 }, |
| 216 | .n = { .min = 1, .max = 3 }, |
| 217 | .m = { .min = 104, .max = 138 }, |
| 218 | .m1 = { .min = 17, .max = 23 }, |
| 219 | .m2 = { .min = 5, .max = 11 }, |
| 220 | .p = { .min = 14, .max = 42 }, |
| 221 | .p1 = { .min = 2, .max = 6 }, |
| 222 | .p2 = { .dot_limit = 0, |
| 223 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 224 | }, |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 225 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | static const intel_limit_t intel_limits_g4x_display_port = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 229 | .dot = { .min = 161670, .max = 227000 }, |
| 230 | .vco = { .min = 1750000, .max = 3500000}, |
| 231 | .n = { .min = 1, .max = 2 }, |
| 232 | .m = { .min = 97, .max = 108 }, |
| 233 | .m1 = { .min = 0x10, .max = 0x12 }, |
| 234 | .m2 = { .min = 0x05, .max = 0x06 }, |
| 235 | .p = { .min = 10, .max = 20 }, |
| 236 | .p1 = { .min = 1, .max = 2}, |
| 237 | .p2 = { .dot_limit = 0, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 238 | .p2_slow = 10, .p2_fast = 10 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 239 | .find_pll = intel_find_pll_g4x_dp, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 240 | }; |
| 241 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 242 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 243 | .dot = { .min = 20000, .max = 400000}, |
| 244 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 245 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 246 | .n = { .min = 3, .max = 6 }, |
| 247 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 248 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 249 | .m1 = { .min = 0, .max = 0 }, |
| 250 | .m2 = { .min = 0, .max = 254 }, |
| 251 | .p = { .min = 5, .max = 80 }, |
| 252 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 253 | .p2 = { .dot_limit = 200000, |
| 254 | .p2_slow = 10, .p2_fast = 5 }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 255 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 256 | }; |
| 257 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 258 | static const intel_limit_t intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 259 | .dot = { .min = 20000, .max = 400000 }, |
| 260 | .vco = { .min = 1700000, .max = 3500000 }, |
| 261 | .n = { .min = 3, .max = 6 }, |
| 262 | .m = { .min = 2, .max = 256 }, |
| 263 | .m1 = { .min = 0, .max = 0 }, |
| 264 | .m2 = { .min = 0, .max = 254 }, |
| 265 | .p = { .min = 7, .max = 112 }, |
| 266 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 267 | .p2 = { .dot_limit = 112000, |
| 268 | .p2_slow = 14, .p2_fast = 14 }, |
Shaohua Li | 6115707 | 2009-04-03 15:24:43 +0800 | [diff] [blame] | 269 | .find_pll = intel_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 270 | }; |
| 271 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 272 | /* Ironlake / Sandybridge |
| 273 | * |
| 274 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 275 | * the range value for them is (actual_value - 2). |
| 276 | */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 277 | static const intel_limit_t intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 278 | .dot = { .min = 25000, .max = 350000 }, |
| 279 | .vco = { .min = 1760000, .max = 3510000 }, |
| 280 | .n = { .min = 1, .max = 5 }, |
| 281 | .m = { .min = 79, .max = 127 }, |
| 282 | .m1 = { .min = 12, .max = 22 }, |
| 283 | .m2 = { .min = 5, .max = 9 }, |
| 284 | .p = { .min = 5, .max = 80 }, |
| 285 | .p1 = { .min = 1, .max = 8 }, |
| 286 | .p2 = { .dot_limit = 225000, |
| 287 | .p2_slow = 10, .p2_fast = 5 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 288 | .find_pll = intel_g4x_find_best_PLL, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 289 | }; |
| 290 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 291 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 292 | .dot = { .min = 25000, .max = 350000 }, |
| 293 | .vco = { .min = 1760000, .max = 3510000 }, |
| 294 | .n = { .min = 1, .max = 3 }, |
| 295 | .m = { .min = 79, .max = 118 }, |
| 296 | .m1 = { .min = 12, .max = 22 }, |
| 297 | .m2 = { .min = 5, .max = 9 }, |
| 298 | .p = { .min = 28, .max = 112 }, |
| 299 | .p1 = { .min = 2, .max = 8 }, |
| 300 | .p2 = { .dot_limit = 225000, |
| 301 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 302 | .find_pll = intel_g4x_find_best_PLL, |
| 303 | }; |
| 304 | |
| 305 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 306 | .dot = { .min = 25000, .max = 350000 }, |
| 307 | .vco = { .min = 1760000, .max = 3510000 }, |
| 308 | .n = { .min = 1, .max = 3 }, |
| 309 | .m = { .min = 79, .max = 127 }, |
| 310 | .m1 = { .min = 12, .max = 22 }, |
| 311 | .m2 = { .min = 5, .max = 9 }, |
| 312 | .p = { .min = 14, .max = 56 }, |
| 313 | .p1 = { .min = 2, .max = 8 }, |
| 314 | .p2 = { .dot_limit = 225000, |
| 315 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 316 | .find_pll = intel_g4x_find_best_PLL, |
| 317 | }; |
| 318 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 319 | /* LVDS 100mhz refclk limits. */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 321 | .dot = { .min = 25000, .max = 350000 }, |
| 322 | .vco = { .min = 1760000, .max = 3510000 }, |
| 323 | .n = { .min = 1, .max = 2 }, |
| 324 | .m = { .min = 79, .max = 126 }, |
| 325 | .m1 = { .min = 12, .max = 22 }, |
| 326 | .m2 = { .min = 5, .max = 9 }, |
| 327 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 328 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 329 | .p2 = { .dot_limit = 225000, |
| 330 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 331 | .find_pll = intel_g4x_find_best_PLL, |
| 332 | }; |
| 333 | |
| 334 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 335 | .dot = { .min = 25000, .max = 350000 }, |
| 336 | .vco = { .min = 1760000, .max = 3510000 }, |
| 337 | .n = { .min = 1, .max = 3 }, |
| 338 | .m = { .min = 79, .max = 126 }, |
| 339 | .m1 = { .min = 12, .max = 22 }, |
| 340 | .m2 = { .min = 5, .max = 9 }, |
| 341 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 342 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 343 | .p2 = { .dot_limit = 225000, |
| 344 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 345 | .find_pll = intel_g4x_find_best_PLL, |
| 346 | }; |
| 347 | |
| 348 | static const intel_limit_t intel_limits_ironlake_display_port = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 349 | .dot = { .min = 25000, .max = 350000 }, |
| 350 | .vco = { .min = 1760000, .max = 3510000}, |
| 351 | .n = { .min = 1, .max = 2 }, |
| 352 | .m = { .min = 81, .max = 90 }, |
| 353 | .m1 = { .min = 12, .max = 22 }, |
| 354 | .m2 = { .min = 5, .max = 9 }, |
| 355 | .p = { .min = 10, .max = 20 }, |
| 356 | .p1 = { .min = 1, .max = 2}, |
| 357 | .p2 = { .dot_limit = 0, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 358 | .p2_slow = 10, .p2_fast = 10 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 359 | .find_pll = intel_find_pll_ironlake_dp, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 360 | }; |
| 361 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 362 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
| 363 | { |
| 364 | unsigned long flags; |
| 365 | u32 val = 0; |
| 366 | |
| 367 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); |
| 368 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
| 369 | DRM_ERROR("DPIO idle wait timed out\n"); |
| 370 | goto out_unlock; |
| 371 | } |
| 372 | |
| 373 | I915_WRITE(DPIO_REG, reg); |
| 374 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | |
| 375 | DPIO_BYTE); |
| 376 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
| 377 | DRM_ERROR("DPIO read wait timed out\n"); |
| 378 | goto out_unlock; |
| 379 | } |
| 380 | val = I915_READ(DPIO_DATA); |
| 381 | |
| 382 | out_unlock: |
| 383 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); |
| 384 | return val; |
| 385 | } |
| 386 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 387 | static void vlv_init_dpio(struct drm_device *dev) |
| 388 | { |
| 389 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 390 | |
| 391 | /* Reset the DPIO config */ |
| 392 | I915_WRITE(DPIO_CTL, 0); |
| 393 | POSTING_READ(DPIO_CTL); |
| 394 | I915_WRITE(DPIO_CTL, 1); |
| 395 | POSTING_READ(DPIO_CTL); |
| 396 | } |
| 397 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 398 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
| 399 | { |
| 400 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
| 401 | return 1; |
| 402 | } |
| 403 | |
| 404 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
| 405 | { |
| 406 | .callback = intel_dual_link_lvds_callback, |
| 407 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", |
| 408 | .matches = { |
| 409 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
| 410 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
| 411 | }, |
| 412 | }, |
| 413 | { } /* terminating entry */ |
| 414 | }; |
| 415 | |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 416 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
| 417 | unsigned int reg) |
| 418 | { |
| 419 | unsigned int val; |
| 420 | |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 421 | /* use the module option value if specified */ |
| 422 | if (i915_lvds_channel_mode > 0) |
| 423 | return i915_lvds_channel_mode == 2; |
| 424 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 425 | if (dmi_check_system(intel_dual_link_lvds)) |
| 426 | return true; |
| 427 | |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 428 | if (dev_priv->lvds_val) |
| 429 | val = dev_priv->lvds_val; |
| 430 | else { |
| 431 | /* BIOS should set the proper LVDS register value at boot, but |
| 432 | * in reality, it doesn't set the value when the lid is closed; |
| 433 | * we need to check "the value to be set" in VBT when LVDS |
| 434 | * register is uninitialized. |
| 435 | */ |
| 436 | val = I915_READ(reg); |
| 437 | if (!(val & ~LVDS_DETECTED)) |
| 438 | val = dev_priv->bios_lvds_val; |
| 439 | dev_priv->lvds_val = val; |
| 440 | } |
| 441 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
| 442 | } |
| 443 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 444 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
| 445 | int refclk) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 446 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 447 | struct drm_device *dev = crtc->dev; |
| 448 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 449 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 450 | |
| 451 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 452 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 453 | /* LVDS dual channel */ |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 454 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 455 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 456 | else |
| 457 | limit = &intel_limits_ironlake_dual_lvds; |
| 458 | } else { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 459 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 460 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 461 | else |
| 462 | limit = &intel_limits_ironlake_single_lvds; |
| 463 | } |
| 464 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 465 | HAS_eDP) |
| 466 | limit = &intel_limits_ironlake_display_port; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 467 | else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 468 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 469 | |
| 470 | return limit; |
| 471 | } |
| 472 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 473 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 474 | { |
| 475 | struct drm_device *dev = crtc->dev; |
| 476 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 477 | const intel_limit_t *limit; |
| 478 | |
| 479 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 480 | if (is_dual_link_lvds(dev_priv, LVDS)) |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 481 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 482 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 483 | else |
| 484 | /* LVDS with dual channel */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 485 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 486 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 487 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 488 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 489 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 490 | limit = &intel_limits_g4x_sdvo; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 491 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 492 | limit = &intel_limits_g4x_display_port; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 493 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 494 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 495 | |
| 496 | return limit; |
| 497 | } |
| 498 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 499 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 500 | { |
| 501 | struct drm_device *dev = crtc->dev; |
| 502 | const intel_limit_t *limit; |
| 503 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 504 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 505 | limit = intel_ironlake_limit(crtc, refclk); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 506 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 507 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 508 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 510 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 511 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 512 | limit = &intel_limits_pineview_sdvo; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 513 | } else if (!IS_GEN2(dev)) { |
| 514 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 515 | limit = &intel_limits_i9xx_lvds; |
| 516 | else |
| 517 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 518 | } else { |
| 519 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 520 | limit = &intel_limits_i8xx_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 521 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 522 | limit = &intel_limits_i8xx_dvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 523 | } |
| 524 | return limit; |
| 525 | } |
| 526 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 527 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 528 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 529 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 530 | clock->m = clock->m2 + 2; |
| 531 | clock->p = clock->p1 * clock->p2; |
| 532 | clock->vco = refclk * clock->m / clock->n; |
| 533 | clock->dot = clock->vco / clock->p; |
| 534 | } |
| 535 | |
| 536 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
| 537 | { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 538 | if (IS_PINEVIEW(dev)) { |
| 539 | pineview_clock(refclk, clock); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 540 | return; |
| 541 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 542 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 543 | clock->p = clock->p1 * clock->p2; |
| 544 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 545 | clock->dot = clock->vco / clock->p; |
| 546 | } |
| 547 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 548 | /** |
| 549 | * Returns whether any output on the specified pipe is of the specified type |
| 550 | */ |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 551 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 552 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 553 | struct drm_device *dev = crtc->dev; |
| 554 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 555 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 556 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 557 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
| 558 | if (encoder->base.crtc == crtc && encoder->type == type) |
| 559 | return true; |
| 560 | |
| 561 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 562 | } |
| 563 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 564 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 565 | /** |
| 566 | * Returns whether the given set of divisors are valid for a given refclk with |
| 567 | * the given connectors. |
| 568 | */ |
| 569 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 570 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 571 | const intel_limit_t *limit, |
| 572 | const intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 573 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 575 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 576 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 577 | INTELPllInvalid("p out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 578 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 579 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 580 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 581 | INTELPllInvalid("m1 out of range\n"); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 582 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 583 | INTELPllInvalid("m1 <= m2\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 584 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 585 | INTELPllInvalid("m out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 586 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 587 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 588 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 589 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 591 | * connector, etc., rather than just a single range. |
| 592 | */ |
| 593 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 594 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 595 | |
| 596 | return true; |
| 597 | } |
| 598 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 599 | static bool |
| 600 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 601 | int target, int refclk, intel_clock_t *match_clock, |
| 602 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 603 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 604 | { |
| 605 | struct drm_device *dev = crtc->dev; |
| 606 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 607 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 608 | int err = target; |
| 609 | |
Bruno Prémont | bc5e571 | 2009-08-08 13:01:17 +0200 | [diff] [blame] | 610 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Florian Mickler | 832cc28 | 2009-07-13 18:40:32 +0800 | [diff] [blame] | 611 | (I915_READ(LVDS)) != 0) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 612 | /* |
| 613 | * For LVDS, if the panel is on, just rely on its current |
| 614 | * settings for dual-channel. We haven't figured out how to |
| 615 | * reliably set up different single/dual channel state, if we |
| 616 | * even can. |
| 617 | */ |
Takashi Iwai | b035438 | 2012-03-20 13:07:05 +0100 | [diff] [blame] | 618 | if (is_dual_link_lvds(dev_priv, LVDS)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 619 | clock.p2 = limit->p2.p2_fast; |
| 620 | else |
| 621 | clock.p2 = limit->p2.p2_slow; |
| 622 | } else { |
| 623 | if (target < limit->p2.dot_limit) |
| 624 | clock.p2 = limit->p2.p2_slow; |
| 625 | else |
| 626 | clock.p2 = limit->p2.p2_fast; |
| 627 | } |
| 628 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 629 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 630 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 631 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 632 | clock.m1++) { |
| 633 | for (clock.m2 = limit->m2.min; |
| 634 | clock.m2 <= limit->m2.max; clock.m2++) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 635 | /* m1 is always 0 in Pineview */ |
| 636 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 637 | break; |
| 638 | for (clock.n = limit->n.min; |
| 639 | clock.n <= limit->n.max; clock.n++) { |
| 640 | for (clock.p1 = limit->p1.min; |
| 641 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 642 | int this_err; |
| 643 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 644 | intel_clock(dev, refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 645 | if (!intel_PLL_is_valid(dev, limit, |
| 646 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 647 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 648 | if (match_clock && |
| 649 | clock.p != match_clock->p) |
| 650 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 651 | |
| 652 | this_err = abs(clock.dot - target); |
| 653 | if (this_err < err) { |
| 654 | *best_clock = clock; |
| 655 | err = this_err; |
| 656 | } |
| 657 | } |
| 658 | } |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | return (err != target); |
| 663 | } |
| 664 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 665 | static bool |
| 666 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 667 | int target, int refclk, intel_clock_t *match_clock, |
| 668 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 669 | { |
| 670 | struct drm_device *dev = crtc->dev; |
| 671 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 672 | intel_clock_t clock; |
| 673 | int max_n; |
| 674 | bool found; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 675 | /* approximately equals target * 0.00585 */ |
| 676 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 677 | found = false; |
| 678 | |
| 679 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 680 | int lvds_reg; |
| 681 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 682 | if (HAS_PCH_SPLIT(dev)) |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 683 | lvds_reg = PCH_LVDS; |
| 684 | else |
| 685 | lvds_reg = LVDS; |
| 686 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 687 | LVDS_CLKB_POWER_UP) |
| 688 | clock.p2 = limit->p2.p2_fast; |
| 689 | else |
| 690 | clock.p2 = limit->p2.p2_slow; |
| 691 | } else { |
| 692 | if (target < limit->p2.dot_limit) |
| 693 | clock.p2 = limit->p2.p2_slow; |
| 694 | else |
| 695 | clock.p2 = limit->p2.p2_fast; |
| 696 | } |
| 697 | |
| 698 | memset(best_clock, 0, sizeof(*best_clock)); |
| 699 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 700 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 701 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 702 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 703 | for (clock.m1 = limit->m1.max; |
| 704 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 705 | for (clock.m2 = limit->m2.max; |
| 706 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 707 | for (clock.p1 = limit->p1.max; |
| 708 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 709 | int this_err; |
| 710 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 711 | intel_clock(dev, refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 712 | if (!intel_PLL_is_valid(dev, limit, |
| 713 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 714 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 715 | if (match_clock && |
| 716 | clock.p != match_clock->p) |
| 717 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 718 | |
| 719 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 720 | if (this_err < err_most) { |
| 721 | *best_clock = clock; |
| 722 | err_most = this_err; |
| 723 | max_n = clock.n; |
| 724 | found = true; |
| 725 | } |
| 726 | } |
| 727 | } |
| 728 | } |
| 729 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 730 | return found; |
| 731 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 732 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 733 | static bool |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 734 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 735 | int target, int refclk, intel_clock_t *match_clock, |
| 736 | intel_clock_t *best_clock) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 737 | { |
| 738 | struct drm_device *dev = crtc->dev; |
| 739 | intel_clock_t clock; |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 740 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 741 | if (target < 200000) { |
| 742 | clock.n = 1; |
| 743 | clock.p1 = 2; |
| 744 | clock.p2 = 10; |
| 745 | clock.m1 = 12; |
| 746 | clock.m2 = 9; |
| 747 | } else { |
| 748 | clock.n = 2; |
| 749 | clock.p1 = 1; |
| 750 | clock.p2 = 10; |
| 751 | clock.m1 = 14; |
| 752 | clock.m2 = 8; |
| 753 | } |
| 754 | intel_clock(dev, refclk, &clock); |
| 755 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 756 | return true; |
| 757 | } |
| 758 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 759 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
| 760 | static bool |
| 761 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 762 | int target, int refclk, intel_clock_t *match_clock, |
| 763 | intel_clock_t *best_clock) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 764 | { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 765 | intel_clock_t clock; |
| 766 | if (target < 200000) { |
| 767 | clock.p1 = 2; |
| 768 | clock.p2 = 10; |
| 769 | clock.n = 2; |
| 770 | clock.m1 = 23; |
| 771 | clock.m2 = 8; |
| 772 | } else { |
| 773 | clock.p1 = 1; |
| 774 | clock.p2 = 10; |
| 775 | clock.n = 1; |
| 776 | clock.m1 = 14; |
| 777 | clock.m2 = 2; |
| 778 | } |
| 779 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
| 780 | clock.p = (clock.p1 * clock.p2); |
| 781 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; |
| 782 | clock.vco = 0; |
| 783 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
| 784 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 785 | } |
| 786 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 787 | /** |
| 788 | * intel_wait_for_vblank - wait for vblank on a given pipe |
| 789 | * @dev: drm device |
| 790 | * @pipe: pipe to wait for |
| 791 | * |
| 792 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
| 793 | * mode setting code. |
| 794 | */ |
| 795 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 796 | { |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 797 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 798 | int pipestat_reg = PIPESTAT(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 799 | |
Chris Wilson | 300387c | 2010-09-05 20:25:43 +0100 | [diff] [blame] | 800 | /* Clear existing vblank status. Note this will clear any other |
| 801 | * sticky status fields as well. |
| 802 | * |
| 803 | * This races with i915_driver_irq_handler() with the result |
| 804 | * that either function could miss a vblank event. Here it is not |
| 805 | * fatal, as we will either wait upon the next vblank interrupt or |
| 806 | * timeout. Generally speaking intel_wait_for_vblank() is only |
| 807 | * called during modeset at which time the GPU should be idle and |
| 808 | * should *not* be performing page flips and thus not waiting on |
| 809 | * vblanks... |
| 810 | * Currently, the result of us stealing a vblank from the irq |
| 811 | * handler is that a single frame will be skipped during swapbuffers. |
| 812 | */ |
| 813 | I915_WRITE(pipestat_reg, |
| 814 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
| 815 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 816 | /* Wait for vblank interrupt bit to set */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 817 | if (wait_for(I915_READ(pipestat_reg) & |
| 818 | PIPE_VBLANK_INTERRUPT_STATUS, |
| 819 | 50)) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 820 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
| 821 | } |
| 822 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 823 | /* |
| 824 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 825 | * @dev: drm device |
| 826 | * @pipe: pipe to wait for |
| 827 | * |
| 828 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 829 | * spinning on the vblank interrupt status bit, since we won't actually |
| 830 | * see an interrupt when the pipe is disabled. |
| 831 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 832 | * On Gen4 and above: |
| 833 | * wait for the pipe register state bit to turn off |
| 834 | * |
| 835 | * Otherwise: |
| 836 | * wait for the display line value to settle (it usually |
| 837 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 838 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 839 | */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 840 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 841 | { |
| 842 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 843 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 844 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 845 | int reg = PIPECONF(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 846 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 847 | /* Wait for the Pipe State to go off */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 848 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 849 | 100)) |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 850 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
| 851 | } else { |
| 852 | u32 last_line; |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 853 | int reg = PIPEDSL(pipe); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 854 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
| 855 | |
| 856 | /* Wait for the display line to settle */ |
| 857 | do { |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 858 | last_line = I915_READ(reg) & DSL_LINEMASK; |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 859 | mdelay(5); |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 860 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 861 | time_after(timeout, jiffies)); |
| 862 | if (time_after(jiffies, timeout)) |
| 863 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
| 864 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 865 | } |
| 866 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 867 | static const char *state_string(bool enabled) |
| 868 | { |
| 869 | return enabled ? "on" : "off"; |
| 870 | } |
| 871 | |
| 872 | /* Only for pre-ILK configs */ |
| 873 | static void assert_pll(struct drm_i915_private *dev_priv, |
| 874 | enum pipe pipe, bool state) |
| 875 | { |
| 876 | int reg; |
| 877 | u32 val; |
| 878 | bool cur_state; |
| 879 | |
| 880 | reg = DPLL(pipe); |
| 881 | val = I915_READ(reg); |
| 882 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 883 | WARN(cur_state != state, |
| 884 | "PLL state assertion failure (expected %s, current %s)\n", |
| 885 | state_string(state), state_string(cur_state)); |
| 886 | } |
| 887 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 888 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) |
| 889 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 890 | /* For ILK+ */ |
| 891 | static void assert_pch_pll(struct drm_i915_private *dev_priv, |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 892 | struct intel_crtc *intel_crtc, bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 893 | { |
| 894 | int reg; |
| 895 | u32 val; |
| 896 | bool cur_state; |
| 897 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 898 | if (!intel_crtc->pch_pll) { |
| 899 | WARN(1, "asserting PCH PLL enabled with no PLL\n"); |
| 900 | return; |
| 901 | } |
| 902 | |
Jesse Barnes | d3ccbe8 | 2011-10-12 09:27:42 -0700 | [diff] [blame] | 903 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 904 | u32 pch_dpll; |
| 905 | |
| 906 | pch_dpll = I915_READ(PCH_DPLL_SEL); |
| 907 | |
| 908 | /* Make sure the selected PLL is enabled to the transcoder */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 909 | WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8), |
| 910 | "transcoder %d PLL not enabled\n", intel_crtc->pipe); |
Jesse Barnes | d3ccbe8 | 2011-10-12 09:27:42 -0700 | [diff] [blame] | 911 | } |
| 912 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 913 | reg = intel_crtc->pch_pll->pll_reg; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 914 | val = I915_READ(reg); |
| 915 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 916 | WARN(cur_state != state, |
| 917 | "PCH PLL state assertion failure (expected %s, current %s)\n", |
| 918 | state_string(state), state_string(cur_state)); |
| 919 | } |
| 920 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) |
| 921 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) |
| 922 | |
| 923 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 924 | enum pipe pipe, bool state) |
| 925 | { |
| 926 | int reg; |
| 927 | u32 val; |
| 928 | bool cur_state; |
| 929 | |
| 930 | reg = FDI_TX_CTL(pipe); |
| 931 | val = I915_READ(reg); |
| 932 | cur_state = !!(val & FDI_TX_ENABLE); |
| 933 | WARN(cur_state != state, |
| 934 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 935 | state_string(state), state_string(cur_state)); |
| 936 | } |
| 937 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 938 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 939 | |
| 940 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 941 | enum pipe pipe, bool state) |
| 942 | { |
| 943 | int reg; |
| 944 | u32 val; |
| 945 | bool cur_state; |
| 946 | |
| 947 | reg = FDI_RX_CTL(pipe); |
| 948 | val = I915_READ(reg); |
| 949 | cur_state = !!(val & FDI_RX_ENABLE); |
| 950 | WARN(cur_state != state, |
| 951 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 952 | state_string(state), state_string(cur_state)); |
| 953 | } |
| 954 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 955 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 956 | |
| 957 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 958 | enum pipe pipe) |
| 959 | { |
| 960 | int reg; |
| 961 | u32 val; |
| 962 | |
| 963 | /* ILK FDI PLL is always enabled */ |
| 964 | if (dev_priv->info->gen == 5) |
| 965 | return; |
| 966 | |
| 967 | reg = FDI_TX_CTL(pipe); |
| 968 | val = I915_READ(reg); |
| 969 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
| 970 | } |
| 971 | |
| 972 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, |
| 973 | enum pipe pipe) |
| 974 | { |
| 975 | int reg; |
| 976 | u32 val; |
| 977 | |
| 978 | reg = FDI_RX_CTL(pipe); |
| 979 | val = I915_READ(reg); |
| 980 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); |
| 981 | } |
| 982 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 983 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 984 | enum pipe pipe) |
| 985 | { |
| 986 | int pp_reg, lvds_reg; |
| 987 | u32 val; |
| 988 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 989 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 990 | |
| 991 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 992 | pp_reg = PCH_PP_CONTROL; |
| 993 | lvds_reg = PCH_LVDS; |
| 994 | } else { |
| 995 | pp_reg = PP_CONTROL; |
| 996 | lvds_reg = LVDS; |
| 997 | } |
| 998 | |
| 999 | val = I915_READ(pp_reg); |
| 1000 | if (!(val & PANEL_POWER_ON) || |
| 1001 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
| 1002 | locked = false; |
| 1003 | |
| 1004 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
| 1005 | panel_pipe = PIPE_B; |
| 1006 | |
| 1007 | WARN(panel_pipe == pipe && locked, |
| 1008 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1009 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1010 | } |
| 1011 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1012 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1013 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1014 | { |
| 1015 | int reg; |
| 1016 | u32 val; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1017 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1018 | |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 1019 | /* if we need the pipe A quirk it must be always on */ |
| 1020 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 1021 | state = true; |
| 1022 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1023 | reg = PIPECONF(pipe); |
| 1024 | val = I915_READ(reg); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1025 | cur_state = !!(val & PIPECONF_ENABLE); |
| 1026 | WARN(cur_state != state, |
| 1027 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1028 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1029 | } |
| 1030 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1031 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1032 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1033 | { |
| 1034 | int reg; |
| 1035 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1036 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1037 | |
| 1038 | reg = DSPCNTR(plane); |
| 1039 | val = I915_READ(reg); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1040 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
| 1041 | WARN(cur_state != state, |
| 1042 | "plane %c assertion failure (expected %s, current %s)\n", |
| 1043 | plane_name(plane), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1044 | } |
| 1045 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1046 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1047 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1048 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1049 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1050 | enum pipe pipe) |
| 1051 | { |
| 1052 | int reg, i; |
| 1053 | u32 val; |
| 1054 | int cur_pipe; |
| 1055 | |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1056 | /* Planes are fixed to pipes on ILK+ */ |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1057 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 1058 | reg = DSPCNTR(pipe); |
| 1059 | val = I915_READ(reg); |
| 1060 | WARN((val & DISPLAY_PLANE_ENABLE), |
| 1061 | "plane %c assertion failure, should be disabled but not\n", |
| 1062 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1063 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1064 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1065 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1066 | /* Need to check both planes against the pipe */ |
| 1067 | for (i = 0; i < 2; i++) { |
| 1068 | reg = DSPCNTR(i); |
| 1069 | val = I915_READ(reg); |
| 1070 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
| 1071 | DISPPLANE_SEL_PIPE_SHIFT; |
| 1072 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1073 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1074 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1075 | } |
| 1076 | } |
| 1077 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1078 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
| 1079 | { |
| 1080 | u32 val; |
| 1081 | bool enabled; |
| 1082 | |
| 1083 | val = I915_READ(PCH_DREF_CONTROL); |
| 1084 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1085 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 1086 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 1087 | } |
| 1088 | |
| 1089 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1090 | enum pipe pipe) |
| 1091 | { |
| 1092 | int reg; |
| 1093 | u32 val; |
| 1094 | bool enabled; |
| 1095 | |
| 1096 | reg = TRANSCONF(pipe); |
| 1097 | val = I915_READ(reg); |
| 1098 | enabled = !!(val & TRANS_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1099 | WARN(enabled, |
| 1100 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1101 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1102 | } |
| 1103 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1104 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1105 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1106 | { |
| 1107 | if ((val & DP_PORT_EN) == 0) |
| 1108 | return false; |
| 1109 | |
| 1110 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1111 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
| 1112 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
| 1113 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1114 | return false; |
| 1115 | } else { |
| 1116 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1117 | return false; |
| 1118 | } |
| 1119 | return true; |
| 1120 | } |
| 1121 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1122 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1123 | enum pipe pipe, u32 val) |
| 1124 | { |
| 1125 | if ((val & PORT_ENABLE) == 0) |
| 1126 | return false; |
| 1127 | |
| 1128 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1129 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1130 | return false; |
| 1131 | } else { |
| 1132 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) |
| 1133 | return false; |
| 1134 | } |
| 1135 | return true; |
| 1136 | } |
| 1137 | |
| 1138 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1139 | enum pipe pipe, u32 val) |
| 1140 | { |
| 1141 | if ((val & LVDS_PORT_EN) == 0) |
| 1142 | return false; |
| 1143 | |
| 1144 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1145 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1146 | return false; |
| 1147 | } else { |
| 1148 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1149 | return false; |
| 1150 | } |
| 1151 | return true; |
| 1152 | } |
| 1153 | |
| 1154 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1155 | enum pipe pipe, u32 val) |
| 1156 | { |
| 1157 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1158 | return false; |
| 1159 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1160 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1161 | return false; |
| 1162 | } else { |
| 1163 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1164 | return false; |
| 1165 | } |
| 1166 | return true; |
| 1167 | } |
| 1168 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1169 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1170 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1171 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1172 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1173 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1174 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1175 | reg, pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1176 | } |
| 1177 | |
| 1178 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
| 1179 | enum pipe pipe, int reg) |
| 1180 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1181 | u32 val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1182 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1183 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1184 | reg, pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1188 | enum pipe pipe) |
| 1189 | { |
| 1190 | int reg; |
| 1191 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1192 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1193 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1194 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1195 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1196 | |
| 1197 | reg = PCH_ADPA; |
| 1198 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1199 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1200 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1201 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1202 | |
| 1203 | reg = PCH_LVDS; |
| 1204 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1205 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1206 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1207 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1208 | |
| 1209 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); |
| 1210 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); |
| 1211 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); |
| 1212 | } |
| 1213 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1214 | /** |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1215 | * intel_enable_pll - enable a PLL |
| 1216 | * @dev_priv: i915 private structure |
| 1217 | * @pipe: pipe PLL to enable |
| 1218 | * |
| 1219 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to |
| 1220 | * make sure the PLL reg is writable first though, since the panel write |
| 1221 | * protect mechanism may be enabled. |
| 1222 | * |
| 1223 | * Note! This is for pre-ILK only. |
| 1224 | */ |
| 1225 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1226 | { |
| 1227 | int reg; |
| 1228 | u32 val; |
| 1229 | |
| 1230 | /* No really, not for ILK+ */ |
| 1231 | BUG_ON(dev_priv->info->gen >= 5); |
| 1232 | |
| 1233 | /* PLL is protected by panel, make sure we can write it */ |
| 1234 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
| 1235 | assert_panel_unlocked(dev_priv, pipe); |
| 1236 | |
| 1237 | reg = DPLL(pipe); |
| 1238 | val = I915_READ(reg); |
| 1239 | val |= DPLL_VCO_ENABLE; |
| 1240 | |
| 1241 | /* We do this three times for luck */ |
| 1242 | I915_WRITE(reg, val); |
| 1243 | POSTING_READ(reg); |
| 1244 | udelay(150); /* wait for warmup */ |
| 1245 | I915_WRITE(reg, val); |
| 1246 | POSTING_READ(reg); |
| 1247 | udelay(150); /* wait for warmup */ |
| 1248 | I915_WRITE(reg, val); |
| 1249 | POSTING_READ(reg); |
| 1250 | udelay(150); /* wait for warmup */ |
| 1251 | } |
| 1252 | |
| 1253 | /** |
| 1254 | * intel_disable_pll - disable a PLL |
| 1255 | * @dev_priv: i915 private structure |
| 1256 | * @pipe: pipe PLL to disable |
| 1257 | * |
| 1258 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1259 | * |
| 1260 | * Note! This is for pre-ILK only. |
| 1261 | */ |
| 1262 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1263 | { |
| 1264 | int reg; |
| 1265 | u32 val; |
| 1266 | |
| 1267 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1268 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1269 | return; |
| 1270 | |
| 1271 | /* Make sure the pipe isn't still relying on us */ |
| 1272 | assert_pipe_disabled(dev_priv, pipe); |
| 1273 | |
| 1274 | reg = DPLL(pipe); |
| 1275 | val = I915_READ(reg); |
| 1276 | val &= ~DPLL_VCO_ENABLE; |
| 1277 | I915_WRITE(reg, val); |
| 1278 | POSTING_READ(reg); |
| 1279 | } |
| 1280 | |
| 1281 | /** |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1282 | * intel_enable_pch_pll - enable PCH PLL |
| 1283 | * @dev_priv: i915 private structure |
| 1284 | * @pipe: pipe PLL to enable |
| 1285 | * |
| 1286 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1287 | * drives the transcoder clock. |
| 1288 | */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1289 | static void intel_enable_pch_pll(struct intel_crtc *intel_crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1290 | { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1291 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
| 1292 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1293 | int reg; |
| 1294 | u32 val; |
| 1295 | |
| 1296 | /* PCH only available on ILK+ */ |
| 1297 | BUG_ON(dev_priv->info->gen < 5); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1298 | BUG_ON(pll == NULL); |
| 1299 | BUG_ON(pll->refcount == 0); |
| 1300 | |
| 1301 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", |
| 1302 | pll->pll_reg, pll->active, pll->on, |
| 1303 | intel_crtc->base.base.id); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1304 | |
| 1305 | /* PCH refclock must be enabled first */ |
| 1306 | assert_pch_refclk_enabled(dev_priv); |
| 1307 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1308 | if (pll->active++ && pll->on) { |
| 1309 | assert_pch_pll_enabled(dev_priv, intel_crtc); |
| 1310 | return; |
| 1311 | } |
| 1312 | |
| 1313 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); |
| 1314 | |
| 1315 | reg = pll->pll_reg; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1316 | val = I915_READ(reg); |
| 1317 | val |= DPLL_VCO_ENABLE; |
| 1318 | I915_WRITE(reg, val); |
| 1319 | POSTING_READ(reg); |
| 1320 | udelay(200); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1321 | |
| 1322 | pll->on = true; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1323 | } |
| 1324 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1325 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1326 | { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1327 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
| 1328 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1329 | int reg; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1330 | u32 val; |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1331 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1332 | /* PCH only available on ILK+ */ |
| 1333 | BUG_ON(dev_priv->info->gen < 5); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1334 | if (pll == NULL) |
| 1335 | return; |
| 1336 | |
| 1337 | BUG_ON(pll->refcount == 0); |
| 1338 | |
| 1339 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
| 1340 | pll->pll_reg, pll->active, pll->on, |
| 1341 | intel_crtc->base.base.id); |
| 1342 | |
| 1343 | BUG_ON(pll->active == 0); |
| 1344 | if (--pll->active) { |
| 1345 | assert_pch_pll_enabled(dev_priv, intel_crtc); |
| 1346 | return; |
| 1347 | } |
| 1348 | |
| 1349 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1350 | |
| 1351 | /* Make sure transcoder isn't still depending on us */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1352 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1353 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1354 | reg = pll->pll_reg; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1355 | val = I915_READ(reg); |
| 1356 | val &= ~DPLL_VCO_ENABLE; |
| 1357 | I915_WRITE(reg, val); |
| 1358 | POSTING_READ(reg); |
| 1359 | udelay(200); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1360 | |
| 1361 | pll->on = false; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1362 | } |
| 1363 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1364 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
| 1365 | enum pipe pipe) |
| 1366 | { |
| 1367 | int reg; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1368 | u32 val, pipeconf_val; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1369 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1370 | |
| 1371 | /* PCH only available on ILK+ */ |
| 1372 | BUG_ON(dev_priv->info->gen < 5); |
| 1373 | |
| 1374 | /* Make sure PCH DPLL is enabled */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1375 | assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1376 | |
| 1377 | /* FDI must be feeding us bits for PCH ports */ |
| 1378 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1379 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1380 | |
| 1381 | reg = TRANSCONF(pipe); |
| 1382 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1383 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1384 | |
| 1385 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1386 | /* |
| 1387 | * make the BPC in transcoder be consistent with |
| 1388 | * that in pipeconf reg. |
| 1389 | */ |
| 1390 | val &= ~PIPE_BPC_MASK; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1391 | val |= pipeconf_val & PIPE_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1392 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1393 | |
| 1394 | val &= ~TRANS_INTERLACE_MASK; |
| 1395 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1396 | if (HAS_PCH_IBX(dev_priv->dev) && |
| 1397 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
| 1398 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 1399 | else |
| 1400 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1401 | else |
| 1402 | val |= TRANS_PROGRESSIVE; |
| 1403 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1404 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 1405 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
| 1406 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
| 1407 | } |
| 1408 | |
| 1409 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, |
| 1410 | enum pipe pipe) |
| 1411 | { |
| 1412 | int reg; |
| 1413 | u32 val; |
| 1414 | |
| 1415 | /* FDI relies on the transcoder */ |
| 1416 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 1417 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 1418 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1419 | /* Ports must be off as well */ |
| 1420 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1421 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1422 | reg = TRANSCONF(pipe); |
| 1423 | val = I915_READ(reg); |
| 1424 | val &= ~TRANS_ENABLE; |
| 1425 | I915_WRITE(reg, val); |
| 1426 | /* wait for PCH transcoder off, transcoder state */ |
| 1427 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Jesse Barnes | 4c9c18c | 2011-10-13 09:46:32 -0700 | [diff] [blame] | 1428 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1429 | } |
| 1430 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1431 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1432 | * intel_enable_pipe - enable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1433 | * @dev_priv: i915 private structure |
| 1434 | * @pipe: pipe to enable |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1435 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1436 | * |
| 1437 | * Enable @pipe, making sure that various hardware specific requirements |
| 1438 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
| 1439 | * |
| 1440 | * @pipe should be %PIPE_A or %PIPE_B. |
| 1441 | * |
| 1442 | * Will wait until the pipe is actually running (i.e. first vblank) before |
| 1443 | * returning. |
| 1444 | */ |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1445 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 1446 | bool pch_port) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1447 | { |
| 1448 | int reg; |
| 1449 | u32 val; |
| 1450 | |
| 1451 | /* |
| 1452 | * A pipe without a PLL won't actually be able to drive bits from |
| 1453 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 1454 | * need the check. |
| 1455 | */ |
| 1456 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
| 1457 | assert_pll_enabled(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1458 | else { |
| 1459 | if (pch_port) { |
| 1460 | /* if driving the PCH, we need FDI enabled */ |
| 1461 | assert_fdi_rx_pll_enabled(dev_priv, pipe); |
| 1462 | assert_fdi_tx_pll_enabled(dev_priv, pipe); |
| 1463 | } |
| 1464 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1465 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1466 | |
| 1467 | reg = PIPECONF(pipe); |
| 1468 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1469 | if (val & PIPECONF_ENABLE) |
| 1470 | return; |
| 1471 | |
| 1472 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1473 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1474 | } |
| 1475 | |
| 1476 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1477 | * intel_disable_pipe - disable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1478 | * @dev_priv: i915 private structure |
| 1479 | * @pipe: pipe to disable |
| 1480 | * |
| 1481 | * Disable @pipe, making sure that various hardware specific requirements |
| 1482 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
| 1483 | * |
| 1484 | * @pipe should be %PIPE_A or %PIPE_B. |
| 1485 | * |
| 1486 | * Will wait until the pipe has shut down before returning. |
| 1487 | */ |
| 1488 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
| 1489 | enum pipe pipe) |
| 1490 | { |
| 1491 | int reg; |
| 1492 | u32 val; |
| 1493 | |
| 1494 | /* |
| 1495 | * Make sure planes won't keep trying to pump pixels to us, |
| 1496 | * or we might hang the display. |
| 1497 | */ |
| 1498 | assert_planes_disabled(dev_priv, pipe); |
| 1499 | |
| 1500 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1501 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1502 | return; |
| 1503 | |
| 1504 | reg = PIPECONF(pipe); |
| 1505 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1506 | if ((val & PIPECONF_ENABLE) == 0) |
| 1507 | return; |
| 1508 | |
| 1509 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1510 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
| 1511 | } |
| 1512 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1513 | /* |
| 1514 | * Plane regs are double buffered, going from enabled->disabled needs a |
| 1515 | * trigger in order to latch. The display address reg provides this. |
| 1516 | */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 1517 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1518 | enum plane plane) |
| 1519 | { |
| 1520 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); |
| 1521 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); |
| 1522 | } |
| 1523 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1524 | /** |
| 1525 | * intel_enable_plane - enable a display plane on a given pipe |
| 1526 | * @dev_priv: i915 private structure |
| 1527 | * @plane: plane to enable |
| 1528 | * @pipe: pipe being fed |
| 1529 | * |
| 1530 | * Enable @plane on @pipe, making sure that @pipe is running first. |
| 1531 | */ |
| 1532 | static void intel_enable_plane(struct drm_i915_private *dev_priv, |
| 1533 | enum plane plane, enum pipe pipe) |
| 1534 | { |
| 1535 | int reg; |
| 1536 | u32 val; |
| 1537 | |
| 1538 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
| 1539 | assert_pipe_enabled(dev_priv, pipe); |
| 1540 | |
| 1541 | reg = DSPCNTR(plane); |
| 1542 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1543 | if (val & DISPLAY_PLANE_ENABLE) |
| 1544 | return; |
| 1545 | |
| 1546 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1547 | intel_flush_display_plane(dev_priv, plane); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1548 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1549 | } |
| 1550 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1551 | /** |
| 1552 | * intel_disable_plane - disable a display plane |
| 1553 | * @dev_priv: i915 private structure |
| 1554 | * @plane: plane to disable |
| 1555 | * @pipe: pipe consuming the data |
| 1556 | * |
| 1557 | * Disable @plane; should be an independent operation. |
| 1558 | */ |
| 1559 | static void intel_disable_plane(struct drm_i915_private *dev_priv, |
| 1560 | enum plane plane, enum pipe pipe) |
| 1561 | { |
| 1562 | int reg; |
| 1563 | u32 val; |
| 1564 | |
| 1565 | reg = DSPCNTR(plane); |
| 1566 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1567 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
| 1568 | return; |
| 1569 | |
| 1570 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1571 | intel_flush_display_plane(dev_priv, plane); |
| 1572 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1573 | } |
| 1574 | |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1575 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1576 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1577 | { |
| 1578 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1579 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1580 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1581 | I915_WRITE(reg, val & ~DP_PORT_EN); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1582 | } |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1583 | } |
| 1584 | |
| 1585 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, |
| 1586 | enum pipe pipe, int reg) |
| 1587 | { |
| 1588 | u32 val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1589 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1590 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
| 1591 | reg, pipe); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1592 | I915_WRITE(reg, val & ~PORT_ENABLE); |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1593 | } |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1594 | } |
| 1595 | |
| 1596 | /* Disable any ports connected to this transcoder */ |
| 1597 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, |
| 1598 | enum pipe pipe) |
| 1599 | { |
| 1600 | u32 reg, val; |
| 1601 | |
| 1602 | val = I915_READ(PCH_PP_CONTROL); |
| 1603 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); |
| 1604 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1605 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1606 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1607 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1608 | |
| 1609 | reg = PCH_ADPA; |
| 1610 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1611 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1612 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
| 1613 | |
| 1614 | reg = PCH_LVDS; |
| 1615 | val = I915_READ(reg); |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1616 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
| 1617 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1618 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
| 1619 | POSTING_READ(reg); |
| 1620 | udelay(100); |
| 1621 | } |
| 1622 | |
| 1623 | disable_pch_hdmi(dev_priv, pipe, HDMIB); |
| 1624 | disable_pch_hdmi(dev_priv, pipe, HDMIC); |
| 1625 | disable_pch_hdmi(dev_priv, pipe, HDMID); |
| 1626 | } |
| 1627 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 1628 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1629 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1630 | struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1631 | struct intel_ring_buffer *pipelined) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1632 | { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1633 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1634 | u32 alignment; |
| 1635 | int ret; |
| 1636 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1637 | switch (obj->tiling_mode) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1638 | case I915_TILING_NONE: |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1639 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1640 | alignment = 128 * 1024; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1641 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1642 | alignment = 4 * 1024; |
| 1643 | else |
| 1644 | alignment = 64 * 1024; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1645 | break; |
| 1646 | case I915_TILING_X: |
| 1647 | /* pin() will align the object as required by fence */ |
| 1648 | alignment = 0; |
| 1649 | break; |
| 1650 | case I915_TILING_Y: |
| 1651 | /* FIXME: Is this true? */ |
| 1652 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); |
| 1653 | return -EINVAL; |
| 1654 | default: |
| 1655 | BUG(); |
| 1656 | } |
| 1657 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1658 | dev_priv->mm.interruptible = false; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 1659 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1660 | if (ret) |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1661 | goto err_interruptible; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1662 | |
| 1663 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 1664 | * fence, whereas 965+ only requires a fence if using |
| 1665 | * framebuffer compression. For simplicity, we always install |
| 1666 | * a fence as the cost is not that onerous. |
| 1667 | */ |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1668 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 1669 | if (ret) |
| 1670 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1671 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 1672 | i915_gem_object_pin_fence(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1673 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1674 | dev_priv->mm.interruptible = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1675 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1676 | |
| 1677 | err_unpin: |
| 1678 | i915_gem_object_unpin(obj); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1679 | err_interruptible: |
| 1680 | dev_priv->mm.interruptible = true; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1681 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1682 | } |
| 1683 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1684 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
| 1685 | { |
| 1686 | i915_gem_object_unpin_fence(obj); |
| 1687 | i915_gem_object_unpin(obj); |
| 1688 | } |
| 1689 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1690 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 1691 | int x, int y) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1692 | { |
| 1693 | struct drm_device *dev = crtc->dev; |
| 1694 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1696 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1697 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1698 | int plane = intel_crtc->plane; |
| 1699 | unsigned long Start, Offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1700 | u32 dspcntr; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1701 | u32 reg; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1702 | |
| 1703 | switch (plane) { |
| 1704 | case 0: |
| 1705 | case 1: |
| 1706 | break; |
| 1707 | default: |
| 1708 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
| 1709 | return -EINVAL; |
| 1710 | } |
| 1711 | |
| 1712 | intel_fb = to_intel_framebuffer(fb); |
| 1713 | obj = intel_fb->obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1714 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1715 | reg = DSPCNTR(plane); |
| 1716 | dspcntr = I915_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1717 | /* Mask out pixel format bits in case we change it */ |
| 1718 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 1719 | switch (fb->bits_per_pixel) { |
| 1720 | case 8: |
| 1721 | dspcntr |= DISPPLANE_8BPP; |
| 1722 | break; |
| 1723 | case 16: |
| 1724 | if (fb->depth == 15) |
| 1725 | dspcntr |= DISPPLANE_15_16BPP; |
| 1726 | else |
| 1727 | dspcntr |= DISPPLANE_16BPP; |
| 1728 | break; |
| 1729 | case 24: |
| 1730 | case 32: |
| 1731 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 1732 | break; |
| 1733 | default: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1734 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1735 | return -EINVAL; |
| 1736 | } |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1737 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1738 | if (obj->tiling_mode != I915_TILING_NONE) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1739 | dspcntr |= DISPPLANE_TILED; |
| 1740 | else |
| 1741 | dspcntr &= ~DISPPLANE_TILED; |
| 1742 | } |
| 1743 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1744 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1745 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1746 | Start = obj->gtt_offset; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1747 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1748 | |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1749 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1750 | Start, Offset, x, y, fb->pitches[0]); |
| 1751 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1752 | if (INTEL_INFO(dev)->gen >= 4) { |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 1753 | I915_MODIFY_DISPBASE(DSPSURF(plane), Start); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1754 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 1755 | I915_WRITE(DSPADDR(plane), Offset); |
| 1756 | } else |
| 1757 | I915_WRITE(DSPADDR(plane), Start + Offset); |
| 1758 | POSTING_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1759 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1760 | return 0; |
| 1761 | } |
| 1762 | |
| 1763 | static int ironlake_update_plane(struct drm_crtc *crtc, |
| 1764 | struct drm_framebuffer *fb, int x, int y) |
| 1765 | { |
| 1766 | struct drm_device *dev = crtc->dev; |
| 1767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1769 | struct intel_framebuffer *intel_fb; |
| 1770 | struct drm_i915_gem_object *obj; |
| 1771 | int plane = intel_crtc->plane; |
| 1772 | unsigned long Start, Offset; |
| 1773 | u32 dspcntr; |
| 1774 | u32 reg; |
| 1775 | |
| 1776 | switch (plane) { |
| 1777 | case 0: |
| 1778 | case 1: |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 1779 | case 2: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1780 | break; |
| 1781 | default: |
| 1782 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); |
| 1783 | return -EINVAL; |
| 1784 | } |
| 1785 | |
| 1786 | intel_fb = to_intel_framebuffer(fb); |
| 1787 | obj = intel_fb->obj; |
| 1788 | |
| 1789 | reg = DSPCNTR(plane); |
| 1790 | dspcntr = I915_READ(reg); |
| 1791 | /* Mask out pixel format bits in case we change it */ |
| 1792 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 1793 | switch (fb->bits_per_pixel) { |
| 1794 | case 8: |
| 1795 | dspcntr |= DISPPLANE_8BPP; |
| 1796 | break; |
| 1797 | case 16: |
| 1798 | if (fb->depth != 16) |
| 1799 | return -EINVAL; |
| 1800 | |
| 1801 | dspcntr |= DISPPLANE_16BPP; |
| 1802 | break; |
| 1803 | case 24: |
| 1804 | case 32: |
| 1805 | if (fb->depth == 24) |
| 1806 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 1807 | else if (fb->depth == 30) |
| 1808 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; |
| 1809 | else |
| 1810 | return -EINVAL; |
| 1811 | break; |
| 1812 | default: |
| 1813 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
| 1814 | return -EINVAL; |
| 1815 | } |
| 1816 | |
| 1817 | if (obj->tiling_mode != I915_TILING_NONE) |
| 1818 | dspcntr |= DISPPLANE_TILED; |
| 1819 | else |
| 1820 | dspcntr &= ~DISPPLANE_TILED; |
| 1821 | |
| 1822 | /* must disable */ |
| 1823 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 1824 | |
| 1825 | I915_WRITE(reg, dspcntr); |
| 1826 | |
| 1827 | Start = obj->gtt_offset; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1828 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1829 | |
| 1830 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1831 | Start, Offset, x, y, fb->pitches[0]); |
| 1832 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 1833 | I915_MODIFY_DISPBASE(DSPSURF(plane), Start); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1834 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 1835 | I915_WRITE(DSPADDR(plane), Offset); |
| 1836 | POSTING_READ(reg); |
| 1837 | |
| 1838 | return 0; |
| 1839 | } |
| 1840 | |
| 1841 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 1842 | static int |
| 1843 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 1844 | int x, int y, enum mode_set_atomic state) |
| 1845 | { |
| 1846 | struct drm_device *dev = crtc->dev; |
| 1847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 1848 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 1849 | if (dev_priv->display.disable_fbc) |
| 1850 | dev_priv->display.disable_fbc(dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 1851 | intel_increase_pllclock(crtc); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1852 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 1853 | return dev_priv->display.update_plane(crtc, fb, x, y); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 1854 | } |
| 1855 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1856 | static int |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 1857 | intel_finish_fb(struct drm_framebuffer *old_fb) |
| 1858 | { |
| 1859 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
| 1860 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1861 | bool was_interruptible = dev_priv->mm.interruptible; |
| 1862 | int ret; |
| 1863 | |
| 1864 | wait_event(dev_priv->pending_flip_queue, |
| 1865 | atomic_read(&dev_priv->mm.wedged) || |
| 1866 | atomic_read(&obj->pending_flip) == 0); |
| 1867 | |
| 1868 | /* Big Hammer, we also need to ensure that any pending |
| 1869 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 1870 | * current scanout is retired before unpinning the old |
| 1871 | * framebuffer. |
| 1872 | * |
| 1873 | * This should only fail upon a hung GPU, in which case we |
| 1874 | * can safely continue. |
| 1875 | */ |
| 1876 | dev_priv->mm.interruptible = false; |
| 1877 | ret = i915_gem_object_finish_gpu(obj); |
| 1878 | dev_priv->mm.interruptible = was_interruptible; |
| 1879 | |
| 1880 | return ret; |
| 1881 | } |
| 1882 | |
| 1883 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1884 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
| 1885 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1886 | { |
| 1887 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1889 | struct drm_i915_master_private *master_priv; |
| 1890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1891 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1892 | |
| 1893 | /* no fb bound */ |
| 1894 | if (!crtc->fb) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 1895 | DRM_ERROR("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1896 | return 0; |
| 1897 | } |
| 1898 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1899 | switch (intel_crtc->plane) { |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1900 | case 0: |
| 1901 | case 1: |
| 1902 | break; |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 1903 | case 2: |
| 1904 | if (IS_IVYBRIDGE(dev)) |
| 1905 | break; |
| 1906 | /* fall through otherwise */ |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1907 | default: |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 1908 | DRM_ERROR("no plane for crtc\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1909 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1910 | } |
| 1911 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1912 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1913 | ret = intel_pin_and_fence_fb_obj(dev, |
| 1914 | to_intel_framebuffer(crtc->fb)->obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1915 | NULL); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1916 | if (ret != 0) { |
| 1917 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 1918 | DRM_ERROR("pin & fence failed\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1919 | return ret; |
| 1920 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1921 | |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 1922 | if (old_fb) |
| 1923 | intel_finish_fb(old_fb); |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1924 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 1925 | ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1926 | if (ret) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1927 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1928 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 1929 | DRM_ERROR("failed to update base address\n"); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 1930 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1931 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 1932 | |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 1933 | if (old_fb) { |
| 1934 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 1935 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 1936 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1937 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 1938 | intel_update_fbc(dev); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1939 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1940 | |
| 1941 | if (!dev->primary->master) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1942 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1943 | |
| 1944 | master_priv = dev->primary->master->driver_priv; |
| 1945 | if (!master_priv->sarea_priv) |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1946 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1947 | |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 1948 | if (intel_crtc->pipe) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1949 | master_priv->sarea_priv->pipeB_x = x; |
| 1950 | master_priv->sarea_priv->pipeB_y = y; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1951 | } else { |
| 1952 | master_priv->sarea_priv->pipeA_x = x; |
| 1953 | master_priv->sarea_priv->pipeA_y = y; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1954 | } |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 1955 | |
| 1956 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1957 | } |
| 1958 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1959 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1960 | { |
| 1961 | struct drm_device *dev = crtc->dev; |
| 1962 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1963 | u32 dpa_ctl; |
| 1964 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1965 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1966 | dpa_ctl = I915_READ(DP_A); |
| 1967 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 1968 | |
| 1969 | if (clock < 200000) { |
| 1970 | u32 temp; |
| 1971 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 1972 | /* workaround for 160Mhz: |
| 1973 | 1) program 0x4600c bits 15:0 = 0x8124 |
| 1974 | 2) program 0x46010 bit 0 = 1 |
| 1975 | 3) program 0x46034 bit 24 = 1 |
| 1976 | 4) program 0x64000 bit 14 = 1 |
| 1977 | */ |
| 1978 | temp = I915_READ(0x4600c); |
| 1979 | temp &= 0xffff0000; |
| 1980 | I915_WRITE(0x4600c, temp | 0x8124); |
| 1981 | |
| 1982 | temp = I915_READ(0x46010); |
| 1983 | I915_WRITE(0x46010, temp | 1); |
| 1984 | |
| 1985 | temp = I915_READ(0x46034); |
| 1986 | I915_WRITE(0x46034, temp | (1 << 24)); |
| 1987 | } else { |
| 1988 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 1989 | } |
| 1990 | I915_WRITE(DP_A, dpa_ctl); |
| 1991 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1992 | POSTING_READ(DP_A); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1993 | udelay(500); |
| 1994 | } |
| 1995 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 1996 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 1997 | { |
| 1998 | struct drm_device *dev = crtc->dev; |
| 1999 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2000 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2001 | int pipe = intel_crtc->pipe; |
| 2002 | u32 reg, temp; |
| 2003 | |
| 2004 | /* enable normal train */ |
| 2005 | reg = FDI_TX_CTL(pipe); |
| 2006 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2007 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2008 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2009 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2010 | } else { |
| 2011 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2012 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2013 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2014 | I915_WRITE(reg, temp); |
| 2015 | |
| 2016 | reg = FDI_RX_CTL(pipe); |
| 2017 | temp = I915_READ(reg); |
| 2018 | if (HAS_PCH_CPT(dev)) { |
| 2019 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2020 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 2021 | } else { |
| 2022 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2023 | temp |= FDI_LINK_TRAIN_NONE; |
| 2024 | } |
| 2025 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 2026 | |
| 2027 | /* wait one idle pattern time */ |
| 2028 | POSTING_READ(reg); |
| 2029 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2030 | |
| 2031 | /* IVB wants error correction enabled */ |
| 2032 | if (IS_IVYBRIDGE(dev)) |
| 2033 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 2034 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2035 | } |
| 2036 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2037 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
| 2038 | { |
| 2039 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2040 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
| 2041 | |
| 2042 | flags |= FDI_PHASE_SYNC_OVR(pipe); |
| 2043 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ |
| 2044 | flags |= FDI_PHASE_SYNC_EN(pipe); |
| 2045 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ |
| 2046 | POSTING_READ(SOUTH_CHICKEN1); |
| 2047 | } |
| 2048 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2049 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 2050 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 2051 | { |
| 2052 | struct drm_device *dev = crtc->dev; |
| 2053 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2055 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2056 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2057 | u32 reg, temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2058 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2059 | /* FDI needs bits from pipe & plane first */ |
| 2060 | assert_pipe_enabled(dev_priv, pipe); |
| 2061 | assert_plane_enabled(dev_priv, plane); |
| 2062 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2063 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2064 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2065 | reg = FDI_RX_IMR(pipe); |
| 2066 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2067 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2068 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2069 | I915_WRITE(reg, temp); |
| 2070 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2071 | udelay(150); |
| 2072 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2073 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2074 | reg = FDI_TX_CTL(pipe); |
| 2075 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 2076 | temp &= ~(7 << 19); |
| 2077 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2078 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2079 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2080 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2081 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2082 | reg = FDI_RX_CTL(pipe); |
| 2083 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2084 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2085 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2086 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2087 | |
| 2088 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2089 | udelay(150); |
| 2090 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2091 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2092 | if (HAS_PCH_IBX(dev)) { |
| 2093 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 2094 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 2095 | FDI_RX_PHASE_SYNC_POINTER_EN); |
| 2096 | } |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2097 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2098 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2099 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2100 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2101 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2102 | |
| 2103 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 2104 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2105 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2106 | break; |
| 2107 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2108 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2109 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2110 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2111 | |
| 2112 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2113 | reg = FDI_TX_CTL(pipe); |
| 2114 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2115 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2116 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2117 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2118 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2119 | reg = FDI_RX_CTL(pipe); |
| 2120 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2121 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2122 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2123 | I915_WRITE(reg, temp); |
| 2124 | |
| 2125 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2126 | udelay(150); |
| 2127 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2128 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2129 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2130 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2131 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2132 | |
| 2133 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2134 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2135 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2136 | break; |
| 2137 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2138 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2139 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2140 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2141 | |
| 2142 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 2143 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2144 | } |
| 2145 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2146 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2147 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 2148 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 2149 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 2150 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 2151 | }; |
| 2152 | |
| 2153 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 2154 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 2155 | { |
| 2156 | struct drm_device *dev = crtc->dev; |
| 2157 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2159 | int pipe = intel_crtc->pipe; |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2160 | u32 reg, temp, i, retry; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2161 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2162 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2163 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2164 | reg = FDI_RX_IMR(pipe); |
| 2165 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2166 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2167 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2168 | I915_WRITE(reg, temp); |
| 2169 | |
| 2170 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2171 | udelay(150); |
| 2172 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2173 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2174 | reg = FDI_TX_CTL(pipe); |
| 2175 | temp = I915_READ(reg); |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 2176 | temp &= ~(7 << 19); |
| 2177 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2178 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2179 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2180 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2181 | /* SNB-B */ |
| 2182 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2183 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2184 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2185 | reg = FDI_RX_CTL(pipe); |
| 2186 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2187 | if (HAS_PCH_CPT(dev)) { |
| 2188 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2189 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2190 | } else { |
| 2191 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2192 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2193 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2194 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2195 | |
| 2196 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2197 | udelay(150); |
| 2198 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2199 | if (HAS_PCH_CPT(dev)) |
| 2200 | cpt_phase_pointer_enable(dev, pipe); |
| 2201 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2202 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2203 | reg = FDI_TX_CTL(pipe); |
| 2204 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2205 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2206 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2207 | I915_WRITE(reg, temp); |
| 2208 | |
| 2209 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2210 | udelay(500); |
| 2211 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2212 | for (retry = 0; retry < 5; retry++) { |
| 2213 | reg = FDI_RX_IIR(pipe); |
| 2214 | temp = I915_READ(reg); |
| 2215 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2216 | if (temp & FDI_RX_BIT_LOCK) { |
| 2217 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 2218 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 2219 | break; |
| 2220 | } |
| 2221 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2222 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2223 | if (retry < 5) |
| 2224 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2225 | } |
| 2226 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2227 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2228 | |
| 2229 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2230 | reg = FDI_TX_CTL(pipe); |
| 2231 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2232 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2233 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2234 | if (IS_GEN6(dev)) { |
| 2235 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2236 | /* SNB-B */ |
| 2237 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 2238 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2239 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2240 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2241 | reg = FDI_RX_CTL(pipe); |
| 2242 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2243 | if (HAS_PCH_CPT(dev)) { |
| 2244 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2245 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 2246 | } else { |
| 2247 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2248 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2249 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2250 | I915_WRITE(reg, temp); |
| 2251 | |
| 2252 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2253 | udelay(150); |
| 2254 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2255 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2256 | reg = FDI_TX_CTL(pipe); |
| 2257 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2258 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2259 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2260 | I915_WRITE(reg, temp); |
| 2261 | |
| 2262 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2263 | udelay(500); |
| 2264 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2265 | for (retry = 0; retry < 5; retry++) { |
| 2266 | reg = FDI_RX_IIR(pipe); |
| 2267 | temp = I915_READ(reg); |
| 2268 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2269 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 2270 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 2271 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2272 | break; |
| 2273 | } |
| 2274 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2275 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2276 | if (retry < 5) |
| 2277 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2278 | } |
| 2279 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2280 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2281 | |
| 2282 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2283 | } |
| 2284 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2285 | /* Manual link training for Ivy Bridge A0 parts */ |
| 2286 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 2287 | { |
| 2288 | struct drm_device *dev = crtc->dev; |
| 2289 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2291 | int pipe = intel_crtc->pipe; |
| 2292 | u32 reg, temp, i; |
| 2293 | |
| 2294 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2295 | for train result */ |
| 2296 | reg = FDI_RX_IMR(pipe); |
| 2297 | temp = I915_READ(reg); |
| 2298 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2299 | temp &= ~FDI_RX_BIT_LOCK; |
| 2300 | I915_WRITE(reg, temp); |
| 2301 | |
| 2302 | POSTING_READ(reg); |
| 2303 | udelay(150); |
| 2304 | |
| 2305 | /* enable CPU FDI TX and PCH FDI RX */ |
| 2306 | reg = FDI_TX_CTL(pipe); |
| 2307 | temp = I915_READ(reg); |
| 2308 | temp &= ~(7 << 19); |
| 2309 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
| 2310 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 2311 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
| 2312 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2313 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Jesse Barnes | c4f9c4c | 2011-10-10 14:28:52 -0700 | [diff] [blame] | 2314 | temp |= FDI_COMPOSITE_SYNC; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2315 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 2316 | |
| 2317 | reg = FDI_RX_CTL(pipe); |
| 2318 | temp = I915_READ(reg); |
| 2319 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 2320 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2321 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
Jesse Barnes | c4f9c4c | 2011-10-10 14:28:52 -0700 | [diff] [blame] | 2322 | temp |= FDI_COMPOSITE_SYNC; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2323 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2324 | |
| 2325 | POSTING_READ(reg); |
| 2326 | udelay(150); |
| 2327 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2328 | if (HAS_PCH_CPT(dev)) |
| 2329 | cpt_phase_pointer_enable(dev, pipe); |
| 2330 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2331 | for (i = 0; i < 4; i++) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2332 | reg = FDI_TX_CTL(pipe); |
| 2333 | temp = I915_READ(reg); |
| 2334 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2335 | temp |= snb_b_fdi_train_param[i]; |
| 2336 | I915_WRITE(reg, temp); |
| 2337 | |
| 2338 | POSTING_READ(reg); |
| 2339 | udelay(500); |
| 2340 | |
| 2341 | reg = FDI_RX_IIR(pipe); |
| 2342 | temp = I915_READ(reg); |
| 2343 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2344 | |
| 2345 | if (temp & FDI_RX_BIT_LOCK || |
| 2346 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 2347 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 2348 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 2349 | break; |
| 2350 | } |
| 2351 | } |
| 2352 | if (i == 4) |
| 2353 | DRM_ERROR("FDI train 1 fail!\n"); |
| 2354 | |
| 2355 | /* Train 2 */ |
| 2356 | reg = FDI_TX_CTL(pipe); |
| 2357 | temp = I915_READ(reg); |
| 2358 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2359 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 2360 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2361 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 2362 | I915_WRITE(reg, temp); |
| 2363 | |
| 2364 | reg = FDI_RX_CTL(pipe); |
| 2365 | temp = I915_READ(reg); |
| 2366 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2367 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 2368 | I915_WRITE(reg, temp); |
| 2369 | |
| 2370 | POSTING_READ(reg); |
| 2371 | udelay(150); |
| 2372 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2373 | for (i = 0; i < 4; i++) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2374 | reg = FDI_TX_CTL(pipe); |
| 2375 | temp = I915_READ(reg); |
| 2376 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2377 | temp |= snb_b_fdi_train_param[i]; |
| 2378 | I915_WRITE(reg, temp); |
| 2379 | |
| 2380 | POSTING_READ(reg); |
| 2381 | udelay(500); |
| 2382 | |
| 2383 | reg = FDI_RX_IIR(pipe); |
| 2384 | temp = I915_READ(reg); |
| 2385 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2386 | |
| 2387 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 2388 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 2389 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2390 | break; |
| 2391 | } |
| 2392 | } |
| 2393 | if (i == 4) |
| 2394 | DRM_ERROR("FDI train 2 fail!\n"); |
| 2395 | |
| 2396 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2397 | } |
| 2398 | |
| 2399 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2400 | { |
| 2401 | struct drm_device *dev = crtc->dev; |
| 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2404 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2405 | u32 reg, temp; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2406 | |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 2407 | /* Write the TU size bits so error detection works */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2408 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 2409 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 2410 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2411 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2412 | reg = FDI_RX_CTL(pipe); |
| 2413 | temp = I915_READ(reg); |
| 2414 | temp &= ~((0x7 << 19) | (0x7 << 16)); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2415 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2416 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2417 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 2418 | |
| 2419 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2420 | udelay(200); |
| 2421 | |
| 2422 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2423 | temp = I915_READ(reg); |
| 2424 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 2425 | |
| 2426 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2427 | udelay(200); |
| 2428 | |
| 2429 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2430 | reg = FDI_TX_CTL(pipe); |
| 2431 | temp = I915_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2432 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2433 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
| 2434 | |
| 2435 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2436 | udelay(100); |
| 2437 | } |
| 2438 | } |
| 2439 | |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2440 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
| 2441 | { |
| 2442 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2443 | u32 flags = I915_READ(SOUTH_CHICKEN1); |
| 2444 | |
| 2445 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); |
| 2446 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ |
| 2447 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); |
| 2448 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ |
| 2449 | POSTING_READ(SOUTH_CHICKEN1); |
| 2450 | } |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2451 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 2452 | { |
| 2453 | struct drm_device *dev = crtc->dev; |
| 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2455 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2456 | int pipe = intel_crtc->pipe; |
| 2457 | u32 reg, temp; |
| 2458 | |
| 2459 | /* disable CPU FDI tx and PCH FDI rx */ |
| 2460 | reg = FDI_TX_CTL(pipe); |
| 2461 | temp = I915_READ(reg); |
| 2462 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 2463 | POSTING_READ(reg); |
| 2464 | |
| 2465 | reg = FDI_RX_CTL(pipe); |
| 2466 | temp = I915_READ(reg); |
| 2467 | temp &= ~(0x7 << 16); |
| 2468 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2469 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 2470 | |
| 2471 | POSTING_READ(reg); |
| 2472 | udelay(100); |
| 2473 | |
| 2474 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2475 | if (HAS_PCH_IBX(dev)) { |
| 2476 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2477 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
| 2478 | I915_READ(FDI_RX_CHICKEN(pipe) & |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2479 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
Jesse Barnes | 291427f | 2011-07-29 12:42:37 -0700 | [diff] [blame] | 2480 | } else if (HAS_PCH_CPT(dev)) { |
| 2481 | cpt_phase_pointer_disable(dev, pipe); |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 2482 | } |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2483 | |
| 2484 | /* still set train pattern 1 */ |
| 2485 | reg = FDI_TX_CTL(pipe); |
| 2486 | temp = I915_READ(reg); |
| 2487 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2488 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2489 | I915_WRITE(reg, temp); |
| 2490 | |
| 2491 | reg = FDI_RX_CTL(pipe); |
| 2492 | temp = I915_READ(reg); |
| 2493 | if (HAS_PCH_CPT(dev)) { |
| 2494 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2495 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2496 | } else { |
| 2497 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2498 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2499 | } |
| 2500 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 2501 | temp &= ~(0x07 << 16); |
| 2502 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
| 2503 | I915_WRITE(reg, temp); |
| 2504 | |
| 2505 | POSTING_READ(reg); |
| 2506 | udelay(100); |
| 2507 | } |
| 2508 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2509 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
| 2510 | { |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 2511 | struct drm_device *dev = crtc->dev; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2512 | |
| 2513 | if (crtc->fb == NULL) |
| 2514 | return; |
| 2515 | |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 2516 | mutex_lock(&dev->struct_mutex); |
| 2517 | intel_finish_fb(crtc->fb); |
| 2518 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2519 | } |
| 2520 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2521 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
| 2522 | { |
| 2523 | struct drm_device *dev = crtc->dev; |
| 2524 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2525 | struct intel_encoder *encoder; |
| 2526 | |
| 2527 | /* |
| 2528 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that |
| 2529 | * must be driven by its own crtc; no sharing is possible. |
| 2530 | */ |
| 2531 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 2532 | if (encoder->base.crtc != crtc) |
| 2533 | continue; |
| 2534 | |
| 2535 | switch (encoder->type) { |
| 2536 | case INTEL_OUTPUT_EDP: |
| 2537 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
| 2538 | return false; |
| 2539 | continue; |
| 2540 | } |
| 2541 | } |
| 2542 | |
| 2543 | return true; |
| 2544 | } |
| 2545 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2546 | /* |
| 2547 | * Enable PCH resources required for PCH ports: |
| 2548 | * - PCH PLLs |
| 2549 | * - FDI training & RX/TX |
| 2550 | * - update transcoder timings |
| 2551 | * - DP transcoding bits |
| 2552 | * - transcoder |
| 2553 | */ |
| 2554 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2555 | { |
| 2556 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2557 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2559 | int pipe = intel_crtc->pipe; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2560 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2561 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2562 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 2563 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2564 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2565 | intel_enable_pch_pll(intel_crtc); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2566 | |
| 2567 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2568 | u32 sel; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 2569 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2570 | temp = I915_READ(PCH_DPLL_SEL); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2571 | switch (pipe) { |
| 2572 | default: |
| 2573 | case 0: |
| 2574 | temp |= TRANSA_DPLL_ENABLE; |
| 2575 | sel = TRANSA_DPLLB_SEL; |
| 2576 | break; |
| 2577 | case 1: |
| 2578 | temp |= TRANSB_DPLL_ENABLE; |
| 2579 | sel = TRANSB_DPLLB_SEL; |
| 2580 | break; |
| 2581 | case 2: |
| 2582 | temp |= TRANSC_DPLL_ENABLE; |
| 2583 | sel = TRANSC_DPLLB_SEL; |
| 2584 | break; |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2585 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2586 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
| 2587 | temp |= sel; |
| 2588 | else |
| 2589 | temp &= ~sel; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2590 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2591 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2592 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 2593 | /* set transcoder timing, panel must allow it */ |
| 2594 | assert_panel_unlocked(dev_priv, pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2595 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
| 2596 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); |
| 2597 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); |
| 2598 | |
| 2599 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
| 2600 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); |
| 2601 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 2602 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2603 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2604 | intel_fdi_normal_train(crtc); |
| 2605 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2606 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 2607 | if (HAS_PCH_CPT(dev) && |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2608 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 2609 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 2610 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2611 | reg = TRANS_DP_CTL(pipe); |
| 2612 | temp = I915_READ(reg); |
| 2613 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 2614 | TRANS_DP_SYNC_MASK | |
| 2615 | TRANS_DP_BPC_MASK); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2616 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
| 2617 | TRANS_DP_ENH_FRAMING); |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 2618 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2619 | |
| 2620 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2621 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2622 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2623 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2624 | |
| 2625 | switch (intel_trans_dp_port_sel(crtc)) { |
| 2626 | case PCH_DP_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2627 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2628 | break; |
| 2629 | case PCH_DP_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2630 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2631 | break; |
| 2632 | case PCH_DP_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2633 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2634 | break; |
| 2635 | default: |
| 2636 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2637 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2638 | break; |
| 2639 | } |
| 2640 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2641 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 2642 | } |
| 2643 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2644 | intel_enable_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2645 | } |
| 2646 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2647 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
| 2648 | { |
| 2649 | struct intel_pch_pll *pll = intel_crtc->pch_pll; |
| 2650 | |
| 2651 | if (pll == NULL) |
| 2652 | return; |
| 2653 | |
| 2654 | if (pll->refcount == 0) { |
| 2655 | WARN(1, "bad PCH PLL refcount\n"); |
| 2656 | return; |
| 2657 | } |
| 2658 | |
| 2659 | --pll->refcount; |
| 2660 | intel_crtc->pch_pll = NULL; |
| 2661 | } |
| 2662 | |
| 2663 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) |
| 2664 | { |
| 2665 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
| 2666 | struct intel_pch_pll *pll; |
| 2667 | int i; |
| 2668 | |
| 2669 | pll = intel_crtc->pch_pll; |
| 2670 | if (pll) { |
| 2671 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", |
| 2672 | intel_crtc->base.base.id, pll->pll_reg); |
| 2673 | goto prepare; |
| 2674 | } |
| 2675 | |
| 2676 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
| 2677 | pll = &dev_priv->pch_plls[i]; |
| 2678 | |
| 2679 | /* Only want to check enabled timings first */ |
| 2680 | if (pll->refcount == 0) |
| 2681 | continue; |
| 2682 | |
| 2683 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && |
| 2684 | fp == I915_READ(pll->fp0_reg)) { |
| 2685 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", |
| 2686 | intel_crtc->base.base.id, |
| 2687 | pll->pll_reg, pll->refcount, pll->active); |
| 2688 | |
| 2689 | goto found; |
| 2690 | } |
| 2691 | } |
| 2692 | |
| 2693 | /* Ok no matching timings, maybe there's a free one? */ |
| 2694 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
| 2695 | pll = &dev_priv->pch_plls[i]; |
| 2696 | if (pll->refcount == 0) { |
| 2697 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", |
| 2698 | intel_crtc->base.base.id, pll->pll_reg); |
| 2699 | goto found; |
| 2700 | } |
| 2701 | } |
| 2702 | |
| 2703 | return NULL; |
| 2704 | |
| 2705 | found: |
| 2706 | intel_crtc->pch_pll = pll; |
| 2707 | pll->refcount++; |
| 2708 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); |
| 2709 | prepare: /* separate function? */ |
| 2710 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); |
| 2711 | I915_WRITE(pll->fp0_reg, fp); |
| 2712 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); |
| 2713 | |
| 2714 | POSTING_READ(pll->pll_reg); |
| 2715 | udelay(150); |
| 2716 | pll->on = false; |
| 2717 | return pll; |
| 2718 | } |
| 2719 | |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 2720 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
| 2721 | { |
| 2722 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2723 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); |
| 2724 | u32 temp; |
| 2725 | |
| 2726 | temp = I915_READ(dslreg); |
| 2727 | udelay(500); |
| 2728 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
| 2729 | /* Without this, mode sets may fail silently on FDI */ |
| 2730 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); |
| 2731 | udelay(250); |
| 2732 | I915_WRITE(tc2reg, 0); |
| 2733 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
| 2734 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); |
| 2735 | } |
| 2736 | } |
| 2737 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2738 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 2739 | { |
| 2740 | struct drm_device *dev = crtc->dev; |
| 2741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2743 | int pipe = intel_crtc->pipe; |
| 2744 | int plane = intel_crtc->plane; |
| 2745 | u32 temp; |
| 2746 | bool is_pch_port; |
| 2747 | |
| 2748 | if (intel_crtc->active) |
| 2749 | return; |
| 2750 | |
| 2751 | intel_crtc->active = true; |
| 2752 | intel_update_watermarks(dev); |
| 2753 | |
| 2754 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 2755 | temp = I915_READ(PCH_LVDS); |
| 2756 | if ((temp & LVDS_PORT_EN) == 0) |
| 2757 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
| 2758 | } |
| 2759 | |
| 2760 | is_pch_port = intel_crtc_driving_pch(crtc); |
| 2761 | |
| 2762 | if (is_pch_port) |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2763 | ironlake_fdi_pll_enable(crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2764 | else |
| 2765 | ironlake_fdi_disable(crtc); |
| 2766 | |
| 2767 | /* Enable panel fitting for LVDS */ |
| 2768 | if (dev_priv->pch_pf_size && |
| 2769 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
| 2770 | /* Force use of hard-coded filter coefficients |
| 2771 | * as some pre-programmed values are broken, |
| 2772 | * e.g. x201. |
| 2773 | */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2774 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
| 2775 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
| 2776 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2777 | } |
| 2778 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 2779 | /* |
| 2780 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 2781 | * clocks enabled |
| 2782 | */ |
| 2783 | intel_crtc_load_lut(crtc); |
| 2784 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 2785 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
| 2786 | intel_enable_plane(dev_priv, plane, pipe); |
| 2787 | |
| 2788 | if (is_pch_port) |
| 2789 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2790 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 2791 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2792 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 2793 | mutex_unlock(&dev->struct_mutex); |
| 2794 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2795 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2796 | } |
| 2797 | |
| 2798 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 2799 | { |
| 2800 | struct drm_device *dev = crtc->dev; |
| 2801 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2803 | int pipe = intel_crtc->pipe; |
| 2804 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2805 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2806 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2807 | if (!intel_crtc->active) |
| 2808 | return; |
| 2809 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2810 | intel_crtc_wait_for_pending_flips(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2811 | drm_vblank_off(dev, pipe); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2812 | intel_crtc_update_cursor(crtc, false); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2813 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2814 | intel_disable_plane(dev_priv, plane, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2815 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 2816 | if (dev_priv->cfb_plane == plane) |
| 2817 | intel_disable_fbc(dev); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2818 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2819 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2820 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2821 | /* Disable PF */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2822 | I915_WRITE(PF_CTL(pipe), 0); |
| 2823 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2824 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2825 | ironlake_fdi_disable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2826 | |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 2827 | /* This is a horrible layering violation; we should be doing this in |
| 2828 | * the connector/encoder ->prepare instead, but we don't always have |
| 2829 | * enough information there about the config to know whether it will |
| 2830 | * actually be necessary or just cause undesired flicker. |
| 2831 | */ |
| 2832 | intel_disable_pch_ports(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2833 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2834 | intel_disable_transcoder(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2835 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2836 | if (HAS_PCH_CPT(dev)) { |
| 2837 | /* disable TRANS_DP_CTL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2838 | reg = TRANS_DP_CTL(pipe); |
| 2839 | temp = I915_READ(reg); |
| 2840 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); |
Eric Anholt | cb3543c | 2011-02-02 12:08:07 -0800 | [diff] [blame] | 2841 | temp |= TRANS_DP_PORT_SEL_NONE; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2842 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2843 | |
| 2844 | /* disable DPLL_SEL */ |
| 2845 | temp = I915_READ(PCH_DPLL_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2846 | switch (pipe) { |
| 2847 | case 0: |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2848 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2849 | break; |
| 2850 | case 1: |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2851 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2852 | break; |
| 2853 | case 2: |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 2854 | /* C shares PLL A or B */ |
Jesse Barnes | d64311a | 2011-10-12 15:01:33 -0700 | [diff] [blame] | 2855 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2856 | break; |
| 2857 | default: |
| 2858 | BUG(); /* wtf */ |
| 2859 | } |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2860 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2861 | } |
| 2862 | |
| 2863 | /* disable PCH DPLL */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2864 | intel_disable_pch_pll(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2865 | |
| 2866 | /* Switch from PCDclk to Rawclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2867 | reg = FDI_RX_CTL(pipe); |
| 2868 | temp = I915_READ(reg); |
| 2869 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2870 | |
| 2871 | /* Disable CPU FDI TX PLL */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2872 | reg = FDI_TX_CTL(pipe); |
| 2873 | temp = I915_READ(reg); |
| 2874 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 2875 | |
| 2876 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2877 | udelay(100); |
| 2878 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2879 | reg = FDI_RX_CTL(pipe); |
| 2880 | temp = I915_READ(reg); |
| 2881 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2882 | |
| 2883 | /* Wait for the clocks to turn off. */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2884 | POSTING_READ(reg); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2885 | udelay(100); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2886 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2887 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2888 | intel_update_watermarks(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 2889 | |
| 2890 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2891 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 2892 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2893 | } |
| 2894 | |
| 2895 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2896 | { |
| 2897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2898 | int pipe = intel_crtc->pipe; |
| 2899 | int plane = intel_crtc->plane; |
| 2900 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2901 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 2902 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 2903 | */ |
| 2904 | switch (mode) { |
| 2905 | case DRM_MODE_DPMS_ON: |
| 2906 | case DRM_MODE_DPMS_STANDBY: |
| 2907 | case DRM_MODE_DPMS_SUSPEND: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2908 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2909 | ironlake_crtc_enable(crtc); |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2910 | break; |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 2911 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2912 | case DRM_MODE_DPMS_OFF: |
Chris Wilson | 868dc58 | 2010-08-07 11:01:31 +0100 | [diff] [blame] | 2913 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 2914 | ironlake_crtc_disable(crtc); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2915 | break; |
| 2916 | } |
| 2917 | } |
| 2918 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2919 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
| 2920 | { |
| 2921 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2922 | intel_put_pch_pll(intel_crtc); |
| 2923 | } |
| 2924 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2925 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 2926 | { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2927 | if (!enable && intel_crtc->overlay) { |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 2928 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2929 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 2930 | |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 2931 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2932 | dev_priv->mm.interruptible = false; |
| 2933 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 2934 | dev_priv->mm.interruptible = true; |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 2935 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2936 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2937 | |
Chris Wilson | 5dcdbcb | 2010-08-12 13:50:28 +0100 | [diff] [blame] | 2938 | /* Let userspace switch the overlay on again. In most cases userspace |
| 2939 | * has to recompute where to put it anyway. |
| 2940 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2941 | } |
| 2942 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2943 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 2944 | { |
| 2945 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2946 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2948 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 2949 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2950 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2951 | if (intel_crtc->active) |
| 2952 | return; |
| 2953 | |
| 2954 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2955 | intel_update_watermarks(dev); |
| 2956 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 2957 | intel_enable_pll(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 2958 | intel_enable_pipe(dev_priv, pipe, false); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2959 | intel_enable_plane(dev_priv, plane, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2960 | |
| 2961 | intel_crtc_load_lut(crtc); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 2962 | intel_update_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2963 | |
| 2964 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
| 2965 | intel_crtc_dpms_overlay(intel_crtc, true); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2966 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2967 | } |
| 2968 | |
| 2969 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 2970 | { |
| 2971 | struct drm_device *dev = crtc->dev; |
| 2972 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2974 | int pipe = intel_crtc->pipe; |
| 2975 | int plane = intel_crtc->plane; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2976 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2977 | if (!intel_crtc->active) |
| 2978 | return; |
| 2979 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2980 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 2981 | intel_crtc_wait_for_pending_flips(crtc); |
| 2982 | drm_vblank_off(dev, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2983 | intel_crtc_dpms_overlay(intel_crtc, false); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2984 | intel_crtc_update_cursor(crtc, false); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2985 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 2986 | if (dev_priv->cfb_plane == plane) |
| 2987 | intel_disable_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2988 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2989 | intel_disable_plane(dev_priv, plane, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 2990 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 2991 | intel_disable_pll(dev_priv, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2992 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 2993 | intel_crtc->active = false; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 2994 | intel_update_fbc(dev); |
| 2995 | intel_update_watermarks(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 2996 | } |
| 2997 | |
| 2998 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2999 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3000 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 3001 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 3002 | */ |
| 3003 | switch (mode) { |
| 3004 | case DRM_MODE_DPMS_ON: |
| 3005 | case DRM_MODE_DPMS_STANDBY: |
| 3006 | case DRM_MODE_DPMS_SUSPEND: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3007 | i9xx_crtc_enable(crtc); |
| 3008 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3009 | case DRM_MODE_DPMS_OFF: |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 3010 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3011 | break; |
| 3012 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3013 | } |
| 3014 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3015 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
| 3016 | { |
| 3017 | } |
| 3018 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3019 | /** |
| 3020 | * Sets the power management mode of the pipe and plane. |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3021 | */ |
| 3022 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 3023 | { |
| 3024 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3025 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3026 | struct drm_i915_master_private *master_priv; |
| 3027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3028 | int pipe = intel_crtc->pipe; |
| 3029 | bool enabled; |
| 3030 | |
Chris Wilson | 032d2a0 | 2010-09-06 16:17:22 +0100 | [diff] [blame] | 3031 | if (intel_crtc->dpms_mode == mode) |
| 3032 | return; |
| 3033 | |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 3034 | intel_crtc->dpms_mode = mode; |
Chris Wilson | debcadd | 2010-08-07 11:01:33 +0100 | [diff] [blame] | 3035 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3036 | dev_priv->display.dpms(crtc, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3037 | |
| 3038 | if (!dev->primary->master) |
| 3039 | return; |
| 3040 | |
| 3041 | master_priv = dev->primary->master->driver_priv; |
| 3042 | if (!master_priv->sarea_priv) |
| 3043 | return; |
| 3044 | |
| 3045 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; |
| 3046 | |
| 3047 | switch (pipe) { |
| 3048 | case 0: |
| 3049 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 3050 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 3051 | break; |
| 3052 | case 1: |
| 3053 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 3054 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 3055 | break; |
| 3056 | default: |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3057 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3058 | break; |
| 3059 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3060 | } |
| 3061 | |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3062 | static void intel_crtc_disable(struct drm_crtc *crtc) |
| 3063 | { |
| 3064 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 3065 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3066 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3067 | |
| 3068 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3069 | dev_priv->display.off(crtc); |
| 3070 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 3071 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
| 3072 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3073 | |
| 3074 | if (crtc->fb) { |
| 3075 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3076 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 3077 | mutex_unlock(&dev->struct_mutex); |
| 3078 | } |
| 3079 | } |
| 3080 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3081 | /* Prepare for a mode set. |
| 3082 | * |
| 3083 | * Note we could be a lot smarter here. We need to figure out which outputs |
| 3084 | * will be enabled, which disabled (in short, how the config will changes) |
| 3085 | * and perform the minimum necessary steps to accomplish that, e.g. updating |
| 3086 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, |
| 3087 | * panel fitting is in the proper state, etc. |
| 3088 | */ |
| 3089 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3090 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3091 | i9xx_crtc_disable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3092 | } |
| 3093 | |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3094 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3095 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3096 | i9xx_crtc_enable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3097 | } |
| 3098 | |
| 3099 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) |
| 3100 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3101 | ironlake_crtc_disable(crtc); |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3102 | } |
| 3103 | |
| 3104 | static void ironlake_crtc_commit(struct drm_crtc *crtc) |
| 3105 | { |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 3106 | ironlake_crtc_enable(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3107 | } |
| 3108 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3109 | void intel_encoder_prepare(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3110 | { |
| 3111 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 3112 | /* lvds has its own version of prepare see intel_lvds_prepare */ |
| 3113 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 3114 | } |
| 3115 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3116 | void intel_encoder_commit(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3117 | { |
| 3118 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3119 | struct drm_device *dev = encoder->dev; |
| 3120 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 3121 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
| 3122 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3123 | /* lvds has its own version of commit see intel_lvds_commit */ |
| 3124 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3125 | |
| 3126 | if (HAS_PCH_CPT(dev)) |
| 3127 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3128 | } |
| 3129 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3130 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 3131 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 3132 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3133 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3134 | drm_encoder_cleanup(encoder); |
| 3135 | kfree(intel_encoder); |
| 3136 | } |
| 3137 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3138 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
| 3139 | struct drm_display_mode *mode, |
| 3140 | struct drm_display_mode *adjusted_mode) |
| 3141 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3142 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3143 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 3144 | if (HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3145 | /* FDI link clock is fixed at 2.7G */ |
Jesse Barnes | 2377b74 | 2010-07-07 14:06:43 -0700 | [diff] [blame] | 3146 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
| 3147 | return false; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3148 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3149 | |
Daniel Vetter | ca9bfa7 | 2012-01-28 14:49:20 +0100 | [diff] [blame] | 3150 | /* All interlaced capable intel hw wants timings in frames. */ |
| 3151 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 3152 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3153 | return true; |
| 3154 | } |
| 3155 | |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 3156 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 3157 | { |
| 3158 | return 400000; /* FIXME */ |
| 3159 | } |
| 3160 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3161 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3162 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3163 | return 400000; |
| 3164 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3165 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3166 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 3167 | { |
| 3168 | return 333000; |
| 3169 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3170 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3171 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 3172 | { |
| 3173 | return 200000; |
| 3174 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3175 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3176 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 3177 | { |
| 3178 | u16 gcfgc = 0; |
| 3179 | |
| 3180 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 3181 | |
| 3182 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3183 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3184 | else { |
| 3185 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 3186 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 3187 | return 333000; |
| 3188 | default: |
| 3189 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 3190 | return 190000; |
| 3191 | } |
| 3192 | } |
| 3193 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3194 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 3195 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 3196 | { |
| 3197 | return 266000; |
| 3198 | } |
| 3199 | |
| 3200 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 3201 | { |
| 3202 | u16 hpllcc = 0; |
| 3203 | /* Assume that the hardware is in the high speed state. This |
| 3204 | * should be the default. |
| 3205 | */ |
| 3206 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 3207 | case GC_CLOCK_133_200: |
| 3208 | case GC_CLOCK_100_200: |
| 3209 | return 200000; |
| 3210 | case GC_CLOCK_166_250: |
| 3211 | return 250000; |
| 3212 | case GC_CLOCK_100_133: |
| 3213 | return 133000; |
| 3214 | } |
| 3215 | |
| 3216 | /* Shouldn't happen */ |
| 3217 | return 0; |
| 3218 | } |
| 3219 | |
| 3220 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 3221 | { |
| 3222 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3223 | } |
| 3224 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3225 | struct fdi_m_n { |
| 3226 | u32 tu; |
| 3227 | u32 gmch_m; |
| 3228 | u32 gmch_n; |
| 3229 | u32 link_m; |
| 3230 | u32 link_n; |
| 3231 | }; |
| 3232 | |
| 3233 | static void |
| 3234 | fdi_reduce_ratio(u32 *num, u32 *den) |
| 3235 | { |
| 3236 | while (*num > 0xffffff || *den > 0xffffff) { |
| 3237 | *num >>= 1; |
| 3238 | *den >>= 1; |
| 3239 | } |
| 3240 | } |
| 3241 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3242 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 3243 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
| 3244 | int link_clock, struct fdi_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3245 | { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3246 | m_n->tu = 64; /* default size */ |
| 3247 | |
Chris Wilson | 22ed111 | 2010-12-04 01:01:29 +0000 | [diff] [blame] | 3248 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
| 3249 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
| 3250 | m_n->gmch_n = link_clock * nlanes * 8; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3251 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 3252 | |
Chris Wilson | 22ed111 | 2010-12-04 01:01:29 +0000 | [diff] [blame] | 3253 | m_n->link_m = pixel_clock; |
| 3254 | m_n->link_n = link_clock; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3255 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 3256 | } |
| 3257 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 3258 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 3259 | { |
Keith Packard | 72bbe58 | 2011-09-26 16:09:45 -0700 | [diff] [blame] | 3260 | if (i915_panel_use_ssc >= 0) |
| 3261 | return i915_panel_use_ssc != 0; |
| 3262 | return dev_priv->lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 3263 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 3264 | } |
| 3265 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3266 | /** |
| 3267 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send |
| 3268 | * @crtc: CRTC structure |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 3269 | * @mode: requested mode |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3270 | * |
| 3271 | * A pipe may be connected to one or more outputs. Based on the depth of the |
| 3272 | * attached framebuffer, choose a good color depth to use on the pipe. |
| 3273 | * |
| 3274 | * If possible, match the pipe depth to the fb depth. In some cases, this |
| 3275 | * isn't ideal, because the connected output supports a lesser or restricted |
| 3276 | * set of depths. Resolve that here: |
| 3277 | * LVDS typically supports only 6bpc, so clamp down in that case |
| 3278 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc |
| 3279 | * Displays may support a restricted set as well, check EDID and clamp as |
| 3280 | * appropriate. |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 3281 | * DP may want to dither down to 6bpc to fit larger modes |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3282 | * |
| 3283 | * RETURNS: |
| 3284 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, |
| 3285 | * true if they don't match). |
| 3286 | */ |
| 3287 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 3288 | unsigned int *pipe_bpp, |
| 3289 | struct drm_display_mode *mode) |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3290 | { |
| 3291 | struct drm_device *dev = crtc->dev; |
| 3292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3293 | struct drm_encoder *encoder; |
| 3294 | struct drm_connector *connector; |
| 3295 | unsigned int display_bpc = UINT_MAX, bpc; |
| 3296 | |
| 3297 | /* Walk the encoders & connectors on this crtc, get min bpc */ |
| 3298 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 3299 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
| 3300 | |
| 3301 | if (encoder->crtc != crtc) |
| 3302 | continue; |
| 3303 | |
| 3304 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { |
| 3305 | unsigned int lvds_bpc; |
| 3306 | |
| 3307 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == |
| 3308 | LVDS_A3_POWER_UP) |
| 3309 | lvds_bpc = 8; |
| 3310 | else |
| 3311 | lvds_bpc = 6; |
| 3312 | |
| 3313 | if (lvds_bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3314 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3315 | display_bpc = lvds_bpc; |
| 3316 | } |
| 3317 | continue; |
| 3318 | } |
| 3319 | |
| 3320 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
| 3321 | /* Use VBT settings if we have an eDP panel */ |
| 3322 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; |
| 3323 | |
| 3324 | if (edp_bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3325 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3326 | display_bpc = edp_bpc; |
| 3327 | } |
| 3328 | continue; |
| 3329 | } |
| 3330 | |
| 3331 | /* Not one of the known troublemakers, check the EDID */ |
| 3332 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 3333 | head) { |
| 3334 | if (connector->encoder != encoder) |
| 3335 | continue; |
| 3336 | |
Jesse Barnes | 62ac41a | 2011-07-28 12:55:14 -0700 | [diff] [blame] | 3337 | /* Don't use an invalid EDID bpc value */ |
| 3338 | if (connector->display_info.bpc && |
| 3339 | connector->display_info.bpc < display_bpc) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3340 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3341 | display_bpc = connector->display_info.bpc; |
| 3342 | } |
| 3343 | } |
| 3344 | |
| 3345 | /* |
| 3346 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
| 3347 | * through, clamp it down. (Note: >12bpc will be caught below.) |
| 3348 | */ |
| 3349 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
| 3350 | if (display_bpc > 8 && display_bpc < 12) { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3351 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3352 | display_bpc = 12; |
| 3353 | } else { |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3354 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3355 | display_bpc = 8; |
| 3356 | } |
| 3357 | } |
| 3358 | } |
| 3359 | |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 3360 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
| 3361 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); |
| 3362 | display_bpc = 6; |
| 3363 | } |
| 3364 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3365 | /* |
| 3366 | * We could just drive the pipe at the highest bpc all the time and |
| 3367 | * enable dithering as needed, but that costs bandwidth. So choose |
| 3368 | * the minimum value that expresses the full color range of the fb but |
| 3369 | * also stays within the max display bpc discovered above. |
| 3370 | */ |
| 3371 | |
| 3372 | switch (crtc->fb->depth) { |
| 3373 | case 8: |
| 3374 | bpc = 8; /* since we go through a colormap */ |
| 3375 | break; |
| 3376 | case 15: |
| 3377 | case 16: |
| 3378 | bpc = 6; /* min is 18bpp */ |
| 3379 | break; |
| 3380 | case 24: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 3381 | bpc = 8; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3382 | break; |
| 3383 | case 30: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 3384 | bpc = 10; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3385 | break; |
| 3386 | case 48: |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 3387 | bpc = 12; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3388 | break; |
| 3389 | default: |
| 3390 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); |
| 3391 | bpc = min((unsigned int)8, display_bpc); |
| 3392 | break; |
| 3393 | } |
| 3394 | |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 3395 | display_bpc = min(display_bpc, bpc); |
| 3396 | |
Adam Jackson | 8282049 | 2011-10-10 16:33:34 -0400 | [diff] [blame] | 3397 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
| 3398 | bpc, display_bpc); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3399 | |
Keith Packard | 578393c | 2011-09-05 11:53:21 -0700 | [diff] [blame] | 3400 | *pipe_bpp = display_bpc * 3; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 3401 | |
| 3402 | return display_bpc != bpc; |
| 3403 | } |
| 3404 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 3405 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
| 3406 | { |
| 3407 | struct drm_device *dev = crtc->dev; |
| 3408 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3409 | int refclk; |
| 3410 | |
| 3411 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 3412 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 3413 | refclk = dev_priv->lvds_ssc_freq * 1000; |
| 3414 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 3415 | refclk / 1000); |
| 3416 | } else if (!IS_GEN2(dev)) { |
| 3417 | refclk = 96000; |
| 3418 | } else { |
| 3419 | refclk = 48000; |
| 3420 | } |
| 3421 | |
| 3422 | return refclk; |
| 3423 | } |
| 3424 | |
| 3425 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, |
| 3426 | intel_clock_t *clock) |
| 3427 | { |
| 3428 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 3429 | this mirrors vbios setting. */ |
| 3430 | if (adjusted_mode->clock >= 100000 |
| 3431 | && adjusted_mode->clock < 140500) { |
| 3432 | clock->p1 = 2; |
| 3433 | clock->p2 = 10; |
| 3434 | clock->n = 3; |
| 3435 | clock->m1 = 16; |
| 3436 | clock->m2 = 8; |
| 3437 | } else if (adjusted_mode->clock >= 140500 |
| 3438 | && adjusted_mode->clock <= 200000) { |
| 3439 | clock->p1 = 1; |
| 3440 | clock->p2 = 10; |
| 3441 | clock->n = 6; |
| 3442 | clock->m1 = 12; |
| 3443 | clock->m2 = 8; |
| 3444 | } |
| 3445 | } |
| 3446 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 3447 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
| 3448 | intel_clock_t *clock, |
| 3449 | intel_clock_t *reduced_clock) |
| 3450 | { |
| 3451 | struct drm_device *dev = crtc->dev; |
| 3452 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3454 | int pipe = intel_crtc->pipe; |
| 3455 | u32 fp, fp2 = 0; |
| 3456 | |
| 3457 | if (IS_PINEVIEW(dev)) { |
| 3458 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; |
| 3459 | if (reduced_clock) |
| 3460 | fp2 = (1 << reduced_clock->n) << 16 | |
| 3461 | reduced_clock->m1 << 8 | reduced_clock->m2; |
| 3462 | } else { |
| 3463 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; |
| 3464 | if (reduced_clock) |
| 3465 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | |
| 3466 | reduced_clock->m2; |
| 3467 | } |
| 3468 | |
| 3469 | I915_WRITE(FP0(pipe), fp); |
| 3470 | |
| 3471 | intel_crtc->lowfreq_avail = false; |
| 3472 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 3473 | reduced_clock && i915_powersave) { |
| 3474 | I915_WRITE(FP1(pipe), fp2); |
| 3475 | intel_crtc->lowfreq_avail = true; |
| 3476 | } else { |
| 3477 | I915_WRITE(FP1(pipe), fp); |
| 3478 | } |
| 3479 | } |
| 3480 | |
Daniel Vetter | 93e537a | 2012-03-28 23:11:26 +0200 | [diff] [blame] | 3481 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
| 3482 | struct drm_display_mode *adjusted_mode) |
| 3483 | { |
| 3484 | struct drm_device *dev = crtc->dev; |
| 3485 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3487 | int pipe = intel_crtc->pipe; |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 3488 | u32 temp; |
Daniel Vetter | 93e537a | 2012-03-28 23:11:26 +0200 | [diff] [blame] | 3489 | |
| 3490 | temp = I915_READ(LVDS); |
| 3491 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
| 3492 | if (pipe == 1) { |
| 3493 | temp |= LVDS_PIPEB_SELECT; |
| 3494 | } else { |
| 3495 | temp &= ~LVDS_PIPEB_SELECT; |
| 3496 | } |
| 3497 | /* set the corresponsding LVDS_BORDER bit */ |
| 3498 | temp |= dev_priv->lvds_border_bits; |
| 3499 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 3500 | * set the DPLLs for dual-channel mode or not. |
| 3501 | */ |
| 3502 | if (clock->p2 == 7) |
| 3503 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 3504 | else |
| 3505 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 3506 | |
| 3507 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 3508 | * appropriately here, but we need to look more thoroughly into how |
| 3509 | * panels behave in the two modes. |
| 3510 | */ |
| 3511 | /* set the dithering flag on LVDS as needed */ |
| 3512 | if (INTEL_INFO(dev)->gen >= 4) { |
| 3513 | if (dev_priv->lvds_dither) |
| 3514 | temp |= LVDS_ENABLE_DITHER; |
| 3515 | else |
| 3516 | temp &= ~LVDS_ENABLE_DITHER; |
| 3517 | } |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 3518 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
Daniel Vetter | 93e537a | 2012-03-28 23:11:26 +0200 | [diff] [blame] | 3519 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 3520 | temp |= LVDS_HSYNC_POLARITY; |
Daniel Vetter | 93e537a | 2012-03-28 23:11:26 +0200 | [diff] [blame] | 3521 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 3522 | temp |= LVDS_VSYNC_POLARITY; |
Daniel Vetter | 93e537a | 2012-03-28 23:11:26 +0200 | [diff] [blame] | 3523 | I915_WRITE(LVDS, temp); |
| 3524 | } |
| 3525 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 3526 | static void i9xx_update_pll(struct drm_crtc *crtc, |
| 3527 | struct drm_display_mode *mode, |
| 3528 | struct drm_display_mode *adjusted_mode, |
| 3529 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
| 3530 | int num_connectors) |
| 3531 | { |
| 3532 | struct drm_device *dev = crtc->dev; |
| 3533 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3534 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3535 | int pipe = intel_crtc->pipe; |
| 3536 | u32 dpll; |
| 3537 | bool is_sdvo; |
| 3538 | |
| 3539 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
| 3540 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); |
| 3541 | |
| 3542 | dpll = DPLL_VGA_MODE_DIS; |
| 3543 | |
| 3544 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 3545 | dpll |= DPLLB_MODE_LVDS; |
| 3546 | else |
| 3547 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 3548 | if (is_sdvo) { |
| 3549 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 3550 | if (pixel_multiplier > 1) { |
| 3551 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 3552 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
| 3553 | } |
| 3554 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 3555 | } |
| 3556 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 3557 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 3558 | |
| 3559 | /* compute bitmask from p1 value */ |
| 3560 | if (IS_PINEVIEW(dev)) |
| 3561 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 3562 | else { |
| 3563 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3564 | if (IS_G4X(dev) && reduced_clock) |
| 3565 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 3566 | } |
| 3567 | switch (clock->p2) { |
| 3568 | case 5: |
| 3569 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 3570 | break; |
| 3571 | case 7: |
| 3572 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 3573 | break; |
| 3574 | case 10: |
| 3575 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 3576 | break; |
| 3577 | case 14: |
| 3578 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 3579 | break; |
| 3580 | } |
| 3581 | if (INTEL_INFO(dev)->gen >= 4) |
| 3582 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 3583 | |
| 3584 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
| 3585 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 3586 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
| 3587 | /* XXX: just matching BIOS for now */ |
| 3588 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 3589 | dpll |= 3; |
| 3590 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 3591 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 3592 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 3593 | else |
| 3594 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 3595 | |
| 3596 | dpll |= DPLL_VCO_ENABLE; |
| 3597 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
| 3598 | POSTING_READ(DPLL(pipe)); |
| 3599 | udelay(150); |
| 3600 | |
| 3601 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 3602 | * This is an exception to the general rule that mode_set doesn't turn |
| 3603 | * things on. |
| 3604 | */ |
| 3605 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 3606 | intel_update_lvds(crtc, clock, adjusted_mode); |
| 3607 | |
| 3608 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 3609 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
| 3610 | |
| 3611 | I915_WRITE(DPLL(pipe), dpll); |
| 3612 | |
| 3613 | /* Wait for the clocks to stabilize. */ |
| 3614 | POSTING_READ(DPLL(pipe)); |
| 3615 | udelay(150); |
| 3616 | |
| 3617 | if (INTEL_INFO(dev)->gen >= 4) { |
| 3618 | u32 temp = 0; |
| 3619 | if (is_sdvo) { |
| 3620 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 3621 | if (temp > 1) |
| 3622 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
| 3623 | else |
| 3624 | temp = 0; |
| 3625 | } |
| 3626 | I915_WRITE(DPLL_MD(pipe), temp); |
| 3627 | } else { |
| 3628 | /* The pixel multiplier can only be updated once the |
| 3629 | * DPLL is enabled and the clocks are stable. |
| 3630 | * |
| 3631 | * So write it again. |
| 3632 | */ |
| 3633 | I915_WRITE(DPLL(pipe), dpll); |
| 3634 | } |
| 3635 | } |
| 3636 | |
| 3637 | static void i8xx_update_pll(struct drm_crtc *crtc, |
| 3638 | struct drm_display_mode *adjusted_mode, |
| 3639 | intel_clock_t *clock, |
| 3640 | int num_connectors) |
| 3641 | { |
| 3642 | struct drm_device *dev = crtc->dev; |
| 3643 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3645 | int pipe = intel_crtc->pipe; |
| 3646 | u32 dpll; |
| 3647 | |
| 3648 | dpll = DPLL_VGA_MODE_DIS; |
| 3649 | |
| 3650 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 3651 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3652 | } else { |
| 3653 | if (clock->p1 == 2) |
| 3654 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 3655 | else |
| 3656 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 3657 | if (clock->p2 == 4) |
| 3658 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 3659 | } |
| 3660 | |
| 3661 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) |
| 3662 | /* XXX: just matching BIOS for now */ |
| 3663 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 3664 | dpll |= 3; |
| 3665 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 3666 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 3667 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 3668 | else |
| 3669 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 3670 | |
| 3671 | dpll |= DPLL_VCO_ENABLE; |
| 3672 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
| 3673 | POSTING_READ(DPLL(pipe)); |
| 3674 | udelay(150); |
| 3675 | |
| 3676 | I915_WRITE(DPLL(pipe), dpll); |
| 3677 | |
| 3678 | /* Wait for the clocks to stabilize. */ |
| 3679 | POSTING_READ(DPLL(pipe)); |
| 3680 | udelay(150); |
| 3681 | |
| 3682 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 3683 | * This is an exception to the general rule that mode_set doesn't turn |
| 3684 | * things on. |
| 3685 | */ |
| 3686 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 3687 | intel_update_lvds(crtc, clock, adjusted_mode); |
| 3688 | |
| 3689 | /* The pixel multiplier can only be updated once the |
| 3690 | * DPLL is enabled and the clocks are stable. |
| 3691 | * |
| 3692 | * So write it again. |
| 3693 | */ |
| 3694 | I915_WRITE(DPLL(pipe), dpll); |
| 3695 | } |
| 3696 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3697 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
| 3698 | struct drm_display_mode *mode, |
| 3699 | struct drm_display_mode *adjusted_mode, |
| 3700 | int x, int y, |
| 3701 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3702 | { |
| 3703 | struct drm_device *dev = crtc->dev; |
| 3704 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3706 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 3707 | int plane = intel_crtc->plane; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3708 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3709 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 3710 | u32 dspcntr, pipeconf, vsyncshift; |
| 3711 | bool ok, has_reduced_clock = false, is_sdvo = false; |
| 3712 | bool is_lvds = false, is_tv = false, is_dp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3713 | struct drm_mode_config *mode_config = &dev->mode_config; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3714 | struct intel_encoder *encoder; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3715 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 3716 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3717 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3718 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 3719 | if (encoder->base.crtc != crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3720 | continue; |
| 3721 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3722 | switch (encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3723 | case INTEL_OUTPUT_LVDS: |
| 3724 | is_lvds = true; |
| 3725 | break; |
| 3726 | case INTEL_OUTPUT_SDVO: |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 3727 | case INTEL_OUTPUT_HDMI: |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3728 | is_sdvo = true; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3729 | if (encoder->needs_tv_clock) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 3730 | is_tv = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3731 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3732 | case INTEL_OUTPUT_TVOUT: |
| 3733 | is_tv = true; |
| 3734 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3735 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3736 | is_dp = true; |
| 3737 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3738 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 3739 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 3740 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3741 | } |
| 3742 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 3743 | refclk = i9xx_get_refclk(crtc, num_connectors); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3744 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 3745 | /* |
| 3746 | * Returns a set of divisors for the desired target clock with the given |
| 3747 | * refclk, or FALSE. The returned values represent the clock equation: |
| 3748 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 3749 | */ |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 3750 | limit = intel_limit(crtc, refclk); |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 3751 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
| 3752 | &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3753 | if (!ok) { |
| 3754 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3755 | return -EINVAL; |
| 3756 | } |
| 3757 | |
| 3758 | /* Ensure that the cursor is valid for the new mode before changing... */ |
| 3759 | intel_crtc_update_cursor(crtc, true); |
| 3760 | |
| 3761 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 3762 | /* |
| 3763 | * Ensure we match the reduced clock's P to the target clock. |
| 3764 | * If the clocks don't match, we can't switch the display clock |
| 3765 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 3766 | * downclock feature. |
| 3767 | */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3768 | has_reduced_clock = limit->find_pll(limit, crtc, |
| 3769 | dev_priv->lvds_downclock, |
| 3770 | refclk, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 3771 | &clock, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3772 | &reduced_clock); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3773 | } |
| 3774 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 3775 | if (is_sdvo && is_tv) |
| 3776 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3777 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 3778 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
| 3779 | &reduced_clock : NULL); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3780 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 3781 | if (IS_GEN2(dev)) |
| 3782 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3783 | else |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 3784 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
| 3785 | has_reduced_clock ? &reduced_clock : NULL, |
| 3786 | num_connectors); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3787 | |
| 3788 | /* setup pipeconf */ |
| 3789 | pipeconf = I915_READ(PIPECONF(pipe)); |
| 3790 | |
| 3791 | /* Set up the display plane register */ |
| 3792 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 3793 | |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 3794 | if (pipe == 0) |
| 3795 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
| 3796 | else |
| 3797 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3798 | |
| 3799 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
| 3800 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
| 3801 | * core speed. |
| 3802 | * |
| 3803 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the |
| 3804 | * pipe == 0 check? |
| 3805 | */ |
| 3806 | if (mode->clock > |
| 3807 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) |
| 3808 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
| 3809 | else |
| 3810 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
| 3811 | } |
| 3812 | |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 3813 | /* default to 8bpc */ |
| 3814 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); |
| 3815 | if (is_dp) { |
| 3816 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
| 3817 | pipeconf |= PIPECONF_BPP_6 | |
| 3818 | PIPECONF_DITHER_EN | |
| 3819 | PIPECONF_DITHER_TYPE_SP; |
| 3820 | } |
| 3821 | } |
| 3822 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3823 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
| 3824 | drm_mode_debug_printmodeline(mode); |
| 3825 | |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 3826 | if (HAS_PIPE_CXSR(dev)) { |
| 3827 | if (intel_crtc->lowfreq_avail) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3828 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 3829 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 3830 | } else { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3831 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 3832 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 3833 | } |
| 3834 | } |
| 3835 | |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 3836 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 3837 | if (!IS_GEN2(dev) && |
| 3838 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3839 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 3840 | /* the chip adds 2 halflines automatically */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3841 | adjusted_mode->crtc_vtotal -= 1; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3842 | adjusted_mode->crtc_vblank_end -= 1; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 3843 | vsyncshift = adjusted_mode->crtc_hsync_start |
| 3844 | - adjusted_mode->crtc_htotal/2; |
| 3845 | } else { |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 3846 | pipeconf |= PIPECONF_PROGRESSIVE; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 3847 | vsyncshift = 0; |
| 3848 | } |
| 3849 | |
| 3850 | if (!IS_GEN3(dev)) |
| 3851 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3852 | |
| 3853 | I915_WRITE(HTOTAL(pipe), |
| 3854 | (adjusted_mode->crtc_hdisplay - 1) | |
| 3855 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 3856 | I915_WRITE(HBLANK(pipe), |
| 3857 | (adjusted_mode->crtc_hblank_start - 1) | |
| 3858 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 3859 | I915_WRITE(HSYNC(pipe), |
| 3860 | (adjusted_mode->crtc_hsync_start - 1) | |
| 3861 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 3862 | |
| 3863 | I915_WRITE(VTOTAL(pipe), |
| 3864 | (adjusted_mode->crtc_vdisplay - 1) | |
| 3865 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
| 3866 | I915_WRITE(VBLANK(pipe), |
| 3867 | (adjusted_mode->crtc_vblank_start - 1) | |
| 3868 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
| 3869 | I915_WRITE(VSYNC(pipe), |
| 3870 | (adjusted_mode->crtc_vsync_start - 1) | |
| 3871 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 3872 | |
| 3873 | /* pipesrc and dspsize control the size that is scaled from, |
| 3874 | * which should always be the user's requested size. |
| 3875 | */ |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 3876 | I915_WRITE(DSPSIZE(plane), |
| 3877 | ((mode->vdisplay - 1) << 16) | |
| 3878 | (mode->hdisplay - 1)); |
| 3879 | I915_WRITE(DSPPOS(plane), 0); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3880 | I915_WRITE(PIPESRC(pipe), |
| 3881 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
| 3882 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3883 | I915_WRITE(PIPECONF(pipe), pipeconf); |
| 3884 | POSTING_READ(PIPECONF(pipe)); |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 3885 | intel_enable_pipe(dev_priv, pipe, false); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3886 | |
| 3887 | intel_wait_for_vblank(dev, pipe); |
| 3888 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3889 | I915_WRITE(DSPCNTR(plane), dspcntr); |
| 3890 | POSTING_READ(DSPCNTR(plane)); |
| 3891 | |
| 3892 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
| 3893 | |
| 3894 | intel_update_watermarks(dev); |
| 3895 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 3896 | return ret; |
| 3897 | } |
| 3898 | |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 3899 | /* |
| 3900 | * Initialize reference clocks when the driver loads |
| 3901 | */ |
| 3902 | void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3903 | { |
| 3904 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3905 | struct drm_mode_config *mode_config = &dev->mode_config; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3906 | struct intel_encoder *encoder; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3907 | u32 temp; |
| 3908 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3909 | bool has_cpu_edp = false; |
| 3910 | bool has_pch_edp = false; |
| 3911 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 3912 | bool has_ck505 = false; |
| 3913 | bool can_ssc = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3914 | |
| 3915 | /* We need to take the global config into account */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3916 | list_for_each_entry(encoder, &mode_config->encoder_list, |
| 3917 | base.head) { |
| 3918 | switch (encoder->type) { |
| 3919 | case INTEL_OUTPUT_LVDS: |
| 3920 | has_panel = true; |
| 3921 | has_lvds = true; |
| 3922 | break; |
| 3923 | case INTEL_OUTPUT_EDP: |
| 3924 | has_panel = true; |
| 3925 | if (intel_encoder_is_pch_edp(&encoder->base)) |
| 3926 | has_pch_edp = true; |
| 3927 | else |
| 3928 | has_cpu_edp = true; |
| 3929 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3930 | } |
| 3931 | } |
| 3932 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 3933 | if (HAS_PCH_IBX(dev)) { |
| 3934 | has_ck505 = dev_priv->display_clock_mode; |
| 3935 | can_ssc = has_ck505; |
| 3936 | } else { |
| 3937 | has_ck505 = false; |
| 3938 | can_ssc = true; |
| 3939 | } |
| 3940 | |
| 3941 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", |
| 3942 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, |
| 3943 | has_ck505); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3944 | |
| 3945 | /* Ironlake: try to setup display ref clock before DPLL |
| 3946 | * enabling. This is only under driver's control after |
| 3947 | * PCH B stepping, previous chipset stepping should be |
| 3948 | * ignoring this setting. |
| 3949 | */ |
| 3950 | temp = I915_READ(PCH_DREF_CONTROL); |
| 3951 | /* Always enable nonspread source */ |
| 3952 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3953 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 3954 | if (has_ck505) |
| 3955 | temp |= DREF_NONSPREAD_CK505_ENABLE; |
| 3956 | else |
| 3957 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3958 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3959 | if (has_panel) { |
| 3960 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 3961 | temp |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3962 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3963 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 3964 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3965 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3966 | temp |= DREF_SSC1_ENABLE; |
Daniel Vetter | e77166b | 2012-03-30 22:14:05 +0200 | [diff] [blame] | 3967 | } else |
| 3968 | temp &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3969 | |
| 3970 | /* Get SSC going before enabling the outputs */ |
| 3971 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3972 | POSTING_READ(PCH_DREF_CONTROL); |
| 3973 | udelay(200); |
| 3974 | |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3975 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 3976 | |
| 3977 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3978 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 3979 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3980 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3981 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3982 | } |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 3983 | else |
| 3984 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 3985 | } else |
| 3986 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 3987 | |
| 3988 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 3989 | POSTING_READ(PCH_DREF_CONTROL); |
| 3990 | udelay(200); |
| 3991 | } else { |
| 3992 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 3993 | |
| 3994 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 3995 | |
| 3996 | /* Turn off CPU output */ |
| 3997 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 3998 | |
| 3999 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 4000 | POSTING_READ(PCH_DREF_CONTROL); |
| 4001 | udelay(200); |
| 4002 | |
| 4003 | /* Turn off the SSC source */ |
| 4004 | temp &= ~DREF_SSC_SOURCE_MASK; |
| 4005 | temp |= DREF_SSC_SOURCE_DISABLE; |
| 4006 | |
| 4007 | /* Turn off SSC1 */ |
| 4008 | temp &= ~ DREF_SSC1_ENABLE; |
| 4009 | |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 4010 | I915_WRITE(PCH_DREF_CONTROL, temp); |
| 4011 | POSTING_READ(PCH_DREF_CONTROL); |
| 4012 | udelay(200); |
| 4013 | } |
| 4014 | } |
| 4015 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 4016 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
| 4017 | { |
| 4018 | struct drm_device *dev = crtc->dev; |
| 4019 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4020 | struct intel_encoder *encoder; |
| 4021 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 4022 | struct intel_encoder *edp_encoder = NULL; |
| 4023 | int num_connectors = 0; |
| 4024 | bool is_lvds = false; |
| 4025 | |
| 4026 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 4027 | if (encoder->base.crtc != crtc) |
| 4028 | continue; |
| 4029 | |
| 4030 | switch (encoder->type) { |
| 4031 | case INTEL_OUTPUT_LVDS: |
| 4032 | is_lvds = true; |
| 4033 | break; |
| 4034 | case INTEL_OUTPUT_EDP: |
| 4035 | edp_encoder = encoder; |
| 4036 | break; |
| 4037 | } |
| 4038 | num_connectors++; |
| 4039 | } |
| 4040 | |
| 4041 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
| 4042 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
| 4043 | dev_priv->lvds_ssc_freq); |
| 4044 | return dev_priv->lvds_ssc_freq * 1000; |
| 4045 | } |
| 4046 | |
| 4047 | return 120000; |
| 4048 | } |
| 4049 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 4050 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
| 4051 | struct drm_display_mode *mode, |
| 4052 | struct drm_display_mode *adjusted_mode, |
| 4053 | int x, int y, |
| 4054 | struct drm_framebuffer *old_fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4055 | { |
| 4056 | struct drm_device *dev = crtc->dev; |
| 4057 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4058 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4059 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4060 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4061 | int refclk, num_connectors = 0; |
| 4062 | intel_clock_t clock, reduced_clock; |
| 4063 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4064 | bool ok, has_reduced_clock = false, is_sdvo = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4065 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4066 | struct drm_mode_config *mode_config = &dev->mode_config; |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4067 | struct intel_encoder *encoder, *edp_encoder = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4068 | const intel_limit_t *limit; |
| 4069 | int ret; |
| 4070 | struct fdi_m_n m_n = {0}; |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 4071 | u32 temp; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4072 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
| 4073 | unsigned int pipe_bpp; |
| 4074 | bool dither; |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4075 | bool is_cpu_edp = false, is_pch_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4076 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4077 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 4078 | if (encoder->base.crtc != crtc) |
| 4079 | continue; |
| 4080 | |
| 4081 | switch (encoder->type) { |
| 4082 | case INTEL_OUTPUT_LVDS: |
| 4083 | is_lvds = true; |
| 4084 | break; |
| 4085 | case INTEL_OUTPUT_SDVO: |
| 4086 | case INTEL_OUTPUT_HDMI: |
| 4087 | is_sdvo = true; |
| 4088 | if (encoder->needs_tv_clock) |
| 4089 | is_tv = true; |
| 4090 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4091 | case INTEL_OUTPUT_TVOUT: |
| 4092 | is_tv = true; |
| 4093 | break; |
| 4094 | case INTEL_OUTPUT_ANALOG: |
| 4095 | is_crt = true; |
| 4096 | break; |
| 4097 | case INTEL_OUTPUT_DISPLAYPORT: |
| 4098 | is_dp = true; |
| 4099 | break; |
| 4100 | case INTEL_OUTPUT_EDP: |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4101 | is_dp = true; |
| 4102 | if (intel_encoder_is_pch_edp(&encoder->base)) |
| 4103 | is_pch_edp = true; |
| 4104 | else |
| 4105 | is_cpu_edp = true; |
| 4106 | edp_encoder = encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4107 | break; |
| 4108 | } |
| 4109 | |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 4110 | num_connectors++; |
| 4111 | } |
| 4112 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 4113 | refclk = ironlake_get_refclk(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4114 | |
| 4115 | /* |
| 4116 | * Returns a set of divisors for the desired target clock with the given |
| 4117 | * refclk, or FALSE. The returned values represent the clock equation: |
| 4118 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 4119 | */ |
| 4120 | limit = intel_limit(crtc, refclk); |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 4121 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
| 4122 | &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4123 | if (!ok) { |
| 4124 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 4125 | return -EINVAL; |
| 4126 | } |
| 4127 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4128 | /* Ensure that the cursor is valid for the new mode before changing... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4129 | intel_crtc_update_cursor(crtc, true); |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4130 | |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 4131 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 4132 | /* |
| 4133 | * Ensure we match the reduced clock's P to the target clock. |
| 4134 | * If the clocks don't match, we can't switch the display clock |
| 4135 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 4136 | * downclock feature. |
| 4137 | */ |
Zhao Yakui | ddc9003 | 2010-01-06 22:05:56 +0800 | [diff] [blame] | 4138 | has_reduced_clock = limit->find_pll(limit, crtc, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4139 | dev_priv->lvds_downclock, |
| 4140 | refclk, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 4141 | &clock, |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4142 | &reduced_clock); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4143 | } |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 4144 | /* SDVO TV has fixed PLL values depend on its clock range, |
| 4145 | this mirrors vbios setting. */ |
| 4146 | if (is_sdvo && is_tv) { |
| 4147 | if (adjusted_mode->clock >= 100000 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4148 | && adjusted_mode->clock < 140500) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 4149 | clock.p1 = 2; |
| 4150 | clock.p2 = 10; |
| 4151 | clock.n = 3; |
| 4152 | clock.m1 = 16; |
| 4153 | clock.m2 = 8; |
| 4154 | } else if (adjusted_mode->clock >= 140500 |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4155 | && adjusted_mode->clock <= 200000) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 4156 | clock.p1 = 1; |
| 4157 | clock.p2 = 10; |
| 4158 | clock.n = 6; |
| 4159 | clock.m1 = 12; |
| 4160 | clock.m2 = 8; |
| 4161 | } |
| 4162 | } |
| 4163 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4164 | /* FDI link */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4165 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 4166 | lane = 0; |
| 4167 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
| 4168 | according to current link config */ |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4169 | if (is_cpu_edp) { |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4170 | target_clock = mode->clock; |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4171 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4172 | } else { |
| 4173 | /* [e]DP over FDI requires target mode clock |
| 4174 | instead of link clock */ |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4175 | if (is_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4176 | target_clock = mode->clock; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4177 | else |
| 4178 | target_clock = adjusted_mode->clock; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 4179 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4180 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 4181 | * each output octet as 10 bits. The actual frequency |
| 4182 | * is stored as a divider into a 100MHz clock, and the |
| 4183 | * mode pixel clock is stored in units of 1KHz. |
| 4184 | * Hence the bw of each lane in terms of the mode signal |
| 4185 | * is: |
| 4186 | */ |
| 4187 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4188 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4189 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4190 | /* determine panel color depth */ |
| 4191 | temp = I915_READ(PIPECONF(pipe)); |
| 4192 | temp &= ~PIPE_BPC_MASK; |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 4193 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4194 | switch (pipe_bpp) { |
| 4195 | case 18: |
| 4196 | temp |= PIPE_6BPC; |
| 4197 | break; |
| 4198 | case 24: |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4199 | temp |= PIPE_8BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4200 | break; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4201 | case 30: |
| 4202 | temp |= PIPE_10BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4203 | break; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4204 | case 36: |
| 4205 | temp |= PIPE_12BPC; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4206 | break; |
| 4207 | default: |
Jesse Barnes | 62ac41a | 2011-07-28 12:55:14 -0700 | [diff] [blame] | 4208 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
| 4209 | pipe_bpp); |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4210 | temp |= PIPE_8BPC; |
| 4211 | pipe_bpp = 24; |
| 4212 | break; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4213 | } |
| 4214 | |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4215 | intel_crtc->bpp = pipe_bpp; |
| 4216 | I915_WRITE(PIPECONF(pipe), temp); |
| 4217 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4218 | if (!lane) { |
| 4219 | /* |
| 4220 | * Account for spread spectrum to avoid |
| 4221 | * oversubscribing the link. Max center spread |
| 4222 | * is 2.5%; use 5% for safety's sake. |
| 4223 | */ |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4224 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4225 | lane = bps / (link_bw * 8) + 1; |
| 4226 | } |
| 4227 | |
| 4228 | intel_crtc->fdi_lanes = lane; |
| 4229 | |
| 4230 | if (pixel_multiplier > 1) |
| 4231 | link_bw *= pixel_multiplier; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4232 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
| 4233 | &m_n); |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4234 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4235 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
| 4236 | if (has_reduced_clock) |
| 4237 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | |
| 4238 | reduced_clock.m2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4239 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 4240 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4241 | factor = 21; |
| 4242 | if (is_lvds) { |
| 4243 | if ((intel_panel_use_ssc(dev_priv) && |
| 4244 | dev_priv->lvds_ssc_freq == 100) || |
| 4245 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) |
| 4246 | factor = 25; |
| 4247 | } else if (is_sdvo && is_tv) |
| 4248 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 4249 | |
Jesse Barnes | cb0e093 | 2011-07-28 14:50:30 -0700 | [diff] [blame] | 4250 | if (clock.m < factor * clock.n) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4251 | fp |= FP_CB_TUNE; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 4252 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4253 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4254 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4255 | if (is_lvds) |
| 4256 | dpll |= DPLLB_MODE_LVDS; |
| 4257 | else |
| 4258 | dpll |= DPLLB_MODE_DAC_SERIAL; |
| 4259 | if (is_sdvo) { |
| 4260 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 4261 | if (pixel_multiplier > 1) { |
| 4262 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4263 | } |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4264 | dpll |= DPLL_DVO_HIGH_SPEED; |
| 4265 | } |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4266 | if (is_dp && !is_cpu_edp) |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4267 | dpll |= DPLL_DVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4268 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 4269 | /* compute bitmask from p1 value */ |
| 4270 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 4271 | /* also FPA1 */ |
| 4272 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 4273 | |
| 4274 | switch (clock.p2) { |
| 4275 | case 5: |
| 4276 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 4277 | break; |
| 4278 | case 7: |
| 4279 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 4280 | break; |
| 4281 | case 10: |
| 4282 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 4283 | break; |
| 4284 | case 14: |
| 4285 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 4286 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4287 | } |
| 4288 | |
| 4289 | if (is_sdvo && is_tv) |
| 4290 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
| 4291 | else if (is_tv) |
| 4292 | /* XXX: just matching BIOS for now */ |
| 4293 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 4294 | dpll |= 3; |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 4295 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4296 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 4297 | else |
| 4298 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 4299 | |
| 4300 | /* setup pipeconf */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4301 | pipeconf = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4302 | |
| 4303 | /* Set up the display plane register */ |
| 4304 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 4305 | |
Jesse Barnes | f7cb34d | 2011-10-12 10:49:14 -0700 | [diff] [blame] | 4306 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4307 | drm_mode_debug_printmodeline(mode); |
| 4308 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4309 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own */ |
| 4310 | if (!is_cpu_edp) { |
| 4311 | struct intel_pch_pll *pll; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4312 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4313 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
| 4314 | if (pll == NULL) { |
| 4315 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", |
| 4316 | pipe); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4317 | return -EINVAL; |
| 4318 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4319 | } else |
| 4320 | intel_put_pch_pll(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4321 | |
| 4322 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 4323 | * This is an exception to the general rule that mode_set doesn't turn |
| 4324 | * things on. |
| 4325 | */ |
| 4326 | if (is_lvds) { |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 4327 | temp = I915_READ(PCH_LVDS); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4328 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
Jesse Barnes | 7885d20 | 2012-01-12 14:51:17 -0800 | [diff] [blame] | 4329 | if (HAS_PCH_CPT(dev)) { |
| 4330 | temp &= ~PORT_TRANS_SEL_MASK; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4331 | temp |= PORT_TRANS_SEL_CPT(pipe); |
Jesse Barnes | 7885d20 | 2012-01-12 14:51:17 -0800 | [diff] [blame] | 4332 | } else { |
| 4333 | if (pipe == 1) |
| 4334 | temp |= LVDS_PIPEB_SELECT; |
| 4335 | else |
| 4336 | temp &= ~LVDS_PIPEB_SELECT; |
| 4337 | } |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4338 | |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 4339 | /* set the corresponsding LVDS_BORDER bit */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4340 | temp |= dev_priv->lvds_border_bits; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4341 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
| 4342 | * set the DPLLs for dual-channel mode or not. |
| 4343 | */ |
| 4344 | if (clock.p2 == 7) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4345 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4346 | else |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4347 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4348 | |
| 4349 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 4350 | * appropriately here, but we need to look more thoroughly into how |
| 4351 | * panels behave in the two modes. |
| 4352 | */ |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 4353 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
Bryan Freed | aa9b500 | 2011-01-12 13:43:19 -0800 | [diff] [blame] | 4354 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 4355 | temp |= LVDS_HSYNC_POLARITY; |
Bryan Freed | aa9b500 | 2011-01-12 13:43:19 -0800 | [diff] [blame] | 4356 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
Chris Wilson | 284d5df | 2012-04-14 17:41:59 +0100 | [diff] [blame] | 4357 | temp |= LVDS_VSYNC_POLARITY; |
Eric Anholt | fae1498 | 2011-03-30 13:01:09 -0700 | [diff] [blame] | 4358 | I915_WRITE(PCH_LVDS, temp); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4359 | } |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 4360 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4361 | pipeconf &= ~PIPECONF_DITHER_EN; |
| 4362 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 4363 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4364 | pipeconf |= PIPECONF_DITHER_EN; |
Daniel Vetter | f74974c | 2011-10-11 17:27:51 +0200 | [diff] [blame] | 4365 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
Jesse Barnes | 434ed09 | 2010-09-07 14:48:06 -0700 | [diff] [blame] | 4366 | } |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4367 | if (is_dp && !is_cpu_edp) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4368 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4369 | } else { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4370 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4371 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
| 4372 | I915_WRITE(TRANSDATA_N1(pipe), 0); |
| 4373 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); |
| 4374 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 4375 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4376 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4377 | if (intel_crtc->pch_pll) { |
| 4378 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4379 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4380 | /* Wait for the clocks to stabilize. */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4381 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4382 | udelay(150); |
| 4383 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4384 | /* The pixel multiplier can only be updated once the |
| 4385 | * DPLL is enabled and the clocks are stable. |
| 4386 | * |
| 4387 | * So write it again. |
| 4388 | */ |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4389 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4390 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4391 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4392 | intel_crtc->lowfreq_avail = false; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4393 | if (intel_crtc->pch_pll) { |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4394 | if (is_lvds && has_reduced_clock && i915_powersave) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4395 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4396 | intel_crtc->lowfreq_avail = true; |
| 4397 | if (HAS_PIPE_CXSR(dev)) { |
| 4398 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 4399 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 4400 | } |
| 4401 | } else { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4402 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 4403 | if (HAS_PIPE_CXSR(dev)) { |
| 4404 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
| 4405 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
| 4406 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4407 | } |
| 4408 | } |
| 4409 | |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 4410 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4411 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
Daniel Vetter | 5def474 | 2012-01-28 14:49:22 +0100 | [diff] [blame] | 4412 | pipeconf |= PIPECONF_INTERLACED_ILK; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4413 | /* the chip adds 2 halflines automatically */ |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4414 | adjusted_mode->crtc_vtotal -= 1; |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4415 | adjusted_mode->crtc_vblank_end -= 1; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 4416 | I915_WRITE(VSYNCSHIFT(pipe), |
| 4417 | adjusted_mode->crtc_hsync_start |
| 4418 | - adjusted_mode->crtc_htotal/2); |
| 4419 | } else { |
Keith Packard | 617cf88 | 2012-02-08 13:53:38 -0800 | [diff] [blame] | 4420 | pipeconf |= PIPECONF_PROGRESSIVE; |
Daniel Vetter | 0529a0d | 2012-01-28 14:49:24 +0100 | [diff] [blame] | 4421 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
| 4422 | } |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 4423 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4424 | I915_WRITE(HTOTAL(pipe), |
| 4425 | (adjusted_mode->crtc_hdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4426 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4427 | I915_WRITE(HBLANK(pipe), |
| 4428 | (adjusted_mode->crtc_hblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4429 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4430 | I915_WRITE(HSYNC(pipe), |
| 4431 | (adjusted_mode->crtc_hsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4432 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4433 | |
| 4434 | I915_WRITE(VTOTAL(pipe), |
| 4435 | (adjusted_mode->crtc_vdisplay - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4436 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4437 | I915_WRITE(VBLANK(pipe), |
| 4438 | (adjusted_mode->crtc_vblank_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4439 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4440 | I915_WRITE(VSYNC(pipe), |
| 4441 | (adjusted_mode->crtc_vsync_start - 1) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4442 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4443 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4444 | /* pipesrc controls the size that is scaled from, which should |
| 4445 | * always be the user's requested size. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4446 | */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4447 | I915_WRITE(PIPESRC(pipe), |
| 4448 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4449 | |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4450 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 4451 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
| 4452 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
| 4453 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4454 | |
Jesse Barnes | e3aef17 | 2012-04-10 11:58:03 -0700 | [diff] [blame] | 4455 | if (is_cpu_edp) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 4456 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4457 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4458 | I915_WRITE(PIPECONF(pipe), pipeconf); |
| 4459 | POSTING_READ(PIPECONF(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4460 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 4461 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4462 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 4463 | I915_WRITE(DSPCNTR(plane), dspcntr); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 4464 | POSTING_READ(DSPCNTR(plane)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4465 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 4466 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 4467 | |
| 4468 | intel_update_watermarks(dev); |
| 4469 | |
Chris Wilson | 1f803ee | 2009-06-06 09:45:59 +0100 | [diff] [blame] | 4470 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4471 | } |
| 4472 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 4473 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
| 4474 | struct drm_display_mode *mode, |
| 4475 | struct drm_display_mode *adjusted_mode, |
| 4476 | int x, int y, |
| 4477 | struct drm_framebuffer *old_fb) |
| 4478 | { |
| 4479 | struct drm_device *dev = crtc->dev; |
| 4480 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 4481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4482 | int pipe = intel_crtc->pipe; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 4483 | int ret; |
| 4484 | |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 4485 | drm_vblank_pre_modeset(dev, pipe); |
| 4486 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 4487 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
| 4488 | x, y, old_fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4489 | drm_vblank_post_modeset(dev, pipe); |
| 4490 | |
Jesse Barnes | d8e70a2 | 2011-11-15 10:28:54 -0800 | [diff] [blame] | 4491 | if (ret) |
| 4492 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; |
| 4493 | else |
| 4494 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; |
Keith Packard | 120eced | 2011-07-27 01:21:40 -0700 | [diff] [blame] | 4495 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4496 | return ret; |
| 4497 | } |
| 4498 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 4499 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 4500 | int reg_eldv, uint32_t bits_eldv, |
| 4501 | int reg_elda, uint32_t bits_elda, |
| 4502 | int reg_edid) |
| 4503 | { |
| 4504 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 4505 | uint8_t *eld = connector->eld; |
| 4506 | uint32_t i; |
| 4507 | |
| 4508 | i = I915_READ(reg_eldv); |
| 4509 | i &= bits_eldv; |
| 4510 | |
| 4511 | if (!eld[0]) |
| 4512 | return !i; |
| 4513 | |
| 4514 | if (!i) |
| 4515 | return false; |
| 4516 | |
| 4517 | i = I915_READ(reg_elda); |
| 4518 | i &= ~bits_elda; |
| 4519 | I915_WRITE(reg_elda, i); |
| 4520 | |
| 4521 | for (i = 0; i < eld[2]; i++) |
| 4522 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 4523 | return false; |
| 4524 | |
| 4525 | return true; |
| 4526 | } |
| 4527 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4528 | static void g4x_write_eld(struct drm_connector *connector, |
| 4529 | struct drm_crtc *crtc) |
| 4530 | { |
| 4531 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 4532 | uint8_t *eld = connector->eld; |
| 4533 | uint32_t eldv; |
| 4534 | uint32_t len; |
| 4535 | uint32_t i; |
| 4536 | |
| 4537 | i = I915_READ(G4X_AUD_VID_DID); |
| 4538 | |
| 4539 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
| 4540 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 4541 | else |
| 4542 | eldv = G4X_ELDV_DEVCTG; |
| 4543 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 4544 | if (intel_eld_uptodate(connector, |
| 4545 | G4X_AUD_CNTL_ST, eldv, |
| 4546 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
| 4547 | G4X_HDMIW_HDMIEDID)) |
| 4548 | return; |
| 4549 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4550 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 4551 | i &= ~(eldv | G4X_ELD_ADDR); |
| 4552 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
| 4553 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 4554 | |
| 4555 | if (!eld[0]) |
| 4556 | return; |
| 4557 | |
| 4558 | len = min_t(uint8_t, eld[2], len); |
| 4559 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 4560 | for (i = 0; i < len; i++) |
| 4561 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 4562 | |
| 4563 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 4564 | i |= eldv; |
| 4565 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 4566 | } |
| 4567 | |
| 4568 | static void ironlake_write_eld(struct drm_connector *connector, |
| 4569 | struct drm_crtc *crtc) |
| 4570 | { |
| 4571 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 4572 | uint8_t *eld = connector->eld; |
| 4573 | uint32_t eldv; |
| 4574 | uint32_t i; |
| 4575 | int len; |
| 4576 | int hdmiw_hdmiedid; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 4577 | int aud_config; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4578 | int aud_cntl_st; |
| 4579 | int aud_cntrl_st2; |
| 4580 | |
Wu Fengguang | b3f33cb | 2011-12-09 20:42:17 +0800 | [diff] [blame] | 4581 | if (HAS_PCH_IBX(connector->dev)) { |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4582 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 4583 | aud_config = IBX_AUD_CONFIG_A; |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4584 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
| 4585 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4586 | } else { |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4587 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 4588 | aud_config = CPT_AUD_CONFIG_A; |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4589 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
| 4590 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4591 | } |
| 4592 | |
| 4593 | i = to_intel_crtc(crtc)->pipe; |
| 4594 | hdmiw_hdmiedid += i * 0x100; |
| 4595 | aud_cntl_st += i * 0x100; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 4596 | aud_config += i * 0x100; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4597 | |
| 4598 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); |
| 4599 | |
| 4600 | i = I915_READ(aud_cntl_st); |
| 4601 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ |
| 4602 | if (!i) { |
| 4603 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
| 4604 | /* operate blindly on all ports */ |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4605 | eldv = IBX_ELD_VALIDB; |
| 4606 | eldv |= IBX_ELD_VALIDB << 4; |
| 4607 | eldv |= IBX_ELD_VALIDB << 8; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4608 | } else { |
| 4609 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4610 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4611 | } |
| 4612 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 4613 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 4614 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 4615 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 4616 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
| 4617 | } else |
| 4618 | I915_WRITE(aud_config, 0); |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 4619 | |
| 4620 | if (intel_eld_uptodate(connector, |
| 4621 | aud_cntrl_st2, eldv, |
| 4622 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 4623 | hdmiw_hdmiedid)) |
| 4624 | return; |
| 4625 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4626 | i = I915_READ(aud_cntrl_st2); |
| 4627 | i &= ~eldv; |
| 4628 | I915_WRITE(aud_cntrl_st2, i); |
| 4629 | |
| 4630 | if (!eld[0]) |
| 4631 | return; |
| 4632 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4633 | i = I915_READ(aud_cntl_st); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 4634 | i &= ~IBX_ELD_ADDRESS; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 4635 | I915_WRITE(aud_cntl_st, i); |
| 4636 | |
| 4637 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 4638 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 4639 | for (i = 0; i < len; i++) |
| 4640 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 4641 | |
| 4642 | i = I915_READ(aud_cntrl_st2); |
| 4643 | i |= eldv; |
| 4644 | I915_WRITE(aud_cntrl_st2, i); |
| 4645 | } |
| 4646 | |
| 4647 | void intel_write_eld(struct drm_encoder *encoder, |
| 4648 | struct drm_display_mode *mode) |
| 4649 | { |
| 4650 | struct drm_crtc *crtc = encoder->crtc; |
| 4651 | struct drm_connector *connector; |
| 4652 | struct drm_device *dev = encoder->dev; |
| 4653 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4654 | |
| 4655 | connector = drm_select_eld(encoder, mode); |
| 4656 | if (!connector) |
| 4657 | return; |
| 4658 | |
| 4659 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 4660 | connector->base.id, |
| 4661 | drm_get_connector_name(connector), |
| 4662 | connector->encoder->base.id, |
| 4663 | drm_get_encoder_name(connector->encoder)); |
| 4664 | |
| 4665 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 4666 | |
| 4667 | if (dev_priv->display.write_eld) |
| 4668 | dev_priv->display.write_eld(connector, crtc); |
| 4669 | } |
| 4670 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4671 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 4672 | void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 4673 | { |
| 4674 | struct drm_device *dev = crtc->dev; |
| 4675 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4677 | int palreg = PALETTE(intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4678 | int i; |
| 4679 | |
| 4680 | /* The clocks have to be on to load the palette. */ |
Alban Browaeys | aed3f09 | 2012-02-24 17:12:45 +0000 | [diff] [blame] | 4681 | if (!crtc->enabled || !intel_crtc->active) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4682 | return; |
| 4683 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 4684 | /* use legacy palette for Ironlake */ |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 4685 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4686 | palreg = LGC_PALETTE(intel_crtc->pipe); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4687 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4688 | for (i = 0; i < 256; i++) { |
| 4689 | I915_WRITE(palreg + 4 * i, |
| 4690 | (intel_crtc->lut_r[i] << 16) | |
| 4691 | (intel_crtc->lut_g[i] << 8) | |
| 4692 | intel_crtc->lut_b[i]); |
| 4693 | } |
| 4694 | } |
| 4695 | |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4696 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
| 4697 | { |
| 4698 | struct drm_device *dev = crtc->dev; |
| 4699 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4700 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4701 | bool visible = base != 0; |
| 4702 | u32 cntl; |
| 4703 | |
| 4704 | if (intel_crtc->cursor_visible == visible) |
| 4705 | return; |
| 4706 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4707 | cntl = I915_READ(_CURACNTR); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4708 | if (visible) { |
| 4709 | /* On these chipsets we can only modify the base whilst |
| 4710 | * the cursor is disabled. |
| 4711 | */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4712 | I915_WRITE(_CURABASE, base); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4713 | |
| 4714 | cntl &= ~(CURSOR_FORMAT_MASK); |
| 4715 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
| 4716 | cntl |= CURSOR_ENABLE | |
| 4717 | CURSOR_GAMMA_ENABLE | |
| 4718 | CURSOR_FORMAT_ARGB; |
| 4719 | } else |
| 4720 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4721 | I915_WRITE(_CURACNTR, cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4722 | |
| 4723 | intel_crtc->cursor_visible = visible; |
| 4724 | } |
| 4725 | |
| 4726 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
| 4727 | { |
| 4728 | struct drm_device *dev = crtc->dev; |
| 4729 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4730 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4731 | int pipe = intel_crtc->pipe; |
| 4732 | bool visible = base != 0; |
| 4733 | |
| 4734 | if (intel_crtc->cursor_visible != visible) { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 4735 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4736 | if (base) { |
| 4737 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 4738 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 4739 | cntl |= pipe << 28; /* Connect to correct pipe */ |
| 4740 | } else { |
| 4741 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 4742 | cntl |= CURSOR_MODE_DISABLE; |
| 4743 | } |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4744 | I915_WRITE(CURCNTR(pipe), cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4745 | |
| 4746 | intel_crtc->cursor_visible = visible; |
| 4747 | } |
| 4748 | /* and commit changes on next vblank */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4749 | I915_WRITE(CURBASE(pipe), base); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4750 | } |
| 4751 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 4752 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
| 4753 | { |
| 4754 | struct drm_device *dev = crtc->dev; |
| 4755 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4756 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4757 | int pipe = intel_crtc->pipe; |
| 4758 | bool visible = base != 0; |
| 4759 | |
| 4760 | if (intel_crtc->cursor_visible != visible) { |
| 4761 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
| 4762 | if (base) { |
| 4763 | cntl &= ~CURSOR_MODE; |
| 4764 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 4765 | } else { |
| 4766 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 4767 | cntl |= CURSOR_MODE_DISABLE; |
| 4768 | } |
| 4769 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
| 4770 | |
| 4771 | intel_crtc->cursor_visible = visible; |
| 4772 | } |
| 4773 | /* and commit changes on next vblank */ |
| 4774 | I915_WRITE(CURBASE_IVB(pipe), base); |
| 4775 | } |
| 4776 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4777 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4778 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 4779 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4780 | { |
| 4781 | struct drm_device *dev = crtc->dev; |
| 4782 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4783 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4784 | int pipe = intel_crtc->pipe; |
| 4785 | int x = intel_crtc->cursor_x; |
| 4786 | int y = intel_crtc->cursor_y; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4787 | u32 base, pos; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4788 | bool visible; |
| 4789 | |
| 4790 | pos = 0; |
| 4791 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4792 | if (on && crtc->enabled && crtc->fb) { |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4793 | base = intel_crtc->cursor_addr; |
| 4794 | if (x > (int) crtc->fb->width) |
| 4795 | base = 0; |
| 4796 | |
| 4797 | if (y > (int) crtc->fb->height) |
| 4798 | base = 0; |
| 4799 | } else |
| 4800 | base = 0; |
| 4801 | |
| 4802 | if (x < 0) { |
| 4803 | if (x + intel_crtc->cursor_width < 0) |
| 4804 | base = 0; |
| 4805 | |
| 4806 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 4807 | x = -x; |
| 4808 | } |
| 4809 | pos |= x << CURSOR_X_SHIFT; |
| 4810 | |
| 4811 | if (y < 0) { |
| 4812 | if (y + intel_crtc->cursor_height < 0) |
| 4813 | base = 0; |
| 4814 | |
| 4815 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 4816 | y = -y; |
| 4817 | } |
| 4818 | pos |= y << CURSOR_Y_SHIFT; |
| 4819 | |
| 4820 | visible = base != 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 4821 | if (!visible && !intel_crtc->cursor_visible) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4822 | return; |
| 4823 | |
Eugeni Dodonov | 0cd83aa | 2012-04-13 17:08:48 -0300 | [diff] [blame] | 4824 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 4825 | I915_WRITE(CURPOS_IVB(pipe), pos); |
| 4826 | ivb_update_cursor(crtc, base); |
| 4827 | } else { |
| 4828 | I915_WRITE(CURPOS(pipe), pos); |
| 4829 | if (IS_845G(dev) || IS_I865G(dev)) |
| 4830 | i845_update_cursor(crtc, base); |
| 4831 | else |
| 4832 | i9xx_update_cursor(crtc, base); |
| 4833 | } |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4834 | |
| 4835 | if (visible) |
| 4836 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); |
| 4837 | } |
| 4838 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4839 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4840 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4841 | uint32_t handle, |
| 4842 | uint32_t width, uint32_t height) |
| 4843 | { |
| 4844 | struct drm_device *dev = crtc->dev; |
| 4845 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4847 | struct drm_i915_gem_object *obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4848 | uint32_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4849 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4850 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4851 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4852 | |
| 4853 | /* if we want to turn off the cursor ignore width and height */ |
| 4854 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 4855 | DRM_DEBUG_KMS("cursor off\n"); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4856 | addr = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4857 | obj = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 4858 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4859 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4860 | } |
| 4861 | |
| 4862 | /* Currently we only support 64x64 cursors */ |
| 4863 | if (width != 64 || height != 64) { |
| 4864 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 4865 | return -EINVAL; |
| 4866 | } |
| 4867 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4868 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4869 | if (&obj->base == NULL) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4870 | return -ENOENT; |
| 4871 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4872 | if (obj->base.size < width * height * 4) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4873 | DRM_ERROR("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4874 | ret = -ENOMEM; |
| 4875 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4876 | } |
| 4877 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4878 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4879 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4880 | if (!dev_priv->info->cursor_needs_physical) { |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 4881 | if (obj->tiling_mode) { |
| 4882 | DRM_ERROR("cursor cannot be tiled\n"); |
| 4883 | ret = -EINVAL; |
| 4884 | goto fail_locked; |
| 4885 | } |
| 4886 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4887 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4888 | if (ret) { |
| 4889 | DRM_ERROR("failed to move cursor bo into the GTT\n"); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4890 | goto fail_locked; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4891 | } |
| 4892 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 4893 | ret = i915_gem_object_put_fence(obj); |
| 4894 | if (ret) { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4895 | DRM_ERROR("failed to release fence for cursor"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 4896 | goto fail_unpin; |
| 4897 | } |
| 4898 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4899 | addr = obj->gtt_offset; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4900 | } else { |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4901 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4902 | ret = i915_gem_attach_phys_object(dev, obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4903 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
| 4904 | align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4905 | if (ret) { |
| 4906 | DRM_ERROR("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4907 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4908 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4909 | addr = obj->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4910 | } |
| 4911 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4912 | if (IS_GEN2(dev)) |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 4913 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 4914 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4915 | finish: |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4916 | if (intel_crtc->cursor_bo) { |
Kristian Høgsberg | b295d1b | 2009-12-16 15:16:17 -0500 | [diff] [blame] | 4917 | if (dev_priv->info->cursor_needs_physical) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4918 | if (intel_crtc->cursor_bo != obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4919 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 4920 | } else |
| 4921 | i915_gem_object_unpin(intel_crtc->cursor_bo); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4922 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4923 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4924 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4925 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4926 | |
| 4927 | intel_crtc->cursor_addr = addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4928 | intel_crtc->cursor_bo = obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4929 | intel_crtc->cursor_width = width; |
| 4930 | intel_crtc->cursor_height = height; |
| 4931 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4932 | intel_crtc_update_cursor(crtc, true); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 4933 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4934 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 4935 | fail_unpin: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4936 | i915_gem_object_unpin(obj); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 4937 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4938 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 4939 | fail: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4940 | drm_gem_object_unreference_unlocked(&obj->base); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 4941 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4942 | } |
| 4943 | |
| 4944 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 4945 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4946 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4947 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 4948 | intel_crtc->cursor_x = x; |
| 4949 | intel_crtc->cursor_y = y; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 4950 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4951 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4952 | |
| 4953 | return 0; |
| 4954 | } |
| 4955 | |
| 4956 | /** Sets the color ramps on behalf of RandR */ |
| 4957 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 4958 | u16 blue, int regno) |
| 4959 | { |
| 4960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4961 | |
| 4962 | intel_crtc->lut_r[regno] = red >> 8; |
| 4963 | intel_crtc->lut_g[regno] = green >> 8; |
| 4964 | intel_crtc->lut_b[regno] = blue >> 8; |
| 4965 | } |
| 4966 | |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 4967 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 4968 | u16 *blue, int regno) |
| 4969 | { |
| 4970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4971 | |
| 4972 | *red = intel_crtc->lut_r[regno] << 8; |
| 4973 | *green = intel_crtc->lut_g[regno] << 8; |
| 4974 | *blue = intel_crtc->lut_b[regno] << 8; |
| 4975 | } |
| 4976 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4977 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4978 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4979 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4980 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4982 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 4983 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4984 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 4985 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 4986 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 4987 | } |
| 4988 | |
| 4989 | intel_crtc_load_lut(crtc); |
| 4990 | } |
| 4991 | |
| 4992 | /** |
| 4993 | * Get a pipe with a simple mode set on it for doing load-based monitor |
| 4994 | * detection. |
| 4995 | * |
| 4996 | * It will be up to the load-detect code to adjust the pipe as appropriate for |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4997 | * its requirements. The pipe will be connected to no other encoders. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4998 | * |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 4999 | * Currently this code will only succeed if there is a pipe with no encoders |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5000 | * configured for it. In the future, it could choose to temporarily disable |
| 5001 | * some outputs to free up a pipe for its use. |
| 5002 | * |
| 5003 | * \return crtc, or NULL if no pipes are available. |
| 5004 | */ |
| 5005 | |
| 5006 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 5007 | static struct drm_display_mode load_detect_mode = { |
| 5008 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 5009 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 5010 | }; |
| 5011 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5012 | static struct drm_framebuffer * |
| 5013 | intel_framebuffer_create(struct drm_device *dev, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 5014 | struct drm_mode_fb_cmd2 *mode_cmd, |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5015 | struct drm_i915_gem_object *obj) |
| 5016 | { |
| 5017 | struct intel_framebuffer *intel_fb; |
| 5018 | int ret; |
| 5019 | |
| 5020 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 5021 | if (!intel_fb) { |
| 5022 | drm_gem_object_unreference_unlocked(&obj->base); |
| 5023 | return ERR_PTR(-ENOMEM); |
| 5024 | } |
| 5025 | |
| 5026 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
| 5027 | if (ret) { |
| 5028 | drm_gem_object_unreference_unlocked(&obj->base); |
| 5029 | kfree(intel_fb); |
| 5030 | return ERR_PTR(ret); |
| 5031 | } |
| 5032 | |
| 5033 | return &intel_fb->base; |
| 5034 | } |
| 5035 | |
| 5036 | static u32 |
| 5037 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 5038 | { |
| 5039 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 5040 | return ALIGN(pitch, 64); |
| 5041 | } |
| 5042 | |
| 5043 | static u32 |
| 5044 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 5045 | { |
| 5046 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
| 5047 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
| 5048 | } |
| 5049 | |
| 5050 | static struct drm_framebuffer * |
| 5051 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 5052 | struct drm_display_mode *mode, |
| 5053 | int depth, int bpp) |
| 5054 | { |
| 5055 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 5056 | struct drm_mode_fb_cmd2 mode_cmd; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5057 | |
| 5058 | obj = i915_gem_alloc_object(dev, |
| 5059 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 5060 | if (obj == NULL) |
| 5061 | return ERR_PTR(-ENOMEM); |
| 5062 | |
| 5063 | mode_cmd.width = mode->hdisplay; |
| 5064 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 5065 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 5066 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 5067 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5068 | |
| 5069 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
| 5070 | } |
| 5071 | |
| 5072 | static struct drm_framebuffer * |
| 5073 | mode_fits_in_fbdev(struct drm_device *dev, |
| 5074 | struct drm_display_mode *mode) |
| 5075 | { |
| 5076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5077 | struct drm_i915_gem_object *obj; |
| 5078 | struct drm_framebuffer *fb; |
| 5079 | |
| 5080 | if (dev_priv->fbdev == NULL) |
| 5081 | return NULL; |
| 5082 | |
| 5083 | obj = dev_priv->fbdev->ifb.obj; |
| 5084 | if (obj == NULL) |
| 5085 | return NULL; |
| 5086 | |
| 5087 | fb = &dev_priv->fbdev->ifb.base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 5088 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 5089 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5090 | return NULL; |
| 5091 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 5092 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5093 | return NULL; |
| 5094 | |
| 5095 | return fb; |
| 5096 | } |
| 5097 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 5098 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
| 5099 | struct drm_connector *connector, |
| 5100 | struct drm_display_mode *mode, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5101 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5102 | { |
| 5103 | struct intel_crtc *intel_crtc; |
| 5104 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5105 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5106 | struct drm_crtc *crtc = NULL; |
| 5107 | struct drm_device *dev = encoder->dev; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5108 | struct drm_framebuffer *old_fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5109 | int i = -1; |
| 5110 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5111 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 5112 | connector->base.id, drm_get_connector_name(connector), |
| 5113 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 5114 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5115 | /* |
| 5116 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 5117 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5118 | * - if the connector already has an assigned crtc, use it (but make |
| 5119 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 5120 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5121 | * - try to find the first unused crtc that can drive this connector, |
| 5122 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5123 | */ |
| 5124 | |
| 5125 | /* See if we already have a CRTC for this connector */ |
| 5126 | if (encoder->crtc) { |
| 5127 | crtc = encoder->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5128 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5129 | intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5130 | old->dpms_mode = intel_crtc->dpms_mode; |
| 5131 | old->load_detect_temp = false; |
| 5132 | |
| 5133 | /* Make sure the crtc and connector are running */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5134 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 5135 | struct drm_encoder_helper_funcs *encoder_funcs; |
| 5136 | struct drm_crtc_helper_funcs *crtc_funcs; |
| 5137 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5138 | crtc_funcs = crtc->helper_private; |
| 5139 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 5140 | |
| 5141 | encoder_funcs = encoder->helper_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5142 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
| 5143 | } |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5144 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 5145 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5146 | } |
| 5147 | |
| 5148 | /* Find an unused one (if possible) */ |
| 5149 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 5150 | i++; |
| 5151 | if (!(encoder->possible_crtcs & (1 << i))) |
| 5152 | continue; |
| 5153 | if (!possible_crtc->enabled) { |
| 5154 | crtc = possible_crtc; |
| 5155 | break; |
| 5156 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5157 | } |
| 5158 | |
| 5159 | /* |
| 5160 | * If we didn't find an unused CRTC, don't use any. |
| 5161 | */ |
| 5162 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 5163 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
| 5164 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5165 | } |
| 5166 | |
| 5167 | encoder->crtc = crtc; |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 5168 | connector->encoder = encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5169 | |
| 5170 | intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5171 | old->dpms_mode = intel_crtc->dpms_mode; |
| 5172 | old->load_detect_temp = true; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5173 | old->release_fb = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5174 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 5175 | if (!mode) |
| 5176 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5177 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5178 | old_fb = crtc->fb; |
| 5179 | |
| 5180 | /* We need a framebuffer large enough to accommodate all accesses |
| 5181 | * that the plane may generate whilst we perform load detection. |
| 5182 | * We can not rely on the fbcon either being present (we get called |
| 5183 | * during its initialisation to detect all boot displays, or it may |
| 5184 | * not even exist) or that it is large enough to satisfy the |
| 5185 | * requested mode. |
| 5186 | */ |
| 5187 | crtc->fb = mode_fits_in_fbdev(dev, mode); |
| 5188 | if (crtc->fb == NULL) { |
| 5189 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
| 5190 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 5191 | old->release_fb = crtc->fb; |
| 5192 | } else |
| 5193 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
| 5194 | if (IS_ERR(crtc->fb)) { |
| 5195 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
| 5196 | crtc->fb = old_fb; |
| 5197 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5198 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5199 | |
| 5200 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 5201 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5202 | if (old->release_fb) |
| 5203 | old->release_fb->funcs->destroy(old->release_fb); |
| 5204 | crtc->fb = old_fb; |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 5205 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5206 | } |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 5207 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5208 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 5209 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5210 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 5211 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5212 | } |
| 5213 | |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 5214 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5215 | struct drm_connector *connector, |
| 5216 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5217 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 5218 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5219 | struct drm_device *dev = encoder->dev; |
| 5220 | struct drm_crtc *crtc = encoder->crtc; |
| 5221 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
| 5222 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 5223 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5224 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 5225 | connector->base.id, drm_get_connector_name(connector), |
| 5226 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 5227 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5228 | if (old->load_detect_temp) { |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 5229 | connector->encoder = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5230 | drm_helper_disable_unused_functions(dev); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 5231 | |
| 5232 | if (old->release_fb) |
| 5233 | old->release_fb->funcs->destroy(old->release_fb); |
| 5234 | |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 5235 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5236 | } |
| 5237 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 5238 | /* Switch crtc and encoder back off if necessary */ |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 5239 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
| 5240 | encoder_funcs->dpms(encoder, old->dpms_mode); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 5241 | crtc_funcs->dpms(crtc, old->dpms_mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5242 | } |
| 5243 | } |
| 5244 | |
| 5245 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 5246 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) |
| 5247 | { |
| 5248 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5250 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 5251 | u32 dpll = I915_READ(DPLL(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5252 | u32 fp; |
| 5253 | intel_clock_t clock; |
| 5254 | |
| 5255 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Chris Wilson | 39adb7a | 2011-04-22 22:17:21 +0100 | [diff] [blame] | 5256 | fp = I915_READ(FP0(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5257 | else |
Chris Wilson | 39adb7a | 2011-04-22 22:17:21 +0100 | [diff] [blame] | 5258 | fp = I915_READ(FP1(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5259 | |
| 5260 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5261 | if (IS_PINEVIEW(dev)) { |
| 5262 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 5263 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5264 | } else { |
| 5265 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 5266 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 5267 | } |
| 5268 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 5269 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 5270 | if (IS_PINEVIEW(dev)) |
| 5271 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 5272 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5273 | else |
| 5274 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5275 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 5276 | |
| 5277 | switch (dpll & DPLL_MODE_MASK) { |
| 5278 | case DPLLB_MODE_DAC_SERIAL: |
| 5279 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 5280 | 5 : 10; |
| 5281 | break; |
| 5282 | case DPLLB_MODE_LVDS: |
| 5283 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 5284 | 7 : 14; |
| 5285 | break; |
| 5286 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 5287 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5288 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
| 5289 | return 0; |
| 5290 | } |
| 5291 | |
| 5292 | /* XXX: Handle the 100Mhz refclk */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5293 | intel_clock(dev, 96000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5294 | } else { |
| 5295 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); |
| 5296 | |
| 5297 | if (is_lvds) { |
| 5298 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 5299 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 5300 | clock.p2 = 14; |
| 5301 | |
| 5302 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 5303 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 5304 | /* XXX: might not be 66MHz */ |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5305 | intel_clock(dev, 66000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5306 | } else |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5307 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5308 | } else { |
| 5309 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 5310 | clock.p1 = 2; |
| 5311 | else { |
| 5312 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 5313 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 5314 | } |
| 5315 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 5316 | clock.p2 = 4; |
| 5317 | else |
| 5318 | clock.p2 = 2; |
| 5319 | |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 5320 | intel_clock(dev, 48000, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5321 | } |
| 5322 | } |
| 5323 | |
| 5324 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 5325 | * i830PllIsValid() because it relies on the xf86_config connector |
| 5326 | * configuration being accurate, which it isn't necessarily. |
| 5327 | */ |
| 5328 | |
| 5329 | return clock.dot; |
| 5330 | } |
| 5331 | |
| 5332 | /** Returns the currently programmed mode of the given pipe. */ |
| 5333 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 5334 | struct drm_crtc *crtc) |
| 5335 | { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 5336 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5338 | int pipe = intel_crtc->pipe; |
| 5339 | struct drm_display_mode *mode; |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 5340 | int htot = I915_READ(HTOTAL(pipe)); |
| 5341 | int hsync = I915_READ(HSYNC(pipe)); |
| 5342 | int vtot = I915_READ(VTOTAL(pipe)); |
| 5343 | int vsync = I915_READ(VSYNC(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5344 | |
| 5345 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 5346 | if (!mode) |
| 5347 | return NULL; |
| 5348 | |
| 5349 | mode->clock = intel_crtc_clock_get(dev, crtc); |
| 5350 | mode->hdisplay = (htot & 0xffff) + 1; |
| 5351 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 5352 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 5353 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 5354 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 5355 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 5356 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 5357 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 5358 | |
| 5359 | drm_mode_set_name(mode); |
| 5360 | drm_mode_set_crtcinfo(mode, 0); |
| 5361 | |
| 5362 | return mode; |
| 5363 | } |
| 5364 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5365 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
| 5366 | |
| 5367 | /* When this timer fires, we've been idle for awhile */ |
| 5368 | static void intel_gpu_idle_timer(unsigned long arg) |
| 5369 | { |
| 5370 | struct drm_device *dev = (struct drm_device *)arg; |
| 5371 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5372 | |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 5373 | if (!list_empty(&dev_priv->mm.active_list)) { |
| 5374 | /* Still processing requests, so just re-arm the timer. */ |
| 5375 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 5376 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
| 5377 | return; |
| 5378 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5379 | |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 5380 | dev_priv->busy = false; |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 5381 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5382 | } |
| 5383 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5384 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
| 5385 | |
| 5386 | static void intel_crtc_idle_timer(unsigned long arg) |
| 5387 | { |
| 5388 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; |
| 5389 | struct drm_crtc *crtc = &intel_crtc->base; |
| 5390 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; |
Chris Wilson | ff7ea4c | 2010-12-08 09:43:41 +0000 | [diff] [blame] | 5391 | struct intel_framebuffer *intel_fb; |
| 5392 | |
| 5393 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 5394 | if (intel_fb && intel_fb->obj->active) { |
| 5395 | /* The framebuffer is still being accessed by the GPU. */ |
| 5396 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 5397 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 5398 | return; |
| 5399 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5400 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5401 | intel_crtc->busy = false; |
Eric Anholt | 01dfba9 | 2009-09-06 15:18:53 -0700 | [diff] [blame] | 5402 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5403 | } |
| 5404 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 5405 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5406 | { |
| 5407 | struct drm_device *dev = crtc->dev; |
| 5408 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5409 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5410 | int pipe = intel_crtc->pipe; |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 5411 | int dpll_reg = DPLL(pipe); |
| 5412 | int dpll; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5413 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5414 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5415 | return; |
| 5416 | |
| 5417 | if (!dev_priv->lvds_downclock_avail) |
| 5418 | return; |
| 5419 | |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 5420 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5421 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 5422 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5423 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 5424 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5425 | |
| 5426 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 5427 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 5428 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 5429 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5430 | dpll = I915_READ(dpll_reg); |
| 5431 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 5432 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5433 | } |
| 5434 | |
| 5435 | /* Schedule downclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 5436 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 5437 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5438 | } |
| 5439 | |
| 5440 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 5441 | { |
| 5442 | struct drm_device *dev = crtc->dev; |
| 5443 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5445 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 5446 | int dpll_reg = DPLL(pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5447 | int dpll = I915_READ(dpll_reg); |
| 5448 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 5449 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5450 | return; |
| 5451 | |
| 5452 | if (!dev_priv->lvds_downclock_avail) |
| 5453 | return; |
| 5454 | |
| 5455 | /* |
| 5456 | * Since this is called by a timer, we should never get here in |
| 5457 | * the manual case. |
| 5458 | */ |
| 5459 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 5460 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5461 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 5462 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5463 | |
| 5464 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 5465 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 5466 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5467 | dpll = I915_READ(dpll_reg); |
| 5468 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 5469 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5470 | } |
| 5471 | |
| 5472 | } |
| 5473 | |
| 5474 | /** |
| 5475 | * intel_idle_update - adjust clocks for idleness |
| 5476 | * @work: work struct |
| 5477 | * |
| 5478 | * Either the GPU or display (or both) went idle. Check the busy status |
| 5479 | * here and adjust the CRTC and GPU clocks as necessary. |
| 5480 | */ |
| 5481 | static void intel_idle_update(struct work_struct *work) |
| 5482 | { |
| 5483 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 5484 | idle_work); |
| 5485 | struct drm_device *dev = dev_priv->dev; |
| 5486 | struct drm_crtc *crtc; |
| 5487 | struct intel_crtc *intel_crtc; |
| 5488 | |
| 5489 | if (!i915_powersave) |
| 5490 | return; |
| 5491 | |
| 5492 | mutex_lock(&dev->struct_mutex); |
| 5493 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 5494 | i915_update_gfx_val(dev_priv); |
| 5495 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5496 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 5497 | /* Skip inactive CRTCs */ |
| 5498 | if (!crtc->fb) |
| 5499 | continue; |
| 5500 | |
| 5501 | intel_crtc = to_intel_crtc(crtc); |
| 5502 | if (!intel_crtc->busy) |
| 5503 | intel_decrease_pllclock(crtc); |
| 5504 | } |
| 5505 | |
Li Peng | 45ac22c | 2010-06-12 23:38:35 +0800 | [diff] [blame] | 5506 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5507 | mutex_unlock(&dev->struct_mutex); |
| 5508 | } |
| 5509 | |
| 5510 | /** |
| 5511 | * intel_mark_busy - mark the GPU and possibly the display busy |
| 5512 | * @dev: drm device |
| 5513 | * @obj: object we're operating on |
| 5514 | * |
| 5515 | * Callers can use this function to indicate that the GPU is busy processing |
| 5516 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout |
| 5517 | * buffer), we'll also mark the display as busy, so we know to increase its |
| 5518 | * clock frequency. |
| 5519 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5520 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5521 | { |
| 5522 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5523 | struct drm_crtc *crtc = NULL; |
| 5524 | struct intel_framebuffer *intel_fb; |
| 5525 | struct intel_crtc *intel_crtc; |
| 5526 | |
Zhenyu Wang | 5e17ee7 | 2009-09-03 09:30:06 +0800 | [diff] [blame] | 5527 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 5528 | return; |
| 5529 | |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 5530 | if (!dev_priv->busy) |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 5531 | dev_priv->busy = true; |
Alexander Lam | 18b2190 | 2011-01-03 13:28:56 -0500 | [diff] [blame] | 5532 | else |
Chris Wilson | 28cf798 | 2009-11-30 01:08:56 +0000 | [diff] [blame] | 5533 | mod_timer(&dev_priv->idle_timer, jiffies + |
| 5534 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5535 | |
| 5536 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 5537 | if (!crtc->fb) |
| 5538 | continue; |
| 5539 | |
| 5540 | intel_crtc = to_intel_crtc(crtc); |
| 5541 | intel_fb = to_intel_framebuffer(crtc->fb); |
| 5542 | if (intel_fb->obj == obj) { |
| 5543 | if (!intel_crtc->busy) { |
| 5544 | /* Non-busy -> busy, upclock */ |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 5545 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5546 | intel_crtc->busy = true; |
| 5547 | } else { |
| 5548 | /* Busy -> busy, put off timer */ |
| 5549 | mod_timer(&intel_crtc->idle_timer, jiffies + |
| 5550 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); |
| 5551 | } |
| 5552 | } |
| 5553 | } |
| 5554 | } |
| 5555 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5556 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 5557 | { |
| 5558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 5559 | struct drm_device *dev = crtc->dev; |
| 5560 | struct intel_unpin_work *work; |
| 5561 | unsigned long flags; |
| 5562 | |
| 5563 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5564 | work = intel_crtc->unpin_work; |
| 5565 | intel_crtc->unpin_work = NULL; |
| 5566 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5567 | |
| 5568 | if (work) { |
| 5569 | cancel_work_sync(&work->work); |
| 5570 | kfree(work); |
| 5571 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5572 | |
| 5573 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 5574 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5575 | kfree(intel_crtc); |
| 5576 | } |
| 5577 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5578 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 5579 | { |
| 5580 | struct intel_unpin_work *work = |
| 5581 | container_of(__work, struct intel_unpin_work, work); |
| 5582 | |
| 5583 | mutex_lock(&work->dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 5584 | intel_unpin_fb_obj(work->old_fb_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5585 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
| 5586 | drm_gem_object_unreference(&work->old_fb_obj->base); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 5587 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 5588 | intel_update_fbc(work->dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5589 | mutex_unlock(&work->dev->struct_mutex); |
| 5590 | kfree(work); |
| 5591 | } |
| 5592 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5593 | static void do_intel_finish_page_flip(struct drm_device *dev, |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5594 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5595 | { |
| 5596 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5597 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5598 | struct intel_unpin_work *work; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5599 | struct drm_i915_gem_object *obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5600 | struct drm_pending_vblank_event *e; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5601 | struct timeval tnow, tvbl; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5602 | unsigned long flags; |
| 5603 | |
| 5604 | /* Ignore early vblank irqs */ |
| 5605 | if (intel_crtc == NULL) |
| 5606 | return; |
| 5607 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5608 | do_gettimeofday(&tnow); |
| 5609 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5610 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5611 | work = intel_crtc->unpin_work; |
| 5612 | if (work == NULL || !work->pending) { |
| 5613 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5614 | return; |
| 5615 | } |
| 5616 | |
| 5617 | intel_crtc->unpin_work = NULL; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5618 | |
| 5619 | if (work->event) { |
| 5620 | e = work->event; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5621 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5622 | |
| 5623 | /* Called before vblank count and timestamps have |
| 5624 | * been updated for the vblank interval of flip |
| 5625 | * completion? Need to increment vblank count and |
| 5626 | * add one videorefresh duration to returned timestamp |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5627 | * to account for this. We assume this happened if we |
| 5628 | * get called over 0.9 frame durations after the last |
| 5629 | * timestamped vblank. |
| 5630 | * |
| 5631 | * This calculation can not be used with vrefresh rates |
| 5632 | * below 5Hz (10Hz to be on the safe side) without |
| 5633 | * promoting to 64 integers. |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5634 | */ |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5635 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
| 5636 | 9 * crtc->framedur_ns) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5637 | e->event.sequence++; |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5638 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
| 5639 | crtc->framedur_ns); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5640 | } |
| 5641 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5642 | e->event.tv_sec = tvbl.tv_sec; |
| 5643 | e->event.tv_usec = tvbl.tv_usec; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5644 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5645 | list_add_tail(&e->base.link, |
| 5646 | &e->base.file_priv->event_list); |
| 5647 | wake_up_interruptible(&e->base.file_priv->event_wait); |
| 5648 | } |
| 5649 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 5650 | drm_vblank_put(dev, intel_crtc->pipe); |
| 5651 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5652 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5653 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5654 | obj = work->old_fb_obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 5655 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 5656 | atomic_clear_mask(1 << intel_crtc->plane, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5657 | &obj->pending_flip.counter); |
| 5658 | if (atomic_read(&obj->pending_flip) == 0) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5659 | wake_up(&dev_priv->pending_flip_queue); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 5660 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5661 | schedule_work(&work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 5662 | |
| 5663 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5664 | } |
| 5665 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5666 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 5667 | { |
| 5668 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5669 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 5670 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5671 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5672 | } |
| 5673 | |
| 5674 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 5675 | { |
| 5676 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5677 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 5678 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 5679 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 5680 | } |
| 5681 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5682 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 5683 | { |
| 5684 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5685 | struct intel_crtc *intel_crtc = |
| 5686 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 5687 | unsigned long flags; |
| 5688 | |
| 5689 | spin_lock_irqsave(&dev->event_lock, flags); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 5690 | if (intel_crtc->unpin_work) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 5691 | if ((++intel_crtc->unpin_work->pending) > 1) |
| 5692 | DRM_ERROR("Prepared flip multiple times\n"); |
Jesse Barnes | de3f440 | 2010-01-14 13:18:02 -0800 | [diff] [blame] | 5693 | } else { |
| 5694 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); |
| 5695 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5696 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5697 | } |
| 5698 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5699 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 5700 | struct drm_crtc *crtc, |
| 5701 | struct drm_framebuffer *fb, |
| 5702 | struct drm_i915_gem_object *obj) |
| 5703 | { |
| 5704 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5706 | unsigned long offset; |
| 5707 | u32 flip_mask; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5708 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5709 | int ret; |
| 5710 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5711 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5712 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5713 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5714 | |
| 5715 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 5716 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5717 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5718 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5719 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5720 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5721 | |
| 5722 | /* Can't queue multiple flips, so wait for the previous |
| 5723 | * one to finish before executing the next. |
| 5724 | */ |
| 5725 | if (intel_crtc->plane) |
| 5726 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 5727 | else |
| 5728 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5729 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 5730 | intel_ring_emit(ring, MI_NOOP); |
| 5731 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 5732 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5733 | intel_ring_emit(ring, fb->pitches[0]); |
| 5734 | intel_ring_emit(ring, obj->gtt_offset + offset); |
| 5735 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
| 5736 | intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5737 | return 0; |
| 5738 | |
| 5739 | err_unpin: |
| 5740 | intel_unpin_fb_obj(obj); |
| 5741 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5742 | return ret; |
| 5743 | } |
| 5744 | |
| 5745 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 5746 | struct drm_crtc *crtc, |
| 5747 | struct drm_framebuffer *fb, |
| 5748 | struct drm_i915_gem_object *obj) |
| 5749 | { |
| 5750 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5751 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5752 | unsigned long offset; |
| 5753 | u32 flip_mask; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5754 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5755 | int ret; |
| 5756 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5757 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5758 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5759 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5760 | |
| 5761 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 5762 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5763 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5764 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5765 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5766 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5767 | |
| 5768 | if (intel_crtc->plane) |
| 5769 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 5770 | else |
| 5771 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5772 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 5773 | intel_ring_emit(ring, MI_NOOP); |
| 5774 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
| 5775 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5776 | intel_ring_emit(ring, fb->pitches[0]); |
| 5777 | intel_ring_emit(ring, obj->gtt_offset + offset); |
| 5778 | intel_ring_emit(ring, MI_NOOP); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5779 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5780 | intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5781 | return 0; |
| 5782 | |
| 5783 | err_unpin: |
| 5784 | intel_unpin_fb_obj(obj); |
| 5785 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5786 | return ret; |
| 5787 | } |
| 5788 | |
| 5789 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 5790 | struct drm_crtc *crtc, |
| 5791 | struct drm_framebuffer *fb, |
| 5792 | struct drm_i915_gem_object *obj) |
| 5793 | { |
| 5794 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5796 | uint32_t pf, pipesrc; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5797 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5798 | int ret; |
| 5799 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5800 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5801 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5802 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5803 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5804 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5805 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5806 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5807 | |
| 5808 | /* i965+ uses the linear or tiled offsets from the |
| 5809 | * Display Registers (which do not change across a page-flip) |
| 5810 | * so we need only reprogram the base address. |
| 5811 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5812 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 5813 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5814 | intel_ring_emit(ring, fb->pitches[0]); |
| 5815 | intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5816 | |
| 5817 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 5818 | * untested on non-native modes, so ignore it for now. |
| 5819 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 5820 | */ |
| 5821 | pf = 0; |
| 5822 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5823 | intel_ring_emit(ring, pf | pipesrc); |
| 5824 | intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5825 | return 0; |
| 5826 | |
| 5827 | err_unpin: |
| 5828 | intel_unpin_fb_obj(obj); |
| 5829 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5830 | return ret; |
| 5831 | } |
| 5832 | |
| 5833 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 5834 | struct drm_crtc *crtc, |
| 5835 | struct drm_framebuffer *fb, |
| 5836 | struct drm_i915_gem_object *obj) |
| 5837 | { |
| 5838 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5840 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5841 | uint32_t pf, pipesrc; |
| 5842 | int ret; |
| 5843 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5844 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5845 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5846 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5847 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5848 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5849 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5850 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5851 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5852 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 5853 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 5854 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
| 5855 | intel_ring_emit(ring, obj->gtt_offset); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5856 | |
| 5857 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 5858 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 5859 | intel_ring_emit(ring, pf | pipesrc); |
| 5860 | intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5861 | return 0; |
| 5862 | |
| 5863 | err_unpin: |
| 5864 | intel_unpin_fb_obj(obj); |
| 5865 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5866 | return ret; |
| 5867 | } |
| 5868 | |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 5869 | /* |
| 5870 | * On gen7 we currently use the blit ring because (in early silicon at least) |
| 5871 | * the render ring doesn't give us interrpts for page flip completion, which |
| 5872 | * means clients will hang after the first flip is queued. Fortunately the |
| 5873 | * blit ring generates interrupts properly, so use it instead. |
| 5874 | */ |
| 5875 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 5876 | struct drm_crtc *crtc, |
| 5877 | struct drm_framebuffer *fb, |
| 5878 | struct drm_i915_gem_object *obj) |
| 5879 | { |
| 5880 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5882 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
| 5883 | int ret; |
| 5884 | |
| 5885 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
| 5886 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5887 | goto err; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 5888 | |
| 5889 | ret = intel_ring_begin(ring, 4); |
| 5890 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5891 | goto err_unpin; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 5892 | |
| 5893 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 5894 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 5895 | intel_ring_emit(ring, (obj->gtt_offset)); |
| 5896 | intel_ring_emit(ring, (MI_NOOP)); |
| 5897 | intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 5898 | return 0; |
| 5899 | |
| 5900 | err_unpin: |
| 5901 | intel_unpin_fb_obj(obj); |
| 5902 | err: |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 5903 | return ret; |
| 5904 | } |
| 5905 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5906 | static int intel_default_queue_flip(struct drm_device *dev, |
| 5907 | struct drm_crtc *crtc, |
| 5908 | struct drm_framebuffer *fb, |
| 5909 | struct drm_i915_gem_object *obj) |
| 5910 | { |
| 5911 | return -ENODEV; |
| 5912 | } |
| 5913 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5914 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 5915 | struct drm_framebuffer *fb, |
| 5916 | struct drm_pending_vblank_event *event) |
| 5917 | { |
| 5918 | struct drm_device *dev = crtc->dev; |
| 5919 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5920 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5921 | struct drm_i915_gem_object *obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5923 | struct intel_unpin_work *work; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5924 | unsigned long flags; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 5925 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5926 | |
| 5927 | work = kzalloc(sizeof *work, GFP_KERNEL); |
| 5928 | if (work == NULL) |
| 5929 | return -ENOMEM; |
| 5930 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5931 | work->event = event; |
| 5932 | work->dev = crtc->dev; |
| 5933 | intel_fb = to_intel_framebuffer(crtc->fb); |
Jesse Barnes | b1b87f6 | 2010-01-26 14:40:05 -0800 | [diff] [blame] | 5934 | work->old_fb_obj = intel_fb->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5935 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 5936 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 5937 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
| 5938 | if (ret) |
| 5939 | goto free_work; |
| 5940 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5941 | /* We borrow the event spin lock for protecting unpin_work */ |
| 5942 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5943 | if (intel_crtc->unpin_work) { |
| 5944 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5945 | kfree(work); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 5946 | drm_vblank_put(dev, intel_crtc->pipe); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 5947 | |
| 5948 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5949 | return -EBUSY; |
| 5950 | } |
| 5951 | intel_crtc->unpin_work = work; |
| 5952 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5953 | |
| 5954 | intel_fb = to_intel_framebuffer(fb); |
| 5955 | obj = intel_fb->obj; |
| 5956 | |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 5957 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5958 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 5959 | /* Reference the objects for the scheduled work. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5960 | drm_gem_object_reference(&work->old_fb_obj->base); |
| 5961 | drm_gem_object_reference(&obj->base); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5962 | |
| 5963 | crtc->fb = fb; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5964 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 5965 | work->pending_flip_obj = obj; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 5966 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 5967 | work->enable_stall_check = true; |
| 5968 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 5969 | /* Block clients from rendering to the new back buffer until |
| 5970 | * the flip occurs and the object is no longer visible. |
| 5971 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5972 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 5973 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5974 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
| 5975 | if (ret) |
| 5976 | goto cleanup_pending; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5977 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 5978 | intel_disable_fbc(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5979 | mutex_unlock(&dev->struct_mutex); |
| 5980 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 5981 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 5982 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5983 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5984 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 5985 | cleanup_pending: |
| 5986 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 5987 | drm_gem_object_unreference(&work->old_fb_obj->base); |
| 5988 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5989 | mutex_unlock(&dev->struct_mutex); |
| 5990 | |
| 5991 | spin_lock_irqsave(&dev->event_lock, flags); |
| 5992 | intel_crtc->unpin_work = NULL; |
| 5993 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 5994 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 5995 | drm_vblank_put(dev, intel_crtc->pipe); |
| 5996 | free_work: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 5997 | kfree(work); |
| 5998 | |
| 5999 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 6000 | } |
| 6001 | |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 6002 | static void intel_sanitize_modesetting(struct drm_device *dev, |
| 6003 | int pipe, int plane) |
| 6004 | { |
| 6005 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6006 | u32 reg, val; |
| 6007 | |
Chris Wilson | f47166d | 2012-03-22 15:00:50 +0000 | [diff] [blame] | 6008 | /* Clear any frame start delays used for debugging left by the BIOS */ |
| 6009 | for_each_pipe(pipe) { |
| 6010 | reg = PIPECONF(pipe); |
| 6011 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 6012 | } |
| 6013 | |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 6014 | if (HAS_PCH_SPLIT(dev)) |
| 6015 | return; |
| 6016 | |
| 6017 | /* Who knows what state these registers were left in by the BIOS or |
| 6018 | * grub? |
| 6019 | * |
| 6020 | * If we leave the registers in a conflicting state (e.g. with the |
| 6021 | * display plane reading from the other pipe than the one we intend |
| 6022 | * to use) then when we attempt to teardown the active mode, we will |
| 6023 | * not disable the pipes and planes in the correct order -- leaving |
| 6024 | * a plane reading from a disabled pipe and possibly leading to |
| 6025 | * undefined behaviour. |
| 6026 | */ |
| 6027 | |
| 6028 | reg = DSPCNTR(plane); |
| 6029 | val = I915_READ(reg); |
| 6030 | |
| 6031 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
| 6032 | return; |
| 6033 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) |
| 6034 | return; |
| 6035 | |
| 6036 | /* This display plane is active and attached to the other CPU pipe. */ |
| 6037 | pipe = !pipe; |
| 6038 | |
| 6039 | /* Disable the plane and wait for it to stop reading from the pipe. */ |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 6040 | intel_disable_plane(dev_priv, plane, pipe); |
| 6041 | intel_disable_pipe(dev_priv, pipe); |
Chris Wilson | 47f1c6c | 2010-12-03 15:37:31 +0000 | [diff] [blame] | 6042 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6043 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 6044 | static void intel_crtc_reset(struct drm_crtc *crtc) |
| 6045 | { |
| 6046 | struct drm_device *dev = crtc->dev; |
| 6047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6048 | |
| 6049 | /* Reset flags back to the 'unknown' status so that they |
| 6050 | * will be correctly set on the initial modeset. |
| 6051 | */ |
| 6052 | intel_crtc->dpms_mode = -1; |
| 6053 | |
| 6054 | /* We need to fix up any BIOS configuration that conflicts with |
| 6055 | * our expectations. |
| 6056 | */ |
| 6057 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); |
| 6058 | } |
| 6059 | |
| 6060 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
| 6061 | .dpms = intel_crtc_dpms, |
| 6062 | .mode_fixup = intel_crtc_mode_fixup, |
| 6063 | .mode_set = intel_crtc_mode_set, |
| 6064 | .mode_set_base = intel_pipe_set_base, |
| 6065 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 6066 | .load_lut = intel_crtc_load_lut, |
| 6067 | .disable = intel_crtc_disable, |
| 6068 | }; |
| 6069 | |
| 6070 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
| 6071 | .reset = intel_crtc_reset, |
| 6072 | .cursor_set = intel_crtc_cursor_set, |
| 6073 | .cursor_move = intel_crtc_cursor_move, |
| 6074 | .gamma_set = intel_crtc_gamma_set, |
| 6075 | .set_config = drm_crtc_helper_set_config, |
| 6076 | .destroy = intel_crtc_destroy, |
| 6077 | .page_flip = intel_crtc_page_flip, |
| 6078 | }; |
| 6079 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6080 | static void intel_pch_pll_init(struct drm_device *dev) |
| 6081 | { |
| 6082 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 6083 | int i; |
| 6084 | |
| 6085 | if (dev_priv->num_pch_pll == 0) { |
| 6086 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); |
| 6087 | return; |
| 6088 | } |
| 6089 | |
| 6090 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
| 6091 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); |
| 6092 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); |
| 6093 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); |
| 6094 | } |
| 6095 | } |
| 6096 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 6097 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6098 | { |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 6099 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6100 | struct intel_crtc *intel_crtc; |
| 6101 | int i; |
| 6102 | |
| 6103 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 6104 | if (intel_crtc == NULL) |
| 6105 | return; |
| 6106 | |
| 6107 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 6108 | |
| 6109 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6110 | for (i = 0; i < 256; i++) { |
| 6111 | intel_crtc->lut_r[i] = i; |
| 6112 | intel_crtc->lut_g[i] = i; |
| 6113 | intel_crtc->lut_b[i] = i; |
| 6114 | } |
| 6115 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 6116 | /* Swap pipes & planes for FBC on pre-965 */ |
| 6117 | intel_crtc->pipe = pipe; |
| 6118 | intel_crtc->plane = pipe; |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 6119 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6120 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 6121 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 6122 | } |
| 6123 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 6124 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 6125 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 6126 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 6127 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 6128 | |
Chris Wilson | 5d1d0cc | 2011-01-24 15:02:15 +0000 | [diff] [blame] | 6129 | intel_crtc_reset(&intel_crtc->base); |
Chris Wilson | 04dbff5 | 2011-02-10 17:38:35 +0000 | [diff] [blame] | 6130 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 6131 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
Jesse Barnes | 7e7d76c | 2010-09-10 10:47:20 -0700 | [diff] [blame] | 6132 | |
| 6133 | if (HAS_PCH_SPLIT(dev)) { |
| 6134 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
| 6135 | intel_helper_funcs.commit = ironlake_crtc_commit; |
| 6136 | } else { |
| 6137 | intel_helper_funcs.prepare = i9xx_crtc_prepare; |
| 6138 | intel_helper_funcs.commit = i9xx_crtc_commit; |
| 6139 | } |
| 6140 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6141 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
| 6142 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6143 | intel_crtc->busy = false; |
| 6144 | |
| 6145 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, |
| 6146 | (unsigned long)intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6147 | } |
| 6148 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6149 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6150 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6151 | { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6152 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 6153 | struct drm_mode_object *drmmode_obj; |
| 6154 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6155 | |
Daniel Vetter | 1cff8f6 | 2012-04-24 09:55:08 +0200 | [diff] [blame] | 6156 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 6157 | return -ENODEV; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6158 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 6159 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 6160 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6161 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 6162 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6163 | DRM_ERROR("no such CRTC id\n"); |
| 6164 | return -EINVAL; |
| 6165 | } |
| 6166 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 6167 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 6168 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6169 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 6170 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 6171 | } |
| 6172 | |
Zhenyu Wang | c5e4df3 | 2010-03-30 14:39:27 +0800 | [diff] [blame] | 6173 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6174 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6175 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6176 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6177 | int entry = 0; |
| 6178 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6179 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 6180 | if (type_mask & encoder->clone_mask) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6181 | index_mask |= (1 << entry); |
| 6182 | entry++; |
| 6183 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6184 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6185 | return index_mask; |
| 6186 | } |
| 6187 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 6188 | static bool has_edp_a(struct drm_device *dev) |
| 6189 | { |
| 6190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6191 | |
| 6192 | if (!IS_MOBILE(dev)) |
| 6193 | return false; |
| 6194 | |
| 6195 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 6196 | return false; |
| 6197 | |
| 6198 | if (IS_GEN5(dev) && |
| 6199 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) |
| 6200 | return false; |
| 6201 | |
| 6202 | return true; |
| 6203 | } |
| 6204 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6205 | static void intel_setup_outputs(struct drm_device *dev) |
| 6206 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6207 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6208 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 6209 | bool dpd_is_edp = false; |
Chris Wilson | f3cfcba | 2012-02-09 09:35:53 +0000 | [diff] [blame] | 6210 | bool has_lvds; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6211 | |
Chris Wilson | f3cfcba | 2012-02-09 09:35:53 +0000 | [diff] [blame] | 6212 | has_lvds = intel_lvds_init(dev); |
Chris Wilson | c5d1b51 | 2010-11-29 18:00:23 +0000 | [diff] [blame] | 6213 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
| 6214 | /* disable the panel fitter on everything but LVDS */ |
| 6215 | I915_WRITE(PFIT_CONTROL, 0); |
| 6216 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6217 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 6218 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 6219 | dpd_is_edp = intel_dpd_is_edp(dev); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 6220 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 6221 | if (has_edp_a(dev)) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 6222 | intel_dp_init(dev, DP_A); |
| 6223 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 6224 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
| 6225 | intel_dp_init(dev, PCH_DP_D); |
| 6226 | } |
| 6227 | |
| 6228 | intel_crt_init(dev); |
| 6229 | |
| 6230 | if (HAS_PCH_SPLIT(dev)) { |
| 6231 | int found; |
| 6232 | |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 6233 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 6234 | /* PCH SDVOB multiplex with HDMIB */ |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 6235 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 6236 | if (!found) |
| 6237 | intel_hdmi_init(dev, HDMIB); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 6238 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
| 6239 | intel_dp_init(dev, PCH_DP_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 6240 | } |
| 6241 | |
| 6242 | if (I915_READ(HDMIC) & PORT_DETECTED) |
| 6243 | intel_hdmi_init(dev, HDMIC); |
| 6244 | |
| 6245 | if (I915_READ(HDMID) & PORT_DETECTED) |
| 6246 | intel_hdmi_init(dev, HDMID); |
| 6247 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 6248 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
| 6249 | intel_dp_init(dev, PCH_DP_C); |
| 6250 | |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 6251 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 6252 | intel_dp_init(dev, PCH_DP_D); |
| 6253 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 6254 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 6255 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 6256 | |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6257 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6258 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 6259 | found = intel_sdvo_init(dev, SDVOB, true); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6260 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 6261 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6262 | intel_hdmi_init(dev, SDVOB); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6263 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 6264 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6265 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
| 6266 | DRM_DEBUG_KMS("probing DP_B\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 6267 | intel_dp_init(dev, DP_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6268 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6269 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 6270 | |
| 6271 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 6272 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6273 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
| 6274 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 6275 | found = intel_sdvo_init(dev, SDVOC, false); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6276 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 6277 | |
| 6278 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { |
| 6279 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6280 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 6281 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6282 | intel_hdmi_init(dev, SDVOC); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6283 | } |
| 6284 | if (SUPPORTS_INTEGRATED_DP(dev)) { |
| 6285 | DRM_DEBUG_KMS("probing DP_C\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 6286 | intel_dp_init(dev, DP_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6287 | } |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 6288 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 6289 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6290 | if (SUPPORTS_INTEGRATED_DP(dev) && |
| 6291 | (I915_READ(DP_D) & DP_DETECTED)) { |
| 6292 | DRM_DEBUG_KMS("probing DP_D\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 6293 | intel_dp_init(dev, DP_D); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 6294 | } |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 6295 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6296 | intel_dvo_init(dev); |
| 6297 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 6298 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6299 | intel_tv_init(dev); |
| 6300 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 6301 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 6302 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 6303 | encoder->base.possible_clones = |
| 6304 | intel_encoder_clones(dev, encoder->clone_mask); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6305 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 6306 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 6307 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
| 6308 | drm_helper_disable_unused_functions(dev); |
Keith Packard | 9fb526d | 2011-09-26 22:24:57 -0700 | [diff] [blame] | 6309 | |
| 6310 | if (HAS_PCH_SPLIT(dev)) |
| 6311 | ironlake_init_pch_refclk(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6312 | } |
| 6313 | |
| 6314 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 6315 | { |
| 6316 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6317 | |
| 6318 | drm_framebuffer_cleanup(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6319 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6320 | |
| 6321 | kfree(intel_fb); |
| 6322 | } |
| 6323 | |
| 6324 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6325 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6326 | unsigned int *handle) |
| 6327 | { |
| 6328 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6329 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6330 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6331 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6332 | } |
| 6333 | |
| 6334 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 6335 | .destroy = intel_user_framebuffer_destroy, |
| 6336 | .create_handle = intel_user_framebuffer_create_handle, |
| 6337 | }; |
| 6338 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 6339 | int intel_framebuffer_init(struct drm_device *dev, |
| 6340 | struct intel_framebuffer *intel_fb, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6341 | struct drm_mode_fb_cmd2 *mode_cmd, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6342 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6343 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6344 | int ret; |
| 6345 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6346 | if (obj->tiling_mode == I915_TILING_Y) |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 6347 | return -EINVAL; |
| 6348 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6349 | if (mode_cmd->pitches[0] & 63) |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 6350 | return -EINVAL; |
| 6351 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6352 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 6353 | case DRM_FORMAT_RGB332: |
| 6354 | case DRM_FORMAT_RGB565: |
| 6355 | case DRM_FORMAT_XRGB8888: |
Jesse Barnes | b250da7 | 2012-03-07 08:49:29 -0800 | [diff] [blame] | 6356 | case DRM_FORMAT_XBGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 6357 | case DRM_FORMAT_ARGB8888: |
| 6358 | case DRM_FORMAT_XRGB2101010: |
| 6359 | case DRM_FORMAT_ARGB2101010: |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6360 | /* RGB formats are common across chipsets */ |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 6361 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 6362 | case DRM_FORMAT_YUYV: |
| 6363 | case DRM_FORMAT_UYVY: |
| 6364 | case DRM_FORMAT_YVYU: |
| 6365 | case DRM_FORMAT_VYUY: |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 6366 | break; |
| 6367 | default: |
Eugeni Dodonov | aca2584 | 2012-01-17 15:25:45 -0200 | [diff] [blame] | 6368 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
| 6369 | mode_cmd->pixel_format); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 6370 | return -EINVAL; |
| 6371 | } |
| 6372 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6373 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 6374 | if (ret) { |
| 6375 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 6376 | return ret; |
| 6377 | } |
| 6378 | |
| 6379 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6380 | intel_fb->obj = obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6381 | return 0; |
| 6382 | } |
| 6383 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6384 | static struct drm_framebuffer * |
| 6385 | intel_user_framebuffer_create(struct drm_device *dev, |
| 6386 | struct drm_file *filp, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6387 | struct drm_mode_fb_cmd2 *mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6388 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 6389 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6390 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 6391 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
| 6392 | mode_cmd->handles[0])); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 6393 | if (&obj->base == NULL) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 6394 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6395 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 6396 | return intel_framebuffer_create(dev, mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6397 | } |
| 6398 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6399 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6400 | .fb_create = intel_user_framebuffer_create, |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 6401 | .output_poll_changed = intel_fb_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6402 | }; |
| 6403 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6404 | /* Set up chip specific display functions */ |
| 6405 | static void intel_init_display(struct drm_device *dev) |
| 6406 | { |
| 6407 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6408 | |
| 6409 | /* We always want a DPMS function */ |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6410 | if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 6411 | dev_priv->display.dpms = ironlake_crtc_dpms; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6412 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6413 | dev_priv->display.off = ironlake_crtc_off; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 6414 | dev_priv->display.update_plane = ironlake_update_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6415 | } else { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6416 | dev_priv->display.dpms = i9xx_crtc_dpms; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6417 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6418 | dev_priv->display.off = i9xx_crtc_off; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 6419 | dev_priv->display.update_plane = i9xx_update_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 6420 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6421 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6422 | /* Returns the core display clock speed */ |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 6423 | if (IS_VALLEYVIEW(dev)) |
| 6424 | dev_priv->display.get_display_clock_speed = |
| 6425 | valleyview_get_display_clock_speed; |
| 6426 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6427 | dev_priv->display.get_display_clock_speed = |
| 6428 | i945_get_display_clock_speed; |
| 6429 | else if (IS_I915G(dev)) |
| 6430 | dev_priv->display.get_display_clock_speed = |
| 6431 | i915_get_display_clock_speed; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 6432 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6433 | dev_priv->display.get_display_clock_speed = |
| 6434 | i9xx_misc_get_display_clock_speed; |
| 6435 | else if (IS_I915GM(dev)) |
| 6436 | dev_priv->display.get_display_clock_speed = |
| 6437 | i915gm_get_display_clock_speed; |
| 6438 | else if (IS_I865G(dev)) |
| 6439 | dev_priv->display.get_display_clock_speed = |
| 6440 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 6441 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6442 | dev_priv->display.get_display_clock_speed = |
| 6443 | i855_get_display_clock_speed; |
| 6444 | else /* 852, 830 */ |
| 6445 | dev_priv->display.get_display_clock_speed = |
| 6446 | i830_get_display_clock_speed; |
| 6447 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 6448 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 6449 | if (IS_GEN5(dev)) { |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 6450 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6451 | dev_priv->display.write_eld = ironlake_write_eld; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 6452 | } else if (IS_GEN6(dev)) { |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 6453 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6454 | dev_priv->display.write_eld = ironlake_write_eld; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 6455 | } else if (IS_IVYBRIDGE(dev)) { |
| 6456 | /* FIXME: detect B0+ stepping and use auto training */ |
| 6457 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6458 | dev_priv->display.write_eld = ironlake_write_eld; |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 6459 | } else |
| 6460 | dev_priv->display.update_wm = NULL; |
Jesse Barnes | ceb0424 | 2012-03-28 13:39:22 -0700 | [diff] [blame] | 6461 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 6462 | dev_priv->display.force_wake_get = vlv_force_wake_get; |
| 6463 | dev_priv->display.force_wake_put = vlv_force_wake_put; |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 6464 | } else if (IS_G4X(dev)) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 6465 | dev_priv->display.write_eld = g4x_write_eld; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6466 | } |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 6467 | |
| 6468 | /* Default just returns -ENODEV to indicate unsupported */ |
| 6469 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 6470 | |
| 6471 | switch (INTEL_INFO(dev)->gen) { |
| 6472 | case 2: |
| 6473 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 6474 | break; |
| 6475 | |
| 6476 | case 3: |
| 6477 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 6478 | break; |
| 6479 | |
| 6480 | case 4: |
| 6481 | case 5: |
| 6482 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 6483 | break; |
| 6484 | |
| 6485 | case 6: |
| 6486 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 6487 | break; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 6488 | case 7: |
| 6489 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 6490 | break; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 6491 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6492 | } |
| 6493 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6494 | /* |
| 6495 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 6496 | * resume, or other times. This quirk makes sure that's the case for |
| 6497 | * affected systems. |
| 6498 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 6499 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6500 | { |
| 6501 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6502 | |
| 6503 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 6504 | DRM_INFO("applying pipe a force quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6505 | } |
| 6506 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 6507 | /* |
| 6508 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 6509 | */ |
| 6510 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 6511 | { |
| 6512 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6513 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 6514 | DRM_INFO("applying lvds SSC disable quirk\n"); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 6515 | } |
| 6516 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 6517 | /* |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 6518 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 6519 | * brightness value |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 6520 | */ |
| 6521 | static void quirk_invert_brightness(struct drm_device *dev) |
| 6522 | { |
| 6523 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6524 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 6525 | DRM_INFO("applying inverted panel brightness quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6526 | } |
| 6527 | |
| 6528 | struct intel_quirk { |
| 6529 | int device; |
| 6530 | int subsystem_vendor; |
| 6531 | int subsystem_device; |
| 6532 | void (*hook)(struct drm_device *dev); |
| 6533 | }; |
| 6534 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 6535 | static struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6536 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 6537 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6538 | |
| 6539 | /* Thinkpad R31 needs pipe A force quirk */ |
| 6540 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, |
| 6541 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 6542 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 6543 | |
| 6544 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ |
| 6545 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, |
| 6546 | /* ThinkPad X40 needs pipe A force quirk */ |
| 6547 | |
| 6548 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 6549 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 6550 | |
| 6551 | /* 855 & before need to leave pipe A & dpll A up */ |
| 6552 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
| 6553 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 6554 | |
| 6555 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 6556 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 6557 | |
| 6558 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 6559 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 6560 | |
| 6561 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 6562 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6563 | }; |
| 6564 | |
| 6565 | static void intel_init_quirks(struct drm_device *dev) |
| 6566 | { |
| 6567 | struct pci_dev *d = dev->pdev; |
| 6568 | int i; |
| 6569 | |
| 6570 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 6571 | struct intel_quirk *q = &intel_quirks[i]; |
| 6572 | |
| 6573 | if (d->device == q->device && |
| 6574 | (d->subsystem_vendor == q->subsystem_vendor || |
| 6575 | q->subsystem_vendor == PCI_ANY_ID) && |
| 6576 | (d->subsystem_device == q->subsystem_device || |
| 6577 | q->subsystem_device == PCI_ANY_ID)) |
| 6578 | q->hook(dev); |
| 6579 | } |
| 6580 | } |
| 6581 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 6582 | /* Disable the VGA plane that we never use */ |
| 6583 | static void i915_disable_vga(struct drm_device *dev) |
| 6584 | { |
| 6585 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6586 | u8 sr1; |
| 6587 | u32 vga_reg; |
| 6588 | |
| 6589 | if (HAS_PCH_SPLIT(dev)) |
| 6590 | vga_reg = CPU_VGACNTRL; |
| 6591 | else |
| 6592 | vga_reg = VGACNTRL; |
| 6593 | |
| 6594 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 3fdcf43 | 2012-04-06 11:46:27 -0700 | [diff] [blame] | 6595 | outb(SR01, VGA_SR_INDEX); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 6596 | sr1 = inb(VGA_SR_DATA); |
| 6597 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 6598 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 6599 | udelay(300); |
| 6600 | |
| 6601 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 6602 | POSTING_READ(vga_reg); |
| 6603 | } |
| 6604 | |
Jesse Barnes | f82cfb6 | 2012-04-11 09:23:35 -0700 | [diff] [blame] | 6605 | static void ivb_pch_pwm_override(struct drm_device *dev) |
| 6606 | { |
| 6607 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6608 | |
| 6609 | /* |
| 6610 | * IVB has CPU eDP backlight regs too, set things up to let the |
| 6611 | * PCH regs control the backlight |
| 6612 | */ |
| 6613 | I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE); |
| 6614 | I915_WRITE(BLC_PWM_CPU_CTL, 0); |
| 6615 | I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30)); |
| 6616 | } |
| 6617 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 6618 | void intel_modeset_init_hw(struct drm_device *dev) |
| 6619 | { |
| 6620 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6621 | |
| 6622 | intel_init_clock_gating(dev); |
| 6623 | |
| 6624 | if (IS_IRONLAKE_M(dev)) { |
| 6625 | ironlake_enable_drps(dev); |
| 6626 | intel_init_emon(dev); |
| 6627 | } |
| 6628 | |
Jesse Barnes | b6834bd | 2012-04-11 09:23:33 -0700 | [diff] [blame] | 6629 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 6630 | gen6_enable_rps(dev_priv); |
| 6631 | gen6_update_ring_freq(dev_priv); |
| 6632 | } |
Jesse Barnes | f82cfb6 | 2012-04-11 09:23:35 -0700 | [diff] [blame] | 6633 | |
| 6634 | if (IS_IVYBRIDGE(dev)) |
| 6635 | ivb_pch_pwm_override(dev); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 6636 | } |
| 6637 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6638 | void intel_modeset_init(struct drm_device *dev) |
| 6639 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6640 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 6641 | int i, ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6642 | |
| 6643 | drm_mode_config_init(dev); |
| 6644 | |
| 6645 | dev->mode_config.min_width = 0; |
| 6646 | dev->mode_config.min_height = 0; |
| 6647 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 6648 | dev->mode_config.preferred_depth = 24; |
| 6649 | dev->mode_config.prefer_shadow = 1; |
| 6650 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6651 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
| 6652 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 6653 | intel_init_quirks(dev); |
| 6654 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6655 | intel_init_pm(dev); |
| 6656 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6657 | intel_init_display(dev); |
| 6658 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6659 | if (IS_GEN2(dev)) { |
| 6660 | dev->mode_config.max_width = 2048; |
| 6661 | dev->mode_config.max_height = 2048; |
| 6662 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 6663 | dev->mode_config.max_width = 4096; |
| 6664 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6665 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 6666 | dev->mode_config.max_width = 8192; |
| 6667 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6668 | } |
Chris Wilson | 35c3047 | 2010-12-22 14:07:12 +0000 | [diff] [blame] | 6669 | dev->mode_config.fb_base = dev->agp->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6670 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 6671 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6672 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6673 | |
Dave Airlie | a3524f1 | 2010-06-06 18:59:41 +1000 | [diff] [blame] | 6674 | for (i = 0; i < dev_priv->num_pipe; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6675 | intel_crtc_init(dev, i); |
Jesse Barnes | 00c2064b | 2012-01-13 15:48:39 -0800 | [diff] [blame] | 6676 | ret = intel_plane_init(dev, i); |
| 6677 | if (ret) |
| 6678 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6679 | } |
| 6680 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6681 | intel_pch_pll_init(dev); |
| 6682 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 6683 | /* Just disable it once at startup */ |
| 6684 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6685 | intel_setup_outputs(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6686 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 6687 | intel_modeset_init_hw(dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 6688 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6689 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
| 6690 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
| 6691 | (unsigned long)dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 6692 | } |
| 6693 | |
| 6694 | void intel_modeset_gem_init(struct drm_device *dev) |
| 6695 | { |
| 6696 | if (IS_IRONLAKE_M(dev)) |
| 6697 | ironlake_enable_rc6(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 6698 | |
| 6699 | intel_setup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6700 | } |
| 6701 | |
| 6702 | void intel_modeset_cleanup(struct drm_device *dev) |
| 6703 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6704 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6705 | struct drm_crtc *crtc; |
| 6706 | struct intel_crtc *intel_crtc; |
| 6707 | |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 6708 | drm_kms_helper_poll_fini(dev); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6709 | mutex_lock(&dev->struct_mutex); |
| 6710 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 6711 | intel_unregister_dsm_handler(); |
| 6712 | |
| 6713 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6714 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 6715 | /* Skip inactive CRTCs */ |
| 6716 | if (!crtc->fb) |
| 6717 | continue; |
| 6718 | |
| 6719 | intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 6720 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 6721 | } |
| 6722 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 6723 | intel_disable_fbc(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 6724 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 6725 | if (IS_IRONLAKE_M(dev)) |
| 6726 | ironlake_disable_drps(dev); |
Jesse Barnes | b6834bd | 2012-04-11 09:23:33 -0700 | [diff] [blame] | 6727 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 6728 | gen6_disable_rps(dev); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 6729 | |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 6730 | if (IS_IRONLAKE_M(dev)) |
| 6731 | ironlake_disable_rc6(dev); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 6732 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 6733 | if (IS_VALLEYVIEW(dev)) |
| 6734 | vlv_init_dpio(dev); |
| 6735 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 6736 | mutex_unlock(&dev->struct_mutex); |
| 6737 | |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 6738 | /* Disable the irq before mode object teardown, for the irq might |
| 6739 | * enqueue unpin/hotplug work. */ |
| 6740 | drm_irq_uninstall(dev); |
| 6741 | cancel_work_sync(&dev_priv->hotplug_work); |
Daniel Vetter | 6fdd4d9 | 2011-09-08 14:00:22 +0200 | [diff] [blame] | 6742 | cancel_work_sync(&dev_priv->rps_work); |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 6743 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 6744 | /* flush any delayed tasks or pending work */ |
| 6745 | flush_scheduled_work(); |
| 6746 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 6747 | /* Shut off idle work before the crtcs get freed. */ |
| 6748 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 6749 | intel_crtc = to_intel_crtc(crtc); |
| 6750 | del_timer_sync(&intel_crtc->idle_timer); |
| 6751 | } |
| 6752 | del_timer_sync(&dev_priv->idle_timer); |
| 6753 | cancel_work_sync(&dev_priv->idle_work); |
| 6754 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6755 | drm_mode_config_cleanup(dev); |
| 6756 | } |
| 6757 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 6758 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 6759 | * Return which encoder is currently attached for connector. |
| 6760 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6761 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6762 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6763 | return &intel_attached_encoder(connector)->base; |
| 6764 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6765 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 6766 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 6767 | struct intel_encoder *encoder) |
| 6768 | { |
| 6769 | connector->encoder = encoder; |
| 6770 | drm_mode_connector_attach_encoder(&connector->base, |
| 6771 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6772 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 6773 | |
| 6774 | /* |
| 6775 | * set vga decode state - true == enable VGA decode |
| 6776 | */ |
| 6777 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 6778 | { |
| 6779 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6780 | u16 gmch_ctrl; |
| 6781 | |
| 6782 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); |
| 6783 | if (state) |
| 6784 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 6785 | else |
| 6786 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
| 6787 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); |
| 6788 | return 0; |
| 6789 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 6790 | |
| 6791 | #ifdef CONFIG_DEBUG_FS |
| 6792 | #include <linux/seq_file.h> |
| 6793 | |
| 6794 | struct intel_display_error_state { |
| 6795 | struct intel_cursor_error_state { |
| 6796 | u32 control; |
| 6797 | u32 position; |
| 6798 | u32 base; |
| 6799 | u32 size; |
| 6800 | } cursor[2]; |
| 6801 | |
| 6802 | struct intel_pipe_error_state { |
| 6803 | u32 conf; |
| 6804 | u32 source; |
| 6805 | |
| 6806 | u32 htotal; |
| 6807 | u32 hblank; |
| 6808 | u32 hsync; |
| 6809 | u32 vtotal; |
| 6810 | u32 vblank; |
| 6811 | u32 vsync; |
| 6812 | } pipe[2]; |
| 6813 | |
| 6814 | struct intel_plane_error_state { |
| 6815 | u32 control; |
| 6816 | u32 stride; |
| 6817 | u32 size; |
| 6818 | u32 pos; |
| 6819 | u32 addr; |
| 6820 | u32 surface; |
| 6821 | u32 tile_offset; |
| 6822 | } plane[2]; |
| 6823 | }; |
| 6824 | |
| 6825 | struct intel_display_error_state * |
| 6826 | intel_display_capture_error_state(struct drm_device *dev) |
| 6827 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 6828 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 6829 | struct intel_display_error_state *error; |
| 6830 | int i; |
| 6831 | |
| 6832 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 6833 | if (error == NULL) |
| 6834 | return NULL; |
| 6835 | |
| 6836 | for (i = 0; i < 2; i++) { |
| 6837 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 6838 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 6839 | error->cursor[i].base = I915_READ(CURBASE(i)); |
| 6840 | |
| 6841 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 6842 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
| 6843 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 6844 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 6845 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
| 6846 | if (INTEL_INFO(dev)->gen >= 4) { |
| 6847 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 6848 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 6849 | } |
| 6850 | |
| 6851 | error->pipe[i].conf = I915_READ(PIPECONF(i)); |
| 6852 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
| 6853 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); |
| 6854 | error->pipe[i].hblank = I915_READ(HBLANK(i)); |
| 6855 | error->pipe[i].hsync = I915_READ(HSYNC(i)); |
| 6856 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); |
| 6857 | error->pipe[i].vblank = I915_READ(VBLANK(i)); |
| 6858 | error->pipe[i].vsync = I915_READ(VSYNC(i)); |
| 6859 | } |
| 6860 | |
| 6861 | return error; |
| 6862 | } |
| 6863 | |
| 6864 | void |
| 6865 | intel_display_print_error_state(struct seq_file *m, |
| 6866 | struct drm_device *dev, |
| 6867 | struct intel_display_error_state *error) |
| 6868 | { |
| 6869 | int i; |
| 6870 | |
| 6871 | for (i = 0; i < 2; i++) { |
| 6872 | seq_printf(m, "Pipe [%d]:\n", i); |
| 6873 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
| 6874 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); |
| 6875 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); |
| 6876 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); |
| 6877 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); |
| 6878 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); |
| 6879 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); |
| 6880 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); |
| 6881 | |
| 6882 | seq_printf(m, "Plane [%d]:\n", i); |
| 6883 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 6884 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
| 6885 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 6886 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
| 6887 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
| 6888 | if (INTEL_INFO(dev)->gen >= 4) { |
| 6889 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 6890 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
| 6891 | } |
| 6892 | |
| 6893 | seq_printf(m, "Cursor [%d]:\n", i); |
| 6894 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 6895 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 6896 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); |
| 6897 | } |
| 6898 | } |
| 6899 | #endif |