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Kristian Høgsbergc781c062007-05-07 20:33:32 -04001/*
2 * Driver for OHCI 1394 controllers
Kristian Høgsberged568912006-12-19 19:58:35 -05003 *
Kristian Høgsberged568912006-12-19 19:58:35 -05004 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
Maxim Levitskydd237362010-11-29 04:09:50 +020021#include <linux/bitops.h>
Stefan Richter65b27422010-06-12 20:26:51 +020022#include <linux/bug.h>
Stefan Richtere524f6162007-08-20 21:58:30 +020023#include <linux/compiler.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050024#include <linux/delay.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020025#include <linux/device.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080026#include <linux/dma-mapping.h>
Stefan Richter77c9a5d2009-06-05 16:26:18 +020027#include <linux/firewire.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020028#include <linux/firewire-constants.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020029#include <linux/init.h>
30#include <linux/interrupt.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020031#include <linux/io.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020032#include <linux/kernel.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020033#include <linux/list.h>
Al Virofaa2fb42007-05-15 20:36:10 +010034#include <linux/mm.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020035#include <linux/module.h>
Stefan Richterad3c0fe2008-03-20 22:04:36 +010036#include <linux/moduleparam.h>
Stefan Richter02d37be2010-07-08 16:09:06 +020037#include <linux/mutex.h>
Stefan Richtera7fb60d2007-08-20 21:41:22 +020038#include <linux/pci.h>
Stefan Richterfc383792009-08-28 13:25:15 +020039#include <linux/pci_ids.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090040#include <linux/slab.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020041#include <linux/spinlock.h>
Stefan Richtere8ca9702009-06-04 21:09:38 +020042#include <linux/string.h>
Stefan Richtere78483c2010-08-02 09:33:25 +020043#include <linux/time.h>
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +010044#include <linux/vmalloc.h>
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +020045#include <linux/workqueue.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080046
Stefan Richtere8ca9702009-06-04 21:09:38 +020047#include <asm/byteorder.h>
Stefan Richterc26f0232007-08-20 21:40:30 +020048#include <asm/page.h>
Kristian Høgsberged568912006-12-19 19:58:35 -050049
Stefan Richterea8d0062008-03-01 02:42:56 +010050#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
Stefan Richter77c9a5d2009-06-05 16:26:18 +020054#include "core.h"
55#include "ohci.h"
Kristian Høgsberged568912006-12-19 19:58:35 -050056
Kristian Høgsberga77754a2007-05-07 20:33:35 -040057#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
Kristian Høgsberged568912006-12-19 19:58:35 -050070
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
Kristian Høgsberga77754a2007-05-07 20:33:35 -040080#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050084
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +010085#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
Kristian Høgsberg32b46092007-02-06 14:49:30 -050093
Kristian Høgsberged568912006-12-19 19:58:35 -050094struct ar_context {
95 struct fw_ohci *ohci;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +010096 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500100 void *pointer;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100101 unsigned int last_buffer_index;
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500102 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -0500103 struct tasklet_struct tasklet;
104};
105
Kristian Høgsberg30200732007-02-16 17:34:39 -0500106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
David Moorefe5ca632008-01-06 17:21:41 -0500111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
Kristian Høgsberg30200732007-02-16 17:34:39 -0500124struct context {
Stefan Richter373b2ed2007-03-04 14:45:18 +0100125 struct fw_ohci *ohci;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500126 u32 regs;
David Moorefe5ca632008-01-06 17:21:41 -0500127 int total_allocation;
Clemens Ladischa572e682011-10-15 23:12:23 +0200128 u32 current_bus;
Clemens Ladisch386a4152010-12-24 14:42:46 +0100129 bool running;
Clemens Ladisch82b662d2010-12-24 14:40:15 +0100130 bool flushing;
Stefan Richter373b2ed2007-03-04 14:45:18 +0100131
David Moorefe5ca632008-01-06 17:21:41 -0500132 /*
133 * List of page-sized buffers for storing DMA descriptors.
134 * Head of list contains buffers in use and tail of list contains
135 * free buffers.
136 */
137 struct list_head buffer_list;
138
139 /*
140 * Pointer to a buffer inside buffer_list that contains the tail
141 * end of the current DMA program.
142 */
143 struct descriptor_buffer *buffer_tail;
144
145 /*
146 * The descriptor containing the branch address of the first
147 * descriptor that has not yet been filled by the device.
148 */
149 struct descriptor *last;
150
151 /*
152 * The last descriptor in the DMA program. It contains the branch
153 * address that must be updated upon appending a new descriptor.
154 */
155 struct descriptor *prev;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500156
157 descriptor_callback_t callback;
158
Stefan Richter373b2ed2007-03-04 14:45:18 +0100159 struct tasklet_struct tasklet;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500160};
Kristian Høgsberg30200732007-02-16 17:34:39 -0500161
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400162#define IT_HEADER_SY(v) ((v) << 0)
163#define IT_HEADER_TCODE(v) ((v) << 4)
164#define IT_HEADER_CHANNEL(v) ((v) << 8)
165#define IT_HEADER_TAG(v) ((v) << 14)
166#define IT_HEADER_SPEED(v) ((v) << 16)
167#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
Kristian Høgsberged568912006-12-19 19:58:35 -0500168
169struct iso_context {
170 struct fw_iso_context base;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500171 struct context context;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500172 void *header;
173 size_t header_length;
Clemens Ladischd1bbd202012-03-18 19:06:39 +0100174 unsigned long flushing_completions;
175 u32 mc_buffer_bus;
176 u16 mc_completed;
Clemens Ladisch910e76c2012-03-18 19:04:43 +0100177 u16 last_timestamp;
Maxim Levitskydd237362010-11-29 04:09:50 +0200178 u8 sync;
179 u8 tags;
Kristian Høgsberged568912006-12-19 19:58:35 -0500180};
181
182#define CONFIG_ROM_SIZE 1024
183
184struct fw_ohci {
185 struct fw_card card;
186
187 __iomem char *registers;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500188 int node_id;
Kristian Høgsberged568912006-12-19 19:58:35 -0500189 int generation;
Stefan Richtere09770d2008-03-11 02:23:29 +0100190 int request_generation; /* for timestamping incoming requests */
Stefan Richter4a635592010-02-21 17:58:01 +0100191 unsigned quirks;
Clemens Ladischa1a11322010-06-10 08:35:06 +0200192 unsigned int pri_req_max;
Clemens Ladischa48777e2010-06-10 08:33:07 +0200193 u32 bus_time;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +0200194 bool is_root;
Stefan Richterc8a94de2010-06-12 20:34:50 +0200195 bool csr_state_setclear_abdicate;
Maxim Levitskydd237362010-11-29 04:09:50 +0200196 int n_ir;
197 int n_it;
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400198 /*
199 * Spinlock for accessing fw_ohci data. Never call out of
200 * this driver with this lock held.
201 */
Kristian Høgsberged568912006-12-19 19:58:35 -0500202 spinlock_t lock;
Kristian Høgsberged568912006-12-19 19:58:35 -0500203
Stefan Richter02d37be2010-07-08 16:09:06 +0200204 struct mutex phy_reg_mutex;
205
Clemens Ladischec766a72010-11-30 08:25:17 +0100206 void *misc_buffer;
207 dma_addr_t misc_buffer_bus;
208
Kristian Høgsberged568912006-12-19 19:58:35 -0500209 struct ar_context ar_request_ctx;
210 struct ar_context ar_response_ctx;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -0500211 struct context at_request_ctx;
212 struct context at_response_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -0500213
Clemens Ladischf117a3e2011-01-10 17:21:35 +0100214 u32 it_context_support;
Stefan Richter872e3302010-07-29 18:19:22 +0200215 u32 it_context_mask; /* unoccupied IT contexts */
Kristian Høgsberged568912006-12-19 19:58:35 -0500216 struct iso_context *it_context_list;
Stefan Richter872e3302010-07-29 18:19:22 +0200217 u64 ir_context_channels; /* unoccupied channels */
Clemens Ladischf117a3e2011-01-10 17:21:35 +0100218 u32 ir_context_support;
Stefan Richter872e3302010-07-29 18:19:22 +0200219 u32 ir_context_mask; /* unoccupied IR contexts */
Kristian Høgsberged568912006-12-19 19:58:35 -0500220 struct iso_context *ir_context_list;
Stefan Richter872e3302010-07-29 18:19:22 +0200221 u64 mc_channels; /* channels in use by the multichannel IR context */
222 bool mc_allocated;
Stefan Richterecb1cf92010-02-21 17:57:32 +0100223
224 __be32 *config_rom;
225 dma_addr_t config_rom_bus;
226 __be32 *next_config_rom;
227 dma_addr_t next_config_rom_bus;
228 __be32 next_header;
229
230 __le32 *self_id_cpu;
231 dma_addr_t self_id_bus;
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +0200232 struct work_struct bus_reset_work;
Stefan Richterecb1cf92010-02-21 17:57:32 +0100233
234 u32 self_id_buffer[512];
Kristian Høgsberged568912006-12-19 19:58:35 -0500235};
236
Adrian Bunk95688e92007-01-22 19:17:37 +0100237static inline struct fw_ohci *fw_ohci(struct fw_card *card)
Kristian Høgsberged568912006-12-19 19:58:35 -0500238{
239 return container_of(card, struct fw_ohci, card);
240}
241
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500242#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
243#define IR_CONTEXT_BUFFER_FILL 0x80000000
244#define IR_CONTEXT_ISOCH_HEADER 0x40000000
245#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
246#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
247#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
Kristian Høgsberged568912006-12-19 19:58:35 -0500248
249#define CONTEXT_RUN 0x8000
250#define CONTEXT_WAKE 0x1000
251#define CONTEXT_DEAD 0x0800
252#define CONTEXT_ACTIVE 0x0400
253
Stefan Richter8b7b6af2009-01-20 19:10:58 +0100254#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
Kristian Høgsberged568912006-12-19 19:58:35 -0500255#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
256#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
257
Kristian Høgsberged568912006-12-19 19:58:35 -0500258#define OHCI1394_REGISTER_SIZE 0x800
Kristian Høgsberged568912006-12-19 19:58:35 -0500259#define OHCI1394_PCI_HCI_Control 0x40
260#define SELF_ID_BUF_SIZE 0x800
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500261#define OHCI_TCODE_PHY_PACKET 0x0e
Kristian Høgsberge364cf42007-02-16 17:34:49 -0500262#define OHCI_VERSION_1_1 0x010010
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500263
Kristian Høgsberged568912006-12-19 19:58:35 -0500264static char ohci_driver_name[] = KBUILD_MODNAME;
265
Stefan Richter9993e0f2010-12-07 20:32:40 +0100266#define PCI_DEVICE_ID_AGERE_FW643 0x5901
Clemens Ladischd1bb3992012-01-26 22:05:58 +0100267#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
Clemens Ladisch262444e2010-06-05 12:31:25 +0200268#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
Clemens Ladisch8301b912010-03-17 11:07:55 +0100269#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
Stephan Gatzka25935eb2011-09-12 22:23:53 +0200270#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
271#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
Stefan Richter7f7e37112011-07-10 00:23:03 +0200272#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
Clemens Ladisch8301b912010-03-17 11:07:55 +0100273
Stefan Richter4a635592010-02-21 17:58:01 +0100274#define QUIRK_CYCLE_TIMER 1
275#define QUIRK_RESET_PACKET 2
276#define QUIRK_BE_HEADERS 4
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200277#define QUIRK_NO_1394A 8
Clemens Ladisch262444e2010-06-05 12:31:25 +0200278#define QUIRK_NO_MSI 16
Stephan Gatzka25935eb2011-09-12 22:23:53 +0200279#define QUIRK_TI_SLLZ059 32
Stefan Richter4a635592010-02-21 17:58:01 +0100280
281/* In case of multiple matches in ohci_quirks[], only the first one is used. */
282static const struct {
Stefan Richter9993e0f2010-12-07 20:32:40 +0100283 unsigned short vendor, device, revision, flags;
Stefan Richter4a635592010-02-21 17:58:01 +0100284} ohci_quirks[] = {
Stefan Richter9993e0f2010-12-07 20:32:40 +0100285 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
286 QUIRK_CYCLE_TIMER},
287
288 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
289 QUIRK_BE_HEADERS},
290
291 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
292 QUIRK_NO_MSI},
293
Clemens Ladischd1bb3992012-01-26 22:05:58 +0100294 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
295 QUIRK_RESET_PACKET},
296
Stefan Richter9993e0f2010-12-07 20:32:40 +0100297 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
298 QUIRK_NO_MSI},
299
300 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
301 QUIRK_CYCLE_TIMER},
302
Ming Leif39aa302011-08-31 10:45:46 +0800303 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
304 QUIRK_NO_MSI},
305
Stefan Richter9993e0f2010-12-07 20:32:40 +0100306 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
Stefan Richter320cfa62012-01-29 12:41:15 +0100307 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
Stefan Richter9993e0f2010-12-07 20:32:40 +0100308
309 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
310 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
311
Stephan Gatzka25935eb2011-09-12 22:23:53 +0200312 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
313 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
314
315 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
316 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
317
Stefan Richter9993e0f2010-12-07 20:32:40 +0100318 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
319 QUIRK_RESET_PACKET},
320
321 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
322 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
Stefan Richter4a635592010-02-21 17:58:01 +0100323};
324
Stefan Richter3e9cc2f2010-02-21 17:58:29 +0100325/* This overrides anything that was found in ohci_quirks[]. */
326static int param_quirks;
327module_param_named(quirks, param_quirks, int, 0644);
328MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
329 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
330 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
331 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200332 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
Clemens Ladisch262444e2010-06-05 12:31:25 +0200333 ", disable MSI = " __stringify(QUIRK_NO_MSI)
Stefan Richter28897fb2011-09-19 00:17:37 +0200334 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
Stefan Richter3e9cc2f2010-02-21 17:58:29 +0100335 ")");
336
Stefan Richtera007bb82008-04-07 22:33:35 +0200337#define OHCI_PARAM_DEBUG_AT_AR 1
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100338#define OHCI_PARAM_DEBUG_SELFIDS 2
Stefan Richtera007bb82008-04-07 22:33:35 +0200339#define OHCI_PARAM_DEBUG_IRQS 4
340#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100341
342static int param_debug;
343module_param_named(debug, param_debug, int, 0644);
344MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100345 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
Stefan Richtera007bb82008-04-07 22:33:35 +0200346 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
347 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
348 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100349 ", or a combination, or all = -1)");
350
Stefan Richter64d21722011-12-20 21:32:46 +0100351static void log_irqs(struct fw_ohci *ohci, u32 evt)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100352{
Stefan Richtera007bb82008-04-07 22:33:35 +0200353 if (likely(!(param_debug &
354 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100355 return;
356
Stefan Richtera007bb82008-04-07 22:33:35 +0200357 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
358 !(evt & OHCI1394_busReset))
359 return;
360
Stefan Richter64d21722011-12-20 21:32:46 +0100361 dev_notice(ohci->card.device,
362 "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
Stefan Richter161b96e2008-06-14 14:23:43 +0200363 evt & OHCI1394_selfIDComplete ? " selfID" : "",
364 evt & OHCI1394_RQPkt ? " AR_req" : "",
365 evt & OHCI1394_RSPkt ? " AR_resp" : "",
366 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
367 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
368 evt & OHCI1394_isochRx ? " IR" : "",
369 evt & OHCI1394_isochTx ? " IT" : "",
370 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
371 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
Clemens Ladischa48777e2010-06-10 08:33:07 +0200372 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
Jay Fenlason5ed1f322009-11-17 12:29:17 -0500373 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
Stefan Richter161b96e2008-06-14 14:23:43 +0200374 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
Clemens Ladischf117a3e2011-01-10 17:21:35 +0100375 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
Stefan Richter161b96e2008-06-14 14:23:43 +0200376 evt & OHCI1394_busReset ? " busReset" : "",
377 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
378 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
379 OHCI1394_respTxComplete | OHCI1394_isochRx |
380 OHCI1394_isochTx | OHCI1394_postedWriteErr |
Clemens Ladischa48777e2010-06-10 08:33:07 +0200381 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
382 OHCI1394_cycleInconsistent |
Stefan Richter161b96e2008-06-14 14:23:43 +0200383 OHCI1394_regAccessFail | OHCI1394_busReset)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100384 ? " ?" : "");
385}
386
387static const char *speed[] = {
388 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
389};
390static const char *power[] = {
391 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
392 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
393};
394static const char port[] = { '.', '-', 'p', 'c', };
395
396static char _p(u32 *s, int shift)
397{
398 return port[*s >> shift & 3];
399}
400
Stefan Richter64d21722011-12-20 21:32:46 +0100401static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100402{
Stefan Richter64d21722011-12-20 21:32:46 +0100403 u32 *s;
404
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100405 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
406 return;
407
Stefan Richter64d21722011-12-20 21:32:46 +0100408 dev_notice(ohci->card.device,
409 "%d selfIDs, generation %d, local node ID %04x\n",
410 self_id_count, generation, ohci->node_id);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100411
Stefan Richter64d21722011-12-20 21:32:46 +0100412 for (s = ohci->self_id_buffer; self_id_count--; ++s)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100413 if ((*s & 1 << 23) == 0)
Stefan Richter64d21722011-12-20 21:32:46 +0100414 dev_notice(ohci->card.device,
415 "selfID 0: %08x, phy %d [%c%c%c] "
Stefan Richter161b96e2008-06-14 14:23:43 +0200416 "%s gc=%d %s %s%s%s\n",
417 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
418 speed[*s >> 14 & 3], *s >> 16 & 63,
419 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
420 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100421 else
Stefan Richter64d21722011-12-20 21:32:46 +0100422 dev_notice(ohci->card.device,
423 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
Stefan Richter161b96e2008-06-14 14:23:43 +0200424 *s, *s >> 24 & 63,
425 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
426 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100427}
428
429static const char *evts[] = {
430 [0x00] = "evt_no_status", [0x01] = "-reserved-",
431 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
432 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
433 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
434 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
435 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
436 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
437 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
438 [0x10] = "-reserved-", [0x11] = "ack_complete",
439 [0x12] = "ack_pending ", [0x13] = "-reserved-",
440 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
441 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
442 [0x18] = "-reserved-", [0x19] = "-reserved-",
443 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
444 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
445 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
446 [0x20] = "pending/cancelled",
447};
448static const char *tcodes[] = {
449 [0x0] = "QW req", [0x1] = "BW req",
450 [0x2] = "W resp", [0x3] = "-reserved-",
451 [0x4] = "QR req", [0x5] = "BR req",
452 [0x6] = "QR resp", [0x7] = "BR resp",
453 [0x8] = "cycle start", [0x9] = "Lk req",
454 [0xa] = "async stream packet", [0xb] = "Lk resp",
455 [0xc] = "-reserved-", [0xd] = "-reserved-",
456 [0xe] = "link internal", [0xf] = "-reserved-",
457};
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100458
Stefan Richter64d21722011-12-20 21:32:46 +0100459static void log_ar_at_event(struct fw_ohci *ohci,
460 char dir, int speed, u32 *header, int evt)
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100461{
462 int tcode = header[0] >> 4 & 0xf;
463 char specific[12];
464
465 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
466 return;
467
468 if (unlikely(evt >= ARRAY_SIZE(evts)))
469 evt = 0x1f;
470
Stefan Richter08ddb2f2008-04-11 00:51:15 +0200471 if (evt == OHCI1394_evt_bus_reset) {
Stefan Richter64d21722011-12-20 21:32:46 +0100472 dev_notice(ohci->card.device,
473 "A%c evt_bus_reset, generation %d\n",
474 dir, (header[2] >> 16) & 0xff);
Stefan Richter08ddb2f2008-04-11 00:51:15 +0200475 return;
476 }
477
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100478 switch (tcode) {
479 case 0x0: case 0x6: case 0x8:
480 snprintf(specific, sizeof(specific), " = %08x",
481 be32_to_cpu((__force __be32)header[3]));
482 break;
483 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
484 snprintf(specific, sizeof(specific), " %x,%x",
485 header[3] >> 16, header[3] & 0xffff);
486 break;
487 default:
488 specific[0] = '\0';
489 }
490
491 switch (tcode) {
Clemens Ladisch5b06db12010-11-30 08:24:47 +0100492 case 0xa:
Stefan Richter64d21722011-12-20 21:32:46 +0100493 dev_notice(ohci->card.device,
494 "A%c %s, %s\n",
495 dir, evts[evt], tcodes[tcode]);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100496 break;
Clemens Ladisch5b06db12010-11-30 08:24:47 +0100497 case 0xe:
Stefan Richter64d21722011-12-20 21:32:46 +0100498 dev_notice(ohci->card.device,
499 "A%c %s, PHY %08x %08x\n",
500 dir, evts[evt], header[1], header[2]);
Clemens Ladisch5b06db12010-11-30 08:24:47 +0100501 break;
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100502 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
Stefan Richter64d21722011-12-20 21:32:46 +0100503 dev_notice(ohci->card.device,
504 "A%c spd %x tl %02x, "
505 "%04x -> %04x, %s, "
506 "%s, %04x%08x%s\n",
507 dir, speed, header[0] >> 10 & 0x3f,
508 header[1] >> 16, header[0] >> 16, evts[evt],
509 tcodes[tcode], header[1] & 0xffff, header[2], specific);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100510 break;
511 default:
Stefan Richter64d21722011-12-20 21:32:46 +0100512 dev_notice(ohci->card.device,
513 "A%c spd %x tl %02x, "
514 "%04x -> %04x, %s, "
515 "%s%s\n",
516 dir, speed, header[0] >> 10 & 0x3f,
517 header[1] >> 16, header[0] >> 16, evts[evt],
518 tcodes[tcode], specific);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100519 }
520}
521
Adrian Bunk95688e92007-01-22 19:17:37 +0100522static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
Kristian Høgsberged568912006-12-19 19:58:35 -0500523{
524 writel(data, ohci->registers + offset);
525}
526
Adrian Bunk95688e92007-01-22 19:17:37 +0100527static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
Kristian Høgsberged568912006-12-19 19:58:35 -0500528{
529 return readl(ohci->registers + offset);
530}
531
Adrian Bunk95688e92007-01-22 19:17:37 +0100532static inline void flush_writes(const struct fw_ohci *ohci)
Kristian Høgsberged568912006-12-19 19:58:35 -0500533{
534 /* Do a dummy read to flush writes. */
535 reg_read(ohci, OHCI1394_Version);
536}
537
Stefan Richterb14c3692011-06-21 15:24:26 +0200538/*
539 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
540 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
541 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
542 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
543 */
Stefan Richter35d999b2010-04-10 16:04:56 +0200544static int read_phy_reg(struct fw_ohci *ohci, int addr)
Kristian Høgsberged568912006-12-19 19:58:35 -0500545{
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200546 u32 val;
Stefan Richter35d999b2010-04-10 16:04:56 +0200547 int i;
Kristian Høgsberged568912006-12-19 19:58:35 -0500548
549 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
Clemens Ladisch153e3972010-06-10 08:22:07 +0200550 for (i = 0; i < 3 + 100; i++) {
Stefan Richter35d999b2010-04-10 16:04:56 +0200551 val = reg_read(ohci, OHCI1394_PhyControl);
Stefan Richter215fa442011-06-22 21:05:08 +0200552 if (!~val)
553 return -ENODEV; /* Card was ejected. */
554
Stefan Richter35d999b2010-04-10 16:04:56 +0200555 if (val & OHCI1394_PhyControl_ReadDone)
556 return OHCI1394_PhyControl_ReadData(val);
557
Clemens Ladisch153e3972010-06-10 08:22:07 +0200558 /*
559 * Try a few times without waiting. Sleeping is necessary
560 * only when the link/PHY interface is busy.
561 */
562 if (i >= 3)
563 msleep(1);
Kristian Høgsberged568912006-12-19 19:58:35 -0500564 }
Stefan Richter64d21722011-12-20 21:32:46 +0100565 dev_err(ohci->card.device, "failed to read phy reg\n");
Kristian Høgsberged568912006-12-19 19:58:35 -0500566
Stefan Richter35d999b2010-04-10 16:04:56 +0200567 return -EBUSY;
568}
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200569
Stefan Richter35d999b2010-04-10 16:04:56 +0200570static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
571{
572 int i;
573
574 reg_write(ohci, OHCI1394_PhyControl,
575 OHCI1394_PhyControl_Write(addr, val));
Clemens Ladisch153e3972010-06-10 08:22:07 +0200576 for (i = 0; i < 3 + 100; i++) {
Stefan Richter35d999b2010-04-10 16:04:56 +0200577 val = reg_read(ohci, OHCI1394_PhyControl);
Stefan Richter215fa442011-06-22 21:05:08 +0200578 if (!~val)
579 return -ENODEV; /* Card was ejected. */
580
Stefan Richter35d999b2010-04-10 16:04:56 +0200581 if (!(val & OHCI1394_PhyControl_WritePending))
582 return 0;
583
Clemens Ladisch153e3972010-06-10 08:22:07 +0200584 if (i >= 3)
585 msleep(1);
Stefan Richter35d999b2010-04-10 16:04:56 +0200586 }
Stefan Richter64d21722011-12-20 21:32:46 +0100587 dev_err(ohci->card.device, "failed to write phy reg\n");
Stefan Richter35d999b2010-04-10 16:04:56 +0200588
589 return -EBUSY;
Clemens Ladisch4a96b4f2010-04-04 15:19:52 +0200590}
591
Stefan Richter02d37be2010-07-08 16:09:06 +0200592static int update_phy_reg(struct fw_ohci *ohci, int addr,
593 int clear_bits, int set_bits)
Kristian Høgsberged568912006-12-19 19:58:35 -0500594{
Stefan Richter02d37be2010-07-08 16:09:06 +0200595 int ret = read_phy_reg(ohci, addr);
Stefan Richter35d999b2010-04-10 16:04:56 +0200596 if (ret < 0)
597 return ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500598
Clemens Ladische7014da2010-04-01 16:40:18 +0200599 /*
600 * The interrupt status bits are cleared by writing a one bit.
601 * Avoid clearing them unless explicitly requested in set_bits.
602 */
603 if (addr == 5)
604 clear_bits |= PHY_INT_STATUS_BITS;
Kristian Høgsberged568912006-12-19 19:58:35 -0500605
Stefan Richter35d999b2010-04-10 16:04:56 +0200606 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
Kristian Høgsberged568912006-12-19 19:58:35 -0500607}
608
Stefan Richter35d999b2010-04-10 16:04:56 +0200609static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200610{
Stefan Richter35d999b2010-04-10 16:04:56 +0200611 int ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200612
Stefan Richter02d37be2010-07-08 16:09:06 +0200613 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
Stefan Richter35d999b2010-04-10 16:04:56 +0200614 if (ret < 0)
615 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +0200616
Stefan Richter35d999b2010-04-10 16:04:56 +0200617 return read_phy_reg(ohci, addr);
Kristian Høgsberged568912006-12-19 19:58:35 -0500618}
619
Stefan Richter02d37be2010-07-08 16:09:06 +0200620static int ohci_read_phy_reg(struct fw_card *card, int addr)
621{
622 struct fw_ohci *ohci = fw_ohci(card);
623 int ret;
624
625 mutex_lock(&ohci->phy_reg_mutex);
626 ret = read_phy_reg(ohci, addr);
627 mutex_unlock(&ohci->phy_reg_mutex);
628
629 return ret;
630}
631
Kristian Høgsberged568912006-12-19 19:58:35 -0500632static int ohci_update_phy_reg(struct fw_card *card, int addr,
633 int clear_bits, int set_bits)
634{
635 struct fw_ohci *ohci = fw_ohci(card);
Stefan Richter02d37be2010-07-08 16:09:06 +0200636 int ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500637
Stefan Richter02d37be2010-07-08 16:09:06 +0200638 mutex_lock(&ohci->phy_reg_mutex);
639 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
640 mutex_unlock(&ohci->phy_reg_mutex);
Kristian Høgsberged568912006-12-19 19:58:35 -0500641
Stefan Richter02d37be2010-07-08 16:09:06 +0200642 return ret;
Kristian Høgsberged568912006-12-19 19:58:35 -0500643}
644
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100645static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
Kristian Høgsberged568912006-12-19 19:58:35 -0500646{
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100647 return page_private(ctx->pages[i]);
648}
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500649
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100650static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
651{
652 struct descriptor *d;
653
654 d = &ctx->descriptors[index];
655 d->branch_address &= cpu_to_le32(~0xf);
656 d->res_count = cpu_to_le16(PAGE_SIZE);
657 d->transfer_status = 0;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500658
Stefan Richter071595e2010-07-27 13:20:33 +0200659 wmb(); /* finish init of new descriptors before branch_address update */
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100660 d = &ctx->descriptors[ctx->last_buffer_index];
661 d->branch_address |= cpu_to_le32(1);
662
663 ctx->last_buffer_index = index;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500664
Kristian Høgsberga77754a2007-05-07 20:33:35 -0400665 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Clemens Ladisch837596a2010-10-25 11:42:42 +0200666}
667
Jay Fenlasona55709b2008-10-22 15:59:42 -0400668static void ar_context_release(struct ar_context *ctx)
669{
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100670 unsigned int i;
Jay Fenlasona55709b2008-10-22 15:59:42 -0400671
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100672 if (ctx->buffer)
673 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
674
675 for (i = 0; i < AR_BUFFERS; i++)
676 if (ctx->pages[i]) {
677 dma_unmap_page(ctx->ohci->card.device,
678 ar_buffer_bus(ctx, i),
679 PAGE_SIZE, DMA_FROM_DEVICE);
680 __free_page(ctx->pages[i]);
681 }
682}
683
684static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
685{
Stefan Richter64d21722011-12-20 21:32:46 +0100686 struct fw_ohci *ohci = ctx->ohci;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100687
Stefan Richter64d21722011-12-20 21:32:46 +0100688 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
689 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
690 flush_writes(ohci);
691
692 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
693 error_msg);
Jay Fenlasona55709b2008-10-22 15:59:42 -0400694 }
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100695 /* FIXME: restart? */
696}
697
698static inline unsigned int ar_next_buffer_index(unsigned int index)
699{
700 return (index + 1) % AR_BUFFERS;
701}
702
703static inline unsigned int ar_prev_buffer_index(unsigned int index)
704{
705 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
706}
707
708static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
709{
710 return ar_next_buffer_index(ctx->last_buffer_index);
711}
712
713/*
714 * We search for the buffer that contains the last AR packet DMA data written
715 * by the controller.
716 */
717static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
718 unsigned int *buffer_offset)
719{
720 unsigned int i, next_i, last = ctx->last_buffer_index;
721 __le16 res_count, next_res_count;
722
723 i = ar_first_buffer_index(ctx);
724 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
725
726 /* A buffer that is not yet completely filled must be the last one. */
727 while (i != last && res_count == 0) {
728
729 /* Peek at the next descriptor. */
730 next_i = ar_next_buffer_index(i);
731 rmb(); /* read descriptors in order */
732 next_res_count = ACCESS_ONCE(
733 ctx->descriptors[next_i].res_count);
734 /*
735 * If the next descriptor is still empty, we must stop at this
736 * descriptor.
737 */
738 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
739 /*
740 * The exception is when the DMA data for one packet is
741 * split over three buffers; in this case, the middle
742 * buffer's descriptor might be never updated by the
743 * controller and look still empty, and we have to peek
744 * at the third one.
745 */
746 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
747 next_i = ar_next_buffer_index(next_i);
748 rmb();
749 next_res_count = ACCESS_ONCE(
750 ctx->descriptors[next_i].res_count);
751 if (next_res_count != cpu_to_le16(PAGE_SIZE))
752 goto next_buffer_is_active;
753 }
754
755 break;
756 }
757
758next_buffer_is_active:
759 i = next_i;
760 res_count = next_res_count;
761 }
762
763 rmb(); /* read res_count before the DMA data */
764
765 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
766 if (*buffer_offset > PAGE_SIZE) {
767 *buffer_offset = 0;
768 ar_context_abort(ctx, "corrupted descriptor");
769 }
770
771 return i;
772}
773
774static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
775 unsigned int end_buffer_index,
776 unsigned int end_buffer_offset)
777{
778 unsigned int i;
779
780 i = ar_first_buffer_index(ctx);
781 while (i != end_buffer_index) {
782 dma_sync_single_for_cpu(ctx->ohci->card.device,
783 ar_buffer_bus(ctx, i),
784 PAGE_SIZE, DMA_FROM_DEVICE);
785 i = ar_next_buffer_index(i);
786 }
787 if (end_buffer_offset > 0)
788 dma_sync_single_for_cpu(ctx->ohci->card.device,
789 ar_buffer_bus(ctx, i),
790 end_buffer_offset, DMA_FROM_DEVICE);
Jay Fenlasona55709b2008-10-22 15:59:42 -0400791}
792
Stefan Richter11bf20a2008-03-01 02:47:15 +0100793#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
794#define cond_le32_to_cpu(v) \
Stefan Richter4a635592010-02-21 17:58:01 +0100795 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
Stefan Richter11bf20a2008-03-01 02:47:15 +0100796#else
797#define cond_le32_to_cpu(v) le32_to_cpu(v)
798#endif
799
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500800static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
Kristian Høgsberged568912006-12-19 19:58:35 -0500801{
Kristian Høgsberged568912006-12-19 19:58:35 -0500802 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500803 struct fw_packet p;
804 u32 status, length, tcode;
Stefan Richter43286562008-03-11 21:22:26 +0100805 int evt;
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500806
Stefan Richter11bf20a2008-03-01 02:47:15 +0100807 p.header[0] = cond_le32_to_cpu(buffer[0]);
808 p.header[1] = cond_le32_to_cpu(buffer[1]);
809 p.header[2] = cond_le32_to_cpu(buffer[2]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500810
811 tcode = (p.header[0] >> 4) & 0x0f;
812 switch (tcode) {
813 case TCODE_WRITE_QUADLET_REQUEST:
814 case TCODE_READ_QUADLET_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500815 p.header[3] = (__force __u32) buffer[3];
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500816 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500817 p.payload_length = 0;
818 break;
819
820 case TCODE_READ_BLOCK_REQUEST :
Stefan Richter11bf20a2008-03-01 02:47:15 +0100821 p.header[3] = cond_le32_to_cpu(buffer[3]);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500822 p.header_length = 16;
823 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500824 break;
825
826 case TCODE_WRITE_BLOCK_REQUEST:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500827 case TCODE_READ_BLOCK_RESPONSE:
828 case TCODE_LOCK_REQUEST:
829 case TCODE_LOCK_RESPONSE:
Stefan Richter11bf20a2008-03-01 02:47:15 +0100830 p.header[3] = cond_le32_to_cpu(buffer[3]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500831 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500832 p.payload_length = p.header[3] >> 16;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100833 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
834 ar_context_abort(ctx, "invalid packet length");
835 return NULL;
836 }
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500837 break;
838
839 case TCODE_WRITE_RESPONSE:
840 case TCODE_READ_QUADLET_REQUEST:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500841 case OHCI_TCODE_PHY_PACKET:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500842 p.header_length = 12;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500843 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500844 break;
Stefan Richterccff9622008-05-31 19:36:06 +0200845
846 default:
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100847 ar_context_abort(ctx, "invalid tcode");
848 return NULL;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500849 }
850
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500851 p.payload = (void *) buffer + p.header_length;
852
853 /* FIXME: What to do about evt_* errors? */
854 length = (p.header_length + p.payload_length + 3) / 4;
Stefan Richter11bf20a2008-03-01 02:47:15 +0100855 status = cond_le32_to_cpu(buffer[length]);
Stefan Richter43286562008-03-11 21:22:26 +0100856 evt = (status >> 16) & 0x1f;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500857
Stefan Richter43286562008-03-11 21:22:26 +0100858 p.ack = evt - 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500859 p.speed = (status >> 21) & 0x7;
860 p.timestamp = status & 0xffff;
861 p.generation = ohci->request_generation;
Kristian Høgsberged568912006-12-19 19:58:35 -0500862
Stefan Richter64d21722011-12-20 21:32:46 +0100863 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
Stefan Richterad3c0fe2008-03-20 22:04:36 +0100864
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400865 /*
Stefan Richtera4dc0902010-08-28 14:21:26 +0200866 * Several controllers, notably from NEC and VIA, forget to
867 * write ack_complete status at PHY packet reception.
868 */
869 if (evt == OHCI1394_evt_no_status &&
870 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
871 p.ack = ACK_COMPLETE;
872
873 /*
874 * The OHCI bus reset handler synthesizes a PHY packet with
Kristian Høgsberged568912006-12-19 19:58:35 -0500875 * the new generation number when a bus reset happens (see
876 * section 8.4.2.3). This helps us determine when a request
877 * was received and make sure we send the response in the same
878 * generation. We only need this for requests; for responses
879 * we use the unique tlabel for finding the matching
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400880 * request.
Stefan Richterd34316a2008-04-12 22:31:25 +0200881 *
882 * Alas some chips sometimes emit bus reset packets with a
883 * wrong generation. We set the correct generation for these
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +0200884 * at a slightly incorrect time (in bus_reset_work).
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400885 */
Stefan Richterd34316a2008-04-12 22:31:25 +0200886 if (evt == OHCI1394_evt_bus_reset) {
Stefan Richter4a635592010-02-21 17:58:01 +0100887 if (!(ohci->quirks & QUIRK_RESET_PACKET))
Stefan Richterd34316a2008-04-12 22:31:25 +0200888 ohci->request_generation = (p.header[2] >> 16) & 0xff;
889 } else if (ctx == &ohci->ar_request_ctx) {
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500890 fw_core_handle_request(&ohci->card, &p);
Stefan Richterd34316a2008-04-12 22:31:25 +0200891 } else {
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500892 fw_core_handle_response(&ohci->card, &p);
Stefan Richterd34316a2008-04-12 22:31:25 +0200893 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500894
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500895 return buffer + length + 1;
896}
Kristian Høgsberged568912006-12-19 19:58:35 -0500897
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100898static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
899{
900 void *next;
901
902 while (p < end) {
903 next = handle_ar_packet(ctx, p);
904 if (!next)
905 return p;
906 p = next;
907 }
908
909 return p;
910}
911
912static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
913{
914 unsigned int i;
915
916 i = ar_first_buffer_index(ctx);
917 while (i != end_buffer) {
918 dma_sync_single_for_device(ctx->ohci->card.device,
919 ar_buffer_bus(ctx, i),
920 PAGE_SIZE, DMA_FROM_DEVICE);
921 ar_context_link_page(ctx, i);
922 i = ar_next_buffer_index(i);
923 }
924}
925
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500926static void ar_context_tasklet(unsigned long data)
927{
928 struct ar_context *ctx = (struct ar_context *)data;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100929 unsigned int end_buffer_index, end_buffer_offset;
930 void *p, *end;
Kristian Høgsberged568912006-12-19 19:58:35 -0500931
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100932 p = ctx->pointer;
933 if (!p)
934 return;
Kristian Høgsberged568912006-12-19 19:58:35 -0500935
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100936 end_buffer_index = ar_search_last_active_buffer(ctx,
937 &end_buffer_offset);
938 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
939 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500940
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100941 if (end_buffer_index < ar_first_buffer_index(ctx)) {
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400942 /*
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100943 * The filled part of the overall buffer wraps around; handle
944 * all packets up to the buffer end here. If the last packet
945 * wraps around, its tail will be visible after the buffer end
946 * because the buffer start pages are mapped there again.
Kristian Høgsbergc781c062007-05-07 20:33:32 -0400947 */
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100948 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
949 p = handle_ar_packets(ctx, p, buffer_end);
950 if (p < buffer_end)
951 goto error;
952 /* adjust p to point back into the actual buffer */
953 p -= AR_BUFFERS * PAGE_SIZE;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500954 }
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100955
956 p = handle_ar_packets(ctx, p, end);
957 if (p != end) {
958 if (p > end)
959 ar_context_abort(ctx, "inconsistent descriptor");
960 goto error;
961 }
962
963 ctx->pointer = p;
964 ar_recycle_buffers(ctx, end_buffer_index);
965
966 return;
967
968error:
969 ctx->pointer = NULL;
Kristian Høgsberged568912006-12-19 19:58:35 -0500970}
971
Clemens Ladischec766a72010-11-30 08:25:17 +0100972static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
973 unsigned int descriptors_offset, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500974{
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100975 unsigned int i;
976 dma_addr_t dma_addr;
977 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
978 struct descriptor *d;
Kristian Høgsberged568912006-12-19 19:58:35 -0500979
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500980 ctx->regs = regs;
981 ctx->ohci = ohci;
Kristian Høgsberged568912006-12-19 19:58:35 -0500982 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
983
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +0100984 for (i = 0; i < AR_BUFFERS; i++) {
985 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
986 if (!ctx->pages[i])
987 goto out_of_memory;
988 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
989 0, PAGE_SIZE, DMA_FROM_DEVICE);
990 if (dma_mapping_error(ohci->card.device, dma_addr)) {
991 __free_page(ctx->pages[i]);
992 ctx->pages[i] = NULL;
993 goto out_of_memory;
994 }
995 set_page_private(ctx->pages[i], dma_addr);
996 }
997
998 for (i = 0; i < AR_BUFFERS; i++)
999 pages[i] = ctx->pages[i];
1000 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1001 pages[AR_BUFFERS + i] = ctx->pages[i];
1002 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
Clemens Ladisch14271302011-01-13 10:12:17 +01001003 -1, PAGE_KERNEL);
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001004 if (!ctx->buffer)
1005 goto out_of_memory;
1006
Clemens Ladischec766a72010-11-30 08:25:17 +01001007 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1008 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001009
1010 for (i = 0; i < AR_BUFFERS; i++) {
1011 d = &ctx->descriptors[i];
1012 d->req_count = cpu_to_le16(PAGE_SIZE);
1013 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1014 DESCRIPTOR_STATUS |
1015 DESCRIPTOR_BRANCH_ALWAYS);
1016 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1017 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1018 ar_next_buffer_index(i) * sizeof(struct descriptor));
1019 }
Kristian Høgsberg32b46092007-02-06 14:49:30 -05001020
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001021 return 0;
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001022
1023out_of_memory:
1024 ar_context_release(ctx);
1025
1026 return -ENOMEM;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001027}
1028
1029static void ar_context_run(struct ar_context *ctx)
1030{
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001031 unsigned int i;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001032
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001033 for (i = 0; i < AR_BUFFERS; i++)
1034 ar_context_link_page(ctx, i);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04001035
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01001036 ctx->pointer = ctx->buffer;
1037
1038 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001039 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
Kristian Høgsberged568912006-12-19 19:58:35 -05001040}
Stefan Richter373b2ed2007-03-04 14:45:18 +01001041
Stefan Richter53dca512008-12-14 21:47:04 +01001042static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001043{
Clemens Ladisch0ff8fbc2011-04-12 07:54:59 +02001044 __le16 branch;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001045
Clemens Ladisch0ff8fbc2011-04-12 07:54:59 +02001046 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001047
1048 /* figure out which descriptor the branch address goes in */
Clemens Ladisch0ff8fbc2011-04-12 07:54:59 +02001049 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001050 return d;
1051 else
1052 return d + z - 1;
1053}
1054
Kristian Høgsberg30200732007-02-16 17:34:39 -05001055static void context_tasklet(unsigned long data)
1056{
1057 struct context *ctx = (struct context *) data;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001058 struct descriptor *d, *last;
1059 u32 address;
1060 int z;
David Moorefe5ca632008-01-06 17:21:41 -05001061 struct descriptor_buffer *desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001062
David Moorefe5ca632008-01-06 17:21:41 -05001063 desc = list_entry(ctx->buffer_list.next,
1064 struct descriptor_buffer, list);
1065 last = ctx->last;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001066 while (last->branch_address != 0) {
David Moorefe5ca632008-01-06 17:21:41 -05001067 struct descriptor_buffer *old_desc = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001068 address = le32_to_cpu(last->branch_address);
1069 z = address & 0xf;
David Moorefe5ca632008-01-06 17:21:41 -05001070 address &= ~0xf;
Clemens Ladischa572e682011-10-15 23:12:23 +02001071 ctx->current_bus = address;
David Moorefe5ca632008-01-06 17:21:41 -05001072
1073 /* If the branch address points to a buffer outside of the
1074 * current buffer, advance to the next buffer. */
1075 if (address < desc->buffer_bus ||
1076 address >= desc->buffer_bus + desc->used)
1077 desc = list_entry(desc->list.next,
1078 struct descriptor_buffer, list);
1079 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001080 last = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001081
1082 if (!ctx->callback(ctx, d, last))
1083 break;
1084
David Moorefe5ca632008-01-06 17:21:41 -05001085 if (old_desc != desc) {
1086 /* If we've advanced to the next buffer, move the
1087 * previous buffer to the free list. */
1088 unsigned long flags;
1089 old_desc->used = 0;
1090 spin_lock_irqsave(&ctx->ohci->lock, flags);
1091 list_move_tail(&old_desc->list, &ctx->buffer_list);
1092 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1093 }
1094 ctx->last = last;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001095 }
1096}
1097
David Moorefe5ca632008-01-06 17:21:41 -05001098/*
1099 * Allocate a new buffer and add it to the list of free buffers for this
1100 * context. Must be called with ohci->lock held.
1101 */
Stefan Richter53dca512008-12-14 21:47:04 +01001102static int context_add_buffer(struct context *ctx)
David Moorefe5ca632008-01-06 17:21:41 -05001103{
1104 struct descriptor_buffer *desc;
Stefan Richterf5101d582008-03-14 00:27:49 +01001105 dma_addr_t uninitialized_var(bus_addr);
David Moorefe5ca632008-01-06 17:21:41 -05001106 int offset;
1107
1108 /*
1109 * 16MB of descriptors should be far more than enough for any DMA
1110 * program. This will catch run-away userspace or DoS attacks.
1111 */
1112 if (ctx->total_allocation >= 16*1024*1024)
1113 return -ENOMEM;
1114
1115 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1116 &bus_addr, GFP_ATOMIC);
1117 if (!desc)
1118 return -ENOMEM;
1119
1120 offset = (void *)&desc->buffer - (void *)desc;
1121 desc->buffer_size = PAGE_SIZE - offset;
1122 desc->buffer_bus = bus_addr + offset;
1123 desc->used = 0;
1124
1125 list_add_tail(&desc->list, &ctx->buffer_list);
1126 ctx->total_allocation += PAGE_SIZE;
1127
1128 return 0;
1129}
1130
Stefan Richter53dca512008-12-14 21:47:04 +01001131static int context_init(struct context *ctx, struct fw_ohci *ohci,
1132 u32 regs, descriptor_callback_t callback)
Kristian Høgsberg30200732007-02-16 17:34:39 -05001133{
1134 ctx->ohci = ohci;
1135 ctx->regs = regs;
David Moorefe5ca632008-01-06 17:21:41 -05001136 ctx->total_allocation = 0;
1137
1138 INIT_LIST_HEAD(&ctx->buffer_list);
1139 if (context_add_buffer(ctx) < 0)
Kristian Høgsberg30200732007-02-16 17:34:39 -05001140 return -ENOMEM;
1141
David Moorefe5ca632008-01-06 17:21:41 -05001142 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1143 struct descriptor_buffer, list);
1144
Kristian Høgsberg30200732007-02-16 17:34:39 -05001145 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1146 ctx->callback = callback;
1147
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001148 /*
1149 * We put a dummy descriptor in the buffer that has a NULL
Kristian Høgsberg30200732007-02-16 17:34:39 -05001150 * branch address and looks like it's been sent. That way we
David Moorefe5ca632008-01-06 17:21:41 -05001151 * have a descriptor to append DMA programs to.
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001152 */
David Moorefe5ca632008-01-06 17:21:41 -05001153 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1154 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1155 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1156 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1157 ctx->last = ctx->buffer_tail->buffer;
1158 ctx->prev = ctx->buffer_tail->buffer;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001159
1160 return 0;
1161}
1162
Stefan Richter53dca512008-12-14 21:47:04 +01001163static void context_release(struct context *ctx)
Kristian Høgsberg30200732007-02-16 17:34:39 -05001164{
1165 struct fw_card *card = &ctx->ohci->card;
David Moorefe5ca632008-01-06 17:21:41 -05001166 struct descriptor_buffer *desc, *tmp;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001167
David Moorefe5ca632008-01-06 17:21:41 -05001168 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1169 dma_free_coherent(card->device, PAGE_SIZE, desc,
1170 desc->buffer_bus -
1171 ((void *)&desc->buffer - (void *)desc));
Kristian Høgsberg30200732007-02-16 17:34:39 -05001172}
1173
David Moorefe5ca632008-01-06 17:21:41 -05001174/* Must be called with ohci->lock held */
Stefan Richter53dca512008-12-14 21:47:04 +01001175static struct descriptor *context_get_descriptors(struct context *ctx,
1176 int z, dma_addr_t *d_bus)
Kristian Høgsberg30200732007-02-16 17:34:39 -05001177{
David Moorefe5ca632008-01-06 17:21:41 -05001178 struct descriptor *d = NULL;
1179 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001180
David Moorefe5ca632008-01-06 17:21:41 -05001181 if (z * sizeof(*d) > desc->buffer_size)
1182 return NULL;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001183
David Moorefe5ca632008-01-06 17:21:41 -05001184 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1185 /* No room for the descriptor in this buffer, so advance to the
1186 * next one. */
1187
1188 if (desc->list.next == &ctx->buffer_list) {
1189 /* If there is no free buffer next in the list,
1190 * allocate one. */
1191 if (context_add_buffer(ctx) < 0)
1192 return NULL;
1193 }
1194 desc = list_entry(desc->list.next,
1195 struct descriptor_buffer, list);
1196 ctx->buffer_tail = desc;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001197 }
1198
David Moorefe5ca632008-01-06 17:21:41 -05001199 d = desc->buffer + desc->used / sizeof(*d);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04001200 memset(d, 0, z * sizeof(*d));
David Moorefe5ca632008-01-06 17:21:41 -05001201 *d_bus = desc->buffer_bus + desc->used;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001202
1203 return d;
1204}
1205
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001206static void context_run(struct context *ctx, u32 extra)
Kristian Høgsberg30200732007-02-16 17:34:39 -05001207{
1208 struct fw_ohci *ohci = ctx->ohci;
1209
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001210 reg_write(ohci, COMMAND_PTR(ctx->regs),
David Moorefe5ca632008-01-06 17:21:41 -05001211 le32_to_cpu(ctx->last->branch_address));
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001212 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1213 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
Clemens Ladisch386a4152010-12-24 14:42:46 +01001214 ctx->running = true;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001215 flush_writes(ohci);
1216}
1217
1218static void context_append(struct context *ctx,
1219 struct descriptor *d, int z, int extra)
1220{
1221 dma_addr_t d_bus;
David Moorefe5ca632008-01-06 17:21:41 -05001222 struct descriptor_buffer *desc = ctx->buffer_tail;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001223
David Moorefe5ca632008-01-06 17:21:41 -05001224 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001225
David Moorefe5ca632008-01-06 17:21:41 -05001226 desc->used += (z + extra) * sizeof(*d);
Stefan Richter071595e2010-07-27 13:20:33 +02001227
1228 wmb(); /* finish init of new descriptors before branch_address update */
David Moorefe5ca632008-01-06 17:21:41 -05001229 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1230 ctx->prev = find_branch_descriptor(d, z);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001231}
1232
1233static void context_stop(struct context *ctx)
1234{
Stefan Richter64d21722011-12-20 21:32:46 +01001235 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001236 u32 reg;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001237 int i;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001238
Stefan Richter64d21722011-12-20 21:32:46 +01001239 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
Clemens Ladisch386a4152010-12-24 14:42:46 +01001240 ctx->running = false;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001241
Stefan Richter9ef28cc2011-06-12 14:30:57 +02001242 for (i = 0; i < 1000; i++) {
Stefan Richter64d21722011-12-20 21:32:46 +01001243 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001244 if ((reg & CONTEXT_ACTIVE) == 0)
Stefan Richterb0068542009-01-05 20:43:23 +01001245 return;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001246
Stefan Richter9ef28cc2011-06-12 14:30:57 +02001247 if (i)
1248 udelay(10);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001249 }
Stefan Richter64d21722011-12-20 21:32:46 +01001250 dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001251}
Kristian Høgsberged568912006-12-19 19:58:35 -05001252
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001253struct driver_data {
Clemens Ladischda289472011-04-11 09:57:54 +02001254 u8 inline_data[8];
Kristian Høgsberged568912006-12-19 19:58:35 -05001255 struct fw_packet *packet;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001256};
1257
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001258/*
1259 * This function apppends a packet to the DMA queue for transmission.
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001260 * Must always be called with the ochi->lock held to ensure proper
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001261 * generation handling and locking around packet queue manipulation.
1262 */
Stefan Richter53dca512008-12-14 21:47:04 +01001263static int at_context_queue_packet(struct context *ctx,
1264 struct fw_packet *packet)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001265{
Kristian Høgsberged568912006-12-19 19:58:35 -05001266 struct fw_ohci *ohci = ctx->ohci;
Stefan Richter4b6d51e2007-10-21 11:20:07 +02001267 dma_addr_t d_bus, uninitialized_var(payload_bus);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001268 struct driver_data *driver_data;
1269 struct descriptor *d, *last;
1270 __le32 *header;
Kristian Høgsberged568912006-12-19 19:58:35 -05001271 int z, tcode;
1272
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001273 d = context_get_descriptors(ctx, 4, &d_bus);
1274 if (d == NULL) {
1275 packet->ack = RCODE_SEND_ERROR;
1276 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001277 }
1278
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001279 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001280 d[0].res_count = cpu_to_le16(packet->timestamp);
1281
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001282 /*
1283 * The DMA format for asyncronous link packets is different
Kristian Høgsberged568912006-12-19 19:58:35 -05001284 * from the IEEE1394 layout, so shift the fields around
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001285 * accordingly.
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001286 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001287
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001288 tcode = (packet->header[0] >> 4) & 0x0f;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001289 header = (__le32 *) &d[1];
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001290 switch (tcode) {
1291 case TCODE_WRITE_QUADLET_REQUEST:
1292 case TCODE_WRITE_BLOCK_REQUEST:
1293 case TCODE_WRITE_RESPONSE:
1294 case TCODE_READ_QUADLET_REQUEST:
1295 case TCODE_READ_BLOCK_REQUEST:
1296 case TCODE_READ_QUADLET_RESPONSE:
1297 case TCODE_READ_BLOCK_RESPONSE:
1298 case TCODE_LOCK_REQUEST:
1299 case TCODE_LOCK_RESPONSE:
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001300 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1301 (packet->speed << 16));
1302 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1303 (packet->header[0] & 0xffff0000));
1304 header[2] = cpu_to_le32(packet->header[2]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001305
Kristian Høgsberged568912006-12-19 19:58:35 -05001306 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001307 header[3] = cpu_to_le32(packet->header[3]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001308 else
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001309 header[3] = (__force __le32) packet->header[3];
1310
1311 d[0].req_count = cpu_to_le16(packet->header_length);
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001312 break;
1313
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001314 case TCODE_LINK_INTERNAL:
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001315 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1316 (packet->speed << 16));
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001317 header[1] = cpu_to_le32(packet->header[1]);
1318 header[2] = cpu_to_le32(packet->header[2]);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001319 d[0].req_count = cpu_to_le16(12);
Stefan Richtercc550212010-07-18 13:00:50 +02001320
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001321 if (is_ping_packet(&packet->header[1]))
Stefan Richtercc550212010-07-18 13:00:50 +02001322 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001323 break;
1324
Clemens Ladisch5b06db12010-11-30 08:24:47 +01001325 case TCODE_STREAM_DATA:
Jay Fenlasonf8c22872009-03-05 19:08:40 +01001326 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1327 (packet->speed << 16));
1328 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1329 d[0].req_count = cpu_to_le16(8);
1330 break;
1331
1332 default:
1333 /* BUG(); */
1334 packet->ack = RCODE_SEND_ERROR;
1335 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001336 }
1337
Clemens Ladischda289472011-04-11 09:57:54 +02001338 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001339 driver_data = (struct driver_data *) &d[3];
1340 driver_data->packet = packet;
Kristian Høgsberg20d11672007-03-26 19:18:19 -04001341 packet->driver_data = driver_data;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001342
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001343 if (packet->payload_length > 0) {
Clemens Ladischda289472011-04-11 09:57:54 +02001344 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1345 payload_bus = dma_map_single(ohci->card.device,
1346 packet->payload,
1347 packet->payload_length,
1348 DMA_TO_DEVICE);
1349 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1350 packet->ack = RCODE_SEND_ERROR;
1351 return -1;
1352 }
1353 packet->payload_bus = payload_bus;
1354 packet->payload_mapped = true;
1355 } else {
1356 memcpy(driver_data->inline_data, packet->payload,
1357 packet->payload_length);
1358 payload_bus = d_bus + 3 * sizeof(*d);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001359 }
1360
1361 d[2].req_count = cpu_to_le16(packet->payload_length);
1362 d[2].data_address = cpu_to_le32(payload_bus);
1363 last = &d[2];
1364 z = 3;
1365 } else {
1366 last = &d[0];
1367 z = 2;
1368 }
1369
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001370 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1371 DESCRIPTOR_IRQ_ALWAYS |
1372 DESCRIPTOR_BRANCH_ALWAYS);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001373
Stefan Richterb6258fc2011-02-26 15:08:35 +01001374 /* FIXME: Document how the locking works. */
1375 if (ohci->generation != packet->generation) {
Stefan Richter19593ff2009-10-14 20:40:10 +02001376 if (packet->payload_mapped)
Stefan Richterab88ca42007-08-29 19:40:28 +02001377 dma_unmap_single(ohci->card.device, payload_bus,
1378 packet->payload_length, DMA_TO_DEVICE);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001379 packet->ack = RCODE_GENERATION;
1380 return -1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001381 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001382
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001383 context_append(ctx, d, z, 4 - z);
Kristian Høgsberged568912006-12-19 19:58:35 -05001384
Clemens Ladischdd6254e2011-05-16 08:10:10 +02001385 if (ctx->running)
Clemens Ladisch13882a82011-05-02 09:33:56 +02001386 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Clemens Ladischdd6254e2011-05-16 08:10:10 +02001387 else
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001388 context_run(ctx, 0);
Kristian Høgsberged568912006-12-19 19:58:35 -05001389
1390 return 0;
1391}
1392
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001393static void at_context_flush(struct context *ctx)
1394{
1395 tasklet_disable(&ctx->tasklet);
1396
1397 ctx->flushing = true;
1398 context_tasklet((unsigned long)ctx);
1399 ctx->flushing = false;
1400
1401 tasklet_enable(&ctx->tasklet);
1402}
1403
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001404static int handle_at_packet(struct context *context,
1405 struct descriptor *d,
1406 struct descriptor *last)
1407{
1408 struct driver_data *driver_data;
1409 struct fw_packet *packet;
1410 struct fw_ohci *ohci = context->ohci;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001411 int evt;
1412
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001413 if (last->transfer_status == 0 && !context->flushing)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001414 /* This descriptor isn't done yet, stop iteration. */
1415 return 0;
1416
1417 driver_data = (struct driver_data *) &d[3];
1418 packet = driver_data->packet;
1419 if (packet == NULL)
1420 /* This packet was cancelled, just continue. */
1421 return 1;
1422
Stefan Richter19593ff2009-10-14 20:40:10 +02001423 if (packet->payload_mapped)
Stefan Richter1d1dc5e2008-12-10 00:20:38 +01001424 dma_unmap_single(ohci->card.device, packet->payload_bus,
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001425 packet->payload_length, DMA_TO_DEVICE);
1426
1427 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1428 packet->timestamp = le16_to_cpu(last->res_count);
1429
Stefan Richter64d21722011-12-20 21:32:46 +01001430 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
Stefan Richterad3c0fe2008-03-20 22:04:36 +01001431
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001432 switch (evt) {
1433 case OHCI1394_evt_timeout:
1434 /* Async response transmit timed out. */
1435 packet->ack = RCODE_CANCELLED;
1436 break;
1437
1438 case OHCI1394_evt_flushed:
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001439 /*
1440 * The packet was flushed should give same error as
1441 * when we try to use a stale generation count.
1442 */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001443 packet->ack = RCODE_GENERATION;
1444 break;
1445
1446 case OHCI1394_evt_missing_ack:
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001447 if (context->flushing)
1448 packet->ack = RCODE_GENERATION;
1449 else {
1450 /*
1451 * Using a valid (current) generation count, but the
1452 * node is not on the bus or not sending acks.
1453 */
1454 packet->ack = RCODE_NO_ACK;
1455 }
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001456 break;
1457
1458 case ACK_COMPLETE + 0x10:
1459 case ACK_PENDING + 0x10:
1460 case ACK_BUSY_X + 0x10:
1461 case ACK_BUSY_A + 0x10:
1462 case ACK_BUSY_B + 0x10:
1463 case ACK_DATA_ERROR + 0x10:
1464 case ACK_TYPE_ERROR + 0x10:
1465 packet->ack = evt - 0x10;
1466 break;
1467
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001468 case OHCI1394_evt_no_status:
1469 if (context->flushing) {
1470 packet->ack = RCODE_GENERATION;
1471 break;
1472 }
1473 /* fall through */
1474
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001475 default:
1476 packet->ack = RCODE_SEND_ERROR;
1477 break;
1478 }
1479
1480 packet->callback(packet, &ohci->card, packet->ack);
1481
1482 return 1;
1483}
1484
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001485#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1486#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1487#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1488#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1489#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001490
Stefan Richter53dca512008-12-14 21:47:04 +01001491static void handle_local_rom(struct fw_ohci *ohci,
1492 struct fw_packet *packet, u32 csr)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001493{
1494 struct fw_packet response;
1495 int tcode, length, i;
1496
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001497 tcode = HEADER_GET_TCODE(packet->header[0]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001498 if (TCODE_IS_BLOCK_PACKET(tcode))
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001499 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001500 else
1501 length = 4;
1502
1503 i = csr - CSR_CONFIG_ROM;
1504 if (i + length > CONFIG_ROM_SIZE) {
1505 fw_fill_response(&response, packet->header,
1506 RCODE_ADDRESS_ERROR, NULL, 0);
1507 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1508 fw_fill_response(&response, packet->header,
1509 RCODE_TYPE_ERROR, NULL, 0);
1510 } else {
1511 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1512 (void *) ohci->config_rom + i, length);
1513 }
1514
1515 fw_core_handle_response(&ohci->card, &response);
1516}
1517
Stefan Richter53dca512008-12-14 21:47:04 +01001518static void handle_local_lock(struct fw_ohci *ohci,
1519 struct fw_packet *packet, u32 csr)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001520{
1521 struct fw_packet response;
Clemens Ladische1393662010-04-12 10:35:44 +02001522 int tcode, length, ext_tcode, sel, try;
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001523 __be32 *payload, lock_old;
1524 u32 lock_arg, lock_data;
1525
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001526 tcode = HEADER_GET_TCODE(packet->header[0]);
1527 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001528 payload = packet->payload;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001529 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001530
1531 if (tcode == TCODE_LOCK_REQUEST &&
1532 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1533 lock_arg = be32_to_cpu(payload[0]);
1534 lock_data = be32_to_cpu(payload[1]);
1535 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1536 lock_arg = 0;
1537 lock_data = 0;
1538 } else {
1539 fw_fill_response(&response, packet->header,
1540 RCODE_TYPE_ERROR, NULL, 0);
1541 goto out;
1542 }
1543
1544 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1545 reg_write(ohci, OHCI1394_CSRData, lock_data);
1546 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1547 reg_write(ohci, OHCI1394_CSRControl, sel);
1548
Clemens Ladische1393662010-04-12 10:35:44 +02001549 for (try = 0; try < 20; try++)
1550 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1551 lock_old = cpu_to_be32(reg_read(ohci,
1552 OHCI1394_CSRData));
1553 fw_fill_response(&response, packet->header,
1554 RCODE_COMPLETE,
1555 &lock_old, sizeof(lock_old));
1556 goto out;
1557 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001558
Stefan Richter64d21722011-12-20 21:32:46 +01001559 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
Clemens Ladische1393662010-04-12 10:35:44 +02001560 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1561
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001562 out:
1563 fw_core_handle_response(&ohci->card, &response);
1564}
1565
Stefan Richter53dca512008-12-14 21:47:04 +01001566static void handle_local_request(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001567{
Clemens Ladisch26082032010-04-12 10:35:30 +02001568 u64 offset, csr;
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001569
Kristian Høgsberg473d28c2007-03-07 12:12:55 -05001570 if (ctx == &ctx->ohci->at_request_ctx) {
1571 packet->ack = ACK_PENDING;
1572 packet->callback(packet, &ctx->ohci->card, packet->ack);
1573 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001574
1575 offset =
1576 ((unsigned long long)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001577 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001578 packet->header[2];
1579 csr = offset - CSR_REGISTER_BASE;
1580
1581 /* Handle config rom reads. */
1582 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1583 handle_local_rom(ctx->ohci, packet, csr);
1584 else switch (csr) {
1585 case CSR_BUS_MANAGER_ID:
1586 case CSR_BANDWIDTH_AVAILABLE:
1587 case CSR_CHANNELS_AVAILABLE_HI:
1588 case CSR_CHANNELS_AVAILABLE_LO:
1589 handle_local_lock(ctx->ohci, packet, csr);
1590 break;
1591 default:
1592 if (ctx == &ctx->ohci->at_request_ctx)
1593 fw_core_handle_request(&ctx->ohci->card, packet);
1594 else
1595 fw_core_handle_response(&ctx->ohci->card, packet);
1596 break;
1597 }
Kristian Høgsberg473d28c2007-03-07 12:12:55 -05001598
1599 if (ctx == &ctx->ohci->at_response_ctx) {
1600 packet->ack = ACK_COMPLETE;
1601 packet->callback(packet, &ctx->ohci->card, packet->ack);
1602 }
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001603}
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001604
Stefan Richter53dca512008-12-14 21:47:04 +01001605static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
Kristian Høgsberged568912006-12-19 19:58:35 -05001606{
Kristian Høgsberged568912006-12-19 19:58:35 -05001607 unsigned long flags;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001608 int ret;
Kristian Høgsberged568912006-12-19 19:58:35 -05001609
1610 spin_lock_irqsave(&ctx->ohci->lock, flags);
1611
Kristian Høgsberga77754a2007-05-07 20:33:35 -04001612 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001613 ctx->ohci->generation == packet->generation) {
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -05001614 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1615 handle_local_request(ctx, packet);
1616 return;
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001617 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001618
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001619 ret = at_context_queue_packet(ctx, packet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001620 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1621
Stefan Richter2dbd7d72008-12-14 21:45:45 +01001622 if (ret < 0)
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001623 packet->callback(packet, &ctx->ohci->card, packet->ack);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05001624
Kristian Høgsberged568912006-12-19 19:58:35 -05001625}
1626
Clemens Ladischf117a3e2011-01-10 17:21:35 +01001627static void detect_dead_context(struct fw_ohci *ohci,
1628 const char *name, unsigned int regs)
1629{
1630 u32 ctl;
1631
1632 ctl = reg_read(ohci, CONTROL_SET(regs));
Stefan Richtercfda62b2012-03-04 21:34:21 +01001633 if (ctl & CONTEXT_DEAD)
Stefan Richter64d21722011-12-20 21:32:46 +01001634 dev_err(ohci->card.device,
1635 "DMA context %s has stopped, error code: %s\n",
1636 name, evts[ctl & 0x1f]);
Clemens Ladischf117a3e2011-01-10 17:21:35 +01001637}
1638
1639static void handle_dead_contexts(struct fw_ohci *ohci)
1640{
1641 unsigned int i;
1642 char name[8];
1643
1644 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1645 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1646 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1647 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1648 for (i = 0; i < 32; ++i) {
1649 if (!(ohci->it_context_support & (1 << i)))
1650 continue;
1651 sprintf(name, "IT%u", i);
1652 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1653 }
1654 for (i = 0; i < 32; ++i) {
1655 if (!(ohci->ir_context_support & (1 << i)))
1656 continue;
1657 sprintf(name, "IR%u", i);
1658 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1659 }
1660 /* TODO: maybe try to flush and restart the dead contexts */
1661}
1662
Clemens Ladischa48777e2010-06-10 08:33:07 +02001663static u32 cycle_timer_ticks(u32 cycle_timer)
1664{
1665 u32 ticks;
1666
1667 ticks = cycle_timer & 0xfff;
1668 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1669 ticks += (3072 * 8000) * (cycle_timer >> 25);
1670
1671 return ticks;
1672}
1673
1674/*
1675 * Some controllers exhibit one or more of the following bugs when updating the
1676 * iso cycle timer register:
1677 * - When the lowest six bits are wrapping around to zero, a read that happens
1678 * at the same time will return garbage in the lowest ten bits.
1679 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1680 * not incremented for about 60 ns.
1681 * - Occasionally, the entire register reads zero.
1682 *
1683 * To catch these, we read the register three times and ensure that the
1684 * difference between each two consecutive reads is approximately the same, i.e.
1685 * less than twice the other. Furthermore, any negative difference indicates an
1686 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1687 * execute, so we have enough precision to compute the ratio of the differences.)
1688 */
1689static u32 get_cycle_time(struct fw_ohci *ohci)
1690{
1691 u32 c0, c1, c2;
1692 u32 t0, t1, t2;
1693 s32 diff01, diff12;
1694 int i;
1695
1696 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1697
1698 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1699 i = 0;
1700 c1 = c2;
1701 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1702 do {
1703 c0 = c1;
1704 c1 = c2;
1705 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1706 t0 = cycle_timer_ticks(c0);
1707 t1 = cycle_timer_ticks(c1);
1708 t2 = cycle_timer_ticks(c2);
1709 diff01 = t1 - t0;
1710 diff12 = t2 - t1;
1711 } while ((diff01 <= 0 || diff12 <= 0 ||
1712 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1713 && i++ < 20);
1714 }
1715
1716 return c2;
1717}
1718
1719/*
1720 * This function has to be called at least every 64 seconds. The bus_time
1721 * field stores not only the upper 25 bits of the BUS_TIME register but also
1722 * the most significant bit of the cycle timer in bit 6 so that we can detect
1723 * changes in this bit.
1724 */
1725static u32 update_bus_time(struct fw_ohci *ohci)
1726{
1727 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1728
1729 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1730 ohci->bus_time += 0x40;
1731
1732 return ohci->bus_time | cycle_time_seconds;
1733}
1734
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001735static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1736{
1737 int reg;
1738
1739 mutex_lock(&ohci->phy_reg_mutex);
1740 reg = write_phy_reg(ohci, 7, port_index);
Stefan Richter28897fb2011-09-19 00:17:37 +02001741 if (reg >= 0)
1742 reg = read_phy_reg(ohci, 8);
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001743 mutex_unlock(&ohci->phy_reg_mutex);
1744 if (reg < 0)
1745 return reg;
1746
1747 switch (reg & 0x0f) {
1748 case 0x06:
1749 return 2; /* is child node (connected to parent node) */
1750 case 0x0e:
1751 return 3; /* is parent node (connected to child node) */
1752 }
1753 return 1; /* not connected */
1754}
1755
1756static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1757 int self_id_count)
1758{
1759 int i;
1760 u32 entry;
Stefan Richter28897fb2011-09-19 00:17:37 +02001761
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001762 for (i = 0; i < self_id_count; i++) {
1763 entry = ohci->self_id_buffer[i];
1764 if ((self_id & 0xff000000) == (entry & 0xff000000))
1765 return -1;
1766 if ((self_id & 0xff000000) < (entry & 0xff000000))
1767 return i;
1768 }
1769 return i;
1770}
1771
1772/*
Stefan Richter28897fb2011-09-19 00:17:37 +02001773 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1774 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1775 * Construct the selfID from phy register contents.
1776 * FIXME: How to determine the selfID.i flag?
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001777 */
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001778static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1779{
Stefan Richter28897fb2011-09-19 00:17:37 +02001780 int reg, i, pos, status;
1781 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1782 u32 self_id = 0x8040c800;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001783
1784 reg = reg_read(ohci, OHCI1394_NodeID);
1785 if (!(reg & OHCI1394_NodeID_idValid)) {
Stefan Richter64d21722011-12-20 21:32:46 +01001786 dev_notice(ohci->card.device,
1787 "node ID not valid, new bus reset in progress\n");
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001788 return -EBUSY;
1789 }
1790 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1791
Stefan Richter28897fb2011-09-19 00:17:37 +02001792 reg = ohci_read_phy_reg(&ohci->card, 4);
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001793 if (reg < 0)
1794 return reg;
1795 self_id |= ((reg & 0x07) << 8); /* power class */
1796
Stefan Richter28897fb2011-09-19 00:17:37 +02001797 reg = ohci_read_phy_reg(&ohci->card, 1);
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001798 if (reg < 0)
1799 return reg;
1800 self_id |= ((reg & 0x3f) << 16); /* gap count */
1801
1802 for (i = 0; i < 3; i++) {
1803 status = get_status_for_port(ohci, i);
1804 if (status < 0)
1805 return status;
1806 self_id |= ((status & 0x3) << (6 - (i * 2)));
1807 }
1808
1809 pos = get_self_id_pos(ohci, self_id, self_id_count);
1810 if (pos >= 0) {
1811 memmove(&(ohci->self_id_buffer[pos+1]),
1812 &(ohci->self_id_buffer[pos]),
1813 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1814 ohci->self_id_buffer[pos] = self_id;
1815 self_id_count++;
1816 }
1817 return self_id_count;
1818}
1819
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02001820static void bus_reset_work(struct work_struct *work)
Kristian Høgsberged568912006-12-19 19:58:35 -05001821{
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02001822 struct fw_ohci *ohci =
1823 container_of(work, struct fw_ohci, bus_reset_work);
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001824 int self_id_count, i, j, reg;
Kristian Høgsberged568912006-12-19 19:58:35 -05001825 int generation, new_generation;
1826 unsigned long flags;
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001827 void *free_rom = NULL;
1828 dma_addr_t free_rom_bus = 0;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02001829 bool is_new_root;
Kristian Høgsberged568912006-12-19 19:58:35 -05001830
1831 reg = reg_read(ohci, OHCI1394_NodeID);
1832 if (!(reg & OHCI1394_NodeID_idValid)) {
Stefan Richter64d21722011-12-20 21:32:46 +01001833 dev_notice(ohci->card.device,
1834 "node ID not valid, new bus reset in progress\n");
Kristian Høgsberged568912006-12-19 19:58:35 -05001835 return;
1836 }
Stefan Richter02ff8f82007-08-30 00:11:40 +02001837 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
Stefan Richter64d21722011-12-20 21:32:46 +01001838 dev_notice(ohci->card.device, "malconfigured bus\n");
Stefan Richter02ff8f82007-08-30 00:11:40 +02001839 return;
1840 }
1841 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1842 OHCI1394_NodeID_nodeNumber);
Kristian Høgsberged568912006-12-19 19:58:35 -05001843
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02001844 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1845 if (!(ohci->is_root && is_new_root))
1846 reg_write(ohci, OHCI1394_LinkControlSet,
1847 OHCI1394_LinkControl_cycleMaster);
1848 ohci->is_root = is_new_root;
1849
Stefan Richterc8a9a492008-03-19 21:40:32 +01001850 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1851 if (reg & OHCI1394_SelfIDCount_selfIDError) {
Stefan Richter64d21722011-12-20 21:32:46 +01001852 dev_notice(ohci->card.device, "inconsistent self IDs\n");
Stefan Richterc8a9a492008-03-19 21:40:32 +01001853 return;
1854 }
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001855 /*
1856 * The count in the SelfIDCount register is the number of
Kristian Høgsberged568912006-12-19 19:58:35 -05001857 * bytes in the self ID receive buffer. Since we also receive
1858 * the inverted quadlets and a header quadlet, we shift one
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001859 * bit extra to get the actual number of self IDs.
1860 */
Stefan Richter928ec5f2009-09-06 18:49:17 +02001861 self_id_count = (reg >> 3) & 0xff;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001862
1863 if (self_id_count > 252) {
Stefan Richter64d21722011-12-20 21:32:46 +01001864 dev_notice(ohci->card.device, "inconsistent self IDs\n");
Stefan Richter016bf3d2008-03-19 22:05:02 +01001865 return;
1866 }
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001867
Stefan Richter11bf20a2008-03-01 02:47:15 +01001868 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
Stefan Richteree71c2f2007-08-25 14:08:19 +02001869 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001870
1871 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
Stefan Richterc8a9a492008-03-19 21:40:32 +01001872 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
Clemens Ladisch32eaeae2011-10-15 18:14:39 +02001873 /*
1874 * If the invalid data looks like a cycle start packet,
1875 * it's likely to be the result of the cycle master
1876 * having a wrong gap count. In this case, the self IDs
1877 * so far are valid and should be processed so that the
1878 * bus manager can then correct the gap count.
1879 */
1880 if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1881 == 0xffff008f) {
Stefan Richter64d21722011-12-20 21:32:46 +01001882 dev_notice(ohci->card.device,
1883 "ignoring spurious self IDs\n");
Clemens Ladisch32eaeae2011-10-15 18:14:39 +02001884 self_id_count = j;
1885 break;
1886 } else {
Stefan Richter64d21722011-12-20 21:32:46 +01001887 dev_notice(ohci->card.device,
1888 "inconsistent self IDs\n");
Clemens Ladisch32eaeae2011-10-15 18:14:39 +02001889 return;
1890 }
Stefan Richterc8a9a492008-03-19 21:40:32 +01001891 }
Stefan Richter11bf20a2008-03-01 02:47:15 +01001892 ohci->self_id_buffer[j] =
1893 cond_le32_to_cpu(ohci->self_id_cpu[i]);
Kristian Høgsberged568912006-12-19 19:58:35 -05001894 }
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001895
1896 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1897 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1898 if (self_id_count < 0) {
Stefan Richter64d21722011-12-20 21:32:46 +01001899 dev_notice(ohci->card.device,
1900 "could not construct local self ID\n");
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001901 return;
1902 }
1903 }
1904
1905 if (self_id_count == 0) {
Stefan Richter64d21722011-12-20 21:32:46 +01001906 dev_notice(ohci->card.device, "inconsistent self IDs\n");
Stephan Gatzka25935eb2011-09-12 22:23:53 +02001907 return;
1908 }
Stefan Richteree71c2f2007-08-25 14:08:19 +02001909 rmb();
Kristian Høgsberged568912006-12-19 19:58:35 -05001910
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001911 /*
1912 * Check the consistency of the self IDs we just read. The
Kristian Høgsberged568912006-12-19 19:58:35 -05001913 * problem we face is that a new bus reset can start while we
1914 * read out the self IDs from the DMA buffer. If this happens,
1915 * the DMA buffer will be overwritten with new self IDs and we
1916 * will read out inconsistent data. The OHCI specification
1917 * (section 11.2) recommends a technique similar to
1918 * linux/seqlock.h, where we remember the generation of the
1919 * self IDs in the buffer before reading them out and compare
1920 * it to the current generation after reading them out. If
1921 * the two generations match we know we have a consistent set
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001922 * of self IDs.
1923 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001924
1925 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1926 if (new_generation != generation) {
Stefan Richter64d21722011-12-20 21:32:46 +01001927 dev_notice(ohci->card.device,
1928 "new bus reset, discarding self ids\n");
Kristian Høgsberged568912006-12-19 19:58:35 -05001929 return;
1930 }
1931
1932 /* FIXME: Document how the locking works. */
1933 spin_lock_irqsave(&ohci->lock, flags);
1934
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001935 ohci->generation = -1; /* prevent AT packet queueing */
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05001936 context_stop(&ohci->at_request_ctx);
1937 context_stop(&ohci->at_response_ctx);
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001938
1939 spin_unlock_irqrestore(&ohci->lock, flags);
1940
Stefan Richter78dec562011-01-01 15:15:40 +01001941 /*
1942 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1943 * packets in the AT queues and software needs to drain them.
1944 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1945 */
Clemens Ladisch82b662d2010-12-24 14:40:15 +01001946 at_context_flush(&ohci->at_request_ctx);
1947 at_context_flush(&ohci->at_response_ctx);
1948
1949 spin_lock_irqsave(&ohci->lock, flags);
1950
1951 ohci->generation = generation;
Kristian Høgsberged568912006-12-19 19:58:35 -05001952 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1953
Stefan Richter4a635592010-02-21 17:58:01 +01001954 if (ohci->quirks & QUIRK_RESET_PACKET)
Stefan Richterd34316a2008-04-12 22:31:25 +02001955 ohci->request_generation = generation;
1956
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001957 /*
1958 * This next bit is unrelated to the AT context stuff but we
Kristian Høgsberged568912006-12-19 19:58:35 -05001959 * have to do it under the spinlock also. If a new config rom
1960 * was set up before this reset, the old one is now no longer
1961 * in use and we can free it. Update the config rom pointers
1962 * to point to the current config rom and clear the
Thomas Weber88393162010-03-16 11:47:56 +01001963 * next_config_rom pointer so a new update can take place.
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001964 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001965
1966 if (ohci->next_config_rom != NULL) {
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04001967 if (ohci->next_config_rom != ohci->config_rom) {
1968 free_rom = ohci->config_rom;
1969 free_rom_bus = ohci->config_rom_bus;
1970 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001971 ohci->config_rom = ohci->next_config_rom;
1972 ohci->config_rom_bus = ohci->next_config_rom_bus;
1973 ohci->next_config_rom = NULL;
1974
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001975 /*
1976 * Restore config_rom image and manually update
Kristian Høgsberged568912006-12-19 19:58:35 -05001977 * config_rom registers. Writing the header quadlet
1978 * will indicate that the config rom is ready, so we
Kristian Høgsbergc781c062007-05-07 20:33:32 -04001979 * do that last.
1980 */
Kristian Høgsberged568912006-12-19 19:58:35 -05001981 reg_write(ohci, OHCI1394_BusOptions,
1982 be32_to_cpu(ohci->config_rom[2]));
Stefan Richter8e859732009-10-08 00:41:59 +02001983 ohci->config_rom[0] = ohci->next_header;
1984 reg_write(ohci, OHCI1394_ConfigROMhdr,
1985 be32_to_cpu(ohci->next_header));
Kristian Høgsberged568912006-12-19 19:58:35 -05001986 }
1987
Stefan Richter080de8c2008-02-28 20:54:43 +01001988#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1989 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1990 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1991#endif
1992
Kristian Høgsberged568912006-12-19 19:58:35 -05001993 spin_unlock_irqrestore(&ohci->lock, flags);
1994
Stefan Richter4eaff7d2007-07-25 19:18:08 +02001995 if (free_rom)
1996 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1997 free_rom, free_rom_bus);
1998
Stefan Richter64d21722011-12-20 21:32:46 +01001999 log_selfids(ohci, generation, self_id_count);
Stefan Richterad3c0fe2008-03-20 22:04:36 +01002000
Kristian Høgsberge636fe22007-01-26 00:38:04 -05002001 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
Stefan Richterc8a94de2010-06-12 20:34:50 +02002002 self_id_count, ohci->self_id_buffer,
2003 ohci->csr_state_setclear_abdicate);
2004 ohci->csr_state_setclear_abdicate = false;
Kristian Høgsberged568912006-12-19 19:58:35 -05002005}
2006
2007static irqreturn_t irq_handler(int irq, void *data)
2008{
2009 struct fw_ohci *ohci = data;
Stefan Richter168cf9a2010-02-14 18:49:18 +01002010 u32 event, iso_event;
Kristian Høgsberged568912006-12-19 19:58:35 -05002011 int i;
2012
2013 event = reg_read(ohci, OHCI1394_IntEventClear);
2014
Stefan Richtera5159582007-06-09 19:31:14 +02002015 if (!event || !~event)
Kristian Høgsberged568912006-12-19 19:58:35 -05002016 return IRQ_NONE;
2017
Clemens Ladisch8327b372010-11-30 08:24:32 +01002018 /*
2019 * busReset and postedWriteErr must not be cleared yet
2020 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2021 */
2022 reg_write(ohci, OHCI1394_IntEventClear,
2023 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
Stefan Richter64d21722011-12-20 21:32:46 +01002024 log_irqs(ohci, event);
Kristian Høgsberged568912006-12-19 19:58:35 -05002025
2026 if (event & OHCI1394_selfIDComplete)
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02002027 queue_work(fw_workqueue, &ohci->bus_reset_work);
Kristian Høgsberged568912006-12-19 19:58:35 -05002028
2029 if (event & OHCI1394_RQPkt)
2030 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2031
2032 if (event & OHCI1394_RSPkt)
2033 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2034
2035 if (event & OHCI1394_reqTxComplete)
2036 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2037
2038 if (event & OHCI1394_respTxComplete)
2039 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2040
Clemens Ladisch2dd5bed2010-11-30 08:25:05 +01002041 if (event & OHCI1394_isochRx) {
2042 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2043 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
Kristian Høgsberged568912006-12-19 19:58:35 -05002044
Clemens Ladisch2dd5bed2010-11-30 08:25:05 +01002045 while (iso_event) {
2046 i = ffs(iso_event) - 1;
2047 tasklet_schedule(
2048 &ohci->ir_context_list[i].context.tasklet);
2049 iso_event &= ~(1 << i);
2050 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002051 }
2052
Clemens Ladisch2dd5bed2010-11-30 08:25:05 +01002053 if (event & OHCI1394_isochTx) {
2054 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2055 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
Kristian Høgsberged568912006-12-19 19:58:35 -05002056
Clemens Ladisch2dd5bed2010-11-30 08:25:05 +01002057 while (iso_event) {
2058 i = ffs(iso_event) - 1;
2059 tasklet_schedule(
2060 &ohci->it_context_list[i].context.tasklet);
2061 iso_event &= ~(1 << i);
2062 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002063 }
2064
Jarod Wilson75f78322008-04-03 17:18:23 -04002065 if (unlikely(event & OHCI1394_regAccessFail))
Stefan Richter98466cc2012-03-04 14:24:31 +01002066 dev_err(ohci->card.device, "register access failure\n");
Jarod Wilson75f78322008-04-03 17:18:23 -04002067
Clemens Ladisch8327b372010-11-30 08:24:32 +01002068 if (unlikely(event & OHCI1394_postedWriteErr)) {
2069 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2070 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2071 reg_write(ohci, OHCI1394_IntEventClear,
2072 OHCI1394_postedWriteErr);
Stephan Gatzkaa74477d2011-09-26 21:44:30 +02002073 if (printk_ratelimit())
Stefan Richter64d21722011-12-20 21:32:46 +01002074 dev_err(ohci->card.device, "PCI posted write error\n");
Clemens Ladisch8327b372010-11-30 08:24:32 +01002075 }
Stefan Richtere524f6162007-08-20 21:58:30 +02002076
Stefan Richterbb9f2202007-12-22 22:14:52 +01002077 if (unlikely(event & OHCI1394_cycleTooLong)) {
2078 if (printk_ratelimit())
Stefan Richter64d21722011-12-20 21:32:46 +01002079 dev_notice(ohci->card.device,
2080 "isochronous cycle too long\n");
Stefan Richterbb9f2202007-12-22 22:14:52 +01002081 reg_write(ohci, OHCI1394_LinkControlSet,
2082 OHCI1394_LinkControl_cycleMaster);
2083 }
2084
Jay Fenlason5ed1f322009-11-17 12:29:17 -05002085 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2086 /*
2087 * We need to clear this event bit in order to make
2088 * cycleMatch isochronous I/O work. In theory we should
2089 * stop active cycleMatch iso contexts now and restart
2090 * them at least two cycles later. (FIXME?)
2091 */
2092 if (printk_ratelimit())
Stefan Richter64d21722011-12-20 21:32:46 +01002093 dev_notice(ohci->card.device,
2094 "isochronous cycle inconsistent\n");
Jay Fenlason5ed1f322009-11-17 12:29:17 -05002095 }
2096
Clemens Ladischf117a3e2011-01-10 17:21:35 +01002097 if (unlikely(event & OHCI1394_unrecoverableError))
2098 handle_dead_contexts(ohci);
2099
Clemens Ladischa48777e2010-06-10 08:33:07 +02002100 if (event & OHCI1394_cycle64Seconds) {
2101 spin_lock(&ohci->lock);
2102 update_bus_time(ohci);
2103 spin_unlock(&ohci->lock);
Clemens Ladische597e982010-11-30 08:24:19 +01002104 } else
2105 flush_writes(ohci);
Clemens Ladischa48777e2010-06-10 08:33:07 +02002106
Kristian Høgsberged568912006-12-19 19:58:35 -05002107 return IRQ_HANDLED;
2108}
2109
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002110static int software_reset(struct fw_ohci *ohci)
2111{
Stefan Richter9f426172011-07-03 17:39:26 +02002112 u32 val;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002113 int i;
2114
2115 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
Stefan Richter9f426172011-07-03 17:39:26 +02002116 for (i = 0; i < 500; i++) {
2117 val = reg_read(ohci, OHCI1394_HCControlSet);
2118 if (!~val)
2119 return -ENODEV; /* Card was ejected. */
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002120
Stefan Richter9f426172011-07-03 17:39:26 +02002121 if (!(val & OHCI1394_HCControl_softReset))
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002122 return 0;
Stefan Richter9f426172011-07-03 17:39:26 +02002123
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002124 msleep(1);
2125 }
2126
2127 return -EBUSY;
2128}
2129
Stefan Richter8e859732009-10-08 00:41:59 +02002130static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2131{
2132 size_t size = length * 4;
2133
2134 memcpy(dest, src, size);
2135 if (size < CONFIG_ROM_SIZE)
2136 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2137}
2138
Clemens Ladisch925e7a62010-04-04 15:19:54 +02002139static int configure_1394a_enhancements(struct fw_ohci *ohci)
2140{
2141 bool enable_1394a;
Stefan Richter35d999b2010-04-10 16:04:56 +02002142 int ret, clear, set, offset;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02002143
2144 /* Check if the driver should configure link and PHY. */
2145 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2146 OHCI1394_HCControl_programPhyEnable))
2147 return 0;
2148
2149 /* Paranoia: check whether the PHY supports 1394a, too. */
2150 enable_1394a = false;
Stefan Richter35d999b2010-04-10 16:04:56 +02002151 ret = read_phy_reg(ohci, 2);
2152 if (ret < 0)
2153 return ret;
2154 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2155 ret = read_paged_phy_reg(ohci, 1, 8);
2156 if (ret < 0)
2157 return ret;
2158 if (ret >= 1)
Clemens Ladisch925e7a62010-04-04 15:19:54 +02002159 enable_1394a = true;
2160 }
2161
2162 if (ohci->quirks & QUIRK_NO_1394A)
2163 enable_1394a = false;
2164
2165 /* Configure PHY and link consistently. */
2166 if (enable_1394a) {
2167 clear = 0;
2168 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2169 } else {
2170 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2171 set = 0;
2172 }
Stefan Richter02d37be2010-07-08 16:09:06 +02002173 ret = update_phy_reg(ohci, 5, clear, set);
Stefan Richter35d999b2010-04-10 16:04:56 +02002174 if (ret < 0)
2175 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02002176
2177 if (enable_1394a)
2178 offset = OHCI1394_HCControlSet;
2179 else
2180 offset = OHCI1394_HCControlClear;
2181 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2182
2183 /* Clean up: configuration has been taken care of. */
2184 reg_write(ohci, OHCI1394_HCControlClear,
2185 OHCI1394_HCControl_programPhyEnable);
2186
2187 return 0;
2188}
2189
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002190static int probe_tsb41ba3d(struct fw_ohci *ohci)
2191{
Stefan Richterb810e4a2011-09-19 09:29:30 +02002192 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2193 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2194 int reg, i;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002195
2196 reg = read_phy_reg(ohci, 2);
2197 if (reg < 0)
2198 return reg;
Stefan Richterb810e4a2011-09-19 09:29:30 +02002199 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2200 return 0;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002201
Stefan Richterb810e4a2011-09-19 09:29:30 +02002202 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2203 reg = read_paged_phy_reg(ohci, 1, i + 10);
2204 if (reg < 0)
2205 return reg;
2206 if (reg != id[i])
2207 return 0;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002208 }
Stefan Richterb810e4a2011-09-19 09:29:30 +02002209 return 1;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002210}
2211
Stefan Richter8e859732009-10-08 00:41:59 +02002212static int ohci_enable(struct fw_card *card,
2213 const __be32 *config_rom, size_t length)
Kristian Høgsberged568912006-12-19 19:58:35 -05002214{
2215 struct fw_ohci *ohci = fw_ohci(card);
2216 struct pci_dev *dev = to_pci_dev(card->device);
Clemens Ladische91b2782010-06-10 08:40:49 +02002217 u32 lps, seconds, version, irqs;
Stefan Richter28897fb2011-09-19 00:17:37 +02002218 int i, ret;
Kristian Høgsberged568912006-12-19 19:58:35 -05002219
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002220 if (software_reset(ohci)) {
Stefan Richter64d21722011-12-20 21:32:46 +01002221 dev_err(card->device, "failed to reset ohci card\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002222 return -EBUSY;
2223 }
2224
2225 /*
2226 * Now enable LPS, which we need in order to start accessing
2227 * most of the registers. In fact, on some cards (ALI M5251),
2228 * accessing registers in the SClk domain without LPS enabled
2229 * will lock up the machine. Wait 50msec to make sure we have
Jarod Wilson02214722008-03-28 10:02:50 -04002230 * full link enabled. However, with some cards (well, at least
2231 * a JMicron PCIe card), we have to try again sometimes.
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002232 */
2233 reg_write(ohci, OHCI1394_HCControlSet,
2234 OHCI1394_HCControl_LPS |
2235 OHCI1394_HCControl_postedWriteEnable);
2236 flush_writes(ohci);
Jarod Wilson02214722008-03-28 10:02:50 -04002237
2238 for (lps = 0, i = 0; !lps && i < 3; i++) {
2239 msleep(50);
2240 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2241 OHCI1394_HCControl_LPS;
2242 }
2243
2244 if (!lps) {
Stefan Richter64d21722011-12-20 21:32:46 +01002245 dev_err(card->device, "failed to set Link Power Status\n");
Jarod Wilson02214722008-03-28 10:02:50 -04002246 return -EIO;
2247 }
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002248
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002249 if (ohci->quirks & QUIRK_TI_SLLZ059) {
Stefan Richter28897fb2011-09-19 00:17:37 +02002250 ret = probe_tsb41ba3d(ohci);
2251 if (ret < 0)
2252 return ret;
2253 if (ret)
Stefan Richter64d21722011-12-20 21:32:46 +01002254 dev_notice(card->device, "local TSB41BA3D phy\n");
Stefan Richter28897fb2011-09-19 00:17:37 +02002255 else
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002256 ohci->quirks &= ~QUIRK_TI_SLLZ059;
Stephan Gatzka25935eb2011-09-12 22:23:53 +02002257 }
2258
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002259 reg_write(ohci, OHCI1394_HCControlClear,
2260 OHCI1394_HCControl_noByteSwapData);
2261
Stefan Richteraffc9c22008-06-05 20:50:53 +02002262 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002263 reg_write(ohci, OHCI1394_LinkControlSet,
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002264 OHCI1394_LinkControl_cycleTimerEnable |
2265 OHCI1394_LinkControl_cycleMaster);
2266
2267 reg_write(ohci, OHCI1394_ATRetries,
2268 OHCI1394_MAX_AT_REQ_RETRIES |
2269 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
Clemens Ladisch27a23292010-06-10 08:34:13 +02002270 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2271 (200 << 16));
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002272
Clemens Ladischa48777e2010-06-10 08:33:07 +02002273 seconds = lower_32_bits(get_seconds());
2274 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2275 ohci->bus_time = seconds & ~0x3f;
2276
Clemens Ladische91b2782010-06-10 08:40:49 +02002277 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2278 if (version >= OHCI_VERSION_1_1) {
2279 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2280 0xfffffffe);
Stefan Richterdb3c9cc2010-06-12 20:30:21 +02002281 card->broadcast_channel_auto_allocated = true;
Clemens Ladische91b2782010-06-10 08:40:49 +02002282 }
2283
Clemens Ladischa1a11322010-06-10 08:35:06 +02002284 /* Get implemented bits of the priority arbitration request counter. */
2285 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2286 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2287 reg_write(ohci, OHCI1394_FairnessControl, 0);
Stefan Richterdb3c9cc2010-06-12 20:30:21 +02002288 card->priority_budget_implemented = ohci->pri_req_max != 0;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002289
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002290 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2291 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2292 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002293
Stefan Richter35d999b2010-04-10 16:04:56 +02002294 ret = configure_1394a_enhancements(ohci);
2295 if (ret < 0)
2296 return ret;
Clemens Ladisch925e7a62010-04-04 15:19:54 +02002297
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002298 /* Activate link_on bit and contender bit in our self ID packets.*/
Stefan Richter35d999b2010-04-10 16:04:56 +02002299 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2300 if (ret < 0)
2301 return ret;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04002302
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002303 /*
2304 * When the link is not yet enabled, the atomic config rom
Kristian Høgsberged568912006-12-19 19:58:35 -05002305 * update mechanism described below in ohci_set_config_rom()
2306 * is not active. We have to update ConfigRomHeader and
2307 * BusOptions manually, and the write to ConfigROMmap takes
2308 * effect immediately. We tie this to the enabling of the
2309 * link, so we have a valid config rom before enabling - the
2310 * OHCI requires that ConfigROMhdr and BusOptions have valid
2311 * values before enabling.
2312 *
2313 * However, when the ConfigROMmap is written, some controllers
2314 * always read back quadlets 0 and 2 from the config rom to
2315 * the ConfigRomHeader and BusOptions registers on bus reset.
2316 * They shouldn't do that in this initial case where the link
2317 * isn't enabled. This means we have to use the same
2318 * workaround here, setting the bus header to 0 and then write
2319 * the right values in the bus reset tasklet.
2320 */
2321
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04002322 if (config_rom) {
2323 ohci->next_config_rom =
2324 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2325 &ohci->next_config_rom_bus,
2326 GFP_KERNEL);
2327 if (ohci->next_config_rom == NULL)
2328 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05002329
Stefan Richter8e859732009-10-08 00:41:59 +02002330 copy_config_rom(ohci->next_config_rom, config_rom, length);
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04002331 } else {
2332 /*
2333 * In the suspend case, config_rom is NULL, which
2334 * means that we just reuse the old config rom.
2335 */
2336 ohci->next_config_rom = ohci->config_rom;
2337 ohci->next_config_rom_bus = ohci->config_rom_bus;
2338 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002339
Stefan Richter8e859732009-10-08 00:41:59 +02002340 ohci->next_header = ohci->next_config_rom[0];
Kristian Høgsberged568912006-12-19 19:58:35 -05002341 ohci->next_config_rom[0] = 0;
2342 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
Kristian Høgsberg0bd243c2007-06-05 19:27:05 -04002343 reg_write(ohci, OHCI1394_BusOptions,
2344 be32_to_cpu(ohci->next_config_rom[2]));
Kristian Høgsberged568912006-12-19 19:58:35 -05002345 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2346
2347 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2348
Clemens Ladisch262444e2010-06-05 12:31:25 +02002349 if (!(ohci->quirks & QUIRK_NO_MSI))
2350 pci_enable_msi(dev);
Kristian Høgsberged568912006-12-19 19:58:35 -05002351 if (request_irq(dev->irq, irq_handler,
Clemens Ladisch262444e2010-06-05 12:31:25 +02002352 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2353 ohci_driver_name, ohci)) {
Stefan Richter64d21722011-12-20 21:32:46 +01002354 dev_err(card->device, "failed to allocate interrupt %d\n",
2355 dev->irq);
Clemens Ladisch262444e2010-06-05 12:31:25 +02002356 pci_disable_msi(dev);
Stefan Richtera01e8362011-08-11 20:40:42 +02002357
2358 if (config_rom) {
2359 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2360 ohci->next_config_rom,
2361 ohci->next_config_rom_bus);
2362 ohci->next_config_rom = NULL;
2363 }
Kristian Høgsberged568912006-12-19 19:58:35 -05002364 return -EIO;
2365 }
2366
Stefan Richter148c7862010-06-05 11:46:49 +02002367 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2368 OHCI1394_RQPkt | OHCI1394_RSPkt |
2369 OHCI1394_isochTx | OHCI1394_isochRx |
2370 OHCI1394_postedWriteErr |
2371 OHCI1394_selfIDComplete |
2372 OHCI1394_regAccessFail |
Clemens Ladischa48777e2010-06-10 08:33:07 +02002373 OHCI1394_cycle64Seconds |
Clemens Ladischf117a3e2011-01-10 17:21:35 +01002374 OHCI1394_cycleInconsistent |
2375 OHCI1394_unrecoverableError |
2376 OHCI1394_cycleTooLong |
Stefan Richter148c7862010-06-05 11:46:49 +02002377 OHCI1394_masterIntEnable;
2378 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2379 irqs |= OHCI1394_busReset;
2380 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2381
Kristian Høgsberged568912006-12-19 19:58:35 -05002382 reg_write(ohci, OHCI1394_HCControlSet,
2383 OHCI1394_HCControl_linkEnable |
2384 OHCI1394_HCControl_BIBimageValid);
Clemens Ladischecf83282011-04-11 09:56:12 +02002385
2386 reg_write(ohci, OHCI1394_LinkControlSet,
2387 OHCI1394_LinkControl_rcvSelfID |
2388 OHCI1394_LinkControl_rcvPhyPkt);
2389
2390 ar_context_run(&ohci->ar_request_ctx);
Clemens Ladischdd6254e2011-05-16 08:10:10 +02002391 ar_context_run(&ohci->ar_response_ctx);
2392
2393 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05002394
Stefan Richter02d37be2010-07-08 16:09:06 +02002395 /* We are ready to go, reset bus to finish initialization. */
2396 fw_schedule_bus_reset(&ohci->card, false, true);
Kristian Høgsberged568912006-12-19 19:58:35 -05002397
2398 return 0;
2399}
2400
Stefan Richter53dca512008-12-14 21:47:04 +01002401static int ohci_set_config_rom(struct fw_card *card,
Stefan Richter8e859732009-10-08 00:41:59 +02002402 const __be32 *config_rom, size_t length)
Kristian Høgsberged568912006-12-19 19:58:35 -05002403{
2404 struct fw_ohci *ohci;
2405 unsigned long flags;
Kristian Høgsberged568912006-12-19 19:58:35 -05002406 __be32 *next_config_rom;
Stefan Richterf5101d582008-03-14 00:27:49 +01002407 dma_addr_t uninitialized_var(next_config_rom_bus);
Kristian Høgsberged568912006-12-19 19:58:35 -05002408
2409 ohci = fw_ohci(card);
2410
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002411 /*
2412 * When the OHCI controller is enabled, the config rom update
Kristian Høgsberged568912006-12-19 19:58:35 -05002413 * mechanism is a bit tricky, but easy enough to use. See
2414 * section 5.5.6 in the OHCI specification.
2415 *
2416 * The OHCI controller caches the new config rom address in a
2417 * shadow register (ConfigROMmapNext) and needs a bus reset
2418 * for the changes to take place. When the bus reset is
2419 * detected, the controller loads the new values for the
2420 * ConfigRomHeader and BusOptions registers from the specified
2421 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2422 * shadow register. All automatically and atomically.
2423 *
2424 * Now, there's a twist to this story. The automatic load of
2425 * ConfigRomHeader and BusOptions doesn't honor the
2426 * noByteSwapData bit, so with a be32 config rom, the
2427 * controller will load be32 values in to these registers
2428 * during the atomic update, even on litte endian
2429 * architectures. The workaround we use is to put a 0 in the
2430 * header quadlet; 0 is endian agnostic and means that the
2431 * config rom isn't ready yet. In the bus reset tasklet we
2432 * then set up the real values for the two registers.
2433 *
2434 * We use ohci->lock to avoid racing with the code that sets
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02002435 * ohci->next_config_rom to NULL (see bus_reset_work).
Kristian Høgsberged568912006-12-19 19:58:35 -05002436 */
2437
2438 next_config_rom =
2439 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2440 &next_config_rom_bus, GFP_KERNEL);
2441 if (next_config_rom == NULL)
2442 return -ENOMEM;
2443
2444 spin_lock_irqsave(&ohci->lock, flags);
2445
B.J. Buchalter2e053a22011-05-02 13:33:42 -04002446 /*
2447 * If there is not an already pending config_rom update,
2448 * push our new allocation into the ohci->next_config_rom
2449 * and then mark the local variable as null so that we
2450 * won't deallocate the new buffer.
2451 *
2452 * OTOH, if there is a pending config_rom update, just
2453 * use that buffer with the new config_rom data, and
2454 * let this routine free the unused DMA allocation.
2455 */
2456
Kristian Høgsberged568912006-12-19 19:58:35 -05002457 if (ohci->next_config_rom == NULL) {
2458 ohci->next_config_rom = next_config_rom;
2459 ohci->next_config_rom_bus = next_config_rom_bus;
B.J. Buchalter2e053a22011-05-02 13:33:42 -04002460 next_config_rom = NULL;
Kristian Høgsberged568912006-12-19 19:58:35 -05002461 }
2462
B.J. Buchalter2e053a22011-05-02 13:33:42 -04002463 copy_config_rom(ohci->next_config_rom, config_rom, length);
2464
2465 ohci->next_header = config_rom[0];
2466 ohci->next_config_rom[0] = 0;
2467
2468 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2469
Kristian Høgsberged568912006-12-19 19:58:35 -05002470 spin_unlock_irqrestore(&ohci->lock, flags);
2471
B.J. Buchalter2e053a22011-05-02 13:33:42 -04002472 /* If we didn't use the DMA allocation, delete it. */
2473 if (next_config_rom != NULL)
2474 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2475 next_config_rom, next_config_rom_bus);
2476
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002477 /*
2478 * Now initiate a bus reset to have the changes take
Kristian Høgsberged568912006-12-19 19:58:35 -05002479 * effect. We clean up the old config rom memory and DMA
2480 * mappings in the bus reset tasklet, since the OHCI
2481 * controller could need to access it before the bus reset
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002482 * takes effect.
2483 */
Kristian Høgsberged568912006-12-19 19:58:35 -05002484
B.J. Buchalter2e053a22011-05-02 13:33:42 -04002485 fw_schedule_bus_reset(&ohci->card, true, true);
2486
2487 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05002488}
2489
2490static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2491{
2492 struct fw_ohci *ohci = fw_ohci(card);
2493
2494 at_context_transmit(&ohci->at_request_ctx, packet);
2495}
2496
2497static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2498{
2499 struct fw_ohci *ohci = fw_ohci(card);
2500
2501 at_context_transmit(&ohci->at_response_ctx, packet);
2502}
2503
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002504static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2505{
2506 struct fw_ohci *ohci = fw_ohci(card);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002507 struct context *ctx = &ohci->at_request_ctx;
2508 struct driver_data *driver_data = packet->driver_data;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002509 int ret = -ENOENT;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002510
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002511 tasklet_disable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002512
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002513 if (packet->ack != 0)
2514 goto out;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002515
Stefan Richter19593ff2009-10-14 20:40:10 +02002516 if (packet->payload_mapped)
Stefan Richter1d1dc5e2008-12-10 00:20:38 +01002517 dma_unmap_single(ohci->card.device, packet->payload_bus,
2518 packet->payload_length, DMA_TO_DEVICE);
2519
Stefan Richter64d21722011-12-20 21:32:46 +01002520 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002521 driver_data->packet = NULL;
2522 packet->ack = RCODE_CANCELLED;
2523 packet->callback(packet, &ohci->card, packet->ack);
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002524 ret = 0;
Kristian Høgsbergf319b6a2007-03-07 12:12:49 -05002525 out:
2526 tasklet_enable(&ctx->tasklet);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002527
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002528 return ret;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05002529}
2530
Stefan Richter53dca512008-12-14 21:47:04 +01002531static int ohci_enable_phys_dma(struct fw_card *card,
2532 int node_id, int generation)
Kristian Høgsberged568912006-12-19 19:58:35 -05002533{
Stefan Richter080de8c2008-02-28 20:54:43 +01002534#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2535 return 0;
2536#else
Kristian Høgsberged568912006-12-19 19:58:35 -05002537 struct fw_ohci *ohci = fw_ohci(card);
2538 unsigned long flags;
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002539 int n, ret = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05002540
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002541 /*
2542 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2543 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2544 */
Kristian Høgsberged568912006-12-19 19:58:35 -05002545
2546 spin_lock_irqsave(&ohci->lock, flags);
2547
2548 if (ohci->generation != generation) {
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002549 ret = -ESTALE;
Kristian Høgsberged568912006-12-19 19:58:35 -05002550 goto out;
2551 }
2552
Kristian Høgsbergc781c062007-05-07 20:33:32 -04002553 /*
2554 * Note, if the node ID contains a non-local bus ID, physical DMA is
2555 * enabled for _all_ nodes on remote buses.
2556 */
Stefan Richter907293d2007-01-23 21:11:43 +01002557
2558 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2559 if (n < 32)
2560 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2561 else
2562 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2563
Kristian Høgsberged568912006-12-19 19:58:35 -05002564 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05002565 out:
Stefan Richter6cad95f2007-01-21 20:46:45 +01002566 spin_unlock_irqrestore(&ohci->lock, flags);
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002567
2568 return ret;
Stefan Richter080de8c2008-02-28 20:54:43 +01002569#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
Kristian Høgsberged568912006-12-19 19:58:35 -05002570}
Stefan Richter373b2ed2007-03-04 14:45:18 +01002571
Stefan Richter0fcff4e2010-06-12 20:35:52 +02002572static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002573{
2574 struct fw_ohci *ohci = fw_ohci(card);
Clemens Ladischa48777e2010-06-10 08:33:07 +02002575 unsigned long flags;
2576 u32 value;
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002577
Clemens Ladisch60d32972010-06-10 08:24:35 +02002578 switch (csr_offset) {
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002579 case CSR_STATE_CLEAR:
2580 case CSR_STATE_SET:
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002581 if (ohci->is_root &&
2582 (reg_read(ohci, OHCI1394_LinkControlSet) &
2583 OHCI1394_LinkControl_cycleMaster))
Stefan Richterc8a94de2010-06-12 20:34:50 +02002584 value = CSR_STATE_BIT_CMSTR;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002585 else
Stefan Richterc8a94de2010-06-12 20:34:50 +02002586 value = 0;
2587 if (ohci->csr_state_setclear_abdicate)
2588 value |= CSR_STATE_BIT_ABDICATE;
Stefan Richter4a9bde92010-02-20 22:24:43 +01002589
Stefan Richterc8a94de2010-06-12 20:34:50 +02002590 return value;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002591
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002592 case CSR_NODE_IDS:
2593 return reg_read(ohci, OHCI1394_NodeID) << 16;
2594
Clemens Ladisch60d32972010-06-10 08:24:35 +02002595 case CSR_CYCLE_TIME:
2596 return get_cycle_time(ohci);
2597
Clemens Ladischa48777e2010-06-10 08:33:07 +02002598 case CSR_BUS_TIME:
2599 /*
2600 * We might be called just after the cycle timer has wrapped
2601 * around but just before the cycle64Seconds handler, so we
2602 * better check here, too, if the bus time needs to be updated.
2603 */
2604 spin_lock_irqsave(&ohci->lock, flags);
2605 value = update_bus_time(ohci);
2606 spin_unlock_irqrestore(&ohci->lock, flags);
2607 return value;
2608
Clemens Ladisch27a23292010-06-10 08:34:13 +02002609 case CSR_BUSY_TIMEOUT:
2610 value = reg_read(ohci, OHCI1394_ATRetries);
2611 return (value >> 4) & 0x0ffff00f;
2612
Clemens Ladischa1a11322010-06-10 08:35:06 +02002613 case CSR_PRIORITY_BUDGET:
2614 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2615 (ohci->pri_req_max << 8);
2616
Clemens Ladisch60d32972010-06-10 08:24:35 +02002617 default:
2618 WARN_ON(1);
2619 return 0;
Clemens Ladischb6775322010-01-20 09:58:02 +01002620 }
Clemens Ladisch60d32972010-06-10 08:24:35 +02002621}
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002622
Stefan Richter0fcff4e2010-06-12 20:35:52 +02002623static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002624{
2625 struct fw_ohci *ohci = fw_ohci(card);
Clemens Ladischa48777e2010-06-10 08:33:07 +02002626 unsigned long flags;
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002627
2628 switch (csr_offset) {
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002629 case CSR_STATE_CLEAR:
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002630 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2631 reg_write(ohci, OHCI1394_LinkControlClear,
2632 OHCI1394_LinkControl_cycleMaster);
2633 flush_writes(ohci);
2634 }
Stefan Richterc8a94de2010-06-12 20:34:50 +02002635 if (value & CSR_STATE_BIT_ABDICATE)
2636 ohci->csr_state_setclear_abdicate = false;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002637 break;
2638
2639 case CSR_STATE_SET:
2640 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2641 reg_write(ohci, OHCI1394_LinkControlSet,
2642 OHCI1394_LinkControl_cycleMaster);
2643 flush_writes(ohci);
2644 }
Stefan Richterc8a94de2010-06-12 20:34:50 +02002645 if (value & CSR_STATE_BIT_ABDICATE)
2646 ohci->csr_state_setclear_abdicate = true;
Clemens Ladisch4ffb7a62010-06-10 08:36:37 +02002647 break;
2648
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002649 case CSR_NODE_IDS:
2650 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2651 flush_writes(ohci);
2652 break;
2653
Clemens Ladisch9ab50712010-06-10 08:26:48 +02002654 case CSR_CYCLE_TIME:
2655 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2656 reg_write(ohci, OHCI1394_IntEventSet,
2657 OHCI1394_cycleInconsistent);
2658 flush_writes(ohci);
2659 break;
2660
Clemens Ladischa48777e2010-06-10 08:33:07 +02002661 case CSR_BUS_TIME:
2662 spin_lock_irqsave(&ohci->lock, flags);
2663 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2664 spin_unlock_irqrestore(&ohci->lock, flags);
2665 break;
2666
Clemens Ladisch27a23292010-06-10 08:34:13 +02002667 case CSR_BUSY_TIMEOUT:
2668 value = (value & 0xf) | ((value & 0xf) << 4) |
2669 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2670 reg_write(ohci, OHCI1394_ATRetries, value);
2671 flush_writes(ohci);
2672 break;
2673
Clemens Ladischa1a11322010-06-10 08:35:06 +02002674 case CSR_PRIORITY_BUDGET:
2675 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2676 flush_writes(ohci);
2677 break;
2678
Clemens Ladisch506f1a32010-06-10 08:25:19 +02002679 default:
2680 WARN_ON(1);
2681 break;
2682 }
Kristian Høgsbergd60d7f12007-03-07 12:12:56 -05002683}
2684
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002685static void flush_iso_completions(struct iso_context *ctx)
David Moore1aa292b2008-07-22 23:23:40 -07002686{
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002687 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2688 ctx->header_length, ctx->header,
2689 ctx->base.callback_data);
2690 ctx->header_length = 0;
2691}
David Moore1aa292b2008-07-22 23:23:40 -07002692
Clemens Ladisch73864012012-03-18 19:04:05 +01002693static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
David Moore1aa292b2008-07-22 23:23:40 -07002694{
Clemens Ladisch73864012012-03-18 19:04:05 +01002695 u32 *ctx_hdr;
David Moore1aa292b2008-07-22 23:23:40 -07002696
Clemens Ladisch73864012012-03-18 19:04:05 +01002697 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
Clemens Ladisch18d62712012-03-18 19:05:29 +01002698 flush_iso_completions(ctx);
David Moore1aa292b2008-07-22 23:23:40 -07002699
Clemens Ladisch73864012012-03-18 19:04:05 +01002700 ctx_hdr = ctx->header + ctx->header_length;
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002701 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
David Moore1aa292b2008-07-22 23:23:40 -07002702
2703 /*
Clemens Ladisch32c507f2012-03-18 19:01:39 +01002704 * The two iso header quadlets are byteswapped to little
2705 * endian by the controller, but we want to present them
2706 * as big endian for consistency with the bus endianness.
David Moore1aa292b2008-07-22 23:23:40 -07002707 */
2708 if (ctx->base.header_size > 0)
Clemens Ladisch73864012012-03-18 19:04:05 +01002709 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
David Moore1aa292b2008-07-22 23:23:40 -07002710 if (ctx->base.header_size > 4)
Clemens Ladisch73864012012-03-18 19:04:05 +01002711 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
David Moore1aa292b2008-07-22 23:23:40 -07002712 if (ctx->base.header_size > 8)
Clemens Ladisch73864012012-03-18 19:04:05 +01002713 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
David Moore1aa292b2008-07-22 23:23:40 -07002714 ctx->header_length += ctx->base.header_size;
2715}
2716
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002717static int handle_ir_packet_per_buffer(struct context *context,
2718 struct descriptor *d,
2719 struct descriptor *last)
2720{
2721 struct iso_context *ctx =
2722 container_of(context, struct iso_context, context);
David Moorebcee8932007-12-19 15:26:38 -05002723 struct descriptor *pd;
Clemens Ladischa572e682011-10-15 23:12:23 +02002724 u32 buffer_dma;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002725
Stefan Richter872e3302010-07-29 18:19:22 +02002726 for (pd = d; pd <= last; pd++)
David Moorebcee8932007-12-19 15:26:38 -05002727 if (pd->transfer_status)
2728 break;
David Moorebcee8932007-12-19 15:26:38 -05002729 if (pd > last)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002730 /* Descriptor(s) not done yet, stop iteration */
2731 return 0;
2732
Clemens Ladischa572e682011-10-15 23:12:23 +02002733 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2734 d++;
2735 buffer_dma = le32_to_cpu(d->data_address);
2736 dma_sync_single_range_for_cpu(context->ohci->card.device,
2737 buffer_dma & PAGE_MASK,
2738 buffer_dma & ~PAGE_MASK,
2739 le16_to_cpu(d->req_count),
2740 DMA_FROM_DEVICE);
2741 }
2742
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002743 copy_iso_headers(ctx, (u32 *) (last + 1));
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002744
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002745 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2746 flush_iso_completions(ctx);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002747
Jarod Wilsona186b4a2007-12-03 13:43:12 -05002748 return 1;
2749}
2750
Stefan Richter872e3302010-07-29 18:19:22 +02002751/* d == last because each descriptor block is only a single descriptor. */
2752static int handle_ir_buffer_fill(struct context *context,
2753 struct descriptor *d,
2754 struct descriptor *last)
2755{
2756 struct iso_context *ctx =
2757 container_of(context, struct iso_context, context);
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002758 unsigned int req_count, res_count, completed;
Clemens Ladischa572e682011-10-15 23:12:23 +02002759 u32 buffer_dma;
Stefan Richter872e3302010-07-29 18:19:22 +02002760
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002761 req_count = le16_to_cpu(last->req_count);
2762 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2763 completed = req_count - res_count;
2764 buffer_dma = le32_to_cpu(last->data_address);
2765
2766 if (completed > 0) {
2767 ctx->mc_buffer_bus = buffer_dma;
2768 ctx->mc_completed = completed;
2769 }
2770
2771 if (res_count != 0)
Stefan Richter872e3302010-07-29 18:19:22 +02002772 /* Descriptor(s) not done yet, stop iteration */
2773 return 0;
2774
Clemens Ladischa572e682011-10-15 23:12:23 +02002775 dma_sync_single_range_for_cpu(context->ohci->card.device,
2776 buffer_dma & PAGE_MASK,
2777 buffer_dma & ~PAGE_MASK,
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002778 completed, DMA_FROM_DEVICE);
Clemens Ladischa572e682011-10-15 23:12:23 +02002779
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002780 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
Stefan Richter872e3302010-07-29 18:19:22 +02002781 ctx->base.callback.mc(&ctx->base,
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002782 buffer_dma + completed,
Stefan Richter872e3302010-07-29 18:19:22 +02002783 ctx->base.callback_data);
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002784 ctx->mc_completed = 0;
2785 }
Stefan Richter872e3302010-07-29 18:19:22 +02002786
2787 return 1;
2788}
2789
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002790static void flush_ir_buffer_fill(struct iso_context *ctx)
2791{
2792 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2793 ctx->mc_buffer_bus & PAGE_MASK,
2794 ctx->mc_buffer_bus & ~PAGE_MASK,
2795 ctx->mc_completed, DMA_FROM_DEVICE);
2796
2797 ctx->base.callback.mc(&ctx->base,
2798 ctx->mc_buffer_bus + ctx->mc_completed,
2799 ctx->base.callback_data);
2800 ctx->mc_completed = 0;
2801}
2802
Clemens Ladischa572e682011-10-15 23:12:23 +02002803static inline void sync_it_packet_for_cpu(struct context *context,
2804 struct descriptor *pd)
2805{
2806 __le16 control;
2807 u32 buffer_dma;
2808
2809 /* only packets beginning with OUTPUT_MORE* have data buffers */
2810 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2811 return;
2812
2813 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2814 pd += 2;
2815
2816 /*
2817 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2818 * data buffer is in the context program's coherent page and must not
2819 * be synced.
2820 */
2821 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2822 (context->current_bus & PAGE_MASK)) {
2823 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2824 return;
2825 pd++;
2826 }
2827
2828 do {
2829 buffer_dma = le32_to_cpu(pd->data_address);
2830 dma_sync_single_range_for_cpu(context->ohci->card.device,
2831 buffer_dma & PAGE_MASK,
2832 buffer_dma & ~PAGE_MASK,
2833 le16_to_cpu(pd->req_count),
2834 DMA_TO_DEVICE);
2835 control = pd->control;
2836 pd++;
2837 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2838}
2839
Kristian Høgsberg30200732007-02-16 17:34:39 -05002840static int handle_it_packet(struct context *context,
2841 struct descriptor *d,
2842 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05002843{
Kristian Høgsberg30200732007-02-16 17:34:39 -05002844 struct iso_context *ctx =
2845 container_of(context, struct iso_context, context);
Jay Fenlason31769ce2009-11-21 00:05:56 +01002846 struct descriptor *pd;
Clemens Ladisch73864012012-03-18 19:04:05 +01002847 __be32 *ctx_hdr;
Stefan Richter373b2ed2007-03-04 14:45:18 +01002848
Jay Fenlason31769ce2009-11-21 00:05:56 +01002849 for (pd = d; pd <= last; pd++)
2850 if (pd->transfer_status)
2851 break;
2852 if (pd > last)
2853 /* Descriptor(s) not done yet, stop iteration */
Kristian Høgsberg30200732007-02-16 17:34:39 -05002854 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05002855
Clemens Ladischa572e682011-10-15 23:12:23 +02002856 sync_it_packet_for_cpu(context, d);
2857
Clemens Ladisch18d62712012-03-18 19:05:29 +01002858 if (ctx->header_length + 4 > PAGE_SIZE)
2859 flush_iso_completions(ctx);
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002860
Clemens Ladisch18d62712012-03-18 19:05:29 +01002861 ctx_hdr = ctx->header + ctx->header_length;
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002862 ctx->last_timestamp = le16_to_cpu(last->res_count);
Clemens Ladisch18d62712012-03-18 19:05:29 +01002863 /* Present this value as big-endian to match the receive code */
2864 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2865 le16_to_cpu(pd->res_count));
2866 ctx->header_length += 4;
2867
Clemens Ladisch910e76c2012-03-18 19:04:43 +01002868 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2869 flush_iso_completions(ctx);
2870
Kristian Høgsberg30200732007-02-16 17:34:39 -05002871 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05002872}
2873
Stefan Richter872e3302010-07-29 18:19:22 +02002874static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2875{
2876 u32 hi = channels >> 32, lo = channels;
2877
2878 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2879 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2880 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2881 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2882 mmiowb();
2883 ohci->mc_channels = channels;
2884}
2885
Stefan Richter53dca512008-12-14 21:47:04 +01002886static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
Stefan Richter4817ed22008-12-21 16:39:46 +01002887 int type, int channel, size_t header_size)
Kristian Høgsberged568912006-12-19 19:58:35 -05002888{
2889 struct fw_ohci *ohci = fw_ohci(card);
Stefan Richter872e3302010-07-29 18:19:22 +02002890 struct iso_context *uninitialized_var(ctx);
2891 descriptor_callback_t uninitialized_var(callback);
2892 u64 *uninitialized_var(channels);
2893 u32 *uninitialized_var(mask), uninitialized_var(regs);
Kristian Høgsberged568912006-12-19 19:58:35 -05002894 unsigned long flags;
Stefan Richter872e3302010-07-29 18:19:22 +02002895 int index, ret = -EBUSY;
Kristian Høgsberged568912006-12-19 19:58:35 -05002896
2897 spin_lock_irqsave(&ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02002898
2899 switch (type) {
2900 case FW_ISO_CONTEXT_TRANSMIT:
2901 mask = &ohci->it_context_mask;
2902 callback = handle_it_packet;
2903 index = ffs(*mask) - 1;
2904 if (index >= 0) {
2905 *mask &= ~(1 << index);
2906 regs = OHCI1394_IsoXmitContextBase(index);
2907 ctx = &ohci->it_context_list[index];
2908 }
2909 break;
2910
2911 case FW_ISO_CONTEXT_RECEIVE:
2912 channels = &ohci->ir_context_channels;
2913 mask = &ohci->ir_context_mask;
2914 callback = handle_ir_packet_per_buffer;
2915 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2916 if (index >= 0) {
2917 *channels &= ~(1ULL << channel);
2918 *mask &= ~(1 << index);
2919 regs = OHCI1394_IsoRcvContextBase(index);
2920 ctx = &ohci->ir_context_list[index];
2921 }
2922 break;
2923
2924 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2925 mask = &ohci->ir_context_mask;
2926 callback = handle_ir_buffer_fill;
2927 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2928 if (index >= 0) {
2929 ohci->mc_allocated = true;
2930 *mask &= ~(1 << index);
2931 regs = OHCI1394_IsoRcvContextBase(index);
2932 ctx = &ohci->ir_context_list[index];
2933 }
2934 break;
2935
2936 default:
2937 index = -1;
2938 ret = -ENOSYS;
Stefan Richter4817ed22008-12-21 16:39:46 +01002939 }
Stefan Richter872e3302010-07-29 18:19:22 +02002940
Kristian Høgsberged568912006-12-19 19:58:35 -05002941 spin_unlock_irqrestore(&ohci->lock, flags);
2942
2943 if (index < 0)
Stefan Richter872e3302010-07-29 18:19:22 +02002944 return ERR_PTR(ret);
Kristian Høgsberged568912006-12-19 19:58:35 -05002945
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04002946 memset(ctx, 0, sizeof(*ctx));
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002947 ctx->header_length = 0;
2948 ctx->header = (void *) __get_free_page(GFP_KERNEL);
Stefan Richter872e3302010-07-29 18:19:22 +02002949 if (ctx->header == NULL) {
2950 ret = -ENOMEM;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002951 goto out;
Stefan Richter872e3302010-07-29 18:19:22 +02002952 }
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002953 ret = context_init(&ctx->context, ohci, regs, callback);
2954 if (ret < 0)
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002955 goto out_with_header;
Kristian Høgsberged568912006-12-19 19:58:35 -05002956
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002957 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
Stefan Richter872e3302010-07-29 18:19:22 +02002958 set_multichannel_mask(ohci, 0);
Clemens Ladischd1bbd202012-03-18 19:06:39 +01002959 ctx->mc_completed = 0;
2960 }
Stefan Richter872e3302010-07-29 18:19:22 +02002961
Kristian Høgsberged568912006-12-19 19:58:35 -05002962 return &ctx->base;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002963
2964 out_with_header:
2965 free_page((unsigned long)ctx->header);
2966 out:
2967 spin_lock_irqsave(&ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02002968
2969 switch (type) {
2970 case FW_ISO_CONTEXT_RECEIVE:
2971 *channels |= 1ULL << channel;
2972 break;
2973
2974 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2975 ohci->mc_allocated = false;
2976 break;
2977 }
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002978 *mask |= 1 << index;
Stefan Richter872e3302010-07-29 18:19:22 +02002979
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05002980 spin_unlock_irqrestore(&ohci->lock, flags);
2981
Stefan Richter2dbd7d72008-12-14 21:45:45 +01002982 return ERR_PTR(ret);
Kristian Høgsberged568912006-12-19 19:58:35 -05002983}
2984
Kristian Høgsbergeb0306e2007-03-14 17:34:54 -04002985static int ohci_start_iso(struct fw_iso_context *base,
2986 s32 cycle, u32 sync, u32 tags)
Kristian Høgsberged568912006-12-19 19:58:35 -05002987{
Stefan Richter373b2ed2007-03-04 14:45:18 +01002988 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberg30200732007-02-16 17:34:39 -05002989 struct fw_ohci *ohci = ctx->context.ohci;
Stefan Richter872e3302010-07-29 18:19:22 +02002990 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
Kristian Høgsberged568912006-12-19 19:58:35 -05002991 int index;
2992
Clemens Ladisch44b74d92011-02-23 09:27:40 +01002993 /* the controller cannot start without any queued packets */
2994 if (ctx->context.last->branch_address == 0)
2995 return -ENODATA;
2996
Stefan Richter872e3302010-07-29 18:19:22 +02002997 switch (ctx->base.type) {
2998 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05002999 index = ctx - ohci->it_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04003000 match = 0;
3001 if (cycle >= 0)
3002 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003003 (cycle & 0x7fff) << 16;
Kristian Høgsberg21efb3c2007-02-16 17:34:50 -05003004
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003005 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3006 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04003007 context_run(&ctx->context, match);
Stefan Richter872e3302010-07-29 18:19:22 +02003008 break;
3009
3010 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3011 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3012 /* fall through */
3013 case FW_ISO_CONTEXT_RECEIVE:
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003014 index = ctx - ohci->ir_context_list;
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04003015 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3016 if (cycle >= 0) {
3017 match |= (cycle & 0x07fff) << 12;
3018 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3019 }
Kristian Høgsberged568912006-12-19 19:58:35 -05003020
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003021 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3022 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003023 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
Kristian Høgsberg8a2f7d92007-03-28 14:26:10 -04003024 context_run(&ctx->context, control);
Maxim Levitskydd237362010-11-29 04:09:50 +02003025
3026 ctx->sync = sync;
3027 ctx->tags = tags;
3028
Stefan Richter872e3302010-07-29 18:19:22 +02003029 break;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003030 }
Kristian Høgsberged568912006-12-19 19:58:35 -05003031
3032 return 0;
3033}
3034
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003035static int ohci_stop_iso(struct fw_iso_context *base)
3036{
3037 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01003038 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003039 int index;
3040
Stefan Richter872e3302010-07-29 18:19:22 +02003041 switch (ctx->base.type) {
3042 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003043 index = ctx - ohci->it_context_list;
3044 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
Stefan Richter872e3302010-07-29 18:19:22 +02003045 break;
3046
3047 case FW_ISO_CONTEXT_RECEIVE:
3048 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003049 index = ctx - ohci->ir_context_list;
3050 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
Stefan Richter872e3302010-07-29 18:19:22 +02003051 break;
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003052 }
3053 flush_writes(ohci);
3054 context_stop(&ctx->context);
Clemens Ladische81cbeb2011-02-16 10:32:11 +01003055 tasklet_kill(&ctx->context.tasklet);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003056
3057 return 0;
3058}
3059
Kristian Høgsberged568912006-12-19 19:58:35 -05003060static void ohci_free_iso_context(struct fw_iso_context *base)
3061{
3062 struct fw_ohci *ohci = fw_ohci(base->card);
Stefan Richter373b2ed2007-03-04 14:45:18 +01003063 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberged568912006-12-19 19:58:35 -05003064 unsigned long flags;
3065 int index;
3066
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003067 ohci_stop_iso(base);
3068 context_release(&ctx->context);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05003069 free_page((unsigned long)ctx->header);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003070
Kristian Høgsberged568912006-12-19 19:58:35 -05003071 spin_lock_irqsave(&ohci->lock, flags);
3072
Stefan Richter872e3302010-07-29 18:19:22 +02003073 switch (base->type) {
3074 case FW_ISO_CONTEXT_TRANSMIT:
Kristian Høgsberged568912006-12-19 19:58:35 -05003075 index = ctx - ohci->it_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05003076 ohci->it_context_mask |= 1 << index;
Stefan Richter872e3302010-07-29 18:19:22 +02003077 break;
3078
3079 case FW_ISO_CONTEXT_RECEIVE:
Kristian Høgsberged568912006-12-19 19:58:35 -05003080 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05003081 ohci->ir_context_mask |= 1 << index;
Stefan Richter4817ed22008-12-21 16:39:46 +01003082 ohci->ir_context_channels |= 1ULL << base->channel;
Stefan Richter872e3302010-07-29 18:19:22 +02003083 break;
3084
3085 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3086 index = ctx - ohci->ir_context_list;
3087 ohci->ir_context_mask |= 1 << index;
3088 ohci->ir_context_channels |= ohci->mc_channels;
3089 ohci->mc_channels = 0;
3090 ohci->mc_allocated = false;
3091 break;
Kristian Høgsberged568912006-12-19 19:58:35 -05003092 }
Kristian Høgsberged568912006-12-19 19:58:35 -05003093
3094 spin_unlock_irqrestore(&ohci->lock, flags);
3095}
3096
Stefan Richter872e3302010-07-29 18:19:22 +02003097static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
Kristian Høgsberged568912006-12-19 19:58:35 -05003098{
Stefan Richter872e3302010-07-29 18:19:22 +02003099 struct fw_ohci *ohci = fw_ohci(base->card);
3100 unsigned long flags;
3101 int ret;
3102
3103 switch (base->type) {
3104 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3105
3106 spin_lock_irqsave(&ohci->lock, flags);
3107
3108 /* Don't allow multichannel to grab other contexts' channels. */
3109 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3110 *channels = ohci->ir_context_channels;
3111 ret = -EBUSY;
3112 } else {
3113 set_multichannel_mask(ohci, *channels);
3114 ret = 0;
3115 }
3116
3117 spin_unlock_irqrestore(&ohci->lock, flags);
3118
3119 break;
3120 default:
3121 ret = -EINVAL;
3122 }
3123
3124 return ret;
3125}
3126
Maxim Levitskydd237362010-11-29 04:09:50 +02003127#ifdef CONFIG_PM
3128static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3129{
3130 int i;
3131 struct iso_context *ctx;
3132
3133 for (i = 0 ; i < ohci->n_ir ; i++) {
3134 ctx = &ohci->ir_context_list[i];
Stefan Richter693a50b2011-01-01 15:17:05 +01003135 if (ctx->context.running)
Maxim Levitskydd237362010-11-29 04:09:50 +02003136 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3137 }
3138
3139 for (i = 0 ; i < ohci->n_it ; i++) {
3140 ctx = &ohci->it_context_list[i];
Stefan Richter693a50b2011-01-01 15:17:05 +01003141 if (ctx->context.running)
Maxim Levitskydd237362010-11-29 04:09:50 +02003142 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3143 }
3144}
3145#endif
3146
Stefan Richter872e3302010-07-29 18:19:22 +02003147static int queue_iso_transmit(struct iso_context *ctx,
3148 struct fw_iso_packet *packet,
3149 struct fw_iso_buffer *buffer,
3150 unsigned long payload)
3151{
Kristian Høgsberg30200732007-02-16 17:34:39 -05003152 struct descriptor *d, *last, *pd;
Kristian Høgsberged568912006-12-19 19:58:35 -05003153 struct fw_iso_packet *p;
3154 __le32 *header;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05003155 dma_addr_t d_bus, page_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -05003156 u32 z, header_z, payload_z, irq;
3157 u32 payload_index, payload_end_index, next_page_index;
Kristian Høgsberg30200732007-02-16 17:34:39 -05003158 int page, end_page, i, length, offset;
Kristian Høgsberged568912006-12-19 19:58:35 -05003159
Kristian Høgsberged568912006-12-19 19:58:35 -05003160 p = packet;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05003161 payload_index = payload;
Kristian Høgsberged568912006-12-19 19:58:35 -05003162
3163 if (p->skip)
3164 z = 1;
3165 else
3166 z = 2;
3167 if (p->header_length > 0)
3168 z++;
3169
3170 /* Determine the first page the payload isn't contained in. */
3171 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3172 if (p->payload_length > 0)
3173 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3174 else
3175 payload_z = 0;
3176
3177 z += payload_z;
3178
3179 /* Get header size in number of descriptors. */
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04003180 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05003181
Kristian Høgsberg30200732007-02-16 17:34:39 -05003182 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3183 if (d == NULL)
3184 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05003185
3186 if (!p->skip) {
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003187 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
Kristian Høgsberged568912006-12-19 19:58:35 -05003188 d[0].req_count = cpu_to_le16(8);
Clemens Ladisch7f51a102010-02-08 08:30:03 +01003189 /*
3190 * Link the skip address to this descriptor itself. This causes
3191 * a context to skip a cycle whenever lost cycles or FIFO
3192 * overruns occur, without dropping the data. The application
3193 * should then decide whether this is an error condition or not.
3194 * FIXME: Make the context's cycle-lost behaviour configurable?
3195 */
3196 d[0].branch_address = cpu_to_le32(d_bus | z);
Kristian Høgsberged568912006-12-19 19:58:35 -05003197
3198 header = (__le32 *) &d[1];
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003199 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3200 IT_HEADER_TAG(p->tag) |
3201 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3202 IT_HEADER_CHANNEL(ctx->base.channel) |
3203 IT_HEADER_SPEED(ctx->base.speed));
Kristian Høgsberged568912006-12-19 19:58:35 -05003204 header[1] =
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003205 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
Kristian Høgsberged568912006-12-19 19:58:35 -05003206 p->payload_length));
3207 }
3208
3209 if (p->header_length > 0) {
3210 d[2].req_count = cpu_to_le16(p->header_length);
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04003211 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
Kristian Høgsberged568912006-12-19 19:58:35 -05003212 memcpy(&d[z], p->header, p->header_length);
3213 }
3214
3215 pd = d + z - payload_z;
3216 payload_end_index = payload_index + p->payload_length;
3217 for (i = 0; i < payload_z; i++) {
3218 page = payload_index >> PAGE_SHIFT;
3219 offset = payload_index & ~PAGE_MASK;
3220 next_page_index = (page + 1) << PAGE_SHIFT;
3221 length =
3222 min(next_page_index, payload_end_index) - payload_index;
3223 pd[i].req_count = cpu_to_le16(length);
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05003224
3225 page_bus = page_private(buffer->pages[page]);
3226 pd[i].data_address = cpu_to_le32(page_bus + offset);
Kristian Høgsberged568912006-12-19 19:58:35 -05003227
Clemens Ladischa572e682011-10-15 23:12:23 +02003228 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3229 page_bus, offset, length,
3230 DMA_TO_DEVICE);
3231
Kristian Høgsberged568912006-12-19 19:58:35 -05003232 payload_index += length;
3233 }
3234
Kristian Høgsberged568912006-12-19 19:58:35 -05003235 if (p->interrupt)
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003236 irq = DESCRIPTOR_IRQ_ALWAYS;
Kristian Høgsberged568912006-12-19 19:58:35 -05003237 else
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003238 irq = DESCRIPTOR_NO_IRQ;
Kristian Høgsberged568912006-12-19 19:58:35 -05003239
Kristian Høgsberg30200732007-02-16 17:34:39 -05003240 last = z == 2 ? d : d + z - 1;
Kristian Høgsberga77754a2007-05-07 20:33:35 -04003241 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3242 DESCRIPTOR_STATUS |
3243 DESCRIPTOR_BRANCH_ALWAYS |
Kristian Høgsbergcbb59da2007-02-16 17:34:35 -05003244 irq);
Kristian Høgsberged568912006-12-19 19:58:35 -05003245
Kristian Høgsberg30200732007-02-16 17:34:39 -05003246 context_append(&ctx->context, d, z, header_z);
Kristian Høgsberged568912006-12-19 19:58:35 -05003247
3248 return 0;
3249}
Stefan Richter373b2ed2007-03-04 14:45:18 +01003250
Stefan Richter872e3302010-07-29 18:19:22 +02003251static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3252 struct fw_iso_packet *packet,
3253 struct fw_iso_buffer *buffer,
3254 unsigned long payload)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003255{
Clemens Ladischa572e682011-10-15 23:12:23 +02003256 struct device *device = ctx->context.ohci->card.device;
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05003257 struct descriptor *d, *pd;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003258 dma_addr_t d_bus, page_bus;
3259 u32 z, header_z, rest;
David Moorebcee8932007-12-19 15:26:38 -05003260 int i, j, length;
3261 int page, offset, packet_count, header_size, payload_per_buffer;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003262
3263 /*
David Moore1aa292b2008-07-22 23:23:40 -07003264 * The OHCI controller puts the isochronous header and trailer in the
3265 * buffer, so we need at least 8 bytes.
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003266 */
Stefan Richter872e3302010-07-29 18:19:22 +02003267 packet_count = packet->header_length / ctx->base.header_size;
David Moore1aa292b2008-07-22 23:23:40 -07003268 header_size = max(ctx->base.header_size, (size_t)8);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003269
3270 /* Get header size in number of descriptors. */
3271 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3272 page = payload >> PAGE_SHIFT;
3273 offset = payload & ~PAGE_MASK;
Stefan Richter872e3302010-07-29 18:19:22 +02003274 payload_per_buffer = packet->payload_length / packet_count;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003275
3276 for (i = 0; i < packet_count; i++) {
3277 /* d points to the header descriptor */
David Moorebcee8932007-12-19 15:26:38 -05003278 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003279 d = context_get_descriptors(&ctx->context,
David Moorebcee8932007-12-19 15:26:38 -05003280 z + header_z, &d_bus);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003281 if (d == NULL)
3282 return -ENOMEM;
3283
David Moorebcee8932007-12-19 15:26:38 -05003284 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3285 DESCRIPTOR_INPUT_MORE);
Stefan Richter872e3302010-07-29 18:19:22 +02003286 if (packet->skip && i == 0)
David Moorebcee8932007-12-19 15:26:38 -05003287 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003288 d->req_count = cpu_to_le16(header_size);
3289 d->res_count = d->req_count;
David Moorebcee8932007-12-19 15:26:38 -05003290 d->transfer_status = 0;
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003291 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3292
David Moorebcee8932007-12-19 15:26:38 -05003293 rest = payload_per_buffer;
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05003294 pd = d;
David Moorebcee8932007-12-19 15:26:38 -05003295 for (j = 1; j < z; j++) {
Jay Fenlason8c0c0cc2009-12-11 14:23:58 -05003296 pd++;
David Moorebcee8932007-12-19 15:26:38 -05003297 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3298 DESCRIPTOR_INPUT_MORE);
3299
3300 if (offset + rest < PAGE_SIZE)
3301 length = rest;
3302 else
3303 length = PAGE_SIZE - offset;
3304 pd->req_count = cpu_to_le16(length);
3305 pd->res_count = pd->req_count;
3306 pd->transfer_status = 0;
3307
3308 page_bus = page_private(buffer->pages[page]);
3309 pd->data_address = cpu_to_le32(page_bus + offset);
3310
Clemens Ladischa572e682011-10-15 23:12:23 +02003311 dma_sync_single_range_for_device(device, page_bus,
3312 offset, length,
3313 DMA_FROM_DEVICE);
3314
David Moorebcee8932007-12-19 15:26:38 -05003315 offset = (offset + length) & ~PAGE_MASK;
3316 rest -= length;
3317 if (offset == 0)
3318 page++;
3319 }
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003320 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3321 DESCRIPTOR_INPUT_LAST |
3322 DESCRIPTOR_BRANCH_ALWAYS);
Stefan Richter872e3302010-07-29 18:19:22 +02003323 if (packet->interrupt && i == packet_count - 1)
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003324 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3325
Jarod Wilsona186b4a2007-12-03 13:43:12 -05003326 context_append(&ctx->context, d, z, header_z);
3327 }
3328
3329 return 0;
3330}
3331
Stefan Richter872e3302010-07-29 18:19:22 +02003332static int queue_iso_buffer_fill(struct iso_context *ctx,
3333 struct fw_iso_packet *packet,
3334 struct fw_iso_buffer *buffer,
3335 unsigned long payload)
3336{
3337 struct descriptor *d;
3338 dma_addr_t d_bus, page_bus;
3339 int page, offset, rest, z, i, length;
3340
3341 page = payload >> PAGE_SHIFT;
3342 offset = payload & ~PAGE_MASK;
3343 rest = packet->payload_length;
3344
3345 /* We need one descriptor for each page in the buffer. */
3346 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3347
3348 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3349 return -EFAULT;
3350
3351 for (i = 0; i < z; i++) {
3352 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3353 if (d == NULL)
3354 return -ENOMEM;
3355
3356 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3357 DESCRIPTOR_BRANCH_ALWAYS);
3358 if (packet->skip && i == 0)
3359 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3360 if (packet->interrupt && i == z - 1)
3361 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3362
3363 if (offset + rest < PAGE_SIZE)
3364 length = rest;
3365 else
3366 length = PAGE_SIZE - offset;
3367 d->req_count = cpu_to_le16(length);
3368 d->res_count = d->req_count;
3369 d->transfer_status = 0;
3370
3371 page_bus = page_private(buffer->pages[page]);
3372 d->data_address = cpu_to_le32(page_bus + offset);
3373
Clemens Ladischa572e682011-10-15 23:12:23 +02003374 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3375 page_bus, offset, length,
3376 DMA_FROM_DEVICE);
3377
Stefan Richter872e3302010-07-29 18:19:22 +02003378 rest -= length;
3379 offset = 0;
3380 page++;
3381
3382 context_append(&ctx->context, d, 1, 0);
3383 }
3384
3385 return 0;
3386}
3387
Stefan Richter53dca512008-12-14 21:47:04 +01003388static int ohci_queue_iso(struct fw_iso_context *base,
3389 struct fw_iso_packet *packet,
3390 struct fw_iso_buffer *buffer,
3391 unsigned long payload)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003392{
Kristian Høgsberge364cf42007-02-16 17:34:49 -05003393 struct iso_context *ctx = container_of(base, struct iso_context, base);
David Moorefe5ca632008-01-06 17:21:41 -05003394 unsigned long flags;
Stefan Richter872e3302010-07-29 18:19:22 +02003395 int ret = -ENOSYS;
Kristian Høgsberge364cf42007-02-16 17:34:49 -05003396
David Moorefe5ca632008-01-06 17:21:41 -05003397 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
Stefan Richter872e3302010-07-29 18:19:22 +02003398 switch (base->type) {
3399 case FW_ISO_CONTEXT_TRANSMIT:
3400 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3401 break;
3402 case FW_ISO_CONTEXT_RECEIVE:
3403 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3404 break;
3405 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3406 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3407 break;
3408 }
David Moorefe5ca632008-01-06 17:21:41 -05003409 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3410
Stefan Richter2dbd7d72008-12-14 21:45:45 +01003411 return ret;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05003412}
3413
Clemens Ladisch13882a82011-05-02 09:33:56 +02003414static void ohci_flush_queue_iso(struct fw_iso_context *base)
3415{
3416 struct context *ctx =
3417 &container_of(base, struct iso_context, base)->context;
3418
3419 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
Clemens Ladisch13882a82011-05-02 09:33:56 +02003420}
3421
Clemens Ladischd1bbd202012-03-18 19:06:39 +01003422static int ohci_flush_iso_completions(struct fw_iso_context *base)
3423{
3424 struct iso_context *ctx = container_of(base, struct iso_context, base);
3425 int ret = 0;
3426
3427 tasklet_disable(&ctx->context.tasklet);
3428
3429 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3430 context_tasklet((unsigned long)&ctx->context);
3431
3432 switch (base->type) {
3433 case FW_ISO_CONTEXT_TRANSMIT:
3434 case FW_ISO_CONTEXT_RECEIVE:
3435 if (ctx->header_length != 0)
3436 flush_iso_completions(ctx);
3437 break;
3438 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3439 if (ctx->mc_completed != 0)
3440 flush_ir_buffer_fill(ctx);
3441 break;
3442 default:
3443 ret = -ENOSYS;
3444 }
3445
3446 clear_bit_unlock(0, &ctx->flushing_completions);
3447 smp_mb__after_clear_bit();
3448 }
3449
3450 tasklet_enable(&ctx->context.tasklet);
3451
3452 return ret;
3453}
3454
Stefan Richter21ebcd12007-01-14 15:29:07 +01003455static const struct fw_card_driver ohci_driver = {
Kristian Høgsberged568912006-12-19 19:58:35 -05003456 .enable = ohci_enable,
Stefan Richter02d37be2010-07-08 16:09:06 +02003457 .read_phy_reg = ohci_read_phy_reg,
Kristian Høgsberged568912006-12-19 19:58:35 -05003458 .update_phy_reg = ohci_update_phy_reg,
3459 .set_config_rom = ohci_set_config_rom,
3460 .send_request = ohci_send_request,
3461 .send_response = ohci_send_response,
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05003462 .cancel_packet = ohci_cancel_packet,
Kristian Høgsberged568912006-12-19 19:58:35 -05003463 .enable_phys_dma = ohci_enable_phys_dma,
Stefan Richter0fcff4e2010-06-12 20:35:52 +02003464 .read_csr = ohci_read_csr,
3465 .write_csr = ohci_write_csr,
Kristian Høgsberged568912006-12-19 19:58:35 -05003466
3467 .allocate_iso_context = ohci_allocate_iso_context,
3468 .free_iso_context = ohci_free_iso_context,
Stefan Richter872e3302010-07-29 18:19:22 +02003469 .set_iso_channels = ohci_set_iso_channels,
Kristian Høgsberged568912006-12-19 19:58:35 -05003470 .queue_iso = ohci_queue_iso,
Clemens Ladisch13882a82011-05-02 09:33:56 +02003471 .flush_queue_iso = ohci_flush_queue_iso,
Clemens Ladischd1bbd202012-03-18 19:06:39 +01003472 .flush_iso_completions = ohci_flush_iso_completions,
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05003473 .start_iso = ohci_start_iso,
Kristian Høgsbergb8295662007-02-16 17:34:42 -05003474 .stop_iso = ohci_stop_iso,
Kristian Høgsberged568912006-12-19 19:58:35 -05003475};
3476
Stefan Richter2ed0f182008-03-01 12:35:29 +01003477#ifdef CONFIG_PPC_PMAC
Stefan Richter5da3dac2010-04-02 14:05:02 +02003478static void pmac_ohci_on(struct pci_dev *dev)
Stefan Richter2ed0f182008-03-01 12:35:29 +01003479{
3480 if (machine_is(powermac)) {
3481 struct device_node *ofn = pci_device_to_OF_node(dev);
3482
3483 if (ofn) {
3484 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3485 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3486 }
3487 }
3488}
3489
Stefan Richter5da3dac2010-04-02 14:05:02 +02003490static void pmac_ohci_off(struct pci_dev *dev)
Stefan Richter2ed0f182008-03-01 12:35:29 +01003491{
3492 if (machine_is(powermac)) {
3493 struct device_node *ofn = pci_device_to_OF_node(dev);
3494
3495 if (ofn) {
3496 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3497 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3498 }
3499 }
3500}
3501#else
Stefan Richter5da3dac2010-04-02 14:05:02 +02003502static inline void pmac_ohci_on(struct pci_dev *dev) {}
3503static inline void pmac_ohci_off(struct pci_dev *dev) {}
Stefan Richter2ed0f182008-03-01 12:35:29 +01003504#endif /* CONFIG_PPC_PMAC */
3505
Stefan Richter53dca512008-12-14 21:47:04 +01003506static int __devinit pci_probe(struct pci_dev *dev,
3507 const struct pci_device_id *ent)
Kristian Høgsberged568912006-12-19 19:58:35 -05003508{
3509 struct fw_ohci *ohci;
Stefan Richteraa0170f2010-10-17 14:09:12 +02003510 u32 bus_options, max_receive, link_speed, version;
Kristian Høgsberged568912006-12-19 19:58:35 -05003511 u64 guid;
Maxim Levitskydd237362010-11-29 04:09:50 +02003512 int i, err;
Kristian Høgsberged568912006-12-19 19:58:35 -05003513 size_t size;
3514
Stefan Richter7f7e37112011-07-10 00:23:03 +02003515 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3516 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3517 return -ENOSYS;
3518 }
3519
Kristian Høgsberg2d826cc2007-05-09 19:23:14 -04003520 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
Kristian Høgsberged568912006-12-19 19:58:35 -05003521 if (ohci == NULL) {
Stefan Richter7007a072008-10-26 09:50:31 +01003522 err = -ENOMEM;
3523 goto fail;
Kristian Høgsberged568912006-12-19 19:58:35 -05003524 }
3525
3526 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3527
Stefan Richter5da3dac2010-04-02 14:05:02 +02003528 pmac_ohci_on(dev);
Stefan Richter130d5492008-03-24 20:55:28 +01003529
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003530 err = pci_enable_device(dev);
3531 if (err) {
Stefan Richter64d21722011-12-20 21:32:46 +01003532 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
Stefan Richterbd7dee62008-02-24 18:59:55 +01003533 goto fail_free;
Kristian Høgsberged568912006-12-19 19:58:35 -05003534 }
3535
3536 pci_set_master(dev);
3537 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3538 pci_set_drvdata(dev, ohci);
3539
3540 spin_lock_init(&ohci->lock);
Stefan Richter02d37be2010-07-08 16:09:06 +02003541 mutex_init(&ohci->phy_reg_mutex);
Kristian Høgsberged568912006-12-19 19:58:35 -05003542
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02003543 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
Kristian Høgsberged568912006-12-19 19:58:35 -05003544
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003545 err = pci_request_region(dev, 0, ohci_driver_name);
3546 if (err) {
Stefan Richter64d21722011-12-20 21:32:46 +01003547 dev_err(&dev->dev, "MMIO resource unavailable\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003548 goto fail_disable;
Kristian Høgsberged568912006-12-19 19:58:35 -05003549 }
3550
3551 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3552 if (ohci->registers == NULL) {
Stefan Richter64d21722011-12-20 21:32:46 +01003553 dev_err(&dev->dev, "failed to remap registers\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003554 err = -ENXIO;
3555 goto fail_iomem;
Kristian Høgsberged568912006-12-19 19:58:35 -05003556 }
3557
Stefan Richter4a635592010-02-21 17:58:01 +01003558 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
Stefan Richter9993e0f2010-12-07 20:32:40 +01003559 if ((ohci_quirks[i].vendor == dev->vendor) &&
3560 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3561 ohci_quirks[i].device == dev->device) &&
3562 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3563 ohci_quirks[i].revision >= dev->revision)) {
Stefan Richter4a635592010-02-21 17:58:01 +01003564 ohci->quirks = ohci_quirks[i].flags;
3565 break;
3566 }
Stefan Richter3e9cc2f2010-02-21 17:58:29 +01003567 if (param_quirks)
3568 ohci->quirks = param_quirks;
Clemens Ladischb6775322010-01-20 09:58:02 +01003569
Clemens Ladischec766a72010-11-30 08:25:17 +01003570 /*
3571 * Because dma_alloc_coherent() allocates at least one page,
3572 * we save space by using a common buffer for the AR request/
3573 * response descriptors and the self IDs buffer.
3574 */
3575 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3576 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3577 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3578 PAGE_SIZE,
3579 &ohci->misc_buffer_bus,
3580 GFP_KERNEL);
3581 if (!ohci->misc_buffer) {
3582 err = -ENOMEM;
3583 goto fail_iounmap;
3584 }
3585
3586 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01003587 OHCI1394_AsReqRcvContextControlSet);
3588 if (err < 0)
Clemens Ladischec766a72010-11-30 08:25:17 +01003589 goto fail_misc_buf;
Kristian Høgsberged568912006-12-19 19:58:35 -05003590
Clemens Ladischec766a72010-11-30 08:25:17 +01003591 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01003592 OHCI1394_AsRspRcvContextControlSet);
3593 if (err < 0)
3594 goto fail_arreq_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -05003595
Clemens Ladischc088ab302010-11-30 08:24:01 +01003596 err = context_init(&ohci->at_request_ctx, ohci,
3597 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3598 if (err < 0)
3599 goto fail_arrsp_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -05003600
Clemens Ladischc088ab302010-11-30 08:24:01 +01003601 err = context_init(&ohci->at_response_ctx, ohci,
3602 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3603 if (err < 0)
3604 goto fail_atreq_ctx;
Kristian Høgsberged568912006-12-19 19:58:35 -05003605
Kristian Høgsberged568912006-12-19 19:58:35 -05003606 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
Stefan Richter4817ed22008-12-21 16:39:46 +01003607 ohci->ir_context_channels = ~0ULL;
Clemens Ladischf117a3e2011-01-10 17:21:35 +01003608 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
Stefan Richter4802f162010-02-21 17:58:52 +01003609 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
Clemens Ladischf117a3e2011-01-10 17:21:35 +01003610 ohci->ir_context_mask = ohci->ir_context_support;
Maxim Levitskydd237362010-11-29 04:09:50 +02003611 ohci->n_ir = hweight32(ohci->ir_context_mask);
3612 size = sizeof(struct iso_context) * ohci->n_ir;
Kristian Høgsberged568912006-12-19 19:58:35 -05003613 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3614
Stefan Richter4802f162010-02-21 17:58:52 +01003615 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
Clemens Ladischf117a3e2011-01-10 17:21:35 +01003616 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
Stefan Richter4802f162010-02-21 17:58:52 +01003617 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
Clemens Ladischf117a3e2011-01-10 17:21:35 +01003618 ohci->it_context_mask = ohci->it_context_support;
Maxim Levitskydd237362010-11-29 04:09:50 +02003619 ohci->n_it = hweight32(ohci->it_context_mask);
3620 size = sizeof(struct iso_context) * ohci->n_it;
Stefan Richter4802f162010-02-21 17:58:52 +01003621 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3622
Kristian Høgsberged568912006-12-19 19:58:35 -05003623 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003624 err = -ENOMEM;
Stefan Richter7007a072008-10-26 09:50:31 +01003625 goto fail_contexts;
Kristian Høgsberged568912006-12-19 19:58:35 -05003626 }
3627
Clemens Ladischec766a72010-11-30 08:25:17 +01003628 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3629 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
Kristian Høgsberged568912006-12-19 19:58:35 -05003630
Kristian Høgsberged568912006-12-19 19:58:35 -05003631 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3632 max_receive = (bus_options >> 12) & 0xf;
3633 link_speed = bus_options & 0x7;
3634 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3635 reg_read(ohci, OHCI1394_GUIDLo);
3636
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003637 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
Stefan Richtere1eff7a2009-02-03 17:55:19 +01003638 if (err)
Clemens Ladischec766a72010-11-30 08:25:17 +01003639 goto fail_contexts;
Kristian Høgsberged568912006-12-19 19:58:35 -05003640
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01003641 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
Stefan Richter64d21722011-12-20 21:32:46 +01003642 dev_notice(&dev->dev,
3643 "added OHCI v%x.%x device as card %d, "
Stefan Richter6fdb2ee2010-02-21 17:59:14 +01003644 "%d IR + %d IT contexts, quirks 0x%x\n",
Stefan Richter64d21722011-12-20 21:32:46 +01003645 version >> 16, version & 0xff, ohci->card.index,
Maxim Levitskydd237362010-11-29 04:09:50 +02003646 ohci->n_ir, ohci->n_it, ohci->quirks);
Stefan Richtere1eff7a2009-02-03 17:55:19 +01003647
Kristian Høgsberged568912006-12-19 19:58:35 -05003648 return 0;
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003649
Stefan Richter7007a072008-10-26 09:50:31 +01003650 fail_contexts:
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003651 kfree(ohci->ir_context_list);
Stefan Richter7007a072008-10-26 09:50:31 +01003652 kfree(ohci->it_context_list);
3653 context_release(&ohci->at_response_ctx);
Clemens Ladischc088ab302010-11-30 08:24:01 +01003654 fail_atreq_ctx:
Stefan Richter7007a072008-10-26 09:50:31 +01003655 context_release(&ohci->at_request_ctx);
Clemens Ladischc088ab302010-11-30 08:24:01 +01003656 fail_arrsp_ctx:
Stefan Richter7007a072008-10-26 09:50:31 +01003657 ar_context_release(&ohci->ar_response_ctx);
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01003658 fail_arreq_ctx:
Stefan Richter7007a072008-10-26 09:50:31 +01003659 ar_context_release(&ohci->ar_request_ctx);
Clemens Ladischec766a72010-11-30 08:25:17 +01003660 fail_misc_buf:
3661 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3662 ohci->misc_buffer, ohci->misc_buffer_bus);
Clemens Ladisch7a39d8b2010-11-26 08:57:31 +01003663 fail_iounmap:
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003664 pci_iounmap(dev, ohci->registers);
3665 fail_iomem:
3666 pci_release_region(dev, 0);
3667 fail_disable:
3668 pci_disable_device(dev);
Stefan Richterbd7dee62008-02-24 18:59:55 +01003669 fail_free:
Oleg Drokind838d2c02011-03-11 04:17:27 +03003670 kfree(ohci);
Stefan Richter5da3dac2010-04-02 14:05:02 +02003671 pmac_ohci_off(dev);
Stefan Richter7007a072008-10-26 09:50:31 +01003672 fail:
3673 if (err == -ENOMEM)
Stefan Richter64d21722011-12-20 21:32:46 +01003674 dev_err(&dev->dev, "out of memory\n");
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003675
3676 return err;
Kristian Høgsberged568912006-12-19 19:58:35 -05003677}
3678
3679static void pci_remove(struct pci_dev *dev)
3680{
3681 struct fw_ohci *ohci;
3682
3683 ohci = pci_get_drvdata(dev);
Kristian Høgsberge254a4b2007-03-07 12:12:38 -05003684 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3685 flush_writes(ohci);
Stephan Gatzka2d7a36e2011-07-25 22:16:24 +02003686 cancel_work_sync(&ohci->bus_reset_work);
Kristian Høgsberged568912006-12-19 19:58:35 -05003687 fw_core_remove_card(&ohci->card);
3688
Kristian Høgsbergc781c062007-05-07 20:33:32 -04003689 /*
3690 * FIXME: Fail all pending packets here, now that the upper
3691 * layers can't queue any more.
3692 */
Kristian Høgsberged568912006-12-19 19:58:35 -05003693
3694 software_reset(ohci);
3695 free_irq(dev->irq, ohci);
Jay Fenlasona55709b2008-10-22 15:59:42 -04003696
3697 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3698 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3699 ohci->next_config_rom, ohci->next_config_rom_bus);
3700 if (ohci->config_rom)
3701 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3702 ohci->config_rom, ohci->config_rom_bus);
Jay Fenlasona55709b2008-10-22 15:59:42 -04003703 ar_context_release(&ohci->ar_request_ctx);
3704 ar_context_release(&ohci->ar_response_ctx);
Clemens Ladischec766a72010-11-30 08:25:17 +01003705 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3706 ohci->misc_buffer, ohci->misc_buffer_bus);
Jay Fenlasona55709b2008-10-22 15:59:42 -04003707 context_release(&ohci->at_request_ctx);
3708 context_release(&ohci->at_response_ctx);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003709 kfree(ohci->it_context_list);
3710 kfree(ohci->ir_context_list);
Clemens Ladisch262444e2010-06-05 12:31:25 +02003711 pci_disable_msi(dev);
Kristian Høgsbergd79406d2007-05-09 19:23:15 -04003712 pci_iounmap(dev, ohci->registers);
3713 pci_release_region(dev, 0);
3714 pci_disable_device(dev);
Oleg Drokind838d2c02011-03-11 04:17:27 +03003715 kfree(ohci);
Stefan Richter5da3dac2010-04-02 14:05:02 +02003716 pmac_ohci_off(dev);
Stefan Richterea8d0062008-03-01 02:42:56 +01003717
Stefan Richter64d21722011-12-20 21:32:46 +01003718 dev_notice(&dev->dev, "removed fw-ohci device\n");
Kristian Høgsberged568912006-12-19 19:58:35 -05003719}
3720
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003721#ifdef CONFIG_PM
Stefan Richter2ed0f182008-03-01 12:35:29 +01003722static int pci_suspend(struct pci_dev *dev, pm_message_t state)
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003723{
Stefan Richter2ed0f182008-03-01 12:35:29 +01003724 struct fw_ohci *ohci = pci_get_drvdata(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003725 int err;
3726
3727 software_reset(ohci);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003728 free_irq(dev->irq, ohci);
Clemens Ladisch262444e2010-06-05 12:31:25 +02003729 pci_disable_msi(dev);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003730 err = pci_save_state(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003731 if (err) {
Stefan Richter64d21722011-12-20 21:32:46 +01003732 dev_err(&dev->dev, "pci_save_state failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003733 return err;
3734 }
Stefan Richter2ed0f182008-03-01 12:35:29 +01003735 err = pci_set_power_state(dev, pci_choose_state(dev, state));
Stefan Richter55111422007-09-06 09:50:30 +02003736 if (err)
Stefan Richter64d21722011-12-20 21:32:46 +01003737 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
Stefan Richter5da3dac2010-04-02 14:05:02 +02003738 pmac_ohci_off(dev);
Stefan Richterea8d0062008-03-01 02:42:56 +01003739
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003740 return 0;
3741}
3742
Stefan Richter2ed0f182008-03-01 12:35:29 +01003743static int pci_resume(struct pci_dev *dev)
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003744{
Stefan Richter2ed0f182008-03-01 12:35:29 +01003745 struct fw_ohci *ohci = pci_get_drvdata(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003746 int err;
3747
Stefan Richter5da3dac2010-04-02 14:05:02 +02003748 pmac_ohci_on(dev);
Stefan Richter2ed0f182008-03-01 12:35:29 +01003749 pci_set_power_state(dev, PCI_D0);
3750 pci_restore_state(dev);
3751 err = pci_enable_device(dev);
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003752 if (err) {
Stefan Richter64d21722011-12-20 21:32:46 +01003753 dev_err(&dev->dev, "pci_enable_device failed\n");
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003754 return err;
3755 }
3756
Maxim Levitsky8662b6b2010-11-29 04:09:49 +02003757 /* Some systems don't setup GUID register on resume from ram */
3758 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3759 !reg_read(ohci, OHCI1394_GUIDHi)) {
3760 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3761 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3762 }
3763
Maxim Levitskydd237362010-11-29 04:09:50 +02003764 err = ohci_enable(&ohci->card, NULL, 0);
Maxim Levitskydd237362010-11-29 04:09:50 +02003765 if (err)
3766 return err;
3767
3768 ohci_resume_iso_dma(ohci);
Stefan Richter693a50b2011-01-01 15:17:05 +01003769
Maxim Levitskydd237362010-11-29 04:09:50 +02003770 return 0;
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003771}
3772#endif
3773
Németh Mártona67483d2010-01-10 13:14:26 +01003774static const struct pci_device_id pci_table[] = {
Kristian Høgsberged568912006-12-19 19:58:35 -05003775 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3776 { }
3777};
3778
3779MODULE_DEVICE_TABLE(pci, pci_table);
3780
3781static struct pci_driver fw_ohci_pci_driver = {
3782 .name = ohci_driver_name,
3783 .id_table = pci_table,
3784 .probe = pci_probe,
3785 .remove = pci_remove,
Kristian Høgsberg2aef4692007-05-30 19:06:35 -04003786#ifdef CONFIG_PM
3787 .resume = pci_resume,
3788 .suspend = pci_suspend,
3789#endif
Kristian Høgsberged568912006-12-19 19:58:35 -05003790};
3791
3792MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3793MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3794MODULE_LICENSE("GPL");
3795
Olaf Hering1e4c7b02007-05-05 23:17:13 +02003796/* Provide a module alias so root-on-sbp2 initrds don't break. */
3797#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3798MODULE_ALIAS("ohci1394");
3799#endif
3800
Kristian Høgsberged568912006-12-19 19:58:35 -05003801static int __init fw_ohci_init(void)
3802{
3803 return pci_register_driver(&fw_ohci_pci_driver);
3804}
3805
3806static void __exit fw_ohci_cleanup(void)
3807{
3808 pci_unregister_driver(&fw_ohci_pci_driver);
3809}
3810
3811module_init(fw_ohci_init);
3812module_exit(fw_ohci_cleanup);