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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050045#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090049#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51
52enum {
53 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090054 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020057 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090058 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090059 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090060 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090063 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090071 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090072 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090076 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090077 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +090080 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82 board_ahci_sb600 = 3,
83 board_ahci_mv = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -070084
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +090098 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +090099 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
Tejun Heo78cd52d2006-05-15 20:58:29 +0900143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900146 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900147 PORT_IRQ_UNK_FIS |
148 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
150 PORT_IRQ_TF_ERR |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155
156 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900162 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
166
Tejun Heo0be0aa92006-07-26 15:59:26 +0900167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400171
Tejun Heo417a1a62007-09-23 13:19:55 +0900172 /* hpriv->flags bits */
173 AHCI_HFLAG_NO_NCQ = (1 << 0),
174 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
175 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
176 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
177 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
178 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900179 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Tejun Heo417a1a62007-09-23 13:19:55 +0900180
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200181 /* ap->flags bits */
Tejun Heo417a1a62007-09-23 13:19:55 +0900182 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900183
184 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
185 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Tejun Heo854c73a2007-09-23 13:14:11 +0900186 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
Tejun Heo0c887582007-08-06 18:36:23 +0900187 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188};
189
190struct ahci_cmd_hdr {
191 u32 opts;
192 u32 status;
193 u32 tbl_addr;
194 u32 tbl_addr_hi;
195 u32 reserved[4];
196};
197
198struct ahci_sg {
199 u32 addr;
200 u32 addr_hi;
201 u32 reserved;
202 u32 flags_size;
203};
204
205struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900206 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900207 u32 cap; /* cap to use */
208 u32 port_map; /* port map to use */
209 u32 saved_cap; /* saved initial cap */
210 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211};
212
213struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900214 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 struct ahci_cmd_hdr *cmd_slot;
216 dma_addr_t cmd_slot_dma;
217 void *cmd_tbl;
218 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 void *rx_fis;
220 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900221 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900222 unsigned int ncq_saw_d2h:1;
223 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900224 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700225 u32 intr_mask; /* interrupts to enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226};
227
Tejun Heoda3dbb12007-07-16 14:29:40 +0900228static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
229static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900231static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233static int ahci_port_start(struct ata_port *ap);
234static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
236static void ahci_qc_prep(struct ata_queued_cmd *qc);
237static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900238static void ahci_freeze(struct ata_port *ap);
239static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900240static void ahci_pmp_attach(struct ata_port *ap);
241static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900242static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900243static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900244static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400245static int ahci_port_resume(struct ata_port *ap);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400246static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
247static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
248 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900249#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900250static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900251static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
252static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900253#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
Jeff Garzik193515d2005-11-07 00:59:37 -0500255static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 .module = THIS_MODULE,
257 .name = DRV_NAME,
258 .ioctl = ata_scsi_ioctl,
259 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900260 .change_queue_depth = ata_scsi_change_queue_depth,
261 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 .this_id = ATA_SHT_THIS_ID,
263 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
265 .emulated = ATA_SHT_EMULATED,
266 .use_clustering = AHCI_USE_CLUSTERING,
267 .proc_name = DRV_NAME,
268 .dma_boundary = AHCI_DMA_BOUNDARY,
269 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900270 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272};
273
Jeff Garzik057ace52005-10-22 14:27:05 -0400274static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 .check_status = ahci_check_status,
276 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 .dev_select = ata_noop_dev_select,
278
279 .tf_read = ahci_tf_read,
280
Tejun Heo7d50b602007-09-23 13:19:54 +0900281 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 .qc_prep = ahci_qc_prep,
283 .qc_issue = ahci_qc_issue,
284
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 .irq_clear = ahci_irq_clear,
286
287 .scr_read = ahci_scr_read,
288 .scr_write = ahci_scr_write,
289
Tejun Heo78cd52d2006-05-15 20:58:29 +0900290 .freeze = ahci_freeze,
291 .thaw = ahci_thaw,
292
293 .error_handler = ahci_error_handler,
294 .post_internal_cmd = ahci_post_internal_cmd,
295
Tejun Heo7d50b602007-09-23 13:19:54 +0900296 .pmp_attach = ahci_pmp_attach,
297 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900298
Tejun Heo438ac6d2007-03-02 17:31:26 +0900299#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900300 .port_suspend = ahci_port_suspend,
301 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900302#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900303
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 .port_start = ahci_port_start,
305 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306};
307
Tejun Heoad616ff2006-11-01 18:00:24 +0900308static const struct ata_port_operations ahci_vt8251_ops = {
Tejun Heoad616ff2006-11-01 18:00:24 +0900309 .check_status = ahci_check_status,
310 .check_altstatus = ahci_check_status,
311 .dev_select = ata_noop_dev_select,
312
313 .tf_read = ahci_tf_read,
314
Tejun Heo7d50b602007-09-23 13:19:54 +0900315 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Tejun Heoad616ff2006-11-01 18:00:24 +0900316 .qc_prep = ahci_qc_prep,
317 .qc_issue = ahci_qc_issue,
318
Tejun Heoad616ff2006-11-01 18:00:24 +0900319 .irq_clear = ahci_irq_clear,
320
321 .scr_read = ahci_scr_read,
322 .scr_write = ahci_scr_write,
323
324 .freeze = ahci_freeze,
325 .thaw = ahci_thaw,
326
327 .error_handler = ahci_vt8251_error_handler,
328 .post_internal_cmd = ahci_post_internal_cmd,
329
Tejun Heo7d50b602007-09-23 13:19:54 +0900330 .pmp_attach = ahci_pmp_attach,
331 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900332
Tejun Heo438ac6d2007-03-02 17:31:26 +0900333#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900334 .port_suspend = ahci_port_suspend,
335 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900336#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900337
338 .port_start = ahci_port_start,
339 .port_stop = ahci_port_stop,
340};
341
Tejun Heo417a1a62007-09-23 13:19:55 +0900342#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
343
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100344static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 /* board_ahci */
346 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900347 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900348 .link_flags = AHCI_LFLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400349 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400350 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 .port_ops = &ahci_ops,
352 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200353 /* board_ahci_vt8251 */
354 {
Tejun Heo6949b912007-09-23 13:19:55 +0900355 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900356 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900357 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200358 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400359 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900360 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200361 },
Tejun Heo41669552006-11-29 11:33:14 +0900362 /* board_ahci_ign_iferr */
363 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900364 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
365 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900366 .link_flags = AHCI_LFLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900367 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400368 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900369 .port_ops = &ahci_ops,
370 },
Conke Hu55a61602007-03-27 18:33:05 +0800371 /* board_ahci_sb600 */
372 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900373 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo6949b912007-09-23 13:19:55 +0900374 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900375 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900376 .link_flags = AHCI_LFLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800377 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400378 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800379 .port_ops = &ahci_ops,
380 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400381 /* board_ahci_mv */
382 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900383 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
384 AHCI_HFLAG_MV_PATA),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400385 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900386 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Tejun Heo0c887582007-08-06 18:36:23 +0900387 .link_flags = AHCI_LFLAG_COMMON,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400388 .pio_mask = 0x1f, /* pio0-4 */
389 .udma_mask = ATA_UDMA6,
390 .port_ops = &ahci_ops,
391 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392};
393
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500394static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400395 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400396 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
397 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
398 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
399 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
400 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900401 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400402 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
403 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
404 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
405 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900406 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
407 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
408 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
409 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
410 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
411 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
414 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
415 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
416 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
417 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
419 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
421 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
422 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400423 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
424 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400425
Tejun Heoe34bb372007-02-26 20:24:03 +0900426 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
427 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
428 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400429
430 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800431 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
henry suc69c0892007-09-20 16:07:33 -0400432 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
437 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400438
439 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400440 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900441 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400442
443 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400444 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500448 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500456 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800464 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
Peer Chen71008192007-09-24 10:16:25 +0800488 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400496
Jeff Garzik95916ed2006-07-29 04:10:14 -0400497 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400498 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
499 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
500 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400501
Jeff Garzikcd70c262007-07-08 02:29:42 -0400502 /* Marvell */
503 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
504
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500505 /* Generic, PCI class code for AHCI */
506 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500507 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500508
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 { } /* terminate list */
510};
511
512
513static struct pci_driver ahci_pci_driver = {
514 .name = DRV_NAME,
515 .id_table = ahci_pci_tbl,
516 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900517 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900518#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900519 .suspend = ahci_pci_device_suspend,
520 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900521#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522};
523
524
Tejun Heo98fa4b62006-11-02 12:17:23 +0900525static inline int ahci_nr_ports(u32 cap)
526{
527 return (cap & 0x1f) + 1;
528}
529
Jeff Garzikdab632e2007-05-28 08:33:01 -0400530static inline void __iomem *__ahci_port_base(struct ata_host *host,
531 unsigned int port_no)
532{
533 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
534
535 return mmio + 0x100 + (port_no * 0x80);
536}
537
Tejun Heo4447d352007-04-17 23:44:08 +0900538static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400540 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541}
542
Tejun Heod447df12007-03-18 22:15:33 +0900543/**
544 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900545 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900546 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900547 *
548 * Some registers containing configuration info might be setup by
549 * BIOS and might be cleared on reset. This function saves the
550 * initial values of those registers into @hpriv such that they
551 * can be restored after controller reset.
552 *
553 * If inconsistent, config values are fixed up by this function.
554 *
555 * LOCKING:
556 * None.
557 */
Tejun Heo4447d352007-04-17 23:44:08 +0900558static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900559 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900560{
Tejun Heo4447d352007-04-17 23:44:08 +0900561 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900562 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900563 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900564
565 /* Values prefixed with saved_ are written back to host after
566 * reset. Values without are used for driver operation.
567 */
568 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
569 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
570
Tejun Heo274c1fd2007-07-16 14:29:40 +0900571 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900572 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200573 dev_printk(KERN_INFO, &pdev->dev,
574 "controller can't do 64bit DMA, forcing 32bit\n");
575 cap &= ~HOST_CAP_64;
576 }
577
Tejun Heo417a1a62007-09-23 13:19:55 +0900578 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900579 dev_printk(KERN_INFO, &pdev->dev,
580 "controller can't do NCQ, turning off CAP_NCQ\n");
581 cap &= ~HOST_CAP_NCQ;
582 }
583
Tejun Heo6949b912007-09-23 13:19:55 +0900584 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
585 dev_printk(KERN_INFO, &pdev->dev,
586 "controller can't do PMP, turning off CAP_PMP\n");
587 cap &= ~HOST_CAP_PMP;
588 }
589
Jeff Garzikcd70c262007-07-08 02:29:42 -0400590 /*
591 * Temporary Marvell 6145 hack: PATA port presence
592 * is asserted through the standard AHCI port
593 * presence register, as bit 4 (counting from 0)
594 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900595 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400596 dev_printk(KERN_ERR, &pdev->dev,
597 "MV_AHCI HACK: port_map %x -> %x\n",
598 hpriv->port_map,
599 hpriv->port_map & 0xf);
600
601 port_map &= 0xf;
602 }
603
Tejun Heo17199b12007-03-18 22:26:53 +0900604 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900605 if (port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900606 u32 tmp_port_map = port_map;
607 int n_ports = ahci_nr_ports(cap);
608
609 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
610 if (tmp_port_map & (1 << i)) {
611 n_ports--;
612 tmp_port_map &= ~(1 << i);
613 }
614 }
615
Tejun Heo7a234af2007-09-03 12:44:57 +0900616 /* If n_ports and port_map are inconsistent, whine and
617 * clear port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900618 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900619 if (n_ports || tmp_port_map) {
Tejun Heo4447d352007-04-17 23:44:08 +0900620 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo17199b12007-03-18 22:26:53 +0900621 "nr_ports (%u) and implemented port map "
Tejun Heo7a234af2007-09-03 12:44:57 +0900622 "(0x%x) don't match, using nr_ports\n",
Tejun Heo17199b12007-03-18 22:26:53 +0900623 ahci_nr_ports(cap), port_map);
Tejun Heo7a234af2007-09-03 12:44:57 +0900624 port_map = 0;
625 }
626 }
627
628 /* fabricate port_map from cap.nr_ports */
629 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900630 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900631 dev_printk(KERN_WARNING, &pdev->dev,
632 "forcing PORTS_IMPL to 0x%x\n", port_map);
633
634 /* write the fixed up value to the PI register */
635 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900636 }
637
Tejun Heod447df12007-03-18 22:15:33 +0900638 /* record values to use during operation */
639 hpriv->cap = cap;
640 hpriv->port_map = port_map;
641}
642
643/**
644 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900645 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900646 *
647 * Restore initial config stored by ahci_save_initial_config().
648 *
649 * LOCKING:
650 * None.
651 */
Tejun Heo4447d352007-04-17 23:44:08 +0900652static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900653{
Tejun Heo4447d352007-04-17 23:44:08 +0900654 struct ahci_host_priv *hpriv = host->private_data;
655 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
656
Tejun Heod447df12007-03-18 22:15:33 +0900657 writel(hpriv->saved_cap, mmio + HOST_CAP);
658 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
659 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
660}
661
Tejun Heo203ef6c2007-07-16 14:29:40 +0900662static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900664 static const int offset[] = {
665 [SCR_STATUS] = PORT_SCR_STAT,
666 [SCR_CONTROL] = PORT_SCR_CTL,
667 [SCR_ERROR] = PORT_SCR_ERR,
668 [SCR_ACTIVE] = PORT_SCR_ACT,
669 [SCR_NOTIFICATION] = PORT_SCR_NTF,
670 };
671 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672
Tejun Heo203ef6c2007-07-16 14:29:40 +0900673 if (sc_reg < ARRAY_SIZE(offset) &&
674 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
675 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900676 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677}
678
Tejun Heo203ef6c2007-07-16 14:29:40 +0900679static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900681 void __iomem *port_mmio = ahci_port_base(ap);
682 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683
Tejun Heo203ef6c2007-07-16 14:29:40 +0900684 if (offset) {
685 *val = readl(port_mmio + offset);
686 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900688 return -EINVAL;
689}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690
Tejun Heo203ef6c2007-07-16 14:29:40 +0900691static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
692{
693 void __iomem *port_mmio = ahci_port_base(ap);
694 int offset = ahci_scr_offset(ap, sc_reg);
695
696 if (offset) {
697 writel(val, port_mmio + offset);
698 return 0;
699 }
700 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701}
702
Tejun Heo4447d352007-04-17 23:44:08 +0900703static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900704{
Tejun Heo4447d352007-04-17 23:44:08 +0900705 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900706 u32 tmp;
707
Tejun Heod8fcd112006-07-26 15:59:25 +0900708 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900709 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900710 tmp |= PORT_CMD_START;
711 writel(tmp, port_mmio + PORT_CMD);
712 readl(port_mmio + PORT_CMD); /* flush */
713}
714
Tejun Heo4447d352007-04-17 23:44:08 +0900715static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900716{
Tejun Heo4447d352007-04-17 23:44:08 +0900717 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900718 u32 tmp;
719
720 tmp = readl(port_mmio + PORT_CMD);
721
Tejun Heod8fcd112006-07-26 15:59:25 +0900722 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900723 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
724 return 0;
725
Tejun Heod8fcd112006-07-26 15:59:25 +0900726 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900727 tmp &= ~PORT_CMD_START;
728 writel(tmp, port_mmio + PORT_CMD);
729
Tejun Heod8fcd112006-07-26 15:59:25 +0900730 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900731 tmp = ata_wait_register(port_mmio + PORT_CMD,
732 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900733 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900734 return -EIO;
735
736 return 0;
737}
738
Tejun Heo4447d352007-04-17 23:44:08 +0900739static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900740{
Tejun Heo4447d352007-04-17 23:44:08 +0900741 void __iomem *port_mmio = ahci_port_base(ap);
742 struct ahci_host_priv *hpriv = ap->host->private_data;
743 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900744 u32 tmp;
745
746 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900747 if (hpriv->cap & HOST_CAP_64)
748 writel((pp->cmd_slot_dma >> 16) >> 16,
749 port_mmio + PORT_LST_ADDR_HI);
750 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900751
Tejun Heo4447d352007-04-17 23:44:08 +0900752 if (hpriv->cap & HOST_CAP_64)
753 writel((pp->rx_fis_dma >> 16) >> 16,
754 port_mmio + PORT_FIS_ADDR_HI);
755 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900756
757 /* enable FIS reception */
758 tmp = readl(port_mmio + PORT_CMD);
759 tmp |= PORT_CMD_FIS_RX;
760 writel(tmp, port_mmio + PORT_CMD);
761
762 /* flush */
763 readl(port_mmio + PORT_CMD);
764}
765
Tejun Heo4447d352007-04-17 23:44:08 +0900766static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900767{
Tejun Heo4447d352007-04-17 23:44:08 +0900768 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900769 u32 tmp;
770
771 /* disable FIS reception */
772 tmp = readl(port_mmio + PORT_CMD);
773 tmp &= ~PORT_CMD_FIS_RX;
774 writel(tmp, port_mmio + PORT_CMD);
775
776 /* wait for completion, spec says 500ms, give it 1000 */
777 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
778 PORT_CMD_FIS_ON, 10, 1000);
779 if (tmp & PORT_CMD_FIS_ON)
780 return -EBUSY;
781
782 return 0;
783}
784
Tejun Heo4447d352007-04-17 23:44:08 +0900785static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900786{
Tejun Heo4447d352007-04-17 23:44:08 +0900787 struct ahci_host_priv *hpriv = ap->host->private_data;
788 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900789 u32 cmd;
790
791 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
792
793 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900794 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900795 cmd |= PORT_CMD_SPIN_UP;
796 writel(cmd, port_mmio + PORT_CMD);
797 }
798
799 /* wake up link */
800 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
801}
802
Tejun Heo438ac6d2007-03-02 17:31:26 +0900803#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +0900804static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900805{
Tejun Heo4447d352007-04-17 23:44:08 +0900806 struct ahci_host_priv *hpriv = ap->host->private_data;
807 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900808 u32 cmd, scontrol;
809
Tejun Heo4447d352007-04-17 23:44:08 +0900810 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +0900811 return;
812
813 /* put device into listen mode, first set PxSCTL.DET to 0 */
814 scontrol = readl(port_mmio + PORT_SCR_CTL);
815 scontrol &= ~0xf;
816 writel(scontrol, port_mmio + PORT_SCR_CTL);
817
818 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900819 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +0900820 cmd &= ~PORT_CMD_SPIN_UP;
821 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900822}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900823#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +0900824
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400825static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900826{
Tejun Heo0be0aa92006-07-26 15:59:26 +0900827 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900828 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900829
830 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900831 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900832}
833
Tejun Heo4447d352007-04-17 23:44:08 +0900834static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900835{
836 int rc;
837
838 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900839 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900840 if (rc) {
841 *emsg = "failed to stop engine";
842 return rc;
843 }
844
845 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900846 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900847 if (rc) {
848 *emsg = "failed stop FIS RX";
849 return rc;
850 }
851
Tejun Heo0be0aa92006-07-26 15:59:26 +0900852 return 0;
853}
854
Tejun Heo4447d352007-04-17 23:44:08 +0900855static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900856{
Tejun Heo4447d352007-04-17 23:44:08 +0900857 struct pci_dev *pdev = to_pci_dev(host->dev);
858 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900859 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +0900860
Jeff Garzik3cc3eb12007-09-26 00:02:41 -0400861 /* we must be in AHCI mode, before using anything
862 * AHCI-specific, such as HOST_RESET.
863 */
Tejun Heod91542c2006-07-26 15:59:26 +0900864 tmp = readl(mmio + HOST_CTL);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -0400865 if (!(tmp & HOST_AHCI_EN))
866 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
867
868 /* global controller reset */
Tejun Heod91542c2006-07-26 15:59:26 +0900869 if ((tmp & HOST_RESET) == 0) {
870 writel(tmp | HOST_RESET, mmio + HOST_CTL);
871 readl(mmio + HOST_CTL); /* flush */
872 }
873
874 /* reset must complete within 1 second, or
875 * the hardware should be considered fried.
876 */
877 ssleep(1);
878
879 tmp = readl(mmio + HOST_CTL);
880 if (tmp & HOST_RESET) {
Tejun Heo4447d352007-04-17 23:44:08 +0900881 dev_printk(KERN_ERR, host->dev,
Tejun Heod91542c2006-07-26 15:59:26 +0900882 "controller reset failed (0x%x)\n", tmp);
883 return -EIO;
884 }
885
Tejun Heo98fa4b62006-11-02 12:17:23 +0900886 /* turn on AHCI mode */
Tejun Heod91542c2006-07-26 15:59:26 +0900887 writel(HOST_AHCI_EN, mmio + HOST_CTL);
888 (void) readl(mmio + HOST_CTL); /* flush */
Tejun Heo98fa4b62006-11-02 12:17:23 +0900889
Tejun Heod447df12007-03-18 22:15:33 +0900890 /* some registers might be cleared on reset. restore initial values */
Tejun Heo4447d352007-04-17 23:44:08 +0900891 ahci_restore_initial_config(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900892
893 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
894 u16 tmp16;
895
896 /* configure PCS */
897 pci_read_config_word(pdev, 0x92, &tmp16);
898 tmp16 |= 0xf;
899 pci_write_config_word(pdev, 0x92, tmp16);
900 }
901
902 return 0;
903}
904
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400905static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
906 int port_no, void __iomem *mmio,
907 void __iomem *port_mmio)
908{
909 const char *emsg = NULL;
910 int rc;
911 u32 tmp;
912
913 /* make sure port is not active */
914 rc = ahci_deinit_port(ap, &emsg);
915 if (rc)
916 dev_printk(KERN_WARNING, &pdev->dev,
917 "%s (%d)\n", emsg, rc);
918
919 /* clear SError */
920 tmp = readl(port_mmio + PORT_SCR_ERR);
921 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
922 writel(tmp, port_mmio + PORT_SCR_ERR);
923
924 /* clear port IRQ */
925 tmp = readl(port_mmio + PORT_IRQ_STAT);
926 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
927 if (tmp)
928 writel(tmp, port_mmio + PORT_IRQ_STAT);
929
930 writel(1 << port_no, mmio + HOST_IRQ_STAT);
931}
932
Tejun Heo4447d352007-04-17 23:44:08 +0900933static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900934{
Tejun Heo417a1a62007-09-23 13:19:55 +0900935 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +0900936 struct pci_dev *pdev = to_pci_dev(host->dev);
937 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400938 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400939 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +0900940 u32 tmp;
941
Tejun Heo417a1a62007-09-23 13:19:55 +0900942 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400943 port_mmio = __ahci_port_base(host, 4);
944
945 writel(0, port_mmio + PORT_IRQ_MASK);
946
947 /* clear port IRQ */
948 tmp = readl(port_mmio + PORT_IRQ_STAT);
949 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
950 if (tmp)
951 writel(tmp, port_mmio + PORT_IRQ_STAT);
952 }
953
Tejun Heo4447d352007-04-17 23:44:08 +0900954 for (i = 0; i < host->n_ports; i++) {
955 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +0900956
Jeff Garzikcd70c262007-07-08 02:29:42 -0400957 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +0900958 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +0900959 continue;
Tejun Heod91542c2006-07-26 15:59:26 +0900960
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400961 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +0900962 }
963
964 tmp = readl(mmio + HOST_CTL);
965 VPRINTK("HOST_CTL 0x%x\n", tmp);
966 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
967 tmp = readl(mmio + HOST_CTL);
968 VPRINTK("HOST_CTL 0x%x\n", tmp);
969}
970
Tejun Heo422b7592005-12-19 22:37:17 +0900971static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972{
Tejun Heo4447d352007-04-17 23:44:08 +0900973 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +0900975 u32 tmp;
976
977 tmp = readl(port_mmio + PORT_SIG);
978 tf.lbah = (tmp >> 24) & 0xff;
979 tf.lbam = (tmp >> 16) & 0xff;
980 tf.lbal = (tmp >> 8) & 0xff;
981 tf.nsect = (tmp) & 0xff;
982
983 return ata_dev_classify(&tf);
984}
985
Tejun Heo12fad3f2006-05-15 21:03:55 +0900986static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
987 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +0900988{
Tejun Heo12fad3f2006-05-15 21:03:55 +0900989 dma_addr_t cmd_tbl_dma;
990
991 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
992
993 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
994 pp->cmd_slot[tag].status = 0;
995 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
996 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +0900997}
998
Tejun Heod2e75df2007-07-16 14:29:39 +0900999static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001000{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001001 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -04001002 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001003 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001004 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001005
Tejun Heod2e75df2007-07-16 14:29:39 +09001006 /* do we need to kick the port? */
1007 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1008 if (!busy && !force_restart)
1009 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001010
Tejun Heod2e75df2007-07-16 14:29:39 +09001011 /* stop engine */
1012 rc = ahci_stop_engine(ap);
1013 if (rc)
1014 goto out_restart;
1015
1016 /* need to do CLO? */
1017 if (!busy) {
1018 rc = 0;
1019 goto out_restart;
1020 }
1021
1022 if (!(hpriv->cap & HOST_CAP_CLO)) {
1023 rc = -EOPNOTSUPP;
1024 goto out_restart;
1025 }
1026
1027 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001028 tmp = readl(port_mmio + PORT_CMD);
1029 tmp |= PORT_CMD_CLO;
1030 writel(tmp, port_mmio + PORT_CMD);
1031
Tejun Heod2e75df2007-07-16 14:29:39 +09001032 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001033 tmp = ata_wait_register(port_mmio + PORT_CMD,
1034 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1035 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001036 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001037
Tejun Heod2e75df2007-07-16 14:29:39 +09001038 /* restart engine */
1039 out_restart:
1040 ahci_start_engine(ap);
1041 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001042}
1043
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001044static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1045 struct ata_taskfile *tf, int is_cmd, u16 flags,
1046 unsigned long timeout_msec)
1047{
1048 const u32 cmd_fis_len = 5; /* five dwords */
1049 struct ahci_port_priv *pp = ap->private_data;
1050 void __iomem *port_mmio = ahci_port_base(ap);
1051 u8 *fis = pp->cmd_tbl;
1052 u32 tmp;
1053
1054 /* prep the command */
1055 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1056 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1057
1058 /* issue & wait */
1059 writel(1, port_mmio + PORT_CMD_ISSUE);
1060
1061 if (timeout_msec) {
1062 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1063 1, timeout_msec);
1064 if (tmp & 0x1) {
1065 ahci_kick_engine(ap, 1);
1066 return -EBUSY;
1067 }
1068 } else
1069 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1070
1071 return 0;
1072}
1073
Tejun Heocc0680a2007-08-06 18:36:23 +09001074static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001075 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001076{
Tejun Heocc0680a2007-08-06 18:36:23 +09001077 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001078 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001079 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001080 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001081 int rc;
1082
1083 DPRINTK("ENTER\n");
1084
Tejun Heocc0680a2007-08-06 18:36:23 +09001085 if (ata_link_offline(link)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001086 DPRINTK("PHY reports no device\n");
1087 *class = ATA_DEV_NONE;
1088 return 0;
1089 }
1090
Tejun Heo4658f792006-03-22 21:07:03 +09001091 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001092 rc = ahci_kick_engine(ap, 1);
1093 if (rc)
Tejun Heocc0680a2007-08-06 18:36:23 +09001094 ata_link_printk(link, KERN_WARNING,
Tejun Heod2e75df2007-07-16 14:29:39 +09001095 "failed to reset engine (errno=%d)", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001096
Tejun Heocc0680a2007-08-06 18:36:23 +09001097 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001098
1099 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001100 msecs = 0;
1101 now = jiffies;
1102 if (time_after(now, deadline))
1103 msecs = jiffies_to_msecs(deadline - now);
1104
Tejun Heo4658f792006-03-22 21:07:03 +09001105 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001106 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001107 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001108 rc = -EIO;
1109 reason = "1st FIS failed";
1110 goto fail;
1111 }
1112
1113 /* spec says at least 5us, but be generous and sleep for 1ms */
1114 msleep(1);
1115
1116 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001117 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001118 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001119
1120 /* spec mandates ">= 2ms" before checking status.
1121 * We wait 150ms, because that was the magic delay used for
1122 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1123 * between when the ATA command register is written, and then
1124 * status is checked. Because waiting for "a while" before
1125 * checking status is fine, post SRST, we perform this magic
1126 * delay here as well.
1127 */
1128 msleep(150);
1129
Tejun Heo9b893912007-02-02 16:50:52 +09001130 rc = ata_wait_ready(ap, deadline);
1131 /* link occupied, -ENODEV too is an error */
1132 if (rc) {
1133 reason = "device not ready";
1134 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001135 }
Tejun Heo9b893912007-02-02 16:50:52 +09001136 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001137
1138 DPRINTK("EXIT, class=%u\n", *class);
1139 return 0;
1140
Tejun Heo4658f792006-03-22 21:07:03 +09001141 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001142 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001143 return rc;
1144}
1145
Tejun Heocc0680a2007-08-06 18:36:23 +09001146static int ahci_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001147 unsigned long deadline)
1148{
Tejun Heo7d50b602007-09-23 13:19:54 +09001149 int pmp = 0;
1150
1151 if (link->ap->flags & ATA_FLAG_PMP)
1152 pmp = SATA_PMP_CTRL_PORT;
1153
1154 return ahci_do_softreset(link, class, pmp, deadline);
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001155}
1156
Tejun Heocc0680a2007-08-06 18:36:23 +09001157static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001158 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001159{
Tejun Heocc0680a2007-08-06 18:36:23 +09001160 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001161 struct ahci_port_priv *pp = ap->private_data;
1162 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1163 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001164 int rc;
1165
1166 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167
Tejun Heo4447d352007-04-17 23:44:08 +09001168 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001169
1170 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001171 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001172 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001173 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001174
Tejun Heocc0680a2007-08-06 18:36:23 +09001175 rc = sata_std_hardreset(link, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001176
Tejun Heo4447d352007-04-17 23:44:08 +09001177 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178
Tejun Heocc0680a2007-08-06 18:36:23 +09001179 if (rc == 0 && ata_link_online(link))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001180 *class = ahci_dev_classify(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001181 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001182 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183
Tejun Heo4bd00f62006-02-11 16:26:02 +09001184 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1185 return rc;
1186}
1187
Tejun Heocc0680a2007-08-06 18:36:23 +09001188static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001189 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001190{
Tejun Heocc0680a2007-08-06 18:36:23 +09001191 struct ata_port *ap = link->ap;
Tejun Heoda3dbb12007-07-16 14:29:40 +09001192 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001193 int rc;
1194
1195 DPRINTK("ENTER\n");
1196
Tejun Heo4447d352007-04-17 23:44:08 +09001197 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001198
Tejun Heocc0680a2007-08-06 18:36:23 +09001199 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heod4b2bab2007-02-02 16:50:52 +09001200 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001201
1202 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001203 ahci_scr_read(ap, SCR_ERROR, &serror);
1204 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001205
Tejun Heo4447d352007-04-17 23:44:08 +09001206 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001207
1208 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1209
1210 /* vt8251 doesn't clear BSY on signature FIS reception,
1211 * request follow-up softreset.
1212 */
1213 return rc ?: -EAGAIN;
1214}
1215
Tejun Heocc0680a2007-08-06 18:36:23 +09001216static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001217{
Tejun Heocc0680a2007-08-06 18:36:23 +09001218 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001219 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001220 u32 new_tmp, tmp;
1221
Tejun Heocc0680a2007-08-06 18:36:23 +09001222 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001223
1224 /* Make sure port's ATAPI bit is set appropriately */
1225 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001226 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001227 new_tmp |= PORT_CMD_ATAPI;
1228 else
1229 new_tmp &= ~PORT_CMD_ATAPI;
1230 if (new_tmp != tmp) {
1231 writel(new_tmp, port_mmio + PORT_CMD);
1232 readl(port_mmio + PORT_CMD); /* flush */
1233 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234}
1235
Tejun Heo7d50b602007-09-23 13:19:54 +09001236static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1237 unsigned long deadline)
1238{
1239 return ahci_do_softreset(link, class, link->pmp, deadline);
1240}
1241
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242static u8 ahci_check_status(struct ata_port *ap)
1243{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001244 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245
1246 return readl(mmio + PORT_TFDATA) & 0xFF;
1247}
1248
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1250{
1251 struct ahci_port_priv *pp = ap->private_data;
1252 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1253
1254 ata_tf_from_fis(d2h_fis, tf);
1255}
1256
Tejun Heo12fad3f2006-05-15 21:03:55 +09001257static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001259 struct scatterlist *sg;
1260 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001261 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262
1263 VPRINTK("ENTER\n");
1264
1265 /*
1266 * Next, the S/G list.
1267 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001268 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001269 ata_for_each_sg(sg, qc) {
1270 dma_addr_t addr = sg_dma_address(sg);
1271 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001273 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1274 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1275 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -05001276
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001277 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001278 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001280
1281 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282}
1283
1284static void ahci_qc_prep(struct ata_queued_cmd *qc)
1285{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001286 struct ata_port *ap = qc->ap;
1287 struct ahci_port_priv *pp = ap->private_data;
Tejun Heocc9278e2006-02-10 17:25:47 +09001288 int is_atapi = is_atapi_taskfile(&qc->tf);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001289 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290 u32 opts;
1291 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001292 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293
1294 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295 * Fill in command table information. First, the header,
1296 * a SATA Register - Host to Device command FIS.
1297 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001298 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1299
Tejun Heo7d50b602007-09-23 13:19:54 +09001300 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001301 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001302 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1303 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001304 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305
Tejun Heocc9278e2006-02-10 17:25:47 +09001306 n_elem = 0;
1307 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001308 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309
Tejun Heocc9278e2006-02-10 17:25:47 +09001310 /*
1311 * Fill in command slot information.
1312 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001313 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001314 if (qc->tf.flags & ATA_TFLAG_WRITE)
1315 opts |= AHCI_CMD_WRITE;
1316 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001317 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001318
Tejun Heo12fad3f2006-05-15 21:03:55 +09001319 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320}
1321
Tejun Heo78cd52d2006-05-15 20:58:29 +09001322static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323{
Tejun Heo417a1a62007-09-23 13:19:55 +09001324 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001325 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001326 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1327 struct ata_link *link = NULL;
1328 struct ata_queued_cmd *active_qc;
1329 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001330 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001331
Tejun Heo7d50b602007-09-23 13:19:54 +09001332 /* determine active link */
1333 ata_port_for_each_link(link, ap)
1334 if (ata_link_active(link))
1335 break;
1336 if (!link)
1337 link = &ap->link;
1338
1339 active_qc = ata_qc_from_tag(ap, link->active_tag);
1340 active_ehi = &link->eh_info;
1341
1342 /* record irq stat */
1343 ata_ehi_clear_desc(host_ehi);
1344 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001345
Tejun Heo78cd52d2006-05-15 20:58:29 +09001346 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001347 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001348 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001349 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350
Tejun Heo41669552006-11-29 11:33:14 +09001351 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001352 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001353 irq_stat &= ~PORT_IRQ_IF_ERR;
1354
Conke Hu55a61602007-03-27 18:33:05 +08001355 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001356 /* If qc is active, charge it; otherwise, the active
1357 * link. There's no active qc on NCQ errors. It will
1358 * be determined by EH by reading log page 10h.
1359 */
1360 if (active_qc)
1361 active_qc->err_mask |= AC_ERR_DEV;
1362 else
1363 active_ehi->err_mask |= AC_ERR_DEV;
1364
Tejun Heo417a1a62007-09-23 13:19:55 +09001365 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001366 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001367 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368
Tejun Heo78cd52d2006-05-15 20:58:29 +09001369 if (irq_stat & PORT_IRQ_UNK_FIS) {
1370 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371
Tejun Heo7d50b602007-09-23 13:19:54 +09001372 active_ehi->err_mask |= AC_ERR_HSM;
1373 active_ehi->action |= ATA_EH_SOFTRESET;
1374 ata_ehi_push_desc(active_ehi,
1375 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001376 unk[0], unk[1], unk[2], unk[3]);
1377 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001378
Tejun Heo7d50b602007-09-23 13:19:54 +09001379 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1380 active_ehi->err_mask |= AC_ERR_HSM;
1381 active_ehi->action |= ATA_EH_SOFTRESET;
1382 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1383 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001384
Tejun Heo7d50b602007-09-23 13:19:54 +09001385 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1386 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1387 host_ehi->action |= ATA_EH_SOFTRESET;
1388 ata_ehi_push_desc(host_ehi, "host bus error");
1389 }
1390
1391 if (irq_stat & PORT_IRQ_IF_ERR) {
1392 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1393 host_ehi->action |= ATA_EH_SOFTRESET;
1394 ata_ehi_push_desc(host_ehi, "interface fatal error");
1395 }
1396
1397 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1398 ata_ehi_hotplugged(host_ehi);
1399 ata_ehi_push_desc(host_ehi, "%s",
1400 irq_stat & PORT_IRQ_CONNECT ?
1401 "connection status changed" : "PHY RDY changed");
1402 }
1403
1404 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405
Tejun Heo78cd52d2006-05-15 20:58:29 +09001406 if (irq_stat & PORT_IRQ_FREEZE)
1407 ata_port_freeze(ap);
1408 else
1409 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410}
1411
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001412static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413{
Tejun Heo4447d352007-04-17 23:44:08 +09001414 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001415 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001416 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09001417 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09001418 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001419 u32 status, qc_active;
Tejun Heo0291f952007-01-25 19:16:28 +09001420 int rc, known_irq = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421
1422 status = readl(port_mmio + PORT_IRQ_STAT);
1423 writel(status, port_mmio + PORT_IRQ_STAT);
1424
Tejun Heob06ce3e2007-10-09 15:06:48 +09001425 /* ignore BAD_PMP while resetting */
1426 if (unlikely(resetting))
1427 status &= ~PORT_IRQ_BAD_PMP;
1428
Tejun Heo78cd52d2006-05-15 20:58:29 +09001429 if (unlikely(status & PORT_IRQ_ERROR)) {
1430 ahci_error_intr(ap, status);
1431 return;
1432 }
1433
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001434 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09001435 /* If SNotification is available, leave notification
1436 * handling to sata_async_notification(). If not,
1437 * emulate it by snooping SDB FIS RX area.
1438 *
1439 * Snooping FIS RX area is probably cheaper than
1440 * poking SNotification but some constrollers which
1441 * implement SNotification, ICH9 for example, don't
1442 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001443 */
Tejun Heo5f226c62007-10-09 15:02:23 +09001444 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09001445 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09001446 else {
1447 /* If the 'N' bit in word 0 of the FIS is set,
1448 * we just received asynchronous notification.
1449 * Tell libata about it.
1450 */
1451 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1452 u32 f0 = le32_to_cpu(f[0]);
1453
1454 if (f0 & (1 << 15))
1455 sata_async_notification(ap);
1456 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001457 }
1458
Tejun Heo7d50b602007-09-23 13:19:54 +09001459 /* pp->active_link is valid iff any command is in flight */
1460 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001461 qc_active = readl(port_mmio + PORT_SCR_ACT);
1462 else
1463 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1464
1465 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
Tejun Heob06ce3e2007-10-09 15:06:48 +09001466
1467 /* If resetting, spurious or invalid completions are expected,
1468 * return unconditionally.
1469 */
1470 if (resetting)
1471 return;
1472
Tejun Heo12fad3f2006-05-15 21:03:55 +09001473 if (rc > 0)
1474 return;
1475 if (rc < 0) {
1476 ehi->err_mask |= AC_ERR_HSM;
1477 ehi->action |= ATA_EH_SOFTRESET;
1478 ata_port_freeze(ap);
1479 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480 }
1481
Tejun Heo2a3917a2006-05-15 20:58:30 +09001482 /* hmmm... a spurious interupt */
1483
Tejun Heo0291f952007-01-25 19:16:28 +09001484 /* if !NCQ, ignore. No modern ATA device has broken HSM
1485 * implementation for non-NCQ commands.
1486 */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001487 if (!ap->link.sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001488 return;
1489
Tejun Heo0291f952007-01-25 19:16:28 +09001490 if (status & PORT_IRQ_D2H_REG_FIS) {
1491 if (!pp->ncq_saw_d2h)
1492 ata_port_printk(ap, KERN_INFO,
1493 "D2H reg with I during NCQ, "
1494 "this message won't be printed again\n");
1495 pp->ncq_saw_d2h = 1;
1496 known_irq = 1;
1497 }
Tejun Heo2a3917a2006-05-15 20:58:30 +09001498
Tejun Heo0291f952007-01-25 19:16:28 +09001499 if (status & PORT_IRQ_DMAS_FIS) {
1500 if (!pp->ncq_saw_dmas)
1501 ata_port_printk(ap, KERN_INFO,
1502 "DMAS FIS during NCQ, "
1503 "this message won't be printed again\n");
1504 pp->ncq_saw_dmas = 1;
1505 known_irq = 1;
1506 }
1507
Tejun Heoa2bbd0c2007-02-21 16:34:25 +09001508 if (status & PORT_IRQ_SDB_FIS) {
Al Viro04d4f7a2007-02-09 16:39:30 +00001509 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
Tejun Heo0291f952007-01-25 19:16:28 +09001510
Tejun Heoafb2d552007-02-27 13:24:19 +09001511 if (le32_to_cpu(f[1])) {
1512 /* SDB FIS containing spurious completions
1513 * might be dangerous, whine and fail commands
1514 * with HSM violation. EH will turn off NCQ
1515 * after several such failures.
1516 */
1517 ata_ehi_push_desc(ehi,
1518 "spurious completions during NCQ "
1519 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1520 readl(port_mmio + PORT_CMD_ISSUE),
1521 readl(port_mmio + PORT_SCR_ACT),
1522 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1523 ehi->err_mask |= AC_ERR_HSM;
1524 ehi->action |= ATA_EH_SOFTRESET;
1525 ata_port_freeze(ap);
1526 } else {
1527 if (!pp->ncq_saw_sdb)
1528 ata_port_printk(ap, KERN_INFO,
1529 "spurious SDB FIS %08x:%08x during NCQ, "
1530 "this message won't be printed again\n",
1531 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1532 pp->ncq_saw_sdb = 1;
1533 }
Tejun Heo0291f952007-01-25 19:16:28 +09001534 known_irq = 1;
1535 }
1536
1537 if (!known_irq)
Tejun Heo78cd52d2006-05-15 20:58:29 +09001538 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
Tejun Heo0291f952007-01-25 19:16:28 +09001539 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001540 status, ap->link.active_tag, ap->link.sactive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541}
1542
1543static void ahci_irq_clear(struct ata_port *ap)
1544{
1545 /* TODO */
1546}
1547
David Howells7d12e782006-10-05 14:55:46 +01001548static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549{
Jeff Garzikcca39742006-08-24 03:19:22 -04001550 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 struct ahci_host_priv *hpriv;
1552 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001553 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 u32 irq_stat, irq_ack = 0;
1555
1556 VPRINTK("ENTER\n");
1557
Jeff Garzikcca39742006-08-24 03:19:22 -04001558 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001559 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560
1561 /* sigh. 0xffffffff is a valid return from h/w */
1562 irq_stat = readl(mmio + HOST_IRQ_STAT);
1563 irq_stat &= hpriv->port_map;
1564 if (!irq_stat)
1565 return IRQ_NONE;
1566
Jeff Garzikcca39742006-08-24 03:19:22 -04001567 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568
Jeff Garzikcca39742006-08-24 03:19:22 -04001569 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001570 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571
Jeff Garzik67846b32005-10-05 02:58:32 -04001572 if (!(irq_stat & (1 << i)))
1573 continue;
1574
Jeff Garzikcca39742006-08-24 03:19:22 -04001575 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001576 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001577 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001578 VPRINTK("port %u\n", i);
1579 } else {
1580 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001581 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001582 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001583 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001585
1586 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 }
1588
1589 if (irq_ack) {
1590 writel(irq_ack, mmio + HOST_IRQ_STAT);
1591 handled = 1;
1592 }
1593
Jeff Garzikcca39742006-08-24 03:19:22 -04001594 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595
1596 VPRINTK("EXIT\n");
1597
1598 return IRQ_RETVAL(handled);
1599}
1600
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001601static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602{
1603 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001604 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001605 struct ahci_port_priv *pp = ap->private_data;
1606
1607 /* Keep track of the currently active link. It will be used
1608 * in completion path to determine whether NCQ phase is in
1609 * progress.
1610 */
1611 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612
Tejun Heo12fad3f2006-05-15 21:03:55 +09001613 if (qc->tf.protocol == ATA_PROT_NCQ)
1614 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1615 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1617
1618 return 0;
1619}
1620
Tejun Heo78cd52d2006-05-15 20:58:29 +09001621static void ahci_freeze(struct ata_port *ap)
1622{
Tejun Heo4447d352007-04-17 23:44:08 +09001623 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001624
1625 /* turn IRQ off */
1626 writel(0, port_mmio + PORT_IRQ_MASK);
1627}
1628
1629static void ahci_thaw(struct ata_port *ap)
1630{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001631 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001632 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001633 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001634 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001635
1636 /* clear IRQ */
1637 tmp = readl(port_mmio + PORT_IRQ_STAT);
1638 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001639 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001640
Tejun Heo1c954a42007-10-09 15:01:37 +09001641 /* turn IRQ back on */
1642 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001643}
1644
1645static void ahci_error_handler(struct ata_port *ap)
1646{
Tejun Heob51e9e52006-06-29 01:29:30 +09001647 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001648 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001649 ahci_stop_engine(ap);
1650 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001651 }
1652
1653 /* perform recovery */
Tejun Heo7d50b602007-09-23 13:19:54 +09001654 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1655 ahci_hardreset, ahci_postreset,
1656 sata_pmp_std_prereset, ahci_pmp_softreset,
1657 sata_pmp_std_hardreset, sata_pmp_std_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001658}
1659
Tejun Heoad616ff2006-11-01 18:00:24 +09001660static void ahci_vt8251_error_handler(struct ata_port *ap)
1661{
Tejun Heoad616ff2006-11-01 18:00:24 +09001662 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1663 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001664 ahci_stop_engine(ap);
1665 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001666 }
1667
1668 /* perform recovery */
1669 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1670 ahci_postreset);
1671}
1672
Tejun Heo78cd52d2006-05-15 20:58:29 +09001673static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1674{
1675 struct ata_port *ap = qc->ap;
1676
Tejun Heod2e75df2007-07-16 14:29:39 +09001677 /* make DMA engine forget about the failed command */
1678 if (qc->flags & ATA_QCFLAG_FAILED)
1679 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001680}
1681
Tejun Heo7d50b602007-09-23 13:19:54 +09001682static void ahci_pmp_attach(struct ata_port *ap)
1683{
1684 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001685 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001686 u32 cmd;
1687
1688 cmd = readl(port_mmio + PORT_CMD);
1689 cmd |= PORT_CMD_PMP;
1690 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001691
1692 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1693 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001694}
1695
1696static void ahci_pmp_detach(struct ata_port *ap)
1697{
1698 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001699 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001700 u32 cmd;
1701
1702 cmd = readl(port_mmio + PORT_CMD);
1703 cmd &= ~PORT_CMD_PMP;
1704 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001705
1706 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1707 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001708}
1709
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001710static int ahci_port_resume(struct ata_port *ap)
1711{
1712 ahci_power_up(ap);
1713 ahci_start_port(ap);
1714
Tejun Heo7d50b602007-09-23 13:19:54 +09001715 if (ap->nr_pmp_links)
1716 ahci_pmp_attach(ap);
1717 else
1718 ahci_pmp_detach(ap);
1719
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001720 return 0;
1721}
1722
Tejun Heo438ac6d2007-03-02 17:31:26 +09001723#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001724static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1725{
Tejun Heoc1332872006-07-26 15:59:26 +09001726 const char *emsg = NULL;
1727 int rc;
1728
Tejun Heo4447d352007-04-17 23:44:08 +09001729 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001730 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001731 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001732 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001733 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001734 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001735 }
1736
1737 return rc;
1738}
1739
Tejun Heoc1332872006-07-26 15:59:26 +09001740static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1741{
Jeff Garzikcca39742006-08-24 03:19:22 -04001742 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001743 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001744 u32 ctl;
1745
1746 if (mesg.event == PM_EVENT_SUSPEND) {
1747 /* AHCI spec rev1.1 section 8.3.3:
1748 * Software must disable interrupts prior to requesting a
1749 * transition of the HBA to D3 state.
1750 */
1751 ctl = readl(mmio + HOST_CTL);
1752 ctl &= ~HOST_IRQ_EN;
1753 writel(ctl, mmio + HOST_CTL);
1754 readl(mmio + HOST_CTL); /* flush */
1755 }
1756
1757 return ata_pci_device_suspend(pdev, mesg);
1758}
1759
1760static int ahci_pci_device_resume(struct pci_dev *pdev)
1761{
Jeff Garzikcca39742006-08-24 03:19:22 -04001762 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001763 int rc;
1764
Tejun Heo553c4aa2006-12-26 19:39:50 +09001765 rc = ata_pci_device_do_resume(pdev);
1766 if (rc)
1767 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09001768
1769 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09001770 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001771 if (rc)
1772 return rc;
1773
Tejun Heo4447d352007-04-17 23:44:08 +09001774 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001775 }
1776
Jeff Garzikcca39742006-08-24 03:19:22 -04001777 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001778
1779 return 0;
1780}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001781#endif
Tejun Heoc1332872006-07-26 15:59:26 +09001782
Tejun Heo254950c2006-07-26 15:59:25 +09001783static int ahci_port_start(struct ata_port *ap)
1784{
Jeff Garzikcca39742006-08-24 03:19:22 -04001785 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09001786 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09001787 void *mem;
1788 dma_addr_t mem_dma;
1789 int rc;
1790
Tejun Heo24dc5f32007-01-20 16:00:28 +09001791 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09001792 if (!pp)
1793 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001794
1795 rc = ata_pad_alloc(ap, dev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001796 if (rc)
Tejun Heo254950c2006-07-26 15:59:25 +09001797 return rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001798
Tejun Heo24dc5f32007-01-20 16:00:28 +09001799 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1800 GFP_KERNEL);
1801 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09001802 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001803 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1804
1805 /*
1806 * First item in chunk of DMA memory: 32-slot command table,
1807 * 32 bytes each in size
1808 */
1809 pp->cmd_slot = mem;
1810 pp->cmd_slot_dma = mem_dma;
1811
1812 mem += AHCI_CMD_SLOT_SZ;
1813 mem_dma += AHCI_CMD_SLOT_SZ;
1814
1815 /*
1816 * Second item: Received-FIS area
1817 */
1818 pp->rx_fis = mem;
1819 pp->rx_fis_dma = mem_dma;
1820
1821 mem += AHCI_RX_FIS_SZ;
1822 mem_dma += AHCI_RX_FIS_SZ;
1823
1824 /*
1825 * Third item: data area for storing a single command
1826 * and its scatter-gather table
1827 */
1828 pp->cmd_tbl = mem;
1829 pp->cmd_tbl_dma = mem_dma;
1830
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001831 /*
1832 * Save off initial list of interrupts to be enabled.
1833 * This could be changed later
1834 */
1835 pp->intr_mask = DEF_PORT_IRQ;
1836
Tejun Heo254950c2006-07-26 15:59:25 +09001837 ap->private_data = pp;
1838
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001839 /* engage engines, captain */
1840 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09001841}
1842
1843static void ahci_port_stop(struct ata_port *ap)
1844{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001845 const char *emsg = NULL;
1846 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001847
Tejun Heo0be0aa92006-07-26 15:59:26 +09001848 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09001849 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001850 if (rc)
1851 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09001852}
1853
Tejun Heo4447d352007-04-17 23:44:08 +09001854static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001855{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858 if (using_dac &&
1859 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1860 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1861 if (rc) {
1862 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1863 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001864 dev_printk(KERN_ERR, &pdev->dev,
1865 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866 return rc;
1867 }
1868 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869 } else {
1870 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1871 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001872 dev_printk(KERN_ERR, &pdev->dev,
1873 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874 return rc;
1875 }
1876 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1877 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001878 dev_printk(KERN_ERR, &pdev->dev,
1879 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 return rc;
1881 }
1882 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883 return 0;
1884}
1885
Tejun Heo4447d352007-04-17 23:44:08 +09001886static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887{
Tejun Heo4447d352007-04-17 23:44:08 +09001888 struct ahci_host_priv *hpriv = host->private_data;
1889 struct pci_dev *pdev = to_pci_dev(host->dev);
1890 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 u32 vers, cap, impl, speed;
1892 const char *speed_s;
1893 u16 cc;
1894 const char *scc_s;
1895
1896 vers = readl(mmio + HOST_VERSION);
1897 cap = hpriv->cap;
1898 impl = hpriv->port_map;
1899
1900 speed = (cap >> 20) & 0xf;
1901 if (speed == 1)
1902 speed_s = "1.5";
1903 else if (speed == 2)
1904 speed_s = "3";
1905 else
1906 speed_s = "?";
1907
1908 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05001909 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05001911 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05001913 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914 scc_s = "RAID";
1915 else
1916 scc_s = "unknown";
1917
Jeff Garzika9524a72005-10-30 14:39:11 -05001918 dev_printk(KERN_INFO, &pdev->dev,
1919 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001920 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1921 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001922
1923 (vers >> 24) & 0xff,
1924 (vers >> 16) & 0xff,
1925 (vers >> 8) & 0xff,
1926 vers & 0xff,
1927
1928 ((cap >> 8) & 0x1f) + 1,
1929 (cap & 0x1f) + 1,
1930 speed_s,
1931 impl,
1932 scc_s);
1933
Jeff Garzika9524a72005-10-30 14:39:11 -05001934 dev_printk(KERN_INFO, &pdev->dev,
1935 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09001936 "%s%s%s%s%s%s%s"
1937 "%s%s%s%s%s%s%s\n"
Linus Torvalds1da177e2005-04-16 15:20:36 -07001938 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939
1940 cap & (1 << 31) ? "64bit " : "",
1941 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09001942 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001943 cap & (1 << 28) ? "ilck " : "",
1944 cap & (1 << 27) ? "stag " : "",
1945 cap & (1 << 26) ? "pm " : "",
1946 cap & (1 << 25) ? "led " : "",
1947
1948 cap & (1 << 24) ? "clo " : "",
1949 cap & (1 << 19) ? "nz " : "",
1950 cap & (1 << 18) ? "only " : "",
1951 cap & (1 << 17) ? "pmp " : "",
1952 cap & (1 << 15) ? "pio " : "",
1953 cap & (1 << 14) ? "slum " : "",
1954 cap & (1 << 13) ? "part " : ""
1955 );
1956}
1957
Tejun Heo24dc5f32007-01-20 16:00:28 +09001958static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959{
1960 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09001961 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1962 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001963 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001965 struct ata_host *host;
1966 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967
1968 VPRINTK("ENTER\n");
1969
Tejun Heo12fad3f2006-05-15 21:03:55 +09001970 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1971
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001973 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974
Tejun Heo4447d352007-04-17 23:44:08 +09001975 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001976 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 if (rc)
1978 return rc;
1979
Tejun Heo0d5ff562007-02-01 15:06:36 +09001980 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1981 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001982 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001983 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001984 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985
Tejun Heo24dc5f32007-01-20 16:00:28 +09001986 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1987 if (!hpriv)
1988 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001989 hpriv->flags |= (unsigned long)pi.private_data;
1990
1991 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1992 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993
Tejun Heo4447d352007-04-17 23:44:08 +09001994 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09001995 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996
Tejun Heo4447d352007-04-17 23:44:08 +09001997 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09001998 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09001999 pi.flags |= ATA_FLAG_NCQ;
2000
Tejun Heo7d50b602007-09-23 13:19:54 +09002001 if (hpriv->cap & HOST_CAP_PMP)
2002 pi.flags |= ATA_FLAG_PMP;
2003
Tejun Heo4447d352007-04-17 23:44:08 +09002004 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2005 if (!host)
2006 return -ENOMEM;
2007 host->iomap = pcim_iomap_table(pdev);
2008 host->private_data = hpriv;
2009
2010 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002011 struct ata_port *ap = host->ports[i];
2012 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09002013
Tejun Heocbcdd872007-08-18 13:14:55 +09002014 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2015 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2016 0x100 + ap->port_no * 0x80, "port");
2017
Jeff Garzikdab632e2007-05-28 08:33:01 -04002018 /* standard SATA port setup */
Tejun Heo203ef6c2007-07-16 14:29:40 +09002019 if (hpriv->port_map & (1 << i))
Tejun Heo4447d352007-04-17 23:44:08 +09002020 ap->ioaddr.cmd_addr = port_mmio;
Jeff Garzikdab632e2007-05-28 08:33:01 -04002021
2022 /* disabled/not-implemented port */
2023 else
2024 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002025 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002026
2027 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002028 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002029 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002030 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031
Tejun Heo4447d352007-04-17 23:44:08 +09002032 rc = ahci_reset_controller(host);
2033 if (rc)
2034 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002035
Tejun Heo4447d352007-04-17 23:44:08 +09002036 ahci_init_controller(host);
2037 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038
Tejun Heo4447d352007-04-17 23:44:08 +09002039 pci_set_master(pdev);
2040 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2041 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002042}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043
2044static int __init ahci_init(void)
2045{
Pavel Roskinb7887192006-08-10 18:13:18 +09002046 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047}
2048
Linus Torvalds1da177e2005-04-16 15:20:36 -07002049static void __exit ahci_exit(void)
2050{
2051 pci_unregister_driver(&ahci_pci_driver);
2052}
2053
2054
2055MODULE_AUTHOR("Jeff Garzik");
2056MODULE_DESCRIPTION("AHCI SATA low-level driver");
2057MODULE_LICENSE("GPL");
2058MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002059MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002060
2061module_init(ahci_init);
2062module_exit(ahci_exit);