Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 40 | |
| 41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 42 | bool pipelined); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 52 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 54 | unsigned alignment, bool mappable); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 57 | struct drm_i915_gem_pwrite *args, |
| 58 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 60 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 61 | static int |
| 62 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 63 | gfp_t gfpmask); |
| 64 | |
| 65 | static void |
| 66 | i915_gem_object_put_pages(struct drm_gem_object *obj); |
| 67 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 68 | static LIST_HEAD(shrink_list); |
| 69 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 87 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 88 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 89 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 90 | dev_priv->mm.gtt_count++; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 91 | dev_priv->mm.gtt_memory += obj->size; |
| 92 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
| 93 | dev_priv->mm.mappable_gtt_used += |
| 94 | min_t(size_t, obj->size, |
| 95 | dev_priv->mm.gtt_mappable_end |
| 96 | - obj_priv->gtt_offset); |
| 97 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 101 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 102 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 103 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 104 | dev_priv->mm.gtt_count--; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 105 | dev_priv->mm.gtt_memory -= obj->size; |
| 106 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
| 107 | dev_priv->mm.mappable_gtt_used -= |
| 108 | min_t(size_t, obj->size, |
| 109 | dev_priv->mm.gtt_mappable_end |
| 110 | - obj_priv->gtt_offset); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * Update the mappable working set counters. Call _only_ when there is a change |
| 116 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. |
| 117 | * @mappable: new state the changed mappable flag (either pin_ or fault_). |
| 118 | */ |
| 119 | static void |
| 120 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, |
| 121 | struct drm_gem_object *obj, |
| 122 | bool mappable) |
| 123 | { |
| 124 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 125 | |
| 126 | if (mappable) { |
| 127 | if (obj_priv->pin_mappable && obj_priv->fault_mappable) |
| 128 | /* Combined state was already mappable. */ |
| 129 | return; |
| 130 | dev_priv->mm.gtt_mappable_count++; |
| 131 | dev_priv->mm.gtt_mappable_memory += obj->size; |
| 132 | } else { |
| 133 | if (obj_priv->pin_mappable || obj_priv->fault_mappable) |
| 134 | /* Combined state still mappable. */ |
| 135 | return; |
| 136 | dev_priv->mm.gtt_mappable_count--; |
| 137 | dev_priv->mm.gtt_mappable_memory -= obj->size; |
| 138 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 142 | struct drm_gem_object *obj, |
| 143 | bool mappable) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 144 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 145 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 146 | dev_priv->mm.pin_count++; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 147 | dev_priv->mm.pin_memory += obj->size; |
| 148 | if (mappable) { |
| 149 | obj_priv->pin_mappable = true; |
| 150 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 151 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 155 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 156 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 157 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 158 | dev_priv->mm.pin_count--; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 159 | dev_priv->mm.pin_memory -= obj->size; |
| 160 | if (obj_priv->pin_mappable) { |
| 161 | obj_priv->pin_mappable = false; |
| 162 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 163 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 166 | int |
| 167 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 168 | { |
| 169 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 170 | struct completion *x = &dev_priv->error_completion; |
| 171 | unsigned long flags; |
| 172 | int ret; |
| 173 | |
| 174 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 175 | return 0; |
| 176 | |
| 177 | ret = wait_for_completion_interruptible(x); |
| 178 | if (ret) |
| 179 | return ret; |
| 180 | |
| 181 | /* Success, we reset the GPU! */ |
| 182 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 183 | return 0; |
| 184 | |
| 185 | /* GPU is hung, bump the completion count to account for |
| 186 | * the token we just consumed so that we never hit zero and |
| 187 | * end up waiting upon a subsequent completion event that |
| 188 | * will never happen. |
| 189 | */ |
| 190 | spin_lock_irqsave(&x->wait.lock, flags); |
| 191 | x->done++; |
| 192 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 193 | return -EIO; |
| 194 | } |
| 195 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 196 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 197 | { |
| 198 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 199 | int ret; |
| 200 | |
| 201 | ret = i915_gem_check_is_wedged(dev); |
| 202 | if (ret) |
| 203 | return ret; |
| 204 | |
| 205 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 206 | if (ret) |
| 207 | return ret; |
| 208 | |
| 209 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 210 | mutex_unlock(&dev->struct_mutex); |
| 211 | return -EAGAIN; |
| 212 | } |
| 213 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 214 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 215 | return 0; |
| 216 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 217 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 218 | static inline bool |
| 219 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 220 | { |
| 221 | return obj_priv->gtt_space && |
| 222 | !obj_priv->active && |
| 223 | obj_priv->pin_count == 0; |
| 224 | } |
| 225 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 226 | int i915_gem_do_init(struct drm_device *dev, |
| 227 | unsigned long start, |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 228 | unsigned long mappable_end, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 229 | unsigned long end) |
| 230 | { |
| 231 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 232 | |
| 233 | if (start >= end || |
| 234 | (start & (PAGE_SIZE - 1)) != 0 || |
| 235 | (end & (PAGE_SIZE - 1)) != 0) { |
| 236 | return -EINVAL; |
| 237 | } |
| 238 | |
| 239 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 240 | end - start); |
| 241 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 242 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 243 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 244 | dev_priv->mm.gtt_mappable_end = mappable_end; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 245 | |
| 246 | return 0; |
| 247 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 248 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 249 | int |
| 250 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 251 | struct drm_file *file_priv) |
| 252 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 254 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 255 | |
| 256 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 257 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | mutex_unlock(&dev->struct_mutex); |
| 259 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 260 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 261 | } |
| 262 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 263 | int |
| 264 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 265 | struct drm_file *file_priv) |
| 266 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 267 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 268 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 269 | |
| 270 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 271 | return -ENODEV; |
| 272 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 273 | mutex_lock(&dev->struct_mutex); |
| 274 | args->aper_size = dev_priv->mm.gtt_total; |
| 275 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 276 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 281 | |
| 282 | /** |
| 283 | * Creates a new mm object and returns a handle to it. |
| 284 | */ |
| 285 | int |
| 286 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 287 | struct drm_file *file_priv) |
| 288 | { |
| 289 | struct drm_i915_gem_create *args = data; |
| 290 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 291 | int ret; |
| 292 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 293 | |
| 294 | args->size = roundup(args->size, PAGE_SIZE); |
| 295 | |
| 296 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 297 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 298 | if (obj == NULL) |
| 299 | return -ENOMEM; |
| 300 | |
| 301 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 302 | if (ret) { |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 303 | drm_gem_object_release(obj); |
| 304 | i915_gem_info_remove_obj(dev->dev_private, obj->size); |
| 305 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 306 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 307 | } |
| 308 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 309 | /* drop reference from allocate - handle holds it now */ |
| 310 | drm_gem_object_unreference(obj); |
| 311 | trace_i915_gem_object_create(obj); |
| 312 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 313 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 314 | return 0; |
| 315 | } |
| 316 | |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 317 | static bool |
| 318 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) |
| 319 | { |
| 320 | struct drm_device *dev = obj->base.dev; |
| 321 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 322 | |
| 323 | return obj->gtt_space == NULL || |
| 324 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
| 325 | } |
| 326 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 327 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 328 | fast_shmem_read(struct page **pages, |
| 329 | loff_t page_base, int page_offset, |
| 330 | char __user *data, |
| 331 | int length) |
| 332 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 333 | char *vaddr; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 334 | int ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 335 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 336 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 337 | ret = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 338 | kunmap_atomic(vaddr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 339 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 340 | return ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 341 | } |
| 342 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 343 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 344 | { |
| 345 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 346 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 347 | |
| 348 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 349 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 350 | } |
| 351 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 352 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 353 | slow_shmem_copy(struct page *dst_page, |
| 354 | int dst_offset, |
| 355 | struct page *src_page, |
| 356 | int src_offset, |
| 357 | int length) |
| 358 | { |
| 359 | char *dst_vaddr, *src_vaddr; |
| 360 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 361 | dst_vaddr = kmap(dst_page); |
| 362 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 363 | |
| 364 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 365 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 366 | kunmap(src_page); |
| 367 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 368 | } |
| 369 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 370 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 371 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 372 | int gpu_offset, |
| 373 | struct page *cpu_page, |
| 374 | int cpu_offset, |
| 375 | int length, |
| 376 | int is_read) |
| 377 | { |
| 378 | char *gpu_vaddr, *cpu_vaddr; |
| 379 | |
| 380 | /* Use the unswizzled path if this page isn't affected. */ |
| 381 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 382 | if (is_read) |
| 383 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 384 | gpu_page, gpu_offset, length); |
| 385 | else |
| 386 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 387 | cpu_page, cpu_offset, length); |
| 388 | } |
| 389 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 390 | gpu_vaddr = kmap(gpu_page); |
| 391 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 392 | |
| 393 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 394 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 395 | */ |
| 396 | while (length > 0) { |
| 397 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 398 | int this_length = min(cacheline_end - gpu_offset, length); |
| 399 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 400 | |
| 401 | if (is_read) { |
| 402 | memcpy(cpu_vaddr + cpu_offset, |
| 403 | gpu_vaddr + swizzled_gpu_offset, |
| 404 | this_length); |
| 405 | } else { |
| 406 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 407 | cpu_vaddr + cpu_offset, |
| 408 | this_length); |
| 409 | } |
| 410 | cpu_offset += this_length; |
| 411 | gpu_offset += this_length; |
| 412 | length -= this_length; |
| 413 | } |
| 414 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 415 | kunmap(cpu_page); |
| 416 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 417 | } |
| 418 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 419 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 420 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 421 | * from the backing pages of the object to the user's address space. On a |
| 422 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 423 | */ |
| 424 | static int |
| 425 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 426 | struct drm_i915_gem_pread *args, |
| 427 | struct drm_file *file_priv) |
| 428 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 429 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 430 | ssize_t remain; |
| 431 | loff_t offset, page_base; |
| 432 | char __user *user_data; |
| 433 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 434 | |
| 435 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 436 | remain = args->size; |
| 437 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 438 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 439 | offset = args->offset; |
| 440 | |
| 441 | while (remain > 0) { |
| 442 | /* Operation in this page |
| 443 | * |
| 444 | * page_base = page offset within aperture |
| 445 | * page_offset = offset within page |
| 446 | * page_length = bytes to copy for this page |
| 447 | */ |
| 448 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 449 | page_offset = offset & (PAGE_SIZE-1); |
| 450 | page_length = remain; |
| 451 | if ((page_offset + remain) > PAGE_SIZE) |
| 452 | page_length = PAGE_SIZE - page_offset; |
| 453 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 454 | if (fast_shmem_read(obj_priv->pages, |
| 455 | page_base, page_offset, |
| 456 | user_data, page_length)) |
| 457 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | |
| 459 | remain -= page_length; |
| 460 | user_data += page_length; |
| 461 | offset += page_length; |
| 462 | } |
| 463 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 464 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 465 | } |
| 466 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 467 | static int |
| 468 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 469 | { |
| 470 | int ret; |
| 471 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 472 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 473 | |
| 474 | /* If we've insufficient memory to map in the pages, attempt |
| 475 | * to make some space by throwing out some old buffers. |
| 476 | */ |
| 477 | if (ret == -ENOMEM) { |
| 478 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 479 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 480 | ret = i915_gem_evict_something(dev, obj->size, |
Daniel Vetter | a6e0aa4 | 2010-09-16 15:45:15 +0200 | [diff] [blame] | 481 | i915_gem_get_gtt_alignment(obj), |
| 482 | false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 483 | if (ret) |
| 484 | return ret; |
| 485 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 486 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | return ret; |
| 490 | } |
| 491 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 492 | /** |
| 493 | * This is the fallback shmem pread path, which allocates temporary storage |
| 494 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 495 | * can copy out of the object's backing pages while holding the struct mutex |
| 496 | * and not take page faults. |
| 497 | */ |
| 498 | static int |
| 499 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 500 | struct drm_i915_gem_pread *args, |
| 501 | struct drm_file *file_priv) |
| 502 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 503 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 504 | struct mm_struct *mm = current->mm; |
| 505 | struct page **user_pages; |
| 506 | ssize_t remain; |
| 507 | loff_t offset, pinned_pages, i; |
| 508 | loff_t first_data_page, last_data_page, num_pages; |
| 509 | int shmem_page_index, shmem_page_offset; |
| 510 | int data_page_index, data_page_offset; |
| 511 | int page_length; |
| 512 | int ret; |
| 513 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 514 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 515 | |
| 516 | remain = args->size; |
| 517 | |
| 518 | /* Pin the user pages containing the data. We can't fault while |
| 519 | * holding the struct mutex, yet we want to hold it while |
| 520 | * dereferencing the user data. |
| 521 | */ |
| 522 | first_data_page = data_ptr / PAGE_SIZE; |
| 523 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 524 | num_pages = last_data_page - first_data_page + 1; |
| 525 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 526 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 527 | if (user_pages == NULL) |
| 528 | return -ENOMEM; |
| 529 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 530 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 531 | down_read(&mm->mmap_sem); |
| 532 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 533 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 534 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 535 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 536 | if (pinned_pages < num_pages) { |
| 537 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 538 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 539 | } |
| 540 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 541 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 542 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 543 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 544 | if (ret) |
| 545 | goto out; |
| 546 | |
| 547 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 548 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 549 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 550 | offset = args->offset; |
| 551 | |
| 552 | while (remain > 0) { |
| 553 | /* Operation in this page |
| 554 | * |
| 555 | * shmem_page_index = page number within shmem file |
| 556 | * shmem_page_offset = offset within page in shmem file |
| 557 | * data_page_index = page number in get_user_pages return |
| 558 | * data_page_offset = offset with data_page_index page. |
| 559 | * page_length = bytes to copy for this page |
| 560 | */ |
| 561 | shmem_page_index = offset / PAGE_SIZE; |
| 562 | shmem_page_offset = offset & ~PAGE_MASK; |
| 563 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 564 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 565 | |
| 566 | page_length = remain; |
| 567 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 568 | page_length = PAGE_SIZE - shmem_page_offset; |
| 569 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 570 | page_length = PAGE_SIZE - data_page_offset; |
| 571 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 572 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 573 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 574 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 575 | user_pages[data_page_index], |
| 576 | data_page_offset, |
| 577 | page_length, |
| 578 | 1); |
| 579 | } else { |
| 580 | slow_shmem_copy(user_pages[data_page_index], |
| 581 | data_page_offset, |
| 582 | obj_priv->pages[shmem_page_index], |
| 583 | shmem_page_offset, |
| 584 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 585 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 586 | |
| 587 | remain -= page_length; |
| 588 | data_ptr += page_length; |
| 589 | offset += page_length; |
| 590 | } |
| 591 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 592 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 593 | for (i = 0; i < pinned_pages; i++) { |
| 594 | SetPageDirty(user_pages[i]); |
| 595 | page_cache_release(user_pages[i]); |
| 596 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 597 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 598 | |
| 599 | return ret; |
| 600 | } |
| 601 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 602 | /** |
| 603 | * Reads data from the object referenced by handle. |
| 604 | * |
| 605 | * On error, the contents of *data are undefined. |
| 606 | */ |
| 607 | int |
| 608 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 609 | struct drm_file *file_priv) |
| 610 | { |
| 611 | struct drm_i915_gem_pread *args = data; |
| 612 | struct drm_gem_object *obj; |
| 613 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 614 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 615 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 616 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 617 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 618 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 619 | |
| 620 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 621 | if (obj == NULL) { |
| 622 | ret = -ENOENT; |
| 623 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 624 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 625 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 626 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 627 | /* Bounds check source. */ |
| 628 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 629 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 630 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 631 | } |
| 632 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 633 | if (args->size == 0) |
| 634 | goto out; |
| 635 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 636 | if (!access_ok(VERIFY_WRITE, |
| 637 | (char __user *)(uintptr_t)args->data_ptr, |
| 638 | args->size)) { |
| 639 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 640 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 641 | } |
| 642 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 643 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 644 | args->size); |
| 645 | if (ret) { |
| 646 | ret = -EFAULT; |
| 647 | goto out; |
| 648 | } |
| 649 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 650 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 651 | if (ret) |
| 652 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 653 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 654 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 655 | args->offset, |
| 656 | args->size); |
| 657 | if (ret) |
| 658 | goto out_put; |
| 659 | |
| 660 | ret = -EFAULT; |
| 661 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 662 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 663 | if (ret == -EFAULT) |
| 664 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 665 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 666 | out_put: |
| 667 | i915_gem_object_put_pages(obj); |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 668 | out: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 669 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 670 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 671 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 672 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 673 | } |
| 674 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 675 | /* This is the fast write path which cannot handle |
| 676 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 677 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 678 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 679 | static inline int |
| 680 | fast_user_write(struct io_mapping *mapping, |
| 681 | loff_t page_base, int page_offset, |
| 682 | char __user *user_data, |
| 683 | int length) |
| 684 | { |
| 685 | char *vaddr_atomic; |
| 686 | unsigned long unwritten; |
| 687 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 688 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 689 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 690 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 691 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 692 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 693 | } |
| 694 | |
| 695 | /* Here's the write path which can sleep for |
| 696 | * page faults |
| 697 | */ |
| 698 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 699 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 700 | slow_kernel_write(struct io_mapping *mapping, |
| 701 | loff_t gtt_base, int gtt_offset, |
| 702 | struct page *user_page, int user_offset, |
| 703 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 704 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 705 | char __iomem *dst_vaddr; |
| 706 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 707 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 708 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 709 | src_vaddr = kmap(user_page); |
| 710 | |
| 711 | memcpy_toio(dst_vaddr + gtt_offset, |
| 712 | src_vaddr + user_offset, |
| 713 | length); |
| 714 | |
| 715 | kunmap(user_page); |
| 716 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 717 | } |
| 718 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 719 | static inline int |
| 720 | fast_shmem_write(struct page **pages, |
| 721 | loff_t page_base, int page_offset, |
| 722 | char __user *data, |
| 723 | int length) |
| 724 | { |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 725 | char *vaddr; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 726 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 727 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 728 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 729 | ret = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 730 | kunmap_atomic(vaddr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 731 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 732 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 733 | } |
| 734 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 735 | /** |
| 736 | * This is the fast pwrite path, where we copy the data directly from the |
| 737 | * user into the GTT, uncached. |
| 738 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 739 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 740 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 741 | struct drm_i915_gem_pwrite *args, |
| 742 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 743 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 744 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 745 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 746 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 747 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 748 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 749 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 750 | |
| 751 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 752 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 753 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 754 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 755 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 756 | |
| 757 | while (remain > 0) { |
| 758 | /* Operation in this page |
| 759 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 760 | * page_base = page offset within aperture |
| 761 | * page_offset = offset within page |
| 762 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 763 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 764 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 765 | page_offset = offset & (PAGE_SIZE-1); |
| 766 | page_length = remain; |
| 767 | if ((page_offset + remain) > PAGE_SIZE) |
| 768 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 769 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 770 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 771 | * source page isn't available. Return the error and we'll |
| 772 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 773 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 774 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 775 | page_offset, user_data, page_length)) |
| 776 | |
| 777 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 778 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 779 | remain -= page_length; |
| 780 | user_data += page_length; |
| 781 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 782 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 783 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 784 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 785 | } |
| 786 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 787 | /** |
| 788 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 789 | * the memory and maps it using kmap_atomic for copying. |
| 790 | * |
| 791 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 792 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 793 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 794 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 795 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 796 | struct drm_i915_gem_pwrite *args, |
| 797 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 798 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 799 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 800 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 801 | ssize_t remain; |
| 802 | loff_t gtt_page_base, offset; |
| 803 | loff_t first_data_page, last_data_page, num_pages; |
| 804 | loff_t pinned_pages, i; |
| 805 | struct page **user_pages; |
| 806 | struct mm_struct *mm = current->mm; |
| 807 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 808 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 809 | uint64_t data_ptr = args->data_ptr; |
| 810 | |
| 811 | remain = args->size; |
| 812 | |
| 813 | /* Pin the user pages containing the data. We can't fault while |
| 814 | * holding the struct mutex, and all of the pwrite implementations |
| 815 | * want to hold it while dereferencing the user data. |
| 816 | */ |
| 817 | first_data_page = data_ptr / PAGE_SIZE; |
| 818 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 819 | num_pages = last_data_page - first_data_page + 1; |
| 820 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 821 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 822 | if (user_pages == NULL) |
| 823 | return -ENOMEM; |
| 824 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 825 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 826 | down_read(&mm->mmap_sem); |
| 827 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 828 | num_pages, 0, 0, user_pages, NULL); |
| 829 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 830 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 831 | if (pinned_pages < num_pages) { |
| 832 | ret = -EFAULT; |
| 833 | goto out_unpin_pages; |
| 834 | } |
| 835 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 836 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 837 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 838 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 839 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 840 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 841 | offset = obj_priv->gtt_offset + args->offset; |
| 842 | |
| 843 | while (remain > 0) { |
| 844 | /* Operation in this page |
| 845 | * |
| 846 | * gtt_page_base = page offset within aperture |
| 847 | * gtt_page_offset = offset within page in aperture |
| 848 | * data_page_index = page number in get_user_pages return |
| 849 | * data_page_offset = offset with data_page_index page. |
| 850 | * page_length = bytes to copy for this page |
| 851 | */ |
| 852 | gtt_page_base = offset & PAGE_MASK; |
| 853 | gtt_page_offset = offset & ~PAGE_MASK; |
| 854 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 855 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 856 | |
| 857 | page_length = remain; |
| 858 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 859 | page_length = PAGE_SIZE - gtt_page_offset; |
| 860 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 861 | page_length = PAGE_SIZE - data_page_offset; |
| 862 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 863 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 864 | gtt_page_base, gtt_page_offset, |
| 865 | user_pages[data_page_index], |
| 866 | data_page_offset, |
| 867 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 868 | |
| 869 | remain -= page_length; |
| 870 | offset += page_length; |
| 871 | data_ptr += page_length; |
| 872 | } |
| 873 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 874 | out_unpin_pages: |
| 875 | for (i = 0; i < pinned_pages; i++) |
| 876 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 877 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 878 | |
| 879 | return ret; |
| 880 | } |
| 881 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 882 | /** |
| 883 | * This is the fast shmem pwrite path, which attempts to directly |
| 884 | * copy_from_user into the kmapped pages backing the object. |
| 885 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 886 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 887 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 888 | struct drm_i915_gem_pwrite *args, |
| 889 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 890 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 891 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 892 | ssize_t remain; |
| 893 | loff_t offset, page_base; |
| 894 | char __user *user_data; |
| 895 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 896 | |
| 897 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 898 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 899 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 900 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 901 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 902 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 903 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 904 | while (remain > 0) { |
| 905 | /* Operation in this page |
| 906 | * |
| 907 | * page_base = page offset within aperture |
| 908 | * page_offset = offset within page |
| 909 | * page_length = bytes to copy for this page |
| 910 | */ |
| 911 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 912 | page_offset = offset & (PAGE_SIZE-1); |
| 913 | page_length = remain; |
| 914 | if ((page_offset + remain) > PAGE_SIZE) |
| 915 | page_length = PAGE_SIZE - page_offset; |
| 916 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 917 | if (fast_shmem_write(obj_priv->pages, |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 918 | page_base, page_offset, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 919 | user_data, page_length)) |
| 920 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 921 | |
| 922 | remain -= page_length; |
| 923 | user_data += page_length; |
| 924 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 925 | } |
| 926 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 927 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | /** |
| 931 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 932 | * the memory and maps it using kmap_atomic for copying. |
| 933 | * |
| 934 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 935 | * struct_mutex is held. |
| 936 | */ |
| 937 | static int |
| 938 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 939 | struct drm_i915_gem_pwrite *args, |
| 940 | struct drm_file *file_priv) |
| 941 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 942 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 943 | struct mm_struct *mm = current->mm; |
| 944 | struct page **user_pages; |
| 945 | ssize_t remain; |
| 946 | loff_t offset, pinned_pages, i; |
| 947 | loff_t first_data_page, last_data_page, num_pages; |
| 948 | int shmem_page_index, shmem_page_offset; |
| 949 | int data_page_index, data_page_offset; |
| 950 | int page_length; |
| 951 | int ret; |
| 952 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 953 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 954 | |
| 955 | remain = args->size; |
| 956 | |
| 957 | /* Pin the user pages containing the data. We can't fault while |
| 958 | * holding the struct mutex, and all of the pwrite implementations |
| 959 | * want to hold it while dereferencing the user data. |
| 960 | */ |
| 961 | first_data_page = data_ptr / PAGE_SIZE; |
| 962 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 963 | num_pages = last_data_page - first_data_page + 1; |
| 964 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 965 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 966 | if (user_pages == NULL) |
| 967 | return -ENOMEM; |
| 968 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 969 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 970 | down_read(&mm->mmap_sem); |
| 971 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 972 | num_pages, 0, 0, user_pages, NULL); |
| 973 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 974 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 975 | if (pinned_pages < num_pages) { |
| 976 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 977 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 978 | } |
| 979 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 980 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 981 | if (ret) |
| 982 | goto out; |
| 983 | |
| 984 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 985 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 986 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 987 | offset = args->offset; |
| 988 | obj_priv->dirty = 1; |
| 989 | |
| 990 | while (remain > 0) { |
| 991 | /* Operation in this page |
| 992 | * |
| 993 | * shmem_page_index = page number within shmem file |
| 994 | * shmem_page_offset = offset within page in shmem file |
| 995 | * data_page_index = page number in get_user_pages return |
| 996 | * data_page_offset = offset with data_page_index page. |
| 997 | * page_length = bytes to copy for this page |
| 998 | */ |
| 999 | shmem_page_index = offset / PAGE_SIZE; |
| 1000 | shmem_page_offset = offset & ~PAGE_MASK; |
| 1001 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 1002 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 1003 | |
| 1004 | page_length = remain; |
| 1005 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 1006 | page_length = PAGE_SIZE - shmem_page_offset; |
| 1007 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 1008 | page_length = PAGE_SIZE - data_page_offset; |
| 1009 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1010 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 1011 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1012 | shmem_page_offset, |
| 1013 | user_pages[data_page_index], |
| 1014 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 1015 | page_length, |
| 1016 | 0); |
| 1017 | } else { |
| 1018 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 1019 | shmem_page_offset, |
| 1020 | user_pages[data_page_index], |
| 1021 | data_page_offset, |
| 1022 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1023 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1024 | |
| 1025 | remain -= page_length; |
| 1026 | data_ptr += page_length; |
| 1027 | offset += page_length; |
| 1028 | } |
| 1029 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1030 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1031 | for (i = 0; i < pinned_pages; i++) |
| 1032 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1033 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1034 | |
| 1035 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1036 | } |
| 1037 | |
| 1038 | /** |
| 1039 | * Writes data to the object referenced by handle. |
| 1040 | * |
| 1041 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1042 | */ |
| 1043 | int |
| 1044 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1045 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1046 | { |
| 1047 | struct drm_i915_gem_pwrite *args = data; |
| 1048 | struct drm_gem_object *obj; |
| 1049 | struct drm_i915_gem_object *obj_priv; |
| 1050 | int ret = 0; |
| 1051 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1052 | ret = i915_mutex_lock_interruptible(dev); |
| 1053 | if (ret) |
| 1054 | return ret; |
| 1055 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1056 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1057 | if (obj == NULL) { |
| 1058 | ret = -ENOENT; |
| 1059 | goto unlock; |
| 1060 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1061 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1062 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1063 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1064 | /* Bounds check destination. */ |
| 1065 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1066 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1067 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1068 | } |
| 1069 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1070 | if (args->size == 0) |
| 1071 | goto out; |
| 1072 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1073 | if (!access_ok(VERIFY_READ, |
| 1074 | (char __user *)(uintptr_t)args->data_ptr, |
| 1075 | args->size)) { |
| 1076 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1077 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1078 | } |
| 1079 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 1080 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1081 | args->size); |
| 1082 | if (ret) { |
| 1083 | ret = -EFAULT; |
| 1084 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1085 | } |
| 1086 | |
| 1087 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1088 | * it would end up going through the fenced access, and we'll get |
| 1089 | * different detiling behavior between reading and writing. |
| 1090 | * pread/pwrite currently are reading and writing from the CPU |
| 1091 | * perspective, requiring manual detiling by the client. |
| 1092 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1093 | if (obj_priv->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1094 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1095 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1096 | obj_priv->gtt_space && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 1097 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 1098 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1099 | if (ret) |
| 1100 | goto out; |
| 1101 | |
| 1102 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1103 | if (ret) |
| 1104 | goto out_unpin; |
| 1105 | |
| 1106 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1107 | if (ret == -EFAULT) |
| 1108 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1109 | |
| 1110 | out_unpin: |
| 1111 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1112 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1113 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 1114 | if (ret) |
| 1115 | goto out; |
| 1116 | |
| 1117 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1118 | if (ret) |
| 1119 | goto out_put; |
| 1120 | |
| 1121 | ret = -EFAULT; |
| 1122 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1123 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1124 | if (ret == -EFAULT) |
| 1125 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
| 1126 | |
| 1127 | out_put: |
| 1128 | i915_gem_object_put_pages(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1129 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1130 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1131 | out: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1132 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1133 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1134 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1135 | return ret; |
| 1136 | } |
| 1137 | |
| 1138 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1139 | * Called when user space prepares to use an object with the CPU, either |
| 1140 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1141 | */ |
| 1142 | int |
| 1143 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1144 | struct drm_file *file_priv) |
| 1145 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1146 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1147 | struct drm_i915_gem_set_domain *args = data; |
| 1148 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1149 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1150 | uint32_t read_domains = args->read_domains; |
| 1151 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1152 | int ret; |
| 1153 | |
| 1154 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1155 | return -ENODEV; |
| 1156 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1157 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1158 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1159 | return -EINVAL; |
| 1160 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1161 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1162 | return -EINVAL; |
| 1163 | |
| 1164 | /* Having something in the write domain implies it's in the read |
| 1165 | * domain, and only that read domain. Enforce that in the request. |
| 1166 | */ |
| 1167 | if (write_domain != 0 && read_domains != write_domain) |
| 1168 | return -EINVAL; |
| 1169 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1170 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1171 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1172 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1173 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1174 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1175 | if (obj == NULL) { |
| 1176 | ret = -ENOENT; |
| 1177 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1178 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1179 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1180 | |
| 1181 | intel_mark_busy(dev, obj); |
| 1182 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1183 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1184 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1185 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1186 | /* Update the LRU on the fence for the CPU access that's |
| 1187 | * about to occur. |
| 1188 | */ |
| 1189 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1190 | struct drm_i915_fence_reg *reg = |
| 1191 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1192 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1193 | &dev_priv->mm.fence_list); |
| 1194 | } |
| 1195 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1196 | /* Silently promote "you're not bound, there was nothing to do" |
| 1197 | * to success, since the client was just asking us to |
| 1198 | * make sure everything was done. |
| 1199 | */ |
| 1200 | if (ret == -EINVAL) |
| 1201 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1202 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1203 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1204 | } |
| 1205 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1206 | /* Maintain LRU order of "inactive" objects */ |
| 1207 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1208 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1209 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1210 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1211 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1212 | mutex_unlock(&dev->struct_mutex); |
| 1213 | return ret; |
| 1214 | } |
| 1215 | |
| 1216 | /** |
| 1217 | * Called when user space has done writes to this buffer |
| 1218 | */ |
| 1219 | int |
| 1220 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1221 | struct drm_file *file_priv) |
| 1222 | { |
| 1223 | struct drm_i915_gem_sw_finish *args = data; |
| 1224 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1225 | int ret = 0; |
| 1226 | |
| 1227 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1228 | return -ENODEV; |
| 1229 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1230 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1231 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1232 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1233 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1234 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1235 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1236 | ret = -ENOENT; |
| 1237 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1238 | } |
| 1239 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1240 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 1241 | if (to_intel_bo(obj)->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1242 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1243 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1244 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1245 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1246 | mutex_unlock(&dev->struct_mutex); |
| 1247 | return ret; |
| 1248 | } |
| 1249 | |
| 1250 | /** |
| 1251 | * Maps the contents of an object, returning the address it is mapped |
| 1252 | * into. |
| 1253 | * |
| 1254 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1255 | * imply a ref on the object itself. |
| 1256 | */ |
| 1257 | int |
| 1258 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1259 | struct drm_file *file_priv) |
| 1260 | { |
| 1261 | struct drm_i915_gem_mmap *args = data; |
| 1262 | struct drm_gem_object *obj; |
| 1263 | loff_t offset; |
| 1264 | unsigned long addr; |
| 1265 | |
| 1266 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1267 | return -ENODEV; |
| 1268 | |
| 1269 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1270 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1271 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1272 | |
| 1273 | offset = args->offset; |
| 1274 | |
| 1275 | down_write(¤t->mm->mmap_sem); |
| 1276 | addr = do_mmap(obj->filp, 0, args->size, |
| 1277 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1278 | args->offset); |
| 1279 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1280 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1281 | if (IS_ERR((void *)addr)) |
| 1282 | return addr; |
| 1283 | |
| 1284 | args->addr_ptr = (uint64_t) addr; |
| 1285 | |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1289 | /** |
| 1290 | * i915_gem_fault - fault a page into the GTT |
| 1291 | * vma: VMA in question |
| 1292 | * vmf: fault info |
| 1293 | * |
| 1294 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1295 | * from userspace. The fault handler takes care of binding the object to |
| 1296 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1297 | * only if needed based on whether the old reg is still valid or the object |
| 1298 | * is tiled) and inserting a new PTE into the faulting process. |
| 1299 | * |
| 1300 | * Note that the faulting process may involve evicting existing objects |
| 1301 | * from the GTT and/or fence registers to make room. So performance may |
| 1302 | * suffer if the GTT working set is large or there are few fence registers |
| 1303 | * left. |
| 1304 | */ |
| 1305 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1306 | { |
| 1307 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1308 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1309 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1310 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1311 | pgoff_t page_offset; |
| 1312 | unsigned long pfn; |
| 1313 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1314 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1315 | |
| 1316 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1317 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1318 | PAGE_SHIFT; |
| 1319 | |
| 1320 | /* Now bind it into the GTT if needed */ |
| 1321 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 1322 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 1323 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
| 1324 | i915_gem_object_unbind(obj); |
| 1325 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1326 | if (!obj_priv->gtt_space) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 1327 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1328 | if (ret) |
| 1329 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1330 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1331 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1332 | if (ret) |
| 1333 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1334 | } |
| 1335 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 1336 | if (!obj_priv->fault_mappable) { |
| 1337 | obj_priv->fault_mappable = true; |
| 1338 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 1339 | } |
| 1340 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1341 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1342 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1343 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1344 | if (ret) |
| 1345 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1346 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1347 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1348 | if (i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1349 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1350 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1351 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1352 | page_offset; |
| 1353 | |
| 1354 | /* Finally, remap it using the new GTT offset */ |
| 1355 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1356 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1357 | mutex_unlock(&dev->struct_mutex); |
| 1358 | |
| 1359 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1360 | case 0: |
| 1361 | case -ERESTARTSYS: |
| 1362 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1363 | case -ENOMEM: |
| 1364 | case -EAGAIN: |
| 1365 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1366 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1367 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1368 | } |
| 1369 | } |
| 1370 | |
| 1371 | /** |
| 1372 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1373 | * @obj: obj in question |
| 1374 | * |
| 1375 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1376 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1377 | * up the object based on the offset and sets up the various memory mapping |
| 1378 | * structures. |
| 1379 | * |
| 1380 | * This routine allocates and attaches a fake offset for @obj. |
| 1381 | */ |
| 1382 | static int |
| 1383 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1384 | { |
| 1385 | struct drm_device *dev = obj->dev; |
| 1386 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1387 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1388 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1389 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1390 | int ret = 0; |
| 1391 | |
| 1392 | /* Set the object up for mmap'ing */ |
| 1393 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1394 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1395 | if (!list->map) |
| 1396 | return -ENOMEM; |
| 1397 | |
| 1398 | map = list->map; |
| 1399 | map->type = _DRM_GEM; |
| 1400 | map->size = obj->size; |
| 1401 | map->handle = obj; |
| 1402 | |
| 1403 | /* Get a DRM GEM mmap offset allocated... */ |
| 1404 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1405 | obj->size / PAGE_SIZE, 0, 0); |
| 1406 | if (!list->file_offset_node) { |
| 1407 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1408 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1409 | goto out_free_list; |
| 1410 | } |
| 1411 | |
| 1412 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1413 | obj->size / PAGE_SIZE, 0); |
| 1414 | if (!list->file_offset_node) { |
| 1415 | ret = -ENOMEM; |
| 1416 | goto out_free_list; |
| 1417 | } |
| 1418 | |
| 1419 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1420 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1421 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1422 | DRM_ERROR("failed to add to map hash\n"); |
| 1423 | goto out_free_mm; |
| 1424 | } |
| 1425 | |
| 1426 | /* By now we should be all set, any drm_mmap request on the offset |
| 1427 | * below will get to our mmap & fault handler */ |
| 1428 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1429 | |
| 1430 | return 0; |
| 1431 | |
| 1432 | out_free_mm: |
| 1433 | drm_mm_put_block(list->file_offset_node); |
| 1434 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1435 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1436 | |
| 1437 | return ret; |
| 1438 | } |
| 1439 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1440 | /** |
| 1441 | * i915_gem_release_mmap - remove physical page mappings |
| 1442 | * @obj: obj in question |
| 1443 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1444 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1445 | * relinquish ownership of the pages back to the system. |
| 1446 | * |
| 1447 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1448 | * object through the GTT and then lose the fence register due to |
| 1449 | * resource pressure. Similarly if the object has been moved out of the |
| 1450 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1451 | * mapping will then trigger a page fault on the next user access, allowing |
| 1452 | * fixup by i915_gem_fault(). |
| 1453 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1454 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1455 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1456 | { |
| 1457 | struct drm_device *dev = obj->dev; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 1458 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1459 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1460 | |
| 1461 | if (dev->dev_mapping) |
| 1462 | unmap_mapping_range(dev->dev_mapping, |
| 1463 | obj_priv->mmap_offset, obj->size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 1464 | |
| 1465 | if (obj_priv->fault_mappable) { |
| 1466 | obj_priv->fault_mappable = false; |
| 1467 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 1468 | } |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1469 | } |
| 1470 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1471 | static void |
| 1472 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1473 | { |
| 1474 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1475 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1476 | struct drm_gem_mm *mm = dev->mm_private; |
| 1477 | struct drm_map_list *list; |
| 1478 | |
| 1479 | list = &obj->map_list; |
| 1480 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1481 | |
| 1482 | if (list->file_offset_node) { |
| 1483 | drm_mm_put_block(list->file_offset_node); |
| 1484 | list->file_offset_node = NULL; |
| 1485 | } |
| 1486 | |
| 1487 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1488 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1489 | list->map = NULL; |
| 1490 | } |
| 1491 | |
| 1492 | obj_priv->mmap_offset = 0; |
| 1493 | } |
| 1494 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1495 | /** |
| 1496 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1497 | * @obj: object to check |
| 1498 | * |
| 1499 | * Return the required GTT alignment for an object, taking into account |
| 1500 | * potential fence register mapping if needed. |
| 1501 | */ |
| 1502 | static uint32_t |
| 1503 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1504 | { |
| 1505 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1506 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1507 | int start, i; |
| 1508 | |
| 1509 | /* |
| 1510 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1511 | * if a fence register is needed for the object. |
| 1512 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1513 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1514 | return 4096; |
| 1515 | |
| 1516 | /* |
| 1517 | * Previous chips need to be aligned to the size of the smallest |
| 1518 | * fence register that can contain the object. |
| 1519 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1520 | if (INTEL_INFO(dev)->gen == 3) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1521 | start = 1024*1024; |
| 1522 | else |
| 1523 | start = 512*1024; |
| 1524 | |
| 1525 | for (i = start; i < obj->size; i <<= 1) |
| 1526 | ; |
| 1527 | |
| 1528 | return i; |
| 1529 | } |
| 1530 | |
| 1531 | /** |
| 1532 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1533 | * @dev: DRM device |
| 1534 | * @data: GTT mapping ioctl data |
| 1535 | * @file_priv: GEM object info |
| 1536 | * |
| 1537 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1538 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1539 | * up so we can get faults in the handler above. |
| 1540 | * |
| 1541 | * The fault handler will take care of binding the object into the GTT |
| 1542 | * (since it may have been evicted to make room for something), allocating |
| 1543 | * a fence register, and mapping the appropriate aperture address into |
| 1544 | * userspace. |
| 1545 | */ |
| 1546 | int |
| 1547 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1548 | struct drm_file *file_priv) |
| 1549 | { |
| 1550 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1551 | struct drm_gem_object *obj; |
| 1552 | struct drm_i915_gem_object *obj_priv; |
| 1553 | int ret; |
| 1554 | |
| 1555 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1556 | return -ENODEV; |
| 1557 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1558 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1559 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1560 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1561 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1562 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1563 | if (obj == NULL) { |
| 1564 | ret = -ENOENT; |
| 1565 | goto unlock; |
| 1566 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1567 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1568 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1569 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1570 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1571 | ret = -EINVAL; |
| 1572 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1573 | } |
| 1574 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1575 | if (!obj_priv->mmap_offset) { |
| 1576 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1577 | if (ret) |
| 1578 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1579 | } |
| 1580 | |
| 1581 | args->offset = obj_priv->mmap_offset; |
| 1582 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1583 | /* |
| 1584 | * Pull it into the GTT so that we have a page list (makes the |
| 1585 | * initial fault faster and any subsequent flushing possible). |
| 1586 | */ |
| 1587 | if (!obj_priv->agp_mem) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 1588 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1589 | if (ret) |
| 1590 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1591 | } |
| 1592 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1593 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1594 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1595 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1596 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1597 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1598 | } |
| 1599 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1600 | static void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1601 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1602 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1603 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1604 | int page_count = obj->size / PAGE_SIZE; |
| 1605 | int i; |
| 1606 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1607 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1608 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1609 | |
| 1610 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1611 | return; |
| 1612 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1613 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1614 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1615 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1616 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1617 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1618 | |
| 1619 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1620 | if (obj_priv->dirty) |
| 1621 | set_page_dirty(obj_priv->pages[i]); |
| 1622 | |
| 1623 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1624 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1625 | |
| 1626 | page_cache_release(obj_priv->pages[i]); |
| 1627 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1628 | obj_priv->dirty = 0; |
| 1629 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1630 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1631 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1632 | } |
| 1633 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1634 | static uint32_t |
| 1635 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1636 | struct intel_ring_buffer *ring) |
| 1637 | { |
| 1638 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1639 | |
| 1640 | ring->outstanding_lazy_request = true; |
| 1641 | return dev_priv->next_seqno; |
| 1642 | } |
| 1643 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | static void |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1645 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1646 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1647 | { |
| 1648 | struct drm_device *dev = obj->dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1650 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1651 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1652 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1653 | BUG_ON(ring == NULL); |
| 1654 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1655 | |
| 1656 | /* Add a reference if we're newly entering the active list. */ |
| 1657 | if (!obj_priv->active) { |
| 1658 | drm_gem_object_reference(obj); |
| 1659 | obj_priv->active = 1; |
| 1660 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1661 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1662 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1663 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
| 1664 | list_move_tail(&obj_priv->ring_list, &ring->active_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1665 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1666 | } |
| 1667 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1668 | static void |
| 1669 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1670 | { |
| 1671 | struct drm_device *dev = obj->dev; |
| 1672 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1673 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1674 | |
| 1675 | BUG_ON(!obj_priv->active); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1676 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
| 1677 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1678 | obj_priv->last_rendering_seqno = 0; |
| 1679 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1680 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1681 | /* Immediately discard the backing storage */ |
| 1682 | static void |
| 1683 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1684 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1685 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1686 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1687 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1688 | /* Our goal here is to return as much of the memory as |
| 1689 | * is possible back to the system as we are called from OOM. |
| 1690 | * To do this we must instruct the shmfs to drop all of its |
| 1691 | * backing pages, *now*. Here we mirror the actions taken |
| 1692 | * when by shmem_delete_inode() to release the backing store. |
| 1693 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1694 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1695 | truncate_inode_pages(inode->i_mapping, 0); |
| 1696 | if (inode->i_op->truncate_range) |
| 1697 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1698 | |
| 1699 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1700 | } |
| 1701 | |
| 1702 | static inline int |
| 1703 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1704 | { |
| 1705 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1706 | } |
| 1707 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1708 | static void |
| 1709 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1710 | { |
| 1711 | struct drm_device *dev = obj->dev; |
| 1712 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1713 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1715 | if (obj_priv->pin_count != 0) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1716 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1717 | else |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1718 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
| 1719 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1720 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1721 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1722 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1723 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1724 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1725 | if (obj_priv->active) { |
| 1726 | obj_priv->active = 0; |
| 1727 | drm_gem_object_unreference(obj); |
| 1728 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1729 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | } |
| 1731 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1732 | static void |
| 1733 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1734 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1735 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1736 | { |
| 1737 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1738 | struct drm_i915_gem_object *obj_priv, *next; |
| 1739 | |
| 1740 | list_for_each_entry_safe(obj_priv, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1741 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1742 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1743 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1744 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1745 | if (obj->write_domain & flush_domains) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1746 | uint32_t old_write_domain = obj->write_domain; |
| 1747 | |
| 1748 | obj->write_domain = 0; |
| 1749 | list_del_init(&obj_priv->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1750 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1751 | |
| 1752 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1753 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1754 | struct drm_i915_fence_reg *reg = |
| 1755 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1756 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1757 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1758 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1759 | |
| 1760 | trace_i915_gem_object_change_domain(obj, |
| 1761 | obj->read_domains, |
| 1762 | old_write_domain); |
| 1763 | } |
| 1764 | } |
| 1765 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1766 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1767 | int |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1768 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1769 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1770 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1771 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1772 | { |
| 1773 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1774 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1775 | uint32_t seqno; |
| 1776 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1777 | int ret; |
| 1778 | |
| 1779 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1780 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1781 | if (file != NULL) |
| 1782 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1783 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1784 | ret = ring->add_request(ring, &seqno); |
| 1785 | if (ret) |
| 1786 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1787 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1788 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1789 | |
| 1790 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1791 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1792 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1793 | was_empty = list_empty(&ring->request_list); |
| 1794 | list_add_tail(&request->list, &ring->request_list); |
| 1795 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1796 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1797 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1798 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1799 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1800 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1801 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1802 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1803 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1804 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1805 | mod_timer(&dev_priv->hangcheck_timer, |
| 1806 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1807 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1808 | queue_delayed_work(dev_priv->wq, |
| 1809 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1810 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1811 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1812 | } |
| 1813 | |
| 1814 | /** |
| 1815 | * Command execution barrier |
| 1816 | * |
| 1817 | * Ensures that all commands in the ring are finished |
| 1818 | * before signalling the CPU |
| 1819 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1820 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1821 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1822 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1823 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | |
| 1825 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1826 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1827 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1828 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1829 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1830 | } |
| 1831 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1832 | static inline void |
| 1833 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1834 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1835 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1836 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1837 | if (!file_priv) |
| 1838 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1839 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1840 | spin_lock(&file_priv->mm.lock); |
| 1841 | list_del(&request->client_list); |
| 1842 | request->file_priv = NULL; |
| 1843 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1844 | } |
| 1845 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1846 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1847 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1848 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1849 | while (!list_empty(&ring->request_list)) { |
| 1850 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1851 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1852 | request = list_first_entry(&ring->request_list, |
| 1853 | struct drm_i915_gem_request, |
| 1854 | list); |
| 1855 | |
| 1856 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1857 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1858 | kfree(request); |
| 1859 | } |
| 1860 | |
| 1861 | while (!list_empty(&ring->active_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1862 | struct drm_i915_gem_object *obj_priv; |
| 1863 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1864 | obj_priv = list_first_entry(&ring->active_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1865 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1866 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1867 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1868 | obj_priv->base.write_domain = 0; |
| 1869 | list_del_init(&obj_priv->gpu_write_list); |
| 1870 | i915_gem_object_move_to_inactive(&obj_priv->base); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1871 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1872 | } |
| 1873 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1874 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1875 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1877 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1878 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1879 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1880 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1881 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1882 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1883 | |
| 1884 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1885 | * to be lost on reset along with the data, so simply move the |
| 1886 | * lost bo to the inactive list. |
| 1887 | */ |
| 1888 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1889 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1890 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1891 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1892 | |
| 1893 | obj_priv->base.write_domain = 0; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1894 | list_del_init(&obj_priv->gpu_write_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1895 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1896 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1897 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1898 | /* Move everything out of the GPU domains to ensure we do any |
| 1899 | * necessary invalidation upon reuse. |
| 1900 | */ |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1901 | list_for_each_entry(obj_priv, |
| 1902 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1903 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1904 | { |
| 1905 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 1906 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1907 | |
| 1908 | /* The fence registers are invalidated so clear them out */ |
| 1909 | for (i = 0; i < 16; i++) { |
| 1910 | struct drm_i915_fence_reg *reg; |
| 1911 | |
| 1912 | reg = &dev_priv->fence_regs[i]; |
| 1913 | if (!reg->obj) |
| 1914 | continue; |
| 1915 | |
| 1916 | i915_gem_clear_fence_reg(reg->obj); |
| 1917 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1918 | } |
| 1919 | |
| 1920 | /** |
| 1921 | * This function clears the request list as sequence numbers are passed. |
| 1922 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1923 | static void |
| 1924 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1925 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1926 | { |
| 1927 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1928 | uint32_t seqno; |
| 1929 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1930 | if (!ring->status_page.page_addr || |
| 1931 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1932 | return; |
| 1933 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1934 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1935 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1936 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1937 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1938 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1939 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1940 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1941 | struct drm_i915_gem_request, |
| 1942 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1943 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1944 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1945 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1946 | |
| 1947 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1948 | |
| 1949 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1950 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1951 | kfree(request); |
| 1952 | } |
| 1953 | |
| 1954 | /* Move any buffers on the active list that are no longer referenced |
| 1955 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1956 | */ |
| 1957 | while (!list_empty(&ring->active_list)) { |
| 1958 | struct drm_gem_object *obj; |
| 1959 | struct drm_i915_gem_object *obj_priv; |
| 1960 | |
| 1961 | obj_priv = list_first_entry(&ring->active_list, |
| 1962 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1963 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1964 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1965 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1966 | break; |
| 1967 | |
| 1968 | obj = &obj_priv->base; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1969 | if (obj->write_domain != 0) |
| 1970 | i915_gem_object_move_to_flushing(obj); |
| 1971 | else |
| 1972 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1973 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1974 | |
| 1975 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1976 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1977 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1978 | dev_priv->trace_irq_seqno = 0; |
| 1979 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1980 | |
| 1981 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1985 | i915_gem_retire_requests(struct drm_device *dev) |
| 1986 | { |
| 1987 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1988 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1989 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 1990 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 1991 | |
| 1992 | /* We must be careful that during unbind() we do not |
| 1993 | * accidentally infinitely recurse into retire requests. |
| 1994 | * Currently: |
| 1995 | * retire -> free -> unbind -> wait -> retire_ring |
| 1996 | */ |
| 1997 | list_for_each_entry_safe(obj_priv, tmp, |
| 1998 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1999 | mm_list) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2000 | i915_gem_free_object_tail(&obj_priv->base); |
| 2001 | } |
| 2002 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2003 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2004 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2005 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2006 | } |
| 2007 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2008 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2009 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2010 | { |
| 2011 | drm_i915_private_t *dev_priv; |
| 2012 | struct drm_device *dev; |
| 2013 | |
| 2014 | dev_priv = container_of(work, drm_i915_private_t, |
| 2015 | mm.retire_work.work); |
| 2016 | dev = dev_priv->dev; |
| 2017 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2018 | /* Come back later if the device is busy... */ |
| 2019 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 2020 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 2021 | return; |
| 2022 | } |
| 2023 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2024 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2025 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2026 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2027 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2028 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 2029 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2030 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2031 | mutex_unlock(&dev->struct_mutex); |
| 2032 | } |
| 2033 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2034 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2035 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2036 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2037 | { |
| 2038 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2039 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2040 | int ret = 0; |
| 2041 | |
| 2042 | BUG_ON(seqno == 0); |
| 2043 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2044 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2045 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 2046 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2047 | if (ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2048 | struct drm_i915_gem_request *request; |
| 2049 | |
| 2050 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2051 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2052 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2053 | |
| 2054 | ret = i915_add_request(dev, NULL, request, ring); |
| 2055 | if (ret) { |
| 2056 | kfree(request); |
| 2057 | return ret; |
| 2058 | } |
| 2059 | |
| 2060 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2061 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2062 | BUG_ON(seqno == dev_priv->next_seqno); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2063 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2064 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2065 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2066 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2067 | else |
| 2068 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2069 | if (!ier) { |
| 2070 | DRM_ERROR("something (likely vbetool) disabled " |
| 2071 | "interrupts, re-enabling\n"); |
| 2072 | i915_driver_irq_preinstall(dev); |
| 2073 | i915_driver_irq_postinstall(dev); |
| 2074 | } |
| 2075 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2076 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2077 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2078 | ring->waiting_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2079 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2080 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2081 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2082 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2083 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2084 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2085 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2086 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2087 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2088 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2089 | ring->user_irq_put(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2090 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2091 | |
| 2092 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2093 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2094 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2095 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2096 | |
| 2097 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2098 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2099 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2100 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2101 | |
| 2102 | /* Directly dispatch request retiring. While we have the work queue |
| 2103 | * to handle this, the waiter on a request often wants an associated |
| 2104 | * buffer to have made it to the inactive list, and we would need |
| 2105 | * a separate wait queue to handle that. |
| 2106 | */ |
| 2107 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2108 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2109 | |
| 2110 | return ret; |
| 2111 | } |
| 2112 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2113 | /** |
| 2114 | * Waits for a sequence number to be signaled, and cleans up the |
| 2115 | * request and object lists appropriately for that event. |
| 2116 | */ |
| 2117 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2118 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2119 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2120 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2121 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2122 | } |
| 2123 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2124 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2125 | i915_gem_flush_ring(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2126 | struct drm_file *file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2127 | struct intel_ring_buffer *ring, |
| 2128 | uint32_t invalidate_domains, |
| 2129 | uint32_t flush_domains) |
| 2130 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2131 | ring->flush(ring, invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2132 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2133 | } |
| 2134 | |
| 2135 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2136 | i915_gem_flush(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2137 | struct drm_file *file_priv, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2138 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2139 | uint32_t flush_domains, |
| 2140 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2141 | { |
| 2142 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2143 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2144 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 2145 | drm_agp_chipset_flush(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2146 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2147 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2148 | if (flush_rings & RING_RENDER) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2149 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2150 | &dev_priv->render_ring, |
| 2151 | invalidate_domains, flush_domains); |
| 2152 | if (flush_rings & RING_BSD) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2153 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2154 | &dev_priv->bsd_ring, |
| 2155 | invalidate_domains, flush_domains); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2156 | if (flush_rings & RING_BLT) |
| 2157 | i915_gem_flush_ring(dev, file_priv, |
| 2158 | &dev_priv->blt_ring, |
| 2159 | invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2160 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2161 | } |
| 2162 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2163 | /** |
| 2164 | * Ensures that all rendering to the object has completed and the object is |
| 2165 | * safe to unbind from the GTT or access from the CPU. |
| 2166 | */ |
| 2167 | static int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2168 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 2169 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2170 | { |
| 2171 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2172 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2173 | int ret; |
| 2174 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2175 | /* This function only exists to support waiting for existing rendering, |
| 2176 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2177 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2178 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2179 | |
| 2180 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2181 | * it. |
| 2182 | */ |
| 2183 | if (obj_priv->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2184 | ret = i915_do_wait_request(dev, |
| 2185 | obj_priv->last_rendering_seqno, |
| 2186 | interruptible, |
| 2187 | obj_priv->ring); |
| 2188 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | return ret; |
| 2190 | } |
| 2191 | |
| 2192 | return 0; |
| 2193 | } |
| 2194 | |
| 2195 | /** |
| 2196 | * Unbinds an object from the GTT aperture. |
| 2197 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2198 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2199 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 2200 | { |
| 2201 | struct drm_device *dev = obj->dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2202 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2203 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2204 | int ret = 0; |
| 2205 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2206 | if (obj_priv->gtt_space == NULL) |
| 2207 | return 0; |
| 2208 | |
| 2209 | if (obj_priv->pin_count != 0) { |
| 2210 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2211 | return -EINVAL; |
| 2212 | } |
| 2213 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2214 | /* blow away mappings if mapped through GTT */ |
| 2215 | i915_gem_release_mmap(obj); |
| 2216 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2217 | /* Move the object to the CPU domain to ensure that |
| 2218 | * any possible CPU writes while it's not in the GTT |
| 2219 | * are flushed when we go to remap it. This will |
| 2220 | * also ensure that all pending GPU writes are finished |
| 2221 | * before we unbind. |
| 2222 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2223 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2224 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2225 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2226 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2227 | * should be safe and we need to cleanup or else we might |
| 2228 | * cause memory corruption through use-after-free. |
| 2229 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2230 | if (ret) { |
| 2231 | i915_gem_clflush_object(obj); |
| 2232 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2233 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2234 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2235 | /* release the fence reg _after_ flushing */ |
| 2236 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2237 | i915_gem_clear_fence_reg(obj); |
| 2238 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2239 | drm_unbind_agp(obj_priv->agp_mem); |
| 2240 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2241 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2242 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2243 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2244 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 2245 | i915_gem_info_remove_gtt(dev_priv, obj); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2246 | list_del_init(&obj_priv->mm_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2247 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2248 | drm_mm_put_block(obj_priv->gtt_space); |
| 2249 | obj_priv->gtt_space = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2250 | obj_priv->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2251 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2252 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2253 | i915_gem_object_truncate(obj); |
| 2254 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2255 | trace_i915_gem_object_unbind(obj); |
| 2256 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2257 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2258 | } |
| 2259 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2260 | static int i915_ring_idle(struct drm_device *dev, |
| 2261 | struct intel_ring_buffer *ring) |
| 2262 | { |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2263 | if (list_empty(&ring->gpu_write_list)) |
| 2264 | return 0; |
| 2265 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2266 | i915_gem_flush_ring(dev, NULL, ring, |
| 2267 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2268 | return i915_wait_request(dev, |
| 2269 | i915_gem_next_request_seqno(dev, ring), |
| 2270 | ring); |
| 2271 | } |
| 2272 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2273 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2274 | i915_gpu_idle(struct drm_device *dev) |
| 2275 | { |
| 2276 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2277 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2278 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2279 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2280 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2281 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2282 | list_empty(&dev_priv->bsd_ring.active_list) && |
| 2283 | list_empty(&dev_priv->blt_ring.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2284 | if (lists_empty) |
| 2285 | return 0; |
| 2286 | |
| 2287 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2288 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2289 | if (ret) |
| 2290 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2291 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2292 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2293 | if (ret) |
| 2294 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2295 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2296 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2297 | if (ret) |
| 2298 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2299 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2300 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2301 | } |
| 2302 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2303 | static int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2304 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2305 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2306 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2307 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2308 | int page_count, i; |
| 2309 | struct address_space *mapping; |
| 2310 | struct inode *inode; |
| 2311 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2312 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2313 | BUG_ON(obj_priv->pages_refcount |
| 2314 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2315 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2316 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2317 | return 0; |
| 2318 | |
| 2319 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2320 | * at this point until we release them. |
| 2321 | */ |
| 2322 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2323 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2324 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2325 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2326 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2327 | return -ENOMEM; |
| 2328 | } |
| 2329 | |
| 2330 | inode = obj->filp->f_path.dentry->d_inode; |
| 2331 | mapping = inode->i_mapping; |
| 2332 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2333 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2334 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2335 | __GFP_COLD | |
Linus Torvalds | cd9f040 | 2010-07-18 09:44:37 -0700 | [diff] [blame] | 2336 | __GFP_RECLAIMABLE | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2337 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2338 | if (IS_ERR(page)) |
| 2339 | goto err_pages; |
| 2340 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2341 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2342 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2343 | |
| 2344 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2345 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2346 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2347 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2348 | |
| 2349 | err_pages: |
| 2350 | while (i--) |
| 2351 | page_cache_release(obj_priv->pages[i]); |
| 2352 | |
| 2353 | drm_free_large(obj_priv->pages); |
| 2354 | obj_priv->pages = NULL; |
| 2355 | obj_priv->pages_refcount--; |
| 2356 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2357 | } |
| 2358 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2359 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2360 | { |
| 2361 | struct drm_gem_object *obj = reg->obj; |
| 2362 | struct drm_device *dev = obj->dev; |
| 2363 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2365 | int regnum = obj_priv->fence_reg; |
| 2366 | uint64_t val; |
| 2367 | |
| 2368 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2369 | 0xfffff000) << 32; |
| 2370 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2371 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2372 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2373 | |
| 2374 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2375 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2376 | val |= I965_FENCE_REG_VALID; |
| 2377 | |
| 2378 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2379 | } |
| 2380 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2381 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2382 | { |
| 2383 | struct drm_gem_object *obj = reg->obj; |
| 2384 | struct drm_device *dev = obj->dev; |
| 2385 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2386 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2387 | int regnum = obj_priv->fence_reg; |
| 2388 | uint64_t val; |
| 2389 | |
| 2390 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2391 | 0xfffff000) << 32; |
| 2392 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2393 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2394 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2395 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2396 | val |= I965_FENCE_REG_VALID; |
| 2397 | |
| 2398 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2399 | } |
| 2400 | |
| 2401 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2402 | { |
| 2403 | struct drm_gem_object *obj = reg->obj; |
| 2404 | struct drm_device *dev = obj->dev; |
| 2405 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2406 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2407 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2408 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2409 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2410 | uint32_t pitch_val; |
| 2411 | |
| 2412 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2413 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2414 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2415 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2416 | return; |
| 2417 | } |
| 2418 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2419 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2420 | HAS_128_BYTE_Y_TILING(dev)) |
| 2421 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2422 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2423 | tile_width = 512; |
| 2424 | |
| 2425 | /* Note: pitch better be a power of two tile widths */ |
| 2426 | pitch_val = obj_priv->stride / tile_width; |
| 2427 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2428 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2429 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2430 | HAS_128_BYTE_Y_TILING(dev)) |
| 2431 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2432 | else |
| 2433 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2434 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2435 | val = obj_priv->gtt_offset; |
| 2436 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2437 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2438 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2439 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2440 | val |= I830_FENCE_REG_VALID; |
| 2441 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2442 | if (regnum < 8) |
| 2443 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2444 | else |
| 2445 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2446 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2447 | } |
| 2448 | |
| 2449 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2450 | { |
| 2451 | struct drm_gem_object *obj = reg->obj; |
| 2452 | struct drm_device *dev = obj->dev; |
| 2453 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2454 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2455 | int regnum = obj_priv->fence_reg; |
| 2456 | uint32_t val; |
| 2457 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2458 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2459 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2460 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2461 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2462 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2463 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2464 | return; |
| 2465 | } |
| 2466 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2467 | pitch_val = obj_priv->stride / 128; |
| 2468 | pitch_val = ffs(pitch_val) - 1; |
| 2469 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2470 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2471 | val = obj_priv->gtt_offset; |
| 2472 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2473 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2474 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2475 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2476 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2477 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2478 | val |= I830_FENCE_REG_VALID; |
| 2479 | |
| 2480 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2481 | } |
| 2482 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2483 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2484 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2485 | { |
| 2486 | struct drm_i915_fence_reg *reg = NULL; |
| 2487 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2488 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2489 | struct drm_gem_object *obj = NULL; |
| 2490 | int i, avail, ret; |
| 2491 | |
| 2492 | /* First try to find a free reg */ |
| 2493 | avail = 0; |
| 2494 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2495 | reg = &dev_priv->fence_regs[i]; |
| 2496 | if (!reg->obj) |
| 2497 | return i; |
| 2498 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2499 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2500 | if (!obj_priv->pin_count) |
| 2501 | avail++; |
| 2502 | } |
| 2503 | |
| 2504 | if (avail == 0) |
| 2505 | return -ENOSPC; |
| 2506 | |
| 2507 | /* None available, try to steal one or wait for a user to finish */ |
| 2508 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2509 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2510 | lru_list) { |
| 2511 | obj = reg->obj; |
| 2512 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2513 | |
| 2514 | if (obj_priv->pin_count) |
| 2515 | continue; |
| 2516 | |
| 2517 | /* found one! */ |
| 2518 | i = obj_priv->fence_reg; |
| 2519 | break; |
| 2520 | } |
| 2521 | |
| 2522 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2523 | |
| 2524 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2525 | * might drop that one, causing a use-after-free in it. So hold a |
| 2526 | * private reference to obj like the other callers of put_fence_reg |
| 2527 | * (set_tiling ioctl) do. */ |
| 2528 | drm_gem_object_reference(obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2529 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2530 | drm_gem_object_unreference(obj); |
| 2531 | if (ret != 0) |
| 2532 | return ret; |
| 2533 | |
| 2534 | return i; |
| 2535 | } |
| 2536 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2537 | /** |
| 2538 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2539 | * @obj: object to map through a fence reg |
| 2540 | * |
| 2541 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2542 | * to them without having to worry about swizzling if the object is tiled. |
| 2543 | * |
| 2544 | * This function walks the fence regs looking for a free one for @obj, |
| 2545 | * stealing one if it can't find any. |
| 2546 | * |
| 2547 | * It then sets up the reg based on the object's properties: address, pitch |
| 2548 | * and tiling format. |
| 2549 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2550 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2551 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
| 2552 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2553 | { |
| 2554 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2555 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2556 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2557 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2558 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2559 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2560 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2561 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2562 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2563 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2564 | return 0; |
| 2565 | } |
| 2566 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2567 | switch (obj_priv->tiling_mode) { |
| 2568 | case I915_TILING_NONE: |
| 2569 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2570 | break; |
| 2571 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2572 | if (!obj_priv->stride) |
| 2573 | return -EINVAL; |
| 2574 | WARN((obj_priv->stride & (512 - 1)), |
| 2575 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2576 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2577 | break; |
| 2578 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2579 | if (!obj_priv->stride) |
| 2580 | return -EINVAL; |
| 2581 | WARN((obj_priv->stride & (128 - 1)), |
| 2582 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2583 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2584 | break; |
| 2585 | } |
| 2586 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2587 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2588 | if (ret < 0) |
| 2589 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2590 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2591 | obj_priv->fence_reg = ret; |
| 2592 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2593 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2594 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2595 | reg->obj = obj; |
| 2596 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2597 | switch (INTEL_INFO(dev)->gen) { |
| 2598 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2599 | sandybridge_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2600 | break; |
| 2601 | case 5: |
| 2602 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2603 | i965_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2604 | break; |
| 2605 | case 3: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2606 | i915_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2607 | break; |
| 2608 | case 2: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2609 | i830_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2610 | break; |
| 2611 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2612 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2613 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2614 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2615 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2616 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2617 | } |
| 2618 | |
| 2619 | /** |
| 2620 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2621 | * @obj: object to clear |
| 2622 | * |
| 2623 | * Zeroes out the fence register itself and clears out the associated |
| 2624 | * data structures in dev_priv and obj_priv. |
| 2625 | */ |
| 2626 | static void |
| 2627 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2628 | { |
| 2629 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2630 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2631 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2632 | struct drm_i915_fence_reg *reg = |
| 2633 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2634 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2635 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2636 | switch (INTEL_INFO(dev)->gen) { |
| 2637 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2638 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2639 | (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2640 | break; |
| 2641 | case 5: |
| 2642 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2643 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2644 | break; |
| 2645 | case 3: |
Chris Wilson | 9b74f73 | 2010-09-22 19:10:44 +0100 | [diff] [blame] | 2646 | if (obj_priv->fence_reg >= 8) |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2647 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2648 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2649 | case 2: |
| 2650 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2651 | |
| 2652 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2653 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2654 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2655 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2656 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2657 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2658 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2659 | } |
| 2660 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2661 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2662 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2663 | * to the buffer to finish, and then resets the fence register. |
| 2664 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2665 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2666 | * |
| 2667 | * Zeroes out the fence register itself and clears out the associated |
| 2668 | * data structures in dev_priv and obj_priv. |
| 2669 | */ |
| 2670 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2671 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
| 2672 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2673 | { |
| 2674 | struct drm_device *dev = obj->dev; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2675 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2676 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2677 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2678 | |
| 2679 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2680 | return 0; |
| 2681 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2682 | /* If we've changed tiling, GTT-mappings of the object |
| 2683 | * need to re-fault to ensure that the correct fence register |
| 2684 | * setup is in place. |
| 2685 | */ |
| 2686 | i915_gem_release_mmap(obj); |
| 2687 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2688 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2689 | * therefore we must wait for any outstanding access to complete |
| 2690 | * before clearing the fence. |
| 2691 | */ |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2692 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2693 | if (reg->gpu) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2694 | int ret; |
| 2695 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2696 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2697 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2698 | return ret; |
| 2699 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2700 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2701 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2702 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2703 | |
| 2704 | reg->gpu = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2705 | } |
| 2706 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2707 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2708 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2709 | |
| 2710 | return 0; |
| 2711 | } |
| 2712 | |
| 2713 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2714 | * Finds free space in the GTT aperture and binds the object there. |
| 2715 | */ |
| 2716 | static int |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2717 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 2718 | unsigned alignment, |
| 2719 | bool mappable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2720 | { |
| 2721 | struct drm_device *dev = obj->dev; |
| 2722 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2723 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2724 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2725 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2726 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2728 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2729 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2730 | return -EINVAL; |
| 2731 | } |
| 2732 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2734 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2735 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2736 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2737 | return -EINVAL; |
| 2738 | } |
| 2739 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2740 | /* If the object is bigger than the entire aperture, reject it early |
| 2741 | * before evicting everything in a vain attempt to find space. |
| 2742 | */ |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2743 | if (obj->size > |
| 2744 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2745 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2746 | return -E2BIG; |
| 2747 | } |
| 2748 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2749 | search_free: |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2750 | if (mappable) |
| 2751 | free_space = |
| 2752 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
| 2753 | obj->size, alignment, 0, |
| 2754 | dev_priv->mm.gtt_mappable_end, |
| 2755 | 0); |
| 2756 | else |
| 2757 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2758 | obj->size, alignment, 0); |
| 2759 | |
| 2760 | if (free_space != NULL) { |
| 2761 | if (mappable) |
| 2762 | obj_priv->gtt_space = |
| 2763 | drm_mm_get_block_range_generic(free_space, |
| 2764 | obj->size, |
| 2765 | alignment, 0, |
| 2766 | dev_priv->mm.gtt_mappable_end, |
| 2767 | 0); |
| 2768 | else |
| 2769 | obj_priv->gtt_space = |
| 2770 | drm_mm_get_block(free_space, obj->size, |
| 2771 | alignment); |
| 2772 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2773 | if (obj_priv->gtt_space == NULL) { |
| 2774 | /* If the gtt is empty and we're still having trouble |
| 2775 | * fitting our object in, we're out of memory. |
| 2776 | */ |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2777 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
| 2778 | mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2779 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2780 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2781 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2782 | goto search_free; |
| 2783 | } |
| 2784 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2785 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2786 | if (ret) { |
| 2787 | drm_mm_put_block(obj_priv->gtt_space); |
| 2788 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2789 | |
| 2790 | if (ret == -ENOMEM) { |
| 2791 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2792 | ret = i915_gem_evict_something(dev, obj->size, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2793 | alignment, mappable); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2794 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2795 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2796 | if (gfpmask) { |
| 2797 | gfpmask = 0; |
| 2798 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2799 | } |
| 2800 | |
| 2801 | return ret; |
| 2802 | } |
| 2803 | |
| 2804 | goto search_free; |
| 2805 | } |
| 2806 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2807 | return ret; |
| 2808 | } |
| 2809 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2810 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2811 | * into the GTT. |
| 2812 | */ |
| 2813 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2814 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2815 | obj->size >> PAGE_SHIFT, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2816 | obj_priv->gtt_space->start, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2817 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2818 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2819 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2820 | drm_mm_put_block(obj_priv->gtt_space); |
| 2821 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2822 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2823 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
| 2824 | mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2825 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2826 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2827 | |
| 2828 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2829 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2830 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 2831 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2832 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2833 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2834 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 2835 | i915_gem_info_add_gtt(dev_priv, obj); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2836 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2837 | /* Assert that the object is not currently in any GPU domain. As it |
| 2838 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2839 | * a GPU cache |
| 2840 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2841 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2842 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2843 | |
Daniel Vetter | ec57d26 | 2010-09-30 23:42:15 +0200 | [diff] [blame] | 2844 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2845 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2846 | return 0; |
| 2847 | } |
| 2848 | |
| 2849 | void |
| 2850 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2851 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2852 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2853 | |
| 2854 | /* If we don't have a page list set up, then we're not pinned |
| 2855 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2856 | * again at bind time. |
| 2857 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2858 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2859 | return; |
| 2860 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2861 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2862 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2863 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2864 | } |
| 2865 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2866 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2867 | static int |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2868 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 2869 | bool pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2870 | { |
| 2871 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2872 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2873 | |
| 2874 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2875 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2876 | |
| 2877 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2878 | old_write_domain = obj->write_domain; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2879 | i915_gem_flush_ring(dev, NULL, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2880 | to_intel_bo(obj)->ring, |
| 2881 | 0, obj->write_domain); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2882 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2883 | |
| 2884 | trace_i915_gem_object_change_domain(obj, |
| 2885 | obj->read_domains, |
| 2886 | old_write_domain); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2887 | |
| 2888 | if (pipelined) |
| 2889 | return 0; |
| 2890 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2891 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2892 | } |
| 2893 | |
| 2894 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2895 | static void |
| 2896 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2897 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2898 | uint32_t old_write_domain; |
| 2899 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2900 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2901 | return; |
| 2902 | |
| 2903 | /* No actual flushing is required for the GTT write domain. Writes |
| 2904 | * to it immediately go to main memory as far as we know, so there's |
| 2905 | * no chipset flush. It also doesn't land in render cache. |
| 2906 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2907 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2908 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2909 | |
| 2910 | trace_i915_gem_object_change_domain(obj, |
| 2911 | obj->read_domains, |
| 2912 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2913 | } |
| 2914 | |
| 2915 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2916 | static void |
| 2917 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2918 | { |
| 2919 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2920 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2921 | |
| 2922 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2923 | return; |
| 2924 | |
| 2925 | i915_gem_clflush_object(obj); |
| 2926 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2927 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2928 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2929 | |
| 2930 | trace_i915_gem_object_change_domain(obj, |
| 2931 | obj->read_domains, |
| 2932 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2933 | } |
| 2934 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2935 | /** |
| 2936 | * Moves a single object to the GTT read, and possibly write domain. |
| 2937 | * |
| 2938 | * This function returns when the move is complete, including waiting on |
| 2939 | * flushes to occur. |
| 2940 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2941 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2942 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2943 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2944 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2945 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2946 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2947 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2948 | /* Not valid to be called on unbound objects. */ |
| 2949 | if (obj_priv->gtt_space == NULL) |
| 2950 | return -EINVAL; |
| 2951 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2952 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2953 | if (ret != 0) |
| 2954 | return ret; |
| 2955 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2956 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2957 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2958 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2959 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2960 | if (ret) |
| 2961 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2962 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2963 | |
| 2964 | old_write_domain = obj->write_domain; |
| 2965 | old_read_domains = obj->read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2966 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2967 | /* It should now be out of any other write domains, and we can update |
| 2968 | * the domain values for our changes. |
| 2969 | */ |
| 2970 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2971 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2972 | if (write) { |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2973 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2974 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2975 | obj_priv->dirty = 1; |
| 2976 | } |
| 2977 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2978 | trace_i915_gem_object_change_domain(obj, |
| 2979 | old_read_domains, |
| 2980 | old_write_domain); |
| 2981 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2982 | return 0; |
| 2983 | } |
| 2984 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2985 | /* |
| 2986 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2987 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2988 | */ |
| 2989 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2990 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
| 2991 | bool pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2992 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2993 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2994 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2995 | int ret; |
| 2996 | |
| 2997 | /* Not valid to be called on unbound objects. */ |
| 2998 | if (obj_priv->gtt_space == NULL) |
| 2999 | return -EINVAL; |
| 3000 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3001 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 3002 | if (ret) |
| 3003 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3004 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 3005 | /* Currently, we are always called from an non-interruptible context. */ |
| 3006 | if (!pipelined) { |
| 3007 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3008 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3009 | return ret; |
| 3010 | } |
| 3011 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3012 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3013 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3014 | old_read_domains = obj->read_domains; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 3015 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3016 | |
| 3017 | trace_i915_gem_object_change_domain(obj, |
| 3018 | old_read_domains, |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3019 | obj->write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3020 | |
| 3021 | return 0; |
| 3022 | } |
| 3023 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3024 | /** |
| 3025 | * Moves a single object to the CPU read, and possibly write domain. |
| 3026 | * |
| 3027 | * This function returns when the move is complete, including waiting on |
| 3028 | * flushes to occur. |
| 3029 | */ |
| 3030 | static int |
| 3031 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 3032 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3033 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3034 | int ret; |
| 3035 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3036 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3037 | if (ret != 0) |
| 3038 | return ret; |
| 3039 | |
| 3040 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3041 | |
| 3042 | /* If we have a partially-valid cache of the object in the CPU, |
| 3043 | * finish invalidating it and free the per-page flags. |
| 3044 | */ |
| 3045 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 3046 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3047 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 3048 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3049 | if (ret) |
| 3050 | return ret; |
| 3051 | } |
| 3052 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3053 | old_write_domain = obj->write_domain; |
| 3054 | old_read_domains = obj->read_domains; |
| 3055 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | /* Flush the CPU cache if it's still invalid. */ |
| 3057 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 3058 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3059 | |
| 3060 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3061 | } |
| 3062 | |
| 3063 | /* It should now be out of any other write domains, and we can update |
| 3064 | * the domain values for our changes. |
| 3065 | */ |
| 3066 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3067 | |
| 3068 | /* If we're writing through the CPU, then the GPU read domains will |
| 3069 | * need to be invalidated at next use. |
| 3070 | */ |
| 3071 | if (write) { |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 3072 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3073 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 3074 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3075 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3076 | trace_i915_gem_object_change_domain(obj, |
| 3077 | old_read_domains, |
| 3078 | old_write_domain); |
| 3079 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3080 | return 0; |
| 3081 | } |
| 3082 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3083 | /* |
| 3084 | * Set the next domain for the specified object. This |
| 3085 | * may not actually perform the necessary flushing/invaliding though, |
| 3086 | * as that may want to be batched with other set_domain operations |
| 3087 | * |
| 3088 | * This is (we hope) the only really tricky part of gem. The goal |
| 3089 | * is fairly simple -- track which caches hold bits of the object |
| 3090 | * and make sure they remain coherent. A few concrete examples may |
| 3091 | * help to explain how it works. For shorthand, we use the notation |
| 3092 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 3093 | * a pair of read and write domain masks. |
| 3094 | * |
| 3095 | * Case 1: the batch buffer |
| 3096 | * |
| 3097 | * 1. Allocated |
| 3098 | * 2. Written by CPU |
| 3099 | * 3. Mapped to GTT |
| 3100 | * 4. Read by GPU |
| 3101 | * 5. Unmapped from GTT |
| 3102 | * 6. Freed |
| 3103 | * |
| 3104 | * Let's take these a step at a time |
| 3105 | * |
| 3106 | * 1. Allocated |
| 3107 | * Pages allocated from the kernel may still have |
| 3108 | * cache contents, so we set them to (CPU, CPU) always. |
| 3109 | * 2. Written by CPU (using pwrite) |
| 3110 | * The pwrite function calls set_domain (CPU, CPU) and |
| 3111 | * this function does nothing (as nothing changes) |
| 3112 | * 3. Mapped by GTT |
| 3113 | * This function asserts that the object is not |
| 3114 | * currently in any GPU-based read or write domains |
| 3115 | * 4. Read by GPU |
| 3116 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3117 | * As write_domain is zero, this function adds in the |
| 3118 | * current read domains (CPU+COMMAND, 0). |
| 3119 | * flush_domains is set to CPU. |
| 3120 | * invalidate_domains is set to COMMAND |
| 3121 | * clflush is run to get data out of the CPU caches |
| 3122 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3123 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3124 | * 5. Unmapped from GTT |
| 3125 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3126 | * flush_domains and invalidate_domains end up both zero |
| 3127 | * so no flushing/invalidating happens |
| 3128 | * 6. Freed |
| 3129 | * yay, done |
| 3130 | * |
| 3131 | * Case 2: The shared render buffer |
| 3132 | * |
| 3133 | * 1. Allocated |
| 3134 | * 2. Mapped to GTT |
| 3135 | * 3. Read/written by GPU |
| 3136 | * 4. set_domain to (CPU,CPU) |
| 3137 | * 5. Read/written by CPU |
| 3138 | * 6. Read/written by GPU |
| 3139 | * |
| 3140 | * 1. Allocated |
| 3141 | * Same as last example, (CPU, CPU) |
| 3142 | * 2. Mapped to GTT |
| 3143 | * Nothing changes (assertions find that it is not in the GPU) |
| 3144 | * 3. Read/written by GPU |
| 3145 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3146 | * flush_domains gets CPU |
| 3147 | * invalidate_domains gets GPU |
| 3148 | * clflush (obj) |
| 3149 | * MI_FLUSH and drm_agp_chipset_flush |
| 3150 | * 4. set_domain (CPU, CPU) |
| 3151 | * flush_domains gets GPU |
| 3152 | * invalidate_domains gets CPU |
| 3153 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3154 | * This will include an MI_FLUSH to get the data from GPU |
| 3155 | * to memory |
| 3156 | * clflush (obj) to invalidate the CPU cache |
| 3157 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3158 | * 5. Read/written by CPU |
| 3159 | * cache lines are loaded and dirtied |
| 3160 | * 6. Read written by GPU |
| 3161 | * Same as last GPU access |
| 3162 | * |
| 3163 | * Case 3: The constant buffer |
| 3164 | * |
| 3165 | * 1. Allocated |
| 3166 | * 2. Written by CPU |
| 3167 | * 3. Read by GPU |
| 3168 | * 4. Updated (written) by CPU again |
| 3169 | * 5. Read by GPU |
| 3170 | * |
| 3171 | * 1. Allocated |
| 3172 | * (CPU, CPU) |
| 3173 | * 2. Written by CPU |
| 3174 | * (CPU, CPU) |
| 3175 | * 3. Read by GPU |
| 3176 | * (CPU+RENDER, 0) |
| 3177 | * flush_domains = CPU |
| 3178 | * invalidate_domains = RENDER |
| 3179 | * clflush (obj) |
| 3180 | * MI_FLUSH |
| 3181 | * drm_agp_chipset_flush |
| 3182 | * 4. Updated (written) by CPU again |
| 3183 | * (CPU, CPU) |
| 3184 | * flush_domains = 0 (no previous write domain) |
| 3185 | * invalidate_domains = 0 (no new read domains) |
| 3186 | * 5. Read by GPU |
| 3187 | * (CPU+RENDER, 0) |
| 3188 | * flush_domains = CPU |
| 3189 | * invalidate_domains = RENDER |
| 3190 | * clflush (obj) |
| 3191 | * MI_FLUSH |
| 3192 | * drm_agp_chipset_flush |
| 3193 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3194 | static void |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3195 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
| 3196 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3197 | { |
| 3198 | struct drm_device *dev = obj->dev; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3200 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3201 | uint32_t invalidate_domains = 0; |
| 3202 | uint32_t flush_domains = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3203 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3204 | /* |
| 3205 | * If the object isn't moving to a new write domain, |
| 3206 | * let the object stay in multiple read domains |
| 3207 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3208 | if (obj->pending_write_domain == 0) |
| 3209 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3210 | |
| 3211 | /* |
| 3212 | * Flush the current write domain if |
| 3213 | * the new read domains don't match. Invalidate |
| 3214 | * any read domains which differ from the old |
| 3215 | * write domain |
| 3216 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3217 | if (obj->write_domain && |
| 3218 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3219 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3220 | invalidate_domains |= |
| 3221 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3222 | } |
| 3223 | /* |
| 3224 | * Invalidate any read caches which may have |
| 3225 | * stale data. That is, any new read domains. |
| 3226 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3227 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3228 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3229 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3230 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3231 | /* The actual obj->write_domain will be updated with |
| 3232 | * pending_write_domain after we emit the accumulated flush for all |
| 3233 | * of our domain changes in execbuffers (which clears objects' |
| 3234 | * write_domains). So if we have a current write domain that we |
| 3235 | * aren't changing, set pending_write_domain to that. |
| 3236 | */ |
| 3237 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3238 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3239 | |
| 3240 | dev->invalidate_domains |= invalidate_domains; |
| 3241 | dev->flush_domains |= flush_domains; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3242 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3243 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3244 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
| 3245 | dev_priv->mm.flush_rings |= ring->id; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3246 | } |
| 3247 | |
| 3248 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3249 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3250 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3251 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3252 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3253 | */ |
| 3254 | static void |
| 3255 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3256 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3257 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3258 | |
| 3259 | if (!obj_priv->page_cpu_valid) |
| 3260 | return; |
| 3261 | |
| 3262 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3263 | */ |
| 3264 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3265 | int i; |
| 3266 | |
| 3267 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3268 | if (obj_priv->page_cpu_valid[i]) |
| 3269 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3270 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3271 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3272 | } |
| 3273 | |
| 3274 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3275 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3276 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3277 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3278 | obj_priv->page_cpu_valid = NULL; |
| 3279 | } |
| 3280 | |
| 3281 | /** |
| 3282 | * Set the CPU read domain on a range of the object. |
| 3283 | * |
| 3284 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3285 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3286 | * pages have been flushed, and will be respected by |
| 3287 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3288 | * of the whole object. |
| 3289 | * |
| 3290 | * This function returns when the move is complete, including waiting on |
| 3291 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3292 | */ |
| 3293 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3294 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3295 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3296 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3297 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3298 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3299 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3300 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3301 | if (offset == 0 && size == obj->size) |
| 3302 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3303 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3304 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3305 | if (ret != 0) |
| 3306 | return ret; |
| 3307 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3308 | |
| 3309 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3310 | if (obj_priv->page_cpu_valid == NULL && |
| 3311 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3312 | return 0; |
| 3313 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3314 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3315 | * newly adding I915_GEM_DOMAIN_CPU |
| 3316 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3317 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3318 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3319 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3320 | if (obj_priv->page_cpu_valid == NULL) |
| 3321 | return -ENOMEM; |
| 3322 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3323 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3324 | |
| 3325 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3326 | * perspective. |
| 3327 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3328 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3329 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3330 | if (obj_priv->page_cpu_valid[i]) |
| 3331 | continue; |
| 3332 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3333 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3334 | |
| 3335 | obj_priv->page_cpu_valid[i] = 1; |
| 3336 | } |
| 3337 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3338 | /* It should now be out of any other write domains, and we can update |
| 3339 | * the domain values for our changes. |
| 3340 | */ |
| 3341 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3342 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3343 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3344 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3345 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3346 | trace_i915_gem_object_change_domain(obj, |
| 3347 | old_read_domains, |
| 3348 | obj->write_domain); |
| 3349 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3350 | return 0; |
| 3351 | } |
| 3352 | |
| 3353 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3354 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3355 | */ |
| 3356 | static int |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3357 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
| 3358 | struct drm_file *file_priv, |
| 3359 | struct drm_i915_gem_exec_object2 *entry) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3360 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3361 | struct drm_device *dev = obj->base.dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3362 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3363 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3364 | struct drm_gem_object *target_obj = NULL; |
| 3365 | uint32_t target_handle = 0; |
| 3366 | int i, ret = 0; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3367 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3368 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3369 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3370 | struct drm_i915_gem_relocation_entry reloc; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3371 | uint32_t target_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3372 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3373 | if (__copy_from_user_inatomic(&reloc, |
| 3374 | user_relocs+i, |
| 3375 | sizeof(reloc))) { |
| 3376 | ret = -EFAULT; |
| 3377 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3378 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3379 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3380 | if (reloc.target_handle != target_handle) { |
| 3381 | drm_gem_object_unreference(target_obj); |
| 3382 | |
| 3383 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3384 | reloc.target_handle); |
| 3385 | if (target_obj == NULL) { |
| 3386 | ret = -ENOENT; |
| 3387 | break; |
| 3388 | } |
| 3389 | |
| 3390 | target_handle = reloc.target_handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3391 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3392 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3393 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3394 | #if WATCH_RELOC |
| 3395 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3396 | "read %08x write %08x gtt %08x " |
| 3397 | "presumed %08x delta %08x\n", |
| 3398 | __func__, |
| 3399 | obj, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3400 | (int) reloc.offset, |
| 3401 | (int) reloc.target_handle, |
| 3402 | (int) reloc.read_domains, |
| 3403 | (int) reloc.write_domain, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3404 | (int) target_offset, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3405 | (int) reloc.presumed_offset, |
| 3406 | reloc.delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3407 | #endif |
| 3408 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3409 | /* The target buffer should have appeared before us in the |
| 3410 | * exec_object list, so it should have a GTT space bound by now. |
| 3411 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3412 | if (target_offset == 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3413 | DRM_ERROR("No GTT space found for object %d\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3414 | reloc.target_handle); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3415 | ret = -EINVAL; |
| 3416 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3417 | } |
| 3418 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3419 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3420 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3421 | DRM_ERROR("reloc with multiple write domains: " |
| 3422 | "obj %p target %d offset %d " |
| 3423 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3424 | obj, reloc.target_handle, |
| 3425 | (int) reloc.offset, |
| 3426 | reloc.read_domains, |
| 3427 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3428 | ret = -EINVAL; |
| 3429 | break; |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3430 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3431 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 3432 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3433 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3434 | "obj %p target %d offset %d " |
| 3435 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3436 | obj, reloc.target_handle, |
| 3437 | (int) reloc.offset, |
| 3438 | reloc.read_domains, |
| 3439 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3440 | ret = -EINVAL; |
| 3441 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3442 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3443 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 3444 | reloc.write_domain != target_obj->pending_write_domain) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3445 | DRM_ERROR("Write domain conflict: " |
| 3446 | "obj %p target %d offset %d " |
| 3447 | "new %08x old %08x\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3448 | obj, reloc.target_handle, |
| 3449 | (int) reloc.offset, |
| 3450 | reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3451 | target_obj->pending_write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3452 | ret = -EINVAL; |
| 3453 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3454 | } |
| 3455 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3456 | target_obj->pending_read_domains |= reloc.read_domains; |
Chris Wilson | 878a3c3 | 2010-10-22 10:48:12 +0100 | [diff] [blame] | 3457 | target_obj->pending_write_domain |= reloc.write_domain; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3458 | |
| 3459 | /* If the relocation already has the right value in it, no |
| 3460 | * more work needs to be done. |
| 3461 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3462 | if (target_offset == reloc.presumed_offset) |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3463 | continue; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3464 | |
| 3465 | /* Check that the relocation address is valid... */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3466 | if (reloc.offset > obj->base.size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3467 | DRM_ERROR("Relocation beyond object bounds: " |
| 3468 | "obj %p target %d offset %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3469 | obj, reloc.target_handle, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3470 | (int) reloc.offset, (int) obj->base.size); |
| 3471 | ret = -EINVAL; |
| 3472 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3473 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3474 | if (reloc.offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3475 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3476 | "obj %p target %d offset %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3477 | obj, reloc.target_handle, |
| 3478 | (int) reloc.offset); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3479 | ret = -EINVAL; |
| 3480 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3481 | } |
| 3482 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3483 | /* and points to somewhere within the target object. */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3484 | if (reloc.delta >= target_obj->size) { |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3485 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3486 | "obj %p target %d delta %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3487 | obj, reloc.target_handle, |
| 3488 | (int) reloc.delta, (int) target_obj->size); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3489 | ret = -EINVAL; |
| 3490 | break; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3491 | } |
| 3492 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3493 | reloc.delta += target_offset; |
| 3494 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3495 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
| 3496 | char *vaddr; |
| 3497 | |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3498 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3499 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3500 | kunmap_atomic(vaddr); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3501 | } else { |
| 3502 | uint32_t __iomem *reloc_entry; |
| 3503 | void __iomem *reloc_page; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3504 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3505 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
| 3506 | if (ret) |
| 3507 | break; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3508 | |
| 3509 | /* Map the page containing the relocation we're going to perform. */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3510 | reloc.offset += obj->gtt_offset; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3511 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3512 | reloc.offset & PAGE_MASK); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3513 | reloc_entry = (uint32_t __iomem *) |
| 3514 | (reloc_page + (reloc.offset & ~PAGE_MASK)); |
| 3515 | iowrite32(reloc.delta, reloc_entry); |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3516 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3517 | } |
| 3518 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3519 | /* and update the user's relocation entry */ |
| 3520 | reloc.presumed_offset = target_offset; |
| 3521 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3522 | &reloc.presumed_offset, |
| 3523 | sizeof(reloc.presumed_offset))) { |
| 3524 | ret = -EFAULT; |
| 3525 | break; |
| 3526 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3527 | } |
| 3528 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3529 | drm_gem_object_unreference(target_obj); |
| 3530 | return ret; |
| 3531 | } |
| 3532 | |
| 3533 | static int |
| 3534 | i915_gem_execbuffer_pin(struct drm_device *dev, |
| 3535 | struct drm_file *file, |
| 3536 | struct drm_gem_object **object_list, |
| 3537 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3538 | int count) |
| 3539 | { |
| 3540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3541 | int ret, i, retry; |
| 3542 | |
| 3543 | /* attempt to pin all of the buffers into the GTT */ |
| 3544 | for (retry = 0; retry < 2; retry++) { |
| 3545 | ret = 0; |
| 3546 | for (i = 0; i < count; i++) { |
| 3547 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3548 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3549 | bool need_fence = |
| 3550 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3551 | obj->tiling_mode != I915_TILING_NONE; |
| 3552 | |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3553 | /* g33/pnv can't fence buffers in the unmappable part */ |
| 3554 | bool need_mappable = |
| 3555 | entry->relocation_count ? true : need_fence; |
| 3556 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3557 | /* Check fence reg constraints and rebind if necessary */ |
| 3558 | if (need_fence && |
| 3559 | !i915_gem_object_fence_offset_ok(&obj->base, |
| 3560 | obj->tiling_mode)) { |
| 3561 | ret = i915_gem_object_unbind(&obj->base); |
| 3562 | if (ret) |
| 3563 | break; |
| 3564 | } |
| 3565 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 3566 | ret = i915_gem_object_pin(&obj->base, |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3567 | entry->alignment, |
| 3568 | need_mappable); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3569 | if (ret) |
| 3570 | break; |
| 3571 | |
| 3572 | /* |
| 3573 | * Pre-965 chips need a fence register set up in order |
| 3574 | * to properly handle blits to/from tiled surfaces. |
| 3575 | */ |
| 3576 | if (need_fence) { |
| 3577 | ret = i915_gem_object_get_fence_reg(&obj->base, true); |
| 3578 | if (ret) { |
| 3579 | i915_gem_object_unpin(&obj->base); |
| 3580 | break; |
| 3581 | } |
| 3582 | |
| 3583 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
| 3584 | } |
| 3585 | |
| 3586 | entry->offset = obj->gtt_offset; |
| 3587 | } |
| 3588 | |
| 3589 | while (i--) |
| 3590 | i915_gem_object_unpin(object_list[i]); |
| 3591 | |
| 3592 | if (ret == 0) |
| 3593 | break; |
| 3594 | |
| 3595 | if (ret != -ENOSPC || retry) |
| 3596 | return ret; |
| 3597 | |
| 3598 | ret = i915_gem_evict_everything(dev); |
| 3599 | if (ret) |
| 3600 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3601 | } |
| 3602 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3603 | return 0; |
| 3604 | } |
| 3605 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3606 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3607 | * emitted over 20 msec ago. |
| 3608 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3609 | * Note that if we were to use the current jiffies each time around the loop, |
| 3610 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3611 | * render a frame was over 20ms. |
| 3612 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3613 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3614 | * relatively low latency when blocking on a particular request to finish. |
| 3615 | */ |
| 3616 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3617 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3618 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3619 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3620 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3621 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3622 | struct drm_i915_gem_request *request; |
| 3623 | struct intel_ring_buffer *ring = NULL; |
| 3624 | u32 seqno = 0; |
| 3625 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3626 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3627 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3628 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3629 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3630 | break; |
| 3631 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3632 | ring = request->ring; |
| 3633 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3634 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3635 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3636 | |
| 3637 | if (seqno == 0) |
| 3638 | return 0; |
| 3639 | |
| 3640 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3641 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3642 | /* And wait for the seqno passing without holding any locks and |
| 3643 | * causing extra latency for others. This is safe as the irq |
| 3644 | * generation is designed to be run atomically and so is |
| 3645 | * lockless. |
| 3646 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3647 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3648 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3649 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3650 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3651 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3652 | |
| 3653 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3654 | ret = -EIO; |
| 3655 | } |
| 3656 | |
| 3657 | if (ret == 0) |
| 3658 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3659 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3660 | return ret; |
| 3661 | } |
| 3662 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3663 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3664 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3665 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3666 | { |
| 3667 | uint32_t exec_start, exec_len; |
| 3668 | |
| 3669 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3670 | exec_len = (uint32_t) exec->batch_len; |
| 3671 | |
| 3672 | if ((exec_start | exec_len) & 0x7) |
| 3673 | return -EINVAL; |
| 3674 | |
| 3675 | if (!exec_start) |
| 3676 | return -EINVAL; |
| 3677 | |
| 3678 | return 0; |
| 3679 | } |
| 3680 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3681 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3682 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3683 | int count) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3684 | { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3685 | int i; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3686 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3687 | for (i = 0; i < count; i++) { |
| 3688 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 3689 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3690 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3691 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3692 | return -EFAULT; |
| 3693 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3694 | /* we may also need to update the presumed offsets */ |
| 3695 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3696 | return -EFAULT; |
| 3697 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3698 | if (fault_in_pages_readable(ptr, length)) |
| 3699 | return -EFAULT; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3700 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3701 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3702 | return 0; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3703 | } |
| 3704 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3705 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3706 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3707 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3708 | struct drm_i915_gem_execbuffer2 *args, |
| 3709 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3710 | { |
| 3711 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3712 | struct drm_gem_object **object_list = NULL; |
| 3713 | struct drm_gem_object *batch_obj; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3714 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3715 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3716 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3717 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3718 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3719 | struct intel_ring_buffer *ring = NULL; |
| 3720 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3721 | ret = i915_gem_check_is_wedged(dev); |
| 3722 | if (ret) |
| 3723 | return ret; |
| 3724 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3725 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3726 | if (ret) |
| 3727 | return ret; |
| 3728 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3729 | #if WATCH_EXEC |
| 3730 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3731 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3732 | #endif |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3733 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 3734 | case I915_EXEC_DEFAULT: |
| 3735 | case I915_EXEC_RENDER: |
| 3736 | ring = &dev_priv->render_ring; |
| 3737 | break; |
| 3738 | case I915_EXEC_BSD: |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3739 | if (!HAS_BSD(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3740 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3741 | return -EINVAL; |
| 3742 | } |
| 3743 | ring = &dev_priv->bsd_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3744 | break; |
| 3745 | case I915_EXEC_BLT: |
| 3746 | if (!HAS_BLT(dev)) { |
| 3747 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); |
| 3748 | return -EINVAL; |
| 3749 | } |
| 3750 | ring = &dev_priv->blt_ring; |
| 3751 | break; |
| 3752 | default: |
| 3753 | DRM_ERROR("execbuf with unknown ring: %d\n", |
| 3754 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 3755 | return -EINVAL; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3756 | } |
| 3757 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3758 | if (args->buffer_count < 1) { |
| 3759 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3760 | return -EINVAL; |
| 3761 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3762 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3763 | if (object_list == NULL) { |
| 3764 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | args->buffer_count); |
| 3766 | ret = -ENOMEM; |
| 3767 | goto pre_mutex_err; |
| 3768 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3769 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3770 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3771 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3772 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3773 | if (cliprects == NULL) { |
| 3774 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3775 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3776 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3777 | |
| 3778 | ret = copy_from_user(cliprects, |
| 3779 | (struct drm_clip_rect __user *) |
| 3780 | (uintptr_t) args->cliprects_ptr, |
| 3781 | sizeof(*cliprects) * args->num_cliprects); |
| 3782 | if (ret != 0) { |
| 3783 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3784 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3785 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3786 | goto pre_mutex_err; |
| 3787 | } |
| 3788 | } |
| 3789 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3790 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3791 | if (request == NULL) { |
| 3792 | ret = -ENOMEM; |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3793 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3794 | } |
| 3795 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3796 | ret = i915_mutex_lock_interruptible(dev); |
| 3797 | if (ret) |
| 3798 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3799 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3800 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3801 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3802 | ret = -EBUSY; |
| 3803 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3804 | } |
| 3805 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3806 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3807 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3808 | struct drm_i915_gem_object *obj_priv; |
| 3809 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3810 | object_list[i] = drm_gem_object_lookup(dev, file, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3811 | exec_list[i].handle); |
| 3812 | if (object_list[i] == NULL) { |
| 3813 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3814 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3815 | /* prevent error path from reading uninitialized data */ |
| 3816 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3817 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3818 | goto err; |
| 3819 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3820 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3821 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3822 | if (obj_priv->in_execbuffer) { |
| 3823 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3824 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3825 | /* prevent error path from reading uninitialized data */ |
| 3826 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3827 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3828 | goto err; |
| 3829 | } |
| 3830 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3831 | } |
| 3832 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3833 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
| 3834 | ret = i915_gem_execbuffer_pin(dev, file, |
| 3835 | object_list, exec_list, |
| 3836 | args->buffer_count); |
| 3837 | if (ret) |
| 3838 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3839 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3840 | /* The objects are in their final locations, apply the relocations. */ |
| 3841 | for (i = 0; i < args->buffer_count; i++) { |
| 3842 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
| 3843 | obj->base.pending_read_domains = 0; |
| 3844 | obj->base.pending_write_domain = 0; |
| 3845 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3846 | if (ret) |
| 3847 | goto err; |
| 3848 | } |
| 3849 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3850 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3851 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3852 | if (batch_obj->pending_write_domain) { |
| 3853 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3854 | ret = -EINVAL; |
| 3855 | goto err; |
| 3856 | } |
| 3857 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3858 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3859 | /* Sanity check the batch buffer */ |
| 3860 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; |
| 3861 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3862 | if (ret != 0) { |
| 3863 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3864 | goto err; |
| 3865 | } |
| 3866 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3867 | /* Zero the global flush/invalidate flags. These |
| 3868 | * will be modified as new domains are computed |
| 3869 | * for each object |
| 3870 | */ |
| 3871 | dev->invalidate_domains = 0; |
| 3872 | dev->flush_domains = 0; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3873 | dev_priv->mm.flush_rings = 0; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3874 | for (i = 0; i < args->buffer_count; i++) |
| 3875 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3876 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3877 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3878 | #if WATCH_EXEC |
| 3879 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3880 | __func__, |
| 3881 | dev->invalidate_domains, |
| 3882 | dev->flush_domains); |
| 3883 | #endif |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3884 | i915_gem_flush(dev, file, |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3885 | dev->invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3886 | dev->flush_domains, |
| 3887 | dev_priv->mm.flush_rings); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3888 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3889 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3890 | #if WATCH_COHERENCY |
| 3891 | for (i = 0; i < args->buffer_count; i++) { |
| 3892 | i915_gem_object_check_coherency(object_list[i], |
| 3893 | exec_list[i].handle); |
| 3894 | } |
| 3895 | #endif |
| 3896 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3897 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3898 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3899 | args->batch_len, |
| 3900 | __func__, |
| 3901 | ~0); |
| 3902 | #endif |
| 3903 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3904 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 3905 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 3906 | * to executing the batch and avoid stalling the CPU. |
| 3907 | */ |
| 3908 | flips = 0; |
| 3909 | for (i = 0; i < args->buffer_count; i++) { |
| 3910 | if (object_list[i]->write_domain) |
| 3911 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); |
| 3912 | } |
| 3913 | if (flips) { |
| 3914 | int plane, flip_mask; |
| 3915 | |
| 3916 | for (plane = 0; flips >> plane; plane++) { |
| 3917 | if (((flips >> plane) & 1) == 0) |
| 3918 | continue; |
| 3919 | |
| 3920 | if (plane) |
| 3921 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 3922 | else |
| 3923 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 3924 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 3925 | ret = intel_ring_begin(ring, 2); |
| 3926 | if (ret) |
| 3927 | goto err; |
| 3928 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3929 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 3930 | intel_ring_emit(ring, MI_NOOP); |
| 3931 | intel_ring_advance(ring); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3932 | } |
| 3933 | } |
| 3934 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3935 | /* Exec the batchbuffer */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3936 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3937 | if (ret) { |
| 3938 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3939 | goto err; |
| 3940 | } |
| 3941 | |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3942 | for (i = 0; i < args->buffer_count; i++) { |
| 3943 | struct drm_gem_object *obj = object_list[i]; |
| 3944 | |
| 3945 | obj->read_domains = obj->pending_read_domains; |
| 3946 | obj->write_domain = obj->pending_write_domain; |
| 3947 | |
| 3948 | i915_gem_object_move_to_active(obj, ring); |
| 3949 | if (obj->write_domain) { |
| 3950 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 3951 | obj_priv->dirty = 1; |
| 3952 | list_move_tail(&obj_priv->gpu_write_list, |
| 3953 | &ring->gpu_write_list); |
| 3954 | intel_mark_busy(dev, obj); |
| 3955 | } |
| 3956 | |
| 3957 | trace_i915_gem_object_change_domain(obj, |
| 3958 | obj->read_domains, |
| 3959 | obj->write_domain); |
| 3960 | } |
| 3961 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3962 | /* |
| 3963 | * Ensure that the commands in the batch buffer are |
| 3964 | * finished before the interrupt fires |
| 3965 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3966 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3967 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 3968 | if (i915_add_request(dev, file, request, ring)) |
| 3969 | ring->outstanding_lazy_request = true; |
| 3970 | else |
| 3971 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3972 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3973 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3974 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3975 | if (object_list[i] == NULL) |
| 3976 | break; |
| 3977 | |
| 3978 | to_intel_bo(object_list[i])->in_execbuffer = false; |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3979 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3980 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3981 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3982 | mutex_unlock(&dev->struct_mutex); |
| 3983 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3984 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3985 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3986 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3987 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3988 | |
| 3989 | return ret; |
| 3990 | } |
| 3991 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3992 | /* |
| 3993 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3994 | * list array and passes it to the real function. |
| 3995 | */ |
| 3996 | int |
| 3997 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3998 | struct drm_file *file_priv) |
| 3999 | { |
| 4000 | struct drm_i915_gem_execbuffer *args = data; |
| 4001 | struct drm_i915_gem_execbuffer2 exec2; |
| 4002 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 4003 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4004 | int ret, i; |
| 4005 | |
| 4006 | #if WATCH_EXEC |
| 4007 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4008 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4009 | #endif |
| 4010 | |
| 4011 | if (args->buffer_count < 1) { |
| 4012 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 4013 | return -EINVAL; |
| 4014 | } |
| 4015 | |
| 4016 | /* Copy in the exec list from userland */ |
| 4017 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 4018 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4019 | if (exec_list == NULL || exec2_list == NULL) { |
| 4020 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4021 | args->buffer_count); |
| 4022 | drm_free_large(exec_list); |
| 4023 | drm_free_large(exec2_list); |
| 4024 | return -ENOMEM; |
| 4025 | } |
| 4026 | ret = copy_from_user(exec_list, |
| 4027 | (struct drm_i915_relocation_entry __user *) |
| 4028 | (uintptr_t) args->buffers_ptr, |
| 4029 | sizeof(*exec_list) * args->buffer_count); |
| 4030 | if (ret != 0) { |
| 4031 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4032 | args->buffer_count, ret); |
| 4033 | drm_free_large(exec_list); |
| 4034 | drm_free_large(exec2_list); |
| 4035 | return -EFAULT; |
| 4036 | } |
| 4037 | |
| 4038 | for (i = 0; i < args->buffer_count; i++) { |
| 4039 | exec2_list[i].handle = exec_list[i].handle; |
| 4040 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4041 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4042 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4043 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4044 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4045 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4046 | else |
| 4047 | exec2_list[i].flags = 0; |
| 4048 | } |
| 4049 | |
| 4050 | exec2.buffers_ptr = args->buffers_ptr; |
| 4051 | exec2.buffer_count = args->buffer_count; |
| 4052 | exec2.batch_start_offset = args->batch_start_offset; |
| 4053 | exec2.batch_len = args->batch_len; |
| 4054 | exec2.DR1 = args->DR1; |
| 4055 | exec2.DR4 = args->DR4; |
| 4056 | exec2.num_cliprects = args->num_cliprects; |
| 4057 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4058 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4059 | |
| 4060 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 4061 | if (!ret) { |
| 4062 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4063 | for (i = 0; i < args->buffer_count; i++) |
| 4064 | exec_list[i].offset = exec2_list[i].offset; |
| 4065 | /* ... and back out to userspace */ |
| 4066 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4067 | (uintptr_t) args->buffers_ptr, |
| 4068 | exec_list, |
| 4069 | sizeof(*exec_list) * args->buffer_count); |
| 4070 | if (ret) { |
| 4071 | ret = -EFAULT; |
| 4072 | DRM_ERROR("failed to copy %d exec entries " |
| 4073 | "back to user (%d)\n", |
| 4074 | args->buffer_count, ret); |
| 4075 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4076 | } |
| 4077 | |
| 4078 | drm_free_large(exec_list); |
| 4079 | drm_free_large(exec2_list); |
| 4080 | return ret; |
| 4081 | } |
| 4082 | |
| 4083 | int |
| 4084 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 4085 | struct drm_file *file_priv) |
| 4086 | { |
| 4087 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4088 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4089 | int ret; |
| 4090 | |
| 4091 | #if WATCH_EXEC |
| 4092 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4093 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4094 | #endif |
| 4095 | |
| 4096 | if (args->buffer_count < 1) { |
| 4097 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4098 | return -EINVAL; |
| 4099 | } |
| 4100 | |
| 4101 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4102 | if (exec2_list == NULL) { |
| 4103 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4104 | args->buffer_count); |
| 4105 | return -ENOMEM; |
| 4106 | } |
| 4107 | ret = copy_from_user(exec2_list, |
| 4108 | (struct drm_i915_relocation_entry __user *) |
| 4109 | (uintptr_t) args->buffers_ptr, |
| 4110 | sizeof(*exec2_list) * args->buffer_count); |
| 4111 | if (ret != 0) { |
| 4112 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4113 | args->buffer_count, ret); |
| 4114 | drm_free_large(exec2_list); |
| 4115 | return -EFAULT; |
| 4116 | } |
| 4117 | |
| 4118 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4119 | if (!ret) { |
| 4120 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4121 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4122 | (uintptr_t) args->buffers_ptr, |
| 4123 | exec2_list, |
| 4124 | sizeof(*exec2_list) * args->buffer_count); |
| 4125 | if (ret) { |
| 4126 | ret = -EFAULT; |
| 4127 | DRM_ERROR("failed to copy %d exec entries " |
| 4128 | "back to user (%d)\n", |
| 4129 | args->buffer_count, ret); |
| 4130 | } |
| 4131 | } |
| 4132 | |
| 4133 | drm_free_large(exec2_list); |
| 4134 | return ret; |
| 4135 | } |
| 4136 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4137 | int |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4138 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
| 4139 | bool mappable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4140 | { |
| 4141 | struct drm_device *dev = obj->dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4142 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4143 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4144 | int ret; |
| 4145 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4146 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4147 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4148 | |
| 4149 | if (obj_priv->gtt_space != NULL) { |
| 4150 | if (alignment == 0) |
| 4151 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 4152 | if (obj_priv->gtt_offset & (alignment - 1) || |
| 4153 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4154 | WARN(obj_priv->pin_count, |
| 4155 | "bo is already pinned with incorrect alignment:" |
| 4156 | " offset=%x, req.alignment=%x\n", |
| 4157 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4158 | ret = i915_gem_object_unbind(obj); |
| 4159 | if (ret) |
| 4160 | return ret; |
| 4161 | } |
| 4162 | } |
| 4163 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4164 | if (obj_priv->gtt_space == NULL) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4165 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4166 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4167 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4168 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4169 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4170 | obj_priv->pin_count++; |
| 4171 | |
| 4172 | /* If the object is not active and not pending a flush, |
| 4173 | * remove it from the inactive list |
| 4174 | */ |
| 4175 | if (obj_priv->pin_count == 1) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 4176 | i915_gem_info_add_pin(dev_priv, obj, mappable); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4177 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4178 | list_move_tail(&obj_priv->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4179 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4180 | } |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 4181 | BUG_ON(!obj_priv->pin_mappable && mappable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4182 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4183 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4184 | return 0; |
| 4185 | } |
| 4186 | |
| 4187 | void |
| 4188 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4189 | { |
| 4190 | struct drm_device *dev = obj->dev; |
| 4191 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4192 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4193 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4194 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4195 | obj_priv->pin_count--; |
| 4196 | BUG_ON(obj_priv->pin_count < 0); |
| 4197 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4198 | |
| 4199 | /* If the object is no longer pinned, and is |
| 4200 | * neither active nor being flushed, then stick it on |
| 4201 | * the inactive list |
| 4202 | */ |
| 4203 | if (obj_priv->pin_count == 0) { |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4204 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4205 | list_move_tail(&obj_priv->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4206 | &dev_priv->mm.inactive_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame^] | 4207 | i915_gem_info_remove_pin(dev_priv, obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4208 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4209 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4210 | } |
| 4211 | |
| 4212 | int |
| 4213 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4214 | struct drm_file *file_priv) |
| 4215 | { |
| 4216 | struct drm_i915_gem_pin *args = data; |
| 4217 | struct drm_gem_object *obj; |
| 4218 | struct drm_i915_gem_object *obj_priv; |
| 4219 | int ret; |
| 4220 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4221 | ret = i915_mutex_lock_interruptible(dev); |
| 4222 | if (ret) |
| 4223 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4224 | |
| 4225 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4226 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4227 | ret = -ENOENT; |
| 4228 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4229 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4230 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4231 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4232 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4233 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4234 | ret = -EINVAL; |
| 4235 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4236 | } |
| 4237 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4238 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4239 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4240 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4241 | ret = -EINVAL; |
| 4242 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4243 | } |
| 4244 | |
| 4245 | obj_priv->user_pin_count++; |
| 4246 | obj_priv->pin_filp = file_priv; |
| 4247 | if (obj_priv->user_pin_count == 1) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4248 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4249 | if (ret) |
| 4250 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4251 | } |
| 4252 | |
| 4253 | /* XXX - flush the CPU caches for pinned objects |
| 4254 | * as the X server doesn't manage domains yet |
| 4255 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4256 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4257 | args->offset = obj_priv->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4258 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4259 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4260 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4261 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4262 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4263 | } |
| 4264 | |
| 4265 | int |
| 4266 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4267 | struct drm_file *file_priv) |
| 4268 | { |
| 4269 | struct drm_i915_gem_pin *args = data; |
| 4270 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4271 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4272 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4273 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4274 | ret = i915_mutex_lock_interruptible(dev); |
| 4275 | if (ret) |
| 4276 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4277 | |
| 4278 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4279 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4280 | ret = -ENOENT; |
| 4281 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4282 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4283 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4284 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4285 | if (obj_priv->pin_filp != file_priv) { |
| 4286 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4287 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4288 | ret = -EINVAL; |
| 4289 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4290 | } |
| 4291 | obj_priv->user_pin_count--; |
| 4292 | if (obj_priv->user_pin_count == 0) { |
| 4293 | obj_priv->pin_filp = NULL; |
| 4294 | i915_gem_object_unpin(obj); |
| 4295 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4296 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4297 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4298 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4299 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4300 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4301 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4302 | } |
| 4303 | |
| 4304 | int |
| 4305 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4306 | struct drm_file *file_priv) |
| 4307 | { |
| 4308 | struct drm_i915_gem_busy *args = data; |
| 4309 | struct drm_gem_object *obj; |
| 4310 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4311 | int ret; |
| 4312 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4313 | ret = i915_mutex_lock_interruptible(dev); |
| 4314 | if (ret) |
| 4315 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4316 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4317 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4318 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4319 | ret = -ENOENT; |
| 4320 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4321 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4322 | obj_priv = to_intel_bo(obj); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4323 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4324 | /* Count all active objects as busy, even if they are currently not used |
| 4325 | * by the gpu. Users of this interface expect objects to eventually |
| 4326 | * become non-busy without any further actions, therefore emit any |
| 4327 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4328 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4329 | args->busy = obj_priv->active; |
| 4330 | if (args->busy) { |
| 4331 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4332 | * object. Userspace calling this function indicates that it wants to |
| 4333 | * use this buffer rather sooner than later, so issuing the required |
| 4334 | * flush earlier is beneficial. |
| 4335 | */ |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 4336 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
| 4337 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 4338 | obj_priv->ring, |
| 4339 | 0, obj->write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4340 | |
| 4341 | /* Update the active list for the hardware's current position. |
| 4342 | * Otherwise this only updates on a delayed timer or when irqs |
| 4343 | * are actually unmasked, and our working set ends up being |
| 4344 | * larger than required. |
| 4345 | */ |
| 4346 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4347 | |
| 4348 | args->busy = obj_priv->active; |
| 4349 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4350 | |
| 4351 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4352 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4353 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4354 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4355 | } |
| 4356 | |
| 4357 | int |
| 4358 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4359 | struct drm_file *file_priv) |
| 4360 | { |
| 4361 | return i915_gem_ring_throttle(dev, file_priv); |
| 4362 | } |
| 4363 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4364 | int |
| 4365 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4366 | struct drm_file *file_priv) |
| 4367 | { |
| 4368 | struct drm_i915_gem_madvise *args = data; |
| 4369 | struct drm_gem_object *obj; |
| 4370 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4371 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4372 | |
| 4373 | switch (args->madv) { |
| 4374 | case I915_MADV_DONTNEED: |
| 4375 | case I915_MADV_WILLNEED: |
| 4376 | break; |
| 4377 | default: |
| 4378 | return -EINVAL; |
| 4379 | } |
| 4380 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4381 | ret = i915_mutex_lock_interruptible(dev); |
| 4382 | if (ret) |
| 4383 | return ret; |
| 4384 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4385 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4386 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4387 | ret = -ENOENT; |
| 4388 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4389 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4390 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4391 | |
| 4392 | if (obj_priv->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4393 | ret = -EINVAL; |
| 4394 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4395 | } |
| 4396 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4397 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4398 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4399 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4400 | /* if the object is no longer bound, discard its backing storage */ |
| 4401 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4402 | obj_priv->gtt_space == NULL) |
| 4403 | i915_gem_object_truncate(obj); |
| 4404 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4405 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4406 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4407 | out: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4408 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4409 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4410 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4411 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4412 | } |
| 4413 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4414 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4415 | size_t size) |
| 4416 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4417 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4418 | struct drm_i915_gem_object *obj; |
| 4419 | |
| 4420 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4421 | if (obj == NULL) |
| 4422 | return NULL; |
| 4423 | |
| 4424 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4425 | kfree(obj); |
| 4426 | return NULL; |
| 4427 | } |
| 4428 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4429 | i915_gem_info_add_obj(dev_priv, size); |
| 4430 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4431 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4432 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4433 | |
| 4434 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4435 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4436 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4437 | INIT_LIST_HEAD(&obj->mm_list); |
| 4438 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4439 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4440 | obj->madv = I915_MADV_WILLNEED; |
| 4441 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4442 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4443 | } |
| 4444 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4445 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4446 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4447 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4448 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4449 | return 0; |
| 4450 | } |
| 4451 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4452 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4453 | { |
| 4454 | struct drm_device *dev = obj->dev; |
| 4455 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4456 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4457 | int ret; |
| 4458 | |
| 4459 | ret = i915_gem_object_unbind(obj); |
| 4460 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4461 | list_move(&obj_priv->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4462 | &dev_priv->mm.deferred_free_list); |
| 4463 | return; |
| 4464 | } |
| 4465 | |
| 4466 | if (obj_priv->mmap_offset) |
| 4467 | i915_gem_free_mmap_offset(obj); |
| 4468 | |
| 4469 | drm_gem_object_release(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4470 | i915_gem_info_remove_obj(dev_priv, obj->size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4471 | |
| 4472 | kfree(obj_priv->page_cpu_valid); |
| 4473 | kfree(obj_priv->bit_17); |
| 4474 | kfree(obj_priv); |
| 4475 | } |
| 4476 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4477 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4478 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4479 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4480 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4481 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4482 | trace_i915_gem_object_destroy(obj); |
| 4483 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4484 | while (obj_priv->pin_count > 0) |
| 4485 | i915_gem_object_unpin(obj); |
| 4486 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4487 | if (obj_priv->phys_obj) |
| 4488 | i915_gem_detach_phys_object(dev, obj); |
| 4489 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4490 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4491 | } |
| 4492 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4493 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4494 | i915_gem_idle(struct drm_device *dev) |
| 4495 | { |
| 4496 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4497 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4498 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4499 | mutex_lock(&dev->struct_mutex); |
| 4500 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4501 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4502 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4503 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4504 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4505 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4506 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4507 | if (ret) { |
| 4508 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4509 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4510 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4511 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4512 | /* Under UMS, be paranoid and evict. */ |
| 4513 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4514 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4515 | if (ret) { |
| 4516 | mutex_unlock(&dev->struct_mutex); |
| 4517 | return ret; |
| 4518 | } |
| 4519 | } |
| 4520 | |
| 4521 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4522 | * We need to replace this with a semaphore, or something. |
| 4523 | * And not confound mm.suspended! |
| 4524 | */ |
| 4525 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4526 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4527 | |
| 4528 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4529 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4530 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4531 | mutex_unlock(&dev->struct_mutex); |
| 4532 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4533 | /* Cancel the retire work handler, which should be idle now. */ |
| 4534 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4535 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4536 | return 0; |
| 4537 | } |
| 4538 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4539 | /* |
| 4540 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4541 | * over cache flushing. |
| 4542 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4543 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4544 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4545 | { |
| 4546 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4547 | struct drm_gem_object *obj; |
| 4548 | struct drm_i915_gem_object *obj_priv; |
| 4549 | int ret; |
| 4550 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4551 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4552 | if (obj == NULL) { |
| 4553 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4554 | ret = -ENOMEM; |
| 4555 | goto err; |
| 4556 | } |
| 4557 | obj_priv = to_intel_bo(obj); |
| 4558 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4559 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4560 | ret = i915_gem_object_pin(obj, 4096, true); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4561 | if (ret) |
| 4562 | goto err_unref; |
| 4563 | |
| 4564 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4565 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4566 | if (dev_priv->seqno_page == NULL) |
| 4567 | goto err_unpin; |
| 4568 | |
| 4569 | dev_priv->seqno_obj = obj; |
| 4570 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4571 | |
| 4572 | return 0; |
| 4573 | |
| 4574 | err_unpin: |
| 4575 | i915_gem_object_unpin(obj); |
| 4576 | err_unref: |
| 4577 | drm_gem_object_unreference(obj); |
| 4578 | err: |
| 4579 | return ret; |
| 4580 | } |
| 4581 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4582 | |
| 4583 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4584 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4585 | { |
| 4586 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4587 | struct drm_gem_object *obj; |
| 4588 | struct drm_i915_gem_object *obj_priv; |
| 4589 | |
| 4590 | obj = dev_priv->seqno_obj; |
| 4591 | obj_priv = to_intel_bo(obj); |
| 4592 | kunmap(obj_priv->pages[0]); |
| 4593 | i915_gem_object_unpin(obj); |
| 4594 | drm_gem_object_unreference(obj); |
| 4595 | dev_priv->seqno_obj = NULL; |
| 4596 | |
| 4597 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4598 | } |
| 4599 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4600 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4601 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4602 | { |
| 4603 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4604 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4605 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4606 | if (HAS_PIPE_CONTROL(dev)) { |
| 4607 | ret = i915_gem_init_pipe_control(dev); |
| 4608 | if (ret) |
| 4609 | return ret; |
| 4610 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4611 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4612 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4613 | if (ret) |
| 4614 | goto cleanup_pipe_control; |
| 4615 | |
| 4616 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4617 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4618 | if (ret) |
| 4619 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4620 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4621 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4622 | if (HAS_BLT(dev)) { |
| 4623 | ret = intel_init_blt_ring_buffer(dev); |
| 4624 | if (ret) |
| 4625 | goto cleanup_bsd_ring; |
| 4626 | } |
| 4627 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4628 | dev_priv->next_seqno = 1; |
| 4629 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4630 | return 0; |
| 4631 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4632 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4633 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4634 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4635 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4636 | cleanup_pipe_control: |
| 4637 | if (HAS_PIPE_CONTROL(dev)) |
| 4638 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4639 | return ret; |
| 4640 | } |
| 4641 | |
| 4642 | void |
| 4643 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4644 | { |
| 4645 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4646 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4647 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 4648 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 4649 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4650 | if (HAS_PIPE_CONTROL(dev)) |
| 4651 | i915_gem_cleanup_pipe_control(dev); |
| 4652 | } |
| 4653 | |
| 4654 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4655 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4656 | struct drm_file *file_priv) |
| 4657 | { |
| 4658 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4659 | int ret; |
| 4660 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4661 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4662 | return 0; |
| 4663 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4664 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4665 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4666 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4667 | } |
| 4668 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4669 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4670 | dev_priv->mm.suspended = 0; |
| 4671 | |
| 4672 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4673 | if (ret != 0) { |
| 4674 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4675 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4676 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4677 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4678 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4679 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4680 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4681 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4682 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4683 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4684 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4685 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4686 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4687 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4688 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4689 | ret = drm_irq_install(dev); |
| 4690 | if (ret) |
| 4691 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4692 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4693 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4694 | |
| 4695 | cleanup_ringbuffer: |
| 4696 | mutex_lock(&dev->struct_mutex); |
| 4697 | i915_gem_cleanup_ringbuffer(dev); |
| 4698 | dev_priv->mm.suspended = 1; |
| 4699 | mutex_unlock(&dev->struct_mutex); |
| 4700 | |
| 4701 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4702 | } |
| 4703 | |
| 4704 | int |
| 4705 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4706 | struct drm_file *file_priv) |
| 4707 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4708 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4709 | return 0; |
| 4710 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4711 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4712 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4713 | } |
| 4714 | |
| 4715 | void |
| 4716 | i915_gem_lastclose(struct drm_device *dev) |
| 4717 | { |
| 4718 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4719 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4720 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4721 | return; |
| 4722 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4723 | ret = i915_gem_idle(dev); |
| 4724 | if (ret) |
| 4725 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4726 | } |
| 4727 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4728 | static void |
| 4729 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4730 | { |
| 4731 | INIT_LIST_HEAD(&ring->active_list); |
| 4732 | INIT_LIST_HEAD(&ring->request_list); |
| 4733 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 4734 | } |
| 4735 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4736 | void |
| 4737 | i915_gem_load(struct drm_device *dev) |
| 4738 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4739 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4740 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4741 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4742 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4743 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4744 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4745 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4746 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4747 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4748 | init_ring_lists(&dev_priv->render_ring); |
| 4749 | init_ring_lists(&dev_priv->bsd_ring); |
| 4750 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4751 | for (i = 0; i < 16; i++) |
| 4752 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4753 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4754 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4755 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4756 | spin_lock(&shrink_list_lock); |
| 4757 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4758 | spin_unlock(&shrink_list_lock); |
| 4759 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4760 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4761 | if (IS_GEN3(dev)) { |
| 4762 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4763 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4764 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4765 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4766 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4767 | } |
| 4768 | } |
| 4769 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4770 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4771 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4772 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4773 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4774 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4775 | dev_priv->num_fence_regs = 16; |
| 4776 | else |
| 4777 | dev_priv->num_fence_regs = 8; |
| 4778 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4779 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4780 | switch (INTEL_INFO(dev)->gen) { |
| 4781 | case 6: |
| 4782 | for (i = 0; i < 16; i++) |
| 4783 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4784 | break; |
| 4785 | case 5: |
| 4786 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4787 | for (i = 0; i < 16; i++) |
| 4788 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4789 | break; |
| 4790 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4791 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4792 | for (i = 0; i < 8; i++) |
| 4793 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4794 | case 2: |
| 4795 | for (i = 0; i < 8; i++) |
| 4796 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4797 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4798 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4799 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4800 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4801 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4802 | |
| 4803 | /* |
| 4804 | * Create a physically contiguous memory object for this object |
| 4805 | * e.g. for cursor + overlay regs |
| 4806 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4807 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4808 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4809 | { |
| 4810 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4811 | struct drm_i915_gem_phys_object *phys_obj; |
| 4812 | int ret; |
| 4813 | |
| 4814 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4815 | return 0; |
| 4816 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4817 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4818 | if (!phys_obj) |
| 4819 | return -ENOMEM; |
| 4820 | |
| 4821 | phys_obj->id = id; |
| 4822 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4823 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4824 | if (!phys_obj->handle) { |
| 4825 | ret = -ENOMEM; |
| 4826 | goto kfree_obj; |
| 4827 | } |
| 4828 | #ifdef CONFIG_X86 |
| 4829 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4830 | #endif |
| 4831 | |
| 4832 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4833 | |
| 4834 | return 0; |
| 4835 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4836 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4837 | return ret; |
| 4838 | } |
| 4839 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4840 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4841 | { |
| 4842 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4843 | struct drm_i915_gem_phys_object *phys_obj; |
| 4844 | |
| 4845 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4846 | return; |
| 4847 | |
| 4848 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4849 | if (phys_obj->cur_obj) { |
| 4850 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4851 | } |
| 4852 | |
| 4853 | #ifdef CONFIG_X86 |
| 4854 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4855 | #endif |
| 4856 | drm_pci_free(dev, phys_obj->handle); |
| 4857 | kfree(phys_obj); |
| 4858 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4859 | } |
| 4860 | |
| 4861 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4862 | { |
| 4863 | int i; |
| 4864 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4865 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4866 | i915_gem_free_phys_object(dev, i); |
| 4867 | } |
| 4868 | |
| 4869 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4870 | struct drm_gem_object *obj) |
| 4871 | { |
| 4872 | struct drm_i915_gem_object *obj_priv; |
| 4873 | int i; |
| 4874 | int ret; |
| 4875 | int page_count; |
| 4876 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4877 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4878 | if (!obj_priv->phys_obj) |
| 4879 | return; |
| 4880 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4881 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4882 | if (ret) |
| 4883 | goto out; |
| 4884 | |
| 4885 | page_count = obj->size / PAGE_SIZE; |
| 4886 | |
| 4887 | for (i = 0; i < page_count; i++) { |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4888 | char *dst = kmap_atomic(obj_priv->pages[i]); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4889 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4890 | |
| 4891 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4892 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4893 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4894 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4895 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4896 | |
| 4897 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4898 | out: |
| 4899 | obj_priv->phys_obj->cur_obj = NULL; |
| 4900 | obj_priv->phys_obj = NULL; |
| 4901 | } |
| 4902 | |
| 4903 | int |
| 4904 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4905 | struct drm_gem_object *obj, |
| 4906 | int id, |
| 4907 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4908 | { |
| 4909 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4910 | struct drm_i915_gem_object *obj_priv; |
| 4911 | int ret = 0; |
| 4912 | int page_count; |
| 4913 | int i; |
| 4914 | |
| 4915 | if (id > I915_MAX_PHYS_OBJECT) |
| 4916 | return -EINVAL; |
| 4917 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4918 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4919 | |
| 4920 | if (obj_priv->phys_obj) { |
| 4921 | if (obj_priv->phys_obj->id == id) |
| 4922 | return 0; |
| 4923 | i915_gem_detach_phys_object(dev, obj); |
| 4924 | } |
| 4925 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4926 | /* create a new object */ |
| 4927 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4928 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4929 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4930 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4931 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4932 | goto out; |
| 4933 | } |
| 4934 | } |
| 4935 | |
| 4936 | /* bind to the object */ |
| 4937 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4938 | obj_priv->phys_obj->cur_obj = obj; |
| 4939 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4940 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4941 | if (ret) { |
| 4942 | DRM_ERROR("failed to get page list\n"); |
| 4943 | goto out; |
| 4944 | } |
| 4945 | |
| 4946 | page_count = obj->size / PAGE_SIZE; |
| 4947 | |
| 4948 | for (i = 0; i < page_count; i++) { |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4949 | char *src = kmap_atomic(obj_priv->pages[i]); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4950 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4951 | |
| 4952 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4953 | kunmap_atomic(src); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4954 | } |
| 4955 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4956 | i915_gem_object_put_pages(obj); |
| 4957 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4958 | return 0; |
| 4959 | out: |
| 4960 | return ret; |
| 4961 | } |
| 4962 | |
| 4963 | static int |
| 4964 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4965 | struct drm_i915_gem_pwrite *args, |
| 4966 | struct drm_file *file_priv) |
| 4967 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4968 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4969 | void *obj_addr; |
| 4970 | int ret; |
| 4971 | char __user *user_data; |
| 4972 | |
| 4973 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4974 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4975 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4976 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4977 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4978 | if (ret) |
| 4979 | return -EFAULT; |
| 4980 | |
| 4981 | drm_agp_chipset_flush(dev); |
| 4982 | return 0; |
| 4983 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4984 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4985 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4986 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4987 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4988 | |
| 4989 | /* Clean up our request list when the client is going away, so that |
| 4990 | * later retire_requests won't dereference our soon-to-be-gone |
| 4991 | * file_priv. |
| 4992 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4993 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4994 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4995 | struct drm_i915_gem_request *request; |
| 4996 | |
| 4997 | request = list_first_entry(&file_priv->mm.request_list, |
| 4998 | struct drm_i915_gem_request, |
| 4999 | client_list); |
| 5000 | list_del(&request->client_list); |
| 5001 | request->file_priv = NULL; |
| 5002 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5003 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5004 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5005 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5006 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5007 | i915_gpu_is_active(struct drm_device *dev) |
| 5008 | { |
| 5009 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 5010 | int lists_empty; |
| 5011 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5012 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 5013 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 5014 | list_empty(&dev_priv->bsd_ring.active_list) && |
| 5015 | list_empty(&dev_priv->blt_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5016 | |
| 5017 | return !lists_empty; |
| 5018 | } |
| 5019 | |
| 5020 | static int |
Dave Chinner | 7f8275d | 2010-07-19 14:56:17 +1000 | [diff] [blame] | 5021 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5022 | { |
| 5023 | drm_i915_private_t *dev_priv, *next_dev; |
| 5024 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 5025 | int cnt = 0; |
| 5026 | int would_deadlock = 1; |
| 5027 | |
| 5028 | /* "fast-path" to count number of available objects */ |
| 5029 | if (nr_to_scan == 0) { |
| 5030 | spin_lock(&shrink_list_lock); |
| 5031 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5032 | struct drm_device *dev = dev_priv->dev; |
| 5033 | |
| 5034 | if (mutex_trylock(&dev->struct_mutex)) { |
| 5035 | list_for_each_entry(obj_priv, |
| 5036 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 5037 | mm_list) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5038 | cnt++; |
| 5039 | mutex_unlock(&dev->struct_mutex); |
| 5040 | } |
| 5041 | } |
| 5042 | spin_unlock(&shrink_list_lock); |
| 5043 | |
| 5044 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5045 | } |
| 5046 | |
| 5047 | spin_lock(&shrink_list_lock); |
| 5048 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5049 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5050 | /* first scan for clean buffers */ |
| 5051 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5052 | &shrink_list, mm.shrink_list) { |
| 5053 | struct drm_device *dev = dev_priv->dev; |
| 5054 | |
| 5055 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5056 | continue; |
| 5057 | |
| 5058 | spin_unlock(&shrink_list_lock); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 5059 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 5060 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5061 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5062 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 5063 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5064 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 5065 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5066 | if (--nr_to_scan <= 0) |
| 5067 | break; |
| 5068 | } |
| 5069 | } |
| 5070 | |
| 5071 | spin_lock(&shrink_list_lock); |
| 5072 | mutex_unlock(&dev->struct_mutex); |
| 5073 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5074 | would_deadlock = 0; |
| 5075 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5076 | if (nr_to_scan <= 0) |
| 5077 | break; |
| 5078 | } |
| 5079 | |
| 5080 | /* second pass, evict/count anything still on the inactive list */ |
| 5081 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5082 | &shrink_list, mm.shrink_list) { |
| 5083 | struct drm_device *dev = dev_priv->dev; |
| 5084 | |
| 5085 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5086 | continue; |
| 5087 | |
| 5088 | spin_unlock(&shrink_list_lock); |
| 5089 | |
| 5090 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5091 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 5092 | mm_list) { |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5093 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 5094 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5095 | nr_to_scan--; |
| 5096 | } else |
| 5097 | cnt++; |
| 5098 | } |
| 5099 | |
| 5100 | spin_lock(&shrink_list_lock); |
| 5101 | mutex_unlock(&dev->struct_mutex); |
| 5102 | |
| 5103 | would_deadlock = 0; |
| 5104 | } |
| 5105 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5106 | if (nr_to_scan) { |
| 5107 | int active = 0; |
| 5108 | |
| 5109 | /* |
| 5110 | * We are desperate for pages, so as a last resort, wait |
| 5111 | * for the GPU to finish and discard whatever we can. |
| 5112 | * This has a dramatic impact to reduce the number of |
| 5113 | * OOM-killer events whilst running the GPU aggressively. |
| 5114 | */ |
| 5115 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5116 | struct drm_device *dev = dev_priv->dev; |
| 5117 | |
| 5118 | if (!mutex_trylock(&dev->struct_mutex)) |
| 5119 | continue; |
| 5120 | |
| 5121 | spin_unlock(&shrink_list_lock); |
| 5122 | |
| 5123 | if (i915_gpu_is_active(dev)) { |
| 5124 | i915_gpu_idle(dev); |
| 5125 | active++; |
| 5126 | } |
| 5127 | |
| 5128 | spin_lock(&shrink_list_lock); |
| 5129 | mutex_unlock(&dev->struct_mutex); |
| 5130 | } |
| 5131 | |
| 5132 | if (active) |
| 5133 | goto rescan; |
| 5134 | } |
| 5135 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5136 | spin_unlock(&shrink_list_lock); |
| 5137 | |
| 5138 | if (would_deadlock) |
| 5139 | return -1; |
| 5140 | else if (cnt > 0) |
| 5141 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5142 | else |
| 5143 | return 0; |
| 5144 | } |
| 5145 | |
| 5146 | static struct shrinker shrinker = { |
| 5147 | .shrink = i915_gem_shrink, |
| 5148 | .seeks = DEFAULT_SEEKS, |
| 5149 | }; |
| 5150 | |
| 5151 | __init void |
| 5152 | i915_gem_shrinker_init(void) |
| 5153 | { |
| 5154 | register_shrinker(&shrinker); |
| 5155 | } |
| 5156 | |
| 5157 | __exit void |
| 5158 | i915_gem_shrinker_exit(void) |
| 5159 | { |
| 5160 | unregister_shrinker(&shrinker); |
| 5161 | } |