blob: eabfe5c22b05a51bf34615a16efde8b3de0ec330 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020070
71static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
72static const char mlxsw_sp_driver_version[] = "1.0";
73
74/* tx_hdr_version
75 * Tx header version.
76 * Must be set to 1.
77 */
78MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
79
80/* tx_hdr_ctl
81 * Packet control type.
82 * 0 - Ethernet control (e.g. EMADs, LACP)
83 * 1 - Ethernet data
84 */
85MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
86
87/* tx_hdr_proto
88 * Packet protocol type. Must be set to 1 (Ethernet).
89 */
90MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
91
92/* tx_hdr_rx_is_router
93 * Packet is sent from the router. Valid for data packets only.
94 */
95MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
96
97/* tx_hdr_fid_valid
98 * Indicates if the 'fid' field is valid and should be used for
99 * forwarding lookup. Valid for data packets only.
100 */
101MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
102
103/* tx_hdr_swid
104 * Switch partition ID. Must be set to 0.
105 */
106MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
107
108/* tx_hdr_control_tclass
109 * Indicates if the packet should use the control TClass and not one
110 * of the data TClasses.
111 */
112MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
113
114/* tx_hdr_etclass
115 * Egress TClass to be used on the egress device on the egress port.
116 */
117MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
118
119/* tx_hdr_port_mid
120 * Destination local port for unicast packets.
121 * Destination multicast ID for multicast packets.
122 *
123 * Control packets are directed to a specific egress port, while data
124 * packets are transmitted through the CPU port (0) into the switch partition,
125 * where forwarding rules are applied.
126 */
127MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
128
129/* tx_hdr_fid
130 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
131 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
132 * Valid for data packets only.
133 */
134MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
135
136/* tx_hdr_type
137 * 0 - Data packets
138 * 6 - Control packets
139 */
140MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
141
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100142int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
143 unsigned int counter_index, u64 *packets,
144 u64 *bytes)
145{
146 char mgpc_pl[MLXSW_REG_MGPC_LEN];
147 int err;
148
149 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
150 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
151 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
152 if (err)
153 return err;
154 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
155 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
156 return 0;
157}
158
159static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
160 unsigned int counter_index)
161{
162 char mgpc_pl[MLXSW_REG_MGPC_LEN];
163
164 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
165 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
166 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
167}
168
169int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
170 unsigned int *p_counter_index)
171{
172 int err;
173
174 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
175 p_counter_index);
176 if (err)
177 return err;
178 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
179 if (err)
180 goto err_counter_clear;
181 return 0;
182
183err_counter_clear:
184 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
185 *p_counter_index);
186 return err;
187}
188
189void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
190 unsigned int counter_index)
191{
192 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
193 counter_index);
194}
195
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200196static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
197 const struct mlxsw_tx_info *tx_info)
198{
199 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
200
201 memset(txhdr, 0, MLXSW_TXHDR_LEN);
202
203 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
204 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
205 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
206 mlxsw_tx_hdr_swid_set(txhdr, 0);
207 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
208 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
209 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
210}
211
212static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
213{
Elad Raz5b090742016-10-28 21:35:46 +0200214 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200215 int err;
216
217 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
218 if (err)
219 return err;
220 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
221 return 0;
222}
223
Yotam Gigi763b4b72016-07-21 12:03:17 +0200224static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
225{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200226 int i;
227
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200228 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200229 return -EIO;
230
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200231 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
232 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200233 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
234 sizeof(struct mlxsw_sp_span_entry),
235 GFP_KERNEL);
236 if (!mlxsw_sp->span.entries)
237 return -ENOMEM;
238
239 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
240 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
241
242 return 0;
243}
244
245static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
246{
247 int i;
248
249 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
250 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
251
252 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
253 }
254 kfree(mlxsw_sp->span.entries);
255}
256
257static struct mlxsw_sp_span_entry *
258mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
259{
260 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
261 struct mlxsw_sp_span_entry *span_entry;
262 char mpat_pl[MLXSW_REG_MPAT_LEN];
263 u8 local_port = port->local_port;
264 int index;
265 int i;
266 int err;
267
268 /* find a free entry to use */
269 index = -1;
270 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
271 if (!mlxsw_sp->span.entries[i].used) {
272 index = i;
273 span_entry = &mlxsw_sp->span.entries[i];
274 break;
275 }
276 }
277 if (index < 0)
278 return NULL;
279
280 /* create a new port analayzer entry for local_port */
281 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
282 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
283 if (err)
284 return NULL;
285
286 span_entry->used = true;
287 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100288 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200289 span_entry->local_port = local_port;
290 return span_entry;
291}
292
293static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
294 struct mlxsw_sp_span_entry *span_entry)
295{
296 u8 local_port = span_entry->local_port;
297 char mpat_pl[MLXSW_REG_MPAT_LEN];
298 int pa_id = span_entry->id;
299
300 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
301 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
302 span_entry->used = false;
303}
304
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200305static struct mlxsw_sp_span_entry *
306mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200307{
308 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
309 int i;
310
311 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
312 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
313
314 if (curr->used && curr->local_port == port->local_port)
315 return curr;
316 }
317 return NULL;
318}
319
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200320static struct mlxsw_sp_span_entry
321*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200322{
323 struct mlxsw_sp_span_entry *span_entry;
324
325 span_entry = mlxsw_sp_span_entry_find(port);
326 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100327 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200328 span_entry->ref_count++;
329 return span_entry;
330 }
331
332 return mlxsw_sp_span_entry_create(port);
333}
334
335static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
336 struct mlxsw_sp_span_entry *span_entry)
337{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100338 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200339 if (--span_entry->ref_count == 0)
340 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
341 return 0;
342}
343
344static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
345{
346 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
347 struct mlxsw_sp_span_inspected_port *p;
348 int i;
349
350 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
351 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
352
353 list_for_each_entry(p, &curr->bound_ports_list, list)
354 if (p->local_port == port->local_port &&
355 p->type == MLXSW_SP_SPAN_EGRESS)
356 return true;
357 }
358
359 return false;
360}
361
Ido Schimmel18281f22017-03-24 08:02:51 +0100362static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
363 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200364{
Ido Schimmel18281f22017-03-24 08:02:51 +0100365 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200366}
367
368static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
369{
370 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
371 char sbib_pl[MLXSW_REG_SBIB_LEN];
372 int err;
373
374 /* If port is egress mirrored, the shared buffer size should be
375 * updated according to the mtu value
376 */
377 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100378 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
379
380 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200381 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
382 if (err) {
383 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
384 return err;
385 }
386 }
387
388 return 0;
389}
390
391static struct mlxsw_sp_span_inspected_port *
392mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
393 struct mlxsw_sp_span_entry *span_entry)
394{
395 struct mlxsw_sp_span_inspected_port *p;
396
397 list_for_each_entry(p, &span_entry->bound_ports_list, list)
398 if (port->local_port == p->local_port)
399 return p;
400 return NULL;
401}
402
403static int
404mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
405 struct mlxsw_sp_span_entry *span_entry,
406 enum mlxsw_sp_span_type type)
407{
408 struct mlxsw_sp_span_inspected_port *inspected_port;
409 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
410 char mpar_pl[MLXSW_REG_MPAR_LEN];
411 char sbib_pl[MLXSW_REG_SBIB_LEN];
412 int pa_id = span_entry->id;
413 int err;
414
415 /* if it is an egress SPAN, bind a shared buffer to it */
416 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100417 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
418 port->dev->mtu);
419
420 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200421 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
422 if (err) {
423 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
424 return err;
425 }
426 }
427
428 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200429 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
430 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200431 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
432 if (err)
433 goto err_mpar_reg_write;
434
435 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
436 if (!inspected_port) {
437 err = -ENOMEM;
438 goto err_inspected_port_alloc;
439 }
440 inspected_port->local_port = port->local_port;
441 inspected_port->type = type;
442 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
443
444 return 0;
445
446err_mpar_reg_write:
447err_inspected_port_alloc:
448 if (type == MLXSW_SP_SPAN_EGRESS) {
449 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
450 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
451 }
452 return err;
453}
454
455static void
456mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
457 struct mlxsw_sp_span_entry *span_entry,
458 enum mlxsw_sp_span_type type)
459{
460 struct mlxsw_sp_span_inspected_port *inspected_port;
461 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
462 char mpar_pl[MLXSW_REG_MPAR_LEN];
463 char sbib_pl[MLXSW_REG_SBIB_LEN];
464 int pa_id = span_entry->id;
465
466 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
467 if (!inspected_port)
468 return;
469
470 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200471 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
472 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200473 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
474
475 /* remove the SBIB buffer if it was egress SPAN */
476 if (type == MLXSW_SP_SPAN_EGRESS) {
477 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
478 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
479 }
480
481 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
482
483 list_del(&inspected_port->list);
484 kfree(inspected_port);
485}
486
487static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
488 struct mlxsw_sp_port *to,
489 enum mlxsw_sp_span_type type)
490{
491 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
492 struct mlxsw_sp_span_entry *span_entry;
493 int err;
494
495 span_entry = mlxsw_sp_span_entry_get(to);
496 if (!span_entry)
497 return -ENOENT;
498
499 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
500 span_entry->id);
501
502 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
503 if (err)
504 goto err_port_bind;
505
506 return 0;
507
508err_port_bind:
509 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
510 return err;
511}
512
513static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
514 struct mlxsw_sp_port *to,
515 enum mlxsw_sp_span_type type)
516{
517 struct mlxsw_sp_span_entry *span_entry;
518
519 span_entry = mlxsw_sp_span_entry_find(to);
520 if (!span_entry) {
521 netdev_err(from->dev, "no span entry found\n");
522 return;
523 }
524
525 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
526 span_entry->id);
527 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
528}
529
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100530static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
531 bool enable, u32 rate)
532{
533 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
534 char mpsc_pl[MLXSW_REG_MPSC_LEN];
535
536 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
537 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
538}
539
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200540static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
541 bool is_up)
542{
543 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
544 char paos_pl[MLXSW_REG_PAOS_LEN];
545
546 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
547 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
548 MLXSW_PORT_ADMIN_STATUS_DOWN);
549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
550}
551
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200552static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
553 unsigned char *addr)
554{
555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
556 char ppad_pl[MLXSW_REG_PPAD_LEN];
557
558 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
559 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
560 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
561}
562
563static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
564{
565 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
566 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
567
568 ether_addr_copy(addr, mlxsw_sp->base_mac);
569 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
570 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
571}
572
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200573static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
574{
575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 char pmtu_pl[MLXSW_REG_PMTU_LEN];
577 int max_mtu;
578 int err;
579
580 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
581 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
582 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
583 if (err)
584 return err;
585 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
586
587 if (mtu > max_mtu)
588 return -EINVAL;
589
590 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
591 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
592}
593
Ido Schimmelbe945352016-06-09 09:51:39 +0200594static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
595 u8 swid)
596{
597 char pspa_pl[MLXSW_REG_PSPA_LEN];
598
599 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
600 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
601}
602
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200603static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
604{
605 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200606
Ido Schimmelbe945352016-06-09 09:51:39 +0200607 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
608 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200609}
610
611static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
612 bool enable)
613{
614 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
615 char svpe_pl[MLXSW_REG_SVPE_LEN];
616
617 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
618 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
619}
620
621int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
622 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
623 u16 vid)
624{
625 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
626 char svfa_pl[MLXSW_REG_SVFA_LEN];
627
628 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
629 fid, vid);
630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
631}
632
Ido Schimmel584d73d2016-08-24 12:00:26 +0200633int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
634 u16 vid_begin, u16 vid_end,
635 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200636{
637 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
638 char *spvmlr_pl;
639 int err;
640
641 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
642 if (!spvmlr_pl)
643 return -ENOMEM;
Ido Schimmel584d73d2016-08-24 12:00:26 +0200644 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
645 vid_end, learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200646 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
647 kfree(spvmlr_pl);
648 return err;
649}
650
Ido Schimmel584d73d2016-08-24 12:00:26 +0200651static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
652 u16 vid, bool learn_enable)
653{
654 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
655 learn_enable);
656}
657
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200658static int
659mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
660{
661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
662 char sspr_pl[MLXSW_REG_SSPR_LEN];
663
664 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
665 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
666}
667
Ido Schimmeld664b412016-06-09 09:51:40 +0200668static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
669 u8 local_port, u8 *p_module,
670 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200671{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200672 char pmlp_pl[MLXSW_REG_PMLP_LEN];
673 int err;
674
Ido Schimmel558c2d52016-02-26 17:32:29 +0100675 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200676 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
677 if (err)
678 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100679 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
680 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200681 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200682 return 0;
683}
684
Ido Schimmel18f1e702016-02-26 17:32:31 +0100685static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
686 u8 module, u8 width, u8 lane)
687{
688 char pmlp_pl[MLXSW_REG_PMLP_LEN];
689 int i;
690
691 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
692 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
693 for (i = 0; i < width; i++) {
694 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
695 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
696 }
697
698 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
699}
700
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100701static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
702{
703 char pmlp_pl[MLXSW_REG_PMLP_LEN];
704
705 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
706 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
707 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
708}
709
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200710static int mlxsw_sp_port_open(struct net_device *dev)
711{
712 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
713 int err;
714
715 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
716 if (err)
717 return err;
718 netif_start_queue(dev);
719 return 0;
720}
721
722static int mlxsw_sp_port_stop(struct net_device *dev)
723{
724 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
725
726 netif_stop_queue(dev);
727 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
728}
729
730static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
731 struct net_device *dev)
732{
733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
734 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
735 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
736 const struct mlxsw_tx_info tx_info = {
737 .local_port = mlxsw_sp_port->local_port,
738 .is_emad = false,
739 };
740 u64 len;
741 int err;
742
Jiri Pirko307c2432016-04-08 19:11:22 +0200743 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200744 return NETDEV_TX_BUSY;
745
746 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
747 struct sk_buff *skb_orig = skb;
748
749 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
750 if (!skb) {
751 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
752 dev_kfree_skb_any(skb_orig);
753 return NETDEV_TX_OK;
754 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100755 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200756 }
757
758 if (eth_skb_pad(skb)) {
759 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
760 return NETDEV_TX_OK;
761 }
762
763 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200764 /* TX header is consumed by HW on the way so we shouldn't count its
765 * bytes as being sent.
766 */
767 len = skb->len - MLXSW_TXHDR_LEN;
768
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200769 /* Due to a race we might fail here because of a full queue. In that
770 * unlikely case we simply drop the packet.
771 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200772 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200773
774 if (!err) {
775 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
776 u64_stats_update_begin(&pcpu_stats->syncp);
777 pcpu_stats->tx_packets++;
778 pcpu_stats->tx_bytes += len;
779 u64_stats_update_end(&pcpu_stats->syncp);
780 } else {
781 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
782 dev_kfree_skb_any(skb);
783 }
784 return NETDEV_TX_OK;
785}
786
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100787static void mlxsw_sp_set_rx_mode(struct net_device *dev)
788{
789}
790
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200791static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
792{
793 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
794 struct sockaddr *addr = p;
795 int err;
796
797 if (!is_valid_ether_addr(addr->sa_data))
798 return -EADDRNOTAVAIL;
799
800 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
801 if (err)
802 return err;
803 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
804 return 0;
805}
806
Ido Schimmel18281f22017-03-24 08:02:51 +0100807static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
808 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200809{
Ido Schimmel18281f22017-03-24 08:02:51 +0100810 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100811}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200812
Ido Schimmelf417f042017-03-24 08:02:50 +0100813#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100814
815static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
816 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100817{
Ido Schimmel18281f22017-03-24 08:02:51 +0100818 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
819 BITS_PER_BYTE));
820 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
821 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100822}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200823
Ido Schimmel18281f22017-03-24 08:02:51 +0100824/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100825 * Assumes 100m cable and maximum MTU.
826 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100827#define MLXSW_SP_PAUSE_DELAY 58752
828
829static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
830 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100831{
832 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100833 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100834 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100835 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200836 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100837 return 0;
838}
839
840static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
841 bool lossy)
842{
843 if (lossy)
844 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
845 else
846 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
847 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200848}
849
850int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200851 u8 *prio_tc, bool pause_en,
852 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200853{
854 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200855 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
856 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200857 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200858 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200859
860 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
861 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
862 if (err)
863 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200864
865 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
866 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200867 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100868 bool lossy;
869 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200870
871 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
872 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200873 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200874 configure = true;
875 break;
876 }
877 }
878
879 if (!configure)
880 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100881
882 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100883 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
884 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
885 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100886 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200887 }
888
Ido Schimmelff6551e2016-04-06 17:10:03 +0200889 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
890}
891
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200892static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200893 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200894{
895 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
896 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200897 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200898 u8 *prio_tc;
899
900 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200901 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200902
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200903 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200904 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200905}
906
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200907static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
908{
909 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200910 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200911 int err;
912
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200913 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914 if (err)
915 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200916 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
917 if (err)
918 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200919 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
920 if (err)
921 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200922 dev->mtu = mtu;
923 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200924
925err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200926 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
927err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200928 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200929 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200930}
931
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300932static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200933mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
934 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200935{
936 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
937 struct mlxsw_sp_port_pcpu_stats *p;
938 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
939 u32 tx_dropped = 0;
940 unsigned int start;
941 int i;
942
943 for_each_possible_cpu(i) {
944 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
945 do {
946 start = u64_stats_fetch_begin_irq(&p->syncp);
947 rx_packets = p->rx_packets;
948 rx_bytes = p->rx_bytes;
949 tx_packets = p->tx_packets;
950 tx_bytes = p->tx_bytes;
951 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
952
953 stats->rx_packets += rx_packets;
954 stats->rx_bytes += rx_bytes;
955 stats->tx_packets += tx_packets;
956 stats->tx_bytes += tx_bytes;
957 /* tx_dropped is u32, updated without syncp protection. */
958 tx_dropped += p->tx_dropped;
959 }
960 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200961 return 0;
962}
963
Or Gerlitz3df5b3c2016-11-22 23:09:54 +0200964static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200965{
966 switch (attr_id) {
967 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
968 return true;
969 }
970
971 return false;
972}
973
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +0300974static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
975 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +0200976{
977 switch (attr_id) {
978 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
979 return mlxsw_sp_port_get_sw_stats64(dev, sp);
980 }
981
982 return -EINVAL;
983}
984
985static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
986 int prio, char *ppcnt_pl)
987{
988 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
989 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
990
991 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
992 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
993}
994
995static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
996 struct rtnl_link_stats64 *stats)
997{
998 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
999 int err;
1000
1001 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1002 0, ppcnt_pl);
1003 if (err)
1004 goto out;
1005
1006 stats->tx_packets =
1007 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1008 stats->rx_packets =
1009 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1010 stats->tx_bytes =
1011 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1012 stats->rx_bytes =
1013 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1014 stats->multicast =
1015 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1016
1017 stats->rx_crc_errors =
1018 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1019 stats->rx_frame_errors =
1020 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1021
1022 stats->rx_length_errors = (
1023 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1024 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1025 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1026
1027 stats->rx_errors = (stats->rx_crc_errors +
1028 stats->rx_frame_errors + stats->rx_length_errors);
1029
1030out:
1031 return err;
1032}
1033
1034static void update_stats_cache(struct work_struct *work)
1035{
1036 struct mlxsw_sp_port *mlxsw_sp_port =
1037 container_of(work, struct mlxsw_sp_port,
1038 hw_stats.update_dw.work);
1039
1040 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1041 goto out;
1042
1043 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1044 mlxsw_sp_port->hw_stats.cache);
1045
1046out:
1047 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1048 MLXSW_HW_STATS_UPDATE_TIME);
1049}
1050
1051/* Return the stats from a cache that is updated periodically,
1052 * as this function might get called in an atomic context.
1053 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001054static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001055mlxsw_sp_port_get_stats64(struct net_device *dev,
1056 struct rtnl_link_stats64 *stats)
1057{
1058 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1059
1060 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001061}
1062
1063int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1064 u16 vid_end, bool is_member, bool untagged)
1065{
1066 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1067 char *spvm_pl;
1068 int err;
1069
1070 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1071 if (!spvm_pl)
1072 return -ENOMEM;
1073
1074 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1075 vid_end, is_member, untagged);
1076 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1077 kfree(spvm_pl);
1078 return err;
1079}
1080
1081static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1082{
1083 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1084 u16 vid, last_visited_vid;
1085 int err;
1086
1087 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1088 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1089 vid);
1090 if (err) {
1091 last_visited_vid = vid;
1092 goto err_port_vid_to_fid_set;
1093 }
1094 }
1095
1096 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1097 if (err) {
1098 last_visited_vid = VLAN_N_VID;
1099 goto err_port_vid_to_fid_set;
1100 }
1101
1102 return 0;
1103
1104err_port_vid_to_fid_set:
1105 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1106 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1107 vid);
1108 return err;
1109}
1110
1111static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1112{
1113 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1114 u16 vid;
1115 int err;
1116
1117 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1118 if (err)
1119 return err;
1120
1121 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1122 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1123 vid, vid);
1124 if (err)
1125 return err;
1126 }
1127
1128 return 0;
1129}
1130
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001131static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +02001132mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001133{
1134 struct mlxsw_sp_port *mlxsw_sp_vport;
1135
1136 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1137 if (!mlxsw_sp_vport)
1138 return NULL;
1139
1140 /* dev will be set correctly after the VLAN device is linked
1141 * with the real device. In case of bridge SELF invocation, dev
1142 * will remain as is.
1143 */
1144 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1145 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1146 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1147 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +01001148 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1149 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +02001150 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001151
1152 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1153
1154 return mlxsw_sp_vport;
1155}
1156
1157static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1158{
1159 list_del(&mlxsw_sp_vport->vport.list);
1160 kfree(mlxsw_sp_vport);
1161}
1162
Ido Schimmel05978482016-08-17 16:39:30 +02001163static int mlxsw_sp_port_add_vid(struct net_device *dev,
1164 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001165{
1166 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001167 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +02001168 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001169 int err;
1170
1171 /* VLAN 0 is added to HW filter when device goes up, but it is
1172 * reserved in our case, so simply return.
1173 */
1174 if (!vid)
1175 return 0;
1176
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001177 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001178 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001179
Ido Schimmel0355b592016-06-20 23:04:13 +02001180 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001181 if (!mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02001182 return -ENOMEM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001183
1184 /* When adding the first VLAN interface on a bridged port we need to
1185 * transition all the active 802.1Q bridge VLANs to use explicit
1186 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1187 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001188 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001189 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001190 if (err)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001191 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001192 }
1193
Ido Schimmel52697a92016-07-02 11:00:09 +02001194 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001195 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001196 goto err_port_add_vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001197
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001198 return 0;
1199
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001200err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001201 if (list_is_singular(&mlxsw_sp_port->vports_list))
1202 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1203err_port_vp_mode_trans:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001204 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001205 return err;
1206}
1207
Ido Schimmel32d863f2016-07-02 11:00:10 +02001208static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1209 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001210{
1211 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001212 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +02001213 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001214
1215 /* VLAN 0 is removed from HW filter when device goes down, but
1216 * it is reserved in our case, so simply return.
1217 */
1218 if (!vid)
1219 return 0;
1220
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001221 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel7a355832016-08-17 16:39:28 +02001222 if (WARN_ON(!mlxsw_sp_vport))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001223 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001224
Ido Schimmel7a355832016-08-17 16:39:28 +02001225 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001226
Ido Schimmel1c800752016-06-20 23:04:20 +02001227 /* Drop FID reference. If this was the last reference the
1228 * resources will be freed.
1229 */
1230 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1231 if (f && !WARN_ON(!f->leave))
1232 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001233
1234 /* When removing the last VLAN interface on a bridged port we need to
1235 * transition all active 802.1Q bridge VLANs to use VID to FID
1236 * mappings and set port's mode to VLAN mode.
1237 */
Ido Schimmel7a355832016-08-17 16:39:28 +02001238 if (list_is_singular(&mlxsw_sp_port->vports_list))
1239 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001240
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001241 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1242
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001243 return 0;
1244}
1245
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001246static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1247 size_t len)
1248{
1249 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001250 u8 module = mlxsw_sp_port->mapping.module;
1251 u8 width = mlxsw_sp_port->mapping.width;
1252 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001253 int err;
1254
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001255 if (!mlxsw_sp_port->split)
1256 err = snprintf(name, len, "p%d", module + 1);
1257 else
1258 err = snprintf(name, len, "p%ds%d", module + 1,
1259 lane / width);
1260
1261 if (err >= len)
1262 return -EINVAL;
1263
1264 return 0;
1265}
1266
Yotam Gigi763b4b72016-07-21 12:03:17 +02001267static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001268mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1269 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001270 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1271
1272 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1273 if (mall_tc_entry->cookie == cookie)
1274 return mall_tc_entry;
1275
1276 return NULL;
1277}
1278
1279static int
1280mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001281 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001282 const struct tc_action *a,
1283 bool ingress)
1284{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001285 struct net *net = dev_net(mlxsw_sp_port->dev);
1286 enum mlxsw_sp_span_type span_type;
1287 struct mlxsw_sp_port *to_port;
1288 struct net_device *to_dev;
1289 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001290
1291 ifindex = tcf_mirred_ifindex(a);
1292 to_dev = __dev_get_by_index(net, ifindex);
1293 if (!to_dev) {
1294 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1295 return -EINVAL;
1296 }
1297
1298 if (!mlxsw_sp_port_dev_check(to_dev)) {
1299 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001300 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001301 }
1302 to_port = netdev_priv(to_dev);
1303
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001304 mirror->to_local_port = to_port->local_port;
1305 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001306 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001307 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1308}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001309
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001310static void
1311mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1312 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1313{
1314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1315 enum mlxsw_sp_span_type span_type;
1316 struct mlxsw_sp_port *to_port;
1317
1318 to_port = mlxsw_sp->ports[mirror->to_local_port];
1319 span_type = mirror->ingress ?
1320 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1321 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001322}
1323
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001324static int
1325mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1326 struct tc_cls_matchall_offload *cls,
1327 const struct tc_action *a,
1328 bool ingress)
1329{
1330 int err;
1331
1332 if (!mlxsw_sp_port->sample)
1333 return -EOPNOTSUPP;
1334 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1335 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1336 return -EEXIST;
1337 }
1338 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1339 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1340 return -EOPNOTSUPP;
1341 }
1342
1343 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1344 tcf_sample_psample_group(a));
1345 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1346 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1347 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1348
1349 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1350 if (err)
1351 goto err_port_sample_set;
1352 return 0;
1353
1354err_port_sample_set:
1355 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1356 return err;
1357}
1358
1359static void
1360mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1361{
1362 if (!mlxsw_sp_port->sample)
1363 return;
1364
1365 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1366 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1367}
1368
Yotam Gigi763b4b72016-07-21 12:03:17 +02001369static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1370 __be16 protocol,
1371 struct tc_cls_matchall_offload *cls,
1372 bool ingress)
1373{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001374 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001375 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001376 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001377 int err;
1378
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001379 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001380 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001381 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001382 }
1383
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001384 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1385 if (!mall_tc_entry)
1386 return -ENOMEM;
1387 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001388
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001389 tcf_exts_to_list(cls->exts, &actions);
1390 a = list_first_entry(&actions, struct tc_action, list);
1391
1392 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1393 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1394
1395 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1396 mirror = &mall_tc_entry->mirror;
1397 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1398 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001399 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1400 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1401 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1402 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001403 } else {
1404 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001405 }
1406
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001407 if (err)
1408 goto err_add_action;
1409
1410 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001411 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001412
1413err_add_action:
1414 kfree(mall_tc_entry);
1415 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001416}
1417
1418static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1419 struct tc_cls_matchall_offload *cls)
1420{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001421 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001422
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001423 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1424 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001425 if (!mall_tc_entry) {
1426 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1427 return;
1428 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001429 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001430
1431 switch (mall_tc_entry->type) {
1432 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001433 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1434 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001435 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001436 case MLXSW_SP_PORT_MALL_SAMPLE:
1437 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1438 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001439 default:
1440 WARN_ON(1);
1441 }
1442
Yotam Gigi763b4b72016-07-21 12:03:17 +02001443 kfree(mall_tc_entry);
1444}
1445
1446static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1447 __be16 proto, struct tc_to_netdev *tc)
1448{
1449 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1450 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1451
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001452 switch (tc->type) {
1453 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001454 switch (tc->cls_mall->command) {
1455 case TC_CLSMATCHALL_REPLACE:
1456 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1457 proto,
1458 tc->cls_mall,
1459 ingress);
1460 case TC_CLSMATCHALL_DESTROY:
1461 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1462 tc->cls_mall);
1463 return 0;
1464 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001465 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001466 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001467 case TC_SETUP_CLSFLOWER:
1468 switch (tc->cls_flower->command) {
1469 case TC_CLSFLOWER_REPLACE:
1470 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1471 proto, tc->cls_flower);
1472 case TC_CLSFLOWER_DESTROY:
1473 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1474 tc->cls_flower);
1475 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001476 case TC_CLSFLOWER_STATS:
1477 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1478 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001479 default:
1480 return -EOPNOTSUPP;
1481 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001482 }
1483
Yotam Gigie915ac62017-01-09 11:25:48 +01001484 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001485}
1486
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001487static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1488 .ndo_open = mlxsw_sp_port_open,
1489 .ndo_stop = mlxsw_sp_port_stop,
1490 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001491 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001492 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001493 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1494 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1495 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001496 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1497 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001498 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1499 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1500 .ndo_fdb_add = switchdev_port_fdb_add,
1501 .ndo_fdb_del = switchdev_port_fdb_del,
1502 .ndo_fdb_dump = switchdev_port_fdb_dump,
1503 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1504 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1505 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001506 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001507};
1508
1509static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1510 struct ethtool_drvinfo *drvinfo)
1511{
1512 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1513 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1514
1515 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1516 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1517 sizeof(drvinfo->version));
1518 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1519 "%d.%d.%d",
1520 mlxsw_sp->bus_info->fw_rev.major,
1521 mlxsw_sp->bus_info->fw_rev.minor,
1522 mlxsw_sp->bus_info->fw_rev.subminor);
1523 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1524 sizeof(drvinfo->bus_info));
1525}
1526
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001527static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1528 struct ethtool_pauseparam *pause)
1529{
1530 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1531
1532 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1533 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1534}
1535
1536static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1537 struct ethtool_pauseparam *pause)
1538{
1539 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1540
1541 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1542 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1543 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1544
1545 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1546 pfcc_pl);
1547}
1548
1549static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1550 struct ethtool_pauseparam *pause)
1551{
1552 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1553 bool pause_en = pause->tx_pause || pause->rx_pause;
1554 int err;
1555
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001556 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1557 netdev_err(dev, "PFC already enabled on port\n");
1558 return -EINVAL;
1559 }
1560
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001561 if (pause->autoneg) {
1562 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1563 return -EINVAL;
1564 }
1565
1566 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1567 if (err) {
1568 netdev_err(dev, "Failed to configure port's headroom\n");
1569 return err;
1570 }
1571
1572 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1573 if (err) {
1574 netdev_err(dev, "Failed to set PAUSE parameters\n");
1575 goto err_port_pause_configure;
1576 }
1577
1578 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1579 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1580
1581 return 0;
1582
1583err_port_pause_configure:
1584 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1585 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1586 return err;
1587}
1588
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001589struct mlxsw_sp_port_hw_stats {
1590 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001591 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001592 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001593};
1594
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001595static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001596 {
1597 .str = "a_frames_transmitted_ok",
1598 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1599 },
1600 {
1601 .str = "a_frames_received_ok",
1602 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1603 },
1604 {
1605 .str = "a_frame_check_sequence_errors",
1606 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1607 },
1608 {
1609 .str = "a_alignment_errors",
1610 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1611 },
1612 {
1613 .str = "a_octets_transmitted_ok",
1614 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1615 },
1616 {
1617 .str = "a_octets_received_ok",
1618 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1619 },
1620 {
1621 .str = "a_multicast_frames_xmitted_ok",
1622 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1623 },
1624 {
1625 .str = "a_broadcast_frames_xmitted_ok",
1626 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1627 },
1628 {
1629 .str = "a_multicast_frames_received_ok",
1630 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1631 },
1632 {
1633 .str = "a_broadcast_frames_received_ok",
1634 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1635 },
1636 {
1637 .str = "a_in_range_length_errors",
1638 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1639 },
1640 {
1641 .str = "a_out_of_range_length_field",
1642 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1643 },
1644 {
1645 .str = "a_frame_too_long_errors",
1646 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1647 },
1648 {
1649 .str = "a_symbol_error_during_carrier",
1650 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1651 },
1652 {
1653 .str = "a_mac_control_frames_transmitted",
1654 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1655 },
1656 {
1657 .str = "a_mac_control_frames_received",
1658 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1659 },
1660 {
1661 .str = "a_unsupported_opcodes_received",
1662 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1663 },
1664 {
1665 .str = "a_pause_mac_ctrl_frames_received",
1666 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1667 },
1668 {
1669 .str = "a_pause_mac_ctrl_frames_xmitted",
1670 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1671 },
1672};
1673
1674#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1675
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001676static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1677 {
1678 .str = "rx_octets_prio",
1679 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1680 },
1681 {
1682 .str = "rx_frames_prio",
1683 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1684 },
1685 {
1686 .str = "tx_octets_prio",
1687 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1688 },
1689 {
1690 .str = "tx_frames_prio",
1691 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1692 },
1693 {
1694 .str = "rx_pause_prio",
1695 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1696 },
1697 {
1698 .str = "rx_pause_duration_prio",
1699 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1700 },
1701 {
1702 .str = "tx_pause_prio",
1703 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1704 },
1705 {
1706 .str = "tx_pause_duration_prio",
1707 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1708 },
1709};
1710
1711#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1712
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001713static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1714 {
1715 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001716 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1717 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001718 },
1719 {
1720 .str = "tc_no_buffer_discard_uc_tc",
1721 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1722 },
1723};
1724
1725#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1726
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001727#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001728 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1729 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001730 IEEE_8021QAZ_MAX_TCS)
1731
1732static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1733{
1734 int i;
1735
1736 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1737 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1738 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1739 *p += ETH_GSTRING_LEN;
1740 }
1741}
1742
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001743static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1744{
1745 int i;
1746
1747 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1748 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1749 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1750 *p += ETH_GSTRING_LEN;
1751 }
1752}
1753
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001754static void mlxsw_sp_port_get_strings(struct net_device *dev,
1755 u32 stringset, u8 *data)
1756{
1757 u8 *p = data;
1758 int i;
1759
1760 switch (stringset) {
1761 case ETH_SS_STATS:
1762 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1763 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1764 ETH_GSTRING_LEN);
1765 p += ETH_GSTRING_LEN;
1766 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001767
1768 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1769 mlxsw_sp_port_get_prio_strings(&p, i);
1770
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001771 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1772 mlxsw_sp_port_get_tc_strings(&p, i);
1773
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001774 break;
1775 }
1776}
1777
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001778static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1779 enum ethtool_phys_id_state state)
1780{
1781 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1782 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1783 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1784 bool active;
1785
1786 switch (state) {
1787 case ETHTOOL_ID_ACTIVE:
1788 active = true;
1789 break;
1790 case ETHTOOL_ID_INACTIVE:
1791 active = false;
1792 break;
1793 default:
1794 return -EOPNOTSUPP;
1795 }
1796
1797 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1798 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1799}
1800
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001801static int
1802mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1803 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1804{
1805 switch (grp) {
1806 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1807 *p_hw_stats = mlxsw_sp_port_hw_stats;
1808 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1809 break;
1810 case MLXSW_REG_PPCNT_PRIO_CNT:
1811 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1812 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1813 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001814 case MLXSW_REG_PPCNT_TC_CNT:
1815 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1816 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1817 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001818 default:
1819 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01001820 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001821 }
1822 return 0;
1823}
1824
1825static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1826 enum mlxsw_reg_ppcnt_grp grp, int prio,
1827 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001828{
Ido Schimmel18281f22017-03-24 08:02:51 +01001829 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001831 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001832 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001833 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001834 int err;
1835
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001836 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1837 if (err)
1838 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001839 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01001840 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01001841 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01001842 if (!hw_stats[i].cells_bytes)
1843 continue;
1844 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
1845 data[data_index + i]);
1846 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001847}
1848
1849static void mlxsw_sp_port_get_stats(struct net_device *dev,
1850 struct ethtool_stats *stats, u64 *data)
1851{
1852 int i, data_index = 0;
1853
1854 /* IEEE 802.3 Counters */
1855 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1856 data, data_index);
1857 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1858
1859 /* Per-Priority Counters */
1860 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1861 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1862 data, data_index);
1863 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1864 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001865
1866 /* Per-TC Counters */
1867 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1868 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1869 data, data_index);
1870 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1871 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001872}
1873
1874static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1875{
1876 switch (sset) {
1877 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001878 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001879 default:
1880 return -EOPNOTSUPP;
1881 }
1882}
1883
1884struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001885 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001886 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001887 u32 speed;
1888};
1889
1890static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1891 {
1892 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001893 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1894 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001895 },
1896 {
1897 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1898 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001899 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1900 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001901 },
1902 {
1903 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001904 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1905 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001906 },
1907 {
1908 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1909 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001910 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1911 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001912 },
1913 {
1914 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1915 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1916 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1917 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001918 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1919 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001920 },
1921 {
1922 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001923 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1924 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001925 },
1926 {
1927 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001928 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1929 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001930 },
1931 {
1932 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001933 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1934 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001935 },
1936 {
1937 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001938 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1939 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001940 },
1941 {
1942 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001943 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1944 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001945 },
1946 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001947 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1948 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1949 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001950 },
1951 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001952 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1953 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1954 .speed = SPEED_25000,
1955 },
1956 {
1957 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1958 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1959 .speed = SPEED_25000,
1960 },
1961 {
1962 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1963 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1964 .speed = SPEED_25000,
1965 },
1966 {
1967 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1968 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1969 .speed = SPEED_50000,
1970 },
1971 {
1972 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1973 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1974 .speed = SPEED_50000,
1975 },
1976 {
1977 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1978 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1979 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001980 },
1981 {
1982 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001983 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1984 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001985 },
1986 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001987 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1988 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1989 .speed = SPEED_56000,
1990 },
1991 {
1992 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1993 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1994 .speed = SPEED_56000,
1995 },
1996 {
1997 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1998 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1999 .speed = SPEED_56000,
2000 },
2001 {
2002 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2003 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2004 .speed = SPEED_100000,
2005 },
2006 {
2007 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2008 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2009 .speed = SPEED_100000,
2010 },
2011 {
2012 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2013 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2014 .speed = SPEED_100000,
2015 },
2016 {
2017 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2018 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2019 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002020 },
2021};
2022
2023#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2024
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002025static void
2026mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2027 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002028{
2029 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2030 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2031 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2032 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2033 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2034 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002035 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002036
2037 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2038 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2039 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2040 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2041 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002042 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002043}
2044
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002045static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002046{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002047 int i;
2048
2049 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2050 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002051 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2052 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002053 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002054}
2055
2056static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002057 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002058{
2059 u32 speed = SPEED_UNKNOWN;
2060 u8 duplex = DUPLEX_UNKNOWN;
2061 int i;
2062
2063 if (!carrier_ok)
2064 goto out;
2065
2066 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2067 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2068 speed = mlxsw_sp_port_link_mode[i].speed;
2069 duplex = DUPLEX_FULL;
2070 break;
2071 }
2072 }
2073out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002074 cmd->base.speed = speed;
2075 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002076}
2077
2078static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2079{
2080 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2081 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2082 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2083 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2084 return PORT_FIBRE;
2085
2086 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2087 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2088 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2089 return PORT_DA;
2090
2091 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2092 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2093 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2094 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2095 return PORT_NONE;
2096
2097 return PORT_OTHER;
2098}
2099
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002100static u32
2101mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002102{
2103 u32 ptys_proto = 0;
2104 int i;
2105
2106 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002107 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2108 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002109 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2110 }
2111 return ptys_proto;
2112}
2113
2114static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2115{
2116 u32 ptys_proto = 0;
2117 int i;
2118
2119 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2120 if (speed == mlxsw_sp_port_link_mode[i].speed)
2121 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2122 }
2123 return ptys_proto;
2124}
2125
Ido Schimmel18f1e702016-02-26 17:32:31 +01002126static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2127{
2128 u32 ptys_proto = 0;
2129 int i;
2130
2131 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2132 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2133 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2134 }
2135 return ptys_proto;
2136}
2137
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002138static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2139 struct ethtool_link_ksettings *cmd)
2140{
2141 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2142 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2143 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2144
2145 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2146 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2147}
2148
2149static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2150 struct ethtool_link_ksettings *cmd)
2151{
2152 if (!autoneg)
2153 return;
2154
2155 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2156 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2157}
2158
2159static void
2160mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2161 struct ethtool_link_ksettings *cmd)
2162{
2163 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2164 return;
2165
2166 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2167 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2168}
2169
2170static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2171 struct ethtool_link_ksettings *cmd)
2172{
2173 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2174 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2175 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2176 char ptys_pl[MLXSW_REG_PTYS_LEN];
2177 u8 autoneg_status;
2178 bool autoneg;
2179 int err;
2180
2181 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002182 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2184 if (err)
2185 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002186 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2187 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002188
2189 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2190
2191 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2192
2193 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2194 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2195 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2196
2197 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2198 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2199 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2200 cmd);
2201
2202 return 0;
2203}
2204
2205static int
2206mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2207 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002208{
2209 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2211 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002212 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002213 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002214 int err;
2215
Elad Raz401c8b42016-10-28 21:35:52 +02002216 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002217 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002218 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002219 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002220 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002221
2222 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2223 eth_proto_new = autoneg ?
2224 mlxsw_sp_to_ptys_advert_link(cmd) :
2225 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002226
2227 eth_proto_new = eth_proto_new & eth_proto_cap;
2228 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002229 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002230 return -EINVAL;
2231 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002232
Elad Raz401c8b42016-10-28 21:35:52 +02002233 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2234 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002235 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002236 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002237 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002238
Ido Schimmel6277d462016-07-15 11:14:58 +02002239 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002240 return 0;
2241
Ido Schimmel0c83f882016-09-12 13:26:23 +02002242 mlxsw_sp_port->link.autoneg = autoneg;
2243
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002244 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2245 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002246
2247 return 0;
2248}
2249
2250static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2251 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2252 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002253 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2254 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002255 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002256 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002257 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2258 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002259 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2260 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002261};
2262
Ido Schimmel18f1e702016-02-26 17:32:31 +01002263static int
2264mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2265{
2266 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2267 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2268 char ptys_pl[MLXSW_REG_PTYS_LEN];
2269 u32 eth_proto_admin;
2270
2271 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002272 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2273 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002274 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2275}
2276
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002277int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2278 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2279 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002280{
2281 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2282 char qeec_pl[MLXSW_REG_QEEC_LEN];
2283
2284 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2285 next_index);
2286 mlxsw_reg_qeec_de_set(qeec_pl, true);
2287 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2288 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2289 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2290}
2291
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002292int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2293 enum mlxsw_reg_qeec_hr hr, u8 index,
2294 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002295{
2296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2297 char qeec_pl[MLXSW_REG_QEEC_LEN];
2298
2299 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2300 next_index);
2301 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2302 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2303 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2304}
2305
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002306int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2307 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002308{
2309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2310 char qtct_pl[MLXSW_REG_QTCT_LEN];
2311
2312 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2313 tclass);
2314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2315}
2316
2317static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2318{
2319 int err, i;
2320
2321 /* Setup the elements hierarcy, so that each TC is linked to
2322 * one subgroup, which are all member in the same group.
2323 */
2324 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2325 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2326 0);
2327 if (err)
2328 return err;
2329 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2330 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2331 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2332 0, false, 0);
2333 if (err)
2334 return err;
2335 }
2336 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2337 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2338 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2339 false, 0);
2340 if (err)
2341 return err;
2342 }
2343
2344 /* Make sure the max shaper is disabled in all hierarcies that
2345 * support it.
2346 */
2347 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2348 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2349 MLXSW_REG_QEEC_MAS_DIS);
2350 if (err)
2351 return err;
2352 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2353 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2354 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2355 i, 0,
2356 MLXSW_REG_QEEC_MAS_DIS);
2357 if (err)
2358 return err;
2359 }
2360 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2361 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2362 MLXSW_REG_QEEC_HIERARCY_TC,
2363 i, i,
2364 MLXSW_REG_QEEC_MAS_DIS);
2365 if (err)
2366 return err;
2367 }
2368
2369 /* Map all priorities to traffic class 0. */
2370 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2371 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2372 if (err)
2373 return err;
2374 }
2375
2376 return 0;
2377}
2378
Ido Schimmel05978482016-08-17 16:39:30 +02002379static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2380{
2381 mlxsw_sp_port->pvid = 1;
2382
2383 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2384}
2385
2386static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2387{
2388 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2389}
2390
Jiri Pirko67963a32016-10-28 21:35:55 +02002391static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2392 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002393{
2394 struct mlxsw_sp_port *mlxsw_sp_port;
2395 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002396 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397 int err;
2398
2399 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2400 if (!dev)
2401 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002402 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002403 mlxsw_sp_port = netdev_priv(dev);
2404 mlxsw_sp_port->dev = dev;
2405 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2406 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002407 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002408 mlxsw_sp_port->mapping.module = module;
2409 mlxsw_sp_port->mapping.width = width;
2410 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002411 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002412 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2413 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2414 if (!mlxsw_sp_port->active_vlans) {
2415 err = -ENOMEM;
2416 goto err_port_active_vlans_alloc;
2417 }
Elad Razfc1273a2016-01-06 13:01:11 +01002418 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2419 if (!mlxsw_sp_port->untagged_vlans) {
2420 err = -ENOMEM;
2421 goto err_port_untagged_vlans_alloc;
2422 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002423 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002424 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002425
2426 mlxsw_sp_port->pcpu_stats =
2427 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2428 if (!mlxsw_sp_port->pcpu_stats) {
2429 err = -ENOMEM;
2430 goto err_alloc_stats;
2431 }
2432
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002433 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2434 GFP_KERNEL);
2435 if (!mlxsw_sp_port->sample) {
2436 err = -ENOMEM;
2437 goto err_alloc_sample;
2438 }
2439
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002440 mlxsw_sp_port->hw_stats.cache =
2441 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2442
2443 if (!mlxsw_sp_port->hw_stats.cache) {
2444 err = -ENOMEM;
2445 goto err_alloc_hw_stats;
2446 }
2447 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2448 &update_stats_cache);
2449
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002450 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2451 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2452
Ido Schimmel3247ff22016-09-08 08:16:02 +02002453 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2454 if (err) {
2455 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2456 mlxsw_sp_port->local_port);
2457 goto err_port_swid_set;
2458 }
2459
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002460 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2461 if (err) {
2462 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2463 mlxsw_sp_port->local_port);
2464 goto err_dev_addr_init;
2465 }
2466
2467 netif_carrier_off(dev);
2468
2469 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002470 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2471 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002472
Jarod Wilsond894be52016-10-20 13:55:16 -04002473 dev->min_mtu = 0;
2474 dev->max_mtu = ETH_MAX_MTU;
2475
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002476 /* Each packet needs to have a Tx header (metadata) on top all other
2477 * headers.
2478 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002479 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002480
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002481 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2482 if (err) {
2483 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2484 mlxsw_sp_port->local_port);
2485 goto err_port_system_port_mapping_set;
2486 }
2487
Ido Schimmel18f1e702016-02-26 17:32:31 +01002488 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2489 if (err) {
2490 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2491 mlxsw_sp_port->local_port);
2492 goto err_port_speed_by_width_set;
2493 }
2494
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002495 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2496 if (err) {
2497 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2498 mlxsw_sp_port->local_port);
2499 goto err_port_mtu_set;
2500 }
2501
2502 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2503 if (err)
2504 goto err_port_admin_status_set;
2505
2506 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2507 if (err) {
2508 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2509 mlxsw_sp_port->local_port);
2510 goto err_port_buffers_init;
2511 }
2512
Ido Schimmel90183b92016-04-06 17:10:08 +02002513 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2514 if (err) {
2515 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2516 mlxsw_sp_port->local_port);
2517 goto err_port_ets_init;
2518 }
2519
Ido Schimmelf00817d2016-04-06 17:10:09 +02002520 /* ETS and buffers must be initialized before DCB. */
2521 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2522 if (err) {
2523 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2524 mlxsw_sp_port->local_port);
2525 goto err_port_dcb_init;
2526 }
2527
Ido Schimmel05978482016-08-17 16:39:30 +02002528 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2529 if (err) {
2530 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2531 mlxsw_sp_port->local_port);
2532 goto err_port_pvid_vport_create;
2533 }
2534
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002535 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002536 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002537 err = register_netdev(dev);
2538 if (err) {
2539 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2540 mlxsw_sp_port->local_port);
2541 goto err_register_netdev;
2542 }
2543
Elad Razd808c7e2016-10-28 21:35:57 +02002544 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2545 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2546 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002547 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002548 return 0;
2549
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002550err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002551 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002552 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002553 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2554err_port_pvid_vport_create:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002555 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002556err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002557err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002558err_port_buffers_init:
2559err_port_admin_status_set:
2560err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002561err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002562err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002563err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002564 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2565err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002566 kfree(mlxsw_sp_port->hw_stats.cache);
2567err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002568 kfree(mlxsw_sp_port->sample);
2569err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002570 free_percpu(mlxsw_sp_port->pcpu_stats);
2571err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01002572 kfree(mlxsw_sp_port->untagged_vlans);
2573err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002574 kfree(mlxsw_sp_port->active_vlans);
2575err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002576 free_netdev(dev);
2577 return err;
2578}
2579
Jiri Pirko67963a32016-10-28 21:35:55 +02002580static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2581 bool split, u8 module, u8 width, u8 lane)
2582{
2583 int err;
2584
2585 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2586 if (err) {
2587 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2588 local_port);
2589 return err;
2590 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002591 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002592 module, width, lane);
2593 if (err)
2594 goto err_port_create;
2595 return 0;
2596
2597err_port_create:
2598 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2599 return err;
2600}
2601
2602static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002603{
2604 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2605
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002606 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002607 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002608 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002609 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002610 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002611 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002612 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002613 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2614 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002615 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002616 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002617 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01002618 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002619 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02002620 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002621 free_netdev(mlxsw_sp_port->dev);
2622}
2623
Jiri Pirko67963a32016-10-28 21:35:55 +02002624static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2625{
2626 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2627 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2628}
2629
Jiri Pirkof83e2102016-10-28 21:35:49 +02002630static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2631{
2632 return mlxsw_sp->ports[local_port] != NULL;
2633}
2634
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002635static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2636{
2637 int i;
2638
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002639 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002640 if (mlxsw_sp_port_created(mlxsw_sp, i))
2641 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002642 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002643 kfree(mlxsw_sp->ports);
2644}
2645
2646static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2647{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002648 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002649 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002650 size_t alloc_size;
2651 int i;
2652 int err;
2653
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002654 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002655 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2656 if (!mlxsw_sp->ports)
2657 return -ENOMEM;
2658
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002659 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2660 if (!mlxsw_sp->port_to_module) {
2661 err = -ENOMEM;
2662 goto err_port_to_module_alloc;
2663 }
2664
2665 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002666 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002667 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002668 if (err)
2669 goto err_port_module_info_get;
2670 if (!width)
2671 continue;
2672 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002673 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2674 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002675 if (err)
2676 goto err_port_create;
2677 }
2678 return 0;
2679
2680err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002681err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002682 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002683 if (mlxsw_sp_port_created(mlxsw_sp, i))
2684 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002685 kfree(mlxsw_sp->port_to_module);
2686err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002687 kfree(mlxsw_sp->ports);
2688 return err;
2689}
2690
Ido Schimmel18f1e702016-02-26 17:32:31 +01002691static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2692{
2693 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2694
2695 return local_port - offset;
2696}
2697
Ido Schimmelbe945352016-06-09 09:51:39 +02002698static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2699 u8 module, unsigned int count)
2700{
2701 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2702 int err, i;
2703
2704 for (i = 0; i < count; i++) {
2705 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2706 width, i * width);
2707 if (err)
2708 goto err_port_module_map;
2709 }
2710
2711 for (i = 0; i < count; i++) {
2712 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2713 if (err)
2714 goto err_port_swid_set;
2715 }
2716
2717 for (i = 0; i < count; i++) {
2718 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02002719 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02002720 if (err)
2721 goto err_port_create;
2722 }
2723
2724 return 0;
2725
2726err_port_create:
2727 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002728 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2729 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02002730 i = count;
2731err_port_swid_set:
2732 for (i--; i >= 0; i--)
2733 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2734 MLXSW_PORT_SWID_DISABLED_PORT);
2735 i = count;
2736err_port_module_map:
2737 for (i--; i >= 0; i--)
2738 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2739 return err;
2740}
2741
2742static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2743 u8 base_port, unsigned int count)
2744{
2745 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2746 int i;
2747
2748 /* Split by four means we need to re-create two ports, otherwise
2749 * only one.
2750 */
2751 count = count / 2;
2752
2753 for (i = 0; i < count; i++) {
2754 local_port = base_port + i * 2;
2755 module = mlxsw_sp->port_to_module[local_port];
2756
2757 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2758 0);
2759 }
2760
2761 for (i = 0; i < count; i++)
2762 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2763
2764 for (i = 0; i < count; i++) {
2765 local_port = base_port + i * 2;
2766 module = mlxsw_sp->port_to_module[local_port];
2767
2768 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002769 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02002770 }
2771}
2772
Jiri Pirkob2f10572016-04-08 19:11:23 +02002773static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2774 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002775{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002776 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002777 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002778 u8 module, cur_width, base_port;
2779 int i;
2780 int err;
2781
2782 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2783 if (!mlxsw_sp_port) {
2784 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2785 local_port);
2786 return -EINVAL;
2787 }
2788
Ido Schimmeld664b412016-06-09 09:51:40 +02002789 module = mlxsw_sp_port->mapping.module;
2790 cur_width = mlxsw_sp_port->mapping.width;
2791
Ido Schimmel18f1e702016-02-26 17:32:31 +01002792 if (count != 2 && count != 4) {
2793 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2794 return -EINVAL;
2795 }
2796
Ido Schimmel18f1e702016-02-26 17:32:31 +01002797 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2798 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2799 return -EINVAL;
2800 }
2801
2802 /* Make sure we have enough slave (even) ports for the split. */
2803 if (count == 2) {
2804 base_port = local_port;
2805 if (mlxsw_sp->ports[base_port + 1]) {
2806 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2807 return -EINVAL;
2808 }
2809 } else {
2810 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2811 if (mlxsw_sp->ports[base_port + 1] ||
2812 mlxsw_sp->ports[base_port + 3]) {
2813 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2814 return -EINVAL;
2815 }
2816 }
2817
2818 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002819 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2820 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002821
Ido Schimmelbe945352016-06-09 09:51:39 +02002822 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2823 if (err) {
2824 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2825 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002826 }
2827
2828 return 0;
2829
Ido Schimmelbe945352016-06-09 09:51:39 +02002830err_port_split_create:
2831 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002832 return err;
2833}
2834
Jiri Pirkob2f10572016-04-08 19:11:23 +02002835static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002836{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002837 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002838 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002839 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002840 unsigned int count;
2841 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002842
2843 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2844 if (!mlxsw_sp_port) {
2845 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2846 local_port);
2847 return -EINVAL;
2848 }
2849
2850 if (!mlxsw_sp_port->split) {
2851 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2852 return -EINVAL;
2853 }
2854
Ido Schimmeld664b412016-06-09 09:51:40 +02002855 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002856 count = cur_width == 1 ? 4 : 2;
2857
2858 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2859
2860 /* Determine which ports to remove. */
2861 if (count == 2 && local_port >= base_port + 2)
2862 base_port = base_port + 2;
2863
2864 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002865 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2866 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002867
Ido Schimmelbe945352016-06-09 09:51:39 +02002868 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002869
2870 return 0;
2871}
2872
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002873static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2874 char *pude_pl, void *priv)
2875{
2876 struct mlxsw_sp *mlxsw_sp = priv;
2877 struct mlxsw_sp_port *mlxsw_sp_port;
2878 enum mlxsw_reg_pude_oper_status status;
2879 u8 local_port;
2880
2881 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2882 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002883 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002884 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002885
2886 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2887 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2888 netdev_info(mlxsw_sp_port->dev, "link up\n");
2889 netif_carrier_on(mlxsw_sp_port->dev);
2890 } else {
2891 netdev_info(mlxsw_sp_port->dev, "link down\n");
2892 netif_carrier_off(mlxsw_sp_port->dev);
2893 }
2894}
2895
Nogah Frankel14eeda92016-11-25 10:33:32 +01002896static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2897 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002898{
2899 struct mlxsw_sp *mlxsw_sp = priv;
2900 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2901 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2902
2903 if (unlikely(!mlxsw_sp_port)) {
2904 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2905 local_port);
2906 return;
2907 }
2908
2909 skb->dev = mlxsw_sp_port->dev;
2910
2911 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2912 u64_stats_update_begin(&pcpu_stats->syncp);
2913 pcpu_stats->rx_packets++;
2914 pcpu_stats->rx_bytes += skb->len;
2915 u64_stats_update_end(&pcpu_stats->syncp);
2916
2917 skb->protocol = eth_type_trans(skb, skb->dev);
2918 netif_receive_skb(skb);
2919}
2920
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02002921static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2922 void *priv)
2923{
2924 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01002925 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02002926}
2927
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002928static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
2929 void *priv)
2930{
2931 struct mlxsw_sp *mlxsw_sp = priv;
2932 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2933 struct psample_group *psample_group;
2934 u32 size;
2935
2936 if (unlikely(!mlxsw_sp_port)) {
2937 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
2938 local_port);
2939 goto out;
2940 }
2941 if (unlikely(!mlxsw_sp_port->sample)) {
2942 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
2943 local_port);
2944 goto out;
2945 }
2946
2947 size = mlxsw_sp_port->sample->truncate ?
2948 mlxsw_sp_port->sample->trunc_size : skb->len;
2949
2950 rcu_read_lock();
2951 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
2952 if (!psample_group)
2953 goto out_unlock;
2954 psample_sample_packet(psample_group, skb, size,
2955 mlxsw_sp_port->dev->ifindex, 0,
2956 mlxsw_sp_port->sample->rate);
2957out_unlock:
2958 rcu_read_unlock();
2959out:
2960 consume_skb(skb);
2961}
2962
Nogah Frankel117b0da2016-11-25 10:33:44 +01002963#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01002964 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01002965 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02002966
Nogah Frankel117b0da2016-11-25 10:33:44 +01002967#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01002968 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01002969 _is_ctrl, SP_##_trap_group, DISCARD)
2970
2971#define MLXSW_SP_EVENTL(_func, _trap_id) \
2972 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01002973
Nogah Frankel45449132016-11-25 10:33:35 +01002974static const struct mlxsw_listener mlxsw_sp_listener[] = {
2975 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01002976 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01002977 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01002978 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
2979 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
2980 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
2981 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
2982 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
2983 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
2984 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
2985 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
2986 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
2987 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
2988 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02002989 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01002990 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2991 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2992 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2993 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
2994 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
2995 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
2996 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
2997 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002998 /* PKT Sample trap */
2999 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3000 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003001};
3002
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003003static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3004{
3005 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3006 enum mlxsw_reg_qpcr_ir_units ir_units;
3007 int max_cpu_policers;
3008 bool is_bytes;
3009 u8 burst_size;
3010 u32 rate;
3011 int i, err;
3012
3013 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3014 return -EIO;
3015
3016 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3017
3018 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3019 for (i = 0; i < max_cpu_policers; i++) {
3020 is_bytes = false;
3021 switch (i) {
3022 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3023 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3024 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3025 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3026 rate = 128;
3027 burst_size = 7;
3028 break;
3029 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3030 rate = 16 * 1024;
3031 burst_size = 10;
3032 break;
3033 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3034 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3035 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3036 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3037 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3038 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3039 rate = 1024;
3040 burst_size = 7;
3041 break;
3042 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3043 is_bytes = true;
3044 rate = 4 * 1024;
3045 burst_size = 4;
3046 break;
3047 default:
3048 continue;
3049 }
3050
3051 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3052 burst_size);
3053 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3054 if (err)
3055 return err;
3056 }
3057
3058 return 0;
3059}
3060
Nogah Frankel579c82e2016-11-25 10:33:42 +01003061static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003062{
3063 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003064 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003065 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003066 int max_trap_groups;
3067 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003068 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003069 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003070
3071 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3072 return -EIO;
3073
3074 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003075 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003076
3077 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003078 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003079 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003080 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3081 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3082 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3083 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3084 priority = 5;
3085 tc = 5;
3086 break;
3087 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3088 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3089 priority = 4;
3090 tc = 4;
3091 break;
3092 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3093 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3094 priority = 3;
3095 tc = 3;
3096 break;
3097 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3098 priority = 2;
3099 tc = 2;
3100 break;
3101 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3102 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3103 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3104 priority = 1;
3105 tc = 1;
3106 break;
3107 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003108 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3109 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003110 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003111 break;
3112 default:
3113 continue;
3114 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003115
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003116 if (max_cpu_policers <= policer_id &&
3117 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3118 return -EIO;
3119
3120 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003121 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3122 if (err)
3123 return err;
3124 }
3125
3126 return 0;
3127}
3128
3129static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3130{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003131 int i;
3132 int err;
3133
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003134 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3135 if (err)
3136 return err;
3137
Nogah Frankel579c82e2016-11-25 10:33:42 +01003138 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003139 if (err)
3140 return err;
3141
Nogah Frankel45449132016-11-25 10:33:35 +01003142 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003143 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003144 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003145 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003146 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003147 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003148
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003149 }
3150 return 0;
3151
Nogah Frankel45449132016-11-25 10:33:35 +01003152err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003153 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003154 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003155 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003156 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003157 }
3158 return err;
3159}
3160
3161static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3162{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003163 int i;
3164
Nogah Frankel45449132016-11-25 10:33:35 +01003165 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003166 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003167 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003168 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003169 }
3170}
3171
3172static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3173 enum mlxsw_reg_sfgc_type type,
3174 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3175{
3176 enum mlxsw_flood_table_type table_type;
3177 enum mlxsw_sp_flood_table flood_table;
3178 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3179
Ido Schimmel19ae6122015-12-15 16:03:39 +01003180 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003181 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003182 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003183 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003184
Nogah Frankel71c365b2017-02-09 14:54:46 +01003185 switch (type) {
3186 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003187 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003188 break;
3189 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003190 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3191 break;
3192 default:
3193 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3194 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003195
3196 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3197 flood_table);
3198 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3199}
3200
3201static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3202{
3203 int type, err;
3204
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003205 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3206 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3207 continue;
3208
3209 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3210 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3211 if (err)
3212 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003213
3214 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3215 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3216 if (err)
3217 return err;
3218 }
3219
3220 return 0;
3221}
3222
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003223static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3224{
3225 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003226 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003227
3228 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3229 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3230 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3231 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3232 MLXSW_REG_SLCR_LAG_HASH_SIP |
3233 MLXSW_REG_SLCR_LAG_HASH_DIP |
3234 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3235 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3236 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003237 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3238 if (err)
3239 return err;
3240
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003241 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3242 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003243 return -EIO;
3244
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003245 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003246 sizeof(struct mlxsw_sp_upper),
3247 GFP_KERNEL);
3248 if (!mlxsw_sp->lags)
3249 return -ENOMEM;
3250
3251 return 0;
3252}
3253
3254static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3255{
3256 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003257}
3258
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003259static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3260{
3261 char htgt_pl[MLXSW_REG_HTGT_LEN];
3262
Nogah Frankel579c82e2016-11-25 10:33:42 +01003263 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3264 MLXSW_REG_HTGT_INVALID_POLICER,
3265 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3266 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003267 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3268}
3269
Jiri Pirkob2f10572016-04-08 19:11:23 +02003270static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003271 const struct mlxsw_bus_info *mlxsw_bus_info)
3272{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003273 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003274 int err;
3275
3276 mlxsw_sp->core = mlxsw_core;
3277 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003278 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003279 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01003280 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003281
3282 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3283 if (err) {
3284 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3285 return err;
3286 }
3287
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003288 err = mlxsw_sp_traps_init(mlxsw_sp);
3289 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003290 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3291 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003292 }
3293
3294 err = mlxsw_sp_flood_init(mlxsw_sp);
3295 if (err) {
3296 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3297 goto err_flood_init;
3298 }
3299
3300 err = mlxsw_sp_buffers_init(mlxsw_sp);
3301 if (err) {
3302 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3303 goto err_buffers_init;
3304 }
3305
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003306 err = mlxsw_sp_lag_init(mlxsw_sp);
3307 if (err) {
3308 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3309 goto err_lag_init;
3310 }
3311
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003312 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3313 if (err) {
3314 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3315 goto err_switchdev_init;
3316 }
3317
Ido Schimmel464dce12016-07-02 11:00:15 +02003318 err = mlxsw_sp_router_init(mlxsw_sp);
3319 if (err) {
3320 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3321 goto err_router_init;
3322 }
3323
Yotam Gigi763b4b72016-07-21 12:03:17 +02003324 err = mlxsw_sp_span_init(mlxsw_sp);
3325 if (err) {
3326 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3327 goto err_span_init;
3328 }
3329
Jiri Pirko22a67762017-02-03 10:29:07 +01003330 err = mlxsw_sp_acl_init(mlxsw_sp);
3331 if (err) {
3332 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3333 goto err_acl_init;
3334 }
3335
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003336 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3337 if (err) {
3338 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3339 goto err_counter_pool_init;
3340 }
3341
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003342 err = mlxsw_sp_ports_create(mlxsw_sp);
3343 if (err) {
3344 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3345 goto err_ports_create;
3346 }
3347
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003348 return 0;
3349
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003350err_ports_create:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003351 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3352err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003353 mlxsw_sp_acl_fini(mlxsw_sp);
3354err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003355 mlxsw_sp_span_fini(mlxsw_sp);
3356err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003357 mlxsw_sp_router_fini(mlxsw_sp);
3358err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003359 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003360err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003361 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003362err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003363 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003364err_buffers_init:
3365err_flood_init:
3366 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003367 return err;
3368}
3369
Jiri Pirkob2f10572016-04-08 19:11:23 +02003370static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003371{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003372 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003373
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003374 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003375 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003376 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003377 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003378 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003379 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003380 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003381 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003382 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003383 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003384 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003385}
3386
3387static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3388 .used_max_vepa_channels = 1,
3389 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003390 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003391 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003392 .used_max_pgt = 1,
3393 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003394 .used_flood_tables = 1,
3395 .used_flood_mode = 1,
3396 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003397 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003398 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003399 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003400 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003401 .used_max_ib_mc = 1,
3402 .max_ib_mc = 0,
3403 .used_max_pkey = 1,
3404 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003405 .used_kvd_split_data = 1,
3406 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3407 .kvd_hash_single_parts = 2,
3408 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003409 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003410 .swid_config = {
3411 {
3412 .used_type = 1,
3413 .type = MLXSW_PORT_SWID_TYPE_ETH,
3414 }
3415 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003416 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003417};
3418
3419static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003420 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003421 .priv_size = sizeof(struct mlxsw_sp),
3422 .init = mlxsw_sp_init,
3423 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003424 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003425 .port_split = mlxsw_sp_port_split,
3426 .port_unsplit = mlxsw_sp_port_unsplit,
3427 .sb_pool_get = mlxsw_sp_sb_pool_get,
3428 .sb_pool_set = mlxsw_sp_sb_pool_set,
3429 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3430 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3431 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3432 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3433 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3434 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3435 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3436 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3437 .txhdr_construct = mlxsw_sp_txhdr_construct,
3438 .txhdr_len = MLXSW_TXHDR_LEN,
3439 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003440};
3441
Jiri Pirko22a67762017-02-03 10:29:07 +01003442bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003443{
3444 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3445}
3446
Jiri Pirko1182e532017-03-06 21:25:20 +01003447static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003448{
Jiri Pirko1182e532017-03-06 21:25:20 +01003449 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003450 int ret = 0;
3451
3452 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003453 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003454 ret = 1;
3455 }
3456
3457 return ret;
3458}
3459
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003460static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3461{
Jiri Pirko1182e532017-03-06 21:25:20 +01003462 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003463
3464 if (mlxsw_sp_port_dev_check(dev))
3465 return netdev_priv(dev);
3466
Jiri Pirko1182e532017-03-06 21:25:20 +01003467 mlxsw_sp_port = NULL;
3468 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003469
Jiri Pirko1182e532017-03-06 21:25:20 +01003470 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003471}
3472
Ido Schimmel4724ba562017-03-10 08:53:39 +01003473struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003474{
3475 struct mlxsw_sp_port *mlxsw_sp_port;
3476
3477 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3478 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3479}
3480
3481static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3482{
Jiri Pirko1182e532017-03-06 21:25:20 +01003483 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003484
3485 if (mlxsw_sp_port_dev_check(dev))
3486 return netdev_priv(dev);
3487
Jiri Pirko1182e532017-03-06 21:25:20 +01003488 mlxsw_sp_port = NULL;
3489 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3490 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003491
Jiri Pirko1182e532017-03-06 21:25:20 +01003492 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003493}
3494
3495struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3496{
3497 struct mlxsw_sp_port *mlxsw_sp_port;
3498
3499 rcu_read_lock();
3500 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3501 if (mlxsw_sp_port)
3502 dev_hold(mlxsw_sp_port->dev);
3503 rcu_read_unlock();
3504 return mlxsw_sp_port;
3505}
3506
3507void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3508{
3509 dev_put(mlxsw_sp_port->dev);
3510}
3511
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003512static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3513 u16 fid)
3514{
3515 if (mlxsw_sp_fid_is_vfid(fid))
3516 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3517 else
3518 return test_bit(fid, lag_port->active_vlans);
3519}
3520
3521static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3522 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003523{
3524 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003525 u8 local_port = mlxsw_sp_port->local_port;
3526 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003527 u64 max_lag_members;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003528 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003529
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003530 if (!mlxsw_sp_port->lagged)
3531 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003532
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003533 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3534 MAX_LAG_MEMBERS);
3535 for (i = 0; i < max_lag_members; i++) {
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003536 struct mlxsw_sp_port *lag_port;
3537
3538 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3539 if (!lag_port || lag_port->local_port == local_port)
3540 continue;
3541 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3542 count++;
3543 }
3544
3545 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003546}
3547
3548static int
3549mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3550 u16 fid)
3551{
3552 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3553 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3554
3555 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3556 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3557 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3558 mlxsw_sp_port->local_port);
3559
Ido Schimmel22305372016-06-20 23:04:21 +02003560 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3561 mlxsw_sp_port->local_port, fid);
3562
Ido Schimmel039c49a2016-01-27 15:20:18 +01003563 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3564}
3565
3566static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003567mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3568 u16 fid)
3569{
3570 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3571 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3572
3573 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3574 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3575 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3576
Ido Schimmel22305372016-06-20 23:04:21 +02003577 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3578 mlxsw_sp_port->lag_id, fid);
3579
Ido Schimmel039c49a2016-01-27 15:20:18 +01003580 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3581}
3582
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003583int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003584{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003585 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3586 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003587
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003588 if (mlxsw_sp_port->lagged)
3589 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003590 fid);
3591 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003592 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003593}
3594
Ido Schimmel701b1862016-07-04 08:23:16 +02003595static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3596{
3597 struct mlxsw_sp_fid *f, *tmp;
3598
3599 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3600 if (--f->ref_count == 0)
3601 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3602 else
3603 WARN_ON_ONCE(1);
3604}
3605
Ido Schimmel7117a572016-06-20 23:04:06 +02003606static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3607 struct net_device *br_dev)
3608{
3609 return !mlxsw_sp->master_bridge.dev ||
3610 mlxsw_sp->master_bridge.dev == br_dev;
3611}
3612
3613static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3614 struct net_device *br_dev)
3615{
3616 mlxsw_sp->master_bridge.dev = br_dev;
3617 mlxsw_sp->master_bridge.ref_count++;
3618}
3619
3620static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3621{
Ido Schimmel701b1862016-07-04 08:23:16 +02003622 if (--mlxsw_sp->master_bridge.ref_count == 0) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003623 mlxsw_sp->master_bridge.dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02003624 /* It's possible upper VLAN devices are still holding
3625 * references to underlying FIDs. Drop the reference
3626 * and release the resources if it was the last one.
3627 * If it wasn't, then something bad happened.
3628 */
3629 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3630 }
Ido Schimmel7117a572016-06-20 23:04:06 +02003631}
3632
3633static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3634 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003635{
3636 struct net_device *dev = mlxsw_sp_port->dev;
3637 int err;
3638
3639 /* When port is not bridged untagged packets are tagged with
3640 * PVID=VID=1, thereby creating an implicit VLAN interface in
3641 * the device. Remove it and let bridge code take care of its
3642 * own VLANs.
3643 */
3644 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003645 if (err)
3646 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003647
Ido Schimmel7117a572016-06-20 23:04:06 +02003648 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3649
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003650 mlxsw_sp_port->learning = 1;
3651 mlxsw_sp_port->learning_sync = 1;
3652 mlxsw_sp_port->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003653 mlxsw_sp_port->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003654 mlxsw_sp_port->mc_router = 0;
3655 mlxsw_sp_port->mc_disabled = 1;
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003656 mlxsw_sp_port->bridged = 1;
3657
3658 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003659}
3660
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003661static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003662{
3663 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003664
Ido Schimmel28a01d22016-02-18 11:30:02 +01003665 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3666
Ido Schimmel7117a572016-06-20 23:04:06 +02003667 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3668
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003669 mlxsw_sp_port->learning = 0;
3670 mlxsw_sp_port->learning_sync = 0;
3671 mlxsw_sp_port->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003672 mlxsw_sp_port->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003673 mlxsw_sp_port->mc_router = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003674 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003675
3676 /* Add implicit VLAN interface in the device, so that untagged
3677 * packets will be classified to the default vFID.
3678 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02003679 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003680}
3681
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003682static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003683{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003684 char sldr_pl[MLXSW_REG_SLDR_LEN];
3685
3686 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3687 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3688}
3689
3690static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3691{
3692 char sldr_pl[MLXSW_REG_SLDR_LEN];
3693
3694 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3695 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3696}
3697
3698static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3699 u16 lag_id, u8 port_index)
3700{
3701 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3702 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3703
3704 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3705 lag_id, port_index);
3706 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3707}
3708
3709static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3710 u16 lag_id)
3711{
3712 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3713 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3714
3715 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3716 lag_id);
3717 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3718}
3719
3720static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3721 u16 lag_id)
3722{
3723 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3724 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3725
3726 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3727 lag_id);
3728 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3729}
3730
3731static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3732 u16 lag_id)
3733{
3734 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3735 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3736
3737 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3738 lag_id);
3739 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3740}
3741
3742static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3743 struct net_device *lag_dev,
3744 u16 *p_lag_id)
3745{
3746 struct mlxsw_sp_upper *lag;
3747 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003748 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003749 int i;
3750
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003751 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3752 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003753 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3754 if (lag->ref_count) {
3755 if (lag->dev == lag_dev) {
3756 *p_lag_id = i;
3757 return 0;
3758 }
3759 } else if (free_lag_id < 0) {
3760 free_lag_id = i;
3761 }
3762 }
3763 if (free_lag_id < 0)
3764 return -EBUSY;
3765 *p_lag_id = free_lag_id;
3766 return 0;
3767}
3768
3769static bool
3770mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3771 struct net_device *lag_dev,
3772 struct netdev_lag_upper_info *lag_upper_info)
3773{
3774 u16 lag_id;
3775
3776 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3777 return false;
3778 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3779 return false;
3780 return true;
3781}
3782
3783static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3784 u16 lag_id, u8 *p_port_index)
3785{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003786 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003787 int i;
3788
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003789 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3790 MAX_LAG_MEMBERS);
3791 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003792 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3793 *p_port_index = i;
3794 return 0;
3795 }
3796 }
3797 return -EBUSY;
3798}
3799
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003800static void
3801mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel186962e2017-03-10 08:53:36 +01003802 struct net_device *lag_dev, u16 lag_id)
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003803{
3804 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003805 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003806
3807 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3808 if (WARN_ON(!mlxsw_sp_vport))
3809 return;
3810
Ido Schimmel11943ff2016-07-02 11:00:12 +02003811 /* If vPort is assigned a RIF, then leave it since it's no
3812 * longer valid.
3813 */
3814 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3815 if (f)
3816 f->leave(mlxsw_sp_vport);
3817
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003818 mlxsw_sp_vport->lag_id = lag_id;
3819 mlxsw_sp_vport->lagged = 1;
Ido Schimmel186962e2017-03-10 08:53:36 +01003820 mlxsw_sp_vport->dev = lag_dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003821}
3822
3823static void
3824mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3825{
3826 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003827 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003828
3829 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3830 if (WARN_ON(!mlxsw_sp_vport))
3831 return;
3832
Ido Schimmel11943ff2016-07-02 11:00:12 +02003833 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3834 if (f)
3835 f->leave(mlxsw_sp_vport);
3836
Ido Schimmel186962e2017-03-10 08:53:36 +01003837 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003838 mlxsw_sp_vport->lagged = 0;
3839}
3840
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003841static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3842 struct net_device *lag_dev)
3843{
3844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3845 struct mlxsw_sp_upper *lag;
3846 u16 lag_id;
3847 u8 port_index;
3848 int err;
3849
3850 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3851 if (err)
3852 return err;
3853 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3854 if (!lag->ref_count) {
3855 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3856 if (err)
3857 return err;
3858 lag->dev = lag_dev;
3859 }
3860
3861 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3862 if (err)
3863 return err;
3864 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3865 if (err)
3866 goto err_col_port_add;
3867 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3868 if (err)
3869 goto err_col_port_enable;
3870
3871 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3872 mlxsw_sp_port->local_port);
3873 mlxsw_sp_port->lag_id = lag_id;
3874 mlxsw_sp_port->lagged = 1;
3875 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003876
Ido Schimmel186962e2017-03-10 08:53:36 +01003877 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003878
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003879 return 0;
3880
Ido Schimmel51554db2016-05-06 22:18:39 +02003881err_col_port_enable:
3882 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003883err_col_port_add:
3884 if (!lag->ref_count)
3885 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003886 return err;
3887}
3888
Ido Schimmel82e6db02016-06-20 23:04:04 +02003889static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3890 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003891{
3892 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003893 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02003894 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003895
3896 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003897 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003898 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3899 WARN_ON(lag->ref_count == 0);
3900
Ido Schimmel82e6db02016-06-20 23:04:04 +02003901 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3902 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003903
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003904 if (mlxsw_sp_port->bridged) {
3905 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003906 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003907 }
3908
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003909 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003910 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003911
3912 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3913 mlxsw_sp_port->local_port);
3914 mlxsw_sp_port->lagged = 0;
3915 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003916
3917 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003918}
3919
Jiri Pirko74581202015-12-03 12:12:30 +01003920static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3921 u16 lag_id)
3922{
3923 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3924 char sldr_pl[MLXSW_REG_SLDR_LEN];
3925
3926 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3927 mlxsw_sp_port->local_port);
3928 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3929}
3930
3931static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3932 u16 lag_id)
3933{
3934 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3935 char sldr_pl[MLXSW_REG_SLDR_LEN];
3936
3937 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3938 mlxsw_sp_port->local_port);
3939 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3940}
3941
3942static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
3943 bool lag_tx_enabled)
3944{
3945 if (lag_tx_enabled)
3946 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
3947 mlxsw_sp_port->lag_id);
3948 else
3949 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3950 mlxsw_sp_port->lag_id);
3951}
3952
3953static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3954 struct netdev_lag_lower_state_info *info)
3955{
3956 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
3957}
3958
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003959static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
3960 struct net_device *vlan_dev)
3961{
3962 struct mlxsw_sp_port *mlxsw_sp_vport;
3963 u16 vid = vlan_dev_vlan_id(vlan_dev);
3964
3965 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003966 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003967 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003968
3969 mlxsw_sp_vport->dev = vlan_dev;
3970
3971 return 0;
3972}
3973
Ido Schimmel82e6db02016-06-20 23:04:04 +02003974static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
3975 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003976{
3977 struct mlxsw_sp_port *mlxsw_sp_vport;
3978 u16 vid = vlan_dev_vlan_id(vlan_dev);
3979
3980 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003981 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02003982 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003983
3984 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003985}
3986
Jiri Pirko74581202015-12-03 12:12:30 +01003987static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3988 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003989{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003990 struct netdev_notifier_changeupper_info *info;
3991 struct mlxsw_sp_port *mlxsw_sp_port;
3992 struct net_device *upper_dev;
3993 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003994 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003995
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003996 mlxsw_sp_port = netdev_priv(dev);
3997 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3998 info = ptr;
3999
4000 switch (event) {
4001 case NETDEV_PRECHANGEUPPER:
4002 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004003 if (!is_vlan_dev(upper_dev) &&
4004 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004005 !netif_is_bridge_master(upper_dev) &&
4006 !netif_is_l3_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004007 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004008 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004009 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004010 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004011 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004012 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004013 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004014 if (netif_is_lag_master(upper_dev) &&
4015 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4016 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004017 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004018 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4019 return -EINVAL;
4020 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4021 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4022 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004023 break;
4024 case NETDEV_CHANGEUPPER:
4025 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004026 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004027 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004028 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4029 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004030 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004031 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4032 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004033 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004034 if (info->linking)
4035 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4036 upper_dev);
4037 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004038 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004039 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004040 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004041 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4042 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004043 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004044 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4045 upper_dev);
Ido Schimmel7179eb52017-03-16 09:08:18 +01004046 } else if (netif_is_l3_master(upper_dev)) {
4047 if (info->linking)
4048 err = mlxsw_sp_port_vrf_join(mlxsw_sp_port);
4049 else
4050 mlxsw_sp_port_vrf_leave(mlxsw_sp_port);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004051 } else {
4052 err = -EINVAL;
4053 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004054 }
4055 break;
4056 }
4057
Ido Schimmel80bedf12016-06-20 23:03:59 +02004058 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004059}
4060
Jiri Pirko74581202015-12-03 12:12:30 +01004061static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4062 unsigned long event, void *ptr)
4063{
4064 struct netdev_notifier_changelowerstate_info *info;
4065 struct mlxsw_sp_port *mlxsw_sp_port;
4066 int err;
4067
4068 mlxsw_sp_port = netdev_priv(dev);
4069 info = ptr;
4070
4071 switch (event) {
4072 case NETDEV_CHANGELOWERSTATE:
4073 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4074 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4075 info->lower_state_info);
4076 if (err)
4077 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4078 }
4079 break;
4080 }
4081
Ido Schimmel80bedf12016-06-20 23:03:59 +02004082 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004083}
4084
4085static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4086 unsigned long event, void *ptr)
4087{
4088 switch (event) {
4089 case NETDEV_PRECHANGEUPPER:
4090 case NETDEV_CHANGEUPPER:
4091 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4092 case NETDEV_CHANGELOWERSTATE:
4093 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4094 }
4095
Ido Schimmel80bedf12016-06-20 23:03:59 +02004096 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004097}
4098
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004099static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4100 unsigned long event, void *ptr)
4101{
4102 struct net_device *dev;
4103 struct list_head *iter;
4104 int ret;
4105
4106 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4107 if (mlxsw_sp_port_dev_check(dev)) {
4108 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004109 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004110 return ret;
4111 }
4112 }
4113
Ido Schimmel80bedf12016-06-20 23:03:59 +02004114 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004115}
4116
Ido Schimmel701b1862016-07-04 08:23:16 +02004117static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4118 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004119{
Ido Schimmel701b1862016-07-04 08:23:16 +02004120 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004121 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004122
Ido Schimmel701b1862016-07-04 08:23:16 +02004123 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4124 if (!f) {
4125 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4126 if (IS_ERR(f))
4127 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004128 }
4129
Ido Schimmel701b1862016-07-04 08:23:16 +02004130 f->ref_count++;
4131
4132 return 0;
4133}
4134
4135static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4136 struct net_device *vlan_dev)
4137{
4138 u16 fid = vlan_dev_vlan_id(vlan_dev);
4139 struct mlxsw_sp_fid *f;
4140
4141 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004142 if (f && f->rif)
4143 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel701b1862016-07-04 08:23:16 +02004144 if (f && --f->ref_count == 0)
4145 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4146}
4147
4148static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4149 unsigned long event, void *ptr)
4150{
4151 struct netdev_notifier_changeupper_info *info;
4152 struct net_device *upper_dev;
4153 struct mlxsw_sp *mlxsw_sp;
Ido Schimmelb4149702017-03-10 08:53:34 +01004154 int err = 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004155
4156 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4157 if (!mlxsw_sp)
4158 return 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004159
4160 info = ptr;
4161
4162 switch (event) {
Ido Schimmelb4149702017-03-10 08:53:34 +01004163 case NETDEV_PRECHANGEUPPER:
Ido Schimmel701b1862016-07-04 08:23:16 +02004164 upper_dev = info->upper_dev;
Ido Schimmel3d70e4582017-03-16 09:08:19 +01004165 if (!is_vlan_dev(upper_dev) && !netif_is_l3_master(upper_dev))
Ido Schimmelb4149702017-03-10 08:53:34 +01004166 return -EINVAL;
4167 if (is_vlan_dev(upper_dev) &&
4168 br_dev != mlxsw_sp->master_bridge.dev)
4169 return -EINVAL;
4170 break;
4171 case NETDEV_CHANGEUPPER:
4172 upper_dev = info->upper_dev;
4173 if (is_vlan_dev(upper_dev)) {
4174 if (info->linking)
4175 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4176 upper_dev);
4177 else
4178 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4179 upper_dev);
Ido Schimmel3d70e4582017-03-16 09:08:19 +01004180 } else if (netif_is_l3_master(upper_dev)) {
4181 if (info->linking)
4182 err = mlxsw_sp_bridge_vrf_join(mlxsw_sp,
4183 br_dev);
4184 else
4185 mlxsw_sp_bridge_vrf_leave(mlxsw_sp, br_dev);
Ido Schimmel701b1862016-07-04 08:23:16 +02004186 } else {
Ido Schimmelb4149702017-03-10 08:53:34 +01004187 err = -EINVAL;
4188 WARN_ON(1);
Ido Schimmel701b1862016-07-04 08:23:16 +02004189 }
4190 break;
4191 }
4192
Ido Schimmelb4149702017-03-10 08:53:34 +01004193 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004194}
4195
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004196static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004197{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004198 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02004199 MLXSW_SP_VFID_MAX);
4200}
4201
4202static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4203{
4204 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4205
4206 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4207 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004208}
4209
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004210static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel1c800752016-06-20 23:04:20 +02004211
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004212static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4213 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004214{
4215 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004216 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004217 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004218 int err;
4219
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004220 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004221 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004222 dev_err(dev, "No available vFIDs\n");
4223 return ERR_PTR(-ERANGE);
4224 }
4225
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004226 fid = mlxsw_sp_vfid_to_fid(vfid);
4227 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004228 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004229 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004230 return ERR_PTR(err);
4231 }
4232
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004233 f = kzalloc(sizeof(*f), GFP_KERNEL);
4234 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004235 goto err_allocate_vfid;
4236
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004237 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004238 f->fid = fid;
4239 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004240
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004241 list_add(&f->list, &mlxsw_sp->vfids.list);
4242 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004243
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004244 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004245
4246err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004247 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004248 return ERR_PTR(-ENOMEM);
4249}
4250
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004251static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4252 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004253{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004254 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004255 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004256
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004257 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004258 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004259
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004260 if (f->rif)
4261 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004262
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004263 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004264
4265 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004266}
4267
Ido Schimmel99724c12016-07-04 08:23:14 +02004268static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4269 bool valid)
4270{
4271 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4272 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4273
4274 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4275 vid);
4276}
4277
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004278static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4279 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004280{
Ido Schimmel0355b592016-06-20 23:04:13 +02004281 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004282 int err;
4283
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004284 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004285 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004286 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004287 if (IS_ERR(f))
4288 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004289 }
4290
Ido Schimmel0355b592016-06-20 23:04:13 +02004291 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4292 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004293 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004294
Ido Schimmel0355b592016-06-20 23:04:13 +02004295 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4296 if (err)
4297 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01004298
Ido Schimmel41b996c2016-06-20 23:04:17 +02004299 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004300 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01004301
Ido Schimmel22305372016-06-20 23:04:21 +02004302 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4303
Ido Schimmel0355b592016-06-20 23:04:13 +02004304 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004305
Ido Schimmel9c4d4422016-06-20 23:04:10 +02004306err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02004307 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4308err_vport_flood_set:
4309 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004310 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004311 return err;
4312}
4313
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004314static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004315{
Ido Schimmel41b996c2016-06-20 23:04:17 +02004316 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004317
Ido Schimmel22305372016-06-20 23:04:21 +02004318 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4319
Ido Schimmel0355b592016-06-20 23:04:13 +02004320 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4321
4322 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4323
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004324 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4325
Ido Schimmel41b996c2016-06-20 23:04:17 +02004326 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +02004327 if (--f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004328 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004329}
4330
4331static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4332 struct net_device *br_dev)
4333{
Ido Schimmel99724c12016-07-04 08:23:14 +02004334 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004335 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4336 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004337 int err;
4338
Ido Schimmel99724c12016-07-04 08:23:14 +02004339 if (f && !WARN_ON(!f->leave))
4340 f->leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004341
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004342 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004343 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02004344 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02004345 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004346 }
4347
4348 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4349 if (err) {
4350 netdev_err(dev, "Failed to enable learning\n");
4351 goto err_port_vid_learning_set;
4352 }
4353
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004354 mlxsw_sp_vport->learning = 1;
4355 mlxsw_sp_vport->learning_sync = 1;
4356 mlxsw_sp_vport->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004357 mlxsw_sp_vport->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004358 mlxsw_sp_vport->mc_router = 0;
4359 mlxsw_sp_vport->mc_disabled = 1;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004360 mlxsw_sp_vport->bridged = 1;
4361
4362 return 0;
4363
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004364err_port_vid_learning_set:
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004365 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004366 return err;
4367}
4368
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004369static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004370{
4371 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004372
4373 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4374
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004375 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004376
Ido Schimmel0355b592016-06-20 23:04:13 +02004377 mlxsw_sp_vport->learning = 0;
4378 mlxsw_sp_vport->learning_sync = 0;
4379 mlxsw_sp_vport->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004380 mlxsw_sp_vport->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004381 mlxsw_sp_vport->mc_router = 0;
Ido Schimmel0355b592016-06-20 23:04:13 +02004382 mlxsw_sp_vport->bridged = 0;
4383}
4384
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004385static bool
4386mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4387 const struct net_device *br_dev)
4388{
4389 struct mlxsw_sp_port *mlxsw_sp_vport;
4390
4391 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4392 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004393 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02004394
4395 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004396 return false;
4397 }
4398
4399 return true;
4400}
4401
4402static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4403 unsigned long event, void *ptr,
4404 u16 vid)
4405{
4406 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4407 struct netdev_notifier_changeupper_info *info = ptr;
4408 struct mlxsw_sp_port *mlxsw_sp_vport;
4409 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004410 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004411
4412 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel1f880612017-03-10 08:53:35 +01004413 if (!mlxsw_sp_vport)
4414 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004415
4416 switch (event) {
4417 case NETDEV_PRECHANGEUPPER:
4418 upper_dev = info->upper_dev;
Ido Schimmel7179eb52017-03-16 09:08:18 +01004419 if (!netif_is_bridge_master(upper_dev) &&
4420 !netif_is_l3_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004421 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02004422 if (!info->linking)
4423 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004424 /* We can't have multiple VLAN interfaces configured on
4425 * the same port and being members in the same bridge.
4426 */
Ido Schimmel7179eb52017-03-16 09:08:18 +01004427 if (netif_is_bridge_master(upper_dev) &&
4428 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004429 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004430 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004431 break;
4432 case NETDEV_CHANGEUPPER:
4433 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004434 if (netif_is_bridge_master(upper_dev)) {
4435 if (info->linking)
4436 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4437 upper_dev);
4438 else
4439 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel7179eb52017-03-16 09:08:18 +01004440 } else if (netif_is_l3_master(upper_dev)) {
4441 if (info->linking)
4442 err = mlxsw_sp_vport_vrf_join(mlxsw_sp_vport);
4443 else
4444 mlxsw_sp_vport_vrf_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004445 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004446 err = -EINVAL;
4447 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004448 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004449 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004450 }
4451
Ido Schimmel80bedf12016-06-20 23:03:59 +02004452 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004453}
4454
Ido Schimmel272c4472015-12-15 16:03:47 +01004455static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4456 unsigned long event, void *ptr,
4457 u16 vid)
4458{
4459 struct net_device *dev;
4460 struct list_head *iter;
4461 int ret;
4462
4463 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4464 if (mlxsw_sp_port_dev_check(dev)) {
4465 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4466 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004467 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004468 return ret;
4469 }
4470 }
4471
Ido Schimmel80bedf12016-06-20 23:03:59 +02004472 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004473}
4474
Ido Schimmel3d70e4582017-03-16 09:08:19 +01004475static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
4476 unsigned long event, void *ptr)
4477{
4478 struct netdev_notifier_changeupper_info *info;
4479 struct mlxsw_sp *mlxsw_sp;
4480 int err = 0;
4481
4482 mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
4483 if (!mlxsw_sp)
4484 return 0;
4485
4486 info = ptr;
4487
4488 switch (event) {
4489 case NETDEV_PRECHANGEUPPER:
4490 /* VLAN devices are only allowed on top of the
4491 * VLAN-aware bridge.
4492 */
4493 if (WARN_ON(vlan_dev_real_dev(vlan_dev) !=
4494 mlxsw_sp->master_bridge.dev))
4495 return -EINVAL;
4496 if (!netif_is_l3_master(info->upper_dev))
4497 return -EINVAL;
4498 break;
4499 case NETDEV_CHANGEUPPER:
4500 if (netif_is_l3_master(info->upper_dev)) {
4501 if (info->linking)
4502 err = mlxsw_sp_bridge_vrf_join(mlxsw_sp,
4503 vlan_dev);
4504 else
4505 mlxsw_sp_bridge_vrf_leave(mlxsw_sp, vlan_dev);
4506 } else {
4507 err = -EINVAL;
4508 WARN_ON(1);
4509 }
4510 break;
4511 }
4512
4513 return err;
4514}
4515
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004516static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4517 unsigned long event, void *ptr)
4518{
4519 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4520 u16 vid = vlan_dev_vlan_id(vlan_dev);
4521
Ido Schimmel272c4472015-12-15 16:03:47 +01004522 if (mlxsw_sp_port_dev_check(real_dev))
4523 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4524 vid);
4525 else if (netif_is_lag_master(real_dev))
4526 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4527 vid);
Ido Schimmel3d70e4582017-03-16 09:08:19 +01004528 else if (netif_is_bridge_master(real_dev))
4529 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, event,
4530 ptr);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004531
Ido Schimmel80bedf12016-06-20 23:03:59 +02004532 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004533}
4534
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004535static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4536 unsigned long event, void *ptr)
4537{
4538 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004539 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004540
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004541 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4542 err = mlxsw_sp_netdevice_router_port_event(dev);
4543 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004544 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4545 else if (netif_is_lag_master(dev))
4546 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004547 else if (netif_is_bridge_master(dev))
4548 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004549 else if (is_vlan_dev(dev))
4550 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004551
Ido Schimmel80bedf12016-06-20 23:03:59 +02004552 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004553}
4554
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004555static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4556 .notifier_call = mlxsw_sp_netdevice_event,
4557};
4558
Ido Schimmel99724c12016-07-04 08:23:14 +02004559static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4560 .notifier_call = mlxsw_sp_inetaddr_event,
4561 .priority = 10, /* Must be called before FIB notifier block */
4562};
4563
Jiri Pirkoe7322632016-09-01 10:37:43 +02004564static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4565 .notifier_call = mlxsw_sp_router_netevent_event,
4566};
4567
Jiri Pirko1d20d232016-10-27 15:12:59 +02004568static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4569 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4570 {0, },
4571};
4572
4573static struct pci_driver mlxsw_sp_pci_driver = {
4574 .name = mlxsw_sp_driver_name,
4575 .id_table = mlxsw_sp_pci_id_table,
4576};
4577
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004578static int __init mlxsw_sp_module_init(void)
4579{
4580 int err;
4581
4582 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004583 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004584 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4585
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004586 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4587 if (err)
4588 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004589
4590 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4591 if (err)
4592 goto err_pci_driver_register;
4593
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004594 return 0;
4595
Jiri Pirko1d20d232016-10-27 15:12:59 +02004596err_pci_driver_register:
4597 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004598err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004599 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004600 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004601 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4602 return err;
4603}
4604
4605static void __exit mlxsw_sp_module_exit(void)
4606{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004607 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004608 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004609 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004610 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004611 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4612}
4613
4614module_init(mlxsw_sp_module_init);
4615module_exit(mlxsw_sp_module_exit);
4616
4617MODULE_LICENSE("Dual BSD/GPL");
4618MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4619MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004620MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);