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gerrit-public.fairphone.software / platform / external / llvm / 6de3c6f1a926f49cca2fd207ab4eeb6c35e0e068 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 3b4e1c5aea77c127e875ffe54e12c73a2a2245e8 [file] [log] [blame]
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
13#include "ARMRegisterInfo.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]14#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]21#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]25#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]26#include "llvm/Support/raw_ostream.h"
27
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]28using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]29
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]32namespace {
33/// ARMDisassembler - ARM disassembler for all ARM platforms.
34class ARMDisassembler : public MCDisassembler {
35public:
36 /// Constructor - Initializes the disassembler.
37 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]40 }
41
42 ~ARMDisassembler() {
43 }
44
45 /// getInstruction - See MCDisassembler.
46 DecodeStatus getInstruction(MCInst &instr,
47 uint64_t &size,
48 const MemoryObject &region,
49 uint64_t address,
50 raw_ostream &vStream) const;
51
52 /// getEDInfo - See MCDisassembler.
53 EDInstInfo *getEDInfo() const;
54private:
55};
56
57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
58class ThumbDisassembler : public MCDisassembler {
59public:
60 /// Constructor - Initializes the disassembler.
61 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]62 ThumbDisassembler(const MCSubtargetInfo &STI) :
63 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]64 }
65
66 ~ThumbDisassembler() {
67 }
68
69 /// getInstruction - See MCDisassembler.
70 DecodeStatus getInstruction(MCInst &instr,
71 uint64_t &size,
72 const MemoryObject &region,
73 uint64_t address,
74 raw_ostream &vStream) const;
75
76 /// getEDInfo - See MCDisassembler.
77 EDInstInfo *getEDInfo() const;
78private:
79 mutable std::vector<unsigned> ITBlock;
80 void AddThumbPredicate(MCInst&) const;
81 void UpdateThumbVFPPredicate(MCInst&) const;
82};
83}
84
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]85static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]86 switch (In) {
87 case MCDisassembler::Success:
88 // Out stays the same.
89 return true;
90 case MCDisassembler::SoftFail:
91 Out = In;
92 return true;
93 case MCDisassembler::Fail:
94 Out = In;
95 return false;
96 }
97 return false;
98}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]99
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]100// Forward declare these because the autogenerated code will reference them.
101// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]102static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]103 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]104static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]105 unsigned RegNo, uint64_t Address,
106 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]107static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]108 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]109static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]110 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]120 unsigned RegNo,
121 uint64_t Address,
122 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]124 uint64_t Address, const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]125
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]126static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]128static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]130static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]131 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]132static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]133 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]134static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]135 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]137 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]138
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]141static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]142 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]144 unsigned Insn,
145 uint64_t Address,
146 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]147static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]148 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]149static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]150 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]151static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]153static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]154 uint64_t Address, const void *Decoder);
155
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 unsigned Insn,
158 uint64_t Adddress,
159 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]162static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]163 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]164static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]166static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]168static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]170static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]172static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]174static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]175 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]176static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]177 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]178static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]180static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]182static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]183 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]184static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]185 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]186static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]188static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]190static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]192static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]194static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]196static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]198static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]199 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]200static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]201 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]202static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]203 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]204static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]205 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]206static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]207 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]208static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]209 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]210static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]211 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]212static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]213 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]214static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]215 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]216static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]217 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]218static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]219 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]220static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]222static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]224static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]226static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]228static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]230static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]232static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]234static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]236static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]237 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]238static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]240static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]242static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]244static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]245 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]246
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]249static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]250 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]251static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]252 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]255static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]256 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]257static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]258 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]259static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]260 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]261static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]277static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]287static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]293static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]294 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]295
296#include "ARMGenDisassemblerTables.inc"
297#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]298#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]299
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]300static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
301 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]302}
303
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]304static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
305 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]306}
307
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]308EDInstInfo *ARMDisassembler::getEDInfo() const {
309 return instInfoARM;
310}
311
312EDInstInfo *ThumbDisassembler::getEDInfo() const {
313 return instInfoARM;
314}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]315
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]316DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]317 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]318 uint64_t Address,
319 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]320 uint8_t bytes[4];
321
322 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]323 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
324 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]325 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]326 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327
328 // Encoded as a small-endian 32-bit word in the stream.
329 uint32_t insn = (bytes[3] << 24) |
330 (bytes[2] << 16) |
331 (bytes[1] << 8) |
332 (bytes[0] << 0);
333
334 // Calling the auto-generated decoder function.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]335 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]336 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]338 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 }
340
341 // Instructions that are shared between ARM and Thumb modes.
342 // FIXME: This shouldn't really exist. It's an artifact of the
343 // fact that we fail to encode a few instructions properly for Thumb.
344 MI.clear();
345 result = decodeCommonInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]346 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]348 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 }
350
351 // VFP and NEON instructions, similarly, are shared between ARM
352 // and Thumb modes.
353 MI.clear();
354 result = decodeVFPInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]355 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]356 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]357 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]358 }
359
360 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]361 result = decodeNEONDataInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]362 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]363 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]364 // Add a fake predicate operand, because we share these instruction
365 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]366 if (!DecodePredicateOperand(MI, 0xE, Address, this))
367 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]368 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]369 }
370
371 MI.clear();
372 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]373 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]374 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]375 // Add a fake predicate operand, because we share these instruction
376 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]377 if (!DecodePredicateOperand(MI, 0xE, Address, this))
378 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]379 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]380 }
381
382 MI.clear();
383 result = decodeNEONDupInstruction32(MI, insn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]384 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]385 Size = 4;
386 // Add a fake predicate operand, because we share these instruction
387 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]388 if (!DecodePredicateOperand(MI, 0xE, Address, this))
389 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]390 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]391 }
392
393 MI.clear();
394
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]395 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]396 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]397}
398
399namespace llvm {
400extern MCInstrDesc ARMInsts[];
401}
402
403// Thumb1 instructions don't have explicit S bits. Rather, they
404// implicitly set CPSR. Since it's not represented in the encoding, the
405// auto-generated decoder won't inject the CPSR operand. We need to fix
406// that as a post-pass.
407static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
408 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]409 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]410 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]411 for (unsigned i = 0; i < NumOps; ++i, ++I) {
412 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]413 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]414 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
416 return;
417 }
418 }
419
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]420 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]421}
422
423// Most Thumb instructions don't have explicit predicates in the
424// encoding, but rather get their predicates from IT context. We need
425// to fix up the predicate operands using this context information as a
426// post-pass.
427void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
428 // A few instructions actually have predicates encoded in them. Don't
429 // try to overwrite it if we're seeing one of those.
430 switch (MI.getOpcode()) {
431 case ARM::tBcc:
432 case ARM::t2Bcc:
433 return;
434 default:
435 break;
436 }
437
438 // If we're in an IT block, base the predicate on that. Otherwise,
439 // assume a predicate of AL.
440 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]441 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]442 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]443 if (CC == 0xF)
444 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]445 ITBlock.pop_back();
446 } else
447 CC = ARMCC::AL;
448
449 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]450 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]451 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]452 for (unsigned i = 0; i < NumOps; ++i, ++I) {
453 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]454 if (OpInfo[i].isPredicate()) {
455 I = MI.insert(I, MCOperand::CreateImm(CC));
456 ++I;
457 if (CC == ARMCC::AL)
458 MI.insert(I, MCOperand::CreateReg(0));
459 else
460 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
461 return;
462 }
463 }
464
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]465 I = MI.insert(I, MCOperand::CreateImm(CC));
466 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]467 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]468 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]469 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]470 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]471}
472
473// Thumb VFP instructions are a special case. Because we share their
474// encodings between ARM and Thumb modes, and they are predicable in ARM
475// mode, the auto-generated decoder will give them an (incorrect)
476// predicate operand. We need to rewrite these operands based on the IT
477// context as a post-pass.
478void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
479 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]480 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]481 CC = ITBlock.back();
482 ITBlock.pop_back();
483 } else
484 CC = ARMCC::AL;
485
486 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
487 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]488 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
489 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]490 if (OpInfo[i].isPredicate() ) {
491 I->setImm(CC);
492 ++I;
493 if (CC == ARMCC::AL)
494 I->setReg(0);
495 else
496 I->setReg(ARM::CPSR);
497 return;
498 }
499 }
500}
501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]502DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]503 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]504 uint64_t Address,
505 raw_ostream &os) const {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]506 uint8_t bytes[4];
507
508 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]509 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
510 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]511 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]512 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]513
514 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]515 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]516 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]517 Size = 2;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]518 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]519 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]520 }
521
522 MI.clear();
523 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
524 if (result) {
525 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]526 bool InITBlock = !ITBlock.empty();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]527 AddThumbPredicate(MI);
528 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]529 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]530 }
531
532 MI.clear();
533 result = decodeThumb2Instruction16(MI, insn16, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]534 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]535 Size = 2;
536 AddThumbPredicate(MI);
537
538 // If we find an IT instruction, we need to parse its condition
539 // code and mask operands so that we can apply them correctly
540 // to the subsequent instructions.
541 if (MI.getOpcode() == ARM::t2IT) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]542 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]543 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]544 unsigned Mask = MI.getOperand(1).getImm();
545 unsigned CondBit0 = Mask >> 4 & 1;
546 unsigned NumTZ = CountTrailingZeros_32(Mask);
547 assert(NumTZ <= 3 && "Invalid IT mask!");
548 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
549 bool T = ((Mask >> Pos) & 1) == CondBit0;
550 if (T)
551 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]552 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]553 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]554 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]555
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]556 ITBlock.push_back(firstcond);
557 }
558
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]559 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]560 }
561
562 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]563 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
564 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]565 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]566 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]567
568 uint32_t insn32 = (bytes[3] << 8) |
569 (bytes[2] << 0) |
570 (bytes[1] << 24) |
571 (bytes[0] << 16);
572 MI.clear();
573 result = decodeThumbInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]574 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]575 Size = 4;
576 bool InITBlock = ITBlock.size();
577 AddThumbPredicate(MI);
578 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]579 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]580 }
581
582 MI.clear();
583 result = decodeThumb2Instruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]584 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]585 Size = 4;
586 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]587 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]588 }
589
590 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]591 result = decodeCommonInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]592 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]593 Size = 4;
594 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]595 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]596 }
597
598 MI.clear();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]599 result = decodeVFPInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]600 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]601 Size = 4;
602 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]603 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]604 }
605
606 MI.clear();
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]607 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]608 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]609 Size = 4;
610 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]611 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]612 }
613
614 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
615 MI.clear();
616 uint32_t NEONLdStInsn = insn32;
617 NEONLdStInsn &= 0xF0FFFFFF;
618 NEONLdStInsn |= 0x04000000;
619 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]620 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]621 Size = 4;
622 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]623 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]624 }
625 }
626
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]627 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]628 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]629 uint32_t NEONDataInsn = insn32;
630 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
631 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
632 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
633 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]634 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]635 Size = 4;
636 AddThumbPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]637 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]638 }
639 }
640
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]641 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]642 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]643}
644
645
646extern "C" void LLVMInitializeARMDisassembler() {
647 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
648 createARMDisassembler);
649 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
650 createThumbDisassembler);
651}
652
653static const unsigned GPRDecoderTable[] = {
654 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
655 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
656 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
657 ARM::R12, ARM::SP, ARM::LR, ARM::PC
658};
659
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]660static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]661 uint64_t Address, const void *Decoder) {
662 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]663 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]664
665 unsigned Register = GPRDecoderTable[RegNo];
666 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]667 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]668}
669
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]670static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]671DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
672 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]673 if (RegNo == 15) return MCDisassembler::Fail;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]674 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
675}
676
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]677static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]678 uint64_t Address, const void *Decoder) {
679 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]680 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]681 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
682}
683
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]684static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]685 uint64_t Address, const void *Decoder) {
686 unsigned Register = 0;
687 switch (RegNo) {
688 case 0:
689 Register = ARM::R0;
690 break;
691 case 1:
692 Register = ARM::R1;
693 break;
694 case 2:
695 Register = ARM::R2;
696 break;
697 case 3:
698 Register = ARM::R3;
699 break;
700 case 9:
701 Register = ARM::R9;
702 break;
703 case 12:
704 Register = ARM::R12;
705 break;
706 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]707 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 }
709
710 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]711 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]712}
713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]714static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]715 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]716 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]717 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
718}
719
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]720static const unsigned SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]721 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
722 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
723 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
724 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
725 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
726 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
727 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
728 ARM::S28, ARM::S29, ARM::S30, ARM::S31
729};
730
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]731static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732 uint64_t Address, const void *Decoder) {
733 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]734 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735
736 unsigned Register = SPRDecoderTable[RegNo];
737 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]738 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]739}
740
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]741static const unsigned DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]742 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
743 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
744 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
745 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
746 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
747 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
748 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
749 ARM::D28, ARM::D29, ARM::D30, ARM::D31
750};
751
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]752static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]753 uint64_t Address, const void *Decoder) {
754 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]755 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]756
757 unsigned Register = DPRDecoderTable[RegNo];
758 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]759 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]760}
761
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]762static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763 uint64_t Address, const void *Decoder) {
764 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]765 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]766 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
767}
768
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]769static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]770DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
771 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]772 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]773 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]774 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
775}
776
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]777static const unsigned QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]778 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
779 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
780 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
781 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
782};
783
784
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]785static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]786 uint64_t Address, const void *Decoder) {
787 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]788 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]789 RegNo >>= 1;
790
791 unsigned Register = QPRDecoderTable[RegNo];
792 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]793 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]794}
795
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]796static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]797 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]798 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]799 // AL predicate is not allowed on Thumb1 branches.
800 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]801 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 Inst.addOperand(MCOperand::CreateImm(Val));
803 if (Val == ARMCC::AL) {
804 Inst.addOperand(MCOperand::CreateReg(0));
805 } else
806 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]807 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]808}
809
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]810static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]811 uint64_t Address, const void *Decoder) {
812 if (Val)
813 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
814 else
815 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]816 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]817}
818
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]819static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]820 uint64_t Address, const void *Decoder) {
821 uint32_t imm = Val & 0xFF;
822 uint32_t rot = (Val & 0xF00) >> 7;
823 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
824 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]825 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]826}
827
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]828static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]829 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]830 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]831
832 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
833 unsigned type = fieldFromInstruction32(Val, 5, 2);
834 unsigned imm = fieldFromInstruction32(Val, 7, 5);
835
836 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
838 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]839
840 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
841 switch (type) {
842 case 0:
843 Shift = ARM_AM::lsl;
844 break;
845 case 1:
846 Shift = ARM_AM::lsr;
847 break;
848 case 2:
849 Shift = ARM_AM::asr;
850 break;
851 case 3:
852 Shift = ARM_AM::ror;
853 break;
854 }
855
856 if (Shift == ARM_AM::ror && imm == 0)
857 Shift = ARM_AM::rrx;
858
859 unsigned Op = Shift | (imm << 3);
860 Inst.addOperand(MCOperand::CreateImm(Op));
861
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]862 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]863}
864
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]865static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]866 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]867 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]868
869 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
870 unsigned type = fieldFromInstruction32(Val, 5, 2);
871 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
872
873 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]874 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
875 return MCDisassembler::Fail;
876 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
877 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]878
879 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
880 switch (type) {
881 case 0:
882 Shift = ARM_AM::lsl;
883 break;
884 case 1:
885 Shift = ARM_AM::lsr;
886 break;
887 case 2:
888 Shift = ARM_AM::asr;
889 break;
890 case 3:
891 Shift = ARM_AM::ror;
892 break;
893 }
894
895 Inst.addOperand(MCOperand::CreateImm(Shift));
896
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]897 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]898}
899
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]900static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]902 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]903
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]904 // Empty register lists are not allowed.
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]905 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]906 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]907 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]908 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
909 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]910 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]911 }
912
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]913 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]914}
915
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]916static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]917 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]918 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]919
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]920 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
921 unsigned regs = Val & 0xFF;
922
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]923 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
924 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]925 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]926 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
927 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]928 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]930 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]931}
932
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]933static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]934 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]935 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]936
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]937 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
938 unsigned regs = (Val & 0xFF) / 2;
939
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]940 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
941 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]942 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]943 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
944 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]945 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]946
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]947 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]948}
949
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]950static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]951 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]952 // This operand encodes a mask of contiguous zeros between a specified MSB
953 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
954 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]955 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]956 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]957 unsigned msb = fieldFromInstruction32(Val, 5, 5);
958 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
959 uint32_t msb_mask = (1 << (msb+1)) - 1;
960 uint32_t lsb_mask = (1 << lsb) - 1;
961 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]962 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963}
964
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]965static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]966 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]967 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]968
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]969 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
970 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
971 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
972 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
973 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
974 unsigned U = fieldFromInstruction32(Insn, 23, 1);
975
976 switch (Inst.getOpcode()) {
977 case ARM::LDC_OFFSET:
978 case ARM::LDC_PRE:
979 case ARM::LDC_POST:
980 case ARM::LDC_OPTION:
981 case ARM::LDCL_OFFSET:
982 case ARM::LDCL_PRE:
983 case ARM::LDCL_POST:
984 case ARM::LDCL_OPTION:
985 case ARM::STC_OFFSET:
986 case ARM::STC_PRE:
987 case ARM::STC_POST:
988 case ARM::STC_OPTION:
989 case ARM::STCL_OFFSET:
990 case ARM::STCL_PRE:
991 case ARM::STCL_POST:
992 case ARM::STCL_OPTION:
993 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]994 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]995 break;
996 default:
997 break;
998 }
999
1000 Inst.addOperand(MCOperand::CreateImm(coproc));
1001 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1003 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1004 switch (Inst.getOpcode()) {
1005 case ARM::LDC_OPTION:
1006 case ARM::LDCL_OPTION:
1007 case ARM::LDC2_OPTION:
1008 case ARM::LDC2L_OPTION:
1009 case ARM::STC_OPTION:
1010 case ARM::STCL_OPTION:
1011 case ARM::STC2_OPTION:
1012 case ARM::STC2L_OPTION:
1013 case ARM::LDCL_POST:
1014 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1015 case ARM::LDC2L_POST:
1016 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1017 break;
1018 default:
1019 Inst.addOperand(MCOperand::CreateReg(0));
1020 break;
1021 }
1022
1023 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1024 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1025
1026 bool writeback = (P == 0) || (W == 1);
1027 unsigned idx_mode = 0;
1028 if (P && writeback)
1029 idx_mode = ARMII::IndexModePre;
1030 else if (!P && writeback)
1031 idx_mode = ARMII::IndexModePost;
1032
1033 switch (Inst.getOpcode()) {
1034 case ARM::LDCL_POST:
1035 case ARM::STCL_POST:
Owen Anderson78affc92011-08-18 22:47:44 +0000[diff] [blame]1036 case ARM::LDC2L_POST:
1037 case ARM::STC2L_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1038 imm |= U << 8;
1039 case ARM::LDC_OPTION:
1040 case ARM::LDCL_OPTION:
1041 case ARM::LDC2_OPTION:
1042 case ARM::LDC2L_OPTION:
1043 case ARM::STC_OPTION:
1044 case ARM::STCL_OPTION:
1045 case ARM::STC2_OPTION:
1046 case ARM::STC2L_OPTION:
1047 Inst.addOperand(MCOperand::CreateImm(imm));
1048 break;
1049 default:
1050 if (U)
1051 Inst.addOperand(MCOperand::CreateImm(
1052 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
1053 else
1054 Inst.addOperand(MCOperand::CreateImm(
1055 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
1056 break;
1057 }
1058
1059 switch (Inst.getOpcode()) {
1060 case ARM::LDC_OFFSET:
1061 case ARM::LDC_PRE:
1062 case ARM::LDC_POST:
1063 case ARM::LDC_OPTION:
1064 case ARM::LDCL_OFFSET:
1065 case ARM::LDCL_PRE:
1066 case ARM::LDCL_POST:
1067 case ARM::LDCL_OPTION:
1068 case ARM::STC_OFFSET:
1069 case ARM::STC_PRE:
1070 case ARM::STC_POST:
1071 case ARM::STC_OPTION:
1072 case ARM::STCL_OFFSET:
1073 case ARM::STCL_PRE:
1074 case ARM::STCL_POST:
1075 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1076 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1077 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1078 break;
1079 default:
1080 break;
1081 }
1082
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1083 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1084}
1085
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1086static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1087DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1088 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1089 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1090
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1091 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1092 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1093 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1094 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1095 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1096 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1097 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1098 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1099
1100 // On stores, the writeback operand precedes Rt.
1101 switch (Inst.getOpcode()) {
1102 case ARM::STR_POST_IMM:
1103 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1104 case ARM::STRB_POST_IMM:
1105 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1106 case ARM::STRT_POST_REG:
1107 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1108 case ARM::STRBT_POST_REG:
1109 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1111 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 break;
1113 default:
1114 break;
1115 }
1116
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1118 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1119
1120 // On loads, the writeback operand comes after Rt.
1121 switch (Inst.getOpcode()) {
1122 case ARM::LDR_POST_IMM:
1123 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1124 case ARM::LDRB_POST_IMM:
1125 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1126 case ARM::LDRBT_POST_REG:
1127 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1128 case ARM::LDRT_POST_REG:
1129 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1131 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1132 break;
1133 default:
1134 break;
1135 }
1136
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1138 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1139
1140 ARM_AM::AddrOpc Op = ARM_AM::add;
1141 if (!fieldFromInstruction32(Insn, 23, 1))
1142 Op = ARM_AM::sub;
1143
1144 bool writeback = (P == 0) || (W == 1);
1145 unsigned idx_mode = 0;
1146 if (P && writeback)
1147 idx_mode = ARMII::IndexModePre;
1148 else if (!P && writeback)
1149 idx_mode = ARMII::IndexModePost;
1150
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1151 if (writeback && (Rn == 15 || Rn == Rt))
1152 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1153
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1154 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1155 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1156 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1157 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1158 switch( fieldFromInstruction32(Insn, 5, 2)) {
1159 case 0:
1160 Opc = ARM_AM::lsl;
1161 break;
1162 case 1:
1163 Opc = ARM_AM::lsr;
1164 break;
1165 case 2:
1166 Opc = ARM_AM::asr;
1167 break;
1168 case 3:
1169 Opc = ARM_AM::ror;
1170 break;
1171 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1172 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1173 }
1174 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1175 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1176
1177 Inst.addOperand(MCOperand::CreateImm(imm));
1178 } else {
1179 Inst.addOperand(MCOperand::CreateReg(0));
1180 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1181 Inst.addOperand(MCOperand::CreateImm(tmp));
1182 }
1183
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1184 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1185 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1187 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1188}
1189
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1190static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1191 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1192 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1193
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1194 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1195 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1196 unsigned type = fieldFromInstruction32(Val, 5, 2);
1197 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1198 unsigned U = fieldFromInstruction32(Val, 12, 1);
1199
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1200 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1201 switch (type) {
1202 case 0:
1203 ShOp = ARM_AM::lsl;
1204 break;
1205 case 1:
1206 ShOp = ARM_AM::lsr;
1207 break;
1208 case 2:
1209 ShOp = ARM_AM::asr;
1210 break;
1211 case 3:
1212 ShOp = ARM_AM::ror;
1213 break;
1214 }
1215
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1217 return MCDisassembler::Fail;
1218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1219 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1220 unsigned shift;
1221 if (U)
1222 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1223 else
1224 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1225 Inst.addOperand(MCOperand::CreateImm(shift));
1226
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1227 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1228}
1229
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1230static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1231DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1232 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1233 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1234
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1236 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1237 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1238 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1239 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1240 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1241 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1242 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1243 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1244
1245 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1246
1247 // For {LD,ST}RD, Rt must be even, else undefined.
1248 switch (Inst.getOpcode()) {
1249 case ARM::STRD:
1250 case ARM::STRD_PRE:
1251 case ARM::STRD_POST:
1252 case ARM::LDRD:
1253 case ARM::LDRD_PRE:
1254 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1255 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1256 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1257 default:
1258 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1259 }
1260
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1261 if (writeback) { // Writeback
1262 if (P)
1263 U |= ARMII::IndexModePre << 9;
1264 else
1265 U |= ARMII::IndexModePost << 9;
1266
1267 // On stores, the writeback operand precedes Rt.
1268 switch (Inst.getOpcode()) {
1269 case ARM::STRD:
1270 case ARM::STRD_PRE:
1271 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1272 case ARM::STRH:
1273 case ARM::STRH_PRE:
1274 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1276 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1277 break;
1278 default:
1279 break;
1280 }
1281 }
1282
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1284 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1285 switch (Inst.getOpcode()) {
1286 case ARM::STRD:
1287 case ARM::STRD_PRE:
1288 case ARM::STRD_POST:
1289 case ARM::LDRD:
1290 case ARM::LDRD_PRE:
1291 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1293 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1294 break;
1295 default:
1296 break;
1297 }
1298
1299 if (writeback) {
1300 // On loads, the writeback operand comes after Rt.
1301 switch (Inst.getOpcode()) {
1302 case ARM::LDRD:
1303 case ARM::LDRD_PRE:
1304 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1305 case ARM::LDRH:
1306 case ARM::LDRH_PRE:
1307 case ARM::LDRH_POST:
1308 case ARM::LDRSH:
1309 case ARM::LDRSH_PRE:
1310 case ARM::LDRSH_POST:
1311 case ARM::LDRSB:
1312 case ARM::LDRSB_PRE:
1313 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1314 case ARM::LDRHTr:
1315 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1317 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1318 break;
1319 default:
1320 break;
1321 }
1322 }
1323
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1325 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1326
1327 if (type) {
1328 Inst.addOperand(MCOperand::CreateReg(0));
1329 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1330 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1332 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1333 Inst.addOperand(MCOperand::CreateImm(U));
1334 }
1335
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1336 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1337 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1338
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1339 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1340}
1341
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1342static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1343 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1344 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1345
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1346 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1347 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1348
1349 switch (mode) {
1350 case 0:
1351 mode = ARM_AM::da;
1352 break;
1353 case 1:
1354 mode = ARM_AM::ia;
1355 break;
1356 case 2:
1357 mode = ARM_AM::db;
1358 break;
1359 case 3:
1360 mode = ARM_AM::ib;
1361 break;
1362 }
1363
1364 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1366 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1367
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1368 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1369}
1370
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1371static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1372 unsigned Insn,
1373 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1374 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1375
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1377 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1378 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1379
1380 if (pred == 0xF) {
1381 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1382 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1383 Inst.setOpcode(ARM::RFEDA);
1384 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1385 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386 Inst.setOpcode(ARM::RFEDA_UPD);
1387 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1388 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1389 Inst.setOpcode(ARM::RFEDB);
1390 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1391 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1392 Inst.setOpcode(ARM::RFEDB_UPD);
1393 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1394 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1395 Inst.setOpcode(ARM::RFEIA);
1396 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1397 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1398 Inst.setOpcode(ARM::RFEIA_UPD);
1399 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1400 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1401 Inst.setOpcode(ARM::RFEIB);
1402 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1403 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1404 Inst.setOpcode(ARM::RFEIB_UPD);
1405 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1406 case ARM::STMDA:
1407 Inst.setOpcode(ARM::SRSDA);
1408 break;
1409 case ARM::STMDA_UPD:
1410 Inst.setOpcode(ARM::SRSDA_UPD);
1411 break;
1412 case ARM::STMDB:
1413 Inst.setOpcode(ARM::SRSDB);
1414 break;
1415 case ARM::STMDB_UPD:
1416 Inst.setOpcode(ARM::SRSDB_UPD);
1417 break;
1418 case ARM::STMIA:
1419 Inst.setOpcode(ARM::SRSIA);
1420 break;
1421 case ARM::STMIA_UPD:
1422 Inst.setOpcode(ARM::SRSIA_UPD);
1423 break;
1424 case ARM::STMIB:
1425 Inst.setOpcode(ARM::SRSIB);
1426 break;
1427 case ARM::STMIB_UPD:
1428 Inst.setOpcode(ARM::SRSIB_UPD);
1429 break;
1430 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1431 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1432 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1433
1434 // For stores (which become SRS's, the only operand is the mode.
1435 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1436 Inst.addOperand(
1437 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1438 return S;
1439 }
1440
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1441 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1442 }
1443
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1445 return MCDisassembler::Fail;
1446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1447 return MCDisassembler::Fail; // Tied
1448 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1449 return MCDisassembler::Fail;
1450 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1451 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1452
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1453 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1454}
1455
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1456static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1457 uint64_t Address, const void *Decoder) {
1458 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1459 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1460 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1461 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1462
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1463 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1464
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1465 // imod == '01' --> UNPREDICTABLE
1466 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1467 // return failure here. The '01' imod value is unprintable, so there's
1468 // nothing useful we could do even if we returned UNPREDICTABLE.
1469
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1470 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1471
1472 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1473 Inst.setOpcode(ARM::CPS3p);
1474 Inst.addOperand(MCOperand::CreateImm(imod));
1475 Inst.addOperand(MCOperand::CreateImm(iflags));
1476 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1477 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1478 Inst.setOpcode(ARM::CPS2p);
1479 Inst.addOperand(MCOperand::CreateImm(imod));
1480 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1481 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1482 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1483 Inst.setOpcode(ARM::CPS1p);
1484 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1485 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1486 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1487 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1488 Inst.setOpcode(ARM::CPS1p);
1489 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1490 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1491 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1492
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1493 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1494}
1495
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1496static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1497 uint64_t Address, const void *Decoder) {
1498 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1499 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1500 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1501 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1502
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1503 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1504
1505 // imod == '01' --> UNPREDICTABLE
1506 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1507 // return failure here. The '01' imod value is unprintable, so there's
1508 // nothing useful we could do even if we returned UNPREDICTABLE.
1509
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1510 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1511
1512 if (imod && M) {
1513 Inst.setOpcode(ARM::t2CPS3p);
1514 Inst.addOperand(MCOperand::CreateImm(imod));
1515 Inst.addOperand(MCOperand::CreateImm(iflags));
1516 Inst.addOperand(MCOperand::CreateImm(mode));
1517 } else if (imod && !M) {
1518 Inst.setOpcode(ARM::t2CPS2p);
1519 Inst.addOperand(MCOperand::CreateImm(imod));
1520 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1521 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1522 } else if (!imod && M) {
1523 Inst.setOpcode(ARM::t2CPS1p);
1524 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1525 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1526 } else {
1527 // imod == '00' && M == '0' --> UNPREDICTABLE
1528 Inst.setOpcode(ARM::t2CPS1p);
1529 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1530 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1531 }
1532
1533 return S;
1534}
1535
1536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1537static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1538 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1539 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1540
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1541 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1542 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1543 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1544 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1545 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1546
1547 if (pred == 0xF)
1548 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1550 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1551 return MCDisassembler::Fail;
1552 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1553 return MCDisassembler::Fail;
1554 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1555 return MCDisassembler::Fail;
1556 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1557 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1558
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1560 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1561
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1562 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1563}
1564
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1565static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1566 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1567 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1568
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1569 unsigned add = fieldFromInstruction32(Val, 12, 1);
1570 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1571 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1574 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1575
1576 if (!add) imm *= -1;
1577 if (imm == 0 && !add) imm = INT32_MIN;
1578 Inst.addOperand(MCOperand::CreateImm(imm));
1579
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1580 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1581}
1582
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1583static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1584 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1585 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1586
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1587 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1588 unsigned U = fieldFromInstruction32(Val, 8, 1);
1589 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1590
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1592 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1593
1594 if (U)
1595 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1596 else
1597 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1598
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1599 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1600}
1601
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1602static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1603 uint64_t Address, const void *Decoder) {
1604 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1605}
1606
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1607static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1608DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1611
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1612 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1613 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1614
1615 if (pred == 0xF) {
1616 Inst.setOpcode(ARM::BLXi);
1617 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1618 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1619 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1620 }
1621
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1622 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1623 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1624 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1625
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1626 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1627}
1628
1629
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1630static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1631 uint64_t Address, const void *Decoder) {
1632 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1633 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1634}
1635
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1636static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1638 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1639
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1640 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1641 unsigned align = fieldFromInstruction32(Val, 4, 2);
1642
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1644 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1645 if (!align)
1646 Inst.addOperand(MCOperand::CreateImm(0));
1647 else
1648 Inst.addOperand(MCOperand::CreateImm(4 << align));
1649
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1650 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1651}
1652
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1653static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1654 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1655 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1656
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1657 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1658 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1659 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1660 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1661 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1662 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1663
1664 // First output register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1666 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1667
1668 // Second output register
1669 switch (Inst.getOpcode()) {
1670 case ARM::VLD1q8:
1671 case ARM::VLD1q16:
1672 case ARM::VLD1q32:
1673 case ARM::VLD1q64:
1674 case ARM::VLD1q8_UPD:
1675 case ARM::VLD1q16_UPD:
1676 case ARM::VLD1q32_UPD:
1677 case ARM::VLD1q64_UPD:
1678 case ARM::VLD1d8T:
1679 case ARM::VLD1d16T:
1680 case ARM::VLD1d32T:
1681 case ARM::VLD1d64T:
1682 case ARM::VLD1d8T_UPD:
1683 case ARM::VLD1d16T_UPD:
1684 case ARM::VLD1d32T_UPD:
1685 case ARM::VLD1d64T_UPD:
1686 case ARM::VLD1d8Q:
1687 case ARM::VLD1d16Q:
1688 case ARM::VLD1d32Q:
1689 case ARM::VLD1d64Q:
1690 case ARM::VLD1d8Q_UPD:
1691 case ARM::VLD1d16Q_UPD:
1692 case ARM::VLD1d32Q_UPD:
1693 case ARM::VLD1d64Q_UPD:
1694 case ARM::VLD2d8:
1695 case ARM::VLD2d16:
1696 case ARM::VLD2d32:
1697 case ARM::VLD2d8_UPD:
1698 case ARM::VLD2d16_UPD:
1699 case ARM::VLD2d32_UPD:
1700 case ARM::VLD2q8:
1701 case ARM::VLD2q16:
1702 case ARM::VLD2q32:
1703 case ARM::VLD2q8_UPD:
1704 case ARM::VLD2q16_UPD:
1705 case ARM::VLD2q32_UPD:
1706 case ARM::VLD3d8:
1707 case ARM::VLD3d16:
1708 case ARM::VLD3d32:
1709 case ARM::VLD3d8_UPD:
1710 case ARM::VLD3d16_UPD:
1711 case ARM::VLD3d32_UPD:
1712 case ARM::VLD4d8:
1713 case ARM::VLD4d16:
1714 case ARM::VLD4d32:
1715 case ARM::VLD4d8_UPD:
1716 case ARM::VLD4d16_UPD:
1717 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1718 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1719 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1720 break;
1721 case ARM::VLD2b8:
1722 case ARM::VLD2b16:
1723 case ARM::VLD2b32:
1724 case ARM::VLD2b8_UPD:
1725 case ARM::VLD2b16_UPD:
1726 case ARM::VLD2b32_UPD:
1727 case ARM::VLD3q8:
1728 case ARM::VLD3q16:
1729 case ARM::VLD3q32:
1730 case ARM::VLD3q8_UPD:
1731 case ARM::VLD3q16_UPD:
1732 case ARM::VLD3q32_UPD:
1733 case ARM::VLD4q8:
1734 case ARM::VLD4q16:
1735 case ARM::VLD4q32:
1736 case ARM::VLD4q8_UPD:
1737 case ARM::VLD4q16_UPD:
1738 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1739 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1740 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1741 default:
1742 break;
1743 }
1744
1745 // Third output register
1746 switch(Inst.getOpcode()) {
1747 case ARM::VLD1d8T:
1748 case ARM::VLD1d16T:
1749 case ARM::VLD1d32T:
1750 case ARM::VLD1d64T:
1751 case ARM::VLD1d8T_UPD:
1752 case ARM::VLD1d16T_UPD:
1753 case ARM::VLD1d32T_UPD:
1754 case ARM::VLD1d64T_UPD:
1755 case ARM::VLD1d8Q:
1756 case ARM::VLD1d16Q:
1757 case ARM::VLD1d32Q:
1758 case ARM::VLD1d64Q:
1759 case ARM::VLD1d8Q_UPD:
1760 case ARM::VLD1d16Q_UPD:
1761 case ARM::VLD1d32Q_UPD:
1762 case ARM::VLD1d64Q_UPD:
1763 case ARM::VLD2q8:
1764 case ARM::VLD2q16:
1765 case ARM::VLD2q32:
1766 case ARM::VLD2q8_UPD:
1767 case ARM::VLD2q16_UPD:
1768 case ARM::VLD2q32_UPD:
1769 case ARM::VLD3d8:
1770 case ARM::VLD3d16:
1771 case ARM::VLD3d32:
1772 case ARM::VLD3d8_UPD:
1773 case ARM::VLD3d16_UPD:
1774 case ARM::VLD3d32_UPD:
1775 case ARM::VLD4d8:
1776 case ARM::VLD4d16:
1777 case ARM::VLD4d32:
1778 case ARM::VLD4d8_UPD:
1779 case ARM::VLD4d16_UPD:
1780 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1781 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1782 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1783 break;
1784 case ARM::VLD3q8:
1785 case ARM::VLD3q16:
1786 case ARM::VLD3q32:
1787 case ARM::VLD3q8_UPD:
1788 case ARM::VLD3q16_UPD:
1789 case ARM::VLD3q32_UPD:
1790 case ARM::VLD4q8:
1791 case ARM::VLD4q16:
1792 case ARM::VLD4q32:
1793 case ARM::VLD4q8_UPD:
1794 case ARM::VLD4q16_UPD:
1795 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1796 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
1797 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1798 break;
1799 default:
1800 break;
1801 }
1802
1803 // Fourth output register
1804 switch (Inst.getOpcode()) {
1805 case ARM::VLD1d8Q:
1806 case ARM::VLD1d16Q:
1807 case ARM::VLD1d32Q:
1808 case ARM::VLD1d64Q:
1809 case ARM::VLD1d8Q_UPD:
1810 case ARM::VLD1d16Q_UPD:
1811 case ARM::VLD1d32Q_UPD:
1812 case ARM::VLD1d64Q_UPD:
1813 case ARM::VLD2q8:
1814 case ARM::VLD2q16:
1815 case ARM::VLD2q32:
1816 case ARM::VLD2q8_UPD:
1817 case ARM::VLD2q16_UPD:
1818 case ARM::VLD2q32_UPD:
1819 case ARM::VLD4d8:
1820 case ARM::VLD4d16:
1821 case ARM::VLD4d32:
1822 case ARM::VLD4d8_UPD:
1823 case ARM::VLD4d16_UPD:
1824 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1825 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
1826 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1827 break;
1828 case ARM::VLD4q8:
1829 case ARM::VLD4q16:
1830 case ARM::VLD4q32:
1831 case ARM::VLD4q8_UPD:
1832 case ARM::VLD4q16_UPD:
1833 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1834 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
1835 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1836 break;
1837 default:
1838 break;
1839 }
1840
1841 // Writeback operand
1842 switch (Inst.getOpcode()) {
1843 case ARM::VLD1d8_UPD:
1844 case ARM::VLD1d16_UPD:
1845 case ARM::VLD1d32_UPD:
1846 case ARM::VLD1d64_UPD:
1847 case ARM::VLD1q8_UPD:
1848 case ARM::VLD1q16_UPD:
1849 case ARM::VLD1q32_UPD:
1850 case ARM::VLD1q64_UPD:
1851 case ARM::VLD1d8T_UPD:
1852 case ARM::VLD1d16T_UPD:
1853 case ARM::VLD1d32T_UPD:
1854 case ARM::VLD1d64T_UPD:
1855 case ARM::VLD1d8Q_UPD:
1856 case ARM::VLD1d16Q_UPD:
1857 case ARM::VLD1d32Q_UPD:
1858 case ARM::VLD1d64Q_UPD:
1859 case ARM::VLD2d8_UPD:
1860 case ARM::VLD2d16_UPD:
1861 case ARM::VLD2d32_UPD:
1862 case ARM::VLD2q8_UPD:
1863 case ARM::VLD2q16_UPD:
1864 case ARM::VLD2q32_UPD:
1865 case ARM::VLD2b8_UPD:
1866 case ARM::VLD2b16_UPD:
1867 case ARM::VLD2b32_UPD:
1868 case ARM::VLD3d8_UPD:
1869 case ARM::VLD3d16_UPD:
1870 case ARM::VLD3d32_UPD:
1871 case ARM::VLD3q8_UPD:
1872 case ARM::VLD3q16_UPD:
1873 case ARM::VLD3q32_UPD:
1874 case ARM::VLD4d8_UPD:
1875 case ARM::VLD4d16_UPD:
1876 case ARM::VLD4d32_UPD:
1877 case ARM::VLD4q8_UPD:
1878 case ARM::VLD4q16_UPD:
1879 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1880 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1881 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1882 break;
1883 default:
1884 break;
1885 }
1886
1887 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1888 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1889 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1890
1891 // AddrMode6 Offset (register)
1892 if (Rm == 0xD)
1893 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1894 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1896 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1897 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1898
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1899 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1900}
1901
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1902static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1905
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1906 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1907 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1908 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1909 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1910 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1911 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1912
1913 // Writeback Operand
1914 switch (Inst.getOpcode()) {
1915 case ARM::VST1d8_UPD:
1916 case ARM::VST1d16_UPD:
1917 case ARM::VST1d32_UPD:
1918 case ARM::VST1d64_UPD:
1919 case ARM::VST1q8_UPD:
1920 case ARM::VST1q16_UPD:
1921 case ARM::VST1q32_UPD:
1922 case ARM::VST1q64_UPD:
1923 case ARM::VST1d8T_UPD:
1924 case ARM::VST1d16T_UPD:
1925 case ARM::VST1d32T_UPD:
1926 case ARM::VST1d64T_UPD:
1927 case ARM::VST1d8Q_UPD:
1928 case ARM::VST1d16Q_UPD:
1929 case ARM::VST1d32Q_UPD:
1930 case ARM::VST1d64Q_UPD:
1931 case ARM::VST2d8_UPD:
1932 case ARM::VST2d16_UPD:
1933 case ARM::VST2d32_UPD:
1934 case ARM::VST2q8_UPD:
1935 case ARM::VST2q16_UPD:
1936 case ARM::VST2q32_UPD:
1937 case ARM::VST2b8_UPD:
1938 case ARM::VST2b16_UPD:
1939 case ARM::VST2b32_UPD:
1940 case ARM::VST3d8_UPD:
1941 case ARM::VST3d16_UPD:
1942 case ARM::VST3d32_UPD:
1943 case ARM::VST3q8_UPD:
1944 case ARM::VST3q16_UPD:
1945 case ARM::VST3q32_UPD:
1946 case ARM::VST4d8_UPD:
1947 case ARM::VST4d16_UPD:
1948 case ARM::VST4d32_UPD:
1949 case ARM::VST4q8_UPD:
1950 case ARM::VST4q16_UPD:
1951 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1952 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
1953 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1954 break;
1955 default:
1956 break;
1957 }
1958
1959 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1960 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
1961 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1962
1963 // AddrMode6 Offset (register)
1964 if (Rm == 0xD)
1965 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1966 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1968 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1969 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1970
1971 // First input register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1972 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1973 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1974
1975 // Second input register
1976 switch (Inst.getOpcode()) {
1977 case ARM::VST1q8:
1978 case ARM::VST1q16:
1979 case ARM::VST1q32:
1980 case ARM::VST1q64:
1981 case ARM::VST1q8_UPD:
1982 case ARM::VST1q16_UPD:
1983 case ARM::VST1q32_UPD:
1984 case ARM::VST1q64_UPD:
1985 case ARM::VST1d8T:
1986 case ARM::VST1d16T:
1987 case ARM::VST1d32T:
1988 case ARM::VST1d64T:
1989 case ARM::VST1d8T_UPD:
1990 case ARM::VST1d16T_UPD:
1991 case ARM::VST1d32T_UPD:
1992 case ARM::VST1d64T_UPD:
1993 case ARM::VST1d8Q:
1994 case ARM::VST1d16Q:
1995 case ARM::VST1d32Q:
1996 case ARM::VST1d64Q:
1997 case ARM::VST1d8Q_UPD:
1998 case ARM::VST1d16Q_UPD:
1999 case ARM::VST1d32Q_UPD:
2000 case ARM::VST1d64Q_UPD:
2001 case ARM::VST2d8:
2002 case ARM::VST2d16:
2003 case ARM::VST2d32:
2004 case ARM::VST2d8_UPD:
2005 case ARM::VST2d16_UPD:
2006 case ARM::VST2d32_UPD:
2007 case ARM::VST2q8:
2008 case ARM::VST2q16:
2009 case ARM::VST2q32:
2010 case ARM::VST2q8_UPD:
2011 case ARM::VST2q16_UPD:
2012 case ARM::VST2q32_UPD:
2013 case ARM::VST3d8:
2014 case ARM::VST3d16:
2015 case ARM::VST3d32:
2016 case ARM::VST3d8_UPD:
2017 case ARM::VST3d16_UPD:
2018 case ARM::VST3d32_UPD:
2019 case ARM::VST4d8:
2020 case ARM::VST4d16:
2021 case ARM::VST4d32:
2022 case ARM::VST4d8_UPD:
2023 case ARM::VST4d16_UPD:
2024 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2025 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2026 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2027 break;
2028 case ARM::VST2b8:
2029 case ARM::VST2b16:
2030 case ARM::VST2b32:
2031 case ARM::VST2b8_UPD:
2032 case ARM::VST2b16_UPD:
2033 case ARM::VST2b32_UPD:
2034 case ARM::VST3q8:
2035 case ARM::VST3q16:
2036 case ARM::VST3q32:
2037 case ARM::VST3q8_UPD:
2038 case ARM::VST3q16_UPD:
2039 case ARM::VST3q32_UPD:
2040 case ARM::VST4q8:
2041 case ARM::VST4q16:
2042 case ARM::VST4q32:
2043 case ARM::VST4q8_UPD:
2044 case ARM::VST4q16_UPD:
2045 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2046 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2047 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2048 break;
2049 default:
2050 break;
2051 }
2052
2053 // Third input register
2054 switch (Inst.getOpcode()) {
2055 case ARM::VST1d8T:
2056 case ARM::VST1d16T:
2057 case ARM::VST1d32T:
2058 case ARM::VST1d64T:
2059 case ARM::VST1d8T_UPD:
2060 case ARM::VST1d16T_UPD:
2061 case ARM::VST1d32T_UPD:
2062 case ARM::VST1d64T_UPD:
2063 case ARM::VST1d8Q:
2064 case ARM::VST1d16Q:
2065 case ARM::VST1d32Q:
2066 case ARM::VST1d64Q:
2067 case ARM::VST1d8Q_UPD:
2068 case ARM::VST1d16Q_UPD:
2069 case ARM::VST1d32Q_UPD:
2070 case ARM::VST1d64Q_UPD:
2071 case ARM::VST2q8:
2072 case ARM::VST2q16:
2073 case ARM::VST2q32:
2074 case ARM::VST2q8_UPD:
2075 case ARM::VST2q16_UPD:
2076 case ARM::VST2q32_UPD:
2077 case ARM::VST3d8:
2078 case ARM::VST3d16:
2079 case ARM::VST3d32:
2080 case ARM::VST3d8_UPD:
2081 case ARM::VST3d16_UPD:
2082 case ARM::VST3d32_UPD:
2083 case ARM::VST4d8:
2084 case ARM::VST4d16:
2085 case ARM::VST4d32:
2086 case ARM::VST4d8_UPD:
2087 case ARM::VST4d16_UPD:
2088 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2090 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2091 break;
2092 case ARM::VST3q8:
2093 case ARM::VST3q16:
2094 case ARM::VST3q32:
2095 case ARM::VST3q8_UPD:
2096 case ARM::VST3q16_UPD:
2097 case ARM::VST3q32_UPD:
2098 case ARM::VST4q8:
2099 case ARM::VST4q16:
2100 case ARM::VST4q32:
2101 case ARM::VST4q8_UPD:
2102 case ARM::VST4q16_UPD:
2103 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2104 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2105 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2106 break;
2107 default:
2108 break;
2109 }
2110
2111 // Fourth input register
2112 switch (Inst.getOpcode()) {
2113 case ARM::VST1d8Q:
2114 case ARM::VST1d16Q:
2115 case ARM::VST1d32Q:
2116 case ARM::VST1d64Q:
2117 case ARM::VST1d8Q_UPD:
2118 case ARM::VST1d16Q_UPD:
2119 case ARM::VST1d32Q_UPD:
2120 case ARM::VST1d64Q_UPD:
2121 case ARM::VST2q8:
2122 case ARM::VST2q16:
2123 case ARM::VST2q32:
2124 case ARM::VST2q8_UPD:
2125 case ARM::VST2q16_UPD:
2126 case ARM::VST2q32_UPD:
2127 case ARM::VST4d8:
2128 case ARM::VST4d16:
2129 case ARM::VST4d32:
2130 case ARM::VST4d8_UPD:
2131 case ARM::VST4d16_UPD:
2132 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2133 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2134 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2135 break;
2136 case ARM::VST4q8:
2137 case ARM::VST4q16:
2138 case ARM::VST4q32:
2139 case ARM::VST4q8_UPD:
2140 case ARM::VST4q16_UPD:
2141 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2142 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2143 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2144 break;
2145 default:
2146 break;
2147 }
2148
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2149 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2150}
2151
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2152static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2153 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2154 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2155
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2156 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2157 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2160 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2161 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2162 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2163
2164 align *= (1 << size);
2165
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2167 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2168 if (regs == 2) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2169 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2170 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2171 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2172 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2174 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2175 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2176
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2178 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2179 Inst.addOperand(MCOperand::CreateImm(align));
2180
2181 if (Rm == 0xD)
2182 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2183 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2185 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2186 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2187
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2188 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2189}
2190
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2191static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2192 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2193 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2194
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2195 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2196 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2197 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2198 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2199 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2200 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2201 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2202 align *= 2*size;
2203
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2205 return MCDisassembler::Fail;
2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2207 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2208 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2210 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2211 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2212
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2214 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2215 Inst.addOperand(MCOperand::CreateImm(align));
2216
2217 if (Rm == 0xD)
2218 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2219 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2221 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2222 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2223
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2224 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2225}
2226
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2227static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2228 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2229 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2230
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2231 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2232 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2233 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2234 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2235 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2236
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2238 return MCDisassembler::Fail;
2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2240 return MCDisassembler::Fail;
2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2242 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2243 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2245 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2246 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2247
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2249 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2250 Inst.addOperand(MCOperand::CreateImm(0));
2251
2252 if (Rm == 0xD)
2253 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2254 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2256 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2257 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2258
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2259 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2260}
2261
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2262static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2263 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2264 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2265
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2266 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2267 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2268 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2269 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2270 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2271 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2272 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2273
2274 if (size == 0x3) {
2275 size = 4;
2276 align = 16;
2277 } else {
2278 if (size == 2) {
2279 size = 1 << size;
2280 align *= 8;
2281 } else {
2282 size = 1 << size;
2283 align *= 4*size;
2284 }
2285 }
2286
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2288 return MCDisassembler::Fail;
2289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2290 return MCDisassembler::Fail;
2291 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2292 return MCDisassembler::Fail;
2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2294 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2295 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2297 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2298 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2299
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2301 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2302 Inst.addOperand(MCOperand::CreateImm(align));
2303
2304 if (Rm == 0xD)
2305 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2306 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2308 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2309 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2310
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2311 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2312}
2313
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2314static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2315DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2316 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2317 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2318
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2319 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2320 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2321 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2322 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2323 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2324 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2325 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2326 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2327
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2328 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2329 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2330 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2331 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2332 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2333 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2334 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2335
2336 Inst.addOperand(MCOperand::CreateImm(imm));
2337
2338 switch (Inst.getOpcode()) {
2339 case ARM::VORRiv4i16:
2340 case ARM::VORRiv2i32:
2341 case ARM::VBICiv4i16:
2342 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2344 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2345 break;
2346 case ARM::VORRiv8i16:
2347 case ARM::VORRiv4i32:
2348 case ARM::VBICiv8i16:
2349 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2350 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2351 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2352 break;
2353 default:
2354 break;
2355 }
2356
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2357 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2358}
2359
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2360static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2361 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2362 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2363
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2364 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2365 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2366 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2367 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2368 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2370 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2371 return MCDisassembler::Fail;
2372 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2373 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2374 Inst.addOperand(MCOperand::CreateImm(8 << size));
2375
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2376 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2377}
2378
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2379static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2380 uint64_t Address, const void *Decoder) {
2381 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2382 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2383}
2384
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2385static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2386 uint64_t Address, const void *Decoder) {
2387 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2388 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2389}
2390
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2391static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2392 uint64_t Address, const void *Decoder) {
2393 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2394 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2395}
2396
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2397static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2398 uint64_t Address, const void *Decoder) {
2399 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2400 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2401}
2402
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2403static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2404 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2405 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2406
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2407 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2408 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2409 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2410 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2411 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2412 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2413 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2414 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2415
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2417 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2418 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2419 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2420 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2421 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2422
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2423 for (unsigned i = 0; i < length; ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2425 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2426 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2427
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2429 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2430
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2431 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2432}
2433
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2434static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2435 uint64_t Address, const void *Decoder) {
2436 // The immediate needs to be a fully instantiated float. However, the
2437 // auto-generated decoder is only able to fill in some of the bits
2438 // necessary. For instance, the 'b' bit is replicated multiple times,
2439 // and is even present in inverted form in one bit. We do a little
2440 // binary parsing here to fill in those missing bits, and then
2441 // reinterpret it all as a float.
2442 union {
2443 uint32_t integer;
2444 float fp;
2445 } fp_conv;
2446
2447 fp_conv.integer = Val;
2448 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2449 fp_conv.integer |= b << 26;
2450 fp_conv.integer |= b << 27;
2451 fp_conv.integer |= b << 28;
2452 fp_conv.integer |= b << 29;
2453 fp_conv.integer |= (~b & 0x1) << 30;
2454
2455 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2456 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2457}
2458
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2459static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2460 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2461 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2462
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2463 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2464 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2466 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2467 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2469 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2470 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2471 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2472 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2473 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2474 case ARM::tADDrSPi:
2475 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2476 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2477 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2478
2479 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2480 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481}
2482
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2483static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2484 uint64_t Address, const void *Decoder) {
2485 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2486 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2487}
2488
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2489static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490 uint64_t Address, const void *Decoder) {
2491 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2492 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2493}
2494
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2495static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496 uint64_t Address, const void *Decoder) {
2497 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2498 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2499}
2500
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2501static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2502 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2503 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2504
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2505 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2506 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2507
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2508 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2509 return MCDisassembler::Fail;
2510 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2511 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2512
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2513 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2514}
2515
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2516static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2517 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2518 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2519
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2520 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2521 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2522
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2523 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2524 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2525 Inst.addOperand(MCOperand::CreateImm(imm));
2526
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2527 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2528}
2529
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2531 uint64_t Address, const void *Decoder) {
2532 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2533
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2534 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2535}
2536
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2537static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538 uint64_t Address, const void *Decoder) {
2539 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2540 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2541
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2542 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2543}
2544
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2545static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2546 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2547 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2548
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2549 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2550 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2551 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2552
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2554 return MCDisassembler::Fail;
2555 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2556 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2557 Inst.addOperand(MCOperand::CreateImm(imm));
2558
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2559 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2560}
2561
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2562static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2563 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2564 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2565
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2566 switch (Inst.getOpcode()) {
2567 case ARM::t2PLDs:
2568 case ARM::t2PLDWs:
2569 case ARM::t2PLIs:
2570 break;
2571 default: {
2572 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2574 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2575 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2576 }
2577
2578 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2579 if (Rn == 0xF) {
2580 switch (Inst.getOpcode()) {
2581 case ARM::t2LDRBs:
2582 Inst.setOpcode(ARM::t2LDRBpci);
2583 break;
2584 case ARM::t2LDRHs:
2585 Inst.setOpcode(ARM::t2LDRHpci);
2586 break;
2587 case ARM::t2LDRSHs:
2588 Inst.setOpcode(ARM::t2LDRSHpci);
2589 break;
2590 case ARM::t2LDRSBs:
2591 Inst.setOpcode(ARM::t2LDRSBpci);
2592 break;
2593 case ARM::t2PLDs:
2594 Inst.setOpcode(ARM::t2PLDi12);
2595 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2596 break;
2597 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2598 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2599 }
2600
2601 int imm = fieldFromInstruction32(Insn, 0, 12);
2602 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2603 Inst.addOperand(MCOperand::CreateImm(imm));
2604
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2605 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2606 }
2607
2608 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2609 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2610 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2611 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2612 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2613
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2614 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2615}
2616
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2617static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2618 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2619 int imm = Val & 0xFF;
2620 if (!(Val & 0x100)) imm *= -1;
2621 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2622
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2623 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2624}
2625
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2626static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2627 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2628 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2629
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2630 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2631 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2632
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2634 return MCDisassembler::Fail;
2635 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2636 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2637
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2638 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2639}
2640
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2641static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2642 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2643 int imm = Val & 0xFF;
2644 if (!(Val & 0x100)) imm *= -1;
2645 Inst.addOperand(MCOperand::CreateImm(imm));
2646
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2647 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2648}
2649
2650
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2651static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2652 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2653 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2654
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2655 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2656 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2657
2658 // Some instructions always use an additive offset.
2659 switch (Inst.getOpcode()) {
2660 case ARM::t2LDRT:
2661 case ARM::t2LDRBT:
2662 case ARM::t2LDRHT:
2663 case ARM::t2LDRSBT:
2664 case ARM::t2LDRSHT:
2665 imm |= 0x100;
2666 break;
2667 default:
2668 break;
2669 }
2670
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2672 return MCDisassembler::Fail;
2673 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2674 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2675
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2676 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2677}
2678
2679
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2680static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2681 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2682 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2683
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2684 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2685 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2688 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2689 Inst.addOperand(MCOperand::CreateImm(imm));
2690
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2691 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2692}
2693
2694
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2695static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2696 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2697 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2698
2699 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2700 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2701 Inst.addOperand(MCOperand::CreateImm(imm));
2702
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2703 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2704}
2705
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2706static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2707 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2708 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2709
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2710 if (Inst.getOpcode() == ARM::tADDrSP) {
2711 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2712 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2715 return MCDisassembler::Fail;
2716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2717 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]2718 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719 } else if (Inst.getOpcode() == ARM::tADDspr) {
2720 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2721
2722 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2723 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2725 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2726 }
2727
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2728 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729}
2730
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2731static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2732 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2733 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2734 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2735
2736 Inst.addOperand(MCOperand::CreateImm(imod));
2737 Inst.addOperand(MCOperand::CreateImm(flags));
2738
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2739 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2740}
2741
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2742static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2743 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2744 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2745 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2746 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2747
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2749 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2750 Inst.addOperand(MCOperand::CreateImm(add));
2751
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2752 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2753}
2754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2755static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2756 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2758 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2759}
2760
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2761static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2762 uint64_t Address, const void *Decoder) {
2763 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2764 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2765
2766 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2767 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768}
2769
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2770static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2771DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2772 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2773 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2774
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2775 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2776 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2777 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2778 switch (opc) {
2779 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2780 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2781 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2782 Inst.setOpcode(ARM::t2DSB);
2783 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2784 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2785 Inst.setOpcode(ARM::t2DMB);
2786 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]2787 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2788 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame^]2789 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790 }
2791
2792 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2793 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2794 }
2795
2796 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2797 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2798 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2799 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2800 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2801
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2802 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
2803 return MCDisassembler::Fail;
2804 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2805 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2806
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2807 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2808}
2809
2810// Decode a shifted immediate operand. These basically consist
2811// of an 8-bit value, and a 4-bit directive that specifies either
2812// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2813static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814 uint64_t Address, const void *Decoder) {
2815 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2816 if (ctrl == 0) {
2817 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2818 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2819 switch (byte) {
2820 case 0:
2821 Inst.addOperand(MCOperand::CreateImm(imm));
2822 break;
2823 case 1:
2824 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2825 break;
2826 case 2:
2827 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2828 break;
2829 case 3:
2830 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2831 (imm << 8) | imm));
2832 break;
2833 }
2834 } else {
2835 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2836 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2837 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2838 Inst.addOperand(MCOperand::CreateImm(imm));
2839 }
2840
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2841 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2842}
2843
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2844static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2845DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2846 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2847 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2848 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2849}
2850
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2851static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]2852 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2853 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2854 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2855}
2856
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2857static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2858 uint64_t Address, const void *Decoder) {
2859 switch (Val) {
2860 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2861 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2862 case 0xF: // SY
2863 case 0xE: // ST
2864 case 0xB: // ISH
2865 case 0xA: // ISHST
2866 case 0x7: // NSH
2867 case 0x6: // NSHST
2868 case 0x3: // OSH
2869 case 0x2: // OSHST
2870 break;
2871 }
2872
2873 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2874 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]2875}
2876
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2877static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2878 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2879 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2880 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2881 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]2882}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2883
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2884static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2885 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2886 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2887
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2888 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2890 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2891
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2892 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2895 return MCDisassembler::Fail;
2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2897 return MCDisassembler::Fail;
2898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2899 return MCDisassembler::Fail;
2900 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2901 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2902
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2903 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]2904}
2905
2906
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2907static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2908 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2909 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2910
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2911 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2912 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2913 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]2914 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2915
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2916 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2917 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2918
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2919 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
2920 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2921
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2923 return MCDisassembler::Fail;
2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2925 return MCDisassembler::Fail;
2926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2927 return MCDisassembler::Fail;
2928 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2929 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2930
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2931 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2932}
2933
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2934static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2935 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2936 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2937
2938 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2939 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2940 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2941 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2942 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2943 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2944
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2945 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2946
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2948 return MCDisassembler::Fail;
2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2950 return MCDisassembler::Fail;
2951 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
2952 return MCDisassembler::Fail;
2953 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2954 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2955
2956 return S;
2957}
2958
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2959static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2960 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2961 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2962
2963 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2964 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2965 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2966 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2967 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2968 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2969 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2970
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2971 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
2972 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2973
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2975 return MCDisassembler::Fail;
2976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2977 return MCDisassembler::Fail;
2978 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
2979 return MCDisassembler::Fail;
2980 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2981 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]2982
2983 return S;
2984}
2985
2986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2987static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2988 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2989 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2990
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2991 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2992 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2993 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2994 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2995 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2996 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]2997
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2998 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]2999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3001 return MCDisassembler::Fail;
3002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3003 return MCDisassembler::Fail;
3004 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3005 return MCDisassembler::Fail;
3006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3007 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3008
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3009 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3010}
3011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3012static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3013 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3014 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3015
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3016 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3017 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3018 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3019 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3020 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3021 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3022
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3023 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3024
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3026 return MCDisassembler::Fail;
3027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3028 return MCDisassembler::Fail;
3029 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3030 return MCDisassembler::Fail;
3031 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3032 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3033
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3034 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3035}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3036
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3037static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3038 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3039 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3040
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3041 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3042 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3043 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3044 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3045 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3046
3047 unsigned align = 0;
3048 unsigned index = 0;
3049 switch (size) {
3050 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3051 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3052 case 0:
3053 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3054 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3055 index = fieldFromInstruction32(Insn, 5, 3);
3056 break;
3057 case 1:
3058 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3059 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3060 index = fieldFromInstruction32(Insn, 6, 2);
3061 if (fieldFromInstruction32(Insn, 4, 1))
3062 align = 2;
3063 break;
3064 case 2:
3065 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3066 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3067 index = fieldFromInstruction32(Insn, 7, 1);
3068 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3069 align = 4;
3070 }
3071
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3072 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3073 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3074 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3076 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3077 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3079 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3080 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3081 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3082 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3084 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3085 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3086 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3087 }
3088
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3089 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3090 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3091 Inst.addOperand(MCOperand::CreateImm(index));
3092
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3093 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3094}
3095
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3096static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3097 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3098 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3099
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3100 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3101 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3102 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3103 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3104 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3105
3106 unsigned align = 0;
3107 unsigned index = 0;
3108 switch (size) {
3109 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3110 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3111 case 0:
3112 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3113 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3114 index = fieldFromInstruction32(Insn, 5, 3);
3115 break;
3116 case 1:
3117 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3118 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3119 index = fieldFromInstruction32(Insn, 6, 2);
3120 if (fieldFromInstruction32(Insn, 4, 1))
3121 align = 2;
3122 break;
3123 case 2:
3124 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3125 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3126 index = fieldFromInstruction32(Insn, 7, 1);
3127 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3128 align = 4;
3129 }
3130
3131 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3133 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3134 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3136 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3137 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3138 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3139 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3141 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3142 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3143 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3144 }
3145
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3147 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3148 Inst.addOperand(MCOperand::CreateImm(index));
3149
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3150 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3151}
3152
3153
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3154static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3155 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3156 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3157
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3158 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3160 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3161 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3162 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3163
3164 unsigned align = 0;
3165 unsigned index = 0;
3166 unsigned inc = 1;
3167 switch (size) {
3168 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3169 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3170 case 0:
3171 index = fieldFromInstruction32(Insn, 5, 3);
3172 if (fieldFromInstruction32(Insn, 4, 1))
3173 align = 2;
3174 break;
3175 case 1:
3176 index = fieldFromInstruction32(Insn, 6, 2);
3177 if (fieldFromInstruction32(Insn, 4, 1))
3178 align = 4;
3179 if (fieldFromInstruction32(Insn, 5, 1))
3180 inc = 2;
3181 break;
3182 case 2:
3183 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3184 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3185 index = fieldFromInstruction32(Insn, 7, 1);
3186 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3187 align = 8;
3188 if (fieldFromInstruction32(Insn, 6, 1))
3189 inc = 2;
3190 break;
3191 }
3192
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3193 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3194 return MCDisassembler::Fail;
3195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3196 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3197 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3199 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3200 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3202 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3203 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3204 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3205 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3207 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3208 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3209 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3210 }
3211
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3213 return MCDisassembler::Fail;
3214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3215 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3216 Inst.addOperand(MCOperand::CreateImm(index));
3217
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3218 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3219}
3220
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3221static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3222 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3223 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3224
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3226 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3227 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3228 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3229 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3230
3231 unsigned align = 0;
3232 unsigned index = 0;
3233 unsigned inc = 1;
3234 switch (size) {
3235 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3236 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3237 case 0:
3238 index = fieldFromInstruction32(Insn, 5, 3);
3239 if (fieldFromInstruction32(Insn, 4, 1))
3240 align = 2;
3241 break;
3242 case 1:
3243 index = fieldFromInstruction32(Insn, 6, 2);
3244 if (fieldFromInstruction32(Insn, 4, 1))
3245 align = 4;
3246 if (fieldFromInstruction32(Insn, 5, 1))
3247 inc = 2;
3248 break;
3249 case 2:
3250 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3251 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3252 index = fieldFromInstruction32(Insn, 7, 1);
3253 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3254 align = 8;
3255 if (fieldFromInstruction32(Insn, 6, 1))
3256 inc = 2;
3257 break;
3258 }
3259
3260 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3262 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3263 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3265 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3266 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3267 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3268 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3270 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3271 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3272 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3273 }
3274
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3276 return MCDisassembler::Fail;
3277 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3278 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3279 Inst.addOperand(MCOperand::CreateImm(index));
3280
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3281 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3282}
3283
3284
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3285static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3286 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3287 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3288
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3289 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3290 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3291 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3292 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3293 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3294
3295 unsigned align = 0;
3296 unsigned index = 0;
3297 unsigned inc = 1;
3298 switch (size) {
3299 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3300 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3301 case 0:
3302 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3303 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3304 index = fieldFromInstruction32(Insn, 5, 3);
3305 break;
3306 case 1:
3307 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3308 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3309 index = fieldFromInstruction32(Insn, 6, 2);
3310 if (fieldFromInstruction32(Insn, 5, 1))
3311 inc = 2;
3312 break;
3313 case 2:
3314 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3315 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3316 index = fieldFromInstruction32(Insn, 7, 1);
3317 if (fieldFromInstruction32(Insn, 6, 1))
3318 inc = 2;
3319 break;
3320 }
3321
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3322 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3323 return MCDisassembler::Fail;
3324 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3325 return MCDisassembler::Fail;
3326 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3327 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3328
3329 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3331 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3332 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3334 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3335 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3336 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3337 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3339 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3340 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3341 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3342 }
3343
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3344 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3345 return MCDisassembler::Fail;
3346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3347 return MCDisassembler::Fail;
3348 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3349 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3350 Inst.addOperand(MCOperand::CreateImm(index));
3351
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3352 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3353}
3354
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3355static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3356 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3357 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3358
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3359 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3360 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3361 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3362 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3363 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3364
3365 unsigned align = 0;
3366 unsigned index = 0;
3367 unsigned inc = 1;
3368 switch (size) {
3369 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3370 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3371 case 0:
3372 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3373 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3374 index = fieldFromInstruction32(Insn, 5, 3);
3375 break;
3376 case 1:
3377 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3378 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3379 index = fieldFromInstruction32(Insn, 6, 2);
3380 if (fieldFromInstruction32(Insn, 5, 1))
3381 inc = 2;
3382 break;
3383 case 2:
3384 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3385 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3386 index = fieldFromInstruction32(Insn, 7, 1);
3387 if (fieldFromInstruction32(Insn, 6, 1))
3388 inc = 2;
3389 break;
3390 }
3391
3392 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3394 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3395 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3397 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3398 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3399 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3400 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3402 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3403 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3404 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3405 }
3406
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3410 return MCDisassembler::Fail;
3411 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3412 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3413 Inst.addOperand(MCOperand::CreateImm(index));
3414
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3415 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3416}
3417
3418
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3419static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3420 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3421 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3422
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3423 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3424 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3425 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3426 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3427 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3428
3429 unsigned align = 0;
3430 unsigned index = 0;
3431 unsigned inc = 1;
3432 switch (size) {
3433 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3434 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3435 case 0:
3436 if (fieldFromInstruction32(Insn, 4, 1))
3437 align = 4;
3438 index = fieldFromInstruction32(Insn, 5, 3);
3439 break;
3440 case 1:
3441 if (fieldFromInstruction32(Insn, 4, 1))
3442 align = 8;
3443 index = fieldFromInstruction32(Insn, 6, 2);
3444 if (fieldFromInstruction32(Insn, 5, 1))
3445 inc = 2;
3446 break;
3447 case 2:
3448 if (fieldFromInstruction32(Insn, 4, 2))
3449 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3450 index = fieldFromInstruction32(Insn, 7, 1);
3451 if (fieldFromInstruction32(Insn, 6, 1))
3452 inc = 2;
3453 break;
3454 }
3455
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3457 return MCDisassembler::Fail;
3458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3459 return MCDisassembler::Fail;
3460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3461 return MCDisassembler::Fail;
3462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3463 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3464
3465 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3467 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3468 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3470 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3471 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3472 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3473 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3475 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3476 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3477 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3478 }
3479
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3481 return MCDisassembler::Fail;
3482 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3483 return MCDisassembler::Fail;
3484 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3485 return MCDisassembler::Fail;
3486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3487 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3488 Inst.addOperand(MCOperand::CreateImm(index));
3489
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3490 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3491}
3492
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3493static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3494 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3495 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3496
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3497 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3498 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3499 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3500 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3501 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3502
3503 unsigned align = 0;
3504 unsigned index = 0;
3505 unsigned inc = 1;
3506 switch (size) {
3507 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3508 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3509 case 0:
3510 if (fieldFromInstruction32(Insn, 4, 1))
3511 align = 4;
3512 index = fieldFromInstruction32(Insn, 5, 3);
3513 break;
3514 case 1:
3515 if (fieldFromInstruction32(Insn, 4, 1))
3516 align = 8;
3517 index = fieldFromInstruction32(Insn, 6, 2);
3518 if (fieldFromInstruction32(Insn, 5, 1))
3519 inc = 2;
3520 break;
3521 case 2:
3522 if (fieldFromInstruction32(Insn, 4, 2))
3523 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3524 index = fieldFromInstruction32(Insn, 7, 1);
3525 if (fieldFromInstruction32(Insn, 6, 1))
3526 inc = 2;
3527 break;
3528 }
3529
3530 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3532 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3533 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3535 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3536 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3537 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3538 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3540 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3541 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3542 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3543 }
3544
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3546 return MCDisassembler::Fail;
3547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3548 return MCDisassembler::Fail;
3549 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3550 return MCDisassembler::Fail;
3551 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3552 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3553 Inst.addOperand(MCOperand::CreateImm(index));
3554
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3555 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3556}
3557
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3558static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3559 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3560 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3561 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3562 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3563 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3564 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3565 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3566
3567 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3568 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3569
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3570 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3571 return MCDisassembler::Fail;
3572 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3573 return MCDisassembler::Fail;
3574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3575 return MCDisassembler::Fail;
3576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3577 return MCDisassembler::Fail;
3578 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3579 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3580
3581 return S;
3582}
3583
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3584static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3585 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3586 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3587 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3588 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3589 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3590 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3591 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3592
3593 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3594 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3595
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3597 return MCDisassembler::Fail;
3598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3599 return MCDisassembler::Fail;
3600 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3601 return MCDisassembler::Fail;
3602 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3603 return MCDisassembler::Fail;
3604 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3605 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]3606
3607 return S;
3608}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]3609
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3610static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3611 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3612 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3613 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3614 // The InstPrinter needs to have the low bit of the predicate in
3615 // the mask operand to be able to print it properly.
3616 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3617
3618 if (pred == 0xF) {
3619 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3620 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]3621 }
3622
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3623 if ((mask & 0xF) == 0) {
3624 // Preserve the high bit of the mask, which is the low bit of
3625 // the predicate.
3626 mask &= 0x10;
3627 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3628 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3629 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3630
3631 Inst.addOperand(MCOperand::CreateImm(pred));
3632 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]3633 return S;
3634}