sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 25e5473 | 2012-08-05 15:36:51 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2012 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
florian | 33b0243 | 2012-08-25 21:48:04 +0000 | [diff] [blame] | 37 | #include "libvex_emnote.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 41 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 42 | #include "libvex_guest_ppc64.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 43 | #include "libvex_guest_s390x.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 44 | #include "libvex_guest_mips32.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 45 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 46 | #include "main_globals.h" |
| 47 | #include "main_util.h" |
| 48 | #include "host_generic_regs.h" |
| 49 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 50 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 51 | #include "host_x86_defs.h" |
| 52 | #include "host_amd64_defs.h" |
| 53 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 54 | #include "host_arm_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 55 | #include "host_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 56 | #include "host_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 57 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 58 | #include "guest_generic_bb_to_IR.h" |
| 59 | #include "guest_x86_defs.h" |
| 60 | #include "guest_amd64_defs.h" |
| 61 | #include "guest_arm_defs.h" |
| 62 | #include "guest_ppc_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 63 | #include "guest_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 64 | #include "guest_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 65 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 66 | #include "host_generic_simd128.h" |
| 67 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 68 | |
| 69 | /* This file contains the top level interface to the library. */ |
| 70 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 71 | /* --------- fwds ... --------- */ |
| 72 | |
| 73 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
| 74 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
| 75 | |
| 76 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 77 | /* --------- Initialise the library. --------- */ |
| 78 | |
| 79 | /* Exported to library client. */ |
| 80 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 81 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 82 | { |
| 83 | vcon->iropt_verbosity = 0; |
| 84 | vcon->iropt_level = 2; |
philippe | c8e2f98 | 2012-08-01 22:04:13 +0000 | [diff] [blame] | 85 | vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 86 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 87 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 88 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 89 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | |
| 93 | /* Exported to library client. */ |
| 94 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 95 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 96 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 97 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 98 | void (*failure_exit) ( void ), |
| 99 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 100 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 101 | /* debug paranoia level */ |
| 102 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 103 | /* Are we supporting valgrind checking? */ |
| 104 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 105 | /* Control ... */ |
| 106 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 107 | ) |
| 108 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 109 | /* First off, do enough minimal setup so that the following |
| 110 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 111 | vex_failure_exit = failure_exit; |
| 112 | vex_log_bytes = log_bytes; |
| 113 | |
| 114 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 115 | vassert(!vex_initdone); |
| 116 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 117 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 118 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 119 | |
| 120 | vassert(vcon->iropt_verbosity >= 0); |
| 121 | vassert(vcon->iropt_level >= 0); |
| 122 | vassert(vcon->iropt_level <= 2); |
| 123 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 124 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 125 | vassert(vcon->guest_max_insns >= 1); |
| 126 | vassert(vcon->guest_max_insns <= 100); |
| 127 | vassert(vcon->guest_chase_thresh >= 0); |
| 128 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 129 | vassert(vcon->guest_chase_cond == True |
| 130 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 131 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 132 | /* Check that Vex has been built with sizes of basic types as |
| 133 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 134 | a serious configuration error and should be corrected |
| 135 | immediately. If any of these assertions fail you can fully |
| 136 | expect Vex not to work properly, if at all. */ |
| 137 | |
| 138 | vassert(1 == sizeof(UChar)); |
| 139 | vassert(1 == sizeof(Char)); |
| 140 | vassert(2 == sizeof(UShort)); |
| 141 | vassert(2 == sizeof(Short)); |
| 142 | vassert(4 == sizeof(UInt)); |
| 143 | vassert(4 == sizeof(Int)); |
| 144 | vassert(8 == sizeof(ULong)); |
| 145 | vassert(8 == sizeof(Long)); |
| 146 | vassert(4 == sizeof(Float)); |
| 147 | vassert(8 == sizeof(Double)); |
| 148 | vassert(1 == sizeof(Bool)); |
| 149 | vassert(4 == sizeof(Addr32)); |
| 150 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 151 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 152 | vassert(16 == sizeof(V128)); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 153 | vassert(32 == sizeof(U256)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 154 | |
| 155 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 156 | vassert(sizeof(void*) == sizeof(int*)); |
| 157 | vassert(sizeof(void*) == sizeof(HWord)); |
| 158 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 159 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 160 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 161 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 162 | /* These take a lot of space, so make sure we don't have |
| 163 | any unnoticed size regressions. */ |
| 164 | if (VEX_HOST_WORDSIZE == 4) { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 165 | vassert(sizeof(IRExpr) == 16); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 166 | vassert(sizeof(IRStmt) == 20 /* x86 */ |
| 167 | || sizeof(IRStmt) == 24 /* arm */); |
| 168 | } else { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 169 | vassert(sizeof(IRExpr) == 32); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 170 | vassert(sizeof(IRStmt) == 32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 171 | } |
| 172 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 173 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 174 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 175 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 176 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 177 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 178 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | |
| 182 | /* --------- Make a translation. --------- */ |
| 183 | |
| 184 | /* Exported to library client. */ |
| 185 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 186 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 187 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 188 | /* This the bundle of functions we need to do the back-end stuff |
| 189 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 190 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 191 | HReg* available_real_regs; |
| 192 | Int n_available_real_regs; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 193 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 194 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 195 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 196 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 197 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 198 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
| 199 | void (*ppInstr) ( HInstr*, Bool ); |
| 200 | void (*ppReg) ( HReg ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 201 | HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo*, |
| 202 | Int, Int, Bool, Bool, Addr64 ); |
| 203 | Int (*emit) ( /*MB_MOD*/Bool*, |
| 204 | UChar*, Int, HInstr*, Bool, |
| 205 | void*, void*, void*, void* ); |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 206 | IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 207 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 208 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 209 | DisOneInstrFn disInstrFn; |
| 210 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 211 | VexGuestLayout* guest_layout; |
| 212 | Bool host_is_bigendian = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 213 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 214 | HInstrArray* vcode; |
| 215 | HInstrArray* rcode; |
| 216 | Int i, j, k, out_used, guest_sizeB; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 217 | Int offB_TISTART, offB_TILEN, offB_GUEST_IP, szB_GUEST_IP; |
| 218 | Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; |
| 219 | UChar insn_bytes[64]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 220 | IRType guest_word_type; |
| 221 | IRType host_word_type; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 222 | Bool mode64, chainingAllowed; |
| 223 | Addr64 max_ga; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 224 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 225 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 226 | available_real_regs = NULL; |
| 227 | n_available_real_regs = 0; |
| 228 | isMove = NULL; |
| 229 | getRegUsage = NULL; |
| 230 | mapRegs = NULL; |
| 231 | genSpill = NULL; |
| 232 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 233 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 234 | ppInstr = NULL; |
| 235 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 236 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 237 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 238 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 239 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 240 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 241 | guest_word_type = Ity_INVALID; |
| 242 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 243 | offB_TISTART = 0; |
| 244 | offB_TILEN = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 245 | offB_GUEST_IP = 0; |
| 246 | szB_GUEST_IP = 0; |
| 247 | offB_HOST_EvC_COUNTER = 0; |
| 248 | offB_HOST_EvC_FAILADDR = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 249 | mode64 = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 250 | chainingAllowed = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 251 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 252 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 253 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 254 | vassert(vex_initdone); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 255 | vassert(vta->needs_self_check != NULL); |
| 256 | vassert(vta->disp_cp_xassisted != NULL); |
| 257 | /* Both the chainers and the indir are either NULL or non-NULL. */ |
| 258 | if (vta->disp_cp_chain_me_to_slowEP != NULL) { |
| 259 | vassert(vta->disp_cp_chain_me_to_fastEP != NULL); |
| 260 | vassert(vta->disp_cp_xindir != NULL); |
| 261 | chainingAllowed = True; |
| 262 | } else { |
| 263 | vassert(vta->disp_cp_chain_me_to_fastEP == NULL); |
| 264 | vassert(vta->disp_cp_xindir == NULL); |
| 265 | } |
florian | 2eeeb9b | 2011-09-23 18:03:21 +0000 | [diff] [blame] | 266 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 267 | vexSetAllocModeTEMP_and_clear(); |
| 268 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 269 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 270 | /* First off, check that the guest and host insn sets |
| 271 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 272 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 273 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 274 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 275 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 276 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 277 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 278 | &available_real_regs ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 279 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 280 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 281 | getRegUsage_X86Instr; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 282 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 283 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 284 | genSpill_X86; |
| 285 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 286 | genReload_X86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 287 | directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; |
| 288 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
| 289 | ppReg = (void(*)(HReg)) ppHRegX86; |
| 290 | iselSB = iselSB_X86; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 291 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 292 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 293 | emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 294 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 295 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 296 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 297 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 298 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 299 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 300 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 301 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 302 | &available_real_regs ); |
| 303 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 304 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 305 | getRegUsage_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 306 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 307 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 308 | genSpill_AMD64; |
| 309 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 310 | genReload_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 311 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 312 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 313 | iselSB = iselSB_AMD64; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 314 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 315 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 316 | emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 317 | host_is_bigendian = False; |
| 318 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 319 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 320 | break; |
| 321 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 322 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 323 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 324 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 325 | &available_real_regs, mode64 ); |
| 326 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 327 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 328 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 329 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 330 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 331 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 332 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 333 | iselSB = iselSB_PPC; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 334 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 335 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 336 | emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 337 | host_is_bigendian = True; |
| 338 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 339 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 340 | break; |
| 341 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 342 | case VexArchPPC64: |
| 343 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 344 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 345 | &available_real_regs, mode64 ); |
| 346 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 347 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 348 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 349 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 350 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 351 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 352 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 353 | iselSB = iselSB_PPC; |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 354 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 355 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 356 | emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 357 | host_is_bigendian = True; |
| 358 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 359 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 360 | break; |
| 361 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 362 | case VexArchS390X: |
| 363 | mode64 = True; |
| 364 | getAllocableRegs_S390 ( &n_available_real_regs, |
| 365 | &available_real_regs, mode64 ); |
| 366 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_S390Instr; |
| 367 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_S390Instr; |
| 368 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_S390Instr; |
| 369 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_S390; |
| 370 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_S390; |
| 371 | ppInstr = (void(*)(HInstr*, Bool)) ppS390Instr; |
| 372 | ppReg = (void(*)(HReg)) ppHRegS390; |
| 373 | iselSB = iselSB_S390; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 374 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 375 | void*,void*,void*,void*)) emit_S390Instr; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 376 | host_is_bigendian = True; |
| 377 | host_word_type = Ity_I64; |
| 378 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 379 | break; |
| 380 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 381 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 382 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 383 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 384 | &available_real_regs ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 385 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; |
| 386 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; |
| 387 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; |
| 388 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; |
| 389 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; |
| 390 | ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; |
| 391 | ppReg = (void(*)(HReg)) ppHRegARM; |
| 392 | iselSB = iselSB_ARM; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 393 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 394 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 395 | emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 396 | host_is_bigendian = False; |
| 397 | host_word_type = Ity_I32; |
| 398 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 399 | break; |
| 400 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 401 | case VexArchMIPS32: |
| 402 | mode64 = False; |
| 403 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 404 | &available_real_regs, mode64 ); |
| 405 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_MIPSInstr; |
| 406 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_MIPSInstr; |
| 407 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_MIPSInstr; |
| 408 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_MIPS; |
| 409 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_MIPS; |
| 410 | ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr; |
| 411 | ppReg = (void(*)(HReg)) ppHRegMIPS; |
| 412 | iselSB = iselSB_MIPS; |
| 413 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, |
| 414 | void*,void*,void*,void*)) |
| 415 | emit_MIPSInstr; |
| 416 | #if defined(VKI_LITTLE_ENDIAN) |
| 417 | host_is_bigendian = False; |
| 418 | #elif defined(VKI_BIG_ENDIAN) |
| 419 | host_is_bigendian = True; |
| 420 | #endif |
| 421 | host_word_type = Ity_I32; |
| 422 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps)); |
| 423 | break; |
| 424 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 425 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 426 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 427 | } |
| 428 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 429 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 430 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 431 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 432 | case VexArchX86: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 433 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
| 434 | disInstrFn = disInstr_X86; |
| 435 | specHelper = guest_x86_spechelper; |
| 436 | guest_sizeB = sizeof(VexGuestX86State); |
| 437 | guest_word_type = Ity_I32; |
| 438 | guest_layout = &x86guest_layout; |
| 439 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 440 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
| 441 | offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); |
| 442 | szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); |
| 443 | offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); |
| 444 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 445 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 446 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 447 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); |
| 448 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
| 449 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 450 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 451 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 452 | case VexArchAMD64: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 453 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 454 | disInstrFn = disInstr_AMD64; |
| 455 | specHelper = guest_amd64_spechelper; |
| 456 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 457 | guest_word_type = Ity_I64; |
| 458 | guest_layout = &amd64guest_layout; |
| 459 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 460 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
| 461 | offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); |
| 462 | szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); |
| 463 | offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); |
| 464 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 465 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 466 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 467 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 468 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
| 469 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 470 | break; |
| 471 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 472 | case VexArchPPC32: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 473 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 474 | disInstrFn = disInstr_PPC; |
| 475 | specHelper = guest_ppc32_spechelper; |
| 476 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 477 | guest_word_type = Ity_I32; |
| 478 | guest_layout = &ppc32Guest_layout; |
| 479 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 480 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
| 481 | offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); |
| 482 | szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); |
| 483 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); |
| 484 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 485 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 486 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 487 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 488 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
| 489 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 490 | break; |
| 491 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 492 | case VexArchPPC64: |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 493 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
| 494 | disInstrFn = disInstr_PPC; |
| 495 | specHelper = guest_ppc64_spechelper; |
| 496 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 497 | guest_word_type = Ity_I64; |
| 498 | guest_layout = &ppc64Guest_layout; |
| 499 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 500 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
| 501 | offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA); |
| 502 | szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA ); |
| 503 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); |
| 504 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 505 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 506 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 507 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
| 508 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 509 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 510 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 511 | break; |
| 512 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 513 | case VexArchS390X: |
| 514 | preciseMemExnsFn = guest_s390x_state_requires_precise_mem_exns; |
| 515 | disInstrFn = disInstr_S390; |
| 516 | specHelper = guest_s390x_spechelper; |
| 517 | guest_sizeB = sizeof(VexGuestS390XState); |
| 518 | guest_word_type = Ity_I64; |
| 519 | guest_layout = &s390xGuest_layout; |
| 520 | offB_TISTART = offsetof(VexGuestS390XState,guest_TISTART); |
| 521 | offB_TILEN = offsetof(VexGuestS390XState,guest_TILEN); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 522 | offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); |
| 523 | szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); |
| 524 | offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); |
| 525 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 526 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); |
| 527 | vassert(0 == sizeof(VexGuestS390XState) % 16); |
| 528 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8); |
| 529 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_TILEN ) == 8); |
| 530 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); |
| 531 | break; |
| 532 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 533 | case VexArchARM: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 534 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 535 | disInstrFn = disInstr_ARM; |
| 536 | specHelper = guest_arm_spechelper; |
| 537 | guest_sizeB = sizeof(VexGuestARMState); |
| 538 | guest_word_type = Ity_I32; |
| 539 | guest_layout = &armGuest_layout; |
| 540 | offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); |
| 541 | offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); |
| 542 | offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); |
| 543 | szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); |
| 544 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); |
| 545 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 546 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
| 547 | vassert(0 == sizeof(VexGuestARMState) % 16); |
| 548 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); |
| 549 | vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); |
| 550 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 551 | break; |
| 552 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 553 | case VexArchMIPS32: |
| 554 | preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; |
| 555 | disInstrFn = disInstr_MIPS; |
| 556 | specHelper = guest_mips32_spechelper; |
| 557 | guest_sizeB = sizeof(VexGuestMIPS32State); |
| 558 | guest_word_type = Ity_I32; |
| 559 | guest_layout = &mips32Guest_layout; |
| 560 | offB_TISTART = offsetof(VexGuestMIPS32State,guest_TISTART); |
| 561 | offB_TILEN = offsetof(VexGuestMIPS32State,guest_TILEN); |
| 562 | offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC); |
| 563 | szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC ); |
| 564 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); |
| 565 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); |
| 566 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps)); |
| 567 | vassert(0 == sizeof(VexGuestMIPS32State) % 16); |
| 568 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4); |
| 569 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4); |
| 570 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); |
| 571 | break; |
| 572 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 573 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 574 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 575 | } |
| 576 | |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 577 | /* Set up result struct. */ |
| 578 | VexTranslateResult res; |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 579 | res.status = VexTransOK; |
| 580 | res.n_sc_extents = 0; |
| 581 | res.offs_profInc = -1; |
| 582 | res.n_guest_instrs = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 583 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 584 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 585 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 586 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 587 | we are simulating one flavour of an architecture a different |
| 588 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 589 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 590 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 591 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 592 | vexAllocSanityCheck(); |
| 593 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 594 | if (vex_traceflags & VEX_TRACE_FE) |
| 595 | vex_printf("\n------------------------" |
| 596 | " Front end " |
| 597 | "------------------------\n\n"); |
| 598 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 599 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 600 | &res.n_sc_extents, |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 601 | &res.n_guest_instrs, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 602 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 603 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 604 | vta->guest_bytes, |
| 605 | vta->guest_bytes_addr, |
| 606 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 607 | host_is_bigendian, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 608 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 609 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 610 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 611 | guest_word_type, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 612 | vta->needs_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 613 | vta->preamble_function, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 614 | offB_TISTART, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 615 | offB_TILEN, |
| 616 | offB_GUEST_IP, |
| 617 | szB_GUEST_IP ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 618 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 619 | vexAllocSanityCheck(); |
| 620 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 621 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 622 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 623 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 624 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 625 | res.status = VexTransAccessFail; return res; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 626 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 627 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 628 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 629 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 630 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 631 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 632 | } |
| 633 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 634 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 635 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 636 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 637 | vex_printf("can't show code due to extents > 1\n"); |
| 638 | } else { |
| 639 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 640 | UChar* p = (UChar*)vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 641 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 642 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 643 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 644 | guest_bytes_read ); |
| 645 | for (i = 0; i < guest_bytes_read; i++) { |
| 646 | UInt b = (UInt)p[i]; |
| 647 | vex_printf(" %02x", b ); |
| 648 | sum = (sum << 1) ^ b; |
| 649 | } |
| 650 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 651 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 655 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 656 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 657 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 658 | vexAllocSanityCheck(); |
| 659 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 660 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 661 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 662 | vta->guest_bytes_addr, |
| 663 | vta->arch_guest ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 664 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 665 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 666 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 667 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 668 | vex_printf("\n------------------------" |
| 669 | " After pre-instr IR optimisation " |
| 670 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 671 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 672 | vex_printf("\n"); |
| 673 | } |
| 674 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 675 | vexAllocSanityCheck(); |
| 676 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 677 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 678 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 679 | irsb = vta->instrument1(vta->callback_opaque, |
| 680 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 681 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame^] | 682 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 683 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 684 | vexAllocSanityCheck(); |
| 685 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 686 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 687 | irsb = vta->instrument2(vta->callback_opaque, |
| 688 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 689 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame^] | 690 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 691 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 692 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 693 | if (vex_traceflags & VEX_TRACE_INST) { |
| 694 | vex_printf("\n------------------------" |
| 695 | " After instrumentation " |
| 696 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 697 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 698 | vex_printf("\n"); |
| 699 | } |
| 700 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 701 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 702 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 703 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 704 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 705 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 706 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 707 | do_deadcode_BB( irsb ); |
| 708 | irsb = cprop_BB( irsb ); |
| 709 | do_deadcode_BB( irsb ); |
| 710 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 711 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 712 | } |
| 713 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 714 | vexAllocSanityCheck(); |
| 715 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 716 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 717 | vex_printf("\n------------------------" |
| 718 | " After post-instr IR optimisation " |
| 719 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 720 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 721 | vex_printf("\n"); |
| 722 | } |
| 723 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 724 | /* Turn it into virtual-registerised code. Build trees -- this |
| 725 | also throws away any dead bindings. */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 726 | max_ga = ado_treebuild_BB( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 727 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 728 | if (vta->finaltidy) { |
| 729 | irsb = vta->finaltidy(irsb); |
| 730 | } |
| 731 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 732 | vexAllocSanityCheck(); |
| 733 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 734 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 735 | vex_printf("\n------------------------" |
| 736 | " After tree-building " |
| 737 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 738 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 739 | vex_printf("\n"); |
| 740 | } |
| 741 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 742 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 743 | if (0) { |
| 744 | *(vta->host_bytes_used) = 0; |
| 745 | res.status = VexTransOK; return res; |
| 746 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 747 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 748 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 749 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 750 | vex_printf("\n------------------------" |
| 751 | " Instruction selection " |
| 752 | "------------------------\n"); |
| 753 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 754 | /* No guest has its IP field at offset zero. If this fails it |
| 755 | means some transformation pass somewhere failed to update/copy |
| 756 | irsb->offsIP properly. */ |
| 757 | vassert(irsb->offsIP >= 16); |
| 758 | |
| 759 | vcode = iselSB ( irsb, vta->arch_host, |
| 760 | &vta->archinfo_host, |
| 761 | &vta->abiinfo_both, |
| 762 | offB_HOST_EvC_COUNTER, |
| 763 | offB_HOST_EvC_FAILADDR, |
| 764 | chainingAllowed, |
| 765 | vta->addProfInc, |
| 766 | max_ga ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 767 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 768 | vexAllocSanityCheck(); |
| 769 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 770 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 771 | vex_printf("\n"); |
| 772 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 773 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 774 | for (i = 0; i < vcode->arr_used; i++) { |
| 775 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 776 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 777 | vex_printf("\n"); |
| 778 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 779 | vex_printf("\n"); |
| 780 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 781 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 782 | /* Register allocate. */ |
| 783 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 784 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 785 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 786 | genSpill, genReload, directReload, |
| 787 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 788 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 789 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 790 | vexAllocSanityCheck(); |
| 791 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 792 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 793 | vex_printf("\n------------------------" |
| 794 | " Register-allocated code " |
| 795 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 796 | for (i = 0; i < rcode->arr_used; i++) { |
| 797 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 798 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 799 | vex_printf("\n"); |
| 800 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 801 | vex_printf("\n"); |
| 802 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 803 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 804 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 805 | if (0) { |
| 806 | *(vta->host_bytes_used) = 0; |
| 807 | res.status = VexTransOK; return res; |
| 808 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 809 | /* end HACK */ |
| 810 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 811 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 812 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 813 | vex_printf("\n------------------------" |
| 814 | " Assembly " |
| 815 | "------------------------\n\n"); |
| 816 | } |
| 817 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 818 | out_used = 0; /* tracks along the host_bytes array */ |
| 819 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 820 | HInstr* hi = rcode->arr[i]; |
| 821 | Bool hi_isProfInc = False; |
| 822 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
| 823 | ppInstr(hi, mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 824 | vex_printf("\n"); |
| 825 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 826 | j = emit( &hi_isProfInc, |
| 827 | insn_bytes, sizeof insn_bytes, hi, mode64, |
| 828 | vta->disp_cp_chain_me_to_slowEP, |
| 829 | vta->disp_cp_chain_me_to_fastEP, |
| 830 | vta->disp_cp_xindir, |
| 831 | vta->disp_cp_xassisted ); |
| 832 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 833 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 834 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 835 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 836 | else |
| 837 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 838 | vex_printf("\n\n"); |
| 839 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 840 | if (UNLIKELY(out_used + j > vta->host_bytes_size)) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 841 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 842 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 843 | res.status = VexTransOutputFull; |
| 844 | return res; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 845 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 846 | if (UNLIKELY(hi_isProfInc)) { |
| 847 | vassert(vta->addProfInc); /* else where did it come from? */ |
| 848 | vassert(res.offs_profInc == -1); /* there can be only one (tm) */ |
| 849 | vassert(out_used >= 0); |
| 850 | res.offs_profInc = out_used; |
| 851 | } |
| 852 | { UChar* dst = &vta->host_bytes[out_used]; |
| 853 | for (k = 0; k < j; k++) { |
| 854 | dst[k] = insn_bytes[k]; |
| 855 | } |
| 856 | out_used += j; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 857 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 858 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 859 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 860 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 861 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 862 | vexAllocSanityCheck(); |
| 863 | |
| 864 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 865 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 866 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 867 | res.status = VexTransOK; |
| 868 | return res; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 869 | } |
| 870 | |
| 871 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 872 | /* --------- Chain/Unchain XDirects. --------- */ |
| 873 | |
| 874 | VexInvalRange LibVEX_Chain ( VexArch arch_host, |
| 875 | void* place_to_chain, |
| 876 | void* disp_cp_chain_me_EXPECTED, |
| 877 | void* place_to_jump_to ) |
| 878 | { |
| 879 | VexInvalRange (*chainXDirect)(void*, void*, void*) = NULL; |
| 880 | switch (arch_host) { |
| 881 | case VexArchX86: |
| 882 | chainXDirect = chainXDirect_X86; break; |
| 883 | case VexArchAMD64: |
| 884 | chainXDirect = chainXDirect_AMD64; break; |
| 885 | case VexArchARM: |
| 886 | chainXDirect = chainXDirect_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 887 | case VexArchS390X: |
| 888 | chainXDirect = chainXDirect_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 889 | case VexArchPPC32: |
| 890 | return chainXDirect_PPC(place_to_chain, |
| 891 | disp_cp_chain_me_EXPECTED, |
| 892 | place_to_jump_to, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 893 | case VexArchPPC64: |
| 894 | return chainXDirect_PPC(place_to_chain, |
| 895 | disp_cp_chain_me_EXPECTED, |
| 896 | place_to_jump_to, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 897 | case VexArchMIPS32: |
| 898 | return chainXDirect_MIPS(place_to_chain, |
| 899 | disp_cp_chain_me_EXPECTED, |
| 900 | place_to_jump_to, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 901 | default: |
| 902 | vassert(0); |
| 903 | } |
| 904 | vassert(chainXDirect); |
| 905 | VexInvalRange vir |
| 906 | = chainXDirect(place_to_chain, disp_cp_chain_me_EXPECTED, |
| 907 | place_to_jump_to); |
| 908 | return vir; |
| 909 | } |
| 910 | |
| 911 | VexInvalRange LibVEX_UnChain ( VexArch arch_host, |
| 912 | void* place_to_unchain, |
| 913 | void* place_to_jump_to_EXPECTED, |
| 914 | void* disp_cp_chain_me ) |
| 915 | { |
| 916 | VexInvalRange (*unchainXDirect)(void*, void*, void*) = NULL; |
| 917 | switch (arch_host) { |
| 918 | case VexArchX86: |
| 919 | unchainXDirect = unchainXDirect_X86; break; |
| 920 | case VexArchAMD64: |
| 921 | unchainXDirect = unchainXDirect_AMD64; break; |
| 922 | case VexArchARM: |
| 923 | unchainXDirect = unchainXDirect_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 924 | case VexArchS390X: |
| 925 | unchainXDirect = unchainXDirect_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 926 | case VexArchPPC32: |
| 927 | return unchainXDirect_PPC(place_to_unchain, |
| 928 | place_to_jump_to_EXPECTED, |
| 929 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 930 | case VexArchPPC64: |
| 931 | return unchainXDirect_PPC(place_to_unchain, |
| 932 | place_to_jump_to_EXPECTED, |
| 933 | disp_cp_chain_me, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 934 | case VexArchMIPS32: |
| 935 | return unchainXDirect_MIPS(place_to_unchain, |
| 936 | place_to_jump_to_EXPECTED, |
| 937 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 938 | default: |
| 939 | vassert(0); |
| 940 | } |
| 941 | vassert(unchainXDirect); |
| 942 | VexInvalRange vir |
| 943 | = unchainXDirect(place_to_unchain, place_to_jump_to_EXPECTED, |
| 944 | disp_cp_chain_me); |
| 945 | return vir; |
| 946 | } |
| 947 | |
| 948 | Int LibVEX_evCheckSzB ( VexArch arch_host ) |
| 949 | { |
| 950 | static Int cached = 0; /* DO NOT MAKE NON-STATIC */ |
| 951 | if (UNLIKELY(cached == 0)) { |
| 952 | switch (arch_host) { |
| 953 | case VexArchX86: |
| 954 | cached = evCheckSzB_X86(); break; |
| 955 | case VexArchAMD64: |
| 956 | cached = evCheckSzB_AMD64(); break; |
| 957 | case VexArchARM: |
| 958 | cached = evCheckSzB_ARM(); break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 959 | case VexArchS390X: |
| 960 | cached = evCheckSzB_S390(); break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 961 | case VexArchPPC32: |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 962 | case VexArchPPC64: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 963 | cached = evCheckSzB_PPC(); break; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 964 | case VexArchMIPS32: |
| 965 | cached = evCheckSzB_MIPS(); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 966 | default: |
| 967 | vassert(0); |
| 968 | } |
| 969 | } |
| 970 | return cached; |
| 971 | } |
| 972 | |
| 973 | VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, |
| 974 | void* place_to_patch, |
| 975 | ULong* location_of_counter ) |
| 976 | { |
| 977 | VexInvalRange (*patchProfInc)(void*,ULong*) = NULL; |
| 978 | switch (arch_host) { |
| 979 | case VexArchX86: |
| 980 | patchProfInc = patchProfInc_X86; break; |
| 981 | case VexArchAMD64: |
| 982 | patchProfInc = patchProfInc_AMD64; break; |
| 983 | case VexArchARM: |
| 984 | patchProfInc = patchProfInc_ARM; break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 985 | case VexArchS390X: |
| 986 | patchProfInc = patchProfInc_S390; break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 987 | case VexArchPPC32: |
| 988 | return patchProfInc_PPC(place_to_patch, |
| 989 | location_of_counter, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 990 | case VexArchPPC64: |
| 991 | return patchProfInc_PPC(place_to_patch, |
| 992 | location_of_counter, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 993 | case VexArchMIPS32: |
| 994 | return patchProfInc_MIPS(place_to_patch, |
| 995 | location_of_counter, False/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 996 | default: |
| 997 | vassert(0); |
| 998 | } |
| 999 | vassert(patchProfInc); |
| 1000 | VexInvalRange vir |
| 1001 | = patchProfInc(place_to_patch, location_of_counter); |
| 1002 | return vir; |
| 1003 | } |
| 1004 | |
| 1005 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1006 | /* --------- Emulation warnings. --------- */ |
| 1007 | |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1008 | HChar* LibVEX_EmNote_string ( VexEmNote ew ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1009 | { |
| 1010 | switch (ew) { |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1011 | case EmNote_NONE: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1012 | return "none"; |
| 1013 | case EmWarn_X86_x87exns: |
| 1014 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1015 | case EmWarn_X86_x87precision: |
| 1016 | return "Selection of non-80-bit x87 FP precision"; |
| 1017 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 1018 | return "Unmasking SSE FP exceptions"; |
| 1019 | case EmWarn_X86_fz: |
| 1020 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 1021 | case EmWarn_X86_daz: |
| 1022 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 1023 | case EmWarn_X86_acFlag: |
| 1024 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1025 | case EmWarn_PPCexns: |
| 1026 | return "Unmasking PPC32/64 FP exceptions"; |
| 1027 | case EmWarn_PPC64_redir_overflow: |
| 1028 | return "PPC64 function redirection stack overflow"; |
| 1029 | case EmWarn_PPC64_redir_underflow: |
| 1030 | return "PPC64 function redirection stack underflow"; |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1031 | case EmWarn_S390X_fpext_rounding: |
| 1032 | return "The specified rounding mode cannot be supported. That\n" |
| 1033 | " feature requires the floating point extension facility.\n" |
| 1034 | " which is not available on this host. Continuing using\n" |
| 1035 | " the rounding mode from FPC. Results may differ!"; |
florian | f0fa1be | 2012-09-18 20:24:38 +0000 | [diff] [blame] | 1036 | case EmWarn_S390X_invalid_rounding: |
| 1037 | return "The specified rounding mode is invalid.\n" |
| 1038 | " Continuing using 'round to nearest'. Results may differ!"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1039 | case EmFail_S390X_stfle: |
florian | 4e0083e | 2012-08-26 03:41:56 +0000 | [diff] [blame] | 1040 | return "Instruction stfle is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1041 | case EmFail_S390X_stckf: |
florian | c5c669b | 2012-08-26 14:32:28 +0000 | [diff] [blame] | 1042 | return "Instruction stckf is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1043 | case EmFail_S390X_ecag: |
florian | 8c88cb6 | 2012-08-26 18:58:13 +0000 | [diff] [blame] | 1044 | return "Instruction ecag is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1045 | case EmFail_S390X_fpext: |
| 1046 | return "Encountered an instruction that requires the floating " |
| 1047 | "point extension facility.\n" |
| 1048 | " That facility is not available on this host"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1049 | default: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1050 | vpanic("LibVEX_EmNote_string: unknown warning"); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1051 | } |
| 1052 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1053 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1054 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1055 | |
| 1056 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 1057 | { |
| 1058 | switch (arch) { |
| 1059 | case VexArch_INVALID: return "INVALID"; |
| 1060 | case VexArchX86: return "X86"; |
| 1061 | case VexArchAMD64: return "AMD64"; |
| 1062 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 1063 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1064 | case VexArchPPC64: return "PPC64"; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1065 | case VexArchS390X: return "S390X"; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1066 | case VexArchMIPS32: return "MIPS32"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1067 | default: return "VexArch???"; |
| 1068 | } |
| 1069 | } |
| 1070 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1071 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1072 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1073 | HChar* str = show_hwcaps(arch,hwcaps); |
| 1074 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1075 | } |
| 1076 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1077 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1078 | /* Write default settings info *vai. */ |
| 1079 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 1080 | { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1081 | vai->hwcaps = 0; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1082 | vai->ppc_cache_line_szB = 0; |
sewardj | e971c6a | 2010-09-03 15:49:57 +0000 | [diff] [blame] | 1083 | vai->ppc_dcbz_szB = 0; |
| 1084 | vai->ppc_dcbzl_szB = 0; |
| 1085 | |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1086 | vai->hwcache_info.num_levels = 0; |
| 1087 | vai->hwcache_info.num_caches = 0; |
| 1088 | vai->hwcache_info.caches = NULL; |
| 1089 | vai->hwcache_info.icaches_maintain_coherence = True; // whatever |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1090 | } |
| 1091 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1092 | /* Write default settings info *vbi. */ |
| 1093 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1094 | { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1095 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 1096 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 1097 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1098 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 1099 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
| 1100 | vbi->guest_ppc_sc_continues_at_LR = False; |
| 1101 | vbi->host_ppc_calls_use_fndescrs = False; |
| 1102 | vbi->host_ppc32_regalign_int64_args = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1103 | } |
| 1104 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1105 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1106 | /* Return a string showing the hwcaps in a nice way. The string will |
| 1107 | be NULL for invalid combinations of flags, so these functions also |
| 1108 | serve as a way to validate hwcaps values. */ |
| 1109 | |
| 1110 | static HChar* show_hwcaps_x86 ( UInt hwcaps ) |
| 1111 | { |
| 1112 | /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */ |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1113 | switch (hwcaps) { |
| 1114 | case 0: |
| 1115 | return "x86-sse0"; |
| 1116 | case VEX_HWCAPS_X86_SSE1: |
| 1117 | return "x86-sse1"; |
| 1118 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2: |
| 1119 | return "x86-sse1-sse2"; |
| 1120 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1121 | | VEX_HWCAPS_X86_LZCNT: |
| 1122 | return "x86-sse1-sse2-lzcnt"; |
| 1123 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1124 | | VEX_HWCAPS_X86_SSE3: |
| 1125 | return "x86-sse1-sse2-sse3"; |
| 1126 | case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
| 1127 | | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT: |
| 1128 | return "x86-sse1-sse2-sse3-lzcnt"; |
| 1129 | default: |
| 1130 | return NULL; |
| 1131 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1132 | } |
| 1133 | |
| 1134 | static HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
| 1135 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1136 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 1137 | don't expect to come across anything which can do SSE3 but can't |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1138 | do CX16. Still, we can handle that case. LZCNT is similarly |
sewardj | f350a42 | 2012-04-26 14:16:52 +0000 | [diff] [blame] | 1139 | orthogonal. AVX is technically orthogonal, but just add the |
| 1140 | cases we actually come across. (This scheme for printing is |
| 1141 | very stupid. We should add strings independently based on |
| 1142 | feature bits, but then it would be hard to return a string that |
| 1143 | didn't need deallocating by the caller.) */ |
sewardj | c4530ae | 2012-05-21 10:18:49 +0000 | [diff] [blame] | 1144 | /* FIXME: show_hwcaps_s390x is a much better way to do this. */ |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1145 | switch (hwcaps) { |
| 1146 | case 0: |
| 1147 | return "amd64-sse2"; |
| 1148 | case VEX_HWCAPS_AMD64_SSE3: |
| 1149 | return "amd64-sse3"; |
| 1150 | case VEX_HWCAPS_AMD64_CX16: |
| 1151 | return "amd64-sse2-cx16"; |
| 1152 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16: |
| 1153 | return "amd64-sse3-cx16"; |
| 1154 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_LZCNT: |
| 1155 | return "amd64-sse3-lzcnt"; |
| 1156 | case VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT: |
| 1157 | return "amd64-sse2-cx16-lzcnt"; |
| 1158 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16 |
| 1159 | | VEX_HWCAPS_AMD64_LZCNT: |
| 1160 | return "amd64-sse3-cx16-lzcnt"; |
sewardj | f350a42 | 2012-04-26 14:16:52 +0000 | [diff] [blame] | 1161 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16 |
| 1162 | | VEX_HWCAPS_AMD64_AVX: |
| 1163 | return "amd64-sse3-cx16-avx"; |
sewardj | b5e17b9 | 2012-05-21 16:16:13 +0000 | [diff] [blame] | 1164 | case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16 |
| 1165 | | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX: |
| 1166 | return "amd64-sse3-cx16-lzcnt-avx"; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1167 | default: |
| 1168 | return NULL; |
| 1169 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1170 | } |
| 1171 | |
| 1172 | static HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
| 1173 | { |
| 1174 | /* Monotonic with complications. Basically V > F > baseline, |
| 1175 | but once you have F then you can have FX or GX too. */ |
| 1176 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 1177 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 1178 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 1179 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1180 | const UInt VX = VEX_HWCAPS_PPC32_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1181 | const UInt DFP = VEX_HWCAPS_PPC32_DFP; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1182 | UInt c = hwcaps; |
| 1183 | if (c == 0) return "ppc32-int"; |
| 1184 | if (c == F) return "ppc32-int-flt"; |
| 1185 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 1186 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 1187 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 1188 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 1189 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 1190 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 1191 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1192 | if (c == (F|V|FX|GX|DFP)) return "ppc32-int-flt-vmx-FX-GX-DFP"; |
| 1193 | if (c == (F|V|FX|GX|VX|DFP)) return "ppc32-int-flt-vmx-FX-GX-VX-DFP"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1194 | return NULL; |
| 1195 | } |
| 1196 | |
| 1197 | static HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
| 1198 | { |
| 1199 | /* Monotonic with complications. Basically V > baseline(==F), |
| 1200 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1201 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 1202 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 1203 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1204 | const UInt VX = VEX_HWCAPS_PPC64_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1205 | const UInt DFP = VEX_HWCAPS_PPC64_DFP; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1206 | UInt c = hwcaps; |
| 1207 | if (c == 0) return "ppc64-int-flt"; |
| 1208 | if (c == FX) return "ppc64-int-flt-FX"; |
| 1209 | if (c == GX) return "ppc64-int-flt-GX"; |
| 1210 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 1211 | if (c == V) return "ppc64-int-flt-vmx"; |
| 1212 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 1213 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 1214 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1215 | if (c == (V|FX|GX|DFP)) return "ppc64-int-flt-vmx-FX-GX-DFP"; |
| 1216 | if (c == (V|FX|GX|VX|DFP)) return "ppc64-int-flt-vmx-FX-GX-VX-DFP"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1217 | return NULL; |
| 1218 | } |
| 1219 | |
| 1220 | static HChar* show_hwcaps_arm ( UInt hwcaps ) |
| 1221 | { |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 1222 | Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); |
| 1223 | Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP | |
| 1224 | VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0); |
| 1225 | switch (VEX_ARM_ARCHLEVEL(hwcaps)) { |
| 1226 | case 5: |
| 1227 | if (N) |
| 1228 | return NULL; |
| 1229 | if (vfp) |
| 1230 | return "ARMv5-vfp"; |
| 1231 | else |
| 1232 | return "ARMv5"; |
| 1233 | return NULL; |
| 1234 | case 6: |
| 1235 | if (N) |
| 1236 | return NULL; |
| 1237 | if (vfp) |
| 1238 | return "ARMv6-vfp"; |
| 1239 | else |
| 1240 | return "ARMv6"; |
| 1241 | return NULL; |
| 1242 | case 7: |
| 1243 | if (vfp) { |
| 1244 | if (N) |
| 1245 | return "ARMv7-vfp-neon"; |
| 1246 | else |
| 1247 | return "ARMv7-vfp"; |
| 1248 | } else { |
| 1249 | if (N) |
| 1250 | return "ARMv7-neon"; |
| 1251 | else |
| 1252 | return "ARMv7"; |
| 1253 | } |
| 1254 | default: |
| 1255 | return NULL; |
| 1256 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1257 | return NULL; |
| 1258 | } |
| 1259 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1260 | static HChar* show_hwcaps_s390x ( UInt hwcaps ) |
| 1261 | { |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1262 | static const HChar prefix[] = "s390x"; |
| 1263 | static const HChar facilities[][6] = { |
| 1264 | { "ldisp" }, |
| 1265 | { "eimm" }, |
| 1266 | { "gie" }, |
| 1267 | { "dfp" }, |
| 1268 | { "fgx" }, |
florian | 90ece04 | 2012-04-21 15:41:51 +0000 | [diff] [blame] | 1269 | { "stfle" }, |
| 1270 | { "etf2" }, |
florian | 79bee4b | 2012-05-03 01:30:48 +0000 | [diff] [blame] | 1271 | { "etf3" }, |
florian | a4c3669 | 2012-08-26 04:22:33 +0000 | [diff] [blame] | 1272 | { "stckf" }, |
florian | 60b665b | 2012-08-30 20:28:00 +0000 | [diff] [blame] | 1273 | { "fpext" }, |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1274 | }; |
| 1275 | static HChar buf[sizeof facilities + sizeof prefix + 1]; |
| 1276 | static HChar *p; |
| 1277 | |
| 1278 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1279 | |
sewardj | 652b56a | 2011-04-13 15:38:17 +0000 | [diff] [blame] | 1280 | hwcaps = VEX_HWCAPS_S390X(hwcaps); |
| 1281 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1282 | p = buf + vex_sprintf(buf, "%s", prefix); |
| 1283 | if (hwcaps & VEX_HWCAPS_S390X_LDISP) |
| 1284 | p = p + vex_sprintf(p, "-%s", facilities[0]); |
| 1285 | if (hwcaps & VEX_HWCAPS_S390X_EIMM) |
| 1286 | p = p + vex_sprintf(p, "-%s", facilities[1]); |
| 1287 | if (hwcaps & VEX_HWCAPS_S390X_GIE) |
| 1288 | p = p + vex_sprintf(p, "-%s", facilities[2]); |
| 1289 | if (hwcaps & VEX_HWCAPS_S390X_DFP) |
| 1290 | p = p + vex_sprintf(p, "-%s", facilities[3]); |
| 1291 | if (hwcaps & VEX_HWCAPS_S390X_FGX) |
| 1292 | p = p + vex_sprintf(p, "-%s", facilities[4]); |
florian | 90ece04 | 2012-04-21 15:41:51 +0000 | [diff] [blame] | 1293 | if (hwcaps & VEX_HWCAPS_S390X_STFLE) |
| 1294 | p = p + vex_sprintf(p, "-%s", facilities[5]); |
| 1295 | if (hwcaps & VEX_HWCAPS_S390X_ETF2) |
| 1296 | p = p + vex_sprintf(p, "-%s", facilities[6]); |
florian | 79bee4b | 2012-05-03 01:30:48 +0000 | [diff] [blame] | 1297 | if (hwcaps & VEX_HWCAPS_S390X_ETF3) |
| 1298 | p = p + vex_sprintf(p, "-%s", facilities[7]); |
florian | a4c3669 | 2012-08-26 04:22:33 +0000 | [diff] [blame] | 1299 | if (hwcaps & VEX_HWCAPS_S390X_STCKF) |
| 1300 | p = p + vex_sprintf(p, "-%s", facilities[8]); |
florian | 60b665b | 2012-08-30 20:28:00 +0000 | [diff] [blame] | 1301 | if (hwcaps & VEX_HWCAPS_S390X_FPEXT) |
| 1302 | p = p + vex_sprintf(p, "-%s", facilities[9]); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1303 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1304 | /* If there are no facilities, add "zarch" */ |
| 1305 | if (hwcaps == 0) |
| 1306 | vex_sprintf(p, "-%s", "zarch"); |
| 1307 | |
| 1308 | return buf; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1309 | } |
| 1310 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1311 | static HChar* show_hwcaps_mips32 ( UInt hwcaps ) |
| 1312 | { |
| 1313 | if (hwcaps == 0x00010000) return "MIPS-baseline"; |
| 1314 | if (hwcaps == 0x00020000) return "Broadcom-baseline"; |
| 1315 | return NULL; |
| 1316 | } |
| 1317 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1318 | /* ---- */ |
| 1319 | static HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1320 | { |
| 1321 | switch (arch) { |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1322 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
| 1323 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 1324 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 1325 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
| 1326 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
| 1327 | case VexArchS390X: return show_hwcaps_s390x(hwcaps); |
| 1328 | case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1329 | default: return NULL; |
| 1330 | } |
| 1331 | } |
| 1332 | |
| 1333 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1334 | { |
| 1335 | return show_hwcaps(arch,hwcaps) != NULL; |
| 1336 | } |
| 1337 | |
| 1338 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1339 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1340 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1341 | /*---------------------------------------------------------------*/ |