blob: 7b231458f6a207f2cbee8cb89fb141c8e0319043 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070035#include "fb.h"
Chia-I Wu09142132014-08-11 15:42:55 +080036
Chia-I Wu3c3edc02014-09-09 10:32:59 +080037/**
38 * Free all resources used by a writer. Note that the initial size is not
39 * reset.
40 */
41static void cmd_writer_reset(struct intel_cmd *cmd,
42 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080043{
Chia-I Wu68f319d2014-09-09 09:43:21 +080044 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080045
Chia-I Wu3c3edc02014-09-09 10:32:59 +080046 if (writer->ptr) {
47 intel_bo_unmap(writer->bo);
48 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080049 }
50
Chia-I Wu3c3edc02014-09-09 10:32:59 +080051 if (writer->bo) {
52 intel_bo_unreference(writer->bo);
53 writer->bo = NULL;
54 }
55
Chia-I Wue24c3292014-08-21 14:05:23 +080056 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080057
Chia-I Wuf98dd882015-02-10 04:17:47 +080058 writer->sba_offset = 0;
59
Chia-I Wu00b51a82014-09-09 12:07:37 +080060 if (writer->items) {
61 icd_free(writer->items);
Courtney Goeltzenleuchter2ba70162014-09-25 18:14:53 -060062 writer->items = NULL;
Chia-I Wu00b51a82014-09-09 12:07:37 +080063 writer->item_alloc = 0;
64 writer->item_used = 0;
65 }
Chia-I Wu3c3edc02014-09-09 10:32:59 +080066}
67
68/**
69 * Discard everything written so far.
70 */
71static void cmd_writer_discard(struct intel_cmd *cmd,
72 enum intel_cmd_writer_type which)
73{
74 struct intel_cmd_writer *writer = &cmd->writers[which];
75
76 intel_bo_truncate_relocs(writer->bo, 0);
77 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +080078 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080079}
80
81static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
82 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060083 size_t size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +080084{
85 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
86 [INTEL_CMD_WRITER_BATCH] = "batch",
Chia-I Wu15cccf72015-02-10 04:07:40 +080087 [INTEL_CMD_WRITER_SURFACE] = "surface",
88 [INTEL_CMD_WRITER_STATE] = "state",
Chia-I Wu3c3edc02014-09-09 10:32:59 +080089 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
90 };
91
Chia-I Wu72292b72014-09-09 10:48:33 +080092 return intel_winsys_alloc_buffer(winsys, writer_names[which], size, true);
Chia-I Wu3c3edc02014-09-09 10:32:59 +080093}
94
95/**
96 * Allocate and map the buffer for writing.
97 */
98static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
99 enum intel_cmd_writer_type which)
100{
101 struct intel_cmd_writer *writer = &cmd->writers[which];
102 struct intel_bo *bo;
103
104 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
105 if (bo) {
106 if (writer->bo)
107 intel_bo_unreference(writer->bo);
108 writer->bo = bo;
109 } else if (writer->bo) {
110 /* reuse the old bo */
111 cmd_writer_discard(cmd, which);
112 } else {
113 return XGL_ERROR_OUT_OF_GPU_MEMORY;
114 }
115
116 writer->used = 0;
Chia-I Wu00b51a82014-09-09 12:07:37 +0800117 writer->item_used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800118
119 writer->ptr = intel_bo_map(writer->bo, true);
120 if (!writer->ptr)
121 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800122
123 return XGL_SUCCESS;
124}
125
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800126/**
127 * Unmap the buffer for submission.
128 */
129static void cmd_writer_unmap(struct intel_cmd *cmd,
130 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800131{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800132 struct intel_cmd_writer *writer = &cmd->writers[which];
133
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800134 intel_bo_unmap(writer->bo);
135 writer->ptr = NULL;
136}
137
138/**
139 * Grow a mapped writer to at least \p new_size. Failures are handled
140 * silently.
141 */
142void cmd_writer_grow(struct intel_cmd *cmd,
143 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600144 size_t new_size)
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800145{
146 struct intel_cmd_writer *writer = &cmd->writers[which];
147 struct intel_bo *new_bo;
148 void *new_ptr;
149
150 if (new_size < writer->size << 1)
151 new_size = writer->size << 1;
152 /* STATE_BASE_ADDRESS requires page-aligned buffers */
Chia-I Wu72292b72014-09-09 10:48:33 +0800153 new_size = u_align(new_size, 4096);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800154
155 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
156 if (!new_bo) {
157 cmd_writer_discard(cmd, which);
158 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
159 return;
160 }
161
162 /* map and copy the data over */
163 new_ptr = intel_bo_map(new_bo, true);
164 if (!new_ptr) {
165 intel_bo_unreference(new_bo);
166 cmd_writer_discard(cmd, which);
167 cmd->result = XGL_ERROR_UNKNOWN;
168 return;
169 }
170
Chia-I Wu72292b72014-09-09 10:48:33 +0800171 memcpy(new_ptr, writer->ptr, writer->used);
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800172
173 intel_bo_unmap(writer->bo);
174 intel_bo_unreference(writer->bo);
175
176 writer->size = new_size;
177 writer->bo = new_bo;
178 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800179}
180
Chia-I Wu00b51a82014-09-09 12:07:37 +0800181/**
182 * Record an item for later decoding.
183 */
184void cmd_writer_record(struct intel_cmd *cmd,
185 enum intel_cmd_writer_type which,
186 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600187 size_t offset, size_t size)
Chia-I Wu00b51a82014-09-09 12:07:37 +0800188{
189 struct intel_cmd_writer *writer = &cmd->writers[which];
190 struct intel_cmd_item *item;
191
192 if (writer->item_used == writer->item_alloc) {
193 const unsigned new_alloc = (writer->item_alloc) ?
194 writer->item_alloc << 1 : 256;
195 struct intel_cmd_item *items;
196
197 items = icd_alloc(sizeof(writer->items[0]) * new_alloc,
198 0, XGL_SYSTEM_ALLOC_DEBUG);
199 if (!items) {
200 writer->item_used = 0;
201 cmd->result = XGL_ERROR_OUT_OF_MEMORY;
202 return;
203 }
204
205 memcpy(items, writer->items,
206 sizeof(writer->items[0]) * writer->item_alloc);
207
208 icd_free(writer->items);
209
210 writer->items = items;
211 writer->item_alloc = new_alloc;
212 }
213
214 item = &writer->items[writer->item_used++];
215 item->type = type;
216 item->offset = offset;
217 item->size = size;
218}
219
Chia-I Wu5e25c272014-08-21 20:19:12 +0800220static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800221 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600222 size_t offset, uint32_t val)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800223{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800224 struct intel_cmd_writer *writer = &cmd->writers[which];
225
Chia-I Wu72292b72014-09-09 10:48:33 +0800226 assert(offset + sizeof(val) <= writer->used);
227 *((uint32_t *) ((char *) writer->ptr + offset)) = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800228}
229
Chia-I Wu730e5362014-08-19 12:15:09 +0800230static void cmd_reset(struct intel_cmd *cmd)
231{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600232 uint32_t i;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800233
234 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
235 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800236
Chia-I Wua57761b2014-10-14 14:27:44 +0800237 if (cmd->bind.shader_cache.entries)
238 icd_free(cmd->bind.shader_cache.entries);
239
Chia-I Wuf8385062015-01-04 16:27:24 +0800240 if (cmd->bind.dset.graphics_dynamic_offsets)
241 icd_free(cmd->bind.dset.graphics_dynamic_offsets);
242 if (cmd->bind.dset.compute_dynamic_offsets)
243 icd_free(cmd->bind.dset.compute_dynamic_offsets);
244
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800245 memset(&cmd->bind, 0, sizeof(cmd->bind));
246
Chia-I Wu343b1372014-08-20 16:39:20 +0800247 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800248 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800249}
250
251static void cmd_destroy(struct intel_obj *obj)
252{
253 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
254
255 intel_cmd_destroy(cmd);
256}
257
258XGL_RESULT intel_cmd_create(struct intel_dev *dev,
259 const XGL_CMD_BUFFER_CREATE_INFO *info,
260 struct intel_cmd **cmd_ret)
261{
Chia-I Wu63883292014-08-25 13:50:26 +0800262 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800263 struct intel_cmd *cmd;
264
Chia-I Wu63883292014-08-25 13:50:26 +0800265 switch (info->queueType) {
266 case XGL_QUEUE_TYPE_GRAPHICS:
267 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
268 break;
269 case XGL_QUEUE_TYPE_COMPUTE:
270 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
271 break;
272 case XGL_QUEUE_TYPE_DMA:
273 pipeline_select = -1;
274 break;
275 default:
276 return XGL_ERROR_INVALID_VALUE;
277 break;
278 }
279
Chia-I Wu730e5362014-08-19 12:15:09 +0800280 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
281 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
282 if (!cmd)
283 return XGL_ERROR_OUT_OF_MEMORY;
284
285 cmd->obj.destroy = cmd_destroy;
286
287 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800288 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800289 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800290
Chia-I Wue0cdd832014-08-25 12:38:56 +0800291 /*
292 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
293 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
294 * and end offsets, for each referenced memories.
295 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800296 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
297 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
298 4096, XGL_SYSTEM_ALLOC_INTERNAL);
299 if (!cmd->relocs) {
300 intel_cmd_destroy(cmd);
301 return XGL_ERROR_OUT_OF_MEMORY;
302 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800303
304 *cmd_ret = cmd;
305
306 return XGL_SUCCESS;
307}
308
309void intel_cmd_destroy(struct intel_cmd *cmd)
310{
311 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800312
313 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800314 intel_base_destroy(&cmd->obj.base);
315}
316
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700317XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, const XGL_CMD_BUFFER_BEGIN_INFO* info)
Chia-I Wu730e5362014-08-19 12:15:09 +0800318{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800319 XGL_RESULT ret;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600320 uint32_t i;
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700321 XGL_FLAGS flags = 0;
322 XGL_CMD_BUFFER_BEGIN_INFO* next= (XGL_CMD_BUFFER_BEGIN_INFO*) info;
323 XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *ginfo;
Chia-I Wu730e5362014-08-19 12:15:09 +0800324
325 cmd_reset(cmd);
326
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700327 while (next != NULL) {
328 switch (next->sType) {
329 case XGL_STRUCTURE_TYPE_CMD_BUFFER_BEGIN_INFO:
330 flags = next->flags;
331 break;
332 case XGL_STRUCTURE_TYPE_CMD_BUFFER_GRAPHICS_BEGIN_INFO:
333 ginfo = (XGL_CMD_BUFFER_GRAPHICS_BEGIN_INFO *) next;
Jon Ashburnb1dbb372015-02-02 09:58:11 -0700334 intel_cmd_begin_render_pass(cmd, (struct intel_render_pass *)
335 ginfo->renderPass);
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700336 break;
337 default:
338 return XGL_ERROR_INVALID_VALUE;
339 break;
340 }
341 next = (XGL_CMD_BUFFER_BEGIN_INFO*) next->pNext;
342 }
343
Chia-I Wu24565ee2014-08-21 20:24:31 +0800344 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800345 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800346 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800347 }
348
Chia-I Wu68f319d2014-09-09 09:43:21 +0800349 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600350 const uint32_t size = cmd->dev->gpu->max_batch_buffer_size / 2;
351 uint32_t divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800352
353 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
354 divider *= 4;
355
Chia-I Wu68f319d2014-09-09 09:43:21 +0800356 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800357 cmd->writers[INTEL_CMD_WRITER_SURFACE].size = size / divider / 2;
358 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider / 2;
Chia-I Wu72292b72014-09-09 10:48:33 +0800359 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size = 16384 / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800360 }
361
Chia-I Wu68f319d2014-09-09 09:43:21 +0800362 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800363 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800364 if (ret != XGL_SUCCESS) {
365 cmd_reset(cmd);
366 return ret;
367 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800368 }
369
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800370 cmd_batch_begin(cmd);
371
Chia-I Wu24565ee2014-08-21 20:24:31 +0800372 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800373}
374
375XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
376{
377 struct intel_winsys *winsys = cmd->dev->winsys;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600378 uint32_t i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800379
Chia-I Wub8762122014-12-01 22:51:03 +0800380 /* no matching intel_cmd_begin() */
381 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].ptr)
382 return XGL_ERROR_INCOMPLETE_COMMAND_BUFFER;
383
Chia-I Wue24c3292014-08-21 14:05:23 +0800384 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800385
Chia-I Wu343b1372014-08-20 16:39:20 +0800386 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800387 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800388 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800389 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800390 uint64_t presumed_offset;
391 int err;
392
Chia-I Wud7d1e482014-10-18 13:25:10 +0800393 /*
394 * Once a bo is used as a reloc target, libdrm_intel disallows more
395 * relocs to be added to it. That may happen when
396 * INTEL_CMD_RELOC_TARGET_IS_WRITER is set. We have to process them
397 * in another pass.
398 */
399 if (reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER)
400 continue;
401
Chia-I Wu72292b72014-09-09 10:48:33 +0800402 err = intel_bo_add_reloc(writer->bo, reloc->offset,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800403 (struct intel_bo *) reloc->target, reloc->target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800404 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800405 if (err) {
406 cmd->result = XGL_ERROR_UNKNOWN;
407 break;
408 }
409
410 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu72292b72014-09-09 10:48:33 +0800411 cmd_writer_patch(cmd, reloc->which, reloc->offset,
Chia-I Wue24c3292014-08-21 14:05:23 +0800412 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800413 }
Chia-I Wud7d1e482014-10-18 13:25:10 +0800414 for (i = 0; i < cmd->reloc_used; i++) {
415 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
416 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
417 uint64_t presumed_offset;
418 int err;
419
420 if (!(reloc->flags & INTEL_CMD_RELOC_TARGET_IS_WRITER))
421 continue;
422
423 err = intel_bo_add_reloc(writer->bo, reloc->offset,
424 cmd->writers[reloc->target].bo, reloc->target_offset,
425 reloc->flags & ~INTEL_CMD_RELOC_TARGET_IS_WRITER,
426 &presumed_offset);
427 if (err) {
428 cmd->result = XGL_ERROR_UNKNOWN;
429 break;
430 }
431
432 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
433 cmd_writer_patch(cmd, reloc->which, reloc->offset,
434 (uint32_t) presumed_offset);
435 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800436
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800437 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
438 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800439
Chia-I Wu04966702014-08-20 15:05:03 +0800440 if (cmd->result != XGL_SUCCESS)
441 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800442
Chia-I Wu68f319d2014-09-09 09:43:21 +0800443 if (intel_winsys_can_submit_bo(winsys,
444 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800445 return XGL_SUCCESS;
446 else
447 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
448}
449
Chia-I Wu96177272015-01-03 15:27:41 +0800450ICD_EXPORT XGL_RESULT XGLAPI xglCreateCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800451 XGL_DEVICE device,
452 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
453 XGL_CMD_BUFFER* pCmdBuffer)
454{
Chia-I Wu730e5362014-08-19 12:15:09 +0800455 struct intel_dev *dev = intel_dev(device);
456
457 return intel_cmd_create(dev, pCreateInfo,
458 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800459}
460
Chia-I Wu96177272015-01-03 15:27:41 +0800461ICD_EXPORT XGL_RESULT XGLAPI xglBeginCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800462 XGL_CMD_BUFFER cmdBuffer,
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700463 const XGL_CMD_BUFFER_BEGIN_INFO *info)
Chia-I Wu09142132014-08-11 15:42:55 +0800464{
Chia-I Wu730e5362014-08-19 12:15:09 +0800465 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
466
Jon Ashburnc04b4dc2015-01-08 18:48:10 -0700467 return intel_cmd_begin(cmd, info);
Chia-I Wu09142132014-08-11 15:42:55 +0800468}
469
Chia-I Wu96177272015-01-03 15:27:41 +0800470ICD_EXPORT XGL_RESULT XGLAPI xglEndCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800471 XGL_CMD_BUFFER cmdBuffer)
472{
Chia-I Wu730e5362014-08-19 12:15:09 +0800473 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
474
475 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800476}
477
Chia-I Wu96177272015-01-03 15:27:41 +0800478ICD_EXPORT XGL_RESULT XGLAPI xglResetCommandBuffer(
Chia-I Wu09142132014-08-11 15:42:55 +0800479 XGL_CMD_BUFFER cmdBuffer)
480{
Chia-I Wu730e5362014-08-19 12:15:09 +0800481 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
482
483 cmd_reset(cmd);
484
485 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800486}
487
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600488ICD_EXPORT void XGLAPI xglCmdInitAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800489 XGL_CMD_BUFFER cmdBuffer,
490 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600491 uint32_t startCounter,
492 uint32_t counterCount,
493 const uint32_t* pData)
Chia-I Wu09142132014-08-11 15:42:55 +0800494{
495}
496
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600497ICD_EXPORT void XGLAPI xglCmdLoadAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800498 XGL_CMD_BUFFER cmdBuffer,
499 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600500 uint32_t startCounter,
501 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800502 XGL_BUFFER srcBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800503 XGL_GPU_SIZE srcOffset)
504{
505}
506
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600507ICD_EXPORT void XGLAPI xglCmdSaveAtomicCounters(
Chia-I Wu09142132014-08-11 15:42:55 +0800508 XGL_CMD_BUFFER cmdBuffer,
509 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600510 uint32_t startCounter,
511 uint32_t counterCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800512 XGL_BUFFER destBuffer,
Chia-I Wu09142132014-08-11 15:42:55 +0800513 XGL_GPU_SIZE destOffset)
514{
515}
516
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600517ICD_EXPORT void XGLAPI xglCmdDbgMarkerBegin(
Chia-I Wu09142132014-08-11 15:42:55 +0800518 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600519 const char* pMarker)
Chia-I Wu09142132014-08-11 15:42:55 +0800520{
521}
522
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600523ICD_EXPORT void XGLAPI xglCmdDbgMarkerEnd(
Chia-I Wu09142132014-08-11 15:42:55 +0800524 XGL_CMD_BUFFER cmdBuffer)
525{
526}