blob: d1ea76a14653b3da59f985b14ddfbff3c36aaf3a [file] [log] [blame]
Eugene Zelenko076468c2017-09-20 21:35:51 +00001//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
Johnny Chen7b999ea2010-04-02 22:27:38 +00002//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Johnny Chen7b999ea2010-04-02 22:27:38 +00006//
7//===----------------------------------------------------------------------===//
Johnny Chen7b999ea2010-04-02 22:27:38 +00008
Owen Andersone0152a72011-08-09 20:55:18 +00009#include "MCTargetDesc/ARMAddressingModes.h"
10#include "MCTargetDesc/ARMBaseInfo.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000011#include "MCTargetDesc/ARMMCTargetDesc.h"
Richard Trieuf3011b92019-05-14 22:29:50 +000012#include "TargetInfo/ARMTargetInfo.h"
Eugene Zelenko076468c2017-09-20 21:35:51 +000013#include "Utils/ARMBaseInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000014#include "llvm/MC/MCContext.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000015#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen7b999ea2010-04-02 22:27:38 +000017#include "llvm/MC/MCInst.h"
Benjamin Kramer48b5bbf2011-11-11 12:39:41 +000018#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith7a3973d2012-04-03 15:48:14 +000019#include "llvm/MC/MCSubtargetInfo.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000020#include "llvm/MC/SubtargetFeature.h"
21#include "llvm/Support/Compiler.h"
Johnny Chen7b999ea2010-04-02 22:27:38 +000022#include "llvm/Support/ErrorHandling.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000023#include "llvm/Support/MathExtras.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000024#include "llvm/Support/TargetRegistry.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000025#include "llvm/Support/raw_ostream.h"
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000026#include <algorithm>
27#include <cassert>
28#include <cstdint>
Richard Bartone9600002012-04-24 11:13:20 +000029#include <vector>
Johnny Chen7b999ea2010-04-02 22:27:38 +000030
James Molloydb4ce602011-09-01 18:02:14 +000031using namespace llvm;
Owen Andersona4043c42011-08-17 17:44:15 +000032
Chandler Carruth84e68b22014-04-22 02:41:26 +000033#define DEBUG_TYPE "arm-disassembler"
34
Eugene Zelenko076468c2017-09-20 21:35:51 +000035using DecodeStatus = MCDisassembler::DecodeStatus;
Owen Anderson03aadae2011-09-01 23:23:50 +000036
Owen Andersoned96b582011-09-01 23:35:51 +000037namespace {
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000038
Richard Bartone9600002012-04-24 11:13:20 +000039 // Handles the condition code status of instructions in IT blocks
40 class ITStatus
41 {
42 public:
43 // Returns the condition code for instruction in IT block
44 unsigned getITCC() {
45 unsigned CC = ARMCC::AL;
46 if (instrInITBlock())
47 CC = ITStates.back();
48 return CC;
49 }
50
51 // Advances the IT block state to the next T or E
52 void advanceITState() {
53 ITStates.pop_back();
54 }
55
56 // Returns true if the current instruction is in an IT block
57 bool instrInITBlock() {
58 return !ITStates.empty();
59 }
60
61 // Returns true if current instruction is the last instruction in an IT block
62 bool instrLastInITBlock() {
63 return ITStates.size() == 1;
64 }
65
66 // Called when decoding an IT instruction. Sets the IT state for the following
Vinicius Tinti67cf33d2015-11-20 23:20:12 +000067 // instructions that for the IT block. Firstcond and Mask correspond to the
Richard Bartone9600002012-04-24 11:13:20 +000068 // fields in the IT instruction encoding.
69 void setITState(char Firstcond, char Mask) {
70 // (3 - the number of trailing zeros) is the number of then / else.
Richard Bartonf435b092012-04-27 08:42:59 +000071 unsigned CondBit0 = Firstcond & 1;
Michael J. Spencerdf1ecbd72013-05-24 22:23:49 +000072 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Bartone9600002012-04-24 11:13:20 +000073 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74 assert(NumTZ <= 3 && "Invalid IT mask!");
75 // push condition codes onto the stack the correct order for the pops
76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77 bool T = ((Mask >> Pos) & 1) == CondBit0;
78 if (T)
79 ITStates.push_back(CCBits);
80 else
81 ITStates.push_back(CCBits ^ 1);
82 }
83 ITStates.push_back(CCBits);
84 }
85
86 private:
87 std::vector<unsigned char> ITStates;
88 };
Richard Bartone9600002012-04-24 11:13:20 +000089
Rafael Espindola4aa6bea2014-11-10 18:11:10 +000090/// ARM disassembler for all ARM platforms.
Owen Andersoned96b582011-09-01 23:35:51 +000091class ARMDisassembler : public MCDisassembler {
92public:
Lang Hamesa1bc0f52014-04-15 04:40:56 +000093 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
Owen Andersoned96b582011-09-01 23:35:51 +000095 }
96
Eugene Zelenkoe79c0772017-01-27 23:58:02 +000097 ~ARMDisassembler() override = default;
Owen Andersoned96b582011-09-01 23:35:51 +000098
Rafael Espindola4aa6bea2014-11-10 18:11:10 +000099 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000100 ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000101 raw_ostream &VStream,
102 raw_ostream &CStream) const override;
Owen Andersoned96b582011-09-01 23:35:51 +0000103};
104
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000105/// Thumb disassembler for all Thumb platforms.
Owen Andersoned96b582011-09-01 23:35:51 +0000106class ThumbDisassembler : public MCDisassembler {
107public:
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109 MCDisassembler(STI, Ctx) {
Owen Andersoned96b582011-09-01 23:35:51 +0000110 }
111
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000112 ~ThumbDisassembler() override = default;
Owen Andersoned96b582011-09-01 23:35:51 +0000113
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000115 ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000116 raw_ostream &VStream,
117 raw_ostream &CStream) const override;
Owen Andersoned96b582011-09-01 23:35:51 +0000118
Owen Andersoned96b582011-09-01 23:35:51 +0000119private:
Richard Bartone9600002012-04-24 11:13:20 +0000120 mutable ITStatus ITBlock;
Eugene Zelenko076468c2017-09-20 21:35:51 +0000121
Owen Anderson2fefa422011-09-08 22:42:49 +0000122 DecodeStatus AddThumbPredicate(MCInst&) const;
Simon Tathamb70fc0c2019-02-25 10:39:53 +0000123 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
Owen Andersoned96b582011-09-01 23:35:51 +0000124};
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000125
126} // end anonymous namespace
Owen Andersoned96b582011-09-01 23:35:51 +0000127
Owen Anderson03aadae2011-09-01 23:23:50 +0000128static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloydb4ce602011-09-01 18:02:14 +0000129 switch (In) {
130 case MCDisassembler::Success:
131 // Out stays the same.
132 return true;
133 case MCDisassembler::SoftFail:
134 Out = In;
135 return true;
136 case MCDisassembler::Fail:
137 Out = In;
138 return false;
139 }
David Blaikie46a9f012012-01-20 21:51:11 +0000140 llvm_unreachable("Invalid DecodeStatus!");
James Molloydb4ce602011-09-01 18:02:14 +0000141}
Owen Andersona4043c42011-08-17 17:44:15 +0000142
Owen Andersone0152a72011-08-09 20:55:18 +0000143// Forward declare these because the autogenerated code will reference them.
144// Definitions are further down.
Craig Topperf6e7e122012-03-27 07:21:54 +0000145static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000146 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000147static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000148 unsigned RegNo, uint64_t Address,
149 const void *Decoder);
Mihai Popadc1764c52013-05-13 14:10:04 +0000150static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
151 unsigned RegNo, uint64_t Address,
152 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000153static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000154 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000155static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000156 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000157static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000158 uint64_t Address, const void *Decoder);
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000159static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
Sjoerd Meijer011de9c2018-01-26 09:26:40 +0000161static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000163static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000164 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000165static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000166 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000167static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000168 uint64_t Address, const void *Decoder);
Diogo N. Sampaioc20c37b2019-03-08 17:11:20 +0000169static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000171static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000172 unsigned RegNo,
173 uint64_t Address,
174 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000175static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000176 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000177static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc988e0c2012-03-05 19:33:30 +0000178 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000179static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbache5307f92012-03-05 21:43:40 +0000180 unsigned RegNo, uint64_t Address,
181 const void *Decoder);
Johnny Chen74491bb2010-08-12 01:40:54 +0000182
Craig Topperf6e7e122012-03-27 07:21:54 +0000183static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000184 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000185static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000186 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000187static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000188 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000189static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000190 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000191static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000192 uint64_t Address, const void *Decoder);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000193
Craig Topperf6e7e122012-03-27 07:21:54 +0000194static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000195 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000196static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000197 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000198static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000199 unsigned Insn,
200 uint64_t Address,
201 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000202static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000203 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000204static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000205 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000206static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000207 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000208static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000209 uint64_t Address, const void *Decoder);
210
Craig Topperf6e7e122012-03-27 07:21:54 +0000211static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Andersone0152a72011-08-09 20:55:18 +0000212 unsigned Insn,
213 uint64_t Adddress,
214 const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000215static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +0000216 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000217static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +0000218 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000219static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000220 uint64_t Address, const void *Decoder);
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000221static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000223static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson3d2e0e9d2011-08-09 23:05:39 +0000224 uint64_t Address, const void *Decoder);
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +0000225static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
226 uint64_t Address, const void *Decoder);
227static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000229static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson9b7bd152011-08-23 17:45:18 +0000230 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000231static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000232 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000233static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000234 uint64_t Address, const void *Decoder);
Oliver Stannard65b85382016-01-25 10:26:26 +0000235static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000237static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000238 uint64_t Address, const void *Decoder);
Kevin Enderby40d4e472012-04-12 23:13:34 +0000239static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
240 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000241static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000242 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000243static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000244 uint64_t Address, const void *Decoder);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +0000245static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000253static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000254 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000255static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000256 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000257static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000258 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000259static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000260 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000261static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000262 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000263static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000264 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000265static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000266 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000267static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000268 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000269static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000270 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000271static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000272 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000273static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000274 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000275static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000276 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000277static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000278 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000279static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000280 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000281static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000282 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000283static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersone0089312011-08-09 23:25:42 +0000284 uint64_t Address, const void *Decoder);
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +0000285static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000287static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson60663402011-08-11 20:21:46 +0000288 uint64_t Address, const void *Decoder);
Tim Northoveree843ef2014-08-15 10:47:12 +0000289static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000291static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersonb685c9f2011-08-11 21:34:58 +0000292 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000293static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Andersonc5798a3a52011-08-12 17:58:32 +0000294 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000295static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +0000296 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000297static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +0000298 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000299static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +0000300 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000301static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +0000302 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000303static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000304 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000305static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000306 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000307static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000308 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000309static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000310 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000311static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000312 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000313static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000314 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000315static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000316 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000317static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +0000318 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000319static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +0000320 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000321static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +0000322 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000323static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersondde461c2011-10-28 18:02:13 +0000324 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000325static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +0000326 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000327static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +0000328 uint64_t Address, const void *Decoder);
Sam Parker963da5b2017-09-29 13:11:33 +0000329static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
330 unsigned Val,
331 uint64_t Address,
332 const void *Decoder);
Owen Anderson0ac90582011-11-15 19:55:00 +0000333
Craig Topperf6e7e122012-03-27 07:21:54 +0000334static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000335 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000336static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000337 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000338static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000339 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000340static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000341 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000342static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000343 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000344static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000345 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000346static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000347 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000348static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000349 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000350static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000351 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000352static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000353 uint64_t Address, const void *Decoder);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +0000354static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void* Decoder);
358static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
359 uint64_t Address, const void* Decoder);
360static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
361 uint64_t Address, const void* Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000362static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000363 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000364static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000365 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000366static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbacha05627e2011-09-09 18:37:27 +0000367 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000368static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000369 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000370static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000371 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000372static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000373 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000374static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000375 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000376static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000377 uint64_t Address, const void *Decoder);
Amaury de la Vieuville631df632013-06-08 13:38:52 +0000378static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
379 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000380static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +0000381 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000382static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000383 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000384static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach05541f42011-09-19 22:21:13 +0000385 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000386static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000387 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000388static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000389 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000390static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000391 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000392static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +0000393 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000394static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson37612a32011-08-24 22:40:22 +0000395 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000396static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +0000397 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000398static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +0000399 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000400static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson5bfb0e02011-09-09 22:24:36 +0000401 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000402static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona9ebf6f2011-09-12 18:56:30 +0000403 uint64_t Address, const void *Decoder);
Craig Topperf6e7e122012-03-27 07:21:54 +0000404static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Andersonf01e2de2011-09-26 21:06:22 +0000405 uint64_t Address, const void *Decoder);
406
Craig Topperf6e7e122012-03-27 07:21:54 +0000407static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangad213f212012-03-22 13:24:43 +0000408 uint64_t Address, const void *Decoder);
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000409static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh39d2d092016-06-17 00:52:41 +0000410 uint64_t Address, const void *Decoder);
Andre Vieira640527f2017-09-22 12:17:42 +0000411static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
412 uint64_t Address, const void *Decoder);
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000413
Owen Andersone0152a72011-08-09 20:55:18 +0000414#include "ARMGenDisassemblerTables.inc"
Sean Callanan814e69b2010-04-13 21:21:57 +0000415
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000416static MCDisassembler *createARMDisassembler(const Target &T,
417 const MCSubtargetInfo &STI,
418 MCContext &Ctx) {
419 return new ARMDisassembler(STI, Ctx);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000420}
421
Lang Hamesa1bc0f52014-04-15 04:40:56 +0000422static MCDisassembler *createThumbDisassembler(const Target &T,
423 const MCSubtargetInfo &STI,
424 MCContext &Ctx) {
425 return new ThumbDisassembler(STI, Ctx);
Johnny Chen7b999ea2010-04-02 22:27:38 +0000426}
427
Charlie Turner30895f92014-12-01 08:50:27 +0000428// Post-decoding checks
429static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
430 uint64_t Address, raw_ostream &OS,
431 raw_ostream &CS,
432 uint32_t Insn,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000433 DecodeStatus Result) {
Charlie Turner30895f92014-12-01 08:50:27 +0000434 switch (MI.getOpcode()) {
435 case ARM::HVC: {
436 // HVC is undefined if condition = 0xf otherwise upredictable
437 // if condition != 0xe
438 uint32_t Cond = (Insn >> 28) & 0xF;
439 if (Cond == 0xF)
440 return MCDisassembler::Fail;
441 if (Cond != 0xE)
442 return MCDisassembler::SoftFail;
443 return Result;
444 }
Tim Northover6af366b2019-04-23 13:50:13 +0000445 case ARM::t2ADDri:
446 case ARM::t2ADDri12:
447 case ARM::t2ADDrr:
448 case ARM::t2ADDrs:
449 case ARM::t2SUBri:
450 case ARM::t2SUBri12:
451 case ARM::t2SUBrr:
452 case ARM::t2SUBrs:
453 if (MI.getOperand(0).getReg() == ARM::SP &&
454 MI.getOperand(1).getReg() != ARM::SP)
455 return MCDisassembler::SoftFail;
456 return Result;
Charlie Turner30895f92014-12-01 08:50:27 +0000457 default: return Result;
458 }
459}
460
Owen Anderson03aadae2011-09-01 23:23:50 +0000461DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000462 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000463 uint64_t Address, raw_ostream &OS,
464 raw_ostream &CS) const {
465 CommentStream = &CS;
Kevin Enderby5dcda642011-10-04 22:44:48 +0000466
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000467 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000468 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
469 "mode!");
James Molloy8067df92011-09-07 19:42:28 +0000470
Owen Andersone0152a72011-08-09 20:55:18 +0000471 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000472 if (Bytes.size() < 4) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000473 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000474 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000475 }
Owen Andersone0152a72011-08-09 20:55:18 +0000476
477 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000478 uint32_t Insn =
479 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Owen Andersone0152a72011-08-09 20:55:18 +0000480
481 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000482 DecodeStatus Result =
483 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
484 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000485 Size = 4;
Charlie Turner30895f92014-12-01 08:50:27 +0000486 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Andersone0152a72011-08-09 20:55:18 +0000487 }
488
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000489 struct DecodeTable {
490 const uint8_t *P;
491 bool DecodePred;
492 };
Owen Andersone0152a72011-08-09 20:55:18 +0000493
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000494 const DecodeTable Tables[] = {
495 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
496 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
497 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
498 {DecoderTablev8Crypto32, false},
499 };
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000500
Sjoerd Meijeraea3a992017-03-13 09:41:10 +0000501 for (auto Table : Tables) {
502 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
503 if (Result != MCDisassembler::Fail) {
504 Size = 4;
505 // Add a fake predicate operand, because we share these instruction
506 // definitions with Thumb2 where these instructions are predicable.
507 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
508 return MCDisassembler::Fail;
509 return Result;
510 }
Amara Emerson33089092013-09-19 11:59:01 +0000511 }
512
Sjoerd Meijer7426c972017-08-11 09:52:30 +0000513 Result =
514 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
515 if (Result != MCDisassembler::Fail) {
516 Size = 4;
517 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
518 }
519
Eugene Leviant6269d392017-06-29 15:38:47 +0000520 Size = 4;
James Molloydb4ce602011-09-01 18:02:14 +0000521 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000522}
523
524namespace llvm {
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000525
Benjamin Kramer0d6d0982011-10-22 16:50:00 +0000526extern const MCInstrDesc ARMInsts[];
Eugene Zelenkoe79c0772017-01-27 23:58:02 +0000527
528} // end namespace llvm
Owen Andersone0152a72011-08-09 20:55:18 +0000529
Kevin Enderby5dcda642011-10-04 22:44:48 +0000530/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
531/// immediate Value in the MCInst. The immediate Value has had any PC
532/// adjustment made by the caller. If the instruction is a branch instruction
533/// then isBranch is true, else false. If the getOpInfo() function was set as
534/// part of the setupForSymbolicDisassembly() call then that function is called
535/// to get any symbolic information at the Address for this instruction. If
536/// that returns non-zero then the symbolic information it returns is used to
537/// create an MCExpr and that is added as an operand to the MCInst. If
538/// getOpInfo() returns zero and isBranch is true then a symbol look up for
539/// Value is done and if a symbol is found an MCExpr is created with that, else
540/// an MCExpr with Value is created. This function returns true if it adds an
541/// operand to the MCInst and false otherwise.
542static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
543 bool isBranch, uint64_t InstSize,
544 MCInst &MI, const void *Decoder) {
545 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougachaad1084d2013-05-24 00:39:57 +0000546 // FIXME: Does it make sense for value to be negative?
547 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
548 /* Offset */ 0, InstSize);
Kevin Enderby5dcda642011-10-04 22:44:48 +0000549}
550
551/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
552/// referenced by a load instruction with the base register that is the Pc.
553/// These can often be values in a literal pool near the Address of the
554/// instruction. The Address of the instruction and its immediate Value are
555/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru35521e22012-07-23 08:51:15 +0000556/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby5dcda642011-10-04 22:44:48 +0000557/// the referenced address is that of a symbol. Or it will return a pointer to
558/// a literal 'C' string if the referenced address of the literal pool's entry
559/// is an address into a section with 'C' string literals.
560static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +0000561 const void *Decoder) {
Kevin Enderby5dcda642011-10-04 22:44:48 +0000562 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougachaad1084d2013-05-24 00:39:57 +0000563 Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby5dcda642011-10-04 22:44:48 +0000564}
565
Owen Andersone0152a72011-08-09 20:55:18 +0000566// Thumb1 instructions don't have explicit S bits. Rather, they
567// implicitly set CPSR. Since it's not represented in the encoding, the
568// auto-generated decoder won't inject the CPSR operand. We need to fix
569// that as a post-pass.
570static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
571 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson187e1e42011-08-17 18:14:48 +0000572 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Andersone0152a72011-08-09 20:55:18 +0000573 MCInst::iterator I = MI.begin();
Owen Anderson187e1e42011-08-17 18:14:48 +0000574 for (unsigned i = 0; i < NumOps; ++i, ++I) {
575 if (I == MI.end()) break;
Owen Andersone0152a72011-08-09 20:55:18 +0000576 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson187e1e42011-08-17 18:14:48 +0000577 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbache9119e42015-05-13 18:37:00 +0000578 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +0000579 return;
580 }
581 }
582
Jim Grosbache9119e42015-05-13 18:37:00 +0000583 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +0000584}
585
586// Most Thumb instructions don't have explicit predicates in the
587// encoding, but rather get their predicates from IT context. We need
588// to fix up the predicate operands using this context information as a
589// post-pass.
Owen Anderson2fefa422011-09-08 22:42:49 +0000590MCDisassembler::DecodeStatus
591ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000592 MCDisassembler::DecodeStatus S = Success;
593
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000594 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
595
Owen Andersone0152a72011-08-09 20:55:18 +0000596 // A few instructions actually have predicates encoded in them. Don't
597 // try to overwrite it if we're seeing one of those.
598 switch (MI.getOpcode()) {
599 case ARM::tBcc:
600 case ARM::t2Bcc:
Owen Anderson2fefa422011-09-08 22:42:49 +0000601 case ARM::tCBZ:
602 case ARM::tCBNZ:
Owen Anderson61e46042011-09-19 23:47:10 +0000603 case ARM::tCPS:
604 case ARM::t2CPS3p:
605 case ARM::t2CPS2p:
606 case ARM::t2CPS1p:
Owen Anderson163be012011-09-19 23:57:20 +0000607 case ARM::tMOVSr:
Owen Anderson44f76ea2011-10-13 17:58:39 +0000608 case ARM::tSETEND:
Owen Anderson33d39532011-09-08 22:48:37 +0000609 // Some instructions (mostly conditional branches) are not
610 // allowed in IT blocks.
Richard Bartone9600002012-04-24 11:13:20 +0000611 if (ITBlock.instrInITBlock())
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000612 S = SoftFail;
613 else
614 return Success;
615 break;
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000616 case ARM::t2HINT:
617 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
618 S = SoftFail;
619 break;
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000620 case ARM::tB:
621 case ARM::t2B:
Owen Andersonf902d922011-09-19 22:34:23 +0000622 case ARM::t2TBB:
623 case ARM::t2TBH:
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000624 // Some instructions (mostly unconditional branches) can
625 // only appears at the end of, or outside of, an IT.
Richard Bartone9600002012-04-24 11:13:20 +0000626 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000627 S = SoftFail;
Owen Anderson2fefa422011-09-08 22:42:49 +0000628 break;
Owen Andersone0152a72011-08-09 20:55:18 +0000629 default:
630 break;
631 }
632
633 // If we're in an IT block, base the predicate on that. Otherwise,
634 // assume a predicate of AL.
635 unsigned CC;
Richard Bartone9600002012-04-24 11:13:20 +0000636 CC = ITBlock.getITCC();
Fangrui Songf78650a2018-07-30 19:41:25 +0000637 if (CC == 0xF)
Owen Andersone0152a72011-08-09 20:55:18 +0000638 CC = ARMCC::AL;
Richard Bartone9600002012-04-24 11:13:20 +0000639 if (ITBlock.instrInITBlock())
640 ITBlock.advanceITState();
Owen Andersone0152a72011-08-09 20:55:18 +0000641
642 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson187e1e42011-08-17 18:14:48 +0000643 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Andersone0152a72011-08-09 20:55:18 +0000644 MCInst::iterator I = MI.begin();
Owen Anderson187e1e42011-08-17 18:14:48 +0000645 for (unsigned i = 0; i < NumOps; ++i, ++I) {
646 if (I == MI.end()) break;
Owen Andersone0152a72011-08-09 20:55:18 +0000647 if (OpInfo[i].isPredicate()) {
Simon Tathamb70fc0c2019-02-25 10:39:53 +0000648 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
649 Check(S, SoftFail);
Jim Grosbache9119e42015-05-13 18:37:00 +0000650 I = MI.insert(I, MCOperand::createImm(CC));
Owen Andersone0152a72011-08-09 20:55:18 +0000651 ++I;
652 if (CC == ARMCC::AL)
Jim Grosbache9119e42015-05-13 18:37:00 +0000653 MI.insert(I, MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +0000654 else
Jim Grosbache9119e42015-05-13 18:37:00 +0000655 MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000656 return S;
Owen Andersone0152a72011-08-09 20:55:18 +0000657 }
658 }
659
Jim Grosbache9119e42015-05-13 18:37:00 +0000660 I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson187e1e42011-08-17 18:14:48 +0000661 ++I;
Owen Andersone0152a72011-08-09 20:55:18 +0000662 if (CC == ARMCC::AL)
Jim Grosbache9119e42015-05-13 18:37:00 +0000663 MI.insert(I, MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +0000664 else
Jim Grosbache9119e42015-05-13 18:37:00 +0000665 MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson2fefa422011-09-08 22:42:49 +0000666
Owen Anderson29cfe6c2011-09-09 21:48:23 +0000667 return S;
Owen Andersone0152a72011-08-09 20:55:18 +0000668}
669
670// Thumb VFP instructions are a special case. Because we share their
671// encodings between ARM and Thumb modes, and they are predicable in ARM
672// mode, the auto-generated decoder will give them an (incorrect)
673// predicate operand. We need to rewrite these operands based on the IT
674// context as a post-pass.
Simon Tathamb70fc0c2019-02-25 10:39:53 +0000675void ThumbDisassembler::UpdateThumbVFPPredicate(
676 DecodeStatus &S, MCInst &MI) const {
Owen Andersone0152a72011-08-09 20:55:18 +0000677 unsigned CC;
Richard Bartone9600002012-04-24 11:13:20 +0000678 CC = ITBlock.getITCC();
Tim Northoverb73efb82018-06-26 11:39:20 +0000679 if (CC == 0xF)
680 CC = ARMCC::AL;
Richard Bartone9600002012-04-24 11:13:20 +0000681 if (ITBlock.instrInITBlock())
682 ITBlock.advanceITState();
Owen Andersone0152a72011-08-09 20:55:18 +0000683
684 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
685 MCInst::iterator I = MI.begin();
Owen Anderson216cfaa2011-08-24 21:35:46 +0000686 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
687 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Andersone0152a72011-08-09 20:55:18 +0000688 if (OpInfo[i].isPredicate() ) {
Simon Tathamb70fc0c2019-02-25 10:39:53 +0000689 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
690 Check(S, SoftFail);
Owen Andersone0152a72011-08-09 20:55:18 +0000691 I->setImm(CC);
692 ++I;
693 if (CC == ARMCC::AL)
694 I->setReg(0);
695 else
696 I->setReg(ARM::CPSR);
697 return;
698 }
699 }
700}
701
Owen Anderson03aadae2011-09-01 23:23:50 +0000702DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000703 ArrayRef<uint8_t> Bytes,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000704 uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000705 raw_ostream &OS,
706 raw_ostream &CS) const {
707 CommentStream = &CS;
Kevin Enderby5dcda642011-10-04 22:44:48 +0000708
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000709 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy8067df92011-09-07 19:42:28 +0000710 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
711
Owen Andersone0152a72011-08-09 20:55:18 +0000712 // We want to read exactly 2 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000713 if (Bytes.size() < 2) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000714 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000715 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000716 }
Owen Andersone0152a72011-08-09 20:55:18 +0000717
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000718 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
719 DecodeStatus Result =
720 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
721 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000722 Size = 2;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000723 Check(Result, AddThumbPredicate(MI));
724 return Result;
Owen Anderson91a8f9b2011-08-16 23:45:44 +0000725 }
726
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000727 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
728 STI);
729 if (Result) {
Owen Anderson91a8f9b2011-08-16 23:45:44 +0000730 Size = 2;
Richard Bartone9600002012-04-24 11:13:20 +0000731 bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000732 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000733 AddThumb1SBit(MI, InITBlock);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000734 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000735 }
736
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000737 Result =
738 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
739 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000740 Size = 2;
Owen Anderson6a5c1502011-10-06 23:33:11 +0000741
742 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
743 // the Thumb predicate.
Richard Bartone9600002012-04-24 11:13:20 +0000744 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000745 Result = MCDisassembler::SoftFail;
Owen Anderson6a5c1502011-10-06 23:33:11 +0000746
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000747 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000748
749 // If we find an IT instruction, we need to parse its condition
750 // code and mask operands so that we can apply them correctly
751 // to the subsequent instructions.
752 if (MI.getOpcode() == ARM::t2IT) {
Richard Bartone9600002012-04-24 11:13:20 +0000753 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson2fa06a72011-08-30 22:58:27 +0000754 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartone9600002012-04-24 11:13:20 +0000755 ITBlock.setITState(Firstcond, Mask);
Tim Northoverbf548582018-06-26 11:38:41 +0000756
757 // An IT instruction that would give a 'NV' predicate is unpredictable.
758 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
759 CS << "unpredictable IT predicate sequence";
Owen Andersone0152a72011-08-09 20:55:18 +0000760 }
761
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000762 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000763 }
764
765 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000766 if (Bytes.size() < 4) {
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000767 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000768 return MCDisassembler::Fail;
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000769 }
Owen Andersone0152a72011-08-09 20:55:18 +0000770
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000771 uint32_t Insn32 =
772 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000773 Result =
774 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
775 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000776 Size = 4;
Richard Bartone9600002012-04-24 11:13:20 +0000777 bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000778 Check(Result, AddThumbPredicate(MI));
Owen Andersone0152a72011-08-09 20:55:18 +0000779 AddThumb1SBit(MI, InITBlock);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000780 return Result;
Owen Andersone0152a72011-08-09 20:55:18 +0000781 }
782
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000783 Result =
784 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
785 if (Result != MCDisassembler::Fail) {
Owen Andersone0152a72011-08-09 20:55:18 +0000786 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000787 Check(Result, AddThumbPredicate(MI));
Tim Northover6af366b2019-04-23 13:50:13 +0000788 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result);
Owen Andersone0152a72011-08-09 20:55:18 +0000789 }
790
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000791 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000792 Result =
793 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
794 if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000795 Size = 4;
Simon Tathamb70fc0c2019-02-25 10:39:53 +0000796 UpdateThumbVFPPredicate(Result, MI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000797 return Result;
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000798 }
Owen Andersone0152a72011-08-09 20:55:18 +0000799 }
800
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000801 Result =
802 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
803 if (Result != MCDisassembler::Fail) {
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000804 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000805 return Result;
Joey Goulycc4ff9e2013-07-04 14:57:20 +0000806 }
807
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000808 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000809 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
810 STI);
811 if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000812 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000813 Check(Result, AddThumbPredicate(MI));
814 return Result;
Amaury de la Vieuville8449c0d2013-06-24 09:15:01 +0000815 }
Owen Andersona6201f02011-08-15 23:38:54 +0000816 }
817
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000818 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000819 uint32_t NEONLdStInsn = Insn32;
Owen Andersona6201f02011-08-15 23:38:54 +0000820 NEONLdStInsn &= 0xF0FFFFFF;
821 NEONLdStInsn |= 0x04000000;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000822 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbachecaef492012-08-14 19:06:05 +0000823 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000824 if (Result != MCDisassembler::Fail) {
Owen Andersona6201f02011-08-15 23:38:54 +0000825 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000826 Check(Result, AddThumbPredicate(MI));
827 return Result;
Owen Andersona6201f02011-08-15 23:38:54 +0000828 }
829 }
830
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000831 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000832 uint32_t NEONDataInsn = Insn32;
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000833 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
834 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
835 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000836 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbachecaef492012-08-14 19:06:05 +0000837 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000838 if (Result != MCDisassembler::Fail) {
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000839 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000840 Check(Result, AddThumbPredicate(MI));
841 return Result;
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000842 }
Owen Andersonc86a5bd2011-08-10 19:01:10 +0000843
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000844 uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000845 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
846 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
847 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000848 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000849 Address, this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000850 if (Result != MCDisassembler::Fail) {
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000851 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000852 return Result;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000853 }
Amara Emerson33089092013-09-19 11:59:01 +0000854
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000855 uint32_t NEONv8Insn = Insn32;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000856 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000857 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000858 this, STI);
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000859 if (Result != MCDisassembler::Fail) {
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000860 Size = 4;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000861 return Result;
Artyom Skrobovc1be9c12013-10-30 18:10:09 +0000862 }
Joey Goulydf686002013-07-17 13:59:38 +0000863 }
864
Sjoerd Meijer7426c972017-08-11 09:52:30 +0000865 Result =
866 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
867 if (Result != MCDisassembler::Fail) {
868 Size = 4;
869 Check(Result, AddThumbPredicate(MI));
870 return Result;
871 }
872
Benjamin Krameraa38dba2011-08-26 18:21:36 +0000873 Size = 0;
James Molloydb4ce602011-09-01 18:02:14 +0000874 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000875}
876
Tom Stellard37457132019-06-10 22:12:56 +0000877extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000878 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
Owen Andersone0152a72011-08-09 20:55:18 +0000879 createARMDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000880 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
Christian Pirker2a111602014-03-28 14:35:30 +0000881 createARMDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000882 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
Christian Pirker2a111602014-03-28 14:35:30 +0000883 createThumbDisassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000884 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
Owen Andersone0152a72011-08-09 20:55:18 +0000885 createThumbDisassembler);
886}
887
Craig Topperca658c22012-03-11 07:16:55 +0000888static const uint16_t GPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +0000889 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
890 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
891 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
892 ARM::R12, ARM::SP, ARM::LR, ARM::PC
893};
894
Craig Topperf6e7e122012-03-27 07:21:54 +0000895static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000896 uint64_t Address, const void *Decoder) {
897 if (RegNo > 15)
James Molloydb4ce602011-09-01 18:02:14 +0000898 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000899
900 unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000901 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +0000902 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +0000903}
904
Owen Anderson03aadae2011-09-01 23:23:50 +0000905static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +0000906DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachd14b70d2011-08-17 21:58:18 +0000907 uint64_t Address, const void *Decoder) {
Silviu Baranga32a49332012-03-20 15:54:56 +0000908 DecodeStatus S = MCDisassembler::Success;
Vinicius Tinti67cf33d2015-11-20 23:20:12 +0000909
Fangrui Songf78650a2018-07-30 19:41:25 +0000910 if (RegNo == 15)
Silviu Baranga32a49332012-03-20 15:54:56 +0000911 S = MCDisassembler::SoftFail;
912
913 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
914
915 return S;
Owen Anderson042619f2011-08-09 22:48:45 +0000916}
917
Mihai Popadc1764c52013-05-13 14:10:04 +0000918static DecodeStatus
919DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address, const void *Decoder) {
921 DecodeStatus S = MCDisassembler::Success;
922
923 if (RegNo == 15)
924 {
Jim Grosbache9119e42015-05-13 18:37:00 +0000925 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popadc1764c52013-05-13 14:10:04 +0000926 return MCDisassembler::Success;
927 }
928
929 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
930 return S;
931}
932
Craig Topperf6e7e122012-03-27 07:21:54 +0000933static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000934 uint64_t Address, const void *Decoder) {
935 if (RegNo > 7)
James Molloydb4ce602011-09-01 18:02:14 +0000936 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000937 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
938}
939
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000940static const uint16_t GPRPairDecoderTable[] = {
941 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
942 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
943};
944
945static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
946 uint64_t Address, const void *Decoder) {
947 DecodeStatus S = MCDisassembler::Success;
948
949 if (RegNo > 13)
950 return MCDisassembler::Fail;
951
952 if ((RegNo & 1) || RegNo == 0xe)
953 S = MCDisassembler::SoftFail;
954
955 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbache9119e42015-05-13 18:37:00 +0000956 Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +0000957 return S;
958}
959
Craig Topperf6e7e122012-03-27 07:21:54 +0000960static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000961 uint64_t Address, const void *Decoder) {
962 unsigned Register = 0;
963 switch (RegNo) {
964 case 0:
965 Register = ARM::R0;
966 break;
967 case 1:
968 Register = ARM::R1;
969 break;
970 case 2:
971 Register = ARM::R2;
972 break;
973 case 3:
974 Register = ARM::R3;
975 break;
976 case 9:
977 Register = ARM::R9;
978 break;
979 case 12:
980 Register = ARM::R12;
981 break;
982 default:
James Molloydb4ce602011-09-01 18:02:14 +0000983 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +0000984 }
985
Jim Grosbache9119e42015-05-13 18:37:00 +0000986 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +0000987 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +0000988}
989
Craig Topperf6e7e122012-03-27 07:21:54 +0000990static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +0000991 uint64_t Address, const void *Decoder) {
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +0000992 DecodeStatus S = MCDisassembler::Success;
Artyom Skrobovb43981072015-10-28 13:58:36 +0000993
994 const FeatureBitset &featureBits =
995 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
996
997 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +0000998 S = MCDisassembler::SoftFail;
Artyom Skrobovb43981072015-10-28 13:58:36 +0000999
Amaury de la Vieuville8175bda2013-06-24 09:14:54 +00001000 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1001 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001002}
1003
Craig Topperca658c22012-03-11 07:16:55 +00001004static const uint16_t SPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +00001005 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1006 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1007 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1008 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1009 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1010 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1011 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1012 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1013};
1014
Craig Topperf6e7e122012-03-27 07:21:54 +00001015static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001016 uint64_t Address, const void *Decoder) {
1017 if (RegNo > 31)
James Molloydb4ce602011-09-01 18:02:14 +00001018 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001019
1020 unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001021 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +00001022 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001023}
1024
Sjoerd Meijer011de9c2018-01-26 09:26:40 +00001025static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1026 uint64_t Address, const void *Decoder) {
1027 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1028}
1029
Craig Topperca658c22012-03-11 07:16:55 +00001030static const uint16_t DPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +00001031 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1032 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1033 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1034 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1035 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1036 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1037 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1038 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1039};
1040
Craig Topperf6e7e122012-03-27 07:21:54 +00001041static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001042 uint64_t Address, const void *Decoder) {
Michael Kupersteindb0712f2015-05-26 10:47:10 +00001043 const FeatureBitset &featureBits =
1044 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1045
Simon Tatham760df472019-05-28 16:13:20 +00001046 bool hasD32 = featureBits[ARM::FeatureD32];
Oliver Stannard9e89d8c2014-11-05 12:06:39 +00001047
Simon Tatham760df472019-05-28 16:13:20 +00001048 if (RegNo > 31 || (!hasD32 && RegNo > 15))
James Molloydb4ce602011-09-01 18:02:14 +00001049 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001050
1051 unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001052 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +00001053 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001054}
1055
Craig Topperf6e7e122012-03-27 07:21:54 +00001056static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001057 uint64_t Address, const void *Decoder) {
1058 if (RegNo > 7)
James Molloydb4ce602011-09-01 18:02:14 +00001059 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001060 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1061}
1062
Diogo N. Sampaioc20c37b2019-03-08 17:11:20 +00001063static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1064 uint64_t Address, const void *Decoder) {
1065 if (RegNo > 15)
1066 return MCDisassembler::Fail;
1067 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1068}
1069
Owen Anderson03aadae2011-09-01 23:23:50 +00001070static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001071DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001072 uint64_t Address, const void *Decoder) {
Owen Andersone0152a72011-08-09 20:55:18 +00001073 if (RegNo > 15)
James Molloydb4ce602011-09-01 18:02:14 +00001074 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001075 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1076}
1077
Craig Topperca658c22012-03-11 07:16:55 +00001078static const uint16_t QPRDecoderTable[] = {
Owen Andersone0152a72011-08-09 20:55:18 +00001079 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1080 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1081 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1082 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1083};
1084
Craig Topperf6e7e122012-03-27 07:21:54 +00001085static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Andersone0152a72011-08-09 20:55:18 +00001086 uint64_t Address, const void *Decoder) {
Mihai Popadcf09222013-05-20 14:42:43 +00001087 if (RegNo > 31 || (RegNo & 1) != 0)
James Molloydb4ce602011-09-01 18:02:14 +00001088 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001089 RegNo >>= 1;
1090
1091 unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001092 Inst.addOperand(MCOperand::createReg(Register));
James Molloydb4ce602011-09-01 18:02:14 +00001093 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001094}
1095
Craig Topperca658c22012-03-11 07:16:55 +00001096static const uint16_t DPairDecoderTable[] = {
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001097 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1098 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1099 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1100 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1101 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1102 ARM::Q15
1103};
1104
Craig Topperf6e7e122012-03-27 07:21:54 +00001105static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001106 uint64_t Address, const void *Decoder) {
1107 if (RegNo > 30)
1108 return MCDisassembler::Fail;
1109
1110 unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001111 Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbachc988e0c2012-03-05 19:33:30 +00001112 return MCDisassembler::Success;
1113}
1114
Craig Topperca658c22012-03-11 07:16:55 +00001115static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbache5307f92012-03-05 21:43:40 +00001116 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1117 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1118 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1119 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1120 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1121 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1122 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1123 ARM::D28_D30, ARM::D29_D31
1124};
1125
Craig Topperf6e7e122012-03-27 07:21:54 +00001126static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbache5307f92012-03-05 21:43:40 +00001127 unsigned RegNo,
1128 uint64_t Address,
1129 const void *Decoder) {
1130 if (RegNo > 29)
1131 return MCDisassembler::Fail;
1132
1133 unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +00001134 Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbache5307f92012-03-05 21:43:40 +00001135 return MCDisassembler::Success;
1136}
1137
Craig Topperf6e7e122012-03-27 07:21:54 +00001138static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001139 uint64_t Address, const void *Decoder) {
Simon Tathamb70fc0c2019-02-25 10:39:53 +00001140 DecodeStatus S = MCDisassembler::Success;
James Molloydb4ce602011-09-01 18:02:14 +00001141 if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson7a2401d2011-08-09 21:07:45 +00001142 // AL predicate is not allowed on Thumb1 branches.
1143 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloydb4ce602011-09-01 18:02:14 +00001144 return MCDisassembler::Fail;
Simon Tathamb70fc0c2019-02-25 10:39:53 +00001145 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1146 Check(S, MCDisassembler::SoftFail);
Jim Grosbache9119e42015-05-13 18:37:00 +00001147 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersone0152a72011-08-09 20:55:18 +00001148 if (Val == ARMCC::AL) {
Jim Grosbache9119e42015-05-13 18:37:00 +00001149 Inst.addOperand(MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +00001150 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00001151 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Simon Tathamb70fc0c2019-02-25 10:39:53 +00001152 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001153}
1154
Craig Topperf6e7e122012-03-27 07:21:54 +00001155static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001156 uint64_t Address, const void *Decoder) {
1157 if (Val)
Jim Grosbache9119e42015-05-13 18:37:00 +00001158 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Andersone0152a72011-08-09 20:55:18 +00001159 else
Jim Grosbache9119e42015-05-13 18:37:00 +00001160 Inst.addOperand(MCOperand::createReg(0));
James Molloydb4ce602011-09-01 18:02:14 +00001161 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001162}
1163
Craig Topperf6e7e122012-03-27 07:21:54 +00001164static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001165 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001166 DecodeStatus S = MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001167
Jim Grosbachecaef492012-08-14 19:06:05 +00001168 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1169 unsigned type = fieldFromInstruction(Val, 5, 2);
1170 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00001171
1172 // Register-immediate
Artyom Skrobovb43981072015-10-28 13:58:36 +00001173 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00001174 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001175
1176 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1177 switch (type) {
1178 case 0:
1179 Shift = ARM_AM::lsl;
1180 break;
1181 case 1:
1182 Shift = ARM_AM::lsr;
1183 break;
1184 case 2:
1185 Shift = ARM_AM::asr;
1186 break;
1187 case 3:
1188 Shift = ARM_AM::ror;
1189 break;
1190 }
1191
1192 if (Shift == ARM_AM::ror && imm == 0)
1193 Shift = ARM_AM::rrx;
1194
1195 unsigned Op = Shift | (imm << 3);
Jim Grosbache9119e42015-05-13 18:37:00 +00001196 Inst.addOperand(MCOperand::createImm(Op));
Owen Andersone0152a72011-08-09 20:55:18 +00001197
Owen Andersona4043c42011-08-17 17:44:15 +00001198 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001199}
1200
Craig Topperf6e7e122012-03-27 07:21:54 +00001201static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001202 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001203 DecodeStatus S = MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00001204
Jim Grosbachecaef492012-08-14 19:06:05 +00001205 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1206 unsigned type = fieldFromInstruction(Val, 5, 2);
1207 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00001208
1209 // Register-register
Owen Anderson03aadae2011-09-01 23:23:50 +00001210 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1211 return MCDisassembler::Fail;
1212 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1213 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001214
1215 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1216 switch (type) {
1217 case 0:
1218 Shift = ARM_AM::lsl;
1219 break;
1220 case 1:
1221 Shift = ARM_AM::lsr;
1222 break;
1223 case 2:
1224 Shift = ARM_AM::asr;
1225 break;
1226 case 3:
1227 Shift = ARM_AM::ror;
1228 break;
1229 }
1230
Jim Grosbache9119e42015-05-13 18:37:00 +00001231 Inst.addOperand(MCOperand::createImm(Shift));
Owen Andersone0152a72011-08-09 20:55:18 +00001232
Owen Andersona4043c42011-08-17 17:44:15 +00001233 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001234}
1235
Craig Topperf6e7e122012-03-27 07:21:54 +00001236static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001237 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001238 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001239
Tim Northover08a86602013-10-22 19:00:39 +00001240 bool NeedDisjointWriteback = false;
1241 unsigned WritebackReg = 0;
Owen Anderson53db43b2011-09-09 23:13:33 +00001242 switch (Inst.getOpcode()) {
Tim Northover08a86602013-10-22 19:00:39 +00001243 default:
1244 break;
1245 case ARM::LDMIA_UPD:
1246 case ARM::LDMDB_UPD:
1247 case ARM::LDMIB_UPD:
1248 case ARM::LDMDA_UPD:
1249 case ARM::t2LDMIA_UPD:
1250 case ARM::t2LDMDB_UPD:
1251 case ARM::t2STMIA_UPD:
1252 case ARM::t2STMDB_UPD:
1253 NeedDisjointWriteback = true;
1254 WritebackReg = Inst.getOperand(0).getReg();
1255 break;
Owen Anderson53db43b2011-09-09 23:13:33 +00001256 }
1257
Owen Anderson60663402011-08-11 20:21:46 +00001258 // Empty register lists are not allowed.
Benjamin Kramer8bad66e2013-05-19 22:01:57 +00001259 if (Val == 0) return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001260 for (unsigned i = 0; i < 16; ++i) {
Owen Andersoned253852011-08-11 18:24:51 +00001261 if (Val & (1 << i)) {
Simon Tatham67065c52019-06-10 15:58:19 +00001262 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1263 return MCDisassembler::Fail;
1264 // Writeback not allowed if Rn is in the target list.
1265 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1266 Check(S, MCDisassembler::SoftFail);
Owen Andersoned253852011-08-11 18:24:51 +00001267 }
Owen Andersone0152a72011-08-09 20:55:18 +00001268 }
1269
Owen Andersona4043c42011-08-17 17:44:15 +00001270 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001271}
1272
Craig Topperf6e7e122012-03-27 07:21:54 +00001273static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001274 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001275 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001276
Jim Grosbachecaef492012-08-14 19:06:05 +00001277 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1278 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00001279
Tim Northover4173e292013-05-31 15:55:51 +00001280 // In case of unpredictable encoding, tweak the operands.
1281 if (regs == 0 || (Vd + regs) > 32) {
1282 regs = Vd + regs > 32 ? 32 - Vd : regs;
1283 regs = std::max( 1u, regs);
1284 S = MCDisassembler::SoftFail;
1285 }
1286
Owen Anderson03aadae2011-09-01 23:23:50 +00001287 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1288 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001289 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001290 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1291 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001292 }
Owen Andersone0152a72011-08-09 20:55:18 +00001293
Owen Andersona4043c42011-08-17 17:44:15 +00001294 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001295}
1296
Craig Topperf6e7e122012-03-27 07:21:54 +00001297static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001298 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001299 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001300
Jim Grosbachecaef492012-08-14 19:06:05 +00001301 unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover4173e292013-05-31 15:55:51 +00001302 unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga9560af82012-05-03 16:38:40 +00001303
Tim Northover4173e292013-05-31 15:55:51 +00001304 // In case of unpredictable encoding, tweak the operands.
1305 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1306 regs = Vd + regs > 32 ? 32 - Vd : regs;
1307 regs = std::max( 1u, regs);
1308 regs = std::min(16u, regs);
1309 S = MCDisassembler::SoftFail;
1310 }
Owen Andersone0152a72011-08-09 20:55:18 +00001311
Owen Anderson03aadae2011-09-01 23:23:50 +00001312 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1313 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001314 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001315 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1316 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00001317 }
Owen Andersone0152a72011-08-09 20:55:18 +00001318
Owen Andersona4043c42011-08-17 17:44:15 +00001319 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001320}
1321
Craig Topperf6e7e122012-03-27 07:21:54 +00001322static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001323 uint64_t Address, const void *Decoder) {
Owen Anderson5d69f632011-08-10 17:36:48 +00001324 // This operand encodes a mask of contiguous zeros between a specified MSB
1325 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1326 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001327 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson5d69f632011-08-10 17:36:48 +00001328 // create the final mask.
Jim Grosbachecaef492012-08-14 19:06:05 +00001329 unsigned msb = fieldFromInstruction(Val, 5, 5);
1330 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson3ca958c2011-09-16 22:29:48 +00001331
Owen Anderson502cd9d2011-09-16 23:30:01 +00001332 DecodeStatus S = MCDisassembler::Success;
Kevin Enderby136d6742012-11-29 23:47:11 +00001333 if (lsb > msb) {
1334 Check(S, MCDisassembler::SoftFail);
1335 // The check above will cause the warning for the "potentially undefined
1336 // instruction encoding" but we can't build a bad MCOperand value here
1337 // with a lsb > msb or else printing the MCInst will cause a crash.
1338 lsb = msb;
1339 }
Owen Anderson502cd9d2011-09-16 23:30:01 +00001340
Owen Andersonb925e932011-09-16 23:04:48 +00001341 uint32_t msb_mask = 0xFFFFFFFF;
1342 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1343 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson3ca958c2011-09-16 22:29:48 +00001344
Jim Grosbache9119e42015-05-13 18:37:00 +00001345 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson502cd9d2011-09-16 23:30:01 +00001346 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001347}
1348
Craig Topperf6e7e122012-03-27 07:21:54 +00001349static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00001350 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001351 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001352
Jim Grosbachecaef492012-08-14 19:06:05 +00001353 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1354 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1355 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1356 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1357 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1358 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001359
1360 switch (Inst.getOpcode()) {
1361 case ARM::LDC_OFFSET:
1362 case ARM::LDC_PRE:
1363 case ARM::LDC_POST:
1364 case ARM::LDC_OPTION:
1365 case ARM::LDCL_OFFSET:
1366 case ARM::LDCL_PRE:
1367 case ARM::LDCL_POST:
1368 case ARM::LDCL_OPTION:
1369 case ARM::STC_OFFSET:
1370 case ARM::STC_PRE:
1371 case ARM::STC_POST:
1372 case ARM::STC_OPTION:
1373 case ARM::STCL_OFFSET:
1374 case ARM::STCL_PRE:
1375 case ARM::STCL_POST:
1376 case ARM::STCL_OPTION:
Owen Anderson18d17aa2011-09-07 21:10:42 +00001377 case ARM::t2LDC_OFFSET:
1378 case ARM::t2LDC_PRE:
1379 case ARM::t2LDC_POST:
1380 case ARM::t2LDC_OPTION:
1381 case ARM::t2LDCL_OFFSET:
1382 case ARM::t2LDCL_PRE:
1383 case ARM::t2LDCL_POST:
1384 case ARM::t2LDCL_OPTION:
1385 case ARM::t2STC_OFFSET:
1386 case ARM::t2STC_PRE:
1387 case ARM::t2STC_POST:
1388 case ARM::t2STC_OPTION:
1389 case ARM::t2STCL_OFFSET:
1390 case ARM::t2STCL_PRE:
1391 case ARM::t2STCL_POST:
1392 case ARM::t2STCL_OPTION:
Simon Tatham67065c52019-06-10 15:58:19 +00001393 if (coproc == 0xA || coproc == 0xB)
James Molloydb4ce602011-09-01 18:02:14 +00001394 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001395 break;
1396 default:
1397 break;
1398 }
1399
Simon Tatham67065c52019-06-10 15:58:19 +00001400 const FeatureBitset &featureBits =
1401 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
Michael Kupersteindb0712f2015-05-26 10:47:10 +00001402 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobove686cec2013-11-08 16:16:30 +00001403 return MCDisassembler::Fail;
1404
Jim Grosbache9119e42015-05-13 18:37:00 +00001405 Inst.addOperand(MCOperand::createImm(coproc));
1406 Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson03aadae2011-09-01 23:23:50 +00001407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1408 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001409
Owen Andersone0152a72011-08-09 20:55:18 +00001410 switch (Inst.getOpcode()) {
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001411 case ARM::t2LDC2_OFFSET:
1412 case ARM::t2LDC2L_OFFSET:
1413 case ARM::t2LDC2_PRE:
1414 case ARM::t2LDC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001415 case ARM::t2STC2_OFFSET:
1416 case ARM::t2STC2L_OFFSET:
1417 case ARM::t2STC2_PRE:
1418 case ARM::t2STC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001419 case ARM::LDC2_OFFSET:
1420 case ARM::LDC2L_OFFSET:
1421 case ARM::LDC2_PRE:
1422 case ARM::LDC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001423 case ARM::STC2_OFFSET:
1424 case ARM::STC2L_OFFSET:
1425 case ARM::STC2_PRE:
1426 case ARM::STC2L_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001427 case ARM::t2LDC_OFFSET:
1428 case ARM::t2LDCL_OFFSET:
1429 case ARM::t2LDC_PRE:
1430 case ARM::t2LDCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001431 case ARM::t2STC_OFFSET:
1432 case ARM::t2STCL_OFFSET:
1433 case ARM::t2STC_PRE:
1434 case ARM::t2STCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001435 case ARM::LDC_OFFSET:
1436 case ARM::LDCL_OFFSET:
1437 case ARM::LDC_PRE:
1438 case ARM::LDCL_PRE:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001439 case ARM::STC_OFFSET:
1440 case ARM::STCL_OFFSET:
1441 case ARM::STC_PRE:
1442 case ARM::STCL_PRE:
Jim Grosbacha098a892011-10-12 21:59:02 +00001443 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbache9119e42015-05-13 18:37:00 +00001444 Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbacha098a892011-10-12 21:59:02 +00001445 break;
1446 case ARM::t2LDC2_POST:
1447 case ARM::t2LDC2L_POST:
1448 case ARM::t2STC2_POST:
1449 case ARM::t2STC2L_POST:
1450 case ARM::LDC2_POST:
1451 case ARM::LDC2L_POST:
1452 case ARM::STC2_POST:
1453 case ARM::STC2L_POST:
1454 case ARM::t2LDC_POST:
1455 case ARM::t2LDCL_POST:
1456 case ARM::t2STC_POST:
1457 case ARM::t2STCL_POST:
1458 case ARM::LDC_POST:
1459 case ARM::LDCL_POST:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001460 case ARM::STC_POST:
1461 case ARM::STCL_POST:
Owen Andersone0152a72011-08-09 20:55:18 +00001462 imm |= U << 8;
Justin Bognercd1d5aa2016-08-17 20:30:52 +00001463 LLVM_FALLTHROUGH;
Owen Andersone0152a72011-08-09 20:55:18 +00001464 default:
Jim Grosbach54a20ed2011-10-12 20:54:17 +00001465 // The 'option' variant doesn't encode 'U' in the immediate since
1466 // the immediate is unsigned [0,255].
Jim Grosbache9119e42015-05-13 18:37:00 +00001467 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00001468 break;
1469 }
1470
1471 switch (Inst.getOpcode()) {
1472 case ARM::LDC_OFFSET:
1473 case ARM::LDC_PRE:
1474 case ARM::LDC_POST:
1475 case ARM::LDC_OPTION:
1476 case ARM::LDCL_OFFSET:
1477 case ARM::LDCL_PRE:
1478 case ARM::LDCL_POST:
1479 case ARM::LDCL_OPTION:
1480 case ARM::STC_OFFSET:
1481 case ARM::STC_PRE:
1482 case ARM::STC_POST:
1483 case ARM::STC_OPTION:
1484 case ARM::STCL_OFFSET:
1485 case ARM::STCL_PRE:
1486 case ARM::STCL_POST:
1487 case ARM::STCL_OPTION:
Owen Anderson03aadae2011-09-01 23:23:50 +00001488 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1489 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001490 break;
1491 default:
1492 break;
1493 }
1494
Owen Andersona4043c42011-08-17 17:44:15 +00001495 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001496}
1497
Owen Anderson03aadae2011-09-01 23:23:50 +00001498static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001499DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001500 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001501 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001502
Jim Grosbachecaef492012-08-14 19:06:05 +00001503 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1504 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1505 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1506 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1507 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1508 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1509 unsigned P = fieldFromInstruction(Insn, 24, 1);
1510 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001511
1512 // On stores, the writeback operand precedes Rt.
1513 switch (Inst.getOpcode()) {
1514 case ARM::STR_POST_IMM:
1515 case ARM::STR_POST_REG:
Owen Anderson3a850f22011-08-11 20:47:56 +00001516 case ARM::STRB_POST_IMM:
1517 case ARM::STRB_POST_REG:
Jim Grosbache2594212011-08-11 22:18:00 +00001518 case ARM::STRT_POST_REG:
1519 case ARM::STRT_POST_IMM:
Jim Grosbach2a502602011-08-11 20:04:56 +00001520 case ARM::STRBT_POST_REG:
1521 case ARM::STRBT_POST_IMM:
Owen Anderson03aadae2011-09-01 23:23:50 +00001522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1523 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001524 break;
1525 default:
1526 break;
1527 }
1528
Owen Anderson03aadae2011-09-01 23:23:50 +00001529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1530 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001531
1532 // On loads, the writeback operand comes after Rt.
1533 switch (Inst.getOpcode()) {
1534 case ARM::LDR_POST_IMM:
1535 case ARM::LDR_POST_REG:
Owen Anderson3a850f22011-08-11 20:47:56 +00001536 case ARM::LDRB_POST_IMM:
1537 case ARM::LDRB_POST_REG:
Owen Andersone0152a72011-08-09 20:55:18 +00001538 case ARM::LDRBT_POST_REG:
1539 case ARM::LDRBT_POST_IMM:
Jim Grosbachd5d63592011-08-10 23:43:54 +00001540 case ARM::LDRT_POST_REG:
1541 case ARM::LDRT_POST_IMM:
Owen Anderson03aadae2011-09-01 23:23:50 +00001542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1543 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001544 break;
1545 default:
1546 break;
1547 }
1548
Owen Anderson03aadae2011-09-01 23:23:50 +00001549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1550 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001551
1552 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachecaef492012-08-14 19:06:05 +00001553 if (!fieldFromInstruction(Insn, 23, 1))
Owen Andersone0152a72011-08-09 20:55:18 +00001554 Op = ARM_AM::sub;
1555
1556 bool writeback = (P == 0) || (W == 1);
1557 unsigned idx_mode = 0;
1558 if (P && writeback)
1559 idx_mode = ARMII::IndexModePre;
1560 else if (!P && writeback)
1561 idx_mode = ARMII::IndexModePost;
1562
Owen Anderson03aadae2011-09-01 23:23:50 +00001563 if (writeback && (Rn == 15 || Rn == Rt))
1564 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson3477f2c2011-08-11 19:00:18 +00001565
Owen Andersone0152a72011-08-09 20:55:18 +00001566 if (reg) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001567 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1568 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001569 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachecaef492012-08-14 19:06:05 +00001570 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Andersone0152a72011-08-09 20:55:18 +00001571 case 0:
1572 Opc = ARM_AM::lsl;
1573 break;
1574 case 1:
1575 Opc = ARM_AM::lsr;
1576 break;
1577 case 2:
1578 Opc = ARM_AM::asr;
1579 break;
1580 case 3:
1581 Opc = ARM_AM::ror;
1582 break;
1583 default:
James Molloydb4ce602011-09-01 18:02:14 +00001584 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001585 }
Jim Grosbachecaef492012-08-14 19:06:05 +00001586 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover0c97e762012-09-22 11:18:12 +00001587 if (Opc == ARM_AM::ror && amt == 0)
1588 Opc = ARM_AM::rrx;
Owen Andersone0152a72011-08-09 20:55:18 +00001589 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1590
Jim Grosbache9119e42015-05-13 18:37:00 +00001591 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00001592 } else {
Jim Grosbache9119e42015-05-13 18:37:00 +00001593 Inst.addOperand(MCOperand::createReg(0));
Owen Andersone0152a72011-08-09 20:55:18 +00001594 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbache9119e42015-05-13 18:37:00 +00001595 Inst.addOperand(MCOperand::createImm(tmp));
Owen Andersone0152a72011-08-09 20:55:18 +00001596 }
1597
Owen Anderson03aadae2011-09-01 23:23:50 +00001598 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1599 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001600
Owen Andersona4043c42011-08-17 17:44:15 +00001601 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001602}
1603
Craig Topperf6e7e122012-03-27 07:21:54 +00001604static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00001605 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001606 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001607
Jim Grosbachecaef492012-08-14 19:06:05 +00001608 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1609 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1610 unsigned type = fieldFromInstruction(Val, 5, 2);
1611 unsigned imm = fieldFromInstruction(Val, 7, 5);
1612 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00001613
Owen Andersond151b092011-08-09 21:38:14 +00001614 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Andersone0152a72011-08-09 20:55:18 +00001615 switch (type) {
1616 case 0:
1617 ShOp = ARM_AM::lsl;
1618 break;
1619 case 1:
1620 ShOp = ARM_AM::lsr;
1621 break;
1622 case 2:
1623 ShOp = ARM_AM::asr;
1624 break;
1625 case 3:
1626 ShOp = ARM_AM::ror;
1627 break;
1628 }
1629
Tim Northover0c97e762012-09-22 11:18:12 +00001630 if (ShOp == ARM_AM::ror && imm == 0)
1631 ShOp = ARM_AM::rrx;
1632
Owen Anderson03aadae2011-09-01 23:23:50 +00001633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1634 return MCDisassembler::Fail;
1635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1636 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001637 unsigned shift;
1638 if (U)
1639 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1640 else
1641 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbache9119e42015-05-13 18:37:00 +00001642 Inst.addOperand(MCOperand::createImm(shift));
Owen Andersone0152a72011-08-09 20:55:18 +00001643
Owen Andersona4043c42011-08-17 17:44:15 +00001644 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001645}
1646
Owen Anderson03aadae2011-09-01 23:23:50 +00001647static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00001648DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00001649 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001650 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001651
Jim Grosbachecaef492012-08-14 19:06:05 +00001652 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1653 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1654 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1655 unsigned type = fieldFromInstruction(Insn, 22, 1);
1656 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1657 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1658 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1659 unsigned W = fieldFromInstruction(Insn, 21, 1);
1660 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001661 unsigned Rt2 = Rt + 1;
Owen Andersone0152a72011-08-09 20:55:18 +00001662
1663 bool writeback = (W == 1) | (P == 0);
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001664
1665 // For {LD,ST}RD, Rt must be even, else undefined.
1666 switch (Inst.getOpcode()) {
1667 case ARM::STRD:
1668 case ARM::STRD_PRE:
1669 case ARM::STRD_POST:
1670 case ARM::LDRD:
1671 case ARM::LDRD_PRE:
1672 case ARM::LDRD_POST:
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001673 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1674 break;
1675 default:
1676 break;
1677 }
1678 switch (Inst.getOpcode()) {
1679 case ARM::STRD:
1680 case ARM::STRD_PRE:
1681 case ARM::STRD_POST:
1682 if (P == 0 && W == 1)
1683 S = MCDisassembler::SoftFail;
Vinicius Tinti67cf33d2015-11-20 23:20:12 +00001684
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001685 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1686 S = MCDisassembler::SoftFail;
1687 if (type && Rm == 15)
1688 S = MCDisassembler::SoftFail;
1689 if (Rt2 == 15)
1690 S = MCDisassembler::SoftFail;
Jim Grosbachecaef492012-08-14 19:06:05 +00001691 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001692 S = MCDisassembler::SoftFail;
1693 break;
1694 case ARM::STRH:
1695 case ARM::STRH_PRE:
1696 case ARM::STRH_POST:
1697 if (Rt == 15)
1698 S = MCDisassembler::SoftFail;
1699 if (writeback && (Rn == 15 || Rn == Rt))
1700 S = MCDisassembler::SoftFail;
1701 if (!type && Rm == 15)
1702 S = MCDisassembler::SoftFail;
1703 break;
1704 case ARM::LDRD:
1705 case ARM::LDRD_PRE:
1706 case ARM::LDRD_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001707 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001708 if (Rt2 == 15)
1709 S = MCDisassembler::SoftFail;
1710 break;
1711 }
1712 if (P == 0 && W == 1)
1713 S = MCDisassembler::SoftFail;
1714 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1715 S = MCDisassembler::SoftFail;
1716 if (!type && writeback && Rn == 15)
1717 S = MCDisassembler::SoftFail;
1718 if (writeback && (Rn == Rt || Rn == Rt2))
1719 S = MCDisassembler::SoftFail;
1720 break;
1721 case ARM::LDRH:
1722 case ARM::LDRH_PRE:
1723 case ARM::LDRH_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001724 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001725 if (Rt == 15)
1726 S = MCDisassembler::SoftFail;
1727 break;
1728 }
1729 if (Rt == 15)
1730 S = MCDisassembler::SoftFail;
1731 if (!type && Rm == 15)
1732 S = MCDisassembler::SoftFail;
1733 if (!type && writeback && (Rn == 15 || Rn == Rt))
1734 S = MCDisassembler::SoftFail;
1735 break;
1736 case ARM::LDRSH:
1737 case ARM::LDRSH_PRE:
1738 case ARM::LDRSH_POST:
1739 case ARM::LDRSB:
1740 case ARM::LDRSB_PRE:
1741 case ARM::LDRSB_POST:
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00001742 if (type && Rn == 15) {
Silviu Baranga4afd7d22012-03-22 14:14:49 +00001743 if (Rt == 15)
1744 S = MCDisassembler::SoftFail;
1745 break;
1746 }
1747 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1748 S = MCDisassembler::SoftFail;
1749 if (!type && (Rt == 15 || Rm == 15))
1750 S = MCDisassembler::SoftFail;
1751 if (!type && writeback && (Rn == 15 || Rn == Rt))
1752 S = MCDisassembler::SoftFail;
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001753 break;
Owen Anderson03aadae2011-09-01 23:23:50 +00001754 default:
1755 break;
Owen Anderson1d5d2ca2011-08-15 20:51:32 +00001756 }
1757
Owen Andersone0152a72011-08-09 20:55:18 +00001758 if (writeback) { // Writeback
1759 if (P)
1760 U |= ARMII::IndexModePre << 9;
1761 else
1762 U |= ARMII::IndexModePost << 9;
1763
1764 // On stores, the writeback operand precedes Rt.
1765 switch (Inst.getOpcode()) {
1766 case ARM::STRD:
1767 case ARM::STRD_PRE:
1768 case ARM::STRD_POST:
Owen Anderson60138ea2011-08-12 20:02:50 +00001769 case ARM::STRH:
1770 case ARM::STRH_PRE:
1771 case ARM::STRH_POST:
Owen Anderson03aadae2011-09-01 23:23:50 +00001772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1773 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001774 break;
1775 default:
1776 break;
1777 }
1778 }
1779
Owen Anderson03aadae2011-09-01 23:23:50 +00001780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1781 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001782 switch (Inst.getOpcode()) {
1783 case ARM::STRD:
1784 case ARM::STRD_PRE:
1785 case ARM::STRD_POST:
1786 case ARM::LDRD:
1787 case ARM::LDRD_PRE:
1788 case ARM::LDRD_POST:
Owen Anderson03aadae2011-09-01 23:23:50 +00001789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1790 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001791 break;
1792 default:
1793 break;
1794 }
1795
1796 if (writeback) {
1797 // On loads, the writeback operand comes after Rt.
1798 switch (Inst.getOpcode()) {
1799 case ARM::LDRD:
1800 case ARM::LDRD_PRE:
1801 case ARM::LDRD_POST:
Owen Anderson2d1d7a12011-08-12 20:36:11 +00001802 case ARM::LDRH:
1803 case ARM::LDRH_PRE:
1804 case ARM::LDRH_POST:
1805 case ARM::LDRSH:
1806 case ARM::LDRSH_PRE:
1807 case ARM::LDRSH_POST:
1808 case ARM::LDRSB:
1809 case ARM::LDRSB_PRE:
1810 case ARM::LDRSB_POST:
Owen Andersone0152a72011-08-09 20:55:18 +00001811 case ARM::LDRHTr:
1812 case ARM::LDRSBTr:
Owen Anderson03aadae2011-09-01 23:23:50 +00001813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1814 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001815 break;
1816 default:
1817 break;
1818 }
1819 }
1820
Owen Anderson03aadae2011-09-01 23:23:50 +00001821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1822 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001823
1824 if (type) {
Jim Grosbache9119e42015-05-13 18:37:00 +00001825 Inst.addOperand(MCOperand::createReg(0));
1826 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
Owen Andersone0152a72011-08-09 20:55:18 +00001827 } else {
Owen Anderson03aadae2011-09-01 23:23:50 +00001828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1829 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00001830 Inst.addOperand(MCOperand::createImm(U));
Owen Andersone0152a72011-08-09 20:55:18 +00001831 }
1832
Owen Anderson03aadae2011-09-01 23:23:50 +00001833 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1834 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001835
Owen Andersona4043c42011-08-17 17:44:15 +00001836 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001837}
1838
Craig Topperf6e7e122012-03-27 07:21:54 +00001839static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00001840 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001841 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001842
Jim Grosbachecaef492012-08-14 19:06:05 +00001843 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1844 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00001845
1846 switch (mode) {
1847 case 0:
1848 mode = ARM_AM::da;
1849 break;
1850 case 1:
1851 mode = ARM_AM::ia;
1852 break;
1853 case 2:
1854 mode = ARM_AM::db;
1855 break;
1856 case 3:
1857 mode = ARM_AM::ib;
1858 break;
1859 }
1860
Jim Grosbache9119e42015-05-13 18:37:00 +00001861 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson03aadae2011-09-01 23:23:50 +00001862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001864
Owen Andersona4043c42011-08-17 17:44:15 +00001865 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001866}
1867
Amaury de la Vieuville631df632013-06-08 13:38:52 +00001868static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1869 uint64_t Address, const void *Decoder) {
1870 DecodeStatus S = MCDisassembler::Success;
1871
1872 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1873 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1874 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1875 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1876
1877 if (pred == 0xF)
1878 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1879
1880 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1881 return MCDisassembler::Fail;
1882 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1883 return MCDisassembler::Fail;
1884 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1885 return MCDisassembler::Fail;
1886 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1887 return MCDisassembler::Fail;
1888 return S;
1889}
1890
Craig Topperf6e7e122012-03-27 07:21:54 +00001891static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Andersone0152a72011-08-09 20:55:18 +00001892 unsigned Insn,
1893 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00001894 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00001895
Jim Grosbachecaef492012-08-14 19:06:05 +00001896 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1897 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1898 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Andersone0152a72011-08-09 20:55:18 +00001899
1900 if (pred == 0xF) {
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001901 // Ambiguous with RFE and SRS
Owen Andersone0152a72011-08-09 20:55:18 +00001902 switch (Inst.getOpcode()) {
Owen Anderson192a7602011-08-18 22:31:17 +00001903 case ARM::LDMDA:
Owen Andersone0152a72011-08-09 20:55:18 +00001904 Inst.setOpcode(ARM::RFEDA);
1905 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001906 case ARM::LDMDA_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001907 Inst.setOpcode(ARM::RFEDA_UPD);
1908 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001909 case ARM::LDMDB:
Owen Andersone0152a72011-08-09 20:55:18 +00001910 Inst.setOpcode(ARM::RFEDB);
1911 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001912 case ARM::LDMDB_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001913 Inst.setOpcode(ARM::RFEDB_UPD);
1914 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001915 case ARM::LDMIA:
Owen Andersone0152a72011-08-09 20:55:18 +00001916 Inst.setOpcode(ARM::RFEIA);
1917 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001918 case ARM::LDMIA_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001919 Inst.setOpcode(ARM::RFEIA_UPD);
1920 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001921 case ARM::LDMIB:
Owen Andersone0152a72011-08-09 20:55:18 +00001922 Inst.setOpcode(ARM::RFEIB);
1923 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001924 case ARM::LDMIB_UPD:
Owen Andersone0152a72011-08-09 20:55:18 +00001925 Inst.setOpcode(ARM::RFEIB_UPD);
1926 break;
Owen Anderson192a7602011-08-18 22:31:17 +00001927 case ARM::STMDA:
1928 Inst.setOpcode(ARM::SRSDA);
1929 break;
1930 case ARM::STMDA_UPD:
1931 Inst.setOpcode(ARM::SRSDA_UPD);
1932 break;
1933 case ARM::STMDB:
1934 Inst.setOpcode(ARM::SRSDB);
1935 break;
1936 case ARM::STMDB_UPD:
1937 Inst.setOpcode(ARM::SRSDB_UPD);
1938 break;
1939 case ARM::STMIA:
1940 Inst.setOpcode(ARM::SRSIA);
1941 break;
1942 case ARM::STMIA_UPD:
1943 Inst.setOpcode(ARM::SRSIA_UPD);
1944 break;
1945 case ARM::STMIB:
1946 Inst.setOpcode(ARM::SRSIB);
1947 break;
1948 case ARM::STMIB_UPD:
1949 Inst.setOpcode(ARM::SRSIB_UPD);
1950 break;
1951 default:
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001952 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001953 }
Owen Anderson192a7602011-08-18 22:31:17 +00001954
1955 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachecaef492012-08-14 19:06:05 +00001956 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville68bcd022013-06-08 13:43:59 +00001957 // Check SRS encoding constraints
1958 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1959 fieldFromInstruction(Insn, 20, 1) == 0))
1960 return MCDisassembler::Fail;
1961
Owen Anderson192a7602011-08-18 22:31:17 +00001962 Inst.addOperand(
Jim Grosbache9119e42015-05-13 18:37:00 +00001963 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson192a7602011-08-18 22:31:17 +00001964 return S;
1965 }
1966
Owen Andersone0152a72011-08-09 20:55:18 +00001967 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1968 }
1969
Owen Anderson03aadae2011-09-01 23:23:50 +00001970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1971 return MCDisassembler::Fail;
1972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1973 return MCDisassembler::Fail; // Tied
1974 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1975 return MCDisassembler::Fail;
1976 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1977 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00001978
Owen Andersona4043c42011-08-17 17:44:15 +00001979 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00001980}
1981
Sjoerd Meijerd906bf12016-06-03 14:03:27 +00001982// Check for UNPREDICTABLE predicated ESB instruction
1983static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1984 uint64_t Address, const void *Decoder) {
1985 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1986 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1987 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1988 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1989
1990 DecodeStatus S = MCDisassembler::Success;
1991
1992 Inst.addOperand(MCOperand::createImm(imm8));
1993
1994 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1995 return MCDisassembler::Fail;
1996
1997 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1998 // so all predicates should be allowed.
1999 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2000 S = MCDisassembler::SoftFail;
2001
2002 return S;
2003}
2004
Craig Topperf6e7e122012-03-27 07:21:54 +00002005static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002006 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00002007 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2008 unsigned M = fieldFromInstruction(Insn, 17, 1);
2009 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2010 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00002011
Owen Anderson03aadae2011-09-01 23:23:50 +00002012 DecodeStatus S = MCDisassembler::Success;
Owen Anderson3d2e0e9d2011-08-09 23:05:39 +00002013
Amaury de la Vieuville631df632013-06-08 13:38:52 +00002014 // This decoder is called from multiple location that do not check
2015 // the full encoding is valid before they do.
2016 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2017 fieldFromInstruction(Insn, 16, 1) != 0 ||
2018 fieldFromInstruction(Insn, 20, 8) != 0x10)
2019 return MCDisassembler::Fail;
2020
Owen Anderson67d6f112011-08-18 22:11:02 +00002021 // imod == '01' --> UNPREDICTABLE
2022 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2023 // return failure here. The '01' imod value is unprintable, so there's
2024 // nothing useful we could do even if we returned UNPREDICTABLE.
2025
James Molloydb4ce602011-09-01 18:02:14 +00002026 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson67d6f112011-08-18 22:11:02 +00002027
2028 if (imod && M) {
Owen Andersone0152a72011-08-09 20:55:18 +00002029 Inst.setOpcode(ARM::CPS3p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002030 Inst.addOperand(MCOperand::createImm(imod));
2031 Inst.addOperand(MCOperand::createImm(iflags));
2032 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson67d6f112011-08-18 22:11:02 +00002033 } else if (imod && !M) {
Owen Andersone0152a72011-08-09 20:55:18 +00002034 Inst.setOpcode(ARM::CPS2p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002035 Inst.addOperand(MCOperand::createImm(imod));
2036 Inst.addOperand(MCOperand::createImm(iflags));
James Molloydb4ce602011-09-01 18:02:14 +00002037 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson67d6f112011-08-18 22:11:02 +00002038 } else if (!imod && M) {
Owen Andersone0152a72011-08-09 20:55:18 +00002039 Inst.setOpcode(ARM::CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002040 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002041 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson5d2db892011-08-18 22:15:25 +00002042 } else {
Owen Anderson67d6f112011-08-18 22:11:02 +00002043 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson5d2db892011-08-18 22:15:25 +00002044 Inst.setOpcode(ARM::CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002045 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002046 S = MCDisassembler::SoftFail;
Owen Anderson5d2db892011-08-18 22:15:25 +00002047 }
Owen Andersone0152a72011-08-09 20:55:18 +00002048
Owen Anderson67d6f112011-08-18 22:11:02 +00002049 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002050}
2051
Craig Topperf6e7e122012-03-27 07:21:54 +00002052static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson9b7bd152011-08-23 17:45:18 +00002053 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00002054 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2055 unsigned M = fieldFromInstruction(Insn, 8, 1);
2056 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2057 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson9b7bd152011-08-23 17:45:18 +00002058
Owen Anderson03aadae2011-09-01 23:23:50 +00002059 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002060
2061 // imod == '01' --> UNPREDICTABLE
2062 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2063 // return failure here. The '01' imod value is unprintable, so there's
2064 // nothing useful we could do even if we returned UNPREDICTABLE.
2065
James Molloydb4ce602011-09-01 18:02:14 +00002066 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002067
2068 if (imod && M) {
2069 Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002070 Inst.addOperand(MCOperand::createImm(imod));
2071 Inst.addOperand(MCOperand::createImm(iflags));
2072 Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson9b7bd152011-08-23 17:45:18 +00002073 } else if (imod && !M) {
2074 Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002075 Inst.addOperand(MCOperand::createImm(imod));
2076 Inst.addOperand(MCOperand::createImm(iflags));
James Molloydb4ce602011-09-01 18:02:14 +00002077 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002078 } else if (!imod && M) {
2079 Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbache9119e42015-05-13 18:37:00 +00002080 Inst.addOperand(MCOperand::createImm(mode));
James Molloydb4ce602011-09-01 18:02:14 +00002081 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson9b7bd152011-08-23 17:45:18 +00002082 } else {
Quentin Colombeta83d5e92013-04-26 17:54:54 +00002083 // imod == '00' && M == '0' --> this is a HINT instruction
2084 int imm = fieldFromInstruction(Insn, 0, 8);
2085 // HINT are defined only for immediate in [0..4]
2086 if(imm > 4) return MCDisassembler::Fail;
2087 Inst.setOpcode(ARM::t2HINT);
Jim Grosbache9119e42015-05-13 18:37:00 +00002088 Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson9b7bd152011-08-23 17:45:18 +00002089 }
2090
2091 return S;
2092}
2093
Craig Topperf6e7e122012-03-27 07:21:54 +00002094static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +00002095 uint64_t Address, const void *Decoder) {
2096 DecodeStatus S = MCDisassembler::Success;
2097
Jim Grosbachecaef492012-08-14 19:06:05 +00002098 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002099 unsigned imm = 0;
2100
Jim Grosbachecaef492012-08-14 19:06:05 +00002101 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2102 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2103 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2104 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002105
2106 if (Inst.getOpcode() == ARM::t2MOVTi16)
2107 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2108 return MCDisassembler::Fail;
2109 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2110 return MCDisassembler::Fail;
2111
2112 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002113 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002114
2115 return S;
2116}
2117
Craig Topperf6e7e122012-03-27 07:21:54 +00002118static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby5dcda642011-10-04 22:44:48 +00002119 uint64_t Address, const void *Decoder) {
2120 DecodeStatus S = MCDisassembler::Success;
2121
Jim Grosbachecaef492012-08-14 19:06:05 +00002122 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2123 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002124 unsigned imm = 0;
2125
Jim Grosbachecaef492012-08-14 19:06:05 +00002126 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2127 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby5dcda642011-10-04 22:44:48 +00002128
2129 if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northovera155ab22013-04-19 09:58:09 +00002130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby5dcda642011-10-04 22:44:48 +00002131 return MCDisassembler::Fail;
Tim Northovera155ab22013-04-19 09:58:09 +00002132
2133 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby5dcda642011-10-04 22:44:48 +00002134 return MCDisassembler::Fail;
2135
2136 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002137 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002138
2139 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2140 return MCDisassembler::Fail;
2141
2142 return S;
2143}
Owen Anderson9b7bd152011-08-23 17:45:18 +00002144
Craig Topperf6e7e122012-03-27 07:21:54 +00002145static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002146 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002147 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002148
Jim Grosbachecaef492012-08-14 19:06:05 +00002149 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2150 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2151 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2152 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2153 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002154
2155 if (pred == 0xF)
2156 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2157
Owen Anderson03aadae2011-09-01 23:23:50 +00002158 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2159 return MCDisassembler::Fail;
2160 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2161 return MCDisassembler::Fail;
2162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2163 return MCDisassembler::Fail;
2164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2165 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002166
Owen Anderson03aadae2011-09-01 23:23:50 +00002167 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2168 return MCDisassembler::Fail;
Owen Anderson2f7aa732011-08-11 22:05:38 +00002169
Owen Andersona4043c42011-08-17 17:44:15 +00002170 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002171}
2172
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002173static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2174 uint64_t Address, const void *Decoder) {
2175 DecodeStatus S = MCDisassembler::Success;
2176
2177 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2178 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2179 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2180
2181 if (Pred == 0xF)
2182 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2183
2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2185 return MCDisassembler::Fail;
2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2187 return MCDisassembler::Fail;
2188 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2189 return MCDisassembler::Fail;
2190
2191 return S;
2192}
2193
2194static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2195 uint64_t Address, const void *Decoder) {
2196 DecodeStatus S = MCDisassembler::Success;
2197
2198 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2199
2200 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Michael Kupersteindb0712f2015-05-26 10:47:10 +00002201 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2202
Fangrui Songf78650a2018-07-30 19:41:25 +00002203 if (!FeatureBits[ARM::HasV8_1aOps] ||
Michael Kupersteindb0712f2015-05-26 10:47:10 +00002204 !FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002205 return MCDisassembler::Fail;
2206
2207 // Decoder can be called from DecodeTST, which does not check the full
2208 // encoding is valid.
2209 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2210 fieldFromInstruction(Insn, 4,4) != 0)
2211 return MCDisassembler::Fail;
2212 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2213 fieldFromInstruction(Insn, 0,4) != 0)
2214 S = MCDisassembler::SoftFail;
2215
2216 Inst.setOpcode(ARM::SETPAN);
Jim Grosbache9119e42015-05-13 18:37:00 +00002217 Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev0e0f8d22015-04-16 11:34:25 +00002218
2219 return S;
2220}
2221
Craig Topperf6e7e122012-03-27 07:21:54 +00002222static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002223 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002224 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002225
Jim Grosbachecaef492012-08-14 19:06:05 +00002226 unsigned add = fieldFromInstruction(Val, 12, 1);
2227 unsigned imm = fieldFromInstruction(Val, 0, 12);
2228 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002229
Owen Anderson03aadae2011-09-01 23:23:50 +00002230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002232
2233 if (!add) imm *= -1;
2234 if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbache9119e42015-05-13 18:37:00 +00002235 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00002236 if (Rn == 15)
2237 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00002238
Owen Andersona4043c42011-08-17 17:44:15 +00002239 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002240}
2241
Craig Topperf6e7e122012-03-27 07:21:54 +00002242static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002243 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002244 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002245
Jim Grosbachecaef492012-08-14 19:06:05 +00002246 unsigned Rn = fieldFromInstruction(Val, 9, 4);
Oliver Stannard65b85382016-01-25 10:26:26 +00002247 // U == 1 to add imm, 0 to subtract it.
Jim Grosbachecaef492012-08-14 19:06:05 +00002248 unsigned U = fieldFromInstruction(Val, 8, 1);
2249 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00002250
Owen Anderson03aadae2011-09-01 23:23:50 +00002251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2252 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002253
2254 if (U)
Jim Grosbache9119e42015-05-13 18:37:00 +00002255 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Andersone0152a72011-08-09 20:55:18 +00002256 else
Jim Grosbache9119e42015-05-13 18:37:00 +00002257 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Andersone0152a72011-08-09 20:55:18 +00002258
Owen Andersona4043c42011-08-17 17:44:15 +00002259 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002260}
2261
Oliver Stannard65b85382016-01-25 10:26:26 +00002262static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2263 uint64_t Address, const void *Decoder) {
2264 DecodeStatus S = MCDisassembler::Success;
2265
2266 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2267 // U == 1 to add imm, 0 to subtract it.
2268 unsigned U = fieldFromInstruction(Val, 8, 1);
2269 unsigned imm = fieldFromInstruction(Val, 0, 8);
2270
2271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2272 return MCDisassembler::Fail;
2273
2274 if (U)
2275 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2276 else
2277 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2278
2279 return S;
2280}
2281
Craig Topperf6e7e122012-03-27 07:21:54 +00002282static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002283 uint64_t Address, const void *Decoder) {
2284 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2285}
2286
Owen Anderson03aadae2011-09-01 23:23:50 +00002287static DecodeStatus
Kevin Enderby40d4e472012-04-12 23:13:34 +00002288DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2289 uint64_t Address, const void *Decoder) {
Kevin Enderby6fd96242012-10-29 23:27:20 +00002290 DecodeStatus Status = MCDisassembler::Success;
2291
2292 // Note the J1 and J2 values are from the encoded instruction. So here
2293 // change them to I1 and I2 values via as documented:
2294 // I1 = NOT(J1 EOR S);
2295 // I2 = NOT(J2 EOR S);
2296 // and build the imm32 with one trailing zero as documented:
2297 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2298 unsigned S = fieldFromInstruction(Insn, 26, 1);
2299 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2300 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2301 unsigned I1 = !(J1 ^ S);
2302 unsigned I2 = !(J2 ^ S);
2303 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2304 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2305 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
Amaury de la Vieuvillebd2b6102013-06-13 16:41:55 +00002306 int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby6fd96242012-10-29 23:27:20 +00002307 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00002308 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002309 Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby6fd96242012-10-29 23:27:20 +00002310
2311 return Status;
Kevin Enderby40d4e472012-04-12 23:13:34 +00002312}
2313
2314static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00002315DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00002316 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002317 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002318
Jim Grosbachecaef492012-08-14 19:06:05 +00002319 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2320 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Andersone0152a72011-08-09 20:55:18 +00002321
2322 if (pred == 0xF) {
2323 Inst.setOpcode(ARM::BLXi);
Jim Grosbachecaef492012-08-14 19:06:05 +00002324 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00002325 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2326 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002327 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Andersona4043c42011-08-17 17:44:15 +00002328 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002329 }
2330
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00002331 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2332 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00002333 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson03aadae2011-09-01 23:23:50 +00002334 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2335 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002336
Owen Andersona4043c42011-08-17 17:44:15 +00002337 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002338}
2339
Craig Topperf6e7e122012-03-27 07:21:54 +00002340static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00002341 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002342 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002343
Jim Grosbachecaef492012-08-14 19:06:05 +00002344 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2345 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00002346
Owen Anderson03aadae2011-09-01 23:23:50 +00002347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2348 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002349 if (!align)
Jim Grosbache9119e42015-05-13 18:37:00 +00002350 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00002351 else
Jim Grosbache9119e42015-05-13 18:37:00 +00002352 Inst.addOperand(MCOperand::createImm(4 << align));
Owen Andersone0152a72011-08-09 20:55:18 +00002353
Owen Andersona4043c42011-08-17 17:44:15 +00002354 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002355}
2356
Craig Topperf6e7e122012-03-27 07:21:54 +00002357static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002358 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002359 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002360
Jim Grosbachecaef492012-08-14 19:06:05 +00002361 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2362 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2363 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2364 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2365 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2366 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002367
2368 // First output register
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002369 switch (Inst.getOpcode()) {
Jim Grosbach13a292c2012-03-06 22:01:44 +00002370 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2371 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2372 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2373 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2374 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2375 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2376 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2377 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2378 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002379 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2380 return MCDisassembler::Fail;
2381 break;
Jim Grosbache5307f92012-03-05 21:43:40 +00002382 case ARM::VLD2b16:
2383 case ARM::VLD2b32:
2384 case ARM::VLD2b8:
2385 case ARM::VLD2b16wb_fixed:
2386 case ARM::VLD2b16wb_register:
2387 case ARM::VLD2b32wb_fixed:
2388 case ARM::VLD2b32wb_register:
2389 case ARM::VLD2b8wb_fixed:
2390 case ARM::VLD2b8wb_register:
2391 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2392 return MCDisassembler::Fail;
2393 break;
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002394 default:
2395 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2396 return MCDisassembler::Fail;
2397 }
Owen Andersone0152a72011-08-09 20:55:18 +00002398
2399 // Second output register
2400 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002401 case ARM::VLD3d8:
2402 case ARM::VLD3d16:
2403 case ARM::VLD3d32:
2404 case ARM::VLD3d8_UPD:
2405 case ARM::VLD3d16_UPD:
2406 case ARM::VLD3d32_UPD:
2407 case ARM::VLD4d8:
2408 case ARM::VLD4d16:
2409 case ARM::VLD4d32:
2410 case ARM::VLD4d8_UPD:
2411 case ARM::VLD4d16_UPD:
2412 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002413 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2414 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002415 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002416 case ARM::VLD3q8:
2417 case ARM::VLD3q16:
2418 case ARM::VLD3q32:
2419 case ARM::VLD3q8_UPD:
2420 case ARM::VLD3q16_UPD:
2421 case ARM::VLD3q32_UPD:
2422 case ARM::VLD4q8:
2423 case ARM::VLD4q16:
2424 case ARM::VLD4q32:
2425 case ARM::VLD4q8_UPD:
2426 case ARM::VLD4q16_UPD:
2427 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002428 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2429 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00002430 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002431 default:
2432 break;
2433 }
2434
2435 // Third output register
2436 switch(Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002437 case ARM::VLD3d8:
2438 case ARM::VLD3d16:
2439 case ARM::VLD3d32:
2440 case ARM::VLD3d8_UPD:
2441 case ARM::VLD3d16_UPD:
2442 case ARM::VLD3d32_UPD:
2443 case ARM::VLD4d8:
2444 case ARM::VLD4d16:
2445 case ARM::VLD4d32:
2446 case ARM::VLD4d8_UPD:
2447 case ARM::VLD4d16_UPD:
2448 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002449 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2450 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002451 break;
2452 case ARM::VLD3q8:
2453 case ARM::VLD3q16:
2454 case ARM::VLD3q32:
2455 case ARM::VLD3q8_UPD:
2456 case ARM::VLD3q16_UPD:
2457 case ARM::VLD3q32_UPD:
2458 case ARM::VLD4q8:
2459 case ARM::VLD4q16:
2460 case ARM::VLD4q32:
2461 case ARM::VLD4q8_UPD:
2462 case ARM::VLD4q16_UPD:
2463 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002464 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2465 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002466 break;
2467 default:
2468 break;
2469 }
2470
2471 // Fourth output register
2472 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002473 case ARM::VLD4d8:
2474 case ARM::VLD4d16:
2475 case ARM::VLD4d32:
2476 case ARM::VLD4d8_UPD:
2477 case ARM::VLD4d16_UPD:
2478 case ARM::VLD4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002479 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2480 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002481 break;
2482 case ARM::VLD4q8:
2483 case ARM::VLD4q16:
2484 case ARM::VLD4q32:
2485 case ARM::VLD4q8_UPD:
2486 case ARM::VLD4q16_UPD:
2487 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002488 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2489 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002490 break;
2491 default:
2492 break;
2493 }
2494
2495 // Writeback operand
2496 switch (Inst.getOpcode()) {
Jim Grosbach2098cb12011-10-24 21:45:13 +00002497 case ARM::VLD1d8wb_fixed:
2498 case ARM::VLD1d16wb_fixed:
2499 case ARM::VLD1d32wb_fixed:
2500 case ARM::VLD1d64wb_fixed:
2501 case ARM::VLD1d8wb_register:
2502 case ARM::VLD1d16wb_register:
2503 case ARM::VLD1d32wb_register:
2504 case ARM::VLD1d64wb_register:
2505 case ARM::VLD1q8wb_fixed:
2506 case ARM::VLD1q16wb_fixed:
2507 case ARM::VLD1q32wb_fixed:
2508 case ARM::VLD1q64wb_fixed:
2509 case ARM::VLD1q8wb_register:
2510 case ARM::VLD1q16wb_register:
2511 case ARM::VLD1q32wb_register:
2512 case ARM::VLD1q64wb_register:
Jim Grosbach92fd05e2011-10-24 23:26:05 +00002513 case ARM::VLD1d8Twb_fixed:
2514 case ARM::VLD1d8Twb_register:
2515 case ARM::VLD1d16Twb_fixed:
2516 case ARM::VLD1d16Twb_register:
2517 case ARM::VLD1d32Twb_fixed:
2518 case ARM::VLD1d32Twb_register:
2519 case ARM::VLD1d64Twb_fixed:
2520 case ARM::VLD1d64Twb_register:
Jim Grosbach17ec1a12011-10-25 00:14:01 +00002521 case ARM::VLD1d8Qwb_fixed:
2522 case ARM::VLD1d8Qwb_register:
2523 case ARM::VLD1d16Qwb_fixed:
2524 case ARM::VLD1d16Qwb_register:
2525 case ARM::VLD1d32Qwb_fixed:
2526 case ARM::VLD1d32Qwb_register:
2527 case ARM::VLD1d64Qwb_fixed:
2528 case ARM::VLD1d64Qwb_register:
Jim Grosbachd146a022011-12-09 21:28:25 +00002529 case ARM::VLD2d8wb_fixed:
2530 case ARM::VLD2d16wb_fixed:
2531 case ARM::VLD2d32wb_fixed:
2532 case ARM::VLD2q8wb_fixed:
2533 case ARM::VLD2q16wb_fixed:
2534 case ARM::VLD2q32wb_fixed:
2535 case ARM::VLD2d8wb_register:
2536 case ARM::VLD2d16wb_register:
2537 case ARM::VLD2d32wb_register:
2538 case ARM::VLD2q8wb_register:
2539 case ARM::VLD2q16wb_register:
2540 case ARM::VLD2q32wb_register:
2541 case ARM::VLD2b8wb_fixed:
2542 case ARM::VLD2b16wb_fixed:
2543 case ARM::VLD2b32wb_fixed:
2544 case ARM::VLD2b8wb_register:
2545 case ARM::VLD2b16wb_register:
2546 case ARM::VLD2b32wb_register:
Jim Grosbache9119e42015-05-13 18:37:00 +00002547 Inst.addOperand(MCOperand::createImm(0));
Kevin Enderbyd2980cd2012-04-11 00:25:40 +00002548 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002549 case ARM::VLD3d8_UPD:
2550 case ARM::VLD3d16_UPD:
2551 case ARM::VLD3d32_UPD:
2552 case ARM::VLD3q8_UPD:
2553 case ARM::VLD3q16_UPD:
2554 case ARM::VLD3q32_UPD:
2555 case ARM::VLD4d8_UPD:
2556 case ARM::VLD4d16_UPD:
2557 case ARM::VLD4d32_UPD:
2558 case ARM::VLD4q8_UPD:
2559 case ARM::VLD4q16_UPD:
2560 case ARM::VLD4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002561 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2562 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002563 break;
2564 default:
2565 break;
2566 }
2567
2568 // AddrMode6 Base (register+alignment)
Owen Anderson03aadae2011-09-01 23:23:50 +00002569 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2570 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002571
2572 // AddrMode6 Offset (register)
Jim Grosbach2098cb12011-10-24 21:45:13 +00002573 switch (Inst.getOpcode()) {
2574 default:
2575 // The below have been updated to have explicit am6offset split
2576 // between fixed and register offset. For those instructions not
2577 // yet updated, we need to add an additional reg0 operand for the
2578 // fixed variant.
2579 //
2580 // The fixed offset encodes as Rm == 0xd, so we check for that.
2581 if (Rm == 0xd) {
Jim Grosbache9119e42015-05-13 18:37:00 +00002582 Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach2098cb12011-10-24 21:45:13 +00002583 break;
2584 }
2585 // Fall through to handle the register offset variant.
Justin Bognercd1d5aa2016-08-17 20:30:52 +00002586 LLVM_FALLTHROUGH;
Jim Grosbach2098cb12011-10-24 21:45:13 +00002587 case ARM::VLD1d8wb_fixed:
2588 case ARM::VLD1d16wb_fixed:
2589 case ARM::VLD1d32wb_fixed:
2590 case ARM::VLD1d64wb_fixed:
Owen Anderson8a6ebd02011-10-27 22:53:10 +00002591 case ARM::VLD1d8Twb_fixed:
2592 case ARM::VLD1d16Twb_fixed:
2593 case ARM::VLD1d32Twb_fixed:
2594 case ARM::VLD1d64Twb_fixed:
Owen Anderson40703f42011-10-31 17:17:32 +00002595 case ARM::VLD1d8Qwb_fixed:
2596 case ARM::VLD1d16Qwb_fixed:
2597 case ARM::VLD1d32Qwb_fixed:
2598 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach2098cb12011-10-24 21:45:13 +00002599 case ARM::VLD1d8wb_register:
2600 case ARM::VLD1d16wb_register:
2601 case ARM::VLD1d32wb_register:
2602 case ARM::VLD1d64wb_register:
2603 case ARM::VLD1q8wb_fixed:
2604 case ARM::VLD1q16wb_fixed:
2605 case ARM::VLD1q32wb_fixed:
2606 case ARM::VLD1q64wb_fixed:
2607 case ARM::VLD1q8wb_register:
2608 case ARM::VLD1q16wb_register:
2609 case ARM::VLD1q32wb_register:
2610 case ARM::VLD1q64wb_register:
2611 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2612 // variant encodes Rm == 0xf. Anything else is a register offset post-
2613 // increment and we need to add the register operand to the instruction.
2614 if (Rm != 0xD && Rm != 0xF &&
2615 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00002616 return MCDisassembler::Fail;
Jim Grosbach2098cb12011-10-24 21:45:13 +00002617 break;
Kevin Enderbyd2980cd2012-04-11 00:25:40 +00002618 case ARM::VLD2d8wb_fixed:
2619 case ARM::VLD2d16wb_fixed:
2620 case ARM::VLD2d32wb_fixed:
2621 case ARM::VLD2b8wb_fixed:
2622 case ARM::VLD2b16wb_fixed:
2623 case ARM::VLD2b32wb_fixed:
2624 case ARM::VLD2q8wb_fixed:
2625 case ARM::VLD2q16wb_fixed:
2626 case ARM::VLD2q32wb_fixed:
2627 break;
Owen Andersoned253852011-08-11 18:24:51 +00002628 }
Owen Andersone0152a72011-08-09 20:55:18 +00002629
Owen Andersona4043c42011-08-17 17:44:15 +00002630 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002631}
2632
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002633static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2634 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002635 unsigned type = fieldFromInstruction(Insn, 8, 4);
2636 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002637 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2638 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2639 if (type == 10 && align == 3) return MCDisassembler::Fail;
2640
2641 unsigned load = fieldFromInstruction(Insn, 21, 1);
2642 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2643 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002644}
2645
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002646static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2647 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002648 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002649 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002650
2651 unsigned type = fieldFromInstruction(Insn, 8, 4);
2652 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002653 if (type == 8 && align == 3) return MCDisassembler::Fail;
2654 if (type == 9 && align == 3) return MCDisassembler::Fail;
2655
2656 unsigned load = fieldFromInstruction(Insn, 21, 1);
2657 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2658 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002659}
2660
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002661static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2662 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002663 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002664 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002665
2666 unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002667 if (align & 2) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002668
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002669 unsigned load = fieldFromInstruction(Insn, 21, 1);
2670 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2671 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002672}
2673
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002674static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2675 uint64_t Address, const void *Decoder) {
Mihai Popaf41e3f52013-05-20 14:57:05 +00002676 unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002677 if (size == 3) return MCDisassembler::Fail;
Mihai Popaf41e3f52013-05-20 14:57:05 +00002678
Amaury de la Vieuville064546c2013-06-11 08:14:14 +00002679 unsigned load = fieldFromInstruction(Insn, 21, 1);
2680 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2681 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popaf41e3f52013-05-20 14:57:05 +00002682}
2683
Craig Topperf6e7e122012-03-27 07:21:54 +00002684static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002685 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002686 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002687
Jim Grosbachecaef492012-08-14 19:06:05 +00002688 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2689 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2690 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2691 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2692 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2693 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00002694
2695 // Writeback Operand
2696 switch (Inst.getOpcode()) {
Jim Grosbach05df4602011-10-31 21:50:31 +00002697 case ARM::VST1d8wb_fixed:
2698 case ARM::VST1d16wb_fixed:
2699 case ARM::VST1d32wb_fixed:
2700 case ARM::VST1d64wb_fixed:
2701 case ARM::VST1d8wb_register:
2702 case ARM::VST1d16wb_register:
2703 case ARM::VST1d32wb_register:
2704 case ARM::VST1d64wb_register:
2705 case ARM::VST1q8wb_fixed:
2706 case ARM::VST1q16wb_fixed:
2707 case ARM::VST1q32wb_fixed:
2708 case ARM::VST1q64wb_fixed:
2709 case ARM::VST1q8wb_register:
2710 case ARM::VST1q16wb_register:
2711 case ARM::VST1q32wb_register:
2712 case ARM::VST1q64wb_register:
Jim Grosbach98d032f2011-11-29 22:38:04 +00002713 case ARM::VST1d8Twb_fixed:
2714 case ARM::VST1d16Twb_fixed:
2715 case ARM::VST1d32Twb_fixed:
2716 case ARM::VST1d64Twb_fixed:
2717 case ARM::VST1d8Twb_register:
2718 case ARM::VST1d16Twb_register:
2719 case ARM::VST1d32Twb_register:
2720 case ARM::VST1d64Twb_register:
Jim Grosbach5ee209c2011-11-29 22:58:48 +00002721 case ARM::VST1d8Qwb_fixed:
2722 case ARM::VST1d16Qwb_fixed:
2723 case ARM::VST1d32Qwb_fixed:
2724 case ARM::VST1d64Qwb_fixed:
2725 case ARM::VST1d8Qwb_register:
2726 case ARM::VST1d16Qwb_register:
2727 case ARM::VST1d32Qwb_register:
2728 case ARM::VST1d64Qwb_register:
Jim Grosbach88ac7612011-12-14 21:32:11 +00002729 case ARM::VST2d8wb_fixed:
2730 case ARM::VST2d16wb_fixed:
2731 case ARM::VST2d32wb_fixed:
2732 case ARM::VST2d8wb_register:
2733 case ARM::VST2d16wb_register:
2734 case ARM::VST2d32wb_register:
2735 case ARM::VST2q8wb_fixed:
2736 case ARM::VST2q16wb_fixed:
2737 case ARM::VST2q32wb_fixed:
2738 case ARM::VST2q8wb_register:
2739 case ARM::VST2q16wb_register:
2740 case ARM::VST2q32wb_register:
2741 case ARM::VST2b8wb_fixed:
2742 case ARM::VST2b16wb_fixed:
2743 case ARM::VST2b32wb_fixed:
2744 case ARM::VST2b8wb_register:
2745 case ARM::VST2b16wb_register:
2746 case ARM::VST2b32wb_register:
Kevin Enderby72f18bb2012-04-11 22:40:17 +00002747 if (Rm == 0xF)
2748 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00002749 Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby7e7d5ee2012-03-21 20:54:32 +00002750 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002751 case ARM::VST3d8_UPD:
2752 case ARM::VST3d16_UPD:
2753 case ARM::VST3d32_UPD:
2754 case ARM::VST3q8_UPD:
2755 case ARM::VST3q16_UPD:
2756 case ARM::VST3q32_UPD:
2757 case ARM::VST4d8_UPD:
2758 case ARM::VST4d16_UPD:
2759 case ARM::VST4d32_UPD:
2760 case ARM::VST4q8_UPD:
2761 case ARM::VST4q16_UPD:
2762 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002763 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2764 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002765 break;
2766 default:
2767 break;
2768 }
2769
2770 // AddrMode6 Base (register+alignment)
Owen Anderson03aadae2011-09-01 23:23:50 +00002771 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2772 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002773
2774 // AddrMode6 Offset (register)
Owen Anderson69e54a72011-11-01 22:18:13 +00002775 switch (Inst.getOpcode()) {
2776 default:
2777 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00002778 Inst.addOperand(MCOperand::createReg(0));
Owen Anderson69e54a72011-11-01 22:18:13 +00002779 else if (Rm != 0xF) {
2780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2781 return MCDisassembler::Fail;
2782 }
2783 break;
2784 case ARM::VST1d8wb_fixed:
2785 case ARM::VST1d16wb_fixed:
2786 case ARM::VST1d32wb_fixed:
2787 case ARM::VST1d64wb_fixed:
2788 case ARM::VST1q8wb_fixed:
2789 case ARM::VST1q16wb_fixed:
2790 case ARM::VST1q32wb_fixed:
2791 case ARM::VST1q64wb_fixed:
Kevin Enderby7e7d5ee2012-03-21 20:54:32 +00002792 case ARM::VST1d8Twb_fixed:
2793 case ARM::VST1d16Twb_fixed:
2794 case ARM::VST1d32Twb_fixed:
2795 case ARM::VST1d64Twb_fixed:
2796 case ARM::VST1d8Qwb_fixed:
2797 case ARM::VST1d16Qwb_fixed:
2798 case ARM::VST1d32Qwb_fixed:
2799 case ARM::VST1d64Qwb_fixed:
2800 case ARM::VST2d8wb_fixed:
2801 case ARM::VST2d16wb_fixed:
2802 case ARM::VST2d32wb_fixed:
2803 case ARM::VST2q8wb_fixed:
2804 case ARM::VST2q16wb_fixed:
2805 case ARM::VST2q32wb_fixed:
2806 case ARM::VST2b8wb_fixed:
2807 case ARM::VST2b16wb_fixed:
2808 case ARM::VST2b32wb_fixed:
Owen Anderson69e54a72011-11-01 22:18:13 +00002809 break;
Owen Andersoned253852011-08-11 18:24:51 +00002810 }
Owen Andersone0152a72011-08-09 20:55:18 +00002811
2812 // First input register
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002813 switch (Inst.getOpcode()) {
2814 case ARM::VST1q16:
2815 case ARM::VST1q32:
2816 case ARM::VST1q64:
2817 case ARM::VST1q8:
2818 case ARM::VST1q16wb_fixed:
2819 case ARM::VST1q16wb_register:
2820 case ARM::VST1q32wb_fixed:
2821 case ARM::VST1q32wb_register:
2822 case ARM::VST1q64wb_fixed:
2823 case ARM::VST1q64wb_register:
2824 case ARM::VST1q8wb_fixed:
2825 case ARM::VST1q8wb_register:
2826 case ARM::VST2d16:
2827 case ARM::VST2d32:
2828 case ARM::VST2d8:
2829 case ARM::VST2d16wb_fixed:
2830 case ARM::VST2d16wb_register:
2831 case ARM::VST2d32wb_fixed:
2832 case ARM::VST2d32wb_register:
2833 case ARM::VST2d8wb_fixed:
2834 case ARM::VST2d8wb_register:
2835 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2836 return MCDisassembler::Fail;
2837 break;
Jim Grosbache5307f92012-03-05 21:43:40 +00002838 case ARM::VST2b16:
2839 case ARM::VST2b32:
2840 case ARM::VST2b8:
2841 case ARM::VST2b16wb_fixed:
2842 case ARM::VST2b16wb_register:
2843 case ARM::VST2b32wb_fixed:
2844 case ARM::VST2b32wb_register:
2845 case ARM::VST2b8wb_fixed:
2846 case ARM::VST2b8wb_register:
2847 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2848 return MCDisassembler::Fail;
2849 break;
Jim Grosbachc988e0c2012-03-05 19:33:30 +00002850 default:
2851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2852 return MCDisassembler::Fail;
2853 }
Owen Andersone0152a72011-08-09 20:55:18 +00002854
2855 // Second input register
2856 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002857 case ARM::VST3d8:
2858 case ARM::VST3d16:
2859 case ARM::VST3d32:
2860 case ARM::VST3d8_UPD:
2861 case ARM::VST3d16_UPD:
2862 case ARM::VST3d32_UPD:
2863 case ARM::VST4d8:
2864 case ARM::VST4d16:
2865 case ARM::VST4d32:
2866 case ARM::VST4d8_UPD:
2867 case ARM::VST4d16_UPD:
2868 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002869 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2870 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002871 break;
Owen Andersone0152a72011-08-09 20:55:18 +00002872 case ARM::VST3q8:
2873 case ARM::VST3q16:
2874 case ARM::VST3q32:
2875 case ARM::VST3q8_UPD:
2876 case ARM::VST3q16_UPD:
2877 case ARM::VST3q32_UPD:
2878 case ARM::VST4q8:
2879 case ARM::VST4q16:
2880 case ARM::VST4q32:
2881 case ARM::VST4q8_UPD:
2882 case ARM::VST4q16_UPD:
2883 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002884 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2885 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002886 break;
2887 default:
2888 break;
2889 }
2890
2891 // Third input register
2892 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002893 case ARM::VST3d8:
2894 case ARM::VST3d16:
2895 case ARM::VST3d32:
2896 case ARM::VST3d8_UPD:
2897 case ARM::VST3d16_UPD:
2898 case ARM::VST3d32_UPD:
2899 case ARM::VST4d8:
2900 case ARM::VST4d16:
2901 case ARM::VST4d32:
2902 case ARM::VST4d8_UPD:
2903 case ARM::VST4d16_UPD:
2904 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002905 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2906 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002907 break;
2908 case ARM::VST3q8:
2909 case ARM::VST3q16:
2910 case ARM::VST3q32:
2911 case ARM::VST3q8_UPD:
2912 case ARM::VST3q16_UPD:
2913 case ARM::VST3q32_UPD:
2914 case ARM::VST4q8:
2915 case ARM::VST4q16:
2916 case ARM::VST4q32:
2917 case ARM::VST4q8_UPD:
2918 case ARM::VST4q16_UPD:
2919 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002920 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2921 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002922 break;
2923 default:
2924 break;
2925 }
2926
2927 // Fourth input register
2928 switch (Inst.getOpcode()) {
Owen Andersone0152a72011-08-09 20:55:18 +00002929 case ARM::VST4d8:
2930 case ARM::VST4d16:
2931 case ARM::VST4d32:
2932 case ARM::VST4d8_UPD:
2933 case ARM::VST4d16_UPD:
2934 case ARM::VST4d32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002935 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2936 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002937 break;
2938 case ARM::VST4q8:
2939 case ARM::VST4q16:
2940 case ARM::VST4q32:
2941 case ARM::VST4q8_UPD:
2942 case ARM::VST4q16_UPD:
2943 case ARM::VST4q32_UPD:
Owen Anderson03aadae2011-09-01 23:23:50 +00002944 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2945 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002946 break;
2947 default:
2948 break;
2949 }
2950
Owen Andersona4043c42011-08-17 17:44:15 +00002951 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002952}
2953
Craig Topperf6e7e122012-03-27 07:21:54 +00002954static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00002955 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002956 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00002957
Jim Grosbachecaef492012-08-14 19:06:05 +00002958 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2959 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2960 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2961 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2962 unsigned align = fieldFromInstruction(Insn, 4, 1);
2963 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00002964
Tim Northover00e071a2012-09-06 15:27:12 +00002965 if (size == 0 && align == 1)
2966 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002967 align *= (1 << size);
2968
Jim Grosbach13a292c2012-03-06 22:01:44 +00002969 switch (Inst.getOpcode()) {
2970 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2971 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2972 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2973 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2974 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2975 return MCDisassembler::Fail;
2976 break;
2977 default:
2978 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2979 return MCDisassembler::Fail;
2980 break;
2981 }
Owen Andersonac92e772011-08-22 18:22:06 +00002982 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00002983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2984 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00002985 }
Owen Andersone0152a72011-08-09 20:55:18 +00002986
Owen Anderson03aadae2011-09-01 23:23:50 +00002987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2988 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00002989 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00002990
Jim Grosbacha68c9a82011-11-30 19:35:44 +00002991 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2992 // variant encodes Rm == 0xf. Anything else is a register offset post-
2993 // increment and we need to add the register operand to the instruction.
2994 if (Rm != 0xD && Rm != 0xF &&
2995 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2996 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00002997
Owen Andersona4043c42011-08-17 17:44:15 +00002998 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00002999}
3000
Craig Topperf6e7e122012-03-27 07:21:54 +00003001static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003002 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003003 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003004
Jim Grosbachecaef492012-08-14 19:06:05 +00003005 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3006 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3007 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3008 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3009 unsigned align = fieldFromInstruction(Insn, 4, 1);
3010 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00003011 align *= 2*size;
3012
Jim Grosbach13a292c2012-03-06 22:01:44 +00003013 switch (Inst.getOpcode()) {
3014 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3015 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3016 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3017 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3018 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3019 return MCDisassembler::Fail;
3020 break;
Jim Grosbached428bc2012-03-06 23:10:38 +00003021 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3022 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3023 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3024 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3025 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3026 return MCDisassembler::Fail;
3027 break;
Jim Grosbach13a292c2012-03-06 22:01:44 +00003028 default:
3029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3030 return MCDisassembler::Fail;
3031 break;
3032 }
Kevin Enderby520eb3b2012-03-06 18:33:12 +00003033
3034 if (Rm != 0xF)
Jim Grosbache9119e42015-05-13 18:37:00 +00003035 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00003036
Owen Anderson03aadae2011-09-01 23:23:50 +00003037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3038 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003039 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00003040
Kevin Enderby29ae5382012-04-17 00:49:27 +00003041 if (Rm != 0xD && Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003044 }
Owen Andersone0152a72011-08-09 20:55:18 +00003045
Owen Andersona4043c42011-08-17 17:44:15 +00003046 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003047}
3048
Craig Topperf6e7e122012-03-27 07:21:54 +00003049static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003050 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003051 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003052
Jim Grosbachecaef492012-08-14 19:06:05 +00003053 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3054 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3055 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3056 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3057 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Andersone0152a72011-08-09 20:55:18 +00003058
Owen Anderson03aadae2011-09-01 23:23:50 +00003059 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3060 return MCDisassembler::Fail;
3061 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3062 return MCDisassembler::Fail;
3063 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3064 return MCDisassembler::Fail;
Owen Andersonac92e772011-08-22 18:22:06 +00003065 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3067 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003068 }
Owen Andersone0152a72011-08-09 20:55:18 +00003069
Owen Anderson03aadae2011-09-01 23:23:50 +00003070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3071 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003072 Inst.addOperand(MCOperand::createImm(0));
Owen Andersone0152a72011-08-09 20:55:18 +00003073
3074 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00003075 Inst.addOperand(MCOperand::createReg(0));
Owen Andersoned253852011-08-11 18:24:51 +00003076 else if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003079 }
Owen Andersone0152a72011-08-09 20:55:18 +00003080
Owen Andersona4043c42011-08-17 17:44:15 +00003081 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003082}
3083
Craig Topperf6e7e122012-03-27 07:21:54 +00003084static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003085 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003086 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003087
Jim Grosbachecaef492012-08-14 19:06:05 +00003088 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3089 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3090 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3091 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3092 unsigned size = fieldFromInstruction(Insn, 6, 2);
3093 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3094 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003095
3096 if (size == 0x3) {
Tim Northover00e071a2012-09-06 15:27:12 +00003097 if (align == 0)
3098 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003099 align = 16;
3100 } else {
3101 if (size == 2) {
Owen Andersone0152a72011-08-09 20:55:18 +00003102 align *= 8;
3103 } else {
3104 size = 1 << size;
3105 align *= 4*size;
3106 }
3107 }
3108
Owen Anderson03aadae2011-09-01 23:23:50 +00003109 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3110 return MCDisassembler::Fail;
3111 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3112 return MCDisassembler::Fail;
3113 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3114 return MCDisassembler::Fail;
3115 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3116 return MCDisassembler::Fail;
Owen Andersonac92e772011-08-22 18:22:06 +00003117 if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003118 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3119 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003120 }
Owen Andersone0152a72011-08-09 20:55:18 +00003121
Owen Anderson03aadae2011-09-01 23:23:50 +00003122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3123 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003124 Inst.addOperand(MCOperand::createImm(align));
Owen Andersone0152a72011-08-09 20:55:18 +00003125
3126 if (Rm == 0xD)
Jim Grosbache9119e42015-05-13 18:37:00 +00003127 Inst.addOperand(MCOperand::createReg(0));
Owen Andersoned253852011-08-11 18:24:51 +00003128 else if (Rm != 0xF) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3130 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003131 }
Owen Andersone0152a72011-08-09 20:55:18 +00003132
Owen Andersona4043c42011-08-17 17:44:15 +00003133 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003134}
3135
Owen Anderson03aadae2011-09-01 23:23:50 +00003136static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00003137DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00003138 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003139 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003140
Jim Grosbachecaef492012-08-14 19:06:05 +00003141 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3142 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3143 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3144 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3145 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3146 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3147 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3148 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003149
Owen Andersoned253852011-08-11 18:24:51 +00003150 if (Q) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003151 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3152 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003153 } else {
Owen Anderson03aadae2011-09-01 23:23:50 +00003154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3155 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003156 }
Owen Andersone0152a72011-08-09 20:55:18 +00003157
Jim Grosbache9119e42015-05-13 18:37:00 +00003158 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003159
3160 switch (Inst.getOpcode()) {
3161 case ARM::VORRiv4i16:
3162 case ARM::VORRiv2i32:
3163 case ARM::VBICiv4i16:
3164 case ARM::VBICiv2i32:
Owen Anderson03aadae2011-09-01 23:23:50 +00003165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3166 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003167 break;
3168 case ARM::VORRiv8i16:
3169 case ARM::VORRiv4i32:
3170 case ARM::VBICiv8i16:
3171 case ARM::VBICiv4i32:
Owen Anderson03aadae2011-09-01 23:23:50 +00003172 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3173 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003174 break;
3175 default:
3176 break;
3177 }
3178
Owen Andersona4043c42011-08-17 17:44:15 +00003179 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003180}
3181
Craig Topperf6e7e122012-03-27 07:21:54 +00003182static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003183 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003184 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003185
Jim Grosbachecaef492012-08-14 19:06:05 +00003186 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3187 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3188 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3189 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3190 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00003191
Owen Anderson03aadae2011-09-01 23:23:50 +00003192 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3193 return MCDisassembler::Fail;
3194 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3195 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003196 Inst.addOperand(MCOperand::createImm(8 << size));
Owen Andersone0152a72011-08-09 20:55:18 +00003197
Owen Andersona4043c42011-08-17 17:44:15 +00003198 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003199}
3200
Craig Topperf6e7e122012-03-27 07:21:54 +00003201static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003202 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003203 Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003204 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003205}
3206
Craig Topperf6e7e122012-03-27 07:21:54 +00003207static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003208 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003209 Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003210 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003211}
3212
Craig Topperf6e7e122012-03-27 07:21:54 +00003213static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003214 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003215 Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003216 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003217}
3218
Craig Topperf6e7e122012-03-27 07:21:54 +00003219static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003220 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003221 Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloydb4ce602011-09-01 18:02:14 +00003222 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003223}
3224
Craig Topperf6e7e122012-03-27 07:21:54 +00003225static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003226 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003227 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003228
Jim Grosbachecaef492012-08-14 19:06:05 +00003229 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3230 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3231 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3232 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3233 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3234 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3235 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003236
Owen Anderson03aadae2011-09-01 23:23:50 +00003237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3238 return MCDisassembler::Fail;
Owen Andersoned253852011-08-11 18:24:51 +00003239 if (op) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3241 return MCDisassembler::Fail; // Writeback
Owen Andersoned253852011-08-11 18:24:51 +00003242 }
Owen Andersone0152a72011-08-09 20:55:18 +00003243
Jim Grosbachc988e0c2012-03-05 19:33:30 +00003244 switch (Inst.getOpcode()) {
3245 case ARM::VTBL2:
3246 case ARM::VTBX2:
3247 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3248 return MCDisassembler::Fail;
3249 break;
3250 default:
3251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3252 return MCDisassembler::Fail;
3253 }
Owen Andersone0152a72011-08-09 20:55:18 +00003254
Owen Anderson03aadae2011-09-01 23:23:50 +00003255 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3256 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003257
Owen Andersona4043c42011-08-17 17:44:15 +00003258 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003259}
3260
Craig Topperf6e7e122012-03-27 07:21:54 +00003261static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003262 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003263 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003264
Jim Grosbachecaef492012-08-14 19:06:05 +00003265 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3266 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00003267
Owen Anderson03aadae2011-09-01 23:23:50 +00003268 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3269 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003270
Owen Andersona01bcbf2011-08-26 18:09:22 +00003271 switch(Inst.getOpcode()) {
Owen Anderson5658b492011-08-26 19:39:26 +00003272 default:
James Molloydb4ce602011-09-01 18:02:14 +00003273 return MCDisassembler::Fail;
Owen Andersona01bcbf2011-08-26 18:09:22 +00003274 case ARM::tADR:
Owen Anderson240d20a2011-08-26 21:47:57 +00003275 break; // tADR does not explicitly represent the PC as an operand.
Owen Andersona01bcbf2011-08-26 18:09:22 +00003276 case ARM::tADDrSPi:
Jim Grosbache9119e42015-05-13 18:37:00 +00003277 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Andersona01bcbf2011-08-26 18:09:22 +00003278 break;
Owen Andersona01bcbf2011-08-26 18:09:22 +00003279 }
Owen Andersone0152a72011-08-09 20:55:18 +00003280
Jim Grosbache9119e42015-05-13 18:37:00 +00003281 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersona4043c42011-08-17 17:44:15 +00003282 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003283}
3284
Craig Topperf6e7e122012-03-27 07:21:54 +00003285static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003286 uint64_t Address, const void *Decoder) {
Kevin Enderby40d4e472012-04-12 23:13:34 +00003287 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3288 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003289 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloydb4ce602011-09-01 18:02:14 +00003290 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003291}
3292
Craig Topperf6e7e122012-03-27 07:21:54 +00003293static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003294 uint64_t Address, const void *Decoder) {
Kevin Enderbycabbae62012-05-04 22:09:52 +00003295 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00003296 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003297 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloydb4ce602011-09-01 18:02:14 +00003298 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003299}
3300
Craig Topperf6e7e122012-03-27 07:21:54 +00003301static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003302 uint64_t Address, const void *Decoder) {
Gordon Keiser772cf462013-03-28 19:22:28 +00003303 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00003304 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003305 Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloydb4ce602011-09-01 18:02:14 +00003306 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003307}
3308
Craig Topperf6e7e122012-03-27 07:21:54 +00003309static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003310 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003311 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003312
Jim Grosbachecaef492012-08-14 19:06:05 +00003313 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3314 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Andersone0152a72011-08-09 20:55:18 +00003315
Owen Anderson03aadae2011-09-01 23:23:50 +00003316 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3317 return MCDisassembler::Fail;
3318 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3319 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003320
Owen Andersona4043c42011-08-17 17:44:15 +00003321 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003322}
3323
Craig Topperf6e7e122012-03-27 07:21:54 +00003324static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003325 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003326 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003327
Jim Grosbachecaef492012-08-14 19:06:05 +00003328 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3329 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00003330
Owen Anderson03aadae2011-09-01 23:23:50 +00003331 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003333 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003334
Owen Andersona4043c42011-08-17 17:44:15 +00003335 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003336}
3337
Craig Topperf6e7e122012-03-27 07:21:54 +00003338static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003339 uint64_t Address, const void *Decoder) {
Kevin Enderby5dcda642011-10-04 22:44:48 +00003340 unsigned imm = Val << 2;
3341
Jim Grosbache9119e42015-05-13 18:37:00 +00003342 Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby5dcda642011-10-04 22:44:48 +00003343 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00003344
James Molloydb4ce602011-09-01 18:02:14 +00003345 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003346}
3347
Craig Topperf6e7e122012-03-27 07:21:54 +00003348static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003349 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +00003350 Inst.addOperand(MCOperand::createReg(ARM::SP));
3351 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersone0152a72011-08-09 20:55:18 +00003352
James Molloydb4ce602011-09-01 18:02:14 +00003353 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003354}
3355
Craig Topperf6e7e122012-03-27 07:21:54 +00003356static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003357 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003358 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003359
Jim Grosbachecaef492012-08-14 19:06:05 +00003360 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3361 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3362 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00003363
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003364 // Thumb stores cannot use PC as dest register.
3365 switch (Inst.getOpcode()) {
3366 case ARM::t2STRHs:
3367 case ARM::t2STRBs:
3368 case ARM::t2STRs:
3369 if (Rn == 15)
3370 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003371 break;
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003372 default:
3373 break;
3374 }
3375
Owen Anderson03aadae2011-09-01 23:23:50 +00003376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3377 return MCDisassembler::Fail;
3378 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3379 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003380 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003381
Owen Andersona4043c42011-08-17 17:44:15 +00003382 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003383}
3384
Craig Topperf6e7e122012-03-27 07:21:54 +00003385static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Andersone0152a72011-08-09 20:55:18 +00003386 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003387 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003388
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003389 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbachecaef492012-08-14 19:06:05 +00003390 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003391
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003392 const FeatureBitset &featureBits =
3393 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3394
3395 bool hasMP = featureBits[ARM::FeatureMP];
3396 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003397
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003398 if (Rn == 15) {
Owen Andersone0152a72011-08-09 20:55:18 +00003399 switch (Inst.getOpcode()) {
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003400 case ARM::t2LDRBs:
3401 Inst.setOpcode(ARM::t2LDRBpci);
3402 break;
3403 case ARM::t2LDRHs:
3404 Inst.setOpcode(ARM::t2LDRHpci);
3405 break;
3406 case ARM::t2LDRSHs:
3407 Inst.setOpcode(ARM::t2LDRSHpci);
3408 break;
3409 case ARM::t2LDRSBs:
3410 Inst.setOpcode(ARM::t2LDRSBpci);
3411 break;
3412 case ARM::t2LDRs:
3413 Inst.setOpcode(ARM::t2LDRpci);
3414 break;
3415 case ARM::t2PLDs:
3416 Inst.setOpcode(ARM::t2PLDpci);
3417 break;
3418 case ARM::t2PLIs:
3419 Inst.setOpcode(ARM::t2PLIpci);
3420 break;
3421 default:
3422 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003423 }
3424
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003425 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3426 }
Owen Andersone0152a72011-08-09 20:55:18 +00003427
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003428 if (Rt == 15) {
3429 switch (Inst.getOpcode()) {
3430 case ARM::t2LDRSHs:
3431 return MCDisassembler::Fail;
3432 case ARM::t2LDRHs:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003433 Inst.setOpcode(ARM::t2PLDWs);
3434 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003435 case ARM::t2LDRSBs:
3436 Inst.setOpcode(ARM::t2PLIs);
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003437 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003438 default:
3439 break;
3440 }
3441 }
3442
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003443 switch (Inst.getOpcode()) {
3444 case ARM::t2PLDs:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003445 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003446 case ARM::t2PLIs:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003447 if (!hasV7Ops)
3448 return MCDisassembler::Fail;
3449 break;
3450 case ARM::t2PLDWs:
3451 if (!hasV7Ops || !hasMP)
3452 return MCDisassembler::Fail;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003453 break;
3454 default:
3455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3456 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003457 }
3458
Jim Grosbachecaef492012-08-14 19:06:05 +00003459 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3460 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3461 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson03aadae2011-09-01 23:23:50 +00003462 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3463 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003464
Owen Andersona4043c42011-08-17 17:44:15 +00003465 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003466}
3467
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003468static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3469 uint64_t Address, const void* Decoder) {
3470 DecodeStatus S = MCDisassembler::Success;
3471
3472 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3473 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3474 unsigned U = fieldFromInstruction(Insn, 9, 1);
3475 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3476 imm |= (U << 8);
3477 imm |= (Rn << 9);
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003478 unsigned add = fieldFromInstruction(Insn, 9, 1);
3479
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003480 const FeatureBitset &featureBits =
3481 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3482
3483 bool hasMP = featureBits[ARM::FeatureMP];
3484 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003485
3486 if (Rn == 15) {
3487 switch (Inst.getOpcode()) {
3488 case ARM::t2LDRi8:
3489 Inst.setOpcode(ARM::t2LDRpci);
3490 break;
3491 case ARM::t2LDRBi8:
3492 Inst.setOpcode(ARM::t2LDRBpci);
3493 break;
3494 case ARM::t2LDRSBi8:
3495 Inst.setOpcode(ARM::t2LDRSBpci);
3496 break;
3497 case ARM::t2LDRHi8:
3498 Inst.setOpcode(ARM::t2LDRHpci);
3499 break;
3500 case ARM::t2LDRSHi8:
3501 Inst.setOpcode(ARM::t2LDRSHpci);
3502 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003503 case ARM::t2PLDi8:
3504 Inst.setOpcode(ARM::t2PLDpci);
3505 break;
3506 case ARM::t2PLIi8:
3507 Inst.setOpcode(ARM::t2PLIpci);
3508 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003509 default:
3510 return MCDisassembler::Fail;
3511 }
3512 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3513 }
3514
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003515 if (Rt == 15) {
3516 switch (Inst.getOpcode()) {
3517 case ARM::t2LDRSHi8:
3518 return MCDisassembler::Fail;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003519 case ARM::t2LDRHi8:
3520 if (!add)
3521 Inst.setOpcode(ARM::t2PLDWi8);
3522 break;
3523 case ARM::t2LDRSBi8:
3524 Inst.setOpcode(ARM::t2PLIi8);
3525 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003526 default:
3527 break;
3528 }
3529 }
3530
3531 switch (Inst.getOpcode()) {
3532 case ARM::t2PLDi8:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003533 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003534 case ARM::t2PLIi8:
3535 if (!hasV7Ops)
3536 return MCDisassembler::Fail;
3537 break;
3538 case ARM::t2PLDWi8:
3539 if (!hasV7Ops || !hasMP)
3540 return MCDisassembler::Fail;
3541 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003542 default:
3543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3544 return MCDisassembler::Fail;
3545 }
3546
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003547 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3548 return MCDisassembler::Fail;
3549 return S;
3550}
3551
3552static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3553 uint64_t Address, const void* Decoder) {
3554 DecodeStatus S = MCDisassembler::Success;
3555
3556 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3557 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3558 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3559 imm |= (Rn << 13);
3560
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003561 const FeatureBitset &featureBits =
3562 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3563
3564 bool hasMP = featureBits[ARM::FeatureMP];
3565 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003566
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003567 if (Rn == 15) {
3568 switch (Inst.getOpcode()) {
3569 case ARM::t2LDRi12:
3570 Inst.setOpcode(ARM::t2LDRpci);
3571 break;
3572 case ARM::t2LDRHi12:
3573 Inst.setOpcode(ARM::t2LDRHpci);
3574 break;
3575 case ARM::t2LDRSHi12:
3576 Inst.setOpcode(ARM::t2LDRSHpci);
3577 break;
3578 case ARM::t2LDRBi12:
3579 Inst.setOpcode(ARM::t2LDRBpci);
3580 break;
3581 case ARM::t2LDRSBi12:
3582 Inst.setOpcode(ARM::t2LDRSBpci);
3583 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003584 case ARM::t2PLDi12:
3585 Inst.setOpcode(ARM::t2PLDpci);
3586 break;
3587 case ARM::t2PLIi12:
3588 Inst.setOpcode(ARM::t2PLIpci);
3589 break;
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003590 default:
3591 return MCDisassembler::Fail;
3592 }
3593 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3594 }
3595
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003596 if (Rt == 15) {
3597 switch (Inst.getOpcode()) {
3598 case ARM::t2LDRSHi12:
3599 return MCDisassembler::Fail;
3600 case ARM::t2LDRHi12:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003601 Inst.setOpcode(ARM::t2PLDWi12);
3602 break;
3603 case ARM::t2LDRSBi12:
3604 Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003605 break;
3606 default:
3607 break;
3608 }
3609 }
3610
3611 switch (Inst.getOpcode()) {
3612 case ARM::t2PLDi12:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003613 break;
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003614 case ARM::t2PLIi12:
3615 if (!hasV7Ops)
3616 return MCDisassembler::Fail;
3617 break;
3618 case ARM::t2PLDWi12:
3619 if (!hasV7Ops || !hasMP)
3620 return MCDisassembler::Fail;
3621 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003622 default:
3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3624 return MCDisassembler::Fail;
3625 }
3626
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003627 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3628 return MCDisassembler::Fail;
3629 return S;
3630}
3631
3632static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3633 uint64_t Address, const void* Decoder) {
3634 DecodeStatus S = MCDisassembler::Success;
3635
3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3637 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3638 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3639 imm |= (Rn << 9);
3640
3641 if (Rn == 15) {
3642 switch (Inst.getOpcode()) {
3643 case ARM::t2LDRT:
3644 Inst.setOpcode(ARM::t2LDRpci);
3645 break;
3646 case ARM::t2LDRBT:
3647 Inst.setOpcode(ARM::t2LDRBpci);
3648 break;
3649 case ARM::t2LDRHT:
3650 Inst.setOpcode(ARM::t2LDRHpci);
3651 break;
3652 case ARM::t2LDRSBT:
3653 Inst.setOpcode(ARM::t2LDRSBpci);
3654 break;
3655 case ARM::t2LDRSHT:
3656 Inst.setOpcode(ARM::t2LDRSHpci);
3657 break;
3658 default:
3659 return MCDisassembler::Fail;
3660 }
3661 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3662 }
3663
3664 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3665 return MCDisassembler::Fail;
3666 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668 return S;
3669}
3670
3671static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3672 uint64_t Address, const void* Decoder) {
3673 DecodeStatus S = MCDisassembler::Success;
3674
3675 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3676 unsigned U = fieldFromInstruction(Insn, 23, 1);
3677 int imm = fieldFromInstruction(Insn, 0, 12);
3678
Michael Kupersteindb0712f2015-05-26 10:47:10 +00003679 const FeatureBitset &featureBits =
3680 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3681
3682 bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003683
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003684 if (Rt == 15) {
3685 switch (Inst.getOpcode()) {
3686 case ARM::t2LDRBpci:
3687 case ARM::t2LDRHpci:
3688 Inst.setOpcode(ARM::t2PLDpci);
3689 break;
3690 case ARM::t2LDRSBpci:
3691 Inst.setOpcode(ARM::t2PLIpci);
3692 break;
3693 case ARM::t2LDRSHpci:
3694 return MCDisassembler::Fail;
3695 default:
3696 break;
3697 }
3698 }
3699
3700 switch(Inst.getOpcode()) {
3701 case ARM::t2PLDpci:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003702 break;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003703 case ARM::t2PLIpci:
Oliver Stannard39a85ab2014-10-23 08:52:58 +00003704 if (!hasV7Ops)
3705 return MCDisassembler::Fail;
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003706 break;
3707 default:
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3709 return MCDisassembler::Fail;
3710 }
3711
3712 if (!U) {
3713 // Special case for #-0.
3714 if (imm == 0)
3715 imm = INT32_MIN;
3716 else
3717 imm = -imm;
3718 }
Jim Grosbache9119e42015-05-13 18:37:00 +00003719 Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003720
3721 return S;
3722}
3723
Craig Topperf6e7e122012-03-27 07:21:54 +00003724static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003725 uint64_t Address, const void *Decoder) {
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003726 if (Val == 0)
Jim Grosbache9119e42015-05-13 18:37:00 +00003727 Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003728 else {
3729 int imm = Val & 0xFF;
3730
3731 if (!(Val & 0x100)) imm *= -1;
Jim Grosbache9119e42015-05-13 18:37:00 +00003732 Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu6a43bf72012-08-02 08:29:50 +00003733 }
Owen Andersone0152a72011-08-09 20:55:18 +00003734
James Molloydb4ce602011-09-01 18:02:14 +00003735 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003736}
3737
Craig Topperf6e7e122012-03-27 07:21:54 +00003738static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003739 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003740 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003741
Jim Grosbachecaef492012-08-14 19:06:05 +00003742 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3743 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Andersone0152a72011-08-09 20:55:18 +00003744
Owen Anderson03aadae2011-09-01 23:23:50 +00003745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746 return MCDisassembler::Fail;
3747 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3748 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003749
Owen Andersona4043c42011-08-17 17:44:15 +00003750 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003751}
3752
Craig Topperf6e7e122012-03-27 07:21:54 +00003753static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbacha05627e2011-09-09 18:37:27 +00003754 uint64_t Address, const void *Decoder) {
3755 DecodeStatus S = MCDisassembler::Success;
3756
Jim Grosbachecaef492012-08-14 19:06:05 +00003757 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3758 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbacha05627e2011-09-09 18:37:27 +00003759
3760 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3761 return MCDisassembler::Fail;
3762
Jim Grosbache9119e42015-05-13 18:37:00 +00003763 Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbacha05627e2011-09-09 18:37:27 +00003764
3765 return S;
3766}
3767
Craig Topperf6e7e122012-03-27 07:21:54 +00003768static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003769 uint64_t Address, const void *Decoder) {
Owen Andersone0152a72011-08-09 20:55:18 +00003770 int imm = Val & 0xFF;
Owen Andersonfe823652011-09-16 21:08:33 +00003771 if (Val == 0)
3772 imm = INT32_MIN;
3773 else if (!(Val & 0x100))
3774 imm *= -1;
Jim Grosbache9119e42015-05-13 18:37:00 +00003775 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003776
James Molloydb4ce602011-09-01 18:02:14 +00003777 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003778}
3779
Craig Topperf6e7e122012-03-27 07:21:54 +00003780static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003781 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003782 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003783
Jim Grosbachecaef492012-08-14 19:06:05 +00003784 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3785 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Andersone0152a72011-08-09 20:55:18 +00003786
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003787 // Thumb stores cannot use PC as dest register.
3788 switch (Inst.getOpcode()) {
3789 case ARM::t2STRT:
3790 case ARM::t2STRBT:
3791 case ARM::t2STRHT:
3792 case ARM::t2STRi8:
3793 case ARM::t2STRHi8:
3794 case ARM::t2STRBi8:
3795 if (Rn == 15)
3796 return MCDisassembler::Fail;
3797 break;
3798 default:
3799 break;
3800 }
3801
Owen Andersone0152a72011-08-09 20:55:18 +00003802 // Some instructions always use an additive offset.
3803 switch (Inst.getOpcode()) {
3804 case ARM::t2LDRT:
3805 case ARM::t2LDRBT:
3806 case ARM::t2LDRHT:
3807 case ARM::t2LDRSBT:
3808 case ARM::t2LDRSHT:
Owen Andersonddfcec92011-09-19 18:07:10 +00003809 case ARM::t2STRT:
3810 case ARM::t2STRBT:
3811 case ARM::t2STRHT:
Owen Andersone0152a72011-08-09 20:55:18 +00003812 imm |= 0x100;
3813 break;
3814 default:
3815 break;
3816 }
3817
Owen Anderson03aadae2011-09-01 23:23:50 +00003818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3819 return MCDisassembler::Fail;
3820 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3821 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003822
Owen Andersona4043c42011-08-17 17:44:15 +00003823 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003824}
3825
Craig Topperf6e7e122012-03-27 07:21:54 +00003826static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003827 uint64_t Address, const void *Decoder) {
3828 DecodeStatus S = MCDisassembler::Success;
3829
Jim Grosbachecaef492012-08-14 19:06:05 +00003830 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3831 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3832 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3833 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003834 addr |= Rn << 9;
Jim Grosbachecaef492012-08-14 19:06:05 +00003835 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003836
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003837 if (Rn == 15) {
3838 switch (Inst.getOpcode()) {
3839 case ARM::t2LDR_PRE:
3840 case ARM::t2LDR_POST:
3841 Inst.setOpcode(ARM::t2LDRpci);
3842 break;
3843 case ARM::t2LDRB_PRE:
3844 case ARM::t2LDRB_POST:
3845 Inst.setOpcode(ARM::t2LDRBpci);
3846 break;
3847 case ARM::t2LDRH_PRE:
3848 case ARM::t2LDRH_POST:
3849 Inst.setOpcode(ARM::t2LDRHpci);
3850 break;
3851 case ARM::t2LDRSB_PRE:
3852 case ARM::t2LDRSB_POST:
Amaury de la Vieuville4b6c0762013-06-24 09:11:38 +00003853 if (Rt == 15)
3854 Inst.setOpcode(ARM::t2PLIpci);
3855 else
3856 Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville4d3e3f22013-06-18 08:03:06 +00003857 break;
3858 case ARM::t2LDRSH_PRE:
3859 case ARM::t2LDRSH_POST:
3860 Inst.setOpcode(ARM::t2LDRSHpci);
3861 break;
3862 default:
3863 return MCDisassembler::Fail;
3864 }
3865 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3866 }
3867
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003868 if (!load) {
3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3870 return MCDisassembler::Fail;
3871 }
3872
Joe Abbeyf686be42013-03-26 13:58:53 +00003873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona9ebf6f2011-09-12 18:56:30 +00003874 return MCDisassembler::Fail;
3875
3876 if (load) {
3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3878 return MCDisassembler::Fail;
3879 }
3880
3881 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3882 return MCDisassembler::Fail;
3883
3884 return S;
3885}
Owen Andersone0152a72011-08-09 20:55:18 +00003886
Craig Topperf6e7e122012-03-27 07:21:54 +00003887static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003888 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003889 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003890
Jim Grosbachecaef492012-08-14 19:06:05 +00003891 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3892 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Andersone0152a72011-08-09 20:55:18 +00003893
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003894 // Thumb stores cannot use PC as dest register.
3895 switch (Inst.getOpcode()) {
3896 case ARM::t2STRi12:
3897 case ARM::t2STRBi12:
3898 case ARM::t2STRHi12:
3899 if (Rn == 15)
3900 return MCDisassembler::Fail;
Adrian Prantl0e6694d2017-12-19 22:05:25 +00003901 break;
Amaury de la Vieuvillee2bb1d12013-06-18 08:02:56 +00003902 default:
3903 break;
3904 }
3905
Owen Anderson03aadae2011-09-01 23:23:50 +00003906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3907 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003908 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003909
Owen Andersona4043c42011-08-17 17:44:15 +00003910 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003911}
3912
Craig Topperf6e7e122012-03-27 07:21:54 +00003913static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003914 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003915 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Andersone0152a72011-08-09 20:55:18 +00003916
Jim Grosbache9119e42015-05-13 18:37:00 +00003917 Inst.addOperand(MCOperand::createReg(ARM::SP));
3918 Inst.addOperand(MCOperand::createReg(ARM::SP));
3919 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00003920
James Molloydb4ce602011-09-01 18:02:14 +00003921 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003922}
3923
Craig Topperf6e7e122012-03-27 07:21:54 +00003924static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003925 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003926 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00003927
Owen Andersone0152a72011-08-09 20:55:18 +00003928 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003929 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3930 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Andersone0152a72011-08-09 20:55:18 +00003931
Owen Anderson03aadae2011-09-01 23:23:50 +00003932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3933 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003934 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson03aadae2011-09-01 23:23:50 +00003935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3936 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003937 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003938 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00003939
Jim Grosbache9119e42015-05-13 18:37:00 +00003940 Inst.addOperand(MCOperand::createReg(ARM::SP));
3941 Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson03aadae2011-09-01 23:23:50 +00003942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3943 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00003944 }
3945
Owen Andersona4043c42011-08-17 17:44:15 +00003946 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003947}
3948
Craig Topperf6e7e122012-03-27 07:21:54 +00003949static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003950 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00003951 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3952 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Andersone0152a72011-08-09 20:55:18 +00003953
Jim Grosbache9119e42015-05-13 18:37:00 +00003954 Inst.addOperand(MCOperand::createImm(imod));
3955 Inst.addOperand(MCOperand::createImm(flags));
Owen Andersone0152a72011-08-09 20:55:18 +00003956
James Molloydb4ce602011-09-01 18:02:14 +00003957 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003958}
3959
Craig Topperf6e7e122012-03-27 07:21:54 +00003960static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson5d69f632011-08-10 17:36:48 +00003961 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00003962 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00003963 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3964 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Andersone0152a72011-08-09 20:55:18 +00003965
Silviu Barangad213f212012-03-22 13:24:43 +00003966 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00003967 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00003968 Inst.addOperand(MCOperand::createImm(add));
Owen Andersone0152a72011-08-09 20:55:18 +00003969
Owen Andersona4043c42011-08-17 17:44:15 +00003970 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00003971}
3972
Craig Topperf6e7e122012-03-27 07:21:54 +00003973static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson5d69f632011-08-10 17:36:48 +00003974 uint64_t Address, const void *Decoder) {
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00003975 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby91422302012-05-03 22:41:56 +00003976 // Note only one trailing zero not two. Also the J1 and J2 values are from
3977 // the encoded instruction. So here change to I1 and I2 values via:
3978 // I1 = NOT(J1 EOR S);
3979 // I2 = NOT(J2 EOR S);
3980 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00003981 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby91422302012-05-03 22:41:56 +00003982 unsigned S = (Val >> 23) & 1;
3983 unsigned J1 = (Val >> 22) & 1;
3984 unsigned J2 = (Val >> 21) & 1;
3985 unsigned I1 = !(J1 ^ S);
3986 unsigned I2 = !(J2 ^ S);
3987 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3988 int imm32 = SignExtend32<25>(tmp << 1);
3989
Jim Grosbach79ebc512011-10-20 17:28:20 +00003990 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby91422302012-05-03 22:41:56 +00003991 (Address & ~2u) + imm32 + 4,
Kevin Enderby5dcda642011-10-04 22:44:48 +00003992 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00003993 Inst.addOperand(MCOperand::createImm(imm32));
James Molloydb4ce602011-09-01 18:02:14 +00003994 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00003995}
3996
Craig Topperf6e7e122012-03-27 07:21:54 +00003997static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00003998 uint64_t Address, const void *Decoder) {
3999 if (Val == 0xA || Val == 0xB)
James Molloydb4ce602011-09-01 18:02:14 +00004000 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00004001
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004002 const FeatureBitset &featureBits =
4003 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4004
4005 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
Artyom Skrobove686cec2013-11-08 16:16:30 +00004006 return MCDisassembler::Fail;
4007
Jim Grosbache9119e42015-05-13 18:37:00 +00004008 Inst.addOperand(MCOperand::createImm(Val));
James Molloydb4ce602011-09-01 18:02:14 +00004009 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004010}
4011
Owen Anderson03aadae2011-09-01 23:23:50 +00004012static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00004013DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach05541f42011-09-19 22:21:13 +00004014 uint64_t Address, const void *Decoder) {
4015 DecodeStatus S = MCDisassembler::Success;
4016
Jim Grosbachecaef492012-08-14 19:06:05 +00004017 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4018 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach05541f42011-09-19 22:21:13 +00004019
4020 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4022 return MCDisassembler::Fail;
4023 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4024 return MCDisassembler::Fail;
4025 return S;
4026}
4027
4028static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00004029DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00004030 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004031 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004032
Jim Grosbachecaef492012-08-14 19:06:05 +00004033 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Andersone0152a72011-08-09 20:55:18 +00004034 if (pred == 0xE || pred == 0xF) {
Jim Grosbachecaef492012-08-14 19:06:05 +00004035 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Andersone0152a72011-08-09 20:55:18 +00004036 switch (opc) {
4037 default:
James Molloydb4ce602011-09-01 18:02:14 +00004038 return MCDisassembler::Fail;
Owen Anderson4af0aa92011-08-31 22:00:41 +00004039 case 0xf3bf8f4:
Owen Andersone0152a72011-08-09 20:55:18 +00004040 Inst.setOpcode(ARM::t2DSB);
4041 break;
Owen Anderson4af0aa92011-08-31 22:00:41 +00004042 case 0xf3bf8f5:
Owen Andersone0152a72011-08-09 20:55:18 +00004043 Inst.setOpcode(ARM::t2DMB);
4044 break;
Owen Anderson4af0aa92011-08-31 22:00:41 +00004045 case 0xf3bf8f6:
Owen Andersone0152a72011-08-09 20:55:18 +00004046 Inst.setOpcode(ARM::t2ISB);
Owen Andersoncd5612d2011-09-07 17:55:19 +00004047 break;
Owen Andersone0152a72011-08-09 20:55:18 +00004048 }
4049
Jim Grosbachecaef492012-08-14 19:06:05 +00004050 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersone0089312011-08-09 23:25:42 +00004051 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Andersone0152a72011-08-09 20:55:18 +00004052 }
4053
Jim Grosbachecaef492012-08-14 19:06:05 +00004054 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4055 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4056 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4057 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4058 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Andersone0152a72011-08-09 20:55:18 +00004059
Owen Anderson03aadae2011-09-01 23:23:50 +00004060 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4061 return MCDisassembler::Fail;
4062 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4063 return MCDisassembler::Fail;
Owen Andersone0152a72011-08-09 20:55:18 +00004064
Owen Andersona4043c42011-08-17 17:44:15 +00004065 return S;
Owen Andersone0152a72011-08-09 20:55:18 +00004066}
4067
4068// Decode a shifted immediate operand. These basically consist
4069// of an 8-bit value, and a 4-bit directive that specifies either
4070// a splat operation or a rotation.
Craig Topperf6e7e122012-03-27 07:21:54 +00004071static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Andersone0152a72011-08-09 20:55:18 +00004072 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00004073 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Andersone0152a72011-08-09 20:55:18 +00004074 if (ctrl == 0) {
Jim Grosbachecaef492012-08-14 19:06:05 +00004075 unsigned byte = fieldFromInstruction(Val, 8, 2);
4076 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Andersone0152a72011-08-09 20:55:18 +00004077 switch (byte) {
4078 case 0:
Jim Grosbache9119e42015-05-13 18:37:00 +00004079 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004080 break;
4081 case 1:
Jim Grosbache9119e42015-05-13 18:37:00 +00004082 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004083 break;
4084 case 2:
Jim Grosbache9119e42015-05-13 18:37:00 +00004085 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
Owen Andersone0152a72011-08-09 20:55:18 +00004086 break;
4087 case 3:
Jim Grosbache9119e42015-05-13 18:37:00 +00004088 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
Owen Andersone0152a72011-08-09 20:55:18 +00004089 (imm << 8) | imm));
4090 break;
4091 }
4092 } else {
Jim Grosbachecaef492012-08-14 19:06:05 +00004093 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4094 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Andersone0152a72011-08-09 20:55:18 +00004095 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
Jim Grosbache9119e42015-05-13 18:37:00 +00004096 Inst.addOperand(MCOperand::createImm(imm));
Owen Andersone0152a72011-08-09 20:55:18 +00004097 }
4098
James Molloydb4ce602011-09-01 18:02:14 +00004099 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004100}
4101
Owen Anderson03aadae2011-09-01 23:23:50 +00004102static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00004103DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004104 uint64_t Address, const void *Decoder) {
Richard Bartonf1ef87d2012-06-06 09:12:53 +00004105 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby40d4e472012-04-12 23:13:34 +00004106 true, 2, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00004107 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloydb4ce602011-09-01 18:02:14 +00004108 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004109}
4110
Craig Topperf6e7e122012-03-27 07:21:54 +00004111static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004112 uint64_t Address,
4113 const void *Decoder) {
Kevin Enderby91422302012-05-03 22:41:56 +00004114 // Val is passed in as S:J1:J2:imm10:imm11
4115 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4116 // the encoded instruction. So here change to I1 and I2 values via:
4117 // I1 = NOT(J1 EOR S);
4118 // I2 = NOT(J2 EOR S);
4119 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi70c1aa02012-05-22 21:47:02 +00004120 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby91422302012-05-03 22:41:56 +00004121 unsigned S = (Val >> 23) & 1;
4122 unsigned J1 = (Val >> 22) & 1;
4123 unsigned J2 = (Val >> 21) & 1;
4124 unsigned I1 = !(J1 ^ S);
4125 unsigned I2 = !(J2 ^ S);
4126 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4127 int imm32 = SignExtend32<25>(tmp << 1);
4128
4129 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby6fbcd8d2012-02-23 18:18:17 +00004130 true, 4, Inst, Decoder))
Jim Grosbache9119e42015-05-13 18:37:00 +00004131 Inst.addOperand(MCOperand::createImm(imm32));
James Molloydb4ce602011-09-01 18:02:14 +00004132 return MCDisassembler::Success;
Owen Andersone0152a72011-08-09 20:55:18 +00004133}
4134
Craig Topperf6e7e122012-03-27 07:21:54 +00004135static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersone0089312011-08-09 23:25:42 +00004136 uint64_t Address, const void *Decoder) {
Jiangning Liu288e1af2012-08-02 08:21:27 +00004137 if (Val & ~0xf)
James Molloydb4ce602011-09-01 18:02:14 +00004138 return MCDisassembler::Fail;
Owen Andersone0089312011-08-09 23:25:42 +00004139
Jim Grosbache9119e42015-05-13 18:37:00 +00004140 Inst.addOperand(MCOperand::createImm(Val));
James Molloydb4ce602011-09-01 18:02:14 +00004141 return MCDisassembler::Success;
Owen Andersone0089312011-08-09 23:25:42 +00004142}
4143
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00004144static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4145 uint64_t Address, const void *Decoder) {
4146 if (Val & ~0xf)
4147 return MCDisassembler::Fail;
4148
Jim Grosbache9119e42015-05-13 18:37:00 +00004149 Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville43cb13a2013-06-10 14:17:08 +00004150 return MCDisassembler::Success;
4151}
4152
Craig Topperf6e7e122012-03-27 07:21:54 +00004153static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson60663402011-08-11 20:21:46 +00004154 uint64_t Address, const void *Decoder) {
Renato Golin92c816c2014-09-01 11:25:07 +00004155 DecodeStatus S = MCDisassembler::Success;
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004156 const FeatureBitset &FeatureBits =
4157 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4158
4159 if (FeatureBits[ARM::FeatureMClass]) {
James Molloy137ce602014-08-01 12:42:11 +00004160 unsigned ValLow = Val & 0xff;
4161
4162 // Validate the SYSm value first.
4163 switch (ValLow) {
4164 case 0: // apsr
4165 case 1: // iapsr
4166 case 2: // eapsr
4167 case 3: // xpsr
4168 case 5: // ipsr
4169 case 6: // epsr
4170 case 7: // iepsr
4171 case 8: // msp
4172 case 9: // psp
4173 case 16: // primask
4174 case 20: // control
4175 break;
4176 case 17: // basepri
4177 case 18: // basepri_max
4178 case 19: // faultmask
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004179 if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy137ce602014-08-01 12:42:11 +00004180 // Values basepri, basepri_max and faultmask are only valid for v7m.
4181 return MCDisassembler::Fail;
4182 break;
Bradley Smithf277c8a2016-01-25 11:25:36 +00004183 case 0x8a: // msplim_ns
4184 case 0x8b: // psplim_ns
4185 case 0x91: // basepri_ns
Bradley Smithf277c8a2016-01-25 11:25:36 +00004186 case 0x93: // faultmask_ns
4187 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4188 return MCDisassembler::Fail;
Justin Bognercd1d5aa2016-08-17 20:30:52 +00004189 LLVM_FALLTHROUGH;
Bradley Smithf277c8a2016-01-25 11:25:36 +00004190 case 10: // msplim
4191 case 11: // psplim
4192 case 0x88: // msp_ns
4193 case 0x89: // psp_ns
4194 case 0x90: // primask_ns
4195 case 0x94: // control_ns
4196 case 0x98: // sp_ns
4197 if (!(FeatureBits[ARM::Feature8MSecExt]))
4198 return MCDisassembler::Fail;
4199 break;
James Molloy137ce602014-08-01 12:42:11 +00004200 default:
Simi Pallipurath75c6bfe2018-03-06 15:21:19 +00004201 // Architecturally defined as unpredictable
4202 S = MCDisassembler::SoftFail;
4203 break;
James Molloy137ce602014-08-01 12:42:11 +00004204 }
4205
Renato Golin92c816c2014-09-01 11:25:07 +00004206 if (Inst.getOpcode() == ARM::t2MSR_M) {
4207 unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kupersteindb0712f2015-05-26 10:47:10 +00004208 if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin92c816c2014-09-01 11:25:07 +00004209 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4210 // unpredictable.
4211 if (Mask != 2)
4212 S = MCDisassembler::SoftFail;
4213 }
4214 else {
4215 // The ARMv7-M architecture stores an additional 2-bit mask value in
4216 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4217 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4218 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4219 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4220 // only if the processor includes the DSP extension.
4221 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
Artyom Skrobovcf296442015-09-24 17:31:16 +00004222 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
Renato Golin92c816c2014-09-01 11:25:07 +00004223 S = MCDisassembler::SoftFail;
4224 }
James Molloy137ce602014-08-01 12:42:11 +00004225 }
4226 } else {
4227 // A/R class
4228 if (Val == 0)
4229 return MCDisassembler::Fail;
4230 }
Jim Grosbache9119e42015-05-13 18:37:00 +00004231 Inst.addOperand(MCOperand::createImm(Val));
Renato Golin92c816c2014-09-01 11:25:07 +00004232 return S;
Owen Anderson60663402011-08-11 20:21:46 +00004233}
Owen Andersonb685c9f2011-08-11 21:34:58 +00004234
Tim Northoveree843ef2014-08-15 10:47:12 +00004235static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4236 uint64_t Address, const void *Decoder) {
Tim Northoveree843ef2014-08-15 10:47:12 +00004237 unsigned R = fieldFromInstruction(Val, 5, 1);
4238 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4239
4240 // The table of encodings for these banked registers comes from B9.2.3 of the
4241 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4242 // neater. So by fiat, these values are UNPREDICTABLE:
Oliver Stannard133b6082018-02-08 14:31:22 +00004243 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4244 return MCDisassembler::Fail;
Tim Northoveree843ef2014-08-15 10:47:12 +00004245
Jim Grosbache9119e42015-05-13 18:37:00 +00004246 Inst.addOperand(MCOperand::createImm(Val));
Tim Northoveree843ef2014-08-15 10:47:12 +00004247 return MCDisassembler::Success;
4248}
4249
Craig Topperf6e7e122012-03-27 07:21:54 +00004250static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachd14b70d2011-08-17 21:58:18 +00004251 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004252 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004253
Jim Grosbachecaef492012-08-14 19:06:05 +00004254 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4255 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4256 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004257
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004258 if (Rn == 0xF)
4259 S = MCDisassembler::SoftFail;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004260
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004261 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004262 return MCDisassembler::Fail;
4263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4264 return MCDisassembler::Fail;
4265 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4266 return MCDisassembler::Fail;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004267
Owen Andersona4043c42011-08-17 17:44:15 +00004268 return S;
Owen Andersonc5798a3a52011-08-12 17:58:32 +00004269}
4270
Craig Topperf6e7e122012-03-27 07:21:54 +00004271static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00004272 uint64_t Address,
4273 const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004274 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004275
Jim Grosbachecaef492012-08-14 19:06:05 +00004276 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4277 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonb685c9f2011-08-11 21:34:58 +00004280
Tim Northover27ff5042013-04-19 15:44:32 +00004281 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004282 return MCDisassembler::Fail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004283
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004284 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4285 S = MCDisassembler::SoftFail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004286
Amaury de la Vieuville53ff0292013-06-11 08:03:20 +00004287 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson03aadae2011-09-01 23:23:50 +00004288 return MCDisassembler::Fail;
4289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4290 return MCDisassembler::Fail;
4291 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4292 return MCDisassembler::Fail;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004293
Owen Andersona4043c42011-08-17 17:44:15 +00004294 return S;
Owen Andersonb685c9f2011-08-11 21:34:58 +00004295}
4296
Craig Topperf6e7e122012-03-27 07:21:54 +00004297static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +00004298 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004299 DecodeStatus S = MCDisassembler::Success;
Owen Anderson16d33f32011-08-26 20:43:14 +00004300
Jim Grosbachecaef492012-08-14 19:06:05 +00004301 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4302 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4303 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4304 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4305 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4306 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson16d33f32011-08-26 20:43:14 +00004307
James Molloydb4ce602011-09-01 18:02:14 +00004308 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004309
Owen Anderson03aadae2011-09-01 23:23:50 +00004310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4311 return MCDisassembler::Fail;
4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4313 return MCDisassembler::Fail;
4314 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4315 return MCDisassembler::Fail;
4316 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4317 return MCDisassembler::Fail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004318
4319 return S;
4320}
4321
Craig Topperf6e7e122012-03-27 07:21:54 +00004322static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson16d33f32011-08-26 20:43:14 +00004323 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004324 DecodeStatus S = MCDisassembler::Success;
Owen Anderson16d33f32011-08-26 20:43:14 +00004325
Jim Grosbachecaef492012-08-14 19:06:05 +00004326 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4327 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4328 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4329 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4330 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4331 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4332 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson16d33f32011-08-26 20:43:14 +00004333
James Molloydb4ce602011-09-01 18:02:14 +00004334 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4335 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004336
Owen Anderson03aadae2011-09-01 23:23:50 +00004337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4338 return MCDisassembler::Fail;
4339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4340 return MCDisassembler::Fail;
4341 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4342 return MCDisassembler::Fail;
4343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4344 return MCDisassembler::Fail;
Owen Anderson16d33f32011-08-26 20:43:14 +00004345
4346 return S;
4347}
4348
Craig Topperf6e7e122012-03-27 07:21:54 +00004349static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +00004350 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004351 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004352
Jim Grosbachecaef492012-08-14 19:06:05 +00004353 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4354 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4355 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4356 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4357 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4358 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersonb685c9f2011-08-11 21:34:58 +00004359
James Molloydb4ce602011-09-01 18:02:14 +00004360 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson3987a612011-08-12 18:12:39 +00004361
Owen Anderson03aadae2011-09-01 23:23:50 +00004362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4363 return MCDisassembler::Fail;
4364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4365 return MCDisassembler::Fail;
4366 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4367 return MCDisassembler::Fail;
4368 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4369 return MCDisassembler::Fail;
Owen Anderson3987a612011-08-12 18:12:39 +00004370
Owen Andersona4043c42011-08-17 17:44:15 +00004371 return S;
Owen Anderson3987a612011-08-12 18:12:39 +00004372}
4373
Craig Topperf6e7e122012-03-27 07:21:54 +00004374static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson3987a612011-08-12 18:12:39 +00004375 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004376 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004377
Jim Grosbachecaef492012-08-14 19:06:05 +00004378 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4379 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4380 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4381 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4382 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4383 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3987a612011-08-12 18:12:39 +00004384
James Molloydb4ce602011-09-01 18:02:14 +00004385 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson3987a612011-08-12 18:12:39 +00004386
Owen Anderson03aadae2011-09-01 23:23:50 +00004387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4388 return MCDisassembler::Fail;
4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4390 return MCDisassembler::Fail;
4391 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4392 return MCDisassembler::Fail;
4393 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4394 return MCDisassembler::Fail;
Owen Anderson3987a612011-08-12 18:12:39 +00004395
Owen Andersona4043c42011-08-17 17:44:15 +00004396 return S;
Owen Anderson3987a612011-08-12 18:12:39 +00004397}
Owen Andersonb9d82f42011-08-15 18:44:44 +00004398
Craig Topperf6e7e122012-03-27 07:21:54 +00004399static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004400 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004401 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004402
Jim Grosbachecaef492012-08-14 19:06:05 +00004403 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4404 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4405 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4406 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4407 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004408
4409 unsigned align = 0;
4410 unsigned index = 0;
4411 switch (size) {
4412 default:
James Molloydb4ce602011-09-01 18:02:14 +00004413 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004414 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004415 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004416 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004417 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004418 break;
4419 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004420 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004421 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004422 index = fieldFromInstruction(Insn, 6, 2);
4423 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004424 align = 2;
4425 break;
4426 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004427 if (fieldFromInstruction(Insn, 6, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004428 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004429 index = fieldFromInstruction(Insn, 7, 1);
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004430
4431 switch (fieldFromInstruction(Insn, 4, 2)) {
4432 case 0 :
4433 align = 0; break;
4434 case 3:
4435 align = 4; break;
4436 default:
4437 return MCDisassembler::Fail;
4438 }
4439 break;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004440 }
4441
Owen Anderson03aadae2011-09-01 23:23:50 +00004442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4443 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004444 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4446 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004447 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4449 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004450 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004451 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004452 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4454 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004455 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004456 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004457 }
4458
Owen Anderson03aadae2011-09-01 23:23:50 +00004459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4460 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004461 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004462
Owen Andersona4043c42011-08-17 17:44:15 +00004463 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004464}
4465
Craig Topperf6e7e122012-03-27 07:21:54 +00004466static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004467 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004468 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004469
Jim Grosbachecaef492012-08-14 19:06:05 +00004470 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4471 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4472 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4473 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4474 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004475
4476 unsigned align = 0;
4477 unsigned index = 0;
4478 switch (size) {
4479 default:
James Molloydb4ce602011-09-01 18:02:14 +00004480 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004481 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004482 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004483 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004484 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004485 break;
4486 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004487 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004488 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004489 index = fieldFromInstruction(Insn, 6, 2);
4490 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004491 align = 2;
4492 break;
4493 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004494 if (fieldFromInstruction(Insn, 6, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004495 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004496 index = fieldFromInstruction(Insn, 7, 1);
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004497
4498 switch (fieldFromInstruction(Insn, 4, 2)) {
Fangrui Songf78650a2018-07-30 19:41:25 +00004499 case 0:
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004500 align = 0; break;
4501 case 3:
4502 align = 4; break;
4503 default:
4504 return MCDisassembler::Fail;
4505 }
4506 break;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004507 }
4508
4509 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4511 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004512 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4514 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004515 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004516 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004517 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4519 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004520 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004521 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004522 }
4523
Owen Anderson03aadae2011-09-01 23:23:50 +00004524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4525 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004526 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004527
Owen Andersona4043c42011-08-17 17:44:15 +00004528 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004529}
4530
Craig Topperf6e7e122012-03-27 07:21:54 +00004531static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004532 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004533 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004534
Jim Grosbachecaef492012-08-14 19:06:05 +00004535 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4536 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4537 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4538 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4539 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004540
4541 unsigned align = 0;
4542 unsigned index = 0;
4543 unsigned inc = 1;
4544 switch (size) {
4545 default:
James Molloydb4ce602011-09-01 18:02:14 +00004546 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004547 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004548 index = fieldFromInstruction(Insn, 5, 3);
4549 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004550 align = 2;
4551 break;
4552 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004553 index = fieldFromInstruction(Insn, 6, 2);
4554 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004555 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004556 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004557 inc = 2;
4558 break;
4559 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004560 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004561 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004562 index = fieldFromInstruction(Insn, 7, 1);
4563 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Andersonb9d82f42011-08-15 18:44:44 +00004564 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004565 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004566 inc = 2;
4567 break;
4568 }
4569
Owen Anderson03aadae2011-09-01 23:23:50 +00004570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4571 return MCDisassembler::Fail;
4572 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4573 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004574 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004577 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004580 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004581 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004582 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4584 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004585 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004586 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004587 }
4588
Owen Anderson03aadae2011-09-01 23:23:50 +00004589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4590 return MCDisassembler::Fail;
4591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4592 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004593 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004594
Owen Andersona4043c42011-08-17 17:44:15 +00004595 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004596}
4597
Craig Topperf6e7e122012-03-27 07:21:54 +00004598static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004599 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004600 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004601
Jim Grosbachecaef492012-08-14 19:06:05 +00004602 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4603 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4604 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4605 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4606 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004607
4608 unsigned align = 0;
4609 unsigned index = 0;
4610 unsigned inc = 1;
4611 switch (size) {
4612 default:
James Molloydb4ce602011-09-01 18:02:14 +00004613 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004614 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004615 index = fieldFromInstruction(Insn, 5, 3);
4616 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004617 align = 2;
4618 break;
4619 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004620 index = fieldFromInstruction(Insn, 6, 2);
4621 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004622 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004623 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004624 inc = 2;
4625 break;
4626 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004627 if (fieldFromInstruction(Insn, 5, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004628 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004629 index = fieldFromInstruction(Insn, 7, 1);
4630 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Andersonb9d82f42011-08-15 18:44:44 +00004631 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004632 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004633 inc = 2;
4634 break;
4635 }
4636
4637 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4639 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004640 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4642 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004643 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004644 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004645 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4647 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004648 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004649 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004650 }
4651
Owen Anderson03aadae2011-09-01 23:23:50 +00004652 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4653 return MCDisassembler::Fail;
4654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4655 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004656 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004657
Owen Andersona4043c42011-08-17 17:44:15 +00004658 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004659}
4660
Craig Topperf6e7e122012-03-27 07:21:54 +00004661static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004662 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004663 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004664
Jim Grosbachecaef492012-08-14 19:06:05 +00004665 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4666 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4667 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4668 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4669 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004670
4671 unsigned align = 0;
4672 unsigned index = 0;
4673 unsigned inc = 1;
4674 switch (size) {
4675 default:
James Molloydb4ce602011-09-01 18:02:14 +00004676 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004677 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004678 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004679 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004680 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004681 break;
4682 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004683 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004684 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004685 index = fieldFromInstruction(Insn, 6, 2);
4686 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004687 inc = 2;
4688 break;
4689 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004690 if (fieldFromInstruction(Insn, 4, 2))
James Molloydb4ce602011-09-01 18:02:14 +00004691 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004692 index = fieldFromInstruction(Insn, 7, 1);
4693 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004694 inc = 2;
4695 break;
4696 }
4697
Owen Anderson03aadae2011-09-01 23:23:50 +00004698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4699 return MCDisassembler::Fail;
4700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4701 return MCDisassembler::Fail;
4702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4703 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004704
4705 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4707 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004708 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4710 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004711 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson2fa06a72011-08-30 22:58:27 +00004712 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004713 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4715 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004716 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004717 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004718 }
4719
Owen Anderson03aadae2011-09-01 23:23:50 +00004720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4721 return MCDisassembler::Fail;
4722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4723 return MCDisassembler::Fail;
4724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4725 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004726 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004727
Owen Andersona4043c42011-08-17 17:44:15 +00004728 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004729}
4730
Craig Topperf6e7e122012-03-27 07:21:54 +00004731static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004732 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004733 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004734
Jim Grosbachecaef492012-08-14 19:06:05 +00004735 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4736 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4737 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4738 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4739 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004740
4741 unsigned align = 0;
4742 unsigned index = 0;
4743 unsigned inc = 1;
4744 switch (size) {
4745 default:
James Molloydb4ce602011-09-01 18:02:14 +00004746 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004747 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004748 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004749 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004750 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004751 break;
4752 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004753 if (fieldFromInstruction(Insn, 4, 1))
James Molloydb4ce602011-09-01 18:02:14 +00004754 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004755 index = fieldFromInstruction(Insn, 6, 2);
4756 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004757 inc = 2;
4758 break;
4759 case 2:
Jim Grosbachecaef492012-08-14 19:06:05 +00004760 if (fieldFromInstruction(Insn, 4, 2))
James Molloydb4ce602011-09-01 18:02:14 +00004761 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachecaef492012-08-14 19:06:05 +00004762 index = fieldFromInstruction(Insn, 7, 1);
4763 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004764 inc = 2;
4765 break;
4766 }
4767
4768 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4770 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004771 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4773 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004774 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004775 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004776 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4778 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004779 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004780 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004781 }
4782
Owen Anderson03aadae2011-09-01 23:23:50 +00004783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4784 return MCDisassembler::Fail;
4785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4786 return MCDisassembler::Fail;
4787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4788 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004789 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004790
Owen Andersona4043c42011-08-17 17:44:15 +00004791 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004792}
4793
Craig Topperf6e7e122012-03-27 07:21:54 +00004794static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004795 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004796 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004797
Jim Grosbachecaef492012-08-14 19:06:05 +00004798 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4799 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4800 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4801 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4802 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004803
4804 unsigned align = 0;
4805 unsigned index = 0;
4806 unsigned inc = 1;
4807 switch (size) {
4808 default:
James Molloydb4ce602011-09-01 18:02:14 +00004809 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004810 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004811 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004812 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004813 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004814 break;
4815 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004816 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004817 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004818 index = fieldFromInstruction(Insn, 6, 2);
4819 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004820 inc = 2;
4821 break;
4822 case 2:
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004823 switch (fieldFromInstruction(Insn, 4, 2)) {
4824 case 0:
4825 align = 0; break;
4826 case 3:
4827 return MCDisassembler::Fail;
4828 default:
4829 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4830 }
4831
Jim Grosbachecaef492012-08-14 19:06:05 +00004832 index = fieldFromInstruction(Insn, 7, 1);
4833 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004834 inc = 2;
4835 break;
4836 }
4837
Owen Anderson03aadae2011-09-01 23:23:50 +00004838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4839 return MCDisassembler::Fail;
4840 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4841 return MCDisassembler::Fail;
4842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4843 return MCDisassembler::Fail;
4844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4845 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004846
4847 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4849 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004850 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4852 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004853 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004854 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004855 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4857 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004858 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004859 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004860 }
4861
Owen Anderson03aadae2011-09-01 23:23:50 +00004862 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4863 return MCDisassembler::Fail;
4864 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4865 return MCDisassembler::Fail;
4866 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4867 return MCDisassembler::Fail;
4868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4869 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004870 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004871
Owen Andersona4043c42011-08-17 17:44:15 +00004872 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004873}
4874
Craig Topperf6e7e122012-03-27 07:21:54 +00004875static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Andersonb9d82f42011-08-15 18:44:44 +00004876 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004877 DecodeStatus S = MCDisassembler::Success;
Owen Andersona4043c42011-08-17 17:44:15 +00004878
Jim Grosbachecaef492012-08-14 19:06:05 +00004879 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4880 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4881 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4882 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4883 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004884
4885 unsigned align = 0;
4886 unsigned index = 0;
4887 unsigned inc = 1;
4888 switch (size) {
4889 default:
James Molloydb4ce602011-09-01 18:02:14 +00004890 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004891 case 0:
Jim Grosbachecaef492012-08-14 19:06:05 +00004892 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004893 align = 4;
Jim Grosbachecaef492012-08-14 19:06:05 +00004894 index = fieldFromInstruction(Insn, 5, 3);
Owen Andersonb9d82f42011-08-15 18:44:44 +00004895 break;
4896 case 1:
Jim Grosbachecaef492012-08-14 19:06:05 +00004897 if (fieldFromInstruction(Insn, 4, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004898 align = 8;
Jim Grosbachecaef492012-08-14 19:06:05 +00004899 index = fieldFromInstruction(Insn, 6, 2);
4900 if (fieldFromInstruction(Insn, 5, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004901 inc = 2;
4902 break;
4903 case 2:
Tim Northoverfb3cdd82012-09-06 15:17:49 +00004904 switch (fieldFromInstruction(Insn, 4, 2)) {
4905 case 0:
4906 align = 0; break;
4907 case 3:
4908 return MCDisassembler::Fail;
4909 default:
4910 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4911 }
4912
Jim Grosbachecaef492012-08-14 19:06:05 +00004913 index = fieldFromInstruction(Insn, 7, 1);
4914 if (fieldFromInstruction(Insn, 6, 1))
Owen Andersonb9d82f42011-08-15 18:44:44 +00004915 inc = 2;
4916 break;
4917 }
4918
4919 if (Rm != 0xF) { // Writeback
Owen Anderson03aadae2011-09-01 23:23:50 +00004920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4921 return MCDisassembler::Fail;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004922 }
Owen Anderson03aadae2011-09-01 23:23:50 +00004923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4924 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004925 Inst.addOperand(MCOperand::createImm(align));
Owen Anderson721c3702011-08-22 18:42:13 +00004926 if (Rm != 0xF) {
James Molloydb4ce602011-09-01 18:02:14 +00004927 if (Rm != 0xD) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4929 return MCDisassembler::Fail;
James Molloydb4ce602011-09-01 18:02:14 +00004930 } else
Jim Grosbache9119e42015-05-13 18:37:00 +00004931 Inst.addOperand(MCOperand::createReg(0));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004932 }
4933
Owen Anderson03aadae2011-09-01 23:23:50 +00004934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4935 return MCDisassembler::Fail;
4936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4937 return MCDisassembler::Fail;
4938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4939 return MCDisassembler::Fail;
4940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4941 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00004942 Inst.addOperand(MCOperand::createImm(index));
Owen Andersonb9d82f42011-08-15 18:44:44 +00004943
Owen Andersona4043c42011-08-17 17:44:15 +00004944 return S;
Owen Andersonb9d82f42011-08-15 18:44:44 +00004945}
4946
Craig Topperf6e7e122012-03-27 07:21:54 +00004947static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +00004948 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004949 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00004950 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4951 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4952 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4953 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4954 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Andersondf698b02011-08-22 20:27:12 +00004955
4956 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloydb4ce602011-09-01 18:02:14 +00004957 S = MCDisassembler::SoftFail;
Owen Andersondf698b02011-08-22 20:27:12 +00004958
Owen Anderson03aadae2011-09-01 23:23:50 +00004959 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4960 return MCDisassembler::Fail;
4961 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4962 return MCDisassembler::Fail;
4963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4964 return MCDisassembler::Fail;
4965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4966 return MCDisassembler::Fail;
4967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4968 return MCDisassembler::Fail;
Owen Andersondf698b02011-08-22 20:27:12 +00004969
4970 return S;
4971}
4972
Craig Topperf6e7e122012-03-27 07:21:54 +00004973static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Andersondf698b02011-08-22 20:27:12 +00004974 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00004975 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00004976 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4977 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4978 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4979 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4980 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Andersondf698b02011-08-22 20:27:12 +00004981
4982 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloydb4ce602011-09-01 18:02:14 +00004983 S = MCDisassembler::SoftFail;
Owen Andersondf698b02011-08-22 20:27:12 +00004984
Owen Anderson03aadae2011-09-01 23:23:50 +00004985 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4986 return MCDisassembler::Fail;
4987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4988 return MCDisassembler::Fail;
4989 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4990 return MCDisassembler::Fail;
4991 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4992 return MCDisassembler::Fail;
4993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4994 return MCDisassembler::Fail;
Owen Andersondf698b02011-08-22 20:27:12 +00004995
4996 return S;
4997}
Owen Andersoneb1367b2011-08-22 23:44:04 +00004998
Craig Topperf6e7e122012-03-27 07:21:54 +00004999static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson2fa06a72011-08-30 22:58:27 +00005000 uint64_t Address, const void *Decoder) {
Owen Anderson03aadae2011-09-01 23:23:50 +00005001 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachecaef492012-08-14 19:06:05 +00005002 unsigned pred = fieldFromInstruction(Insn, 4, 4);
5003 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson2fa06a72011-08-30 22:58:27 +00005004
5005 if (pred == 0xF) {
5006 pred = 0xE;
James Molloydb4ce602011-09-01 18:02:14 +00005007 S = MCDisassembler::SoftFail;
Owen Anderson52300412011-08-24 17:21:43 +00005008 }
5009
Amaury de la Vieuville2f0ac8d2013-06-24 09:11:45 +00005010 if (mask == 0x0)
5011 return MCDisassembler::Fail;
Owen Anderson2fa06a72011-08-30 22:58:27 +00005012
Jim Grosbache9119e42015-05-13 18:37:00 +00005013 Inst.addOperand(MCOperand::createImm(pred));
5014 Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson37612a32011-08-24 22:40:22 +00005015 return S;
5016}
Jim Grosbach7db8d692011-09-08 22:07:06 +00005017
5018static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00005019DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +00005020 uint64_t Address, const void *Decoder) {
5021 DecodeStatus S = MCDisassembler::Success;
5022
Jim Grosbachecaef492012-08-14 19:06:05 +00005023 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5024 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5025 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5026 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5027 unsigned W = fieldFromInstruction(Insn, 21, 1);
5028 unsigned U = fieldFromInstruction(Insn, 23, 1);
5029 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach7db8d692011-09-08 22:07:06 +00005030 bool writeback = (W == 1) | (P == 0);
5031
5032 addr |= (U << 8) | (Rn << 9);
5033
5034 if (writeback && (Rn == Rt || Rn == Rt2))
5035 Check(S, MCDisassembler::SoftFail);
5036 if (Rt == Rt2)
5037 Check(S, MCDisassembler::SoftFail);
5038
5039 // Rt
5040 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5041 return MCDisassembler::Fail;
5042 // Rt2
5043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5044 return MCDisassembler::Fail;
5045 // Writeback operand
5046 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5047 return MCDisassembler::Fail;
5048 // addr
5049 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5050 return MCDisassembler::Fail;
5051
5052 return S;
5053}
5054
5055static DecodeStatus
Craig Topperf6e7e122012-03-27 07:21:54 +00005056DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach7db8d692011-09-08 22:07:06 +00005057 uint64_t Address, const void *Decoder) {
5058 DecodeStatus S = MCDisassembler::Success;
5059
Jim Grosbachecaef492012-08-14 19:06:05 +00005060 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5061 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5062 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5063 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5064 unsigned W = fieldFromInstruction(Insn, 21, 1);
5065 unsigned U = fieldFromInstruction(Insn, 23, 1);
5066 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach7db8d692011-09-08 22:07:06 +00005067 bool writeback = (W == 1) | (P == 0);
5068
5069 addr |= (U << 8) | (Rn << 9);
5070
5071 if (writeback && (Rn == Rt || Rn == Rt2))
5072 Check(S, MCDisassembler::SoftFail);
5073
5074 // Writeback operand
5075 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5076 return MCDisassembler::Fail;
5077 // Rt
5078 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5079 return MCDisassembler::Fail;
5080 // Rt2
5081 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5082 return MCDisassembler::Fail;
5083 // addr
5084 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5085 return MCDisassembler::Fail;
5086
5087 return S;
5088}
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005089
Craig Topperf6e7e122012-03-27 07:21:54 +00005090static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005091 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00005092 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5093 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005094 if (sign1 != sign2) return MCDisassembler::Fail;
5095
Jim Grosbachecaef492012-08-14 19:06:05 +00005096 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5097 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5098 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005099 Val |= sign1 << 12;
Jim Grosbache9119e42015-05-13 18:37:00 +00005100 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson5bfb0e02011-09-09 22:24:36 +00005101
5102 return MCDisassembler::Success;
5103}
5104
Craig Topperf6e7e122012-03-27 07:21:54 +00005105static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Andersonf01e2de2011-09-26 21:06:22 +00005106 uint64_t Address,
5107 const void *Decoder) {
5108 DecodeStatus S = MCDisassembler::Success;
5109
5110 // Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith3131e852015-01-19 16:37:17 +00005111 if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005112 Inst.addOperand(MCOperand::createImm(Val));
Owen Andersonf01e2de2011-09-26 21:06:22 +00005113 return S;
5114}
5115
Craig Topperf6e7e122012-03-27 07:21:54 +00005116static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersondde461c2011-10-28 18:02:13 +00005117 uint64_t Address, const void *Decoder) {
Jim Grosbachecaef492012-08-14 19:06:05 +00005118 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5119 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5120 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5121 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersondde461c2011-10-28 18:02:13 +00005122
5123 if (pred == 0xF)
5124 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5125
5126 DecodeStatus S = MCDisassembler::Success;
Silviu Barangaca45af92012-04-18 14:18:57 +00005127
5128 if (Rt == Rn || Rn == Rt2)
5129 S = MCDisassembler::SoftFail;
5130
Owen Andersondde461c2011-10-28 18:02:13 +00005131 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5132 return MCDisassembler::Fail;
5133 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5134 return MCDisassembler::Fail;
5135 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5136 return MCDisassembler::Fail;
5137 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5138 return MCDisassembler::Fail;
5139
5140 return S;
5141}
Owen Anderson0ac90582011-11-15 19:55:00 +00005142
Craig Topperf6e7e122012-03-27 07:21:54 +00005143static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +00005144 uint64_t Address, const void *Decoder) {
Oliver Stannard2de8c162015-12-16 12:37:39 +00005145 const FeatureBitset &featureBits =
5146 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5147 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5148
Jim Grosbachecaef492012-08-14 19:06:05 +00005149 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5150 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5151 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5152 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5153 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5154 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuvillef4ec0c852013-06-08 13:54:05 +00005155 unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson0ac90582011-11-15 19:55:00 +00005156
5157 DecodeStatus S = MCDisassembler::Success;
5158
Oliver Stannard2de8c162015-12-16 12:37:39 +00005159 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5160 if (!(imm & 0x38)) {
5161 if (cmode == 0xF) {
5162 if (op == 1) return MCDisassembler::Fail;
5163 Inst.setOpcode(ARM::VMOVv2f32);
5164 }
5165 if (hasFullFP16) {
5166 if (cmode == 0xE) {
5167 if (op == 1) {
5168 Inst.setOpcode(ARM::VMOVv1i64);
5169 } else {
5170 Inst.setOpcode(ARM::VMOVv8i8);
5171 }
5172 }
5173 if (cmode == 0xD) {
5174 if (op == 1) {
5175 Inst.setOpcode(ARM::VMVNv2i32);
5176 } else {
5177 Inst.setOpcode(ARM::VMOVv2i32);
5178 }
5179 }
5180 if (cmode == 0xC) {
5181 if (op == 1) {
5182 Inst.setOpcode(ARM::VMVNv2i32);
5183 } else {
5184 Inst.setOpcode(ARM::VMOVv2i32);
5185 }
5186 }
5187 }
Owen Anderson0ac90582011-11-15 19:55:00 +00005188 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5189 }
5190
Amaury de la Vieuvilleea7bb572013-06-08 13:29:11 +00005191 if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson0ac90582011-11-15 19:55:00 +00005192
5193 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5194 return MCDisassembler::Fail;
5195 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5196 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005197 Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson0ac90582011-11-15 19:55:00 +00005198
5199 return S;
5200}
5201
Craig Topperf6e7e122012-03-27 07:21:54 +00005202static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson0ac90582011-11-15 19:55:00 +00005203 uint64_t Address, const void *Decoder) {
Oliver Stannard2de8c162015-12-16 12:37:39 +00005204 const FeatureBitset &featureBits =
5205 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5206 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5207
Jim Grosbachecaef492012-08-14 19:06:05 +00005208 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5209 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5210 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5211 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5212 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5213 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuvillef4ec0c852013-06-08 13:54:05 +00005214 unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson0ac90582011-11-15 19:55:00 +00005215
5216 DecodeStatus S = MCDisassembler::Success;
5217
Oliver Stannard2de8c162015-12-16 12:37:39 +00005218 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5219 if (!(imm & 0x38)) {
5220 if (cmode == 0xF) {
5221 if (op == 1) return MCDisassembler::Fail;
5222 Inst.setOpcode(ARM::VMOVv4f32);
5223 }
5224 if (hasFullFP16) {
5225 if (cmode == 0xE) {
5226 if (op == 1) {
5227 Inst.setOpcode(ARM::VMOVv2i64);
5228 } else {
5229 Inst.setOpcode(ARM::VMOVv16i8);
5230 }
5231 }
5232 if (cmode == 0xD) {
5233 if (op == 1) {
5234 Inst.setOpcode(ARM::VMVNv4i32);
5235 } else {
5236 Inst.setOpcode(ARM::VMOVv4i32);
5237 }
5238 }
5239 if (cmode == 0xC) {
5240 if (op == 1) {
5241 Inst.setOpcode(ARM::VMVNv4i32);
5242 } else {
5243 Inst.setOpcode(ARM::VMOVv4i32);
5244 }
5245 }
5246 }
Owen Anderson0ac90582011-11-15 19:55:00 +00005247 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5248 }
5249
Amaury de la Vieuvilleea7bb572013-06-08 13:29:11 +00005250 if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson0ac90582011-11-15 19:55:00 +00005251
5252 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5253 return MCDisassembler::Fail;
5254 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5255 return MCDisassembler::Fail;
Jim Grosbache9119e42015-05-13 18:37:00 +00005256 Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson0ac90582011-11-15 19:55:00 +00005257
5258 return S;
5259}
Silviu Barangad213f212012-03-22 13:24:43 +00005260
Sam Parker963da5b2017-09-29 13:11:33 +00005261static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5262 unsigned Insn,
5263 uint64_t Address,
5264 const void *Decoder) {
5265 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5266 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5267 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5268 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5269 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5270 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5271 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5272 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5273
5274 DecodeStatus S = MCDisassembler::Success;
5275
5276 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5277
5278 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5279 return MCDisassembler::Fail;
5280 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5281 return MCDisassembler::Fail;
5282 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5283 return MCDisassembler::Fail;
5284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5285 return MCDisassembler::Fail;
5286 // The lane index does not have any bits in the encoding, because it can only
5287 // be 0.
5288 Inst.addOperand(MCOperand::createImm(0));
5289 Inst.addOperand(MCOperand::createImm(rotate));
5290
5291 return S;
5292}
5293
Craig Topperf6e7e122012-03-27 07:21:54 +00005294static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangad213f212012-03-22 13:24:43 +00005295 uint64_t Address, const void *Decoder) {
5296 DecodeStatus S = MCDisassembler::Success;
5297
Jim Grosbachecaef492012-08-14 19:06:05 +00005298 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5299 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5300 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5301 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5302 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Vinicius Tinti67cf33d2015-11-20 23:20:12 +00005303
Jim Grosbachecaef492012-08-14 19:06:05 +00005304 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangad213f212012-03-22 13:24:43 +00005305 S = MCDisassembler::SoftFail;
5306
5307 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5308 return MCDisassembler::Fail;
5309 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5310 return MCDisassembler::Fail;
Fangrui Songf78650a2018-07-30 19:41:25 +00005311 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
Silviu Barangad213f212012-03-22 13:24:43 +00005312 return MCDisassembler::Fail;
5313 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5314 return MCDisassembler::Fail;
5315 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5316 return MCDisassembler::Fail;
5317
5318 return S;
5319}
5320
Eugene Zelenkoe79c0772017-01-27 23:58:02 +00005321static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005322 uint64_t Address, const void *Decoder) {
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005323 DecodeStatus S = MCDisassembler::Success;
5324
Jim Grosbachecaef492012-08-14 19:06:05 +00005325 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5326 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5327 unsigned cop = fieldFromInstruction(Val, 8, 4);
5328 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5329 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005330
5331 if ((cop & ~0x1) == 0xa)
5332 return MCDisassembler::Fail;
5333
5334 if (Rt == Rt2)
5335 S = MCDisassembler::SoftFail;
5336
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005337 // We have to check if the instruction is MRRC2
5338 // or MCRR2 when constructing the operands for
5339 // Inst. Reason is because MRRC2 stores to two
5340 // registers so it's tablegen desc has has two
5341 // outputs whereas MCRR doesn't store to any
5342 // registers so all of it's operands are listed
5343 // as inputs, therefore the operand order for
5344 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5345 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5346
5347 if (Inst.getOpcode() == ARM::MRRC2) {
5348 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5349 return MCDisassembler::Fail;
5350 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5351 return MCDisassembler::Fail;
5352 }
Jim Grosbache9119e42015-05-13 18:37:00 +00005353 Inst.addOperand(MCOperand::createImm(cop));
5354 Inst.addOperand(MCOperand::createImm(opc1));
Ranjeet Singh39d2d092016-06-17 00:52:41 +00005355 if (Inst.getOpcode() == ARM::MCRR2) {
5356 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5357 return MCDisassembler::Fail;
5358 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5359 return MCDisassembler::Fail;
5360 }
Jim Grosbache9119e42015-05-13 18:37:00 +00005361 Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga41f1fcd2012-04-18 13:12:50 +00005362
5363 return S;
5364}
Andre Vieira640527f2017-09-22 12:17:42 +00005365
5366static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5367 uint64_t Address,
5368 const void *Decoder) {
5369 const FeatureBitset &featureBits =
5370 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5371 DecodeStatus S = MCDisassembler::Success;
5372
Simon Tatham67065c52019-06-10 15:58:19 +00005373 unsigned Rt = fieldFromInstruction(Val, 12, 4);
Andre Vieira640527f2017-09-22 12:17:42 +00005374
Simon Tatham67065c52019-06-10 15:58:19 +00005375 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5376 if (Rt == 13 || Rt == 15)
5377 S = MCDisassembler::SoftFail;
5378 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5379 } else
5380 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
Andre Vieira640527f2017-09-22 12:17:42 +00005381
Andre Vieirad4a25702017-10-18 14:47:37 +00005382 if (featureBits[ARM::ModeThumb]) {
5383 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5384 Inst.addOperand(MCOperand::createReg(0));
5385 } else {
5386 unsigned pred = fieldFromInstruction(Val, 28, 4);
5387 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5388 return MCDisassembler::Fail;
5389 }
Andre Vieira640527f2017-09-22 12:17:42 +00005390
5391 return S;
5392}