Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Eugene Zelenko	076468c	2017-09-20 21:35:51 +0000	[diff] [blame]	1	//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	10	#include "MCTargetDesc/ARMAddressingModes.h"
				11	#include "MCTargetDesc/ARMBaseInfo.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	12	#include "MCTargetDesc/ARMMCTargetDesc.h"
Eugene Zelenko	076468c	2017-09-20 21:35:51 +0000	[diff] [blame]	13	#include "Utils/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	15	#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	20	#include "llvm/MC/SubtargetFeature.h"
				21	#include "llvm/Support/Compiler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/ErrorHandling.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	23	#include "llvm/Support/MathExtras.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	24	#include "llvm/Support/TargetRegistry.h"
Chandler Carruth	6bda14b	2017-06-06 11:49:48 +0000	[diff] [blame]	25	#include "llvm/Support/raw_ostream.h"
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	26	#include <algorithm>
				27	#include <cassert>
				28	#include <cstdint>
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	29	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	30
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	31	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	32
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	33	#define DEBUG_TYPE "arm-disassembler"
				34
Eugene Zelenko	076468c	2017-09-20 21:35:51 +0000	[diff] [blame]	35	using DecodeStatus = MCDisassembler::DecodeStatus;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	36
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	37	namespace {
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	38
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	39	// Handles the condition code status of instructions in IT blocks
				40	class ITStatus
				41	{
				42	public:
				43	// Returns the condition code for instruction in IT block
				44	unsigned getITCC() {
				45	unsigned CC = ARMCC::AL;
				46	if (instrInITBlock())
				47	CC = ITStates.back();
				48	return CC;
				49	}
				50
				51	// Advances the IT block state to the next T or E
				52	void advanceITState() {
				53	ITStates.pop_back();
				54	}
				55
				56	// Returns true if the current instruction is in an IT block
				57	bool instrInITBlock() {
				58	return !ITStates.empty();
				59	}
				60
				61	// Returns true if current instruction is the last instruction in an IT block
				62	bool instrLastInITBlock() {
				63	return ITStates.size() == 1;
				64	}
				65
				66	// Called when decoding an IT instruction. Sets the IT state for the following
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	67	// instructions that for the IT block. Firstcond and Mask correspond to the
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	68	// fields in the IT instruction encoding.
				69	void setITState(char Firstcond, char Mask) {
				70	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	71	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	72	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	73	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				74	assert(NumTZ <= 3 && "Invalid IT mask!");
				75	// push condition codes onto the stack the correct order for the pops
				76	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				77	bool T = ((Mask >> Pos) & 1) == CondBit0;
				78	if (T)
				79	ITStates.push_back(CCBits);
				80	else
				81	ITStates.push_back(CCBits ^ 1);
				82	}
				83	ITStates.push_back(CCBits);
				84	}
				85
				86	private:
				87	std::vector<unsigned char> ITStates;
				88	};
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	89
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	90	/// ARM disassembler for all ARM platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	91	class ARMDisassembler : public MCDisassembler {
				92	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				94	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	97	~ARMDisassembler() override = default;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	98
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	99	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	100	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	101	raw_ostream &VStream,
				102	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	103	};
				104
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	105	/// Thumb disassembler for all Thumb platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	106	class ThumbDisassembler : public MCDisassembler {
				107	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	108	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				109	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	110	}
				111
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	112	~ThumbDisassembler() override = default;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	113
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	114	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	115	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	116	raw_ostream &VStream,
				117	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	118
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	119	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	120	mutable ITStatus ITBlock;
Eugene Zelenko	076468c	2017-09-20 21:35:51 +0000	[diff] [blame]	121
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	122	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	123	void UpdateThumbVFPPredicate(MCInst&) const;
				124	};
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	125
				126	} // end anonymous namespace
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	127
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	128	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	129	switch (In) {
				130	case MCDisassembler::Success:
				131	// Out stays the same.
				132	return true;
				133	case MCDisassembler::SoftFail:
				134	Out = In;
				135	return true;
				136	case MCDisassembler::Fail:
				137	Out = In;
				138	return false;
				139	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	140	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	141	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	142
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	143	// Forward declare these because the autogenerated code will reference them.
				144	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	145	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	146	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	147	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	148	unsigned RegNo, uint64_t Address,
				149	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	150	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				151	unsigned RegNo, uint64_t Address,
				152	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	153	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	154	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	155	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	156	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	157	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	158	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				160	uint64_t Address, const void *Decoder);
Sjoerd Meijer	011de9c	2018-01-26 09:26:40 +0000	[diff] [blame]	161	static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
				162	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	164	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	165	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	166	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	167	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	169	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	170	unsigned RegNo,
				171	uint64_t Address,
				172	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	173	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	174	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	175	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	177	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	178	unsigned RegNo, uint64_t Address,
				179	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	180
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	181	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	183	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	185	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	186	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	187	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	188	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	189	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	190	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	191
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	197	unsigned Insn,
				198	uint64_t Address,
				199	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	202	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	203	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	204	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	205	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	206	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	207	uint64_t Address, const void *Decoder);
				208
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	unsigned Insn,
				211	uint64_t Adddress,
				212	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	217	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	218	uint64_t Address, const void *Decoder);
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	219	static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
				220	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	221	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	223	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				224	uint64_t Address, const void *Decoder);
				225	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				226	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	227	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	228	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	229	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	231	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	232	uint64_t Address, const void *Decoder);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	233	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				234	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	235	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	236	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	237	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				238	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	239	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	240	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	241	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	242	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	243	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				244	uint64_t Address, const void *Decoder);
				245	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				246	uint64_t Address, const void *Decoder);
				247	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				248	uint64_t Address, const void *Decoder);
				249	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				250	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	251	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	252	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	253	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	254	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	255	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	256	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	257	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	258	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	259	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	260	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	261	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	262	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	263	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	264	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	265	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	266	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	267	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	268	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	269	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	270	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	271	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	272	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	273	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	274	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	275	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	276	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	277	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	278	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	279	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	280	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	281	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	282	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	283	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				284	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	285	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	286	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	287	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				288	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	289	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	290	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	291	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	292	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	293	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	294	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	295	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	296	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	297	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	298	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	299	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	300	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	301	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	302	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	303	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	304	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	305	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	306	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	307	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	308	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	309	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	310	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	311	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	312	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	313	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	314	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	315	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	316	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	317	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	318	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	319	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	320	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	321	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	322	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	323	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	324	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	325	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	326	uint64_t Address, const void *Decoder);
Sam Parker	963da5b	2017-09-29 13:11:33 +0000	[diff] [blame]	327	static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
				328	unsigned Val,
				329	uint64_t Address,
				330	const void *Decoder);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	331
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	352	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				353	uint64_t Address, const void* Decoder);
				354	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				355	uint64_t Address, const void* Decoder);
				356	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				357	uint64_t Address, const void* Decoder);
				358	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				359	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	376	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	398	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	399	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	400	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	401	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	402	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	403	uint64_t Address, const void *Decoder);
				404
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	405	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	406	uint64_t Address, const void *Decoder);
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	407	static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	408	uint64_t Address, const void *Decoder);
Andre Vieira	640527f	2017-09-22 12:17:42 +0000	[diff] [blame]	409	static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
				410	uint64_t Address, const void *Decoder);
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	411
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	412	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	413
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	414	static MCDisassembler *createARMDisassembler(const Target &T,
				415	const MCSubtargetInfo &STI,
				416	MCContext &Ctx) {
				417	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	418	}
				419
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	420	static MCDisassembler *createThumbDisassembler(const Target &T,
				421	const MCSubtargetInfo &STI,
				422	MCContext &Ctx) {
				423	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	424	}
				425
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	426	// Post-decoding checks
				427	static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
				428	uint64_t Address, raw_ostream &OS,
				429	raw_ostream &CS,
				430	uint32_t Insn,
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	431	DecodeStatus Result) {
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	432	switch (MI.getOpcode()) {
				433	case ARM::HVC: {
				434	// HVC is undefined if condition = 0xf otherwise upredictable
				435	// if condition != 0xe
				436	uint32_t Cond = (Insn >> 28) & 0xF;
				437	if (Cond == 0xF)
				438	return MCDisassembler::Fail;
				439	if (Cond != 0xE)
				440	return MCDisassembler::SoftFail;
				441	return Result;
				442	}
				443	default: return Result;
				444	}
				445	}
				446
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	447	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	448	ArrayRef<uint8_t> Bytes,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	449	uint64_t Address, raw_ostream &OS,
				450	raw_ostream &CS) const {
				451	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	452
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	453	assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	454	"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
				455	"mode!");
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	456
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	457	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	458	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	459	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	460	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	461	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	462
				463	// Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	464	uint32_t Insn =
				465	(Bytes[3] << 24) \| (Bytes[2] << 16) \| (Bytes[1] << 8) \| (Bytes[0] << 0);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	466
				467	// Calling the auto-generated decoder function.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	468	DecodeStatus Result =
				469	decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
				470	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	471	Size = 4;
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	472	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	473	}
				474
Sjoerd Meijer	aea3a99	2017-03-13 09:41:10 +0000	[diff] [blame]	475	struct DecodeTable {
				476	const uint8_t *P;
				477	bool DecodePred;
				478	};
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	479
Sjoerd Meijer	aea3a99	2017-03-13 09:41:10 +0000	[diff] [blame]	480	const DecodeTable Tables[] = {
				481	{DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
				482	{DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
				483	{DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
				484	{DecoderTablev8Crypto32, false},
				485	};
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	486
Sjoerd Meijer	aea3a99	2017-03-13 09:41:10 +0000	[diff] [blame]	487	for (auto Table : Tables) {
				488	Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
				489	if (Result != MCDisassembler::Fail) {
				490	Size = 4;
				491	// Add a fake predicate operand, because we share these instruction
				492	// definitions with Thumb2 where these instructions are predicable.
				493	if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
				494	return MCDisassembler::Fail;
				495	return Result;
				496	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	497	}
				498
Sjoerd Meijer	7426c97	2017-08-11 09:52:30 +0000	[diff] [blame]	499	Result =
				500	decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
				501	if (Result != MCDisassembler::Fail) {
				502	Size = 4;
				503	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
				504	}
				505
Eugene Leviant	6269d39	2017-06-29 15:38:47 +0000	[diff] [blame]	506	Size = 4;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	507	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	508	}
				509
				510	namespace llvm {
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	511
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	512	extern const MCInstrDesc ARMInsts[];
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	513
				514	} // end namespace llvm
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	515
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	516	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				517	/// immediate Value in the MCInst. The immediate Value has had any PC
				518	/// adjustment made by the caller. If the instruction is a branch instruction
				519	/// then isBranch is true, else false. If the getOpInfo() function was set as
				520	/// part of the setupForSymbolicDisassembly() call then that function is called
				521	/// to get any symbolic information at the Address for this instruction. If
				522	/// that returns non-zero then the symbolic information it returns is used to
				523	/// create an MCExpr and that is added as an operand to the MCInst. If
				524	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				525	/// Value is done and if a symbol is found an MCExpr is created with that, else
				526	/// an MCExpr with Value is created. This function returns true if it adds an
				527	/// operand to the MCInst and false otherwise.
				528	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				529	bool isBranch, uint64_t InstSize,
				530	MCInst &MI, const void *Decoder) {
				531	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	532	// FIXME: Does it make sense for value to be negative?
				533	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				534	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	535	}
				536
				537	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				538	/// referenced by a load instruction with the base register that is the Pc.
				539	/// These can often be values in a literal pool near the Address of the
				540	/// instruction. The Address of the instruction and its immediate Value are
				541	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	542	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	543	/// the referenced address is that of a symbol. Or it will return a pointer to
				544	/// a literal 'C' string if the referenced address of the literal pool's entry
				545	/// is an address into a section with 'C' string literals.
				546	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	547	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	548	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	549	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	550	}
				551
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	552	// Thumb1 instructions don't have explicit S bits. Rather, they
				553	// implicitly set CPSR. Since it's not represented in the encoding, the
				554	// auto-generated decoder won't inject the CPSR operand. We need to fix
				555	// that as a post-pass.
				556	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				557	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	558	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	559	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	560	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				561	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	562	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	563	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	564	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	565	return;
				566	}
				567	}
				568
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	569	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	570	}
				571
				572	// Most Thumb instructions don't have explicit predicates in the
				573	// encoding, but rather get their predicates from IT context. We need
				574	// to fix up the predicate operands using this context information as a
				575	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	576	MCDisassembler::DecodeStatus
				577	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	578	MCDisassembler::DecodeStatus S = Success;
				579
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	580	const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
				581
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	582	// A few instructions actually have predicates encoded in them. Don't
				583	// try to overwrite it if we're seeing one of those.
				584	switch (MI.getOpcode()) {
				585	case ARM::tBcc:
				586	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	587	case ARM::tCBZ:
				588	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	589	case ARM::tCPS:
				590	case ARM::t2CPS3p:
				591	case ARM::t2CPS2p:
				592	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	593	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	594	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	595	// Some instructions (mostly conditional branches) are not
				596	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	597	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	598	S = SoftFail;
				599	else
				600	return Success;
				601	break;
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	602	case ARM::t2HINT:
				603	if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
				604	S = SoftFail;
				605	break;
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	606	case ARM::tB:
				607	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	608	case ARM::t2TBB:
				609	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	610	// Some instructions (mostly unconditional branches) can
				611	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	612	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	613	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	614	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	615	default:
				616	break;
				617	}
				618
				619	// If we're in an IT block, base the predicate on that. Otherwise,
				620	// assume a predicate of AL.
				621	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	622	CC = ITBlock.getITCC();
				623	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	624	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	625	if (ITBlock.instrInITBlock())
				626	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	627
				628	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	629	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	630	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	631	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				632	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	633	if (OpInfo[i].isPredicate()) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	634	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	635	++I;
				636	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	637	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	638	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	639	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	640	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	641	}
				642	}
				643
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	644	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	645	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	646	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	647	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	648	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	649	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	650
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	651	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	652	}
				653
				654	// Thumb VFP instructions are a special case. Because we share their
				655	// encodings between ARM and Thumb modes, and they are predicable in ARM
				656	// mode, the auto-generated decoder will give them an (incorrect)
				657	// predicate operand. We need to rewrite these operands based on the IT
				658	// context as a post-pass.
				659	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				660	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	661	CC = ITBlock.getITCC();
				662	if (ITBlock.instrInITBlock())
				663	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	664
				665	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				666	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	667	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				668	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	669	if (OpInfo[i].isPredicate() ) {
				670	I->setImm(CC);
				671	++I;
				672	if (CC == ARMCC::AL)
				673	I->setReg(0);
				674	else
				675	I->setReg(ARM::CPSR);
				676	return;
				677	}
				678	}
				679	}
				680
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	681	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	682	ArrayRef<uint8_t> Bytes,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	683	uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	684	raw_ostream &OS,
				685	raw_ostream &CS) const {
				686	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	687
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	688	assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	689	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				690
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	691	// We want to read exactly 2 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	692	if (Bytes.size() < 2) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	693	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	694	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	695	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	696
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	697	uint16_t Insn16 = (Bytes[1] << 8) \| Bytes[0];
				698	DecodeStatus Result =
				699	decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
				700	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	701	Size = 2;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	702	Check(Result, AddThumbPredicate(MI));
				703	return Result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	704	}
				705
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	706	Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
				707	STI);
				708	if (Result) {
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	709	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	710	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	711	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	712	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	713	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	714	}
				715
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	716	Result =
				717	decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
				718	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	719	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	720
				721	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				722	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	723	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	724	Result = MCDisassembler::SoftFail;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	725
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	726	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	727
				728	// If we find an IT instruction, we need to parse its condition
				729	// code and mask operands so that we can apply them correctly
				730	// to the subsequent instructions.
				731	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	732
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	733	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	734	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	735	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	}
				737
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	738	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	739	}
				740
				741	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	742	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	743	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	744	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	745	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	746
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	747	uint32_t Insn32 =
				748	(Bytes[3] << 8) \| (Bytes[2] << 0) \| (Bytes[1] << 24) \| (Bytes[0] << 16);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	749	Result =
				750	decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
				751	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	752	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	753	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	754	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	755	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	756	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	757	}
				758
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	759	Result =
				760	decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
				761	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	762	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	763	Check(Result, AddThumbPredicate(MI));
				764	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	765	}
				766
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	767	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	768	Result =
				769	decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
				770	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	771	Size = 4;
				772	UpdateThumbVFPPredicate(MI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	773	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	774	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	775	}
				776
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	777	Result =
				778	decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
				779	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	780	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	781	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	782	}
				783
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	784	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	785	Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
				786	STI);
				787	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	788	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	789	Check(Result, AddThumbPredicate(MI));
				790	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	791	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	792	}
				793
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	794	if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	795	uint32_t NEONLdStInsn = Insn32;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	796	NEONLdStInsn &= 0xF0FFFFFF;
				797	NEONLdStInsn \|= 0x04000000;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	798	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	799	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	800	if (Result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	801	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	802	Check(Result, AddThumbPredicate(MI));
				803	return Result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	804	}
				805	}
				806
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	807	if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	808	uint32_t NEONDataInsn = Insn32;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	809	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				810	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				811	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	812	Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	813	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	814	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	815	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	816	Check(Result, AddThumbPredicate(MI));
				817	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	818	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	819
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	820	uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	821	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				822	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				823	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	824	Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	825	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	826	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	827	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	828	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	829	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	830
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	831	uint32_t NEONv8Insn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	832	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	833	Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	834	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	835	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	836	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	837	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	838	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	839	}
				840
Sjoerd Meijer	7426c97	2017-08-11 09:52:30 +0000	[diff] [blame]	841	Result =
				842	decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
				843	if (Result != MCDisassembler::Fail) {
				844	Size = 4;
				845	Check(Result, AddThumbPredicate(MI));
				846	return Result;
				847	}
				848
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	849	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	850	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	851	}
				852
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	853	extern "C" void LLVMInitializeARMDisassembler() {
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame]	854	TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	855	createARMDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame]	856	TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	857	createARMDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame]	858	TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	859	createThumbDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame]	860	TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	861	createThumbDisassembler);
				862	}
				863
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	864	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	865	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				866	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				867	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				868	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				869	};
				870
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	871	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	872	uint64_t Address, const void *Decoder) {
				873	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	874	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	875
				876	unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	877	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	878	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	879	}
				880
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	881	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	882	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	883	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	884	DecodeStatus S = MCDisassembler::Success;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	885
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	886	if (RegNo == 15)
				887	S = MCDisassembler::SoftFail;
				888
				889	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				890
				891	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	892	}
				893
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	894	static DecodeStatus
				895	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				896	uint64_t Address, const void *Decoder) {
				897	DecodeStatus S = MCDisassembler::Success;
				898
				899	if (RegNo == 15)
				900	{
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	901	Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	902	return MCDisassembler::Success;
				903	}
				904
				905	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				906	return S;
				907	}
				908
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	909	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	910	uint64_t Address, const void *Decoder) {
				911	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	912	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	913	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				914	}
				915
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	916	static const uint16_t GPRPairDecoderTable[] = {
				917	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				918	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				919	};
				920
				921	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				922	uint64_t Address, const void *Decoder) {
				923	DecodeStatus S = MCDisassembler::Success;
				924
				925	if (RegNo > 13)
				926	return MCDisassembler::Fail;
				927
				928	if ((RegNo & 1) \|\| RegNo == 0xe)
				929	S = MCDisassembler::SoftFail;
				930
				931	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	932	Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	933	return S;
				934	}
				935
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	936	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	937	uint64_t Address, const void *Decoder) {
				938	unsigned Register = 0;
				939	switch (RegNo) {
				940	case 0:
				941	Register = ARM::R0;
				942	break;
				943	case 1:
				944	Register = ARM::R1;
				945	break;
				946	case 2:
				947	Register = ARM::R2;
				948	break;
				949	case 3:
				950	Register = ARM::R3;
				951	break;
				952	case 9:
				953	Register = ARM::R9;
				954	break;
				955	case 12:
				956	Register = ARM::R12;
				957	break;
				958	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	959	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	960	}
				961
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	962	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	963	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	964	}
				965
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	966	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	967	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	968	DecodeStatus S = MCDisassembler::Success;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	969
				970	const FeatureBitset &featureBits =
				971	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				972
				973	if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) \|\| RegNo == 15)
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	974	S = MCDisassembler::SoftFail;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	975
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	976	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				977	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	978	}
				979
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	980	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	981	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				982	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				983	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				984	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				985	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				986	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				987	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				988	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				989	};
				990
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	991	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	992	uint64_t Address, const void *Decoder) {
				993	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	994	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	995
				996	unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	997	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	998	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	999	}
				1000
Sjoerd Meijer	011de9c	2018-01-26 09:26:40 +0000	[diff] [blame]	1001	static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
				1002	uint64_t Address, const void *Decoder) {
				1003	return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
				1004	}
				1005
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1006	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1007	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1008	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1009	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1010	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1011	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1012	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1013	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1014	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1015	};
				1016
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1017	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1018	uint64_t Address, const void *Decoder) {
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1019	const FeatureBitset &featureBits =
				1020	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1021
				1022	bool hasD16 = featureBits[ARM::FeatureD16];
Oliver Stannard	9e89d8c	2014-11-05 12:06:39 +0000	[diff] [blame]	1023
				1024	if (RegNo > 31 \|\| (hasD16 && RegNo > 15))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1025	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1026
				1027	unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1028	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1029	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1030	}
				1031
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1032	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1033	uint64_t Address, const void *Decoder) {
				1034	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1035	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1036	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1037	}
				1038
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1039	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1040	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1041	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1042	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1043	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1044	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1045	}
				1046
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1047	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1048	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1049	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1050	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1051	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1052	};
				1053
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1054	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1055	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1056	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1057	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1058	RegNo >>= 1;
				1059
				1060	unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1061	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1062	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1063	}
				1064
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1065	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1066	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1067	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1068	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1069	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1070	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1071	ARM::Q15
				1072	};
				1073
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1074	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1075	uint64_t Address, const void *Decoder) {
				1076	if (RegNo > 30)
				1077	return MCDisassembler::Fail;
				1078
				1079	unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1080	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1081	return MCDisassembler::Success;
				1082	}
				1083
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1084	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1085	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1086	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1087	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1088	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1089	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1090	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1091	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1092	ARM::D28_D30, ARM::D29_D31
				1093	};
				1094
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1095	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1096	unsigned RegNo,
				1097	uint64_t Address,
				1098	const void *Decoder) {
				1099	if (RegNo > 29)
				1100	return MCDisassembler::Fail;
				1101
				1102	unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1103	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1104	return MCDisassembler::Success;
				1105	}
				1106
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1107	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1108	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1109	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1110	// AL predicate is not allowed on Thumb1 branches.
				1111	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1112	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1113	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1114	if (Val == ARMCC::AL) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1115	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1116	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1117	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1118	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1119	}
				1120
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1121	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	uint64_t Address, const void *Decoder) {
				1123	if (Val)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1124	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1126	Inst.addOperand(MCOperand::createReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1127	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	}
				1129
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1130	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1131	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1132	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1133
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1134	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1135	unsigned type = fieldFromInstruction(Val, 5, 2);
				1136	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1137
				1138	// Register-immediate
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	1139	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1140	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1141
				1142	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1143	switch (type) {
				1144	case 0:
				1145	Shift = ARM_AM::lsl;
				1146	break;
				1147	case 1:
				1148	Shift = ARM_AM::lsr;
				1149	break;
				1150	case 2:
				1151	Shift = ARM_AM::asr;
				1152	break;
				1153	case 3:
				1154	Shift = ARM_AM::ror;
				1155	break;
				1156	}
				1157
				1158	if (Shift == ARM_AM::ror && imm == 0)
				1159	Shift = ARM_AM::rrx;
				1160
				1161	unsigned Op = Shift \| (imm << 3);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1162	Inst.addOperand(MCOperand::createImm(Op));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1163
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1164	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1165	}
				1166
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1167	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1168	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1169	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1170
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1171	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1172	unsigned type = fieldFromInstruction(Val, 5, 2);
				1173	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1174
				1175	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1176	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1177	return MCDisassembler::Fail;
				1178	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1179	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
				1181	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1182	switch (type) {
				1183	case 0:
				1184	Shift = ARM_AM::lsl;
				1185	break;
				1186	case 1:
				1187	Shift = ARM_AM::lsr;
				1188	break;
				1189	case 2:
				1190	Shift = ARM_AM::asr;
				1191	break;
				1192	case 3:
				1193	Shift = ARM_AM::ror;
				1194	break;
				1195	}
				1196
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1197	Inst.addOperand(MCOperand::createImm(Shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1198
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1199	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1200	}
				1201
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1202	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1203	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1204	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1205
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1206	bool NeedDisjointWriteback = false;
				1207	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1208	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1209	default:
				1210	break;
				1211	case ARM::LDMIA_UPD:
				1212	case ARM::LDMDB_UPD:
				1213	case ARM::LDMIB_UPD:
				1214	case ARM::LDMDA_UPD:
				1215	case ARM::t2LDMIA_UPD:
				1216	case ARM::t2LDMDB_UPD:
				1217	case ARM::t2STMIA_UPD:
				1218	case ARM::t2STMDB_UPD:
				1219	NeedDisjointWriteback = true;
				1220	WritebackReg = Inst.getOperand(0).getReg();
				1221	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1222	}
				1223
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1224	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1225	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1226	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1227	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1228	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1229	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1230	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1231	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1232	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1233	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1234	}
				1235
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1236	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	}
				1238
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1239	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1240	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1241	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1242
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1243	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1244	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1245
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1246	// In case of unpredictable encoding, tweak the operands.
				1247	if (regs == 0 \|\| (Vd + regs) > 32) {
				1248	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1249	regs = std::max( 1u, regs);
				1250	S = MCDisassembler::SoftFail;
				1251	}
				1252
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1253	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1254	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1255	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1256	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1257	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1258	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1259
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1260	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1261	}
				1262
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1263	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1264	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1266
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1267	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1268	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1269
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1270	// In case of unpredictable encoding, tweak the operands.
				1271	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1272	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1273	regs = std::max( 1u, regs);
				1274	regs = std::min(16u, regs);
				1275	S = MCDisassembler::SoftFail;
				1276	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1277
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1278	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1279	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1280	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1281	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1282	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1283	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1284
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1285	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1286	}
				1287
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1288	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1289	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1290	// This operand encodes a mask of contiguous zeros between a specified MSB
				1291	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1292	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1293	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1294	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1295	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1296	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1297
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1298	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1299	if (lsb > msb) {
				1300	Check(S, MCDisassembler::SoftFail);
				1301	// The check above will cause the warning for the "potentially undefined
				1302	// instruction encoding" but we can't build a bad MCOperand value here
				1303	// with a lsb > msb or else printing the MCInst will cause a crash.
				1304	lsb = msb;
				1305	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1306
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1307	uint32_t msb_mask = 0xFFFFFFFF;
				1308	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1309	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1310
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1311	Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1312	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1313	}
				1314
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1315	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1316	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1317	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1318
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1319	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1320	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1321	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1322	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1323	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1324	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1325
				1326	switch (Inst.getOpcode()) {
				1327	case ARM::LDC_OFFSET:
				1328	case ARM::LDC_PRE:
				1329	case ARM::LDC_POST:
				1330	case ARM::LDC_OPTION:
				1331	case ARM::LDCL_OFFSET:
				1332	case ARM::LDCL_PRE:
				1333	case ARM::LDCL_POST:
				1334	case ARM::LDCL_OPTION:
				1335	case ARM::STC_OFFSET:
				1336	case ARM::STC_PRE:
				1337	case ARM::STC_POST:
				1338	case ARM::STC_OPTION:
				1339	case ARM::STCL_OFFSET:
				1340	case ARM::STCL_PRE:
				1341	case ARM::STCL_POST:
				1342	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1343	case ARM::t2LDC_OFFSET:
				1344	case ARM::t2LDC_PRE:
				1345	case ARM::t2LDC_POST:
				1346	case ARM::t2LDC_OPTION:
				1347	case ARM::t2LDCL_OFFSET:
				1348	case ARM::t2LDCL_PRE:
				1349	case ARM::t2LDCL_POST:
				1350	case ARM::t2LDCL_OPTION:
				1351	case ARM::t2STC_OFFSET:
				1352	case ARM::t2STC_PRE:
				1353	case ARM::t2STC_POST:
				1354	case ARM::t2STC_OPTION:
				1355	case ARM::t2STCL_OFFSET:
				1356	case ARM::t2STCL_PRE:
				1357	case ARM::t2STCL_POST:
				1358	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1359	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1360	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1361	break;
				1362	default:
				1363	break;
				1364	}
				1365
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1366	const FeatureBitset &featureBits =
				1367	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1368	if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1369	return MCDisassembler::Fail;
				1370
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1371	Inst.addOperand(MCOperand::createImm(coproc));
				1372	Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1373	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1374	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1375
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1376	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1377	case ARM::t2LDC2_OFFSET:
				1378	case ARM::t2LDC2L_OFFSET:
				1379	case ARM::t2LDC2_PRE:
				1380	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1381	case ARM::t2STC2_OFFSET:
				1382	case ARM::t2STC2L_OFFSET:
				1383	case ARM::t2STC2_PRE:
				1384	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1385	case ARM::LDC2_OFFSET:
				1386	case ARM::LDC2L_OFFSET:
				1387	case ARM::LDC2_PRE:
				1388	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1389	case ARM::STC2_OFFSET:
				1390	case ARM::STC2L_OFFSET:
				1391	case ARM::STC2_PRE:
				1392	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1393	case ARM::t2LDC_OFFSET:
				1394	case ARM::t2LDCL_OFFSET:
				1395	case ARM::t2LDC_PRE:
				1396	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1397	case ARM::t2STC_OFFSET:
				1398	case ARM::t2STCL_OFFSET:
				1399	case ARM::t2STC_PRE:
				1400	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1401	case ARM::LDC_OFFSET:
				1402	case ARM::LDCL_OFFSET:
				1403	case ARM::LDC_PRE:
				1404	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1405	case ARM::STC_OFFSET:
				1406	case ARM::STCL_OFFSET:
				1407	case ARM::STC_PRE:
				1408	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1409	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1410	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1411	break;
				1412	case ARM::t2LDC2_POST:
				1413	case ARM::t2LDC2L_POST:
				1414	case ARM::t2STC2_POST:
				1415	case ARM::t2STC2L_POST:
				1416	case ARM::LDC2_POST:
				1417	case ARM::LDC2L_POST:
				1418	case ARM::STC2_POST:
				1419	case ARM::STC2L_POST:
				1420	case ARM::t2LDC_POST:
				1421	case ARM::t2LDCL_POST:
				1422	case ARM::t2STC_POST:
				1423	case ARM::t2STCL_POST:
				1424	case ARM::LDC_POST:
				1425	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1426	case ARM::STC_POST:
				1427	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1428	imm \|= U << 8;
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	1429	LLVM_FALLTHROUGH;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1430	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1431	// The 'option' variant doesn't encode 'U' in the immediate since
				1432	// the immediate is unsigned [0,255].
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1433	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1434	break;
				1435	}
				1436
				1437	switch (Inst.getOpcode()) {
				1438	case ARM::LDC_OFFSET:
				1439	case ARM::LDC_PRE:
				1440	case ARM::LDC_POST:
				1441	case ARM::LDC_OPTION:
				1442	case ARM::LDCL_OFFSET:
				1443	case ARM::LDCL_PRE:
				1444	case ARM::LDCL_POST:
				1445	case ARM::LDCL_OPTION:
				1446	case ARM::STC_OFFSET:
				1447	case ARM::STC_PRE:
				1448	case ARM::STC_POST:
				1449	case ARM::STC_OPTION:
				1450	case ARM::STCL_OFFSET:
				1451	case ARM::STCL_PRE:
				1452	case ARM::STCL_POST:
				1453	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1454	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1455	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1456	break;
				1457	default:
				1458	break;
				1459	}
				1460
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1461	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1462	}
				1463
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1464	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1465	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1466	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1467	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1468
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1469	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1470	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1471	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1472	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1473	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1474	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1475	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1476	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1477
				1478	// On stores, the writeback operand precedes Rt.
				1479	switch (Inst.getOpcode()) {
				1480	case ARM::STR_POST_IMM:
				1481	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1482	case ARM::STRB_POST_IMM:
				1483	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1484	case ARM::STRT_POST_REG:
				1485	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1486	case ARM::STRBT_POST_REG:
				1487	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1489	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1490	break;
				1491	default:
				1492	break;
				1493	}
				1494
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1495	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1496	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1497
				1498	// On loads, the writeback operand comes after Rt.
				1499	switch (Inst.getOpcode()) {
				1500	case ARM::LDR_POST_IMM:
				1501	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1502	case ARM::LDRB_POST_IMM:
				1503	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1504	case ARM::LDRBT_POST_REG:
				1505	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1506	case ARM::LDRT_POST_REG:
				1507	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1508	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1509	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	break;
				1511	default:
				1512	break;
				1513	}
				1514
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1515	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1516	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1517
				1518	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1519	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1520	Op = ARM_AM::sub;
				1521
				1522	bool writeback = (P == 0) \|\| (W == 1);
				1523	unsigned idx_mode = 0;
				1524	if (P && writeback)
				1525	idx_mode = ARMII::IndexModePre;
				1526	else if (!P && writeback)
				1527	idx_mode = ARMII::IndexModePost;
				1528
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1529	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1530	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1531
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1532	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1533	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1534	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1535	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1536	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1537	case 0:
				1538	Opc = ARM_AM::lsl;
				1539	break;
				1540	case 1:
				1541	Opc = ARM_AM::lsr;
				1542	break;
				1543	case 2:
				1544	Opc = ARM_AM::asr;
				1545	break;
				1546	case 3:
				1547	Opc = ARM_AM::ror;
				1548	break;
				1549	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1550	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1551	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1552	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1553	if (Opc == ARM_AM::ror && amt == 0)
				1554	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1555	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1556
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1557	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1558	} else {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1559	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1560	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1561	Inst.addOperand(MCOperand::createImm(tmp));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1562	}
				1563
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1564	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1565	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1567	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1568	}
				1569
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1570	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1571	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1572	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1573
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1574	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1575	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1576	unsigned type = fieldFromInstruction(Val, 5, 2);
				1577	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1578	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1579
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1580	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1581	switch (type) {
				1582	case 0:
				1583	ShOp = ARM_AM::lsl;
				1584	break;
				1585	case 1:
				1586	ShOp = ARM_AM::lsr;
				1587	break;
				1588	case 2:
				1589	ShOp = ARM_AM::asr;
				1590	break;
				1591	case 3:
				1592	ShOp = ARM_AM::ror;
				1593	break;
				1594	}
				1595
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1596	if (ShOp == ARM_AM::ror && imm == 0)
				1597	ShOp = ARM_AM::rrx;
				1598
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1599	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1600	return MCDisassembler::Fail;
				1601	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1602	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1603	unsigned shift;
				1604	if (U)
				1605	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1606	else
				1607	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1608	Inst.addOperand(MCOperand::createImm(shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1609
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1610	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1611	}
				1612
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1613	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1614	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1615	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1616	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1617
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1618	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1619	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1620	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1621	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1622	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1623	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1624	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1625	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1626	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1627	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1628
				1629	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1630
				1631	// For {LD,ST}RD, Rt must be even, else undefined.
				1632	switch (Inst.getOpcode()) {
				1633	case ARM::STRD:
				1634	case ARM::STRD_PRE:
				1635	case ARM::STRD_POST:
				1636	case ARM::LDRD:
				1637	case ARM::LDRD_PRE:
				1638	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1639	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1640	break;
				1641	default:
				1642	break;
				1643	}
				1644	switch (Inst.getOpcode()) {
				1645	case ARM::STRD:
				1646	case ARM::STRD_PRE:
				1647	case ARM::STRD_POST:
				1648	if (P == 0 && W == 1)
				1649	S = MCDisassembler::SoftFail;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	1650
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1651	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1652	S = MCDisassembler::SoftFail;
				1653	if (type && Rm == 15)
				1654	S = MCDisassembler::SoftFail;
				1655	if (Rt2 == 15)
				1656	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1657	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1658	S = MCDisassembler::SoftFail;
				1659	break;
				1660	case ARM::STRH:
				1661	case ARM::STRH_PRE:
				1662	case ARM::STRH_POST:
				1663	if (Rt == 15)
				1664	S = MCDisassembler::SoftFail;
				1665	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1666	S = MCDisassembler::SoftFail;
				1667	if (!type && Rm == 15)
				1668	S = MCDisassembler::SoftFail;
				1669	break;
				1670	case ARM::LDRD:
				1671	case ARM::LDRD_PRE:
				1672	case ARM::LDRD_POST:
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	1673	if (type && Rn == 15) {
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1674	if (Rt2 == 15)
				1675	S = MCDisassembler::SoftFail;
				1676	break;
				1677	}
				1678	if (P == 0 && W == 1)
				1679	S = MCDisassembler::SoftFail;
				1680	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1681	S = MCDisassembler::SoftFail;
				1682	if (!type && writeback && Rn == 15)
				1683	S = MCDisassembler::SoftFail;
				1684	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1685	S = MCDisassembler::SoftFail;
				1686	break;
				1687	case ARM::LDRH:
				1688	case ARM::LDRH_PRE:
				1689	case ARM::LDRH_POST:
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	1690	if (type && Rn == 15) {
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1691	if (Rt == 15)
				1692	S = MCDisassembler::SoftFail;
				1693	break;
				1694	}
				1695	if (Rt == 15)
				1696	S = MCDisassembler::SoftFail;
				1697	if (!type && Rm == 15)
				1698	S = MCDisassembler::SoftFail;
				1699	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1700	S = MCDisassembler::SoftFail;
				1701	break;
				1702	case ARM::LDRSH:
				1703	case ARM::LDRSH_PRE:
				1704	case ARM::LDRSH_POST:
				1705	case ARM::LDRSB:
				1706	case ARM::LDRSB_PRE:
				1707	case ARM::LDRSB_POST:
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	1708	if (type && Rn == 15) {
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1709	if (Rt == 15)
				1710	S = MCDisassembler::SoftFail;
				1711	break;
				1712	}
				1713	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1714	S = MCDisassembler::SoftFail;
				1715	if (!type && (Rt == 15 \|\| Rm == 15))
				1716	S = MCDisassembler::SoftFail;
				1717	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1718	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1719	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1720	default:
				1721	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1722	}
				1723
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1724	if (writeback) { // Writeback
				1725	if (P)
				1726	U \|= ARMII::IndexModePre << 9;
				1727	else
				1728	U \|= ARMII::IndexModePost << 9;
				1729
				1730	// On stores, the writeback operand precedes Rt.
				1731	switch (Inst.getOpcode()) {
				1732	case ARM::STRD:
				1733	case ARM::STRD_PRE:
				1734	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1735	case ARM::STRH:
				1736	case ARM::STRH_PRE:
				1737	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1738	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1739	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1740	break;
				1741	default:
				1742	break;
				1743	}
				1744	}
				1745
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1746	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1747	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1748	switch (Inst.getOpcode()) {
				1749	case ARM::STRD:
				1750	case ARM::STRD_PRE:
				1751	case ARM::STRD_POST:
				1752	case ARM::LDRD:
				1753	case ARM::LDRD_PRE:
				1754	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1755	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1756	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1757	break;
				1758	default:
				1759	break;
				1760	}
				1761
				1762	if (writeback) {
				1763	// On loads, the writeback operand comes after Rt.
				1764	switch (Inst.getOpcode()) {
				1765	case ARM::LDRD:
				1766	case ARM::LDRD_PRE:
				1767	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1768	case ARM::LDRH:
				1769	case ARM::LDRH_PRE:
				1770	case ARM::LDRH_POST:
				1771	case ARM::LDRSH:
				1772	case ARM::LDRSH_PRE:
				1773	case ARM::LDRSH_POST:
				1774	case ARM::LDRSB:
				1775	case ARM::LDRSB_PRE:
				1776	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1777	case ARM::LDRHTr:
				1778	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1779	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1780	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1781	break;
				1782	default:
				1783	break;
				1784	}
				1785	}
				1786
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1787	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1788	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1789
				1790	if (type) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1791	Inst.addOperand(MCOperand::createReg(0));
				1792	Inst.addOperand(MCOperand::createImm(U \| (imm << 4) \| Rm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1793	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1794	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1795	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1796	Inst.addOperand(MCOperand::createImm(U));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1797	}
				1798
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1799	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1800	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1801
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1802	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1803	}
				1804
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1805	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1806	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1807	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1808
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1809	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1810	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1811
				1812	switch (mode) {
				1813	case 0:
				1814	mode = ARM_AM::da;
				1815	break;
				1816	case 1:
				1817	mode = ARM_AM::ia;
				1818	break;
				1819	case 2:
				1820	mode = ARM_AM::db;
				1821	break;
				1822	case 3:
				1823	mode = ARM_AM::ib;
				1824	break;
				1825	}
				1826
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1827	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1828	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1829	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1830
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1831	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1832	}
				1833
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1834	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1835	uint64_t Address, const void *Decoder) {
				1836	DecodeStatus S = MCDisassembler::Success;
				1837
				1838	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1839	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1840	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1841	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1842
				1843	if (pred == 0xF)
				1844	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1845
				1846	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1847	return MCDisassembler::Fail;
				1848	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1849	return MCDisassembler::Fail;
				1850	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1851	return MCDisassembler::Fail;
				1852	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1853	return MCDisassembler::Fail;
				1854	return S;
				1855	}
				1856
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1857	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1858	unsigned Insn,
				1859	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1860	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1861
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1862	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1863	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1864	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1865
				1866	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1867	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1869	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1870	Inst.setOpcode(ARM::RFEDA);
				1871	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1872	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1873	Inst.setOpcode(ARM::RFEDA_UPD);
				1874	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1875	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1876	Inst.setOpcode(ARM::RFEDB);
				1877	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1878	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1879	Inst.setOpcode(ARM::RFEDB_UPD);
				1880	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1881	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1882	Inst.setOpcode(ARM::RFEIA);
				1883	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1884	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1885	Inst.setOpcode(ARM::RFEIA_UPD);
				1886	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1887	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	Inst.setOpcode(ARM::RFEIB);
				1889	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1890	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1891	Inst.setOpcode(ARM::RFEIB_UPD);
				1892	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1893	case ARM::STMDA:
				1894	Inst.setOpcode(ARM::SRSDA);
				1895	break;
				1896	case ARM::STMDA_UPD:
				1897	Inst.setOpcode(ARM::SRSDA_UPD);
				1898	break;
				1899	case ARM::STMDB:
				1900	Inst.setOpcode(ARM::SRSDB);
				1901	break;
				1902	case ARM::STMDB_UPD:
				1903	Inst.setOpcode(ARM::SRSDB_UPD);
				1904	break;
				1905	case ARM::STMIA:
				1906	Inst.setOpcode(ARM::SRSIA);
				1907	break;
				1908	case ARM::STMIA_UPD:
				1909	Inst.setOpcode(ARM::SRSIA_UPD);
				1910	break;
				1911	case ARM::STMIB:
				1912	Inst.setOpcode(ARM::SRSIB);
				1913	break;
				1914	case ARM::STMIB_UPD:
				1915	Inst.setOpcode(ARM::SRSIB_UPD);
				1916	break;
				1917	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1918	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1919	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1920
				1921	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1922	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1923	// Check SRS encoding constraints
				1924	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1925	fieldFromInstruction(Insn, 20, 1) == 0))
				1926	return MCDisassembler::Fail;
				1927
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1928	Inst.addOperand(
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1929	MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1930	return S;
				1931	}
				1932
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1933	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1934	}
				1935
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1936	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1937	return MCDisassembler::Fail;
				1938	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1939	return MCDisassembler::Fail; // Tied
				1940	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1941	return MCDisassembler::Fail;
				1942	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1943	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1944
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1945	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1946	}
				1947
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	1948	// Check for UNPREDICTABLE predicated ESB instruction
				1949	static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
				1950	uint64_t Address, const void *Decoder) {
				1951	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1952	unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
				1953	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				1954	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				1955
				1956	DecodeStatus S = MCDisassembler::Success;
				1957
				1958	Inst.addOperand(MCOperand::createImm(imm8));
				1959
				1960	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1961	return MCDisassembler::Fail;
				1962
				1963	// ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
				1964	// so all predicates should be allowed.
				1965	if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
				1966	S = MCDisassembler::SoftFail;
				1967
				1968	return S;
				1969	}
				1970
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1971	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1972	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1973	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1974	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1975	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1976	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1977
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1978	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1979
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1980	// This decoder is called from multiple location that do not check
				1981	// the full encoding is valid before they do.
				1982	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1983	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1984	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1985	return MCDisassembler::Fail;
				1986
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1987	// imod == '01' --> UNPREDICTABLE
				1988	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1989	// return failure here. The '01' imod value is unprintable, so there's
				1990	// nothing useful we could do even if we returned UNPREDICTABLE.
				1991
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1992	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1993
				1994	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1995	Inst.setOpcode(ARM::CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1996	Inst.addOperand(MCOperand::createImm(imod));
				1997	Inst.addOperand(MCOperand::createImm(iflags));
				1998	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1999	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2000	Inst.setOpcode(ARM::CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2001	Inst.addOperand(MCOperand::createImm(imod));
				2002	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2003	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2004	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2005	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2006	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2007	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2008	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2009	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2010	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2011	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2012	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2013	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2014
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2015	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2016	}
				2017
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2018	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2019	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2020	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				2021	unsigned M = fieldFromInstruction(Insn, 8, 1);
				2022	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2023	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2024
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2025	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2026
				2027	// imod == '01' --> UNPREDICTABLE
				2028	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2029	// return failure here. The '01' imod value is unprintable, so there's
				2030	// nothing useful we could do even if we returned UNPREDICTABLE.
				2031
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2032	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2033
				2034	if (imod && M) {
				2035	Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2036	Inst.addOperand(MCOperand::createImm(imod));
				2037	Inst.addOperand(MCOperand::createImm(iflags));
				2038	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2039	} else if (imod && !M) {
				2040	Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2041	Inst.addOperand(MCOperand::createImm(imod));
				2042	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2043	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2044	} else if (!imod && M) {
				2045	Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2046	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2047	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2048	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2049	// imod == '00' && M == '0' --> this is a HINT instruction
				2050	int imm = fieldFromInstruction(Insn, 0, 8);
				2051	// HINT are defined only for immediate in [0..4]
				2052	if(imm > 4) return MCDisassembler::Fail;
				2053	Inst.setOpcode(ARM::t2HINT);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2054	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2055	}
				2056
				2057	return S;
				2058	}
				2059
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2060	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2061	uint64_t Address, const void *Decoder) {
				2062	DecodeStatus S = MCDisassembler::Success;
				2063
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2064	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2065	unsigned imm = 0;
				2066
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2067	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2068	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2069	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2070	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2071
				2072	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2073	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2074	return MCDisassembler::Fail;
				2075	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2076	return MCDisassembler::Fail;
				2077
				2078	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2079	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2080
				2081	return S;
				2082	}
				2083
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2084	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2085	uint64_t Address, const void *Decoder) {
				2086	DecodeStatus S = MCDisassembler::Success;
				2087
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2088	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2089	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2090	unsigned imm = 0;
				2091
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2092	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2093	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2094
				2095	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2096	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2097	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2098
				2099	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2100	return MCDisassembler::Fail;
				2101
				2102	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2103	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2104
				2105	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2106	return MCDisassembler::Fail;
				2107
				2108	return S;
				2109	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2110
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2111	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2112	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2113	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2114
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2115	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2116	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2117	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2118	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2119	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2120
				2121	if (pred == 0xF)
				2122	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2123
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2124	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2125	return MCDisassembler::Fail;
				2126	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2127	return MCDisassembler::Fail;
				2128	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2129	return MCDisassembler::Fail;
				2130	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2131	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2132
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2133	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2134	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2135
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2136	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2137	}
				2138
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2139	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				2140	uint64_t Address, const void *Decoder) {
				2141	DecodeStatus S = MCDisassembler::Success;
				2142
				2143	unsigned Pred = fieldFromInstruction(Insn, 28, 4);
				2144	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2145	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2146
				2147	if (Pred == 0xF)
				2148	return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
				2149
				2150	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2151	return MCDisassembler::Fail;
				2152	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2153	return MCDisassembler::Fail;
				2154	if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
				2155	return MCDisassembler::Fail;
				2156
				2157	return S;
				2158	}
				2159
				2160	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				2161	uint64_t Address, const void *Decoder) {
				2162	DecodeStatus S = MCDisassembler::Success;
				2163
				2164	unsigned Imm = fieldFromInstruction(Insn, 9, 1);
				2165
				2166	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	2167	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				2168
				2169	if (!FeatureBits[ARM::HasV8_1aOps] \|\|
				2170	!FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2171	return MCDisassembler::Fail;
				2172
				2173	// Decoder can be called from DecodeTST, which does not check the full
				2174	// encoding is valid.
				2175	if (fieldFromInstruction(Insn, 20,12) != 0xf11 \|\|
				2176	fieldFromInstruction(Insn, 4,4) != 0)
				2177	return MCDisassembler::Fail;
				2178	if (fieldFromInstruction(Insn, 10,10) != 0 \|\|
				2179	fieldFromInstruction(Insn, 0,4) != 0)
				2180	S = MCDisassembler::SoftFail;
				2181
				2182	Inst.setOpcode(ARM::SETPAN);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2183	Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2184
				2185	return S;
				2186	}
				2187
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2188	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2189	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2190	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2191
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2192	unsigned add = fieldFromInstruction(Val, 12, 1);
				2193	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2194	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2195
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2196	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2197	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2198
				2199	if (!add) imm *= -1;
				2200	if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2201	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2202	if (Rn == 15)
				2203	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2205	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2206	}
				2207
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2208	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2209	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2210	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2211
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2212	unsigned Rn = fieldFromInstruction(Val, 9, 4);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2213	// U == 1 to add imm, 0 to subtract it.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2214	unsigned U = fieldFromInstruction(Val, 8, 1);
				2215	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2216
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2217	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2218	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2219
				2220	if (U)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2221	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2222	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2223	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2224
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2225	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2226	}
				2227
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2228	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				2229	uint64_t Address, const void *Decoder) {
				2230	DecodeStatus S = MCDisassembler::Success;
				2231
				2232	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2233	// U == 1 to add imm, 0 to subtract it.
				2234	unsigned U = fieldFromInstruction(Val, 8, 1);
				2235	unsigned imm = fieldFromInstruction(Val, 0, 8);
				2236
				2237	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2238	return MCDisassembler::Fail;
				2239
				2240	if (U)
				2241	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
				2242	else
				2243	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
				2244
				2245	return S;
				2246	}
				2247
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2248	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2249	uint64_t Address, const void *Decoder) {
				2250	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2251	}
				2252
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2253	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2254	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2255	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2256	DecodeStatus Status = MCDisassembler::Success;
				2257
				2258	// Note the J1 and J2 values are from the encoded instruction. So here
				2259	// change them to I1 and I2 values via as documented:
				2260	// I1 = NOT(J1 EOR S);
				2261	// I2 = NOT(J2 EOR S);
				2262	// and build the imm32 with one trailing zero as documented:
				2263	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2264	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2265	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2266	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2267	unsigned I1 = !(J1 ^ S);
				2268	unsigned I2 = !(J2 ^ S);
				2269	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2270	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2271	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2272	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2273	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2274	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2275	Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2276
				2277	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2278	}
				2279
				2280	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2281	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2282	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2283	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2284
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2285	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2286	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2287
				2288	if (pred == 0xF) {
				2289	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2290	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2291	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2292	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2293	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2294	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2295	}
				2296
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2297	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2298	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2299	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2300	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2301	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2302
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2303	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2304	}
				2305
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2306	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2307	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2308	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2309
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2310	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2311	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2312
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2313	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2314	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2315	if (!align)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2316	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2317	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2318	Inst.addOperand(MCOperand::createImm(4 << align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2319
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2320	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2321	}
				2322
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2323	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2324	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2325	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2326
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2327	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2328	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2329	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2330	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2331	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2332	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2333
				2334	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2335	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2336	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2337	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2338	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2339	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2340	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2341	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2342	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2343	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2344	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2345	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2346	return MCDisassembler::Fail;
				2347	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2348	case ARM::VLD2b16:
				2349	case ARM::VLD2b32:
				2350	case ARM::VLD2b8:
				2351	case ARM::VLD2b16wb_fixed:
				2352	case ARM::VLD2b16wb_register:
				2353	case ARM::VLD2b32wb_fixed:
				2354	case ARM::VLD2b32wb_register:
				2355	case ARM::VLD2b8wb_fixed:
				2356	case ARM::VLD2b8wb_register:
				2357	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2358	return MCDisassembler::Fail;
				2359	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2360	default:
				2361	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2362	return MCDisassembler::Fail;
				2363	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2364
				2365	// Second output register
				2366	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2367	case ARM::VLD3d8:
				2368	case ARM::VLD3d16:
				2369	case ARM::VLD3d32:
				2370	case ARM::VLD3d8_UPD:
				2371	case ARM::VLD3d16_UPD:
				2372	case ARM::VLD3d32_UPD:
				2373	case ARM::VLD4d8:
				2374	case ARM::VLD4d16:
				2375	case ARM::VLD4d32:
				2376	case ARM::VLD4d8_UPD:
				2377	case ARM::VLD4d16_UPD:
				2378	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2379	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2380	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2381	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2382	case ARM::VLD3q8:
				2383	case ARM::VLD3q16:
				2384	case ARM::VLD3q32:
				2385	case ARM::VLD3q8_UPD:
				2386	case ARM::VLD3q16_UPD:
				2387	case ARM::VLD3q32_UPD:
				2388	case ARM::VLD4q8:
				2389	case ARM::VLD4q16:
				2390	case ARM::VLD4q32:
				2391	case ARM::VLD4q8_UPD:
				2392	case ARM::VLD4q16_UPD:
				2393	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2394	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2395	return MCDisassembler::Fail;
Adrian Prantl	0e6694d	2017-12-19 22:05:25 +0000	[diff] [blame]	2396	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2397	default:
				2398	break;
				2399	}
				2400
				2401	// Third output register
				2402	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2403	case ARM::VLD3d8:
				2404	case ARM::VLD3d16:
				2405	case ARM::VLD3d32:
				2406	case ARM::VLD3d8_UPD:
				2407	case ARM::VLD3d16_UPD:
				2408	case ARM::VLD3d32_UPD:
				2409	case ARM::VLD4d8:
				2410	case ARM::VLD4d16:
				2411	case ARM::VLD4d32:
				2412	case ARM::VLD4d8_UPD:
				2413	case ARM::VLD4d16_UPD:
				2414	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2415	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2416	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2417	break;
				2418	case ARM::VLD3q8:
				2419	case ARM::VLD3q16:
				2420	case ARM::VLD3q32:
				2421	case ARM::VLD3q8_UPD:
				2422	case ARM::VLD3q16_UPD:
				2423	case ARM::VLD3q32_UPD:
				2424	case ARM::VLD4q8:
				2425	case ARM::VLD4q16:
				2426	case ARM::VLD4q32:
				2427	case ARM::VLD4q8_UPD:
				2428	case ARM::VLD4q16_UPD:
				2429	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2430	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2431	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2432	break;
				2433	default:
				2434	break;
				2435	}
				2436
				2437	// Fourth output register
				2438	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2439	case ARM::VLD4d8:
				2440	case ARM::VLD4d16:
				2441	case ARM::VLD4d32:
				2442	case ARM::VLD4d8_UPD:
				2443	case ARM::VLD4d16_UPD:
				2444	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2445	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2446	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2447	break;
				2448	case ARM::VLD4q8:
				2449	case ARM::VLD4q16:
				2450	case ARM::VLD4q32:
				2451	case ARM::VLD4q8_UPD:
				2452	case ARM::VLD4q16_UPD:
				2453	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2454	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2455	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2456	break;
				2457	default:
				2458	break;
				2459	}
				2460
				2461	// Writeback operand
				2462	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2463	case ARM::VLD1d8wb_fixed:
				2464	case ARM::VLD1d16wb_fixed:
				2465	case ARM::VLD1d32wb_fixed:
				2466	case ARM::VLD1d64wb_fixed:
				2467	case ARM::VLD1d8wb_register:
				2468	case ARM::VLD1d16wb_register:
				2469	case ARM::VLD1d32wb_register:
				2470	case ARM::VLD1d64wb_register:
				2471	case ARM::VLD1q8wb_fixed:
				2472	case ARM::VLD1q16wb_fixed:
				2473	case ARM::VLD1q32wb_fixed:
				2474	case ARM::VLD1q64wb_fixed:
				2475	case ARM::VLD1q8wb_register:
				2476	case ARM::VLD1q16wb_register:
				2477	case ARM::VLD1q32wb_register:
				2478	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2479	case ARM::VLD1d8Twb_fixed:
				2480	case ARM::VLD1d8Twb_register:
				2481	case ARM::VLD1d16Twb_fixed:
				2482	case ARM::VLD1d16Twb_register:
				2483	case ARM::VLD1d32Twb_fixed:
				2484	case ARM::VLD1d32Twb_register:
				2485	case ARM::VLD1d64Twb_fixed:
				2486	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2487	case ARM::VLD1d8Qwb_fixed:
				2488	case ARM::VLD1d8Qwb_register:
				2489	case ARM::VLD1d16Qwb_fixed:
				2490	case ARM::VLD1d16Qwb_register:
				2491	case ARM::VLD1d32Qwb_fixed:
				2492	case ARM::VLD1d32Qwb_register:
				2493	case ARM::VLD1d64Qwb_fixed:
				2494	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2495	case ARM::VLD2d8wb_fixed:
				2496	case ARM::VLD2d16wb_fixed:
				2497	case ARM::VLD2d32wb_fixed:
				2498	case ARM::VLD2q8wb_fixed:
				2499	case ARM::VLD2q16wb_fixed:
				2500	case ARM::VLD2q32wb_fixed:
				2501	case ARM::VLD2d8wb_register:
				2502	case ARM::VLD2d16wb_register:
				2503	case ARM::VLD2d32wb_register:
				2504	case ARM::VLD2q8wb_register:
				2505	case ARM::VLD2q16wb_register:
				2506	case ARM::VLD2q32wb_register:
				2507	case ARM::VLD2b8wb_fixed:
				2508	case ARM::VLD2b16wb_fixed:
				2509	case ARM::VLD2b32wb_fixed:
				2510	case ARM::VLD2b8wb_register:
				2511	case ARM::VLD2b16wb_register:
				2512	case ARM::VLD2b32wb_register:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2513	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2514	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2515	case ARM::VLD3d8_UPD:
				2516	case ARM::VLD3d16_UPD:
				2517	case ARM::VLD3d32_UPD:
				2518	case ARM::VLD3q8_UPD:
				2519	case ARM::VLD3q16_UPD:
				2520	case ARM::VLD3q32_UPD:
				2521	case ARM::VLD4d8_UPD:
				2522	case ARM::VLD4d16_UPD:
				2523	case ARM::VLD4d32_UPD:
				2524	case ARM::VLD4q8_UPD:
				2525	case ARM::VLD4q16_UPD:
				2526	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2527	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2528	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2529	break;
				2530	default:
				2531	break;
				2532	}
				2533
				2534	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2535	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2536	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2537
				2538	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2539	switch (Inst.getOpcode()) {
				2540	default:
				2541	// The below have been updated to have explicit am6offset split
				2542	// between fixed and register offset. For those instructions not
				2543	// yet updated, we need to add an additional reg0 operand for the
				2544	// fixed variant.
				2545	//
				2546	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2547	if (Rm == 0xd) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2548	Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2549	break;
				2550	}
				2551	// Fall through to handle the register offset variant.
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	2552	LLVM_FALLTHROUGH;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2553	case ARM::VLD1d8wb_fixed:
				2554	case ARM::VLD1d16wb_fixed:
				2555	case ARM::VLD1d32wb_fixed:
				2556	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2557	case ARM::VLD1d8Twb_fixed:
				2558	case ARM::VLD1d16Twb_fixed:
				2559	case ARM::VLD1d32Twb_fixed:
				2560	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2561	case ARM::VLD1d8Qwb_fixed:
				2562	case ARM::VLD1d16Qwb_fixed:
				2563	case ARM::VLD1d32Qwb_fixed:
				2564	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2565	case ARM::VLD1d8wb_register:
				2566	case ARM::VLD1d16wb_register:
				2567	case ARM::VLD1d32wb_register:
				2568	case ARM::VLD1d64wb_register:
				2569	case ARM::VLD1q8wb_fixed:
				2570	case ARM::VLD1q16wb_fixed:
				2571	case ARM::VLD1q32wb_fixed:
				2572	case ARM::VLD1q64wb_fixed:
				2573	case ARM::VLD1q8wb_register:
				2574	case ARM::VLD1q16wb_register:
				2575	case ARM::VLD1q32wb_register:
				2576	case ARM::VLD1q64wb_register:
				2577	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2578	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2579	// increment and we need to add the register operand to the instruction.
				2580	if (Rm != 0xD && Rm != 0xF &&
				2581	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2582	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2583	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2584	case ARM::VLD2d8wb_fixed:
				2585	case ARM::VLD2d16wb_fixed:
				2586	case ARM::VLD2d32wb_fixed:
				2587	case ARM::VLD2b8wb_fixed:
				2588	case ARM::VLD2b16wb_fixed:
				2589	case ARM::VLD2b32wb_fixed:
				2590	case ARM::VLD2q8wb_fixed:
				2591	case ARM::VLD2q16wb_fixed:
				2592	case ARM::VLD2q32wb_fixed:
				2593	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2594	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2595
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2596	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2597	}
				2598
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2599	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2600	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2601	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2602	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2603	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2604	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2605	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2606
				2607	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2608	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2609	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2610	}
				2611
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2612	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2613	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2614	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2615	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2616
				2617	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2618	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2619	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2620	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2621
				2622	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2623	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2624	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2625	}
				2626
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2627	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2628	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2629	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2630	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2631
				2632	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2633	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2634
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2635	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2636	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2637	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2638	}
				2639
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2640	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2641	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2642	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2643	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2644
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2645	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2646	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2647	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2648	}
				2649
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2650	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2651	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2652	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2653
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2654	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2655	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2656	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2657	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2658	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2659	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2660
				2661	// Writeback Operand
				2662	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2663	case ARM::VST1d8wb_fixed:
				2664	case ARM::VST1d16wb_fixed:
				2665	case ARM::VST1d32wb_fixed:
				2666	case ARM::VST1d64wb_fixed:
				2667	case ARM::VST1d8wb_register:
				2668	case ARM::VST1d16wb_register:
				2669	case ARM::VST1d32wb_register:
				2670	case ARM::VST1d64wb_register:
				2671	case ARM::VST1q8wb_fixed:
				2672	case ARM::VST1q16wb_fixed:
				2673	case ARM::VST1q32wb_fixed:
				2674	case ARM::VST1q64wb_fixed:
				2675	case ARM::VST1q8wb_register:
				2676	case ARM::VST1q16wb_register:
				2677	case ARM::VST1q32wb_register:
				2678	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2679	case ARM::VST1d8Twb_fixed:
				2680	case ARM::VST1d16Twb_fixed:
				2681	case ARM::VST1d32Twb_fixed:
				2682	case ARM::VST1d64Twb_fixed:
				2683	case ARM::VST1d8Twb_register:
				2684	case ARM::VST1d16Twb_register:
				2685	case ARM::VST1d32Twb_register:
				2686	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2687	case ARM::VST1d8Qwb_fixed:
				2688	case ARM::VST1d16Qwb_fixed:
				2689	case ARM::VST1d32Qwb_fixed:
				2690	case ARM::VST1d64Qwb_fixed:
				2691	case ARM::VST1d8Qwb_register:
				2692	case ARM::VST1d16Qwb_register:
				2693	case ARM::VST1d32Qwb_register:
				2694	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2695	case ARM::VST2d8wb_fixed:
				2696	case ARM::VST2d16wb_fixed:
				2697	case ARM::VST2d32wb_fixed:
				2698	case ARM::VST2d8wb_register:
				2699	case ARM::VST2d16wb_register:
				2700	case ARM::VST2d32wb_register:
				2701	case ARM::VST2q8wb_fixed:
				2702	case ARM::VST2q16wb_fixed:
				2703	case ARM::VST2q32wb_fixed:
				2704	case ARM::VST2q8wb_register:
				2705	case ARM::VST2q16wb_register:
				2706	case ARM::VST2q32wb_register:
				2707	case ARM::VST2b8wb_fixed:
				2708	case ARM::VST2b16wb_fixed:
				2709	case ARM::VST2b32wb_fixed:
				2710	case ARM::VST2b8wb_register:
				2711	case ARM::VST2b16wb_register:
				2712	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2713	if (Rm == 0xF)
				2714	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2715	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2716	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2717	case ARM::VST3d8_UPD:
				2718	case ARM::VST3d16_UPD:
				2719	case ARM::VST3d32_UPD:
				2720	case ARM::VST3q8_UPD:
				2721	case ARM::VST3q16_UPD:
				2722	case ARM::VST3q32_UPD:
				2723	case ARM::VST4d8_UPD:
				2724	case ARM::VST4d16_UPD:
				2725	case ARM::VST4d32_UPD:
				2726	case ARM::VST4q8_UPD:
				2727	case ARM::VST4q16_UPD:
				2728	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2729	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2730	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2731	break;
				2732	default:
				2733	break;
				2734	}
				2735
				2736	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2737	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2738	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2739
				2740	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2741	switch (Inst.getOpcode()) {
				2742	default:
				2743	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2744	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2745	else if (Rm != 0xF) {
				2746	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2747	return MCDisassembler::Fail;
				2748	}
				2749	break;
				2750	case ARM::VST1d8wb_fixed:
				2751	case ARM::VST1d16wb_fixed:
				2752	case ARM::VST1d32wb_fixed:
				2753	case ARM::VST1d64wb_fixed:
				2754	case ARM::VST1q8wb_fixed:
				2755	case ARM::VST1q16wb_fixed:
				2756	case ARM::VST1q32wb_fixed:
				2757	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2758	case ARM::VST1d8Twb_fixed:
				2759	case ARM::VST1d16Twb_fixed:
				2760	case ARM::VST1d32Twb_fixed:
				2761	case ARM::VST1d64Twb_fixed:
				2762	case ARM::VST1d8Qwb_fixed:
				2763	case ARM::VST1d16Qwb_fixed:
				2764	case ARM::VST1d32Qwb_fixed:
				2765	case ARM::VST1d64Qwb_fixed:
				2766	case ARM::VST2d8wb_fixed:
				2767	case ARM::VST2d16wb_fixed:
				2768	case ARM::VST2d32wb_fixed:
				2769	case ARM::VST2q8wb_fixed:
				2770	case ARM::VST2q16wb_fixed:
				2771	case ARM::VST2q32wb_fixed:
				2772	case ARM::VST2b8wb_fixed:
				2773	case ARM::VST2b16wb_fixed:
				2774	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2775	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2776	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2777
				2778	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2779	switch (Inst.getOpcode()) {
				2780	case ARM::VST1q16:
				2781	case ARM::VST1q32:
				2782	case ARM::VST1q64:
				2783	case ARM::VST1q8:
				2784	case ARM::VST1q16wb_fixed:
				2785	case ARM::VST1q16wb_register:
				2786	case ARM::VST1q32wb_fixed:
				2787	case ARM::VST1q32wb_register:
				2788	case ARM::VST1q64wb_fixed:
				2789	case ARM::VST1q64wb_register:
				2790	case ARM::VST1q8wb_fixed:
				2791	case ARM::VST1q8wb_register:
				2792	case ARM::VST2d16:
				2793	case ARM::VST2d32:
				2794	case ARM::VST2d8:
				2795	case ARM::VST2d16wb_fixed:
				2796	case ARM::VST2d16wb_register:
				2797	case ARM::VST2d32wb_fixed:
				2798	case ARM::VST2d32wb_register:
				2799	case ARM::VST2d8wb_fixed:
				2800	case ARM::VST2d8wb_register:
				2801	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2802	return MCDisassembler::Fail;
				2803	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2804	case ARM::VST2b16:
				2805	case ARM::VST2b32:
				2806	case ARM::VST2b8:
				2807	case ARM::VST2b16wb_fixed:
				2808	case ARM::VST2b16wb_register:
				2809	case ARM::VST2b32wb_fixed:
				2810	case ARM::VST2b32wb_register:
				2811	case ARM::VST2b8wb_fixed:
				2812	case ARM::VST2b8wb_register:
				2813	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2814	return MCDisassembler::Fail;
				2815	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2816	default:
				2817	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2818	return MCDisassembler::Fail;
				2819	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2820
				2821	// Second input register
				2822	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2823	case ARM::VST3d8:
				2824	case ARM::VST3d16:
				2825	case ARM::VST3d32:
				2826	case ARM::VST3d8_UPD:
				2827	case ARM::VST3d16_UPD:
				2828	case ARM::VST3d32_UPD:
				2829	case ARM::VST4d8:
				2830	case ARM::VST4d16:
				2831	case ARM::VST4d32:
				2832	case ARM::VST4d8_UPD:
				2833	case ARM::VST4d16_UPD:
				2834	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2835	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2836	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2837	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2838	case ARM::VST3q8:
				2839	case ARM::VST3q16:
				2840	case ARM::VST3q32:
				2841	case ARM::VST3q8_UPD:
				2842	case ARM::VST3q16_UPD:
				2843	case ARM::VST3q32_UPD:
				2844	case ARM::VST4q8:
				2845	case ARM::VST4q16:
				2846	case ARM::VST4q32:
				2847	case ARM::VST4q8_UPD:
				2848	case ARM::VST4q16_UPD:
				2849	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2850	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2851	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2852	break;
				2853	default:
				2854	break;
				2855	}
				2856
				2857	// Third input register
				2858	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2859	case ARM::VST3d8:
				2860	case ARM::VST3d16:
				2861	case ARM::VST3d32:
				2862	case ARM::VST3d8_UPD:
				2863	case ARM::VST3d16_UPD:
				2864	case ARM::VST3d32_UPD:
				2865	case ARM::VST4d8:
				2866	case ARM::VST4d16:
				2867	case ARM::VST4d32:
				2868	case ARM::VST4d8_UPD:
				2869	case ARM::VST4d16_UPD:
				2870	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2871	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2872	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2873	break;
				2874	case ARM::VST3q8:
				2875	case ARM::VST3q16:
				2876	case ARM::VST3q32:
				2877	case ARM::VST3q8_UPD:
				2878	case ARM::VST3q16_UPD:
				2879	case ARM::VST3q32_UPD:
				2880	case ARM::VST4q8:
				2881	case ARM::VST4q16:
				2882	case ARM::VST4q32:
				2883	case ARM::VST4q8_UPD:
				2884	case ARM::VST4q16_UPD:
				2885	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2886	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2887	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2888	break;
				2889	default:
				2890	break;
				2891	}
				2892
				2893	// Fourth input register
				2894	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2895	case ARM::VST4d8:
				2896	case ARM::VST4d16:
				2897	case ARM::VST4d32:
				2898	case ARM::VST4d8_UPD:
				2899	case ARM::VST4d16_UPD:
				2900	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2901	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2902	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2903	break;
				2904	case ARM::VST4q8:
				2905	case ARM::VST4q16:
				2906	case ARM::VST4q32:
				2907	case ARM::VST4q8_UPD:
				2908	case ARM::VST4q16_UPD:
				2909	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2910	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2911	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2912	break;
				2913	default:
				2914	break;
				2915	}
				2916
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2917	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2918	}
				2919
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2920	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2921	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2922	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2923
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2924	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2925	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2926	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2927	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2928	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2929	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2930
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2931	if (size == 0 && align == 1)
				2932	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2933	align *= (1 << size);
				2934
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2935	switch (Inst.getOpcode()) {
				2936	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2937	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2938	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2939	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2940	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2941	return MCDisassembler::Fail;
				2942	break;
				2943	default:
				2944	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2945	return MCDisassembler::Fail;
				2946	break;
				2947	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2948	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2949	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2950	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2951	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2952
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2953	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2954	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2955	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2956
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2957	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2958	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2959	// increment and we need to add the register operand to the instruction.
				2960	if (Rm != 0xD && Rm != 0xF &&
				2961	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2962	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2963
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2964	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2965	}
				2966
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2967	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2968	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2969	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2970
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2971	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2972	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2973	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2974	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2975	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2976	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2977	align = 2size;
				2978
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2979	switch (Inst.getOpcode()) {
				2980	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2981	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2982	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2983	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2984	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2985	return MCDisassembler::Fail;
				2986	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2987	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2988	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2989	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2990	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2991	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2992	return MCDisassembler::Fail;
				2993	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2994	default:
				2995	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2996	return MCDisassembler::Fail;
				2997	break;
				2998	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2999
				3000	if (Rm != 0xF)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3001	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3002
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3003	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3004	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3005	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3006
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	3007	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3008	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3009	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3010	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3011
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3012	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3013	}
				3014
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3015	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3016	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3017	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3018
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3019	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3020	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3021	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3022	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3023	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3024
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3025	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3026	return MCDisassembler::Fail;
				3027	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3028	return MCDisassembler::Fail;
				3029	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3030	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3031	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3032	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3033	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3034	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3035
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3036	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3037	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3038	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3039
				3040	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3041	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3042	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3043	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3044	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3045	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3046
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3047	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3048	}
				3049
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3050	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3051	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3052	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3053
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3054	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3055	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3056	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3057	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3058	unsigned size = fieldFromInstruction(Insn, 6, 2);
				3059	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				3060	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3061
				3062	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	3063	if (align == 0)
				3064	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3065	align = 16;
				3066	} else {
				3067	if (size == 2) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3068	align *= 8;
				3069	} else {
				3070	size = 1 << size;
				3071	align = 4size;
				3072	}
				3073	}
				3074
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3075	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3076	return MCDisassembler::Fail;
				3077	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3078	return MCDisassembler::Fail;
				3079	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3080	return MCDisassembler::Fail;
				3081	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				3082	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3083	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3084	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3085	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3086	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3087
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3088	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3089	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3090	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3091
				3092	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3093	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3094	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3095	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3096	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3097	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3099	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3100	}
				3101
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3102	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3103	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3104	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3105	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3106
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3107	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3108	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3109	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3110	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3111	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3112	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3113	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3114	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3115
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3116	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3117	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3118	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3119	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3120	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3121	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3122	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3123
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3124	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3125
				3126	switch (Inst.getOpcode()) {
				3127	case ARM::VORRiv4i16:
				3128	case ARM::VORRiv2i32:
				3129	case ARM::VBICiv4i16:
				3130	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3131	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3132	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	break;
				3134	case ARM::VORRiv8i16:
				3135	case ARM::VORRiv4i32:
				3136	case ARM::VBICiv8i16:
				3137	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3139	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3140	break;
				3141	default:
				3142	break;
				3143	}
				3144
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3145	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3146	}
				3147
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3148	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3149	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3150	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3151
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3152	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3153	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3154	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3155	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3156	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3157
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3158	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3159	return MCDisassembler::Fail;
				3160	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3161	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3162	Inst.addOperand(MCOperand::createImm(8 << size));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3163
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3164	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3165	}
				3166
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3167	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3168	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3169	Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3170	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3171	}
				3172
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3173	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3174	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3175	Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3176	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3177	}
				3178
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3179	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3180	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3181	Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3182	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3183	}
				3184
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3185	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3186	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3187	Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3188	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3189	}
				3190
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3191	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3192	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3193	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3194
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3195	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3196	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3197	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3198	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3199	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3200	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3201	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3202
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3203	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3204	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3205	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3206	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3207	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3208	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3209
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3210	switch (Inst.getOpcode()) {
				3211	case ARM::VTBL2:
				3212	case ARM::VTBX2:
				3213	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3214	return MCDisassembler::Fail;
				3215	break;
				3216	default:
				3217	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3218	return MCDisassembler::Fail;
				3219	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3220
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3221	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3222	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3223
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3224	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3225	}
				3226
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3227	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3228	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3229	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3230
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3231	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3232	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3233
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3234	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3235	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3236
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3237	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3238	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3239	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3240	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3241	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3242	case ARM::tADDrSPi:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3243	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3244	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3245	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3246
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3247	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3248	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3249	}
				3250
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3251	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3252	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3253	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3254	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3255	Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3256	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3257	}
				3258
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3259	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3260	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3261	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3262	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3263	Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3264	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3265	}
				3266
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3267	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3268	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3269	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3270	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3271	Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3272	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3273	}
				3274
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3275	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3276	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3277	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3278
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3279	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3280	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3281
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3282	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3283	return MCDisassembler::Fail;
				3284	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3285	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3286
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3287	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3288	}
				3289
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3290	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3291	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3292	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3293
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3294	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3295	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3296
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3297	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3298	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3299	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3300
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3301	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3302	}
				3303
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3304	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3305	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3306	unsigned imm = Val << 2;
				3307
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3308	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3309	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3310
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3311	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3312	}
				3313
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3314	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3315	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3316	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3317	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3318
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3319	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3320	}
				3321
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3322	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3323	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3324	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3325
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3326	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3327	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3328	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3329
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3330	// Thumb stores cannot use PC as dest register.
				3331	switch (Inst.getOpcode()) {
				3332	case ARM::t2STRHs:
				3333	case ARM::t2STRBs:
				3334	case ARM::t2STRs:
				3335	if (Rn == 15)
				3336	return MCDisassembler::Fail;
Adrian Prantl	0e6694d	2017-12-19 22:05:25 +0000	[diff] [blame]	3337	break;
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3338	default:
				3339	break;
				3340	}
				3341
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3342	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3343	return MCDisassembler::Fail;
				3344	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3345	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3346	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3347
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3348	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3349	}
				3350
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3351	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3352	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3353	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3354
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3355	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3356	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3357
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3358	const FeatureBitset &featureBits =
				3359	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3360
				3361	bool hasMP = featureBits[ARM::FeatureMP];
				3362	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3363
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3364	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3365	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3366	case ARM::t2LDRBs:
				3367	Inst.setOpcode(ARM::t2LDRBpci);
				3368	break;
				3369	case ARM::t2LDRHs:
				3370	Inst.setOpcode(ARM::t2LDRHpci);
				3371	break;
				3372	case ARM::t2LDRSHs:
				3373	Inst.setOpcode(ARM::t2LDRSHpci);
				3374	break;
				3375	case ARM::t2LDRSBs:
				3376	Inst.setOpcode(ARM::t2LDRSBpci);
				3377	break;
				3378	case ARM::t2LDRs:
				3379	Inst.setOpcode(ARM::t2LDRpci);
				3380	break;
				3381	case ARM::t2PLDs:
				3382	Inst.setOpcode(ARM::t2PLDpci);
				3383	break;
				3384	case ARM::t2PLIs:
				3385	Inst.setOpcode(ARM::t2PLIpci);
				3386	break;
				3387	default:
				3388	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3389	}
				3390
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3391	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3392	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3393
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3394	if (Rt == 15) {
				3395	switch (Inst.getOpcode()) {
				3396	case ARM::t2LDRSHs:
				3397	return MCDisassembler::Fail;
				3398	case ARM::t2LDRHs:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3399	Inst.setOpcode(ARM::t2PLDWs);
				3400	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3401	case ARM::t2LDRSBs:
				3402	Inst.setOpcode(ARM::t2PLIs);
Adrian Prantl	0e6694d	2017-12-19 22:05:25 +0000	[diff] [blame]	3403	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3404	default:
				3405	break;
				3406	}
				3407	}
				3408
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3409	switch (Inst.getOpcode()) {
				3410	case ARM::t2PLDs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3411	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3412	case ARM::t2PLIs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3413	if (!hasV7Ops)
				3414	return MCDisassembler::Fail;
				3415	break;
				3416	case ARM::t2PLDWs:
				3417	if (!hasV7Ops \|\| !hasMP)
				3418	return MCDisassembler::Fail;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3419	break;
				3420	default:
				3421	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3422	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3423	}
				3424
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3425	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3426	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3427	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3428	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3429	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3430
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3431	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3432	}
				3433
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3434	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3435	uint64_t Address, const void* Decoder) {
				3436	DecodeStatus S = MCDisassembler::Success;
				3437
				3438	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3439	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3440	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3441	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3442	imm \|= (U << 8);
				3443	imm \|= (Rn << 9);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3444	unsigned add = fieldFromInstruction(Insn, 9, 1);
				3445
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3446	const FeatureBitset &featureBits =
				3447	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3448
				3449	bool hasMP = featureBits[ARM::FeatureMP];
				3450	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3451
				3452	if (Rn == 15) {
				3453	switch (Inst.getOpcode()) {
				3454	case ARM::t2LDRi8:
				3455	Inst.setOpcode(ARM::t2LDRpci);
				3456	break;
				3457	case ARM::t2LDRBi8:
				3458	Inst.setOpcode(ARM::t2LDRBpci);
				3459	break;
				3460	case ARM::t2LDRSBi8:
				3461	Inst.setOpcode(ARM::t2LDRSBpci);
				3462	break;
				3463	case ARM::t2LDRHi8:
				3464	Inst.setOpcode(ARM::t2LDRHpci);
				3465	break;
				3466	case ARM::t2LDRSHi8:
				3467	Inst.setOpcode(ARM::t2LDRSHpci);
				3468	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3469	case ARM::t2PLDi8:
				3470	Inst.setOpcode(ARM::t2PLDpci);
				3471	break;
				3472	case ARM::t2PLIi8:
				3473	Inst.setOpcode(ARM::t2PLIpci);
				3474	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3475	default:
				3476	return MCDisassembler::Fail;
				3477	}
				3478	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3479	}
				3480
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3481	if (Rt == 15) {
				3482	switch (Inst.getOpcode()) {
				3483	case ARM::t2LDRSHi8:
				3484	return MCDisassembler::Fail;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3485	case ARM::t2LDRHi8:
				3486	if (!add)
				3487	Inst.setOpcode(ARM::t2PLDWi8);
				3488	break;
				3489	case ARM::t2LDRSBi8:
				3490	Inst.setOpcode(ARM::t2PLIi8);
				3491	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3492	default:
				3493	break;
				3494	}
				3495	}
				3496
				3497	switch (Inst.getOpcode()) {
				3498	case ARM::t2PLDi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3499	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3500	case ARM::t2PLIi8:
				3501	if (!hasV7Ops)
				3502	return MCDisassembler::Fail;
				3503	break;
				3504	case ARM::t2PLDWi8:
				3505	if (!hasV7Ops \|\| !hasMP)
				3506	return MCDisassembler::Fail;
				3507	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3508	default:
				3509	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3510	return MCDisassembler::Fail;
				3511	}
				3512
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3513	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3514	return MCDisassembler::Fail;
				3515	return S;
				3516	}
				3517
				3518	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3519	uint64_t Address, const void* Decoder) {
				3520	DecodeStatus S = MCDisassembler::Success;
				3521
				3522	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3523	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3524	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3525	imm \|= (Rn << 13);
				3526
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3527	const FeatureBitset &featureBits =
				3528	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3529
				3530	bool hasMP = featureBits[ARM::FeatureMP];
				3531	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3532
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3533	if (Rn == 15) {
				3534	switch (Inst.getOpcode()) {
				3535	case ARM::t2LDRi12:
				3536	Inst.setOpcode(ARM::t2LDRpci);
				3537	break;
				3538	case ARM::t2LDRHi12:
				3539	Inst.setOpcode(ARM::t2LDRHpci);
				3540	break;
				3541	case ARM::t2LDRSHi12:
				3542	Inst.setOpcode(ARM::t2LDRSHpci);
				3543	break;
				3544	case ARM::t2LDRBi12:
				3545	Inst.setOpcode(ARM::t2LDRBpci);
				3546	break;
				3547	case ARM::t2LDRSBi12:
				3548	Inst.setOpcode(ARM::t2LDRSBpci);
				3549	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3550	case ARM::t2PLDi12:
				3551	Inst.setOpcode(ARM::t2PLDpci);
				3552	break;
				3553	case ARM::t2PLIi12:
				3554	Inst.setOpcode(ARM::t2PLIpci);
				3555	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3556	default:
				3557	return MCDisassembler::Fail;
				3558	}
				3559	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3560	}
				3561
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3562	if (Rt == 15) {
				3563	switch (Inst.getOpcode()) {
				3564	case ARM::t2LDRSHi12:
				3565	return MCDisassembler::Fail;
				3566	case ARM::t2LDRHi12:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3567	Inst.setOpcode(ARM::t2PLDWi12);
				3568	break;
				3569	case ARM::t2LDRSBi12:
				3570	Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3571	break;
				3572	default:
				3573	break;
				3574	}
				3575	}
				3576
				3577	switch (Inst.getOpcode()) {
				3578	case ARM::t2PLDi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3579	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3580	case ARM::t2PLIi12:
				3581	if (!hasV7Ops)
				3582	return MCDisassembler::Fail;
				3583	break;
				3584	case ARM::t2PLDWi12:
				3585	if (!hasV7Ops \|\| !hasMP)
				3586	return MCDisassembler::Fail;
				3587	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3588	default:
				3589	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3590	return MCDisassembler::Fail;
				3591	}
				3592
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3593	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3594	return MCDisassembler::Fail;
				3595	return S;
				3596	}
				3597
				3598	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3599	uint64_t Address, const void* Decoder) {
				3600	DecodeStatus S = MCDisassembler::Success;
				3601
				3602	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3603	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3604	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3605	imm \|= (Rn << 9);
				3606
				3607	if (Rn == 15) {
				3608	switch (Inst.getOpcode()) {
				3609	case ARM::t2LDRT:
				3610	Inst.setOpcode(ARM::t2LDRpci);
				3611	break;
				3612	case ARM::t2LDRBT:
				3613	Inst.setOpcode(ARM::t2LDRBpci);
				3614	break;
				3615	case ARM::t2LDRHT:
				3616	Inst.setOpcode(ARM::t2LDRHpci);
				3617	break;
				3618	case ARM::t2LDRSBT:
				3619	Inst.setOpcode(ARM::t2LDRSBpci);
				3620	break;
				3621	case ARM::t2LDRSHT:
				3622	Inst.setOpcode(ARM::t2LDRSHpci);
				3623	break;
				3624	default:
				3625	return MCDisassembler::Fail;
				3626	}
				3627	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3628	}
				3629
				3630	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3631	return MCDisassembler::Fail;
				3632	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3633	return MCDisassembler::Fail;
				3634	return S;
				3635	}
				3636
				3637	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3638	uint64_t Address, const void* Decoder) {
				3639	DecodeStatus S = MCDisassembler::Success;
				3640
				3641	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3642	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3643	int imm = fieldFromInstruction(Insn, 0, 12);
				3644
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3645	const FeatureBitset &featureBits =
				3646	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3647
				3648	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3649
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3650	if (Rt == 15) {
				3651	switch (Inst.getOpcode()) {
				3652	case ARM::t2LDRBpci:
				3653	case ARM::t2LDRHpci:
				3654	Inst.setOpcode(ARM::t2PLDpci);
				3655	break;
				3656	case ARM::t2LDRSBpci:
				3657	Inst.setOpcode(ARM::t2PLIpci);
				3658	break;
				3659	case ARM::t2LDRSHpci:
				3660	return MCDisassembler::Fail;
				3661	default:
				3662	break;
				3663	}
				3664	}
				3665
				3666	switch(Inst.getOpcode()) {
				3667	case ARM::t2PLDpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3668	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3669	case ARM::t2PLIpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3670	if (!hasV7Ops)
				3671	return MCDisassembler::Fail;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3672	break;
				3673	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3674	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3675	return MCDisassembler::Fail;
				3676	}
				3677
				3678	if (!U) {
				3679	// Special case for #-0.
				3680	if (imm == 0)
				3681	imm = INT32_MIN;
				3682	else
				3683	imm = -imm;
				3684	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3685	Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3686
				3687	return S;
				3688	}
				3689
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3690	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3691	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3692	if (Val == 0)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3693	Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3694	else {
				3695	int imm = Val & 0xFF;
				3696
				3697	if (!(Val & 0x100)) imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3698	Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3699	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3700
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3701	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3702	}
				3703
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3704	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3705	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3706	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3707
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3708	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3709	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3710
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3711	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3712	return MCDisassembler::Fail;
				3713	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3714	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3715
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3716	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3717	}
				3718
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3719	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3720	uint64_t Address, const void *Decoder) {
				3721	DecodeStatus S = MCDisassembler::Success;
				3722
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3723	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3724	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3725
				3726	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3727	return MCDisassembler::Fail;
				3728
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3729	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3730
				3731	return S;
				3732	}
				3733
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3734	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3735	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3736	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3737	if (Val == 0)
				3738	imm = INT32_MIN;
				3739	else if (!(Val & 0x100))
				3740	imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3741	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3742
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3743	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3744	}
				3745
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3746	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3747	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3748	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3749
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3750	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3751	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3752
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3753	// Thumb stores cannot use PC as dest register.
				3754	switch (Inst.getOpcode()) {
				3755	case ARM::t2STRT:
				3756	case ARM::t2STRBT:
				3757	case ARM::t2STRHT:
				3758	case ARM::t2STRi8:
				3759	case ARM::t2STRHi8:
				3760	case ARM::t2STRBi8:
				3761	if (Rn == 15)
				3762	return MCDisassembler::Fail;
				3763	break;
				3764	default:
				3765	break;
				3766	}
				3767
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3768	// Some instructions always use an additive offset.
				3769	switch (Inst.getOpcode()) {
				3770	case ARM::t2LDRT:
				3771	case ARM::t2LDRBT:
				3772	case ARM::t2LDRHT:
				3773	case ARM::t2LDRSBT:
				3774	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3775	case ARM::t2STRT:
				3776	case ARM::t2STRBT:
				3777	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3778	imm \|= 0x100;
				3779	break;
				3780	default:
				3781	break;
				3782	}
				3783
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3784	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3785	return MCDisassembler::Fail;
				3786	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3787	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3788
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3789	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3790	}
				3791
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3792	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3793	uint64_t Address, const void *Decoder) {
				3794	DecodeStatus S = MCDisassembler::Success;
				3795
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3796	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3797	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3798	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3799	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3800	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3801	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3802
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3803	if (Rn == 15) {
				3804	switch (Inst.getOpcode()) {
				3805	case ARM::t2LDR_PRE:
				3806	case ARM::t2LDR_POST:
				3807	Inst.setOpcode(ARM::t2LDRpci);
				3808	break;
				3809	case ARM::t2LDRB_PRE:
				3810	case ARM::t2LDRB_POST:
				3811	Inst.setOpcode(ARM::t2LDRBpci);
				3812	break;
				3813	case ARM::t2LDRH_PRE:
				3814	case ARM::t2LDRH_POST:
				3815	Inst.setOpcode(ARM::t2LDRHpci);
				3816	break;
				3817	case ARM::t2LDRSB_PRE:
				3818	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3819	if (Rt == 15)
				3820	Inst.setOpcode(ARM::t2PLIpci);
				3821	else
				3822	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3823	break;
				3824	case ARM::t2LDRSH_PRE:
				3825	case ARM::t2LDRSH_POST:
				3826	Inst.setOpcode(ARM::t2LDRSHpci);
				3827	break;
				3828	default:
				3829	return MCDisassembler::Fail;
				3830	}
				3831	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3832	}
				3833
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3834	if (!load) {
				3835	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3836	return MCDisassembler::Fail;
				3837	}
				3838
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3839	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3840	return MCDisassembler::Fail;
				3841
				3842	if (load) {
				3843	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3844	return MCDisassembler::Fail;
				3845	}
				3846
				3847	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3848	return MCDisassembler::Fail;
				3849
				3850	return S;
				3851	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3852
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3853	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3854	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3855	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3856
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3857	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3858	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3859
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3860	// Thumb stores cannot use PC as dest register.
				3861	switch (Inst.getOpcode()) {
				3862	case ARM::t2STRi12:
				3863	case ARM::t2STRBi12:
				3864	case ARM::t2STRHi12:
				3865	if (Rn == 15)
				3866	return MCDisassembler::Fail;
Adrian Prantl	0e6694d	2017-12-19 22:05:25 +0000	[diff] [blame]	3867	break;
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3868	default:
				3869	break;
				3870	}
				3871
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3872	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3873	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3874	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3875
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3876	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3877	}
				3878
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3879	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3880	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3881	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3882
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3883	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3884	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3885	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3886
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3887	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3888	}
				3889
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3890	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3891	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3892	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3893
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3894	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3895	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3896	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3897
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3898	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3899	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3900	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3901	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3902	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3903	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3904	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3905
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3906	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3907	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3908	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3909	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3910	}
				3911
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3912	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3913	}
				3914
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3915	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3916	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3917	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3918	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3919
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3920	Inst.addOperand(MCOperand::createImm(imod));
				3921	Inst.addOperand(MCOperand::createImm(flags));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3922
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3923	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3924	}
				3925
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3926	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3927	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3928	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3929	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3930	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3931
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3932	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3933	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3934	Inst.addOperand(MCOperand::createImm(add));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3935
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3936	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3937	}
				3938
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3939	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3940	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3941	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3942	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3943	// the encoded instruction. So here change to I1 and I2 values via:
				3944	// I1 = NOT(J1 EOR S);
				3945	// I2 = NOT(J2 EOR S);
				3946	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3947	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3948	unsigned S = (Val >> 23) & 1;
				3949	unsigned J1 = (Val >> 22) & 1;
				3950	unsigned J2 = (Val >> 21) & 1;
				3951	unsigned I1 = !(J1 ^ S);
				3952	unsigned I2 = !(J2 ^ S);
				3953	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3954	int imm32 = SignExtend32<25>(tmp << 1);
				3955
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3956	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3957	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3958	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3959	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3960	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3961	}
				3962
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3963	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3964	uint64_t Address, const void *Decoder) {
				3965	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3966	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3967
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3968	const FeatureBitset &featureBits =
				3969	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3970
				3971	if (featureBits[ARM::HasV8Ops] && !(Val == 14 \|\| Val == 15))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3972	return MCDisassembler::Fail;
				3973
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3974	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3975	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3976	}
				3977
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3978	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3979	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3980	uint64_t Address, const void *Decoder) {
				3981	DecodeStatus S = MCDisassembler::Success;
				3982
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3983	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3984	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3985
				3986	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3987	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3988	return MCDisassembler::Fail;
				3989	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3990	return MCDisassembler::Fail;
				3991	return S;
				3992	}
				3993
				3994	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3995	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3996	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3997	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3998
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3999	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4000	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4001	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4002	switch (opc) {
				4003	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4004	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4005	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4006	Inst.setOpcode(ARM::t2DSB);
				4007	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4008	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4009	Inst.setOpcode(ARM::t2DMB);
				4010	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4011	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4012	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	4013	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4014	}
				4015
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4016	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4017	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4018	}
				4019
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4020	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				4021	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				4022	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				4023	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				4024	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4025
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4026	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				4027	return MCDisassembler::Fail;
				4028	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4029	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4030
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4031	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4032	}
				4033
				4034	// Decode a shifted immediate operand. These basically consist
				4035	// of an 8-bit value, and a 4-bit directive that specifies either
				4036	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4037	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4038	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4039	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4040	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4041	unsigned byte = fieldFromInstruction(Val, 8, 2);
				4042	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4043	switch (byte) {
				4044	case 0:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4045	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4046	break;
				4047	case 1:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4048	Inst.addOperand(MCOperand::createImm((imm << 16) \| imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4049	break;
				4050	case 2:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4051	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 8)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4052	break;
				4053	case 3:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4054	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 16) \|
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4055	(imm << 8) \| imm));
				4056	break;
				4057	}
				4058	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4059	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				4060	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4061	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4062	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4063	}
				4064
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4065	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4066	}
				4067
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4068	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4069	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	4070	uint64_t Address, const void *Decoder) {
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4071	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	4072	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4073	Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4074	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4075	}
				4076
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4077	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	4078	uint64_t Address,
				4079	const void *Decoder) {
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4080	// Val is passed in as S:J1:J2:imm10:imm11
				4081	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				4082	// the encoded instruction. So here change to I1 and I2 values via:
				4083	// I1 = NOT(J1 EOR S);
				4084	// I2 = NOT(J2 EOR S);
				4085	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	4086	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4087	unsigned S = (Val >> 23) & 1;
				4088	unsigned J1 = (Val >> 22) & 1;
				4089	unsigned J2 = (Val >> 21) & 1;
				4090	unsigned I1 = !(J1 ^ S);
				4091	unsigned I2 = !(J2 ^ S);
				4092	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				4093	int imm32 = SignExtend32<25>(tmp << 1);
				4094
				4095	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	4096	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4097	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4098	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4099	}
				4100
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4101	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4102	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	4103	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4104	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4105
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4106	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4107	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4108	}
				4109
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4110	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				4111	uint64_t Address, const void *Decoder) {
				4112	if (Val & ~0xf)
				4113	return MCDisassembler::Fail;
				4114
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4115	Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4116	return MCDisassembler::Success;
				4117	}
				4118
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4119	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4120	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4121	DecodeStatus S = MCDisassembler::Success;
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4122	const FeatureBitset &FeatureBits =
				4123	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				4124
				4125	if (FeatureBits[ARM::FeatureMClass]) {
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4126	unsigned ValLow = Val & 0xff;
				4127
				4128	// Validate the SYSm value first.
				4129	switch (ValLow) {
				4130	case 0: // apsr
				4131	case 1: // iapsr
				4132	case 2: // eapsr
				4133	case 3: // xpsr
				4134	case 5: // ipsr
				4135	case 6: // epsr
				4136	case 7: // iepsr
				4137	case 8: // msp
				4138	case 9: // psp
				4139	case 16: // primask
				4140	case 20: // control
				4141	break;
				4142	case 17: // basepri
				4143	case 18: // basepri_max
				4144	case 19: // faultmask
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4145	if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4146	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4147	return MCDisassembler::Fail;
				4148	break;
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4149	case 0x8a: // msplim_ns
				4150	case 0x8b: // psplim_ns
				4151	case 0x91: // basepri_ns
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4152	case 0x93: // faultmask_ns
				4153	if (!(FeatureBits[ARM::HasV8MMainlineOps]))
				4154	return MCDisassembler::Fail;
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	4155	LLVM_FALLTHROUGH;
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4156	case 10: // msplim
				4157	case 11: // psplim
				4158	case 0x88: // msp_ns
				4159	case 0x89: // psp_ns
				4160	case 0x90: // primask_ns
				4161	case 0x94: // control_ns
				4162	case 0x98: // sp_ns
				4163	if (!(FeatureBits[ARM::Feature8MSecExt]))
				4164	return MCDisassembler::Fail;
				4165	break;
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4166	default:
Simi Pallipurath	75c6bfe	2018-03-06 15:21:19 +0000	[diff] [blame]	4167	// Architecturally defined as unpredictable
				4168	S = MCDisassembler::SoftFail;
				4169	break;
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4170	}
				4171
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4172	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4173	unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4174	if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4175	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4176	// unpredictable.
				4177	if (Mask != 2)
				4178	S = MCDisassembler::SoftFail;
				4179	}
				4180	else {
				4181	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4182	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4183	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4184	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4185	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4186	// only if the processor includes the DSP extension.
				4187	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
Artyom Skrobov	cf29644	2015-09-24 17:31:16 +0000	[diff] [blame]	4188	(!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4189	S = MCDisassembler::SoftFail;
				4190	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4191	}
				4192	} else {
				4193	// A/R class
				4194	if (Val == 0)
				4195	return MCDisassembler::Fail;
				4196	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4197	Inst.addOperand(MCOperand::createImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4198	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4199	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4200
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4201	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4202	uint64_t Address, const void *Decoder) {
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4203	unsigned R = fieldFromInstruction(Val, 5, 1);
				4204	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4205
				4206	// The table of encodings for these banked registers comes from B9.2.3 of the
				4207	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4208	// neater. So by fiat, these values are UNPREDICTABLE:
Oliver Stannard	133b608	2018-02-08 14:31:22 +0000	[diff] [blame]	4209	if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) \| SysM))
				4210	return MCDisassembler::Fail;
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4211
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4212	Inst.addOperand(MCOperand::createImm(Val));
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4213	return MCDisassembler::Success;
				4214	}
				4215
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4216	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4217	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4218	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4219
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4220	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4221	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4222	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4223
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4224	if (Rn == 0xF)
				4225	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4226
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4227	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4228	return MCDisassembler::Fail;
				4229	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4230	return MCDisassembler::Fail;
				4231	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4232	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4233
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4234	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4235	}
				4236
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4237	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	4238	uint64_t Address,
				4239	const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4240	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4241
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4242	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4243	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4244	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4245	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4246
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4247	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4248	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4249
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4250	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4251	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4252
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4253	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4254	return MCDisassembler::Fail;
				4255	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4256	return MCDisassembler::Fail;
				4257	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4258	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4259
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4260	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4261	}
				4262
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4263	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4264	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4265	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4266
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4267	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4268	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4269	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4270	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4271	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4272	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4273
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4274	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4275
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4276	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4277	return MCDisassembler::Fail;
				4278	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4279	return MCDisassembler::Fail;
				4280	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4281	return MCDisassembler::Fail;
				4282	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4283	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4284
				4285	return S;
				4286	}
				4287
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4288	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4289	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4290	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4291
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4292	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4293	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4294	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4295	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4296	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4297	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4298	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4299
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4300	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4301	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4302
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4303	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4304	return MCDisassembler::Fail;
				4305	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4306	return MCDisassembler::Fail;
				4307	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4308	return MCDisassembler::Fail;
				4309	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4310	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4311
				4312	return S;
				4313	}
				4314
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4315	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4316	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4317	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4318
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4319	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4320	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4321	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4322	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4323	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4324	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4325
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4326	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4327
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4328	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4329	return MCDisassembler::Fail;
				4330	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4331	return MCDisassembler::Fail;
				4332	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4333	return MCDisassembler::Fail;
				4334	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4335	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4336
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4337	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4338	}
				4339
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4340	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4341	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4342	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4343
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4344	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4345	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4346	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4347	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4348	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4349	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4350
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4351	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4352
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4353	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4354	return MCDisassembler::Fail;
				4355	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4356	return MCDisassembler::Fail;
				4357	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4358	return MCDisassembler::Fail;
				4359	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4360	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4361
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4362	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4363	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4364
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4365	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4366	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4367	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4368
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4369	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4370	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4371	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4372	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4373	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4374
				4375	unsigned align = 0;
				4376	unsigned index = 0;
				4377	switch (size) {
				4378	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4379	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4380	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4381	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4382	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4383	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4384	break;
				4385	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4386	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4387	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4388	index = fieldFromInstruction(Insn, 6, 2);
				4389	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4390	align = 2;
				4391	break;
				4392	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4393	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4394	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4395	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4396
				4397	switch (fieldFromInstruction(Insn, 4, 2)) {
				4398	case 0 :
				4399	align = 0; break;
				4400	case 3:
				4401	align = 4; break;
				4402	default:
				4403	return MCDisassembler::Fail;
				4404	}
				4405	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4406	}
				4407
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4408	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4409	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4410	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4411	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4412	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4413	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4414	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4415	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4416	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4417	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4418	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4419	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4420	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4421	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4422	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4423	}
				4424
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4425	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4426	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4427	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4428
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4429	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4430	}
				4431
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4432	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4433	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4434	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4435
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4436	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4437	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4438	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4439	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4440	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4441
				4442	unsigned align = 0;
				4443	unsigned index = 0;
				4444	switch (size) {
				4445	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4446	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4447	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4448	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4449	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4450	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4451	break;
				4452	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4453	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4454	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4455	index = fieldFromInstruction(Insn, 6, 2);
				4456	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4457	align = 2;
				4458	break;
				4459	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4460	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4461	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4462	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4463
				4464	switch (fieldFromInstruction(Insn, 4, 2)) {
				4465	case 0:
				4466	align = 0; break;
				4467	case 3:
				4468	align = 4; break;
				4469	default:
				4470	return MCDisassembler::Fail;
				4471	}
				4472	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4473	}
				4474
				4475	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4476	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4477	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4478	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4479	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4480	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4481	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4482	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4483	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4484	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4485	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4486	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4487	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4488	}
				4489
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4490	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4491	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4492	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4493
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4494	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4495	}
				4496
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4497	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4498	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4499	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4500
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4501	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4502	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4503	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4504	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4505	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4506
				4507	unsigned align = 0;
				4508	unsigned index = 0;
				4509	unsigned inc = 1;
				4510	switch (size) {
				4511	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4512	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4513	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4514	index = fieldFromInstruction(Insn, 5, 3);
				4515	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4516	align = 2;
				4517	break;
				4518	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4519	index = fieldFromInstruction(Insn, 6, 2);
				4520	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4521	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4522	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4523	inc = 2;
				4524	break;
				4525	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4526	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4527	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4528	index = fieldFromInstruction(Insn, 7, 1);
				4529	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4530	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4531	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4532	inc = 2;
				4533	break;
				4534	}
				4535
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4536	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4537	return MCDisassembler::Fail;
				4538	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4539	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4540	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4541	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4542	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4544	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4545	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4546	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4547	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4548	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4549	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4550	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4551	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4552	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4553	}
				4554
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4555	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4556	return MCDisassembler::Fail;
				4557	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4558	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4559	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4560
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4561	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4562	}
				4563
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4564	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4565	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4566	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4567
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4568	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4569	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4570	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4571	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4572	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4573
				4574	unsigned align = 0;
				4575	unsigned index = 0;
				4576	unsigned inc = 1;
				4577	switch (size) {
				4578	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4579	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4580	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4581	index = fieldFromInstruction(Insn, 5, 3);
				4582	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4583	align = 2;
				4584	break;
				4585	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4586	index = fieldFromInstruction(Insn, 6, 2);
				4587	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4588	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4589	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4590	inc = 2;
				4591	break;
				4592	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4593	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4594	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4595	index = fieldFromInstruction(Insn, 7, 1);
				4596	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4597	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4598	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4599	inc = 2;
				4600	break;
				4601	}
				4602
				4603	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4604	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4605	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4606	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4607	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4608	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4609	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4610	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4611	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4612	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4613	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4614	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4615	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4616	}
				4617
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4618	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4619	return MCDisassembler::Fail;
				4620	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4621	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4622	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4623
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4624	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4625	}
				4626
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4627	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4628	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4629	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4630
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4631	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4632	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4633	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4634	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4635	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4636
				4637	unsigned align = 0;
				4638	unsigned index = 0;
				4639	unsigned inc = 1;
				4640	switch (size) {
				4641	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4642	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4643	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4644	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4645	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4646	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4647	break;
				4648	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4649	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4650	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4651	index = fieldFromInstruction(Insn, 6, 2);
				4652	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4653	inc = 2;
				4654	break;
				4655	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4656	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4657	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4658	index = fieldFromInstruction(Insn, 7, 1);
				4659	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4660	inc = 2;
				4661	break;
				4662	}
				4663
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4664	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4665	return MCDisassembler::Fail;
				4666	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4667	return MCDisassembler::Fail;
				4668	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4669	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4670
				4671	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4672	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4673	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4674	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4675	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4676	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4677	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4678	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4679	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4680	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4681	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4682	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4683	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4684	}
				4685
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4686	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4687	return MCDisassembler::Fail;
				4688	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4689	return MCDisassembler::Fail;
				4690	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4691	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4692	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4693
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4694	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4695	}
				4696
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4697	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4698	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4699	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4700
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4701	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4702	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4703	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4704	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4705	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4706
				4707	unsigned align = 0;
				4708	unsigned index = 0;
				4709	unsigned inc = 1;
				4710	switch (size) {
				4711	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4712	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4713	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4714	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4715	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4716	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4717	break;
				4718	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4719	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4720	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4721	index = fieldFromInstruction(Insn, 6, 2);
				4722	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4723	inc = 2;
				4724	break;
				4725	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4726	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4727	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4728	index = fieldFromInstruction(Insn, 7, 1);
				4729	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4730	inc = 2;
				4731	break;
				4732	}
				4733
				4734	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4735	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4736	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4737	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4738	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4739	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4740	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4741	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4742	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4743	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4744	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4745	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4746	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4747	}
				4748
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4749	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4750	return MCDisassembler::Fail;
				4751	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4752	return MCDisassembler::Fail;
				4753	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4754	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4755	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4756
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4757	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4758	}
				4759
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4760	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4761	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4762	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4763
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4764	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4765	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4766	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4767	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4768	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4769
				4770	unsigned align = 0;
				4771	unsigned index = 0;
				4772	unsigned inc = 1;
				4773	switch (size) {
				4774	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4775	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4776	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4777	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4778	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4779	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4780	break;
				4781	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4782	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4783	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4784	index = fieldFromInstruction(Insn, 6, 2);
				4785	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4786	inc = 2;
				4787	break;
				4788	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4789	switch (fieldFromInstruction(Insn, 4, 2)) {
				4790	case 0:
				4791	align = 0; break;
				4792	case 3:
				4793	return MCDisassembler::Fail;
				4794	default:
				4795	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4796	}
				4797
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4798	index = fieldFromInstruction(Insn, 7, 1);
				4799	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4800	inc = 2;
				4801	break;
				4802	}
				4803
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4804	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4805	return MCDisassembler::Fail;
				4806	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4807	return MCDisassembler::Fail;
				4808	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4809	return MCDisassembler::Fail;
				4810	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4811	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4812
				4813	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4814	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4815	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4816	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4817	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4818	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4819	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4820	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4821	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4822	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4823	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4824	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4825	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4826	}
				4827
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4828	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4829	return MCDisassembler::Fail;
				4830	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4831	return MCDisassembler::Fail;
				4832	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4833	return MCDisassembler::Fail;
				4834	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4835	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4836	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4837
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4838	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4839	}
				4840
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4841	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4842	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4843	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4844
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4845	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4846	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4847	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4848	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4849	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4850
				4851	unsigned align = 0;
				4852	unsigned index = 0;
				4853	unsigned inc = 1;
				4854	switch (size) {
				4855	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4856	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4857	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4858	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4859	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4860	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4861	break;
				4862	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4863	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4864	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4865	index = fieldFromInstruction(Insn, 6, 2);
				4866	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4867	inc = 2;
				4868	break;
				4869	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4870	switch (fieldFromInstruction(Insn, 4, 2)) {
				4871	case 0:
				4872	align = 0; break;
				4873	case 3:
				4874	return MCDisassembler::Fail;
				4875	default:
				4876	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4877	}
				4878
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4879	index = fieldFromInstruction(Insn, 7, 1);
				4880	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4881	inc = 2;
				4882	break;
				4883	}
				4884
				4885	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4886	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4887	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4888	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4889	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4890	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4891	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4892	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4893	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4894	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4895	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4896	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4897	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4898	}
				4899
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4900	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4901	return MCDisassembler::Fail;
				4902	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4903	return MCDisassembler::Fail;
				4904	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4905	return MCDisassembler::Fail;
				4906	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4907	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4908	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4909
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4910	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4911	}
				4912
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4913	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4914	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4915	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4916	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4917	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4918	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4919	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4920	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4921
				4922	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4923	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4924
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4925	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4926	return MCDisassembler::Fail;
				4927	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4928	return MCDisassembler::Fail;
				4929	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4930	return MCDisassembler::Fail;
				4931	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4932	return MCDisassembler::Fail;
				4933	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4934	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4935
				4936	return S;
				4937	}
				4938
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4939	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4940	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4941	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4942	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4943	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4944	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4945	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4946	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4947
				4948	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4949	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4950
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4951	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4952	return MCDisassembler::Fail;
				4953	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4954	return MCDisassembler::Fail;
				4955	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4956	return MCDisassembler::Fail;
				4957	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4958	return MCDisassembler::Fail;
				4959	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4960	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4961
				4962	return S;
				4963	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4964
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4965	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4966	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4967	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4968	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4969	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4970
				4971	if (pred == 0xF) {
				4972	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4973	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4974	}
				4975
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4976	if (mask == 0x0)
				4977	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4978
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4979	Inst.addOperand(MCOperand::createImm(pred));
				4980	Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4981	return S;
				4982	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4983
				4984	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4985	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4986	uint64_t Address, const void *Decoder) {
				4987	DecodeStatus S = MCDisassembler::Success;
				4988
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4989	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4990	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4991	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4992	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4993	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4994	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4995	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4996	bool writeback = (W == 1) \| (P == 0);
				4997
				4998	addr \|= (U << 8) \| (Rn << 9);
				4999
				5000	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				5001	Check(S, MCDisassembler::SoftFail);
				5002	if (Rt == Rt2)
				5003	Check(S, MCDisassembler::SoftFail);
				5004
				5005	// Rt
				5006	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5007	return MCDisassembler::Fail;
				5008	// Rt2
				5009	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5010	return MCDisassembler::Fail;
				5011	// Writeback operand
				5012	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				5013	return MCDisassembler::Fail;
				5014	// addr
				5015	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5016	return MCDisassembler::Fail;
				5017
				5018	return S;
				5019	}
				5020
				5021	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5022	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5023	uint64_t Address, const void *Decoder) {
				5024	DecodeStatus S = MCDisassembler::Success;
				5025
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5026	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5027	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				5028	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5029	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				5030	unsigned W = fieldFromInstruction(Insn, 21, 1);
				5031	unsigned U = fieldFromInstruction(Insn, 23, 1);
				5032	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5033	bool writeback = (W == 1) \| (P == 0);
				5034
				5035	addr \|= (U << 8) \| (Rn << 9);
				5036
				5037	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				5038	Check(S, MCDisassembler::SoftFail);
				5039
				5040	// Writeback operand
				5041	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				5042	return MCDisassembler::Fail;
				5043	// Rt
				5044	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5045	return MCDisassembler::Fail;
				5046	// Rt2
				5047	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5048	return MCDisassembler::Fail;
				5049	// addr
				5050	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5051	return MCDisassembler::Fail;
				5052
				5053	return S;
				5054	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5055
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5056	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5057	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5058	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				5059	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5060	if (sign1 != sign2) return MCDisassembler::Fail;
				5061
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5062	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				5063	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				5064	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5065	Val \|= sign1 << 12;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5066	Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5067
				5068	return MCDisassembler::Success;
				5069	}
				5070
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5071	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5072	uint64_t Address,
				5073	const void *Decoder) {
				5074	DecodeStatus S = MCDisassembler::Success;
				5075
				5076	// Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith	3131e85	2015-01-19 16:37:17 +0000	[diff] [blame]	5077	if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5078	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5079	return S;
				5080	}
				5081
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5082	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5083	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5084	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5085	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				5086	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5087	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5088
				5089	if (pred == 0xF)
				5090	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				5091
				5092	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	5093
				5094	if (Rt == Rn \|\| Rn == Rt2)
				5095	S = MCDisassembler::SoftFail;
				5096
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5097	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5098	return MCDisassembler::Fail;
				5099	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5100	return MCDisassembler::Fail;
				5101	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5102	return MCDisassembler::Fail;
				5103	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5104	return MCDisassembler::Fail;
				5105
				5106	return S;
				5107	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5108
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5109	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5110	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5111	const FeatureBitset &featureBits =
				5112	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5113	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5114
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5115	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5116	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5117	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5118	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5119	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5120	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5121	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5122
				5123	DecodeStatus S = MCDisassembler::Success;
				5124
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5125	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5126	if (!(imm & 0x38)) {
				5127	if (cmode == 0xF) {
				5128	if (op == 1) return MCDisassembler::Fail;
				5129	Inst.setOpcode(ARM::VMOVv2f32);
				5130	}
				5131	if (hasFullFP16) {
				5132	if (cmode == 0xE) {
				5133	if (op == 1) {
				5134	Inst.setOpcode(ARM::VMOVv1i64);
				5135	} else {
				5136	Inst.setOpcode(ARM::VMOVv8i8);
				5137	}
				5138	}
				5139	if (cmode == 0xD) {
				5140	if (op == 1) {
				5141	Inst.setOpcode(ARM::VMVNv2i32);
				5142	} else {
				5143	Inst.setOpcode(ARM::VMOVv2i32);
				5144	}
				5145	}
				5146	if (cmode == 0xC) {
				5147	if (op == 1) {
				5148	Inst.setOpcode(ARM::VMVNv2i32);
				5149	} else {
				5150	Inst.setOpcode(ARM::VMOVv2i32);
				5151	}
				5152	}
				5153	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5154	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5155	}
				5156
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5157	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5158
				5159	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				5160	return MCDisassembler::Fail;
				5161	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5162	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5163	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5164
				5165	return S;
				5166	}
				5167
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5168	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5169	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5170	const FeatureBitset &featureBits =
				5171	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5172	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5173
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5174	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5175	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5176	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5177	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5178	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5179	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5180	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5181
				5182	DecodeStatus S = MCDisassembler::Success;
				5183
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5184	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5185	if (!(imm & 0x38)) {
				5186	if (cmode == 0xF) {
				5187	if (op == 1) return MCDisassembler::Fail;
				5188	Inst.setOpcode(ARM::VMOVv4f32);
				5189	}
				5190	if (hasFullFP16) {
				5191	if (cmode == 0xE) {
				5192	if (op == 1) {
				5193	Inst.setOpcode(ARM::VMOVv2i64);
				5194	} else {
				5195	Inst.setOpcode(ARM::VMOVv16i8);
				5196	}
				5197	}
				5198	if (cmode == 0xD) {
				5199	if (op == 1) {
				5200	Inst.setOpcode(ARM::VMVNv4i32);
				5201	} else {
				5202	Inst.setOpcode(ARM::VMOVv4i32);
				5203	}
				5204	}
				5205	if (cmode == 0xC) {
				5206	if (op == 1) {
				5207	Inst.setOpcode(ARM::VMVNv4i32);
				5208	} else {
				5209	Inst.setOpcode(ARM::VMOVv4i32);
				5210	}
				5211	}
				5212	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5213	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5214	}
				5215
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5216	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5217
				5218	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5219	return MCDisassembler::Fail;
				5220	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5221	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5222	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5223
				5224	return S;
				5225	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5226
Sam Parker	963da5b	2017-09-29 13:11:33 +0000	[diff] [blame]	5227	static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
				5228	unsigned Insn,
				5229	uint64_t Address,
				5230	const void *Decoder) {
				5231	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5232	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5233	unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
				5234	Vn \|= (fieldFromInstruction(Insn, 7, 1) << 4);
				5235	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5236	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5237	unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
				5238	unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
				5239
				5240	DecodeStatus S = MCDisassembler::Success;
				5241
				5242	auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
				5243
				5244	if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
				5245	return MCDisassembler::Fail;
				5246	if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
				5247	return MCDisassembler::Fail;
				5248	if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
				5249	return MCDisassembler::Fail;
				5250	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5251	return MCDisassembler::Fail;
				5252	// The lane index does not have any bits in the encoding, because it can only
				5253	// be 0.
				5254	Inst.addOperand(MCOperand::createImm(0));
				5255	Inst.addOperand(MCOperand::createImm(rotate));
				5256
				5257	return S;
				5258	}
				5259
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5260	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5261	uint64_t Address, const void *Decoder) {
				5262	DecodeStatus S = MCDisassembler::Success;
				5263
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5264	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5265	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5266	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5267	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5268	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	5269
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5270	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5271	S = MCDisassembler::SoftFail;
				5272
				5273	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5274	return MCDisassembler::Fail;
				5275	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5276	return MCDisassembler::Fail;
				5277	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5278	return MCDisassembler::Fail;
				5279	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5280	return MCDisassembler::Fail;
				5281	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5282	return MCDisassembler::Fail;
				5283
				5284	return S;
				5285	}
				5286
Eugene Zelenko	e79c077	2017-01-27 23:58:02 +0000	[diff] [blame]	5287	static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5288	uint64_t Address, const void *Decoder) {
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5289	DecodeStatus S = MCDisassembler::Success;
				5290
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5291	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5292	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5293	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5294	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5295	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5296
				5297	if ((cop & ~0x1) == 0xa)
				5298	return MCDisassembler::Fail;
				5299
				5300	if (Rt == Rt2)
				5301	S = MCDisassembler::SoftFail;
				5302
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5303	// We have to check if the instruction is MRRC2
				5304	// or MCRR2 when constructing the operands for
				5305	// Inst. Reason is because MRRC2 stores to two
				5306	// registers so it's tablegen desc has has two
				5307	// outputs whereas MCRR doesn't store to any
				5308	// registers so all of it's operands are listed
				5309	// as inputs, therefore the operand order for
				5310	// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
				5311	// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
				5312
				5313	if (Inst.getOpcode() == ARM::MRRC2) {
				5314	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5315	return MCDisassembler::Fail;
				5316	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5317	return MCDisassembler::Fail;
				5318	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5319	Inst.addOperand(MCOperand::createImm(cop));
				5320	Inst.addOperand(MCOperand::createImm(opc1));
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5321	if (Inst.getOpcode() == ARM::MCRR2) {
				5322	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5323	return MCDisassembler::Fail;
				5324	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5325	return MCDisassembler::Fail;
				5326	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5327	Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5328
				5329	return S;
				5330	}
Andre Vieira	640527f	2017-09-22 12:17:42 +0000	[diff] [blame]	5331
				5332	static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
				5333	uint64_t Address,
				5334	const void *Decoder) {
				5335	const FeatureBitset &featureBits =
				5336	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5337	DecodeStatus S = MCDisassembler::Success;
				5338
				5339	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5340
				5341	if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
				5342	if (Rt == 13 \|\| Rt == 15)
				5343	S = MCDisassembler::SoftFail;
				5344	Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
				5345	} else
				5346	Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
				5347
Andre Vieira	d4a2570	2017-10-18 14:47:37 +0000	[diff] [blame]	5348	if (featureBits[ARM::ModeThumb]) {
				5349	Inst.addOperand(MCOperand::createImm(ARMCC::AL));
				5350	Inst.addOperand(MCOperand::createReg(0));
				5351	} else {
				5352	unsigned pred = fieldFromInstruction(Val, 28, 4);
				5353	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5354	return MCDisassembler::Fail;
				5355	}
Andre Vieira	640527f	2017-09-22 12:17:42 +0000	[diff] [blame]	5356
				5357	return S;
				5358	}