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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng81a03822007-11-17 00:40:40 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
67 ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000072 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
73 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
Evan Cheng81a03822007-11-17 00:40:40 +000076 Virt2SplitMap.grow(LastVirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +000077 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000078}
79
Chris Lattner8c4d88d2004-09-30 01:54:45 +000080int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
81 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000082 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000083 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000084 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
85 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
86 RC->getAlignment());
87 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000088 ++NumSpills;
89 return frameIndex;
90}
91
92void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
93 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000094 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000095 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000096 assert((frameIndex >= 0 ||
97 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
98 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000099 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +0000100}
101
Evan Cheng2638e1a2007-03-20 08:13:50 +0000102int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
103 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000104 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000105 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000106 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000107 return ReMatId++;
108}
109
Evan Cheng549f27d32007-08-13 23:45:17 +0000110void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
111 assert(MRegisterInfo::isVirtualRegister(virtReg));
112 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
113 "attempt to assign re-mat id to already spilled register");
114 Virt2ReMatIdMap[virtReg] = id;
115}
116
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000117void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Evan Chengaee4af62007-12-02 08:30:39 +0000118 MachineInstr *NewMI, ModRef MRInfo) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000119 // Move previous memory references folded to new instruction.
120 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000121 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000122 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
123 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000124 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000125 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000126
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000127 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000128 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000129}
130
Evan Cheng7f566252007-10-13 02:50:24 +0000131void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
132 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
133 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
134}
135
Chris Lattner7f690e62004-09-30 02:15:18 +0000136void VirtRegMap::print(std::ostream &OS) const {
137 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000138
Chris Lattner7f690e62004-09-30 02:15:18 +0000139 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000140 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000141 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
142 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
143 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000144
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000145 }
146
147 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000148 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
149 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
150 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
151 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000152}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000153
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000154void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000155 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000156}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000157
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000158
159//===----------------------------------------------------------------------===//
160// Simple Spiller Implementation
161//===----------------------------------------------------------------------===//
162
163Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000164
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000165namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000166 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000167 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000168 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000169}
170
Chris Lattner35f27052006-05-01 21:16:03 +0000171bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000172 DOUT << "********** REWRITE MACHINE CODE **********\n";
173 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000174 const TargetMachine &TM = MF.getTarget();
175 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000176
Chris Lattner4ea1b822004-09-30 02:33:48 +0000177 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
178 // each vreg once (in the case where a spilled vreg is used by multiple
179 // operands). This is always smaller than the number of operands to the
180 // current machine instr, so it should be small.
181 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000182
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000183 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
184 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000185 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000186 MachineBasicBlock &MBB = *MBBI;
187 for (MachineBasicBlock::iterator MII = MBB.begin(),
188 E = MBB.end(); MII != E; ++MII) {
189 MachineInstr &MI = *MII;
190 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000191 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000192 if (MO.isRegister() && MO.getReg())
193 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
194 unsigned VirtReg = MO.getReg();
195 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000196 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000197 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000198 const TargetRegisterClass* RC =
199 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000200
Chris Lattner886dd912005-04-04 21:35:34 +0000201 if (MO.isUse() &&
202 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
203 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000205 LoadedRegs.push_back(VirtReg);
206 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000207 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000208 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000209
Chris Lattner886dd912005-04-04 21:35:34 +0000210 if (MO.isDef()) {
Evan Chengd64b5c82007-12-05 03:14:33 +0000211 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
212 StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000213 ++NumStores;
214 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000215 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000216 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000217 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000218 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000219 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000220 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 }
Chris Lattner886dd912005-04-04 21:35:34 +0000222
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000223 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000224 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000225 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000226 }
227 return true;
228}
229
230//===----------------------------------------------------------------------===//
231// Local Spiller Implementation
232//===----------------------------------------------------------------------===//
233
234namespace {
Evan Cheng66f71632007-10-19 21:23:22 +0000235 class AvailableSpills;
236
Chris Lattner7fb64342004-10-01 19:04:51 +0000237 /// LocalSpiller - This spiller does a simple pass over the machine basic
238 /// block to attempt to keep spills in registers as much as possible for
239 /// blocks that have low register pressure (the vreg may be spilled due to
240 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000241 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000242 SSARegMap *RegMap;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000243 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000244 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000245 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000246 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Evan Cheng32dfbea2007-10-12 08:50:34 +0000247 RegMap = MF.getSSARegMap();
Chris Lattner7fb64342004-10-01 19:04:51 +0000248 MRI = MF.getTarget().getRegisterInfo();
249 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000250 DOUT << "\n**** Local spiller rewriting function '"
251 << MF.getFunction()->getName() << "':\n";
David Greene04fa32f2007-09-06 16:36:39 +0000252 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n";
253 DEBUG(MF.dump());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000254
Chris Lattner7fb64342004-10-01 19:04:51 +0000255 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
256 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000257 RewriteMBB(*MBB, VRM);
David Greene04fa32f2007-09-06 16:36:39 +0000258
259 DOUT << "**** Post Machine Instrs ****\n";
260 DEBUG(MF.dump());
261
Chris Lattner7fb64342004-10-01 19:04:51 +0000262 return true;
263 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000264 private:
Evan Cheng66f71632007-10-19 21:23:22 +0000265 bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator &MII,
267 std::vector<MachineInstr*> &MaybeDeadStores,
268 AvailableSpills &Spills, BitVector &RegKills,
269 std::vector<MachineOperand*> &KillOps,
270 VirtRegMap &VRM);
Evan Cheng81a03822007-11-17 00:40:40 +0000271 void SpillRegToStackSlot(MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator &MII,
273 int Idx, unsigned PhysReg, int StackSlot,
274 const TargetRegisterClass *RC,
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000275 bool isAvailable, MachineInstr *&LastStore,
Evan Cheng81a03822007-11-17 00:40:40 +0000276 AvailableSpills &Spills,
277 SmallSet<MachineInstr*, 4> &ReMatDefs,
278 BitVector &RegKills,
279 std::vector<MachineOperand*> &KillOps,
Evan Chenge4b39002007-12-03 21:31:55 +0000280 VirtRegMap &VRM);
Evan Cheng549f27d32007-08-13 23:45:17 +0000281 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000282 };
283}
284
Chris Lattner66cf80f2006-02-03 23:13:58 +0000285/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000286/// top down, keep track of which spills slots or remat are available in each
287/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000288///
289/// Note that not all physregs are created equal here. In particular, some
290/// physregs are reloads that we are allowed to clobber or ignore at any time.
291/// Other physregs are values that the register allocated program is using that
292/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000293/// per-stack-slot / remat id basis as the low bit in the value of the
294/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
295/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000296namespace {
297class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298 const MRegisterInfo *MRI;
299 const TargetInstrInfo *TII;
300
Evan Cheng549f27d32007-08-13 23:45:17 +0000301 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
302 // or remat'ed virtual register values that are still available, due to being
303 // loaded or stored to, but not invalidated yet.
304 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000305
Evan Cheng549f27d32007-08-13 23:45:17 +0000306 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
307 // indicating which stack slot values are currently held by a physreg. This
308 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
309 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000310 std::multimap<unsigned, int> PhysRegsAvailable;
311
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000312 void disallowClobberPhysRegOnly(unsigned PhysReg);
313
Chris Lattner66cf80f2006-02-03 23:13:58 +0000314 void ClobberPhysRegOnly(unsigned PhysReg);
315public:
316 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
317 : MRI(mri), TII(tii) {
318 }
319
Evan Cheng91e23902007-02-23 01:13:26 +0000320 const MRegisterInfo *getRegInfo() const { return MRI; }
321
Evan Cheng549f27d32007-08-13 23:45:17 +0000322 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
323 /// available in a physical register, return that PhysReg, otherwise
324 /// return 0.
325 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
326 std::map<int, unsigned>::const_iterator I =
327 SpillSlotsOrReMatsAvailable.find(Slot);
328 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000329 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000330 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000331 return 0;
332 }
Evan Chengde4e9422007-02-25 09:51:27 +0000333
Evan Cheng549f27d32007-08-13 23:45:17 +0000334 /// addAvailable - Mark that the specified stack slot / remat is available in
335 /// the specified physreg. If CanClobber is true, the physreg can be modified
336 /// at any time without changing the semantics of the program.
337 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000338 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000339 // If this stack slot is thought to be available in some other physreg,
340 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000341 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000342
Evan Cheng549f27d32007-08-13 23:45:17 +0000343 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
Evan Cheng90a43c32007-08-15 20:20:34 +0000344 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000345
Evan Cheng549f27d32007-08-13 23:45:17 +0000346 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
347 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000348 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000349 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000350 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000351 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000352
Chris Lattner593c9582006-02-03 23:28:46 +0000353 /// canClobberPhysReg - Return true if the spiller is allowed to change the
354 /// value of the specified stackslot register if it desires. The specified
355 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000356 bool canClobberPhysReg(int SlotOrReMat) const {
Evan Cheng90a43c32007-08-15 20:20:34 +0000357 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
358 "Value not available!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000359 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000360 }
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000361
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000362 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
363 /// stackslot register. The register is still available but is no longer
364 /// allowed to be modifed.
365 void disallowClobberPhysReg(unsigned PhysReg);
366
Chris Lattner66cf80f2006-02-03 23:13:58 +0000367 /// ClobberPhysReg - This is called when the specified physreg changes
Evan Cheng66f71632007-10-19 21:23:22 +0000368 /// value. We use this to invalidate any info about stuff that lives in
Chris Lattner66cf80f2006-02-03 23:13:58 +0000369 /// it and any of its aliases.
370 void ClobberPhysReg(unsigned PhysReg);
371
Evan Cheng90a43c32007-08-15 20:20:34 +0000372 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
373 /// slot changes. This removes information about which register the previous
374 /// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000375 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000376};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000377}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000378
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000379/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
380/// stackslot register. The register is still available but is no longer
381/// allowed to be modifed.
382void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
383 std::multimap<unsigned, int>::iterator I =
384 PhysRegsAvailable.lower_bound(PhysReg);
385 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000386 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000387 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000388 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000389 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000390 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000391 DOUT << "PhysReg " << MRI->getName(PhysReg)
392 << " copied, it is available for use but can no longer be modified\n";
393 }
394}
395
396/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
397/// stackslot register and its aliases. The register and its aliases may
398/// still available but is no longer allowed to be modifed.
399void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
400 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
401 disallowClobberPhysRegOnly(*AS);
402 disallowClobberPhysRegOnly(PhysReg);
403}
404
Chris Lattner66cf80f2006-02-03 23:13:58 +0000405/// ClobberPhysRegOnly - This is called when the specified physreg changes
406/// value. We use this to invalidate any info about stuff we thing lives in it.
407void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
408 std::multimap<unsigned, int>::iterator I =
409 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000410 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000411 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000412 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000413 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000414 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000415 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000416 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000417 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000418 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
419 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000420 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000421 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000422 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000423}
424
Chris Lattner66cf80f2006-02-03 23:13:58 +0000425/// ClobberPhysReg - This is called when the specified physreg changes
426/// value. We use this to invalidate any info about stuff we thing lives in
427/// it and any of its aliases.
428void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000429 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000430 ClobberPhysRegOnly(*AS);
431 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000432}
433
Evan Cheng90a43c32007-08-15 20:20:34 +0000434/// ModifyStackSlotOrReMat - This method is called when the value in a stack
435/// slot changes. This removes information about which register the previous
436/// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000437void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
Evan Cheng90a43c32007-08-15 20:20:34 +0000438 std::map<int, unsigned>::iterator It =
439 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
Evan Cheng549f27d32007-08-13 23:45:17 +0000440 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000441 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000442 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000443
444 // This register may hold the value of multiple stack slots, only remove this
445 // stack slot from the set of values the register contains.
446 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
447 for (; ; ++I) {
448 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
449 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000450 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000451 }
452 PhysRegsAvailable.erase(I);
453}
454
455
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000456
Evan Cheng28bb4622007-07-11 19:17:18 +0000457/// InvalidateKills - MI is going to be deleted. If any of its operands are
458/// marked kill, then invalidate the information.
459static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000460 std::vector<MachineOperand*> &KillOps,
Evan Cheng66f71632007-10-19 21:23:22 +0000461 SmallVector<unsigned, 2> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000462 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
463 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000464 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
Evan Cheng28bb4622007-07-11 19:17:18 +0000465 continue;
466 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000467 if (KillRegs)
468 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000469 if (KillOps[Reg] == &MO) {
470 RegKills.reset(Reg);
471 KillOps[Reg] = NULL;
472 }
473 }
474}
475
Evan Chengb6ca4b32007-08-14 23:25:37 +0000476/// InvalidateRegDef - If the def operand of the specified def MI is now dead
477/// (since it's spill instruction is removed), mark it isDead. Also checks if
478/// the def MI has other definition operands that are not dead. Returns it by
479/// reference.
480static bool InvalidateRegDef(MachineBasicBlock::iterator I,
481 MachineInstr &NewDef, unsigned Reg,
482 bool &HasLiveDef) {
483 // Due to remat, it's possible this reg isn't being reused. That is,
484 // the def of this reg (by prev MI) is now dead.
485 MachineInstr *DefMI = I;
486 MachineOperand *DefOp = NULL;
487 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
488 MachineOperand &MO = DefMI->getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000489 if (MO.isRegister() && MO.isDef()) {
Evan Chengb6ca4b32007-08-14 23:25:37 +0000490 if (MO.getReg() == Reg)
491 DefOp = &MO;
492 else if (!MO.isDead())
493 HasLiveDef = true;
494 }
495 }
496 if (!DefOp)
497 return false;
498
499 bool FoundUse = false, Done = false;
500 MachineBasicBlock::iterator E = NewDef;
501 ++I; ++E;
502 for (; !Done && I != E; ++I) {
503 MachineInstr *NMI = I;
504 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
505 MachineOperand &MO = NMI->getOperand(j);
Dan Gohman92dfe202007-09-14 20:33:02 +0000506 if (!MO.isRegister() || MO.getReg() != Reg)
Evan Chengb6ca4b32007-08-14 23:25:37 +0000507 continue;
508 if (MO.isUse())
509 FoundUse = true;
510 Done = true; // Stop after scanning all the operands of this MI.
511 }
512 }
513 if (!FoundUse) {
514 // Def is dead!
515 DefOp->setIsDead();
516 return true;
517 }
518 return false;
519}
520
Evan Cheng28bb4622007-07-11 19:17:18 +0000521/// UpdateKills - Track and update kill info. If a MI reads a register that is
522/// marked kill, then it must be due to register reuse. Transfer the kill info
523/// over.
524static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
525 std::vector<MachineOperand*> &KillOps) {
526 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
527 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
528 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000529 if (!MO.isRegister() || !MO.isUse())
Evan Cheng28bb4622007-07-11 19:17:18 +0000530 continue;
531 unsigned Reg = MO.getReg();
532 if (Reg == 0)
533 continue;
534
535 if (RegKills[Reg]) {
536 // That can't be right. Register is killed but not re-defined and it's
537 // being reused. Let's fix that.
538 KillOps[Reg]->unsetIsKill();
539 if (i < TID->numOperands &&
540 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
541 // Unless it's a two-address operand, this is the new kill.
542 MO.setIsKill();
543 }
544
545 if (MO.isKill()) {
546 RegKills.set(Reg);
547 KillOps[Reg] = &MO;
548 }
549 }
550
551 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
552 const MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000553 if (!MO.isRegister() || !MO.isDef())
Evan Cheng28bb4622007-07-11 19:17:18 +0000554 continue;
555 unsigned Reg = MO.getReg();
556 RegKills.reset(Reg);
557 KillOps[Reg] = NULL;
558 }
559}
560
561
Chris Lattner7fb64342004-10-01 19:04:51 +0000562// ReusedOp - For each reused operand, we keep track of a bit of information, in
563// case we need to rollback upon processing a new operand. See comments below.
564namespace {
565 struct ReusedOp {
566 // The MachineInstr operand that reused an available value.
567 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000568
Evan Cheng549f27d32007-08-13 23:45:17 +0000569 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
570 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000571
Chris Lattner7fb64342004-10-01 19:04:51 +0000572 // PhysRegReused - The physical register the value was available in.
573 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000574
Chris Lattner7fb64342004-10-01 19:04:51 +0000575 // AssignedPhysReg - The physreg that was assigned for use by the reload.
576 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000577
578 // VirtReg - The virtual register itself.
579 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000580
Chris Lattner8a61a752005-10-06 17:19:06 +0000581 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
582 unsigned vreg)
Evan Cheng90a43c32007-08-15 20:20:34 +0000583 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
584 AssignedPhysReg(apr), VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000585 };
Chris Lattner540fec62006-02-25 01:51:33 +0000586
587 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
588 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000589 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000590 MachineInstr &MI;
591 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000592 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000593 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000594 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000595 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000596 }
Chris Lattner540fec62006-02-25 01:51:33 +0000597
598 bool hasReuses() const {
599 return !Reuses.empty();
600 }
601
602 /// addReuse - If we choose to reuse a virtual register that is already
603 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000604 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000605 unsigned PhysRegReused, unsigned AssignedPhysReg,
606 unsigned VirtReg) {
607 // If the reload is to the assigned register anyway, no undo will be
608 // required.
609 if (PhysRegReused == AssignedPhysReg) return;
610
611 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000612 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000613 AssignedPhysReg, VirtReg));
614 }
Evan Chenge077ef62006-11-04 00:21:55 +0000615
616 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000617 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000618 }
619
620 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000621 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000622 }
Chris Lattner540fec62006-02-25 01:51:33 +0000623
624 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
625 /// is some other operand that is using the specified register, either pick
626 /// a new register to use, or evict the previous reload and use this reg.
627 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
628 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000629 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000630 SmallSet<unsigned, 8> &Rejected,
631 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000632 std::vector<MachineOperand*> &KillOps,
633 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000634 if (Reuses.empty()) return PhysReg; // This is most often empty.
635
636 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
637 ReusedOp &Op = Reuses[ro];
638 // If we find some other reuse that was supposed to use this register
639 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000640 // register. That is, unless its reload register has already been
641 // considered and subsequently rejected because it has also been reused
642 // by another operand.
643 if (Op.PhysRegReused == PhysReg &&
644 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000645 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000646 unsigned NewReg = Op.AssignedPhysReg;
647 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000648 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000649 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000650 } else {
651 // Otherwise, we might also have a problem if a previously reused
652 // value aliases the new register. If so, codegen the previous reload
653 // and use this one.
654 unsigned PRRU = Op.PhysRegReused;
655 const MRegisterInfo *MRI = Spills.getRegInfo();
656 if (MRI->areAliases(PRRU, PhysReg)) {
657 // Okay, we found out that an alias of a reused register
658 // was used. This isn't good because it means we have
659 // to undo a previous reuse.
660 MachineBasicBlock *MBB = MI->getParent();
661 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000662 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
663
664 // Copy Op out of the vector and remove it, we're going to insert an
665 // explicit load for it.
666 ReusedOp NewOp = Op;
667 Reuses.erase(Reuses.begin()+ro);
668
669 // Ok, we're going to try to reload the assigned physreg into the
670 // slot that we were supposed to in the first place. However, that
671 // register could hold a reuse. Check to see if it conflicts or
672 // would prefer us to use a different register.
673 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000674 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000675 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000676
Evan Cheng549f27d32007-08-13 23:45:17 +0000677 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
678 MRI->reMaterialize(*MBB, MI, NewPhysReg,
679 VRM.getReMaterializedMI(NewOp.VirtReg));
680 ++NumReMats;
681 } else {
682 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
683 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000684 // Any stores to this stack slot are not dead anymore.
685 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000686 ++NumLoads;
687 }
Chris Lattner28bad082006-02-25 02:17:31 +0000688 Spills.ClobberPhysReg(NewPhysReg);
689 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000690
Chris Lattnere53f4a02006-05-04 17:52:23 +0000691 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000692
Evan Cheng549f27d32007-08-13 23:45:17 +0000693 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000694 MachineBasicBlock::iterator MII = MI;
695 --MII;
696 UpdateKills(*MII, RegKills, KillOps);
697 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000698
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000699 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000700 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000701
702 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000703 return PhysReg;
704 }
705 }
706 }
707 return PhysReg;
708 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000709
710 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
711 /// 'Rejected' set to remember which registers have been considered and
712 /// rejected for the reload. This avoids infinite looping in case like
713 /// this:
714 /// t1 := op t2, t3
715 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
716 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
717 /// t1 <- desires r1
718 /// sees r1 is taken by t2, tries t2's reload register r0
719 /// sees r0 is taken by t3, tries t3's reload register r1
720 /// sees r1 is taken by t2, tries t2's reload register r0 ...
721 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
722 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000723 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000724 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000725 std::vector<MachineOperand*> &KillOps,
726 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000727 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000728 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000729 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000730 }
Chris Lattner540fec62006-02-25 01:51:33 +0000731 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000732}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000733
Evan Cheng66f71632007-10-19 21:23:22 +0000734/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
735/// instruction. e.g.
736/// xorl %edi, %eax
737/// movl %eax, -32(%ebp)
738/// movl -36(%ebp), %eax
739/// orl %eax, -32(%ebp)
740/// ==>
741/// xorl %edi, %eax
742/// orl -36(%ebp), %eax
743/// mov %eax, -32(%ebp)
744/// This enables unfolding optimization for a subsequent instruction which will
745/// also eliminate the newly introduced store instruction.
746bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
747 MachineBasicBlock::iterator &MII,
748 std::vector<MachineInstr*> &MaybeDeadStores,
749 AvailableSpills &Spills,
750 BitVector &RegKills,
751 std::vector<MachineOperand*> &KillOps,
752 VirtRegMap &VRM) {
753 MachineFunction &MF = *MBB.getParent();
754 MachineInstr &MI = *MII;
755 unsigned UnfoldedOpc = 0;
756 unsigned UnfoldPR = 0;
757 unsigned UnfoldVR = 0;
758 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
759 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
760 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
761 // Only transform a MI that folds a single register.
762 if (UnfoldedOpc)
763 return false;
764 UnfoldVR = I->second.first;
765 VirtRegMap::ModRef MR = I->second.second;
766 if (VRM.isAssignedReg(UnfoldVR))
767 continue;
768 // If this reference is not a use, any previous store is now dead.
769 // Otherwise, the store to this stack slot is not dead anymore.
770 FoldedSS = VRM.getStackSlot(UnfoldVR);
771 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
772 if (DeadStore && (MR & VirtRegMap::isModRef)) {
773 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
774 if (!PhysReg ||
775 DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
776 continue;
777 UnfoldPR = PhysReg;
778 UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
779 false, true);
780 }
781 }
782
783 if (!UnfoldedOpc)
784 return false;
785
786 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
787 MachineOperand &MO = MI.getOperand(i);
788 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
789 continue;
790 unsigned VirtReg = MO.getReg();
Evan Chengc498b022007-11-14 07:59:08 +0000791 if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
Evan Cheng66f71632007-10-19 21:23:22 +0000792 continue;
793 if (VRM.isAssignedReg(VirtReg)) {
794 unsigned PhysReg = VRM.getPhys(VirtReg);
795 if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR))
796 return false;
797 } else if (VRM.isReMaterialized(VirtReg))
798 continue;
799 int SS = VRM.getStackSlot(VirtReg);
800 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
801 if (PhysReg) {
802 if (MRI->regsOverlap(PhysReg, UnfoldPR))
803 return false;
804 continue;
805 }
806 PhysReg = VRM.getPhys(VirtReg);
807 if (!MRI->regsOverlap(PhysReg, UnfoldPR))
808 continue;
809
810 // Ok, we'll need to reload the value into a register which makes
811 // it impossible to perform the store unfolding optimization later.
812 // Let's see if it is possible to fold the load if the store is
813 // unfolded. This allows us to perform the store unfolding
814 // optimization.
815 SmallVector<MachineInstr*, 4> NewMIs;
816 if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
817 assert(NewMIs.size() == 1);
818 MachineInstr *NewMI = NewMIs.back();
819 NewMIs.clear();
Evan Cheng81a03822007-11-17 00:40:40 +0000820 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg);
821 assert(Idx != -1);
Evan Chengaee4af62007-12-02 08:30:39 +0000822 SmallVector<unsigned, 2> Ops;
823 Ops.push_back(Idx);
824 MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS);
Evan Cheng66f71632007-10-19 21:23:22 +0000825 if (FoldedMI) {
Evan Chengcbfb9b22007-10-22 03:01:44 +0000826 if (!VRM.hasPhys(UnfoldVR))
Evan Cheng66f71632007-10-19 21:23:22 +0000827 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
Evan Cheng66f71632007-10-19 21:23:22 +0000828 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
829 MII = MBB.insert(MII, FoldedMI);
Evan Chengcada2452007-11-28 01:28:46 +0000830 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +0000831 MBB.erase(&MI);
832 return true;
833 }
834 delete NewMI;
835 }
836 }
837 return false;
838}
Chris Lattner7fb64342004-10-01 19:04:51 +0000839
Evan Cheng7277a7d2007-11-02 17:35:08 +0000840/// findSuperReg - Find the SubReg's super-register of given register class
841/// where its SubIdx sub-register is SubReg.
842static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
843 unsigned SubIdx, const MRegisterInfo *MRI) {
844 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
845 I != E; ++I) {
846 unsigned Reg = *I;
847 if (MRI->getSubReg(Reg, SubIdx) == SubReg)
848 return Reg;
849 }
850 return 0;
851}
852
Evan Cheng81a03822007-11-17 00:40:40 +0000853/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
854/// the last store to the same slot is now dead. If so, remove the last store.
855void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
856 MachineBasicBlock::iterator &MII,
857 int Idx, unsigned PhysReg, int StackSlot,
858 const TargetRegisterClass *RC,
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000859 bool isAvailable, MachineInstr *&LastStore,
Evan Cheng81a03822007-11-17 00:40:40 +0000860 AvailableSpills &Spills,
861 SmallSet<MachineInstr*, 4> &ReMatDefs,
862 BitVector &RegKills,
863 std::vector<MachineOperand*> &KillOps,
Evan Chenge4b39002007-12-03 21:31:55 +0000864 VirtRegMap &VRM) {
Evan Chengd64b5c82007-12-05 03:14:33 +0000865 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
Evan Cheng81a03822007-11-17 00:40:40 +0000866 DOUT << "Store:\t" << *next(MII);
867
868 // If there is a dead store to this stack slot, nuke it now.
869 if (LastStore) {
870 DOUT << "Removed dead store:\t" << *LastStore;
871 ++NumDSE;
872 SmallVector<unsigned, 2> KillRegs;
873 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
874 MachineBasicBlock::iterator PrevMII = LastStore;
875 bool CheckDef = PrevMII != MBB.begin();
876 if (CheckDef)
877 --PrevMII;
878 MBB.erase(LastStore);
Evan Chengcada2452007-11-28 01:28:46 +0000879 VRM.RemoveMachineInstrFromMaps(LastStore);
Evan Cheng81a03822007-11-17 00:40:40 +0000880 if (CheckDef) {
881 // Look at defs of killed registers on the store. Mark the defs
882 // as dead since the store has been deleted and they aren't
883 // being reused.
884 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
885 bool HasOtherDef = false;
886 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
887 MachineInstr *DeadDef = PrevMII;
888 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
889 // FIXME: This assumes a remat def does not have side
890 // effects.
891 MBB.erase(DeadDef);
Evan Chengcada2452007-11-28 01:28:46 +0000892 VRM.RemoveMachineInstrFromMaps(DeadDef);
Evan Cheng81a03822007-11-17 00:40:40 +0000893 ++NumDRM;
894 }
895 }
896 }
897 }
898 }
899
Evan Chenge4b39002007-12-03 21:31:55 +0000900 LastStore = next(MII);
Evan Cheng81a03822007-11-17 00:40:40 +0000901
902 // If the stack slot value was previously available in some other
903 // register, change it now. Otherwise, make the register available,
904 // in PhysReg.
905 Spills.ModifyStackSlotOrReMat(StackSlot);
906 Spills.ClobberPhysReg(PhysReg);
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000907 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
Evan Cheng81a03822007-11-17 00:40:40 +0000908 ++NumStores;
909}
910
Chris Lattner7fb64342004-10-01 19:04:51 +0000911/// rewriteMBB - Keep track of which spills are available even after the
Evan Cheng81a03822007-11-17 00:40:40 +0000912/// register allocator is done with them. If possible, avid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000913void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000914 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000915
Evan Chengfff3e192007-08-14 09:11:18 +0000916 MachineFunction &MF = *MBB.getParent();
917
Chris Lattner66cf80f2006-02-03 23:13:58 +0000918 // Spills - Keep track of which spilled values are available in physregs so
919 // that we can choose to reuse the physregs instead of emitting reloads.
920 AvailableSpills Spills(MRI, TII);
921
Chris Lattner52b25db2004-10-01 19:47:12 +0000922 // MaybeDeadStores - When we need to write a value back into a stack slot,
923 // keep track of the inserted store. If the stack slot value is never read
924 // (because the value was used from some available register, for example), and
925 // subsequently stored to, the original store is dead. This map keeps track
926 // of inserted stores that are not used. If we see a subsequent store to the
927 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000928 std::vector<MachineInstr*> MaybeDeadStores;
929 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000930
Evan Chengb6ca4b32007-08-14 23:25:37 +0000931 // ReMatDefs - These are rematerializable def MIs which are not deleted.
932 SmallSet<MachineInstr*, 4> ReMatDefs;
933
Evan Cheng0c40d722007-07-11 05:28:39 +0000934 // Keep track of kill information.
935 BitVector RegKills(MRI->getNumRegs());
936 std::vector<MachineOperand*> KillOps;
937 KillOps.resize(MRI->getNumRegs(), NULL);
938
Chris Lattner7fb64342004-10-01 19:04:51 +0000939 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
940 MII != E; ) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000941 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000942
Evan Cheng66f71632007-10-19 21:23:22 +0000943 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
Evan Cheng0c40d722007-07-11 05:28:39 +0000944 bool Erased = false;
945 bool BackTracked = false;
Evan Cheng66f71632007-10-19 21:23:22 +0000946 if (PrepForUnfoldOpti(MBB, MII,
947 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
948 NextMII = next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +0000949
Evan Cheng66f71632007-10-19 21:23:22 +0000950 MachineInstr &MI = *MII;
Evan Cheng86facc22006-12-15 06:41:01 +0000951 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Chenge077ef62006-11-04 00:21:55 +0000952
Evan Cheng0cbb1162007-11-29 01:06:25 +0000953 // Insert restores here if asked to.
954 if (VRM.isRestorePt(&MI)) {
955 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
956 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
957 unsigned VirtReg = RestoreRegs[i];
958 if (!VRM.getPreSplitReg(VirtReg))
959 continue; // Split interval spilled again.
960 unsigned Phys = VRM.getPhys(VirtReg);
961 MF.setPhysRegUsed(Phys);
962 if (VRM.isReMaterialized(VirtReg)) {
963 MRI->reMaterialize(MBB, &MI, Phys,
964 VRM.getReMaterializedMI(VirtReg));
965 ++NumReMats;
966 } else {
967 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
968 MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC);
969 ++NumLoads;
970 }
971 // This invalidates Phys.
972 Spills.ClobberPhysReg(Phys);
973 UpdateKills(*prior(MII), RegKills, KillOps);
974 DOUT << '\t' << *prior(MII);
975 }
976 }
977
Evan Cheng81a03822007-11-17 00:40:40 +0000978 // Insert spills here if asked to.
Evan Chengcada2452007-11-28 01:28:46 +0000979 if (VRM.isSpillPt(&MI)) {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000980 std::vector<std::pair<unsigned,bool> > &SpillRegs =
981 VRM.getSpillPtSpills(&MI);
Evan Chengcada2452007-11-28 01:28:46 +0000982 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000983 unsigned VirtReg = SpillRegs[i].first;
984 bool isKill = SpillRegs[i].second;
Evan Chengcada2452007-11-28 01:28:46 +0000985 if (!VRM.getPreSplitReg(VirtReg))
986 continue; // Split interval spilled again.
987 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
988 unsigned Phys = VRM.getPhys(VirtReg);
989 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Chengb50bb8c2007-12-05 08:16:32 +0000990 MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
Evan Chengd64b5c82007-12-05 03:14:33 +0000991 MachineInstr *StoreMI = next(MII);
992 DOUT << "Store:\t" << StoreMI;
993 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
Evan Chengcada2452007-11-28 01:28:46 +0000994 }
Evan Chenge4b39002007-12-03 21:31:55 +0000995 NextMII = next(MII);
Evan Cheng81a03822007-11-17 00:40:40 +0000996 }
997
998 /// ReusedOperands - Keep track of operand reuse in case we need to undo
999 /// reuse.
1000 ReuseInfo ReusedOperands(MI, MRI);
Chris Lattner7fb64342004-10-01 19:04:51 +00001001 // Process all of the spilled uses and all non spilled reg references.
1002 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1003 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001004 if (!MO.isRegister() || MO.getReg() == 0)
1005 continue; // Ignore non-register operands.
1006
Evan Cheng32dfbea2007-10-12 08:50:34 +00001007 unsigned VirtReg = MO.getReg();
1008 if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +00001009 // Ignore physregs for spilling, but remember that it is used by this
1010 // function.
Evan Cheng32dfbea2007-10-12 08:50:34 +00001011 MF.setPhysRegUsed(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001012 continue;
1013 }
1014
Evan Cheng32dfbea2007-10-12 08:50:34 +00001015 assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
Chris Lattner50ea01e2005-09-09 20:29:51 +00001016 "Not a virtual or a physical register?");
Evan Cheng70306f82007-12-03 09:58:48 +00001017
Evan Chengc498b022007-11-14 07:59:08 +00001018 unsigned SubIdx = MO.getSubReg();
Evan Cheng549f27d32007-08-13 23:45:17 +00001019 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +00001020 // This virtual register was assigned a physreg!
1021 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001022 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +00001023 if (MO.isDef())
1024 ReusedOperands.markClobbered(Phys);
Evan Chengc498b022007-11-14 07:59:08 +00001025 unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001026 MI.getOperand(i).setReg(RReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001027 continue;
1028 }
1029
1030 // This virtual register is now known to be a spilled value.
1031 if (!MO.isUse())
1032 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +00001033
Evan Cheng549f27d32007-08-13 23:45:17 +00001034 bool DoReMat = VRM.isReMaterialized(VirtReg);
1035 int SSorRMId = DoReMat
1036 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +00001037 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +00001038
Chris Lattner50ea01e2005-09-09 20:29:51 +00001039 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +00001040 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001041
1042 // If this is a sub-register use, make sure the reuse register is in the
1043 // right register class. For example, for x86 not all of the 32-bit
1044 // registers have accessible sub-registers.
1045 // Similarly so for EXTRACT_SUBREG. Consider this:
1046 // EDI = op
1047 // MOV32_mr fi#1, EDI
1048 // ...
1049 // = EXTRACT_SUBREG fi#1
1050 // fi#1 is available in EDI, but it cannot be reused because it's not in
1051 // the right register file.
1052 if (PhysReg &&
Evan Chengc498b022007-11-14 07:59:08 +00001053 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
Evan Cheng32dfbea2007-10-12 08:50:34 +00001054 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
1055 if (!RC->contains(PhysReg))
1056 PhysReg = 0;
1057 }
1058
Evan Chengdc6be192007-08-14 05:42:54 +00001059 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +00001060 // This spilled operand might be part of a two-address operand. If this
1061 // is the case, then changing it will necessarily require changing the
1062 // def part of the instruction as well. However, in some cases, we
1063 // aren't allowed to modify the reused register. If none of these cases
1064 // apply, reuse it.
1065 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +00001066 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001067 if (ti != -1 &&
Dan Gohman92dfe202007-09-14 20:33:02 +00001068 MI.getOperand(ti).isRegister() &&
Evan Cheng360c2dd2006-11-01 23:06:55 +00001069 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +00001070 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +00001071 // long as we are allowed to clobber the value and there isn't an
1072 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +00001073 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +00001074 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +00001075 }
1076
1077 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +00001078 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +00001079 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1080 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001081 else
Evan Chengdc6be192007-08-14 05:42:54 +00001082 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001083 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001084 << MRI->getName(PhysReg) << " for vreg"
1085 << VirtReg <<" instead of reloading into physreg "
1086 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Evan Chengc498b022007-11-14 07:59:08 +00001087 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001088 MI.getOperand(i).setReg(RReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001089
1090 // The only technical detail we have is that we don't know that
1091 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1092 // later in the instruction. In particular, consider 'op V1, V2'.
1093 // If V1 is available in physreg R0, we would choose to reuse it
1094 // here, instead of reloading it into the register the allocator
1095 // indicated (say R1). However, V2 might have to be reloaded
1096 // later, and it might indicate that it needs to live in R0. When
1097 // this occurs, we need to have information available that
1098 // indicates it is safe to use R1 for the reload instead of R0.
1099 //
1100 // To further complicate matters, we might conflict with an alias,
1101 // or R0 and R1 might not be compatible with each other. In this
1102 // case, we actually insert a reload for V1 in R1, ensuring that
1103 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +00001104 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +00001105 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001106 if (ti != -1)
1107 // Only mark it clobbered if this is a use&def operand.
1108 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001109 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +00001110
1111 if (MI.getOperand(i).isKill() &&
1112 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1113 // This was the last use and the spilled value is still available
1114 // for reuse. That means the spill was unnecessary!
1115 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
1116 if (DeadStore) {
1117 DOUT << "Removed dead store:\t" << *DeadStore;
1118 InvalidateKills(*DeadStore, RegKills, KillOps);
Evan Chengcada2452007-11-28 01:28:46 +00001119 VRM.RemoveMachineInstrFromMaps(DeadStore);
Evan Cheng66f71632007-10-19 21:23:22 +00001120 MBB.erase(DeadStore);
Evan Chengfff3e192007-08-14 09:11:18 +00001121 MaybeDeadStores[ReuseSlot] = NULL;
1122 ++NumDSE;
1123 }
1124 }
Chris Lattneraddc55a2006-04-28 01:46:50 +00001125 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001126 } // CanReuse
Chris Lattneraddc55a2006-04-28 01:46:50 +00001127
1128 // Otherwise we have a situation where we have a two-address instruction
1129 // whose mod/ref operand needs to be reloaded. This reload is already
1130 // available in some register "PhysReg", but if we used PhysReg as the
1131 // operand to our 2-addr instruction, the instruction would modify
1132 // PhysReg. This isn't cool if something later uses PhysReg and expects
1133 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +00001134 //
Chris Lattneraddc55a2006-04-28 01:46:50 +00001135 // To avoid this problem, and to avoid doing a load right after a store,
1136 // we emit a copy from PhysReg into the designated register for this
1137 // operand.
1138 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1139 assert(DesignatedReg && "Must map virtreg to physreg!");
1140
1141 // Note that, if we reused a register for a previous operand, the
1142 // register we want to reload into might not actually be
1143 // available. If this occurs, use the register indicated by the
1144 // reuser.
1145 if (ReusedOperands.hasReuses())
1146 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001147 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001148
Chris Lattnerba1fc3d2006-04-28 04:43:18 +00001149 // If the mapped designated register is actually the physreg we have
1150 // incoming, we don't need to inserted a dead copy.
1151 if (DesignatedReg == PhysReg) {
1152 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +00001153 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1154 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001155 else
Evan Chengdc6be192007-08-14 05:42:54 +00001156 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001157 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001158 << VirtReg
1159 << " instead of reloading into same physreg.\n";
Evan Chengc498b022007-11-14 07:59:08 +00001160 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001161 MI.getOperand(i).setReg(RReg);
Evan Cheng7277a7d2007-11-02 17:35:08 +00001162 ReusedOperands.markClobbered(RReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +00001163 ++NumReused;
1164 continue;
1165 }
1166
Evan Cheng32dfbea2007-10-12 08:50:34 +00001167 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001168 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001169 ReusedOperands.markClobbered(DesignatedReg);
Evan Cheng9efce632007-09-26 06:25:56 +00001170 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
Evan Chengde4e9422007-02-25 09:51:27 +00001171
Evan Cheng6b448092007-03-02 08:52:00 +00001172 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +00001173 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +00001174
Chris Lattneraddc55a2006-04-28 01:46:50 +00001175 // This invalidates DesignatedReg.
1176 Spills.ClobberPhysReg(DesignatedReg);
1177
Evan Chengdc6be192007-08-14 05:42:54 +00001178 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001179 unsigned RReg =
Evan Chengc498b022007-11-14 07:59:08 +00001180 SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001181 MI.getOperand(i).setReg(RReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001182 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001183 ++NumReused;
1184 continue;
Evan Cheng66f71632007-10-19 21:23:22 +00001185 } // if (PhysReg)
Chris Lattner50ea01e2005-09-09 20:29:51 +00001186
1187 // Otherwise, reload it and remember that we have it.
1188 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +00001189 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattner7fb64342004-10-01 19:04:51 +00001190
Chris Lattner50ea01e2005-09-09 20:29:51 +00001191 // Note that, if we reused a register for a previous operand, the
1192 // register we want to reload into might not actually be
1193 // available. If this occurs, use the register indicated by the
1194 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +00001195 if (ReusedOperands.hasReuses())
1196 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001197 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +00001198
Evan Cheng6c087e52007-04-25 22:13:27 +00001199 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001200 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +00001201 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +00001202 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +00001203 ++NumReMats;
1204 } else {
Evan Cheng32dfbea2007-10-12 08:50:34 +00001205 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +00001206 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +00001207 ++NumLoads;
1208 }
Chris Lattner50ea01e2005-09-09 20:29:51 +00001209 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001210 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001211
1212 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +00001213 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +00001214 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +00001215 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +00001216 // Assumes this is the last use. IsKill will be unset if reg is reused
1217 // unless it's a two-address operand.
1218 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
1219 MI.getOperand(i).setIsKill();
Evan Chengc498b022007-11-14 07:59:08 +00001220 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001221 MI.getOperand(i).setReg(RReg);
Evan Cheng0c40d722007-07-11 05:28:39 +00001222 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001223 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001224 }
1225
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001226 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001227
Evan Cheng81a03822007-11-17 00:40:40 +00001228
Chris Lattner7fb64342004-10-01 19:04:51 +00001229 // If we have folded references to memory operands, make sure we clear all
1230 // physical registers that may contain the value of the spilled virtual
1231 // register
Evan Cheng66f71632007-10-19 21:23:22 +00001232 SmallSet<int, 2> FoldedSS;
Chris Lattner8f1d6402005-01-14 15:54:24 +00001233 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +00001234 unsigned VirtReg = I->second.first;
1235 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng66f71632007-10-19 21:23:22 +00001236 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
Evan Cheng81a03822007-11-17 00:40:40 +00001237
Chris Lattnercea86882005-09-19 06:56:21 +00001238 int SS = VRM.getStackSlot(VirtReg);
Evan Cheng81a03822007-11-17 00:40:40 +00001239 if (SS == VirtRegMap::NO_STACK_SLOT)
1240 continue;
Evan Cheng90a43c32007-08-15 20:20:34 +00001241 FoldedSS.insert(SS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001242 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001243
1244 // If this folded instruction is just a use, check to see if it's a
1245 // straight load from the virt reg slot.
1246 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1247 int FrameIdx;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001248 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1249 if (DestReg && FrameIdx == SS) {
1250 // If this spill slot is available, turn it into a copy (or nothing)
1251 // instead of leaving it as a load!
1252 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1253 DOUT << "Promoted Load To Copy: " << MI;
1254 if (DestReg != InReg) {
1255 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1256 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1257 // Revisit the copy so we make sure to notice the effects of the
1258 // operation on the destreg (either needing to RA it if it's
1259 // virtual or needing to clobber any values if it's physical).
1260 NextMII = &MI;
1261 --NextMII; // backtrack to the copy.
1262 BackTracked = true;
1263 } else
1264 DOUT << "Removing now-noop copy: " << MI;
Evan Chengde4e9422007-02-25 09:51:27 +00001265
Evan Chengcada2452007-11-28 01:28:46 +00001266 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001267 MBB.erase(&MI);
1268 Erased = true;
1269 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001270 }
Evan Cheng7f566252007-10-13 02:50:24 +00001271 } else {
1272 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1273 SmallVector<MachineInstr*, 4> NewMIs;
1274 if (PhysReg &&
1275 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
1276 MBB.insert(MII, NewMIs[0]);
Evan Chengcada2452007-11-28 01:28:46 +00001277 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng7f566252007-10-13 02:50:24 +00001278 MBB.erase(&MI);
1279 Erased = true;
1280 --NextMII; // backtrack to the unfolded instruction.
1281 BackTracked = true;
1282 goto ProcessNextInst;
1283 }
Chris Lattnercea86882005-09-19 06:56:21 +00001284 }
1285 }
1286
1287 // If this reference is not a use, any previous store is now dead.
1288 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001289 MachineInstr* DeadStore = MaybeDeadStores[SS];
1290 if (DeadStore) {
Evan Cheng66f71632007-10-19 21:23:22 +00001291 bool isDead = !(MR & VirtRegMap::isRef);
Evan Cheng7f566252007-10-13 02:50:24 +00001292 MachineInstr *NewStore = NULL;
Evan Chengcbfb9b22007-10-22 03:01:44 +00001293 if (MR & VirtRegMap::isModRef) {
Evan Cheng7f566252007-10-13 02:50:24 +00001294 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1295 SmallVector<MachineInstr*, 4> NewMIs;
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001296 // We can reuse this physreg as long as we are allowed to clobber
1297 // the value and there isn't an earlier def that has already clobbered the
1298 // physreg.
Evan Cheng7f566252007-10-13 02:50:24 +00001299 if (PhysReg &&
1300 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
1301 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
1302 MBB.insert(MII, NewMIs[0]);
1303 NewStore = NewMIs[1];
1304 MBB.insert(MII, NewStore);
Evan Chengcada2452007-11-28 01:28:46 +00001305 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng7f566252007-10-13 02:50:24 +00001306 MBB.erase(&MI);
1307 Erased = true;
1308 --NextMII;
1309 --NextMII; // backtrack to the unfolded instruction.
1310 BackTracked = true;
Evan Cheng66f71632007-10-19 21:23:22 +00001311 isDead = true;
1312 }
Evan Cheng7f566252007-10-13 02:50:24 +00001313 }
1314
1315 if (isDead) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001316 // If we get here, the store is dead, nuke it now.
Evan Chengfff3e192007-08-14 09:11:18 +00001317 DOUT << "Removed dead store:\t" << *DeadStore;
1318 InvalidateKills(*DeadStore, RegKills, KillOps);
Evan Chengcada2452007-11-28 01:28:46 +00001319 VRM.RemoveMachineInstrFromMaps(DeadStore);
Evan Cheng7f566252007-10-13 02:50:24 +00001320 MBB.erase(DeadStore);
1321 if (!NewStore)
1322 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001323 }
Evan Cheng7f566252007-10-13 02:50:24 +00001324
Evan Chengfff3e192007-08-14 09:11:18 +00001325 MaybeDeadStores[SS] = NULL;
Evan Cheng7f566252007-10-13 02:50:24 +00001326 if (NewStore) {
1327 // Treat this store as a spill merged into a copy. That makes the
1328 // stack slot value available.
1329 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1330 goto ProcessNextInst;
1331 }
Chris Lattnercea86882005-09-19 06:56:21 +00001332 }
1333
1334 // If the spill slot value is available, and this is a new definition of
1335 // the value, the value is not available anymore.
1336 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001337 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001338 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001339
1340 // If this is *just* a mod of the value, check to see if this is just a
1341 // store to the spill slot (i.e. the spill got merged into the copy). If
1342 // so, realize that the vreg is available now, and add the store to the
1343 // MaybeDeadStore info.
1344 int StackSlot;
1345 if (!(MR & VirtRegMap::isRef)) {
1346 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1347 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1348 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001349 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001350 // this as a potentially dead store in case there is a subsequent
1351 // store into the stack slot without a read from it.
1352 MaybeDeadStores[StackSlot] = &MI;
1353
Chris Lattnercd816392006-02-02 23:29:36 +00001354 // If the stack slot value was previously available in some other
1355 // register, change it now. Otherwise, make the register available,
1356 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001357 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001358 }
1359 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001360 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001361 }
1362
Chris Lattner7fb64342004-10-01 19:04:51 +00001363 // Process all of the spilled defs.
1364 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1365 MachineOperand &MO = MI.getOperand(i);
Evan Cheng66f71632007-10-19 21:23:22 +00001366 if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
1367 continue;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001368
Evan Cheng66f71632007-10-19 21:23:22 +00001369 unsigned VirtReg = MO.getReg();
1370 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
1371 // Check to see if this is a noop copy. If so, eliminate the
1372 // instruction before considering the dest reg to be changed.
1373 unsigned Src, Dst;
1374 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1375 ++NumDCE;
1376 DOUT << "Removing now-noop copy: " << MI;
1377 MBB.erase(&MI);
1378 Erased = true;
Evan Chengcada2452007-11-28 01:28:46 +00001379 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +00001380 Spills.disallowClobberPhysReg(VirtReg);
1381 goto ProcessNextInst;
1382 }
1383
1384 // If it's not a no-op copy, it clobbers the value in the destreg.
1385 Spills.ClobberPhysReg(VirtReg);
1386 ReusedOperands.markClobbered(VirtReg);
1387
1388 // Check to see if this instruction is a load from a stack slot into
1389 // a register. If so, this provides the stack slot value in the reg.
1390 int FrameIdx;
1391 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1392 assert(DestReg == VirtReg && "Unknown load situation!");
1393
1394 // If it is a folded reference, then it's not safe to clobber.
1395 bool Folded = FoldedSS.count(FrameIdx);
1396 // Otherwise, if it wasn't available, remember that it is now!
1397 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
1398 goto ProcessNextInst;
1399 }
1400
1401 continue;
1402 }
1403
Evan Chengc498b022007-11-14 07:59:08 +00001404 unsigned SubIdx = MO.getSubReg();
Evan Cheng66f71632007-10-19 21:23:22 +00001405 bool DoReMat = VRM.isReMaterialized(VirtReg);
1406 if (DoReMat)
1407 ReMatDefs.insert(&MI);
1408
1409 // The only vregs left are stack slot definitions.
1410 int StackSlot = VRM.getStackSlot(VirtReg);
1411 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1412
1413 // If this def is part of a two-address operand, make sure to execute
1414 // the store from the correct physical register.
1415 unsigned PhysReg;
1416 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng7277a7d2007-11-02 17:35:08 +00001417 if (TiedOp != -1) {
Evan Cheng66f71632007-10-19 21:23:22 +00001418 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chengc498b022007-11-14 07:59:08 +00001419 if (SubIdx) {
Evan Cheng7277a7d2007-11-02 17:35:08 +00001420 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI);
1421 assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
1422 "Can't find corresponding super-register!");
1423 PhysReg = SuperReg;
1424 }
1425 } else {
Evan Cheng66f71632007-10-19 21:23:22 +00001426 PhysReg = VRM.getPhys(VirtReg);
1427 if (ReusedOperands.isClobbered(PhysReg)) {
1428 // Another def has taken the assigned physreg. It must have been a
1429 // use&def which got it due to reuse. Undo the reuse!
1430 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1431 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1432 }
1433 }
1434
1435 MF.setPhysRegUsed(PhysReg);
Evan Chengc498b022007-11-14 07:59:08 +00001436 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng7277a7d2007-11-02 17:35:08 +00001437 ReusedOperands.markClobbered(RReg);
1438 MI.getOperand(i).setReg(RReg);
1439
Evan Cheng66f71632007-10-19 21:23:22 +00001440 if (!MO.isDead()) {
Evan Cheng66f71632007-10-19 21:23:22 +00001441 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001442 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
1443 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
Evan Chenge4b39002007-12-03 21:31:55 +00001444 NextMII = next(MII);
Evan Cheng66f71632007-10-19 21:23:22 +00001445
1446 // Check to see if this is a noop copy. If so, eliminate the
1447 // instruction before considering the dest reg to be changed.
1448 {
Chris Lattner29268692006-09-05 02:12:02 +00001449 unsigned Src, Dst;
1450 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1451 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001452 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001453 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001454 Erased = true;
Evan Chengcada2452007-11-28 01:28:46 +00001455 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +00001456 UpdateKills(*LastStore, RegKills, KillOps);
Chris Lattner29268692006-09-05 02:12:02 +00001457 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001458 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00001459 }
Evan Cheng66f71632007-10-19 21:23:22 +00001460 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001461 }
Chris Lattnercea86882005-09-19 06:56:21 +00001462 ProcessNextInst:
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001463 if (!Erased && !BackTracked) {
Evan Cheng0c40d722007-07-11 05:28:39 +00001464 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1465 UpdateKills(*II, RegKills, KillOps);
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001466 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001467 MII = NextMII;
1468 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001469}
1470
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001471llvm::Spiller* llvm::createSpiller() {
1472 switch (SpillerOpt) {
1473 default: assert(0 && "Unreachable!");
1474 case local:
1475 return new LocalSpiller();
1476 case simple:
1477 return new SimpleSpiller();
1478 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001479}