Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 43 | #define MDSS_MDP_MAX_PREFILL_FETCH 25 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 44 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 45 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 46 | |
| 47 | static int mdp_rev; |
| 48 | |
| 49 | void mdp_set_revision(int rev) |
| 50 | { |
| 51 | mdp_rev = rev; |
| 52 | } |
| 53 | |
| 54 | int mdp_get_revision() |
| 55 | { |
| 56 | return mdp_rev; |
| 57 | } |
| 58 | |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 59 | static inline bool is_software_pixel_ext_config_needed() |
| 60 | { |
| 61 | return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 62 | MDSS_MDP_HW_REV_107); |
| 63 | } |
| 64 | |
| 65 | static inline bool has_fixed_size_smp() |
| 66 | { |
| 67 | return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 68 | MDSS_MDP_HW_REV_107); |
| 69 | } |
| 70 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 71 | uint32_t mdss_mdp_intf_offset() |
| 72 | { |
| 73 | uint32_t mdss_mdp_intf_off; |
| 74 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 75 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 76 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 77 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 78 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 79 | mdss_mdp_intf_off = 0x59100; |
| 80 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 81 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 82 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 83 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 84 | |
| 85 | return mdss_mdp_intf_off; |
| 86 | } |
| 87 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 88 | static uint32_t mdss_mdp_get_ppb_offset() |
| 89 | { |
| 90 | uint32_t mdss_mdp_ppb_off = 0; |
| 91 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 92 | |
| 93 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
| 94 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) |
| 95 | mdss_mdp_ppb_off = 0x1420; |
| 96 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 97 | mdss_mdp_ppb_off = 0x1334; |
| 98 | else |
| 99 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 100 | |
| 101 | return mdss_mdp_ppb_off; |
| 102 | } |
| 103 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 104 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 105 | { |
| 106 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 107 | |
| 108 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 109 | return 0xB0020; |
| 110 | else |
| 111 | return 0xC8020; |
| 112 | } |
| 113 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 114 | void mdp_clk_gating_ctrl(void) |
| 115 | { |
| 116 | writel(0x40000000, MDP_CLK_CTRL0); |
| 117 | udelay(20); |
| 118 | writel(0x40000040, MDP_CLK_CTRL0); |
| 119 | writel(0x40000000, MDP_CLK_CTRL1); |
| 120 | writel(0x00400000, MDP_CLK_CTRL3); |
| 121 | udelay(20); |
| 122 | writel(0x00404000, MDP_CLK_CTRL3); |
| 123 | writel(0x40000000, MDP_CLK_CTRL4); |
| 124 | } |
| 125 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 126 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 127 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 128 | { |
| 129 | switch (pinfo->pipe_type) { |
| 130 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 131 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 132 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 133 | break; |
| 134 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 135 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 136 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 137 | break; |
| 138 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 139 | default: |
| 140 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 141 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 142 | break; |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 147 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 148 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 149 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 150 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 151 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 152 | switch (pinfo->pipe_type) { |
| 153 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 154 | if (dual_pipe_single_ctl) |
| 155 | *ctl0_reg_val = 0x220D8; |
| 156 | else |
| 157 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 158 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 159 | |
| 160 | if (pinfo->lcdc.dst_split) |
| 161 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 162 | break; |
| 163 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 164 | if (dual_pipe_single_ctl) |
| 165 | *ctl0_reg_val = 0x238C0; |
| 166 | else |
| 167 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 168 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 169 | if (pinfo->lcdc.dst_split) |
| 170 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 171 | break; |
| 172 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 173 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 174 | if (dual_pipe_single_ctl) |
| 175 | *ctl0_reg_val = 0x220C3; |
| 176 | else |
| 177 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 178 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 179 | if (pinfo->lcdc.dst_split) |
| 180 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 181 | break; |
| 182 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 183 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 184 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 185 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 186 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 187 | if (pinfo->dest == DISPLAY_2) { |
| 188 | *ctl0_reg_val |= BIT(31); |
| 189 | *ctl1_reg_val |= BIT(30); |
| 190 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 191 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 192 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 193 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 194 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 195 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 196 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, |
| 197 | MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 198 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 199 | if (pinfo->dest == DISPLAY_2) { |
| 200 | *ctl0_reg_val |= BIT(29); |
| 201 | *ctl1_reg_val |= BIT(30); |
| 202 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 203 | *ctl0_reg_val |= BIT(30); |
| 204 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 205 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 206 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 207 | } |
| 208 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 209 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 210 | *pinfo, uint32_t pipe_base) |
| 211 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 212 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 213 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 214 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 215 | uint32_t src_xy = 0, dst_xy = 0; |
| 216 | uint32_t height, width; |
| 217 | |
| 218 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 219 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 220 | |
| 221 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 222 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 223 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 224 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 225 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 226 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 227 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 228 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 229 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | stride = (fb->stride * fb->bpp/8); |
| 233 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 234 | if (fb_off == 0) { /* left */ |
| 235 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 236 | src_xy = dst_xy; |
| 237 | } else { /* right */ |
| 238 | dst_xy = (pinfo->border_top << 16); |
| 239 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 240 | } |
| 241 | |
| 242 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 243 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 244 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 245 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 246 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 247 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 248 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 249 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 250 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 251 | |
| 252 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 253 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 254 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 255 | |
| 256 | /* bit(0) is set if hflip is required. |
| 257 | * bit(1) is set if vflip is required. |
| 258 | */ |
| 259 | if (pinfo->orientation & 0x1) |
| 260 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 261 | if (pinfo->orientation & 0x2) |
| 262 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 263 | |
| 264 | if (is_software_pixel_ext_config_needed()) { |
| 265 | flip_bits |= BIT(31); |
| 266 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ); |
| 267 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ); |
| 268 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ); |
| 269 | /* configure phase step 1 for all color components */ |
| 270 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_X); |
| 271 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_Y); |
| 272 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_X); |
| 273 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_Y); |
| 274 | } |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 275 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 276 | } |
| 277 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 278 | static void mdss_vbif_setup() |
| 279 | { |
| 280 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 281 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 282 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 283 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 284 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 285 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 286 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 287 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 288 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 289 | |
| 290 | /* |
| 291 | * Following configuration is needed because on some versions, |
| 292 | * recommended reset values are not stored. |
| 293 | */ |
| 294 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 295 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 296 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 297 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 298 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 299 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 300 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 301 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 302 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 303 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 304 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 305 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 306 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 307 | } |
| 308 | } |
| 309 | } |
| 310 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 311 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 312 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 313 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 314 | uint32_t i, j; |
| 315 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 316 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 317 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 318 | /* max 3 MMB per register */ |
| 319 | reg_val |= client_id << (((j++) % 3) * 8); |
| 320 | if ((j % 3) == 0) { |
| 321 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 322 | free_smp_offset); |
| 323 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 324 | free_smp_offset); |
| 325 | reg_val = 0; |
| 326 | free_smp_offset += 4; |
| 327 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 328 | } |
| 329 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 330 | if (j % 3) { |
| 331 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 332 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 333 | free_smp_offset += 4; |
| 334 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 335 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 336 | return free_smp_offset; |
| 337 | } |
| 338 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 339 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 340 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 341 | { |
| 342 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 343 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 344 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 345 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) || |
| 346 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 347 | switch (pinfo->pipe_type) { |
| 348 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 349 | *left_sspp_client_id = 0x7; /* 7 */ |
| 350 | *right_sspp_client_id = 0x11; /* 17 */ |
| 351 | break; |
| 352 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 353 | *left_sspp_client_id = 0x4; /* 4 */ |
| 354 | *right_sspp_client_id = 0xD; /* 13 */ |
| 355 | break; |
| 356 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 357 | default: |
| 358 | *left_sspp_client_id = 0x1; /* 1 */ |
| 359 | *right_sspp_client_id = 0x4; /* 4 */ |
| 360 | break; |
| 361 | } |
| 362 | } else { |
| 363 | switch (pinfo->pipe_type) { |
| 364 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 365 | *left_sspp_client_id = 0x10; /* 16 */ |
| 366 | *right_sspp_client_id = 0x11; /* 17 */ |
| 367 | break; |
| 368 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 369 | *left_sspp_client_id = 0xA; /* 10 */ |
| 370 | *right_sspp_client_id = 0xD; /* 13 */ |
| 371 | break; |
| 372 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 373 | default: |
| 374 | *left_sspp_client_id = 0x1; /* 1 */ |
| 375 | *right_sspp_client_id = 0x4; /* 4 */ |
| 376 | break; |
| 377 | } |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 382 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 383 | { |
| 384 | switch (pinfo->pipe_type) { |
| 385 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 386 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 387 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 388 | break; |
| 389 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 390 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 391 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 392 | break; |
| 393 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 394 | default: |
| 395 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 396 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 397 | break; |
| 398 | } |
| 399 | } |
| 400 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 401 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 402 | uint32_t right_pipe) |
| 403 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 404 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 405 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 406 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 407 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 408 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 409 | |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 410 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 411 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
| 412 | /* 8Kb per SMP on 8916/8952 */ |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 413 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 414 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 415 | /* 10Kb per SMP on 8939 */ |
| 416 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 417 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 418 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 419 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 420 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 421 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 422 | fixed_smp_cnt = 2; |
| 423 | else |
| 424 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 425 | } |
| 426 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 427 | mdp_select_pipe_client_id(pinfo, |
| 428 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 429 | |
| 430 | /* Each pipe driving half the screen */ |
| 431 | if (pinfo->lcdc.dual_pipe) |
| 432 | xres /= 2; |
| 433 | |
| 434 | /* bpp = bytes per pixel of input image */ |
| 435 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 436 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 437 | |
| 438 | if (smp_cnt > 4) { |
| 439 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 440 | smp_cnt); |
| 441 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 442 | } |
| 443 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 444 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 445 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 446 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 447 | |
| 448 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 449 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 450 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 451 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 452 | } |
| 453 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 454 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 455 | fixed_smp_cnt, free_smp_offset); |
| 456 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 457 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 458 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 459 | } |
| 460 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 461 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 462 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 463 | uint32_t hsync_period, vsync_period; |
| 464 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 465 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 466 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 467 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 468 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 469 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 470 | |
| 471 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 472 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 473 | |
| 474 | lcdc = &(pinfo->lcdc); |
| 475 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 476 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 477 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 478 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 479 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 480 | adjust_xres /= 2; |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 481 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 482 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 483 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 484 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 485 | } |
| 486 | } |
| 487 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 488 | if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 489 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 490 | writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 491 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 492 | } |
| 493 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 494 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 495 | pinfo->fbc.comp_ratio = 1; |
| 496 | |
| 497 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 498 | itp.yres = pinfo->yres; |
| 499 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 500 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 501 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 502 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 503 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 504 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 505 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 506 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 507 | |
| 508 | itp.border_clr = pinfo->lcdc.border_clr; |
| 509 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 510 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 511 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 512 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 513 | itp.width + itp.h_front_porch; |
| 514 | |
| 515 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 516 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 517 | |
| 518 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 519 | itp.hsync_pulse_width + |
| 520 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 521 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 522 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 523 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 524 | display_vstart = (itp.vsync_pulse_width + |
| 525 | itp.v_back_porch) |
| 526 | * hsync_period + itp.hsync_skew; |
| 527 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 528 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 529 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 530 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 531 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 532 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 533 | } |
| 534 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 535 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 536 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 537 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 538 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 539 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 540 | intf_base); |
| 541 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 542 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 543 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 544 | intf_base); |
| 545 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 546 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 547 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 548 | intf_base); |
| 549 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 550 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 551 | intf_base); |
| 552 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 553 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 554 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 555 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 556 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 557 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 558 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 559 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 560 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 561 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 562 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 563 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 564 | } |
| 565 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 566 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 567 | uint32_t intf_base) |
| 568 | { |
| 569 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 570 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 571 | uint32_t prefetch_avail, prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 572 | uint32_t adjust_xres = 0; |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 573 | uint32_t fetch_enable = BIT(31); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 574 | |
| 575 | struct lcdc_panel_info *lcdc = NULL; |
| 576 | |
| 577 | if (pinfo == NULL) |
| 578 | return; |
| 579 | |
| 580 | lcdc = &(pinfo->lcdc); |
| 581 | if (lcdc == NULL) |
| 582 | return; |
| 583 | |
| 584 | /* |
| 585 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 586 | * Programmable fetch is not needed if vertical back porch |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 587 | * plus vertical puls width is >= 25. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 588 | */ |
| 589 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 590 | (lcdc->v_back_porch + lcdc->v_pulse_width) >= |
| 591 | MDSS_MDP_MAX_PREFILL_FETCH) |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 592 | return; |
| 593 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 594 | adjust_xres = pinfo->xres; |
| 595 | if (pinfo->lcdc.split_display) |
| 596 | adjust_xres /= 2; |
| 597 | |
Jeevan Shriram | 4466729 | 2015-03-17 17:28:39 -0700 | [diff] [blame] | 598 | if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) |
| 599 | adjust_xres /= pinfo->fbc.comp_ratio; |
| 600 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 601 | /* |
| 602 | * Fetch should always be outside the active lines. If the fetching |
| 603 | * is programmed within active region, hardware behavior is unknown. |
| 604 | */ |
| 605 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 606 | lcdc->v_front_porch; |
| 607 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 608 | lcdc->h_front_porch; |
| 609 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 610 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 611 | prefetch_avail = v_total - vfp_start; |
| 612 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - |
| 613 | lcdc->v_back_porch - |
| 614 | lcdc->v_pulse_width; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 615 | |
| 616 | /* |
| 617 | * In some cases, vertical front porch is too high. In such cases limit |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 618 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 619 | */ |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 620 | if (prefetch_avail > prefetch_needed) |
| 621 | prefetch_avail = prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 622 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 623 | fetch_start = (v_total - prefetch_avail) * h_total + 1; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 624 | |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 625 | if (pinfo->dfps.panel_dfps.enabled) |
| 626 | fetch_enable |= BIT(23); |
| 627 | |
| 628 | writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 629 | writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 630 | } |
| 631 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 632 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 633 | *pinfo) |
| 634 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 635 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 636 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 637 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 638 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 639 | width = fb->width; |
| 640 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 641 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 642 | width /= 2; |
| 643 | |
| 644 | /* write active region size*/ |
| 645 | mdp_rgb_size = (height << 16) | width; |
| 646 | |
| 647 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 648 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 649 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 650 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 651 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 652 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 653 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 654 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 655 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 656 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 657 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 658 | switch (pinfo->pipe_type) { |
| 659 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 660 | left_staging_level = 0x0000200; |
| 661 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 662 | break; |
| 663 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 664 | left_staging_level = 0x0040000; |
| 665 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 666 | break; |
| 667 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 668 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 669 | left_staging_level = 0x1; |
| 670 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 671 | break; |
| 672 | } |
| 673 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 674 | /* |
| 675 | * When ping-pong split is enabled and two pipes are used, |
| 676 | * both the pipes need to be staged on the same layer mixer. |
| 677 | */ |
| 678 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 679 | left_staging_level |= right_staging_level; |
| 680 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 681 | /* Base layer for layer mixer 0 */ |
| 682 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 683 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 684 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 685 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 686 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 687 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 688 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 689 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 690 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 691 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 692 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 693 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 694 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 695 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 696 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 697 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 698 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 699 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 700 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 701 | } |
| 702 | } |
| 703 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 704 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 705 | { |
| 706 | uint32_t mode = 0; |
| 707 | uint32_t budget_ctl = 0; |
| 708 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 709 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 710 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 711 | |
| 712 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 713 | |
| 714 | if (!pinfo->fbc.enabled) |
| 715 | return; |
| 716 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 717 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 718 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 719 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 720 | width = pinfo->xres; |
| 721 | if (enc_mode) |
| 722 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 723 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 724 | if (pinfo->mipi.dual_dsi) |
| 725 | width /= 2; |
| 726 | |
| 727 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 728 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 729 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 730 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 731 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 732 | |
| 733 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 734 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 735 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 736 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 737 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 738 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 739 | |
| 740 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 741 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 742 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 743 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 744 | ((fbc->lossy_mode_thd) << 8) | |
| 745 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 746 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 747 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 748 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 749 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 750 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 751 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 752 | |
| 753 | if (pinfo->mipi.dual_dsi) { |
| 754 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 755 | writel(budget_ctl, MDP_PP_1_BASE + |
| 756 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 757 | writel(lossy_mode, MDP_PP_1_BASE + |
| 758 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 759 | } |
| 760 | } |
| 761 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 762 | void mdss_qos_remapper_setup(void) |
| 763 | { |
| 764 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 765 | uint32_t map; |
| 766 | |
| 767 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 768 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 769 | MDSS_MDP_HW_REV_102)) |
| 770 | map = 0xE9; |
| 771 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 772 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 773 | map = 0xA5; |
| 774 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 775 | MDSS_MDP_HW_REV_106) || |
| 776 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 777 | MDSS_MDP_HW_REV_108) || |
| 778 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 779 | MDSS_MDP_HW_REV_112)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 780 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 781 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 782 | MDSS_MDP_HW_REV_105) || |
| 783 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 784 | MDSS_MDP_HW_REV_109) || |
| 785 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 786 | MDSS_MDP_HW_REV_107) || |
| 787 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 788 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 789 | map = 0xA4; |
| 790 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 791 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 792 | map = 0xFA; |
| 793 | else |
| 794 | return; |
| 795 | |
| 796 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 797 | } |
| 798 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 799 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 800 | { |
| 801 | uint32_t mask, reg_val, i; |
| 802 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 803 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 804 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 805 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 806 | |
| 807 | mdp_select_pipe_xin_id(pinfo, |
| 808 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 809 | |
| 810 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 811 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) || |
| 812 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 813 | vbif_qos[0] = 2; |
| 814 | vbif_qos[1] = 2; |
| 815 | vbif_qos[2] = 2; |
| 816 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 817 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 818 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 819 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 820 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 821 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 822 | vbif_qos[1] = 2; |
| 823 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 824 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 825 | } else { |
| 826 | return; |
| 827 | } |
| 828 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 829 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 830 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 831 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 832 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 833 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 834 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 835 | reg_val &= ~(mask); |
| 836 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 837 | |
| 838 | if (pinfo->lcdc.dual_pipe) { |
| 839 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 840 | reg_val &= ~(mask); |
| 841 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 842 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 843 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 844 | } |
| 845 | } |
| 846 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 847 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 848 | int is_main_ctl) |
| 849 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 850 | uint32_t mctl_intf_sel; |
| 851 | uint32_t sctl_intf_sel; |
| 852 | |
| 853 | if ((pinfo->dest == DISPLAY_2) || |
| 854 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 855 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 856 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 857 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 858 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 859 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 860 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 861 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 862 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 863 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 864 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 865 | } |
| 866 | |
| 867 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 868 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 869 | uint32_t *intf_base, uint32_t *sintf_base) |
| 870 | { |
| 871 | if (pinfo->dest == DISPLAY_2) { |
| 872 | *intf_sel = BIT(16); |
| 873 | *sintf_sel = BIT(8); |
| 874 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 875 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 876 | } else { |
| 877 | *intf_sel = BIT(8); |
| 878 | *sintf_sel = BIT(16); |
| 879 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 880 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 881 | } |
| 882 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 883 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 884 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 885 | } |
| 886 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 887 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 888 | struct fbcon_config *fb) |
| 889 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 890 | uint32_t intf_sel, sintf_sel; |
| 891 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 892 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 893 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 894 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 895 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 896 | |
| 897 | mdss_intf_tg_setup(pinfo, intf_base); |
| 898 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 899 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 900 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 901 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 902 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 903 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 904 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 905 | mdp_clk_gating_ctrl(); |
| 906 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 907 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 908 | mdss_vbif_setup(); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame^] | 909 | if (!has_fixed_size_smp()) |
| 910 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 911 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 912 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 913 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 914 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 915 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 916 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 917 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 918 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 919 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 920 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 921 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 922 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 923 | |
| 924 | /* enable 3D mux for dual_pipe but single interface config */ |
| 925 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 926 | !pinfo->lcdc.split_display) |
| 927 | reg |= BIT(19) | BIT(20); |
| 928 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 929 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 930 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 931 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 932 | CTL_1 path should not be set since CTL_0 itself is going |
| 933 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 934 | if (pinfo->fbc.enabled) |
| 935 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 936 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 937 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 938 | if (!pinfo->lcdc.dst_split) { |
| 939 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 940 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 941 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 942 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 943 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 944 | |
| 945 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 946 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 947 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 948 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 949 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 950 | |
| 951 | return 0; |
| 952 | } |
| 953 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 954 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 955 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 956 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 957 | |
| 958 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 959 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 960 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 961 | mdp_clk_gating_ctrl(); |
| 962 | |
| 963 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 964 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 965 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 966 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 967 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 968 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 969 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 970 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 971 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 972 | |
| 973 | mdss_layer_mixer_setup(fb, pinfo); |
| 974 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 975 | if (pinfo->lcdc.dual_pipe) |
| 976 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 977 | else |
| 978 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 979 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 980 | writel(0x9, MDP_DISP_INTF_SEL); |
| 981 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 982 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 983 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 984 | |
| 985 | return 0; |
| 986 | } |
| 987 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 988 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 989 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 990 | uint32_t left_pipe, right_pipe; |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 991 | dprintf(SPEW, "ENTER: %s\n", __func__); |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 992 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 993 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset()); |
| 994 | pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB; |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 995 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 996 | |
| 997 | mdp_clk_gating_ctrl(); |
| 998 | mdss_vbif_setup(); |
| 999 | |
| 1000 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 1001 | |
| 1002 | mdss_qos_remapper_setup(); |
| 1003 | |
| 1004 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1005 | if (pinfo->lcdc.dual_pipe) |
| 1006 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 1007 | |
| 1008 | mdss_layer_mixer_setup(fb, pinfo); |
| 1009 | |
| 1010 | if (pinfo->lcdc.dual_pipe) |
| 1011 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 1012 | else |
| 1013 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 1014 | |
| 1015 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 1016 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1017 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1018 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1019 | |
| 1020 | return 0; |
| 1021 | } |
| 1022 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1023 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 1024 | struct fbcon_config *fb) |
| 1025 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1026 | uint32_t intf_sel, sintf_sel; |
| 1027 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1028 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1029 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1030 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1031 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1032 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1033 | |
| 1034 | if (pinfo == NULL) |
| 1035 | return ERR_INVALID_ARGS; |
| 1036 | |
| 1037 | lcdc = &(pinfo->lcdc); |
| 1038 | if (lcdc == NULL) |
| 1039 | return ERR_INVALID_ARGS; |
| 1040 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1041 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 1042 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1043 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1044 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1045 | if (pinfo->lcdc.dst_split) |
| 1046 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1047 | if (pinfo->lcdc.pipe_swap) |
| 1048 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 1049 | else |
| 1050 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1051 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1052 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1053 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1054 | } |
| 1055 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1056 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1057 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 1058 | writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 1059 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1060 | } |
| 1061 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1062 | mdp_clk_gating_ctrl(); |
| 1063 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1064 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1065 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1066 | |
| 1067 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1068 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1069 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1070 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1071 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1072 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1073 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1074 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1075 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1076 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1077 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1078 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1079 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1080 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1081 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1082 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1083 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 1084 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1085 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1086 | if (pinfo->fbc.enabled) |
| 1087 | mdss_fbc_cfg(pinfo); |
| 1088 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1089 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1090 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1091 | if (!pinfo->lcdc.dst_split) { |
| 1092 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1093 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1094 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1095 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1096 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1097 | return ret; |
| 1098 | } |
| 1099 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1100 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1101 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1102 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1103 | uint32_t timing_engine_en; |
| 1104 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1105 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1106 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1107 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1108 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1109 | |
| 1110 | if (pinfo->dest == DISPLAY_1) |
| 1111 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1112 | else |
| 1113 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1114 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1115 | |
| 1116 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1117 | } |
| 1118 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1119 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1120 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1121 | uint32_t timing_engine_en; |
| 1122 | |
| 1123 | if (pinfo->dest == DISPLAY_1) |
| 1124 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1125 | else |
| 1126 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1127 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1128 | if(!target_cont_splash_screen()) |
| 1129 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1130 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1131 | mdelay(60); |
| 1132 | /* Ping-Pong done Tear Check Read/Write */ |
| 1133 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1134 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1135 | } |
| 1136 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1137 | writel(0x00000000, MDP_INTR_EN); |
| 1138 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1139 | return NO_ERROR; |
| 1140 | } |
| 1141 | |
| 1142 | int mdp_dsi_cmd_off() |
| 1143 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1144 | if(!target_cont_splash_screen()) |
| 1145 | { |
| 1146 | /* Ping-Pong done Tear Check Read/Write */ |
| 1147 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1148 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1149 | } |
| 1150 | writel(0x00000000, MDP_INTR_EN); |
| 1151 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1152 | return NO_ERROR; |
| 1153 | } |
| 1154 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1155 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1156 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1157 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1158 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1159 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1160 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1161 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1162 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1163 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1164 | return NO_ERROR; |
| 1165 | } |
| 1166 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1167 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1168 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1169 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1170 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1171 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1172 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1173 | return NO_ERROR; |
| 1174 | } |
| 1175 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1176 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1177 | { |
| 1178 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1179 | |
| 1180 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1181 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1182 | |
| 1183 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1184 | |
| 1185 | return NO_ERROR; |
| 1186 | } |
| 1187 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1188 | int mdp_edp_off(void) |
| 1189 | { |
| 1190 | if (!target_cont_splash_screen()) { |
| 1191 | |
| 1192 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1193 | mdss_mdp_intf_offset()); |
| 1194 | mdelay(60); |
| 1195 | /* Ping-Pong done Tear Check Read/Write */ |
| 1196 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1197 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1198 | writel(0x00000000, MDP_INTR_EN); |
| 1199 | } |
| 1200 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1201 | writel(0x00000000, MDP_INTR_EN); |
| 1202 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1203 | return NO_ERROR; |
| 1204 | } |