Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 43 | #define MDSS_MDP_MAX_PREFILL_FETCH 25 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 44 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 45 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 46 | |
| 47 | static int mdp_rev; |
| 48 | |
| 49 | void mdp_set_revision(int rev) |
| 50 | { |
| 51 | mdp_rev = rev; |
| 52 | } |
| 53 | |
| 54 | int mdp_get_revision() |
| 55 | { |
| 56 | return mdp_rev; |
| 57 | } |
| 58 | |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 59 | static inline bool is_software_pixel_ext_config_needed() |
| 60 | { |
| 61 | return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 62 | MDSS_MDP_HW_REV_107); |
| 63 | } |
| 64 | |
| 65 | static inline bool has_fixed_size_smp() |
| 66 | { |
| 67 | return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 68 | MDSS_MDP_HW_REV_107); |
| 69 | } |
| 70 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 71 | uint32_t mdss_mdp_intf_offset() |
| 72 | { |
| 73 | uint32_t mdss_mdp_intf_off; |
| 74 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 75 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 76 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 77 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 78 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 79 | mdss_mdp_intf_off = 0x59100; |
| 80 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 81 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 82 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 83 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 84 | |
| 85 | return mdss_mdp_intf_off; |
| 86 | } |
| 87 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 88 | static uint32_t mdss_mdp_get_ppb_offset() |
| 89 | { |
| 90 | uint32_t mdss_mdp_ppb_off = 0; |
| 91 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 92 | |
| 93 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
| 94 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) |
| 95 | mdss_mdp_ppb_off = 0x1420; |
| 96 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 97 | mdss_mdp_ppb_off = 0x1334; |
| 98 | else |
| 99 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 100 | |
| 101 | return mdss_mdp_ppb_off; |
| 102 | } |
| 103 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 104 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 105 | { |
| 106 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 107 | |
| 108 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 109 | return 0xB0020; |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 110 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 111 | return 0xB0000; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 112 | else |
| 113 | return 0xC8020; |
| 114 | } |
| 115 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 116 | void mdp_clk_gating_ctrl(void) |
| 117 | { |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 118 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 119 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 120 | return; |
| 121 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 122 | writel(0x40000000, MDP_CLK_CTRL0); |
| 123 | udelay(20); |
| 124 | writel(0x40000040, MDP_CLK_CTRL0); |
| 125 | writel(0x40000000, MDP_CLK_CTRL1); |
| 126 | writel(0x00400000, MDP_CLK_CTRL3); |
| 127 | udelay(20); |
| 128 | writel(0x00404000, MDP_CLK_CTRL3); |
| 129 | writel(0x40000000, MDP_CLK_CTRL4); |
| 130 | } |
| 131 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 132 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 133 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 134 | { |
| 135 | switch (pinfo->pipe_type) { |
| 136 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 137 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 138 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 139 | break; |
| 140 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 141 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 142 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 143 | break; |
| 144 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 145 | default: |
| 146 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 147 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 148 | break; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 153 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 154 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 155 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 156 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 157 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 158 | switch (pinfo->pipe_type) { |
| 159 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 160 | if (dual_pipe_single_ctl) |
| 161 | *ctl0_reg_val = 0x220D8; |
| 162 | else |
| 163 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 164 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 165 | |
| 166 | if (pinfo->lcdc.dst_split) |
| 167 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 168 | break; |
| 169 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 170 | if (dual_pipe_single_ctl) |
| 171 | *ctl0_reg_val = 0x238C0; |
| 172 | else |
| 173 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 174 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 175 | if (pinfo->lcdc.dst_split) |
| 176 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 177 | break; |
| 178 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 179 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 180 | if (dual_pipe_single_ctl) |
| 181 | *ctl0_reg_val = 0x220C3; |
| 182 | else |
| 183 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 184 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 185 | if (pinfo->lcdc.dst_split) |
| 186 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 187 | break; |
| 188 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 189 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 190 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 191 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 192 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 193 | if (pinfo->dest == DISPLAY_2) { |
| 194 | *ctl0_reg_val |= BIT(31); |
| 195 | *ctl1_reg_val |= BIT(30); |
| 196 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 197 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 198 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 199 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 200 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 201 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 202 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, |
| 203 | MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 204 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 205 | if (pinfo->dest == DISPLAY_2) { |
| 206 | *ctl0_reg_val |= BIT(29); |
| 207 | *ctl1_reg_val |= BIT(30); |
| 208 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 209 | *ctl0_reg_val |= BIT(30); |
| 210 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 211 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 212 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 213 | } |
| 214 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 215 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 216 | *pinfo, uint32_t pipe_base) |
| 217 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 218 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 219 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 220 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 221 | uint32_t src_xy = 0, dst_xy = 0; |
| 222 | uint32_t height, width; |
| 223 | |
| 224 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 225 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 226 | |
| 227 | /* write active region size*/ |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 228 | src_size = (height << 16) + width; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 229 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 230 | if (pinfo->lcdc.dual_pipe) { |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 231 | out_size = (height << 16) + (width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 232 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 233 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 234 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 235 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | stride = (fb->stride * fb->bpp/8); |
| 239 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 240 | if (fb_off == 0) { /* left */ |
| 241 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 242 | src_xy = dst_xy; |
| 243 | } else { /* right */ |
| 244 | dst_xy = (pinfo->border_top << 16); |
| 245 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 246 | } |
| 247 | |
| 248 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 249 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 250 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 251 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 252 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 253 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 254 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 255 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 256 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 257 | |
| 258 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 259 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 260 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 261 | |
| 262 | /* bit(0) is set if hflip is required. |
| 263 | * bit(1) is set if vflip is required. |
| 264 | */ |
| 265 | if (pinfo->orientation & 0x1) |
| 266 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 267 | if (pinfo->orientation & 0x2) |
| 268 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 269 | |
| 270 | if (is_software_pixel_ext_config_needed()) { |
| 271 | flip_bits |= BIT(31); |
| 272 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ); |
| 273 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ); |
| 274 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ); |
| 275 | /* configure phase step 1 for all color components */ |
| 276 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_X); |
| 277 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_Y); |
| 278 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_X); |
| 279 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_Y); |
| 280 | } |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 281 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 282 | } |
| 283 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 284 | static void mdss_vbif_setup() |
| 285 | { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 286 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 287 | int access_secure = false; |
| 288 | if (!MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107)) |
| 289 | access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 290 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 291 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 292 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 293 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 294 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 295 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 296 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 297 | |
| 298 | /* |
| 299 | * Following configuration is needed because on some versions, |
| 300 | * recommended reset values are not stored. |
| 301 | */ |
| 302 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 303 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 304 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 305 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 306 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 307 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 308 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 309 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 310 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 311 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 312 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 313 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 314 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 315 | } |
| 316 | } |
| 317 | } |
| 318 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 319 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 320 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 321 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 322 | uint32_t i, j; |
| 323 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 324 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 325 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 326 | /* max 3 MMB per register */ |
| 327 | reg_val |= client_id << (((j++) % 3) * 8); |
| 328 | if ((j % 3) == 0) { |
| 329 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 330 | free_smp_offset); |
| 331 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 332 | free_smp_offset); |
| 333 | reg_val = 0; |
| 334 | free_smp_offset += 4; |
| 335 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 336 | } |
| 337 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 338 | if (j % 3) { |
| 339 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 340 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 341 | free_smp_offset += 4; |
| 342 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 343 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 344 | return free_smp_offset; |
| 345 | } |
| 346 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 347 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 348 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 349 | { |
| 350 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 351 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 352 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 353 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) || |
| 354 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 355 | switch (pinfo->pipe_type) { |
| 356 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 357 | *left_sspp_client_id = 0x7; /* 7 */ |
| 358 | *right_sspp_client_id = 0x11; /* 17 */ |
| 359 | break; |
| 360 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 361 | *left_sspp_client_id = 0x4; /* 4 */ |
| 362 | *right_sspp_client_id = 0xD; /* 13 */ |
| 363 | break; |
| 364 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 365 | default: |
| 366 | *left_sspp_client_id = 0x1; /* 1 */ |
| 367 | *right_sspp_client_id = 0x4; /* 4 */ |
| 368 | break; |
| 369 | } |
| 370 | } else { |
| 371 | switch (pinfo->pipe_type) { |
| 372 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 373 | *left_sspp_client_id = 0x10; /* 16 */ |
| 374 | *right_sspp_client_id = 0x11; /* 17 */ |
| 375 | break; |
| 376 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 377 | *left_sspp_client_id = 0xA; /* 10 */ |
| 378 | *right_sspp_client_id = 0xD; /* 13 */ |
| 379 | break; |
| 380 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 381 | default: |
| 382 | *left_sspp_client_id = 0x1; /* 1 */ |
| 383 | *right_sspp_client_id = 0x4; /* 4 */ |
| 384 | break; |
| 385 | } |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 390 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 391 | { |
| 392 | switch (pinfo->pipe_type) { |
| 393 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 394 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 395 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 396 | break; |
| 397 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 398 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 399 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 400 | break; |
| 401 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 402 | default: |
| 403 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 404 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 405 | break; |
| 406 | } |
| 407 | } |
| 408 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 409 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 410 | uint32_t right_pipe) |
| 411 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 412 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 413 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 414 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 415 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 416 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 417 | |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 418 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 419 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
| 420 | /* 8Kb per SMP on 8916/8952 */ |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 421 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 422 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 423 | /* 10Kb per SMP on 8939 */ |
| 424 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 425 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 426 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 427 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 428 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 429 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 430 | fixed_smp_cnt = 2; |
| 431 | else |
| 432 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 433 | } |
| 434 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 435 | mdp_select_pipe_client_id(pinfo, |
| 436 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 437 | |
| 438 | /* Each pipe driving half the screen */ |
| 439 | if (pinfo->lcdc.dual_pipe) |
| 440 | xres /= 2; |
| 441 | |
| 442 | /* bpp = bytes per pixel of input image */ |
| 443 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 444 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 445 | |
| 446 | if (smp_cnt > 4) { |
| 447 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 448 | smp_cnt); |
| 449 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 450 | } |
| 451 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 452 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 453 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 454 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 455 | |
| 456 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 457 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 458 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 459 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 460 | } |
| 461 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 462 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 463 | fixed_smp_cnt, free_smp_offset); |
| 464 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 465 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 466 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 467 | } |
| 468 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 469 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 470 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 471 | uint32_t hsync_period, vsync_period; |
| 472 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 473 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 474 | uint32_t adjust_xres = 0; |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame^] | 475 | uint32_t upper = 0, lower = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 476 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 477 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 478 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 479 | |
| 480 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 481 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 482 | |
| 483 | lcdc = &(pinfo->lcdc); |
| 484 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 485 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 486 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 487 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 488 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 489 | adjust_xres /= 2; |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 490 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) { |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame^] | 491 | if (pinfo->lcdc.pipe_swap) { |
| 492 | lower |= BIT(4); |
| 493 | upper |= BIT(8); |
| 494 | } else { |
| 495 | lower |= BIT(8); |
| 496 | upper |= BIT(4); |
| 497 | } |
| 498 | writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
| 499 | writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 500 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 501 | } |
| 502 | } |
| 503 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 504 | if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 505 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 506 | writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 507 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 508 | } |
| 509 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 510 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 511 | pinfo->fbc.comp_ratio = 1; |
| 512 | |
| 513 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 514 | itp.yres = pinfo->yres; |
| 515 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
| 516 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 517 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 518 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 519 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 520 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 521 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 522 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 523 | |
| 524 | itp.border_clr = pinfo->lcdc.border_clr; |
| 525 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 526 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 527 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 528 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 529 | itp.width + itp.h_front_porch; |
| 530 | |
| 531 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 532 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 533 | |
| 534 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 535 | itp.hsync_pulse_width + |
| 536 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 537 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 538 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 539 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 540 | display_vstart = (itp.vsync_pulse_width + |
| 541 | itp.v_back_porch) |
| 542 | * hsync_period + itp.hsync_skew; |
| 543 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 544 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 545 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 546 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 547 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 548 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 549 | } |
| 550 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 551 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 552 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 553 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 554 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 555 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 556 | intf_base); |
| 557 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 558 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 559 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 560 | intf_base); |
| 561 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 562 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 563 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 564 | intf_base); |
| 565 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 566 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 567 | intf_base); |
| 568 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 569 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 570 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 571 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 572 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 573 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 574 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 575 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 576 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 577 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 578 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 579 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 580 | } |
| 581 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 582 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 583 | uint32_t intf_base) |
| 584 | { |
| 585 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 586 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 587 | uint32_t prefetch_avail, prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 588 | uint32_t adjust_xres = 0; |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 589 | uint32_t fetch_enable = BIT(31); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 590 | |
| 591 | struct lcdc_panel_info *lcdc = NULL; |
| 592 | |
| 593 | if (pinfo == NULL) |
| 594 | return; |
| 595 | |
| 596 | lcdc = &(pinfo->lcdc); |
| 597 | if (lcdc == NULL) |
| 598 | return; |
| 599 | |
| 600 | /* |
| 601 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 602 | * Programmable fetch is not needed if vertical back porch |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 603 | * plus vertical puls width is >= 25. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 604 | */ |
| 605 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 606 | (lcdc->v_back_porch + lcdc->v_pulse_width) >= |
| 607 | MDSS_MDP_MAX_PREFILL_FETCH) |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 608 | return; |
| 609 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 610 | adjust_xres = pinfo->xres; |
| 611 | if (pinfo->lcdc.split_display) |
| 612 | adjust_xres /= 2; |
| 613 | |
Jeevan Shriram | 4466729 | 2015-03-17 17:28:39 -0700 | [diff] [blame] | 614 | if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) |
| 615 | adjust_xres /= pinfo->fbc.comp_ratio; |
| 616 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 617 | /* |
| 618 | * Fetch should always be outside the active lines. If the fetching |
| 619 | * is programmed within active region, hardware behavior is unknown. |
| 620 | */ |
| 621 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 622 | lcdc->v_front_porch; |
| 623 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 624 | lcdc->h_front_porch; |
| 625 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 626 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 627 | prefetch_avail = v_total - vfp_start; |
| 628 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - |
| 629 | lcdc->v_back_porch - |
| 630 | lcdc->v_pulse_width; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 631 | |
| 632 | /* |
| 633 | * In some cases, vertical front porch is too high. In such cases limit |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 634 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 635 | */ |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 636 | if (prefetch_avail > prefetch_needed) |
| 637 | prefetch_avail = prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 638 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 639 | fetch_start = (v_total - prefetch_avail) * h_total + 1; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 640 | |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 641 | if (pinfo->dfps.panel_dfps.enabled) |
| 642 | fetch_enable |= BIT(23); |
| 643 | |
| 644 | writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 645 | writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 646 | } |
| 647 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 648 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 649 | *pinfo) |
| 650 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 651 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 652 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 653 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 654 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 655 | width = fb->width; |
| 656 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 657 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 658 | width /= 2; |
| 659 | |
| 660 | /* write active region size*/ |
| 661 | mdp_rgb_size = (height << 16) | width; |
| 662 | |
| 663 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 664 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 665 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 666 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 667 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 668 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 669 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 670 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 671 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 672 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 673 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 674 | switch (pinfo->pipe_type) { |
| 675 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 676 | left_staging_level = 0x0000200; |
| 677 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 678 | break; |
| 679 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 680 | left_staging_level = 0x0040000; |
| 681 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 682 | break; |
| 683 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 684 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 685 | left_staging_level = 0x1; |
| 686 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 687 | break; |
| 688 | } |
| 689 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 690 | /* |
| 691 | * When ping-pong split is enabled and two pipes are used, |
| 692 | * both the pipes need to be staged on the same layer mixer. |
| 693 | */ |
| 694 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 695 | left_staging_level |= right_staging_level; |
| 696 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 697 | /* Base layer for layer mixer 0 */ |
| 698 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 699 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 700 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 701 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 702 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 703 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 704 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 705 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 706 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 707 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 708 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 709 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 710 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 711 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 712 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 713 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 714 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 715 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 716 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 717 | } |
| 718 | } |
| 719 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 720 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 721 | { |
| 722 | uint32_t mode = 0; |
| 723 | uint32_t budget_ctl = 0; |
| 724 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 725 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 726 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 727 | |
| 728 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 729 | |
| 730 | if (!pinfo->fbc.enabled) |
| 731 | return; |
| 732 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 733 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 734 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 735 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 736 | width = pinfo->xres; |
| 737 | if (enc_mode) |
| 738 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 739 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 740 | if (pinfo->mipi.dual_dsi) |
| 741 | width /= 2; |
| 742 | |
| 743 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 744 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 745 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 746 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 747 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 748 | |
| 749 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 750 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 751 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 752 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 753 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 754 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 755 | |
| 756 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 757 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 758 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 759 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 760 | ((fbc->lossy_mode_thd) << 8) | |
| 761 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 762 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 763 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 764 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 765 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 766 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 767 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 768 | |
| 769 | if (pinfo->mipi.dual_dsi) { |
| 770 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 771 | writel(budget_ctl, MDP_PP_1_BASE + |
| 772 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 773 | writel(lossy_mode, MDP_PP_1_BASE + |
| 774 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 775 | } |
| 776 | } |
| 777 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 778 | void mdss_qos_remapper_setup(void) |
| 779 | { |
| 780 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 781 | uint32_t map; |
| 782 | |
| 783 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 784 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 785 | MDSS_MDP_HW_REV_102)) |
| 786 | map = 0xE9; |
| 787 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 788 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 789 | map = 0xA5; |
| 790 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 791 | MDSS_MDP_HW_REV_106) || |
| 792 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 793 | MDSS_MDP_HW_REV_108) || |
| 794 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 795 | MDSS_MDP_HW_REV_112)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 796 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 797 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 798 | MDSS_MDP_HW_REV_105) || |
| 799 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 800 | MDSS_MDP_HW_REV_109) || |
| 801 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 802 | MDSS_MDP_HW_REV_107) || |
| 803 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 804 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 805 | map = 0xA4; |
| 806 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 807 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 808 | map = 0xFA; |
| 809 | else |
| 810 | return; |
| 811 | |
| 812 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 813 | } |
| 814 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 815 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 816 | { |
| 817 | uint32_t mask, reg_val, i; |
| 818 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 819 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 820 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 821 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 822 | |
| 823 | mdp_select_pipe_xin_id(pinfo, |
| 824 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 825 | |
| 826 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 827 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) || |
| 828 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 829 | vbif_qos[0] = 2; |
| 830 | vbif_qos[1] = 2; |
| 831 | vbif_qos[2] = 2; |
| 832 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 833 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 834 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 835 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 836 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 837 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 838 | vbif_qos[1] = 2; |
| 839 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 840 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 841 | } else { |
| 842 | return; |
| 843 | } |
| 844 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 845 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 846 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 847 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 848 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 849 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 850 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 851 | reg_val &= ~(mask); |
| 852 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 853 | |
| 854 | if (pinfo->lcdc.dual_pipe) { |
| 855 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 856 | reg_val &= ~(mask); |
| 857 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 858 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 859 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 860 | } |
| 861 | } |
| 862 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 863 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 864 | int is_main_ctl) |
| 865 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 866 | uint32_t mctl_intf_sel; |
| 867 | uint32_t sctl_intf_sel; |
| 868 | |
| 869 | if ((pinfo->dest == DISPLAY_2) || |
| 870 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 871 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 872 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 873 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 874 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 875 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 876 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 877 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 878 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 879 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 880 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 881 | } |
| 882 | |
| 883 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 884 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 885 | uint32_t *intf_base, uint32_t *sintf_base) |
| 886 | { |
| 887 | if (pinfo->dest == DISPLAY_2) { |
| 888 | *intf_sel = BIT(16); |
| 889 | *sintf_sel = BIT(8); |
| 890 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 891 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 892 | } else { |
| 893 | *intf_sel = BIT(8); |
| 894 | *sintf_sel = BIT(16); |
| 895 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 896 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 897 | } |
| 898 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 899 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 900 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 901 | } |
| 902 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 903 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 904 | struct fbcon_config *fb) |
| 905 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 906 | uint32_t intf_sel, sintf_sel; |
| 907 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 908 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 909 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 910 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 911 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 912 | |
| 913 | mdss_intf_tg_setup(pinfo, intf_base); |
| 914 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 915 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 916 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 917 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 918 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 919 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 920 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 921 | mdp_clk_gating_ctrl(); |
| 922 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 923 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 924 | mdss_vbif_setup(); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 925 | if (!has_fixed_size_smp()) |
| 926 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 927 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 928 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 929 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 930 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 931 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 932 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 933 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 934 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 935 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 936 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 937 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 938 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 939 | |
| 940 | /* enable 3D mux for dual_pipe but single interface config */ |
| 941 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 942 | !pinfo->lcdc.split_display) |
| 943 | reg |= BIT(19) | BIT(20); |
| 944 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 945 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 946 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 947 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 948 | CTL_1 path should not be set since CTL_0 itself is going |
| 949 | to split after DSPP block*/ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 950 | if (pinfo->fbc.enabled) |
| 951 | mdss_fbc_cfg(pinfo); |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 952 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 953 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 954 | if (!pinfo->lcdc.dst_split) { |
| 955 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 956 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 957 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 958 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 959 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 960 | |
| 961 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 962 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 963 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 964 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 965 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 966 | |
| 967 | return 0; |
| 968 | } |
| 969 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 970 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 971 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 972 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 973 | |
| 974 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 975 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 976 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 977 | mdp_clk_gating_ctrl(); |
| 978 | |
| 979 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 980 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 981 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 982 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 983 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 984 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 985 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 986 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 987 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 988 | |
| 989 | mdss_layer_mixer_setup(fb, pinfo); |
| 990 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 991 | if (pinfo->lcdc.dual_pipe) |
| 992 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 993 | else |
| 994 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 995 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 996 | writel(0x9, MDP_DISP_INTF_SEL); |
| 997 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 998 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 999 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1000 | |
| 1001 | return 0; |
| 1002 | } |
| 1003 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1004 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1005 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1006 | uint32_t left_pipe, right_pipe; |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1007 | dprintf(SPEW, "ENTER: %s\n", __func__); |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1008 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1009 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset()); |
| 1010 | pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB; |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1011 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 1012 | |
| 1013 | mdp_clk_gating_ctrl(); |
| 1014 | mdss_vbif_setup(); |
| 1015 | |
| 1016 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 1017 | |
| 1018 | mdss_qos_remapper_setup(); |
| 1019 | |
| 1020 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1021 | if (pinfo->lcdc.dual_pipe) |
| 1022 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 1023 | |
| 1024 | mdss_layer_mixer_setup(fb, pinfo); |
| 1025 | |
| 1026 | if (pinfo->lcdc.dual_pipe) |
| 1027 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 1028 | else |
| 1029 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 1030 | |
| 1031 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 1032 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1033 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1034 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1035 | |
| 1036 | return 0; |
| 1037 | } |
| 1038 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1039 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 1040 | struct fbcon_config *fb) |
| 1041 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1042 | uint32_t intf_sel, sintf_sel; |
| 1043 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1044 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1045 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1046 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1047 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1048 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1049 | |
| 1050 | if (pinfo == NULL) |
| 1051 | return ERR_INVALID_ARGS; |
| 1052 | |
| 1053 | lcdc = &(pinfo->lcdc); |
| 1054 | if (lcdc == NULL) |
| 1055 | return ERR_INVALID_ARGS; |
| 1056 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1057 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 1058 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1059 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1060 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1061 | if (pinfo->lcdc.dst_split) |
| 1062 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1063 | if (pinfo->lcdc.pipe_swap) |
| 1064 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 1065 | else |
| 1066 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1067 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1068 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1069 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1070 | } |
| 1071 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1072 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1073 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
| 1074 | writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */ |
| 1075 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1076 | } |
| 1077 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1078 | mdp_clk_gating_ctrl(); |
| 1079 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1080 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1081 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1082 | |
| 1083 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1084 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1085 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1086 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1087 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1088 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1089 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1090 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1091 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1092 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1093 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1094 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1095 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1096 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1097 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1098 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1099 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 1100 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1101 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1102 | if (pinfo->fbc.enabled) |
| 1103 | mdss_fbc_cfg(pinfo); |
| 1104 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1105 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1106 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1107 | if (!pinfo->lcdc.dst_split) { |
| 1108 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1109 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1110 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1111 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1112 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1113 | return ret; |
| 1114 | } |
| 1115 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1116 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1117 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1118 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1119 | uint32_t timing_engine_en; |
| 1120 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1121 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1122 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1123 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1124 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1125 | |
| 1126 | if (pinfo->dest == DISPLAY_1) |
| 1127 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1128 | else |
| 1129 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1130 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1131 | |
| 1132 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1133 | } |
| 1134 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1135 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1136 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1137 | uint32_t timing_engine_en; |
| 1138 | |
| 1139 | if (pinfo->dest == DISPLAY_1) |
| 1140 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1141 | else |
| 1142 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1143 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1144 | if(!target_cont_splash_screen()) |
| 1145 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1146 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1147 | mdelay(60); |
| 1148 | /* Ping-Pong done Tear Check Read/Write */ |
| 1149 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1150 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1151 | } |
| 1152 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1153 | writel(0x00000000, MDP_INTR_EN); |
| 1154 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1155 | return NO_ERROR; |
| 1156 | } |
| 1157 | |
| 1158 | int mdp_dsi_cmd_off() |
| 1159 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1160 | if(!target_cont_splash_screen()) |
| 1161 | { |
| 1162 | /* Ping-Pong done Tear Check Read/Write */ |
| 1163 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1164 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1165 | } |
| 1166 | writel(0x00000000, MDP_INTR_EN); |
| 1167 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1168 | return NO_ERROR; |
| 1169 | } |
| 1170 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1171 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1172 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1173 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1174 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1175 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1176 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1177 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1178 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1179 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1180 | return NO_ERROR; |
| 1181 | } |
| 1182 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1183 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1184 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1185 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1186 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1187 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1188 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1189 | return NO_ERROR; |
| 1190 | } |
| 1191 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1192 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1193 | { |
| 1194 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1195 | |
| 1196 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1197 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1198 | |
| 1199 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1200 | |
| 1201 | return NO_ERROR; |
| 1202 | } |
| 1203 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1204 | int mdp_edp_off(void) |
| 1205 | { |
| 1206 | if (!target_cont_splash_screen()) { |
| 1207 | |
| 1208 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1209 | mdss_mdp_intf_offset()); |
| 1210 | mdelay(60); |
| 1211 | /* Ping-Pong done Tear Check Read/Write */ |
| 1212 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1213 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1214 | writel(0x00000000, MDP_INTR_EN); |
| 1215 | } |
| 1216 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1217 | writel(0x00000000, MDP_INTR_EN); |
| 1218 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1219 | return NO_ERROR; |
| 1220 | } |