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Jeevan Shriramd8f99a32015-01-07 19:07:05 -08001/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of The Linux Foundation nor
11 * the names of its contributors may be used to endorse or promote
12 * products derived from this software without specific prior written
13 * permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <mdp5.h>
29#include <debug.h>
30#include <reg.h>
31#include <target/display.h>
32#include <platform/timer.h>
33#include <platform/iomap.h>
34#include <dev/lcdc.h>
35#include <dev/fbcon.h>
36#include <bits.h>
37#include <msm_panel.h>
38#include <mipi_dsi.h>
39#include <err.h>
40#include <clock.h>
Siddhartha Agrawal8d690822013-01-28 12:18:58 -080041#include <scm.h>
42
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -080043#define MDSS_MDP_MAX_PREFILL_FETCH 25
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +053044
Siddhartha Agrawal8d690822013-01-28 12:18:58 -080045int restore_secure_cfg(uint32_t id);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -080046
47static int mdp_rev;
48
49void mdp_set_revision(int rev)
50{
51 mdp_rev = rev;
52}
53
54int mdp_get_revision()
55{
56 return mdp_rev;
57}
58
Dhaval Patel44014672015-03-26 10:58:32 -070059static inline bool is_software_pixel_ext_config_needed()
60{
61 return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV),
62 MDSS_MDP_HW_REV_107);
63}
64
65static inline bool has_fixed_size_smp()
66{
67 return MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV),
68 MDSS_MDP_HW_REV_107);
69}
70
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080071uint32_t mdss_mdp_intf_offset()
72{
73 uint32_t mdss_mdp_intf_off;
74 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
75
Padmanabhan Komanduru3908d172014-06-04 18:00:56 +053076 if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -070077 (mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
78 (mdss_mdp_rev == MDSS_MDP_HW_REV_112))
Padmanabhan Komanduru6f0e83d2014-03-22 01:12:28 +053079 mdss_mdp_intf_off = 0x59100;
80 else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102)
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080081 mdss_mdp_intf_off = 0;
Aravind Venkateswarand78d1592013-06-19 15:39:54 -070082 else
Chandan Uddarajuaab58512013-06-25 17:47:39 -070083 mdss_mdp_intf_off = 0xEC00;
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -080084
85 return mdss_mdp_intf_off;
86}
87
Jeevan Shriramd9c12652015-01-07 19:09:14 -080088static uint32_t mdss_mdp_get_ppb_offset()
89{
90 uint32_t mdss_mdp_ppb_off = 0;
91 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
92
93 /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */
94 if (mdss_mdp_rev == MDSS_MDP_HW_REV_108)
95 mdss_mdp_ppb_off = 0x1420;
96 else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
97 mdss_mdp_ppb_off = 0x1334;
98 else
99 dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n");
100
101 return mdss_mdp_ppb_off;
102}
103
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800104static uint32_t mdss_mdp_vbif_qos_remap_get_offset()
105{
106 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
107
108 if (mdss_mdp_rev == MDSS_MDP_HW_REV_110)
109 return 0xB0020;
Dhaval Patel225cde12015-05-04 11:14:12 -0700110 else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
111 return 0xB0000;
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800112 else
113 return 0xC8020;
114}
115
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800116void mdp_clk_gating_ctrl(void)
117{
Dhaval Patel225cde12015-05-04 11:14:12 -0700118 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
119 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107))
120 return;
121
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800122 writel(0x40000000, MDP_CLK_CTRL0);
123 udelay(20);
124 writel(0x40000040, MDP_CLK_CTRL0);
125 writel(0x40000000, MDP_CLK_CTRL1);
126 writel(0x00400000, MDP_CLK_CTRL3);
127 udelay(20);
128 writel(0x00404000, MDP_CLK_CTRL3);
129 writel(0x40000000, MDP_CLK_CTRL4);
130}
131
Jayant Shekhar07373922014-05-26 10:13:49 +0530132static void mdp_select_pipe_type(struct msm_panel_info *pinfo,
133 uint32_t *left_pipe, uint32_t *right_pipe)
134{
135 switch (pinfo->pipe_type) {
136 case MDSS_MDP_PIPE_TYPE_RGB:
137 *left_pipe = MDP_VP_0_RGB_0_BASE;
138 *right_pipe = MDP_VP_0_RGB_1_BASE;
139 break;
140 case MDSS_MDP_PIPE_TYPE_DMA:
141 *left_pipe = MDP_VP_0_DMA_0_BASE;
142 *right_pipe = MDP_VP_0_DMA_1_BASE;
143 break;
144 case MDSS_MDP_PIPE_TYPE_VIG:
145 default:
146 *left_pipe = MDP_VP_0_VIG_0_BASE;
147 *right_pipe = MDP_VP_0_VIG_1_BASE;
148 break;
149 }
150}
151
152static void mdss_mdp_set_flush(struct msm_panel_info *pinfo,
153 uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val)
154{
Padmanabhan Komandurudaebf6b2014-08-20 20:39:40 +0530155 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
Ujwal Patel190369c2014-11-06 14:18:55 -0800156 bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe &&
157 !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display;
Jayant Shekhar07373922014-05-26 10:13:49 +0530158 switch (pinfo->pipe_type) {
159 case MDSS_MDP_PIPE_TYPE_RGB:
Ujwal Patel190369c2014-11-06 14:18:55 -0800160 if (dual_pipe_single_ctl)
161 *ctl0_reg_val = 0x220D8;
162 else
163 *ctl0_reg_val = 0x22048;
Jayant Shekhar07373922014-05-26 10:13:49 +0530164 *ctl1_reg_val = 0x24090;
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800165
166 if (pinfo->lcdc.dst_split)
167 *ctl0_reg_val |= BIT(4);
Jayant Shekhar07373922014-05-26 10:13:49 +0530168 break;
169 case MDSS_MDP_PIPE_TYPE_DMA:
Ujwal Patel190369c2014-11-06 14:18:55 -0800170 if (dual_pipe_single_ctl)
171 *ctl0_reg_val = 0x238C0;
172 else
173 *ctl0_reg_val = 0x22840;
Jayant Shekhar07373922014-05-26 10:13:49 +0530174 *ctl1_reg_val = 0x25080;
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800175 if (pinfo->lcdc.dst_split)
176 *ctl0_reg_val |= BIT(12);
Jayant Shekhar07373922014-05-26 10:13:49 +0530177 break;
178 case MDSS_MDP_PIPE_TYPE_VIG:
179 default:
Ujwal Patel190369c2014-11-06 14:18:55 -0800180 if (dual_pipe_single_ctl)
181 *ctl0_reg_val = 0x220C3;
182 else
183 *ctl0_reg_val = 0x22041;
Jayant Shekhar07373922014-05-26 10:13:49 +0530184 *ctl1_reg_val = 0x24082;
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800185 if (pinfo->lcdc.dst_split)
186 *ctl0_reg_val |= BIT(1);
Jayant Shekhar07373922014-05-26 10:13:49 +0530187 break;
188 }
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530189 /* For targets from MDP v1.5, MDP INTF registers are double buffered */
Padmanabhan Komandurudaebf6b2014-08-20 20:39:40 +0530190 if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -0700191 (mdss_mdp_rev == MDSS_MDP_HW_REV_108) ||
192 (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800193 if (pinfo->dest == DISPLAY_2) {
194 *ctl0_reg_val |= BIT(31);
195 *ctl1_reg_val |= BIT(30);
196 } else {
Padmanabhan Komandurudaebf6b2014-08-20 20:39:40 +0530197 *ctl0_reg_val |= BIT(30);
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530198 *ctl1_reg_val |= BIT(31);
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800199 }
Chandan Uddaraju18a50372014-10-01 18:45:30 -0700200 } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800201 (mdss_mdp_rev == MDSS_MDP_HW_REV_109) ||
Dhaval Patel44014672015-03-26 10:58:32 -0700202 MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev,
203 MDSS_MDP_HW_REV_107) ||
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800204 (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800205 if (pinfo->dest == DISPLAY_2) {
206 *ctl0_reg_val |= BIT(29);
207 *ctl1_reg_val |= BIT(30);
208 } else {
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530209 *ctl0_reg_val |= BIT(30);
210 *ctl1_reg_val |= BIT(29);
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800211 }
Padmanabhan Komandurudaebf6b2014-08-20 20:39:40 +0530212 }
Jayant Shekhar07373922014-05-26 10:13:49 +0530213}
214
Jayant Shekhar32397f92014-03-27 13:30:41 +0530215static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700216 *pinfo, uint32_t pipe_base)
217{
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700218 uint32_t src_size, out_size, stride;
Siddhartha Agrawal6ef1e222013-06-12 18:24:58 -0700219 uint32_t fb_off = 0;
Prashant Nukala64eeff92014-07-11 07:35:34 +0530220 uint32_t flip_bits = 0;
Kuogee Hsieh31b4ff92014-10-22 14:55:42 -0700221 uint32_t src_xy = 0, dst_xy = 0;
222 uint32_t height, width;
223
224 height = fb->height - pinfo->border_top - pinfo->border_bottom;
225 width = fb->width - pinfo->border_left - pinfo->border_right;
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700226
227 /* write active region size*/
Kuogee Hsieh31b4ff92014-10-22 14:55:42 -0700228 src_size = (height << 16) + width;
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700229 out_size = src_size;
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700230 if (pinfo->lcdc.dual_pipe) {
Kuogee Hsieh31b4ff92014-10-22 14:55:42 -0700231 out_size = (height << 16) + (width / 2);
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700232 if ((pipe_base == MDP_VP_0_RGB_1_BASE) ||
233 (pipe_base == MDP_VP_0_DMA_1_BASE) ||
234 (pipe_base == MDP_VP_0_VIG_1_BASE))
Siddhartha Agrawal6ef1e222013-06-12 18:24:58 -0700235 fb_off = (pinfo->xres / 2);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700236 }
237
238 stride = (fb->stride * fb->bpp/8);
239
Kuogee Hsieh31b4ff92014-10-22 14:55:42 -0700240 if (fb_off == 0) { /* left */
241 dst_xy = (pinfo->border_top << 16) | pinfo->border_left;
242 src_xy = dst_xy;
243 } else { /* right */
244 dst_xy = (pinfo->border_top << 16);
245 src_xy = (pinfo->border_top << 16) | fb_off;
246 }
247
248 dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n",
249 __func__, out_size, fb_off, src_xy, dst_xy);
Veera Sundaram Sankarandb0b2bf2014-12-16 18:09:27 -0800250 writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700251 writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE);
252 writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE);
253 writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE);
254 writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE);
Kuogee Hsieh31b4ff92014-10-22 14:55:42 -0700255 writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY);
256 writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700257
258 /* Tight Packing 3bpp 0-Alpha 8-bit R B G */
259 writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT);
260 writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN);
Prashant Nukala64eeff92014-07-11 07:35:34 +0530261
262 /* bit(0) is set if hflip is required.
263 * bit(1) is set if vflip is required.
264 */
265 if (pinfo->orientation & 0x1)
266 flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR;
267 if (pinfo->orientation & 0x2)
268 flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD;
Dhaval Patel44014672015-03-26 10:58:32 -0700269
270 if (is_software_pixel_ext_config_needed()) {
271 flip_bits |= BIT(31);
272 writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ);
273 writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ);
274 writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ);
275 /* configure phase step 1 for all color components */
276 writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_X);
277 writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_Y);
278 writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_X);
279 writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_Y);
280 }
Prashant Nukala64eeff92014-07-11 07:35:34 +0530281 writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE);
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700282}
283
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700284static void mdss_vbif_setup()
285{
Aravind Venkateswarand78d1592013-06-19 15:39:54 -0700286 uint32_t mdp_hw_rev = readl(MDP_HW_REV);
Dhaval Patel225cde12015-05-04 11:14:12 -0700287 int access_secure = false;
288 if (!MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107))
289 access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700290
Padmanabhan Komanduru6f0e83d2014-03-22 01:12:28 +0530291 if (!access_secure) {
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700292 dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n");
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700293
Padmanabhan Komandurua874ae62014-05-14 14:59:50 +0530294 /* Force VBIF Clocks on, needed for 8974 and 8x26 */
295 if (mdp_hw_rev < MDSS_MDP_HW_REV_103)
Ujwal Patel00e19852013-12-18 20:40:38 -0800296 writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON);
297
298 /*
299 * Following configuration is needed because on some versions,
300 * recommended reset values are not stored.
301 */
302 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
303 MDSS_MDP_HW_REV_100)) {
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700304 writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
305 writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL );
306 writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
307 writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN);
308 writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO);
309 writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0);
310 writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1);
Ujwal Patel00e19852013-12-18 20:40:38 -0800311 } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Padmanabhan Komandurua874ae62014-05-14 14:59:50 +0530312 MDSS_MDP_HW_REV_101)) {
Aravind Venkateswarand78d1592013-06-19 15:39:54 -0700313 writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST);
Padmanabhan Komanduru6f0e83d2014-03-22 01:12:28 +0530314 writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700315 }
316 }
317}
318
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800319static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt,
320 uint32_t fixed_smp_cnt, uint32_t free_smp_offset)
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700321{
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800322 uint32_t i, j;
323 uint32_t reg_val = 0;
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700324
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800325 for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) {
326 /* max 3 MMB per register */
327 reg_val |= client_id << (((j++) % 3) * 8);
328 if ((j % 3) == 0) {
329 writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE +
330 free_smp_offset);
331 writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE +
332 free_smp_offset);
333 reg_val = 0;
334 free_smp_offset += 4;
335 }
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700336 }
337
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800338 if (j % 3) {
339 writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset);
340 writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset);
341 free_smp_offset += 4;
342 }
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700343
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800344 return free_smp_offset;
345}
346
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530347static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo,
348 uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id)
349{
350 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
351 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) ||
352 MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) ||
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -0700353 MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) ||
354 MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) {
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530355 switch (pinfo->pipe_type) {
356 case MDSS_MDP_PIPE_TYPE_RGB:
357 *left_sspp_client_id = 0x7; /* 7 */
358 *right_sspp_client_id = 0x11; /* 17 */
359 break;
360 case MDSS_MDP_PIPE_TYPE_DMA:
361 *left_sspp_client_id = 0x4; /* 4 */
362 *right_sspp_client_id = 0xD; /* 13 */
363 break;
364 case MDSS_MDP_PIPE_TYPE_VIG:
365 default:
366 *left_sspp_client_id = 0x1; /* 1 */
367 *right_sspp_client_id = 0x4; /* 4 */
368 break;
369 }
370 } else {
371 switch (pinfo->pipe_type) {
372 case MDSS_MDP_PIPE_TYPE_RGB:
373 *left_sspp_client_id = 0x10; /* 16 */
374 *right_sspp_client_id = 0x11; /* 17 */
375 break;
376 case MDSS_MDP_PIPE_TYPE_DMA:
377 *left_sspp_client_id = 0xA; /* 10 */
378 *right_sspp_client_id = 0xD; /* 13 */
379 break;
380 case MDSS_MDP_PIPE_TYPE_VIG:
381 default:
382 *left_sspp_client_id = 0x1; /* 1 */
383 *right_sspp_client_id = 0x4; /* 4 */
384 break;
385 }
386 }
387}
388
389static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo,
390 uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id)
391{
392 switch (pinfo->pipe_type) {
393 case MDSS_MDP_PIPE_TYPE_RGB:
394 *left_pipe_xin_id = 0x1; /* 1 */
395 *right_pipe_xin_id = 0x5; /* 5 */
396 break;
397 case MDSS_MDP_PIPE_TYPE_DMA:
398 *left_pipe_xin_id = 0x2; /* 2 */
399 *right_pipe_xin_id = 0xA; /* 10 */
400 break;
401 case MDSS_MDP_PIPE_TYPE_VIG:
402 default:
403 *left_pipe_xin_id = 0x0; /* 0 */
404 *right_pipe_xin_id = 0x4; /* 4 */
405 break;
406 }
407}
408
Jayant Shekhar32397f92014-03-27 13:30:41 +0530409static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe,
410 uint32_t right_pipe)
411
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800412{
Jayant Shekhar32397f92014-03-27 13:30:41 +0530413 uint32_t left_sspp_client_id, right_sspp_client_id;
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800414 uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH;
415 uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0;
416 uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
417
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -0700418 if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
419 (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) {
420 /* 8Kb per SMP on 8916/8952 */
Padmanabhan Komanduru6f0e83d2014-03-22 01:12:28 +0530421 smp_size = 8192;
Padmanabhan Komanduru3908d172014-06-04 18:00:56 +0530422 } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) {
423 /* 10Kb per SMP on 8939 */
424 smp_size = 10240;
Padmanabhan Komanduru6f0e83d2014-03-22 01:12:28 +0530425 } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) &&
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800426 (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) {
427 smp_size = 8192;
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800428 free_smp_offset = 0xC;
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530429 if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB)
430 fixed_smp_cnt = 2;
431 else
432 fixed_smp_cnt = 0;
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800433 }
434
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530435 mdp_select_pipe_client_id(pinfo,
436 &left_sspp_client_id, &right_sspp_client_id);
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800437
438 /* Each pipe driving half the screen */
439 if (pinfo->lcdc.dual_pipe)
440 xres /= 2;
441
442 /* bpp = bytes per pixel of input image */
443 smp_cnt = (xres * bpp * 2) + smp_size - 1;
444 smp_cnt /= smp_size;
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700445
446 if (smp_cnt > 4) {
447 dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__,
448 smp_cnt);
449 ASSERT(0); /* Max 4 SMPs can be allocated per client */
450 }
451
Jayant Shekhar32397f92014-03-27 13:30:41 +0530452 writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0);
453 writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1);
454 writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700455
456 if (pinfo->lcdc.dual_pipe) {
Jayant Shekhar32397f92014-03-27 13:30:41 +0530457 writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0);
458 writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1);
459 writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700460 }
461
Jayant Shekhar32397f92014-03-27 13:30:41 +0530462 free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt,
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800463 fixed_smp_cnt, free_smp_offset);
464 if (pinfo->lcdc.dual_pipe)
Jayant Shekhar32397f92014-03-27 13:30:41 +0530465 mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt,
Ujwal Patel1b52ca42013-12-18 23:32:36 -0800466 free_smp_offset);
Siddhartha Agrawal76574f82013-05-23 19:33:01 -0700467}
468
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800469static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800470{
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800471 uint32_t hsync_period, vsync_period;
472 uint32_t hsync_start_x, hsync_end_x;
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700473 uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700474 uint32_t adjust_xres = 0;
Dhaval Patel55c12172015-05-04 22:25:22 -0700475 uint32_t upper = 0, lower = 0;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700476
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800477 struct lcdc_panel_info *lcdc = NULL;
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700478 struct intf_timing_params itp = {0};
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800479
480 if (pinfo == NULL)
Veera Sundaram Sankarandb0b2bf2014-12-16 18:09:27 -0800481 return;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800482
483 lcdc = &(pinfo->lcdc);
484 if (lcdc == NULL)
Veera Sundaram Sankarandb0b2bf2014-12-16 18:09:27 -0800485 return;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800486
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700487 adjust_xres = pinfo->xres;
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700488 if (pinfo->lcdc.split_display) {
Siddhartha Agrawald359f142013-06-12 19:16:08 -0700489 adjust_xres /= 2;
Jayant Shekhar4e895d02015-03-30 12:30:14 +0530490 if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) {
Dhaval Patel55c12172015-05-04 22:25:22 -0700491 if (pinfo->lcdc.pipe_swap) {
492 lower |= BIT(4);
493 upper |= BIT(8);
494 } else {
495 lower |= BIT(8);
496 upper |= BIT(4);
497 }
498 writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
499 writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700500 writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
501 }
502 }
503
Jayant Shekhar4e895d02015-03-30 12:30:14 +0530504 if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800505 uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
506 writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
507 writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
Vineet Bajaj2f08a362014-07-24 20:50:42 +0530508 }
509
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700510 if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
511 pinfo->fbc.comp_ratio = 1;
512
513 itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
514 itp.yres = pinfo->yres;
515 itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
516 itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
517 itp.h_back_porch = pinfo->lcdc.h_back_porch;
518 itp.h_front_porch = pinfo->lcdc.h_front_porch;
519 itp.v_back_porch = pinfo->lcdc.v_back_porch;
520 itp.v_front_porch = pinfo->lcdc.v_front_porch;
521 itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
522 itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
523
524 itp.border_clr = pinfo->lcdc.border_clr;
525 itp.underflow_clr = pinfo->lcdc.underflow_clr;
526 itp.hsync_skew = pinfo->lcdc.hsync_skew;
527
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700528 hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
529 itp.width + itp.h_front_porch;
530
531 vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
532 itp.height + itp.v_front_porch;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800533
534 hsync_start_x =
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700535 itp.hsync_pulse_width +
536 itp.h_back_porch;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800537 hsync_end_x =
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700538 hsync_period - itp.h_front_porch - 1;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800539
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700540 display_vstart = (itp.vsync_pulse_width +
541 itp.v_back_porch)
542 * hsync_period + itp.hsync_skew;
543 display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
544 + itp.hsync_skew - 1;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800545
Jayant Shekhar4e895d02015-03-30 12:30:14 +0530546 if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700547 display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
548 display_vend -= itp.h_front_porch;
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300549 }
550
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700551 hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800552 display_hctl = (hsync_end_x << 16) | hsync_start_x;
553
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800554 writel(hsync_ctl, MDP_HSYNC_CTL + intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700555 writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800556 intf_base);
557 writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base);
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700558 writel(itp.vsync_pulse_width*hsync_period,
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700559 MDP_VSYNC_PULSE_WIDTH_F0 +
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800560 intf_base);
561 writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base);
562 writel(display_hctl, MDP_DISPLAY_HCTL + intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700563 writel(display_vstart, MDP_DISPLAY_V_START_F0 +
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800564 intf_base);
565 writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700566 writel(display_vend, MDP_DISPLAY_V_END_F0 +
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800567 intf_base);
568 writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base);
569 writel(0x00, MDP_ACTIVE_HCTL + intf_base);
570 writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base);
571 writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base);
572 writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base);
573 writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base);
574 writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700575
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800576 if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */
577 writel(0x212A, MDP_PANEL_FORMAT + intf_base);
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300578 else
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800579 writel(0x213F, MDP_PANEL_FORMAT + intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700580}
581
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800582static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530583 uint32_t intf_base)
584{
585 uint32_t mdp_hw_rev = readl(MDP_HW_REV);
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800586 uint32_t v_total, h_total, fetch_start, vfp_start;
587 uint32_t prefetch_avail, prefetch_needed;
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530588 uint32_t adjust_xres = 0;
Huaibin Yang617cbb02015-01-14 14:17:07 -0800589 uint32_t fetch_enable = BIT(31);
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530590
591 struct lcdc_panel_info *lcdc = NULL;
592
593 if (pinfo == NULL)
594 return;
595
596 lcdc = &(pinfo->lcdc);
597 if (lcdc == NULL)
598 return;
599
600 /*
601 * MDP programmable fetch is for MDP with rev >= 1.05.
602 * Programmable fetch is not needed if vertical back porch
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800603 * plus vertical puls width is >= 25.
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530604 */
605 if (mdp_hw_rev < MDSS_MDP_HW_REV_105 ||
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800606 (lcdc->v_back_porch + lcdc->v_pulse_width) >=
607 MDSS_MDP_MAX_PREFILL_FETCH)
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530608 return;
609
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530610 adjust_xres = pinfo->xres;
611 if (pinfo->lcdc.split_display)
612 adjust_xres /= 2;
613
Jeevan Shriram44667292015-03-17 17:28:39 -0700614 if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio)
615 adjust_xres /= pinfo->fbc.comp_ratio;
616
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530617 /*
618 * Fetch should always be outside the active lines. If the fetching
619 * is programmed within active region, hardware behavior is unknown.
620 */
621 v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres +
622 lcdc->v_front_porch;
623 h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres +
624 lcdc->h_front_porch;
625 vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres;
626
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800627 prefetch_avail = v_total - vfp_start;
628 prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH -
629 lcdc->v_back_porch -
630 lcdc->v_pulse_width;
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530631
632 /*
633 * In some cases, vertical front porch is too high. In such cases limit
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800634 * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch.
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530635 */
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800636 if (prefetch_avail > prefetch_needed)
637 prefetch_avail = prefetch_needed;
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530638
Ingrid Gallardo0a6cebb2015-02-13 17:18:26 -0800639 fetch_start = (v_total - prefetch_avail) * h_total + 1;
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530640
Huaibin Yang617cbb02015-01-14 14:17:07 -0800641 if (pinfo->dfps.panel_dfps.enabled)
642 fetch_enable |= BIT(23);
643
644 writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base);
645 writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base);
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530646}
647
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700648void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
649 *pinfo)
650{
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530651 uint32_t mdp_rgb_size, height, width;
Jayant Shekhar07373922014-05-26 10:13:49 +0530652 uint32_t left_staging_level, right_staging_level;
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700653
Dhaval Patel0a9ab812013-10-25 10:25:06 -0700654 height = fb->height;
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700655 width = fb->width;
656
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800657 if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700658 width /= 2;
659
660 /* write active region size*/
661 mdp_rgb_size = (height << 16) | width;
662
663 writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE);
664 writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE);
665 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP);
666 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA);
667 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP);
668 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA);
669 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP);
670 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA);
671 writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP);
672 writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA);
673
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530674 switch (pinfo->pipe_type) {
675 case MDSS_MDP_PIPE_TYPE_RGB:
Jayant Shekhar07373922014-05-26 10:13:49 +0530676 left_staging_level = 0x0000200;
677 right_staging_level = 0x1000;
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530678 break;
679 case MDSS_MDP_PIPE_TYPE_DMA:
Jayant Shekhar07373922014-05-26 10:13:49 +0530680 left_staging_level = 0x0040000;
681 right_staging_level = 0x200000;
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530682 break;
683 case MDSS_MDP_PIPE_TYPE_VIG:
684 default:
Jayant Shekhar07373922014-05-26 10:13:49 +0530685 left_staging_level = 0x1;
686 right_staging_level = 0x8;
Jayant Shekhar03e1a222014-05-22 11:03:53 +0530687 break;
688 }
689
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800690 /*
691 * When ping-pong split is enabled and two pipes are used,
692 * both the pipes need to be staged on the same layer mixer.
693 */
694 if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split)
695 left_staging_level |= right_staging_level;
696
Jayant Shekhar07373922014-05-26 10:13:49 +0530697 /* Base layer for layer mixer 0 */
698 writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0);
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700699
Jeevan Shriramd9c12652015-01-07 19:09:14 -0800700 if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) {
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700701 writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE);
702 writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE);
703 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP);
704 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA);
705 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP);
706 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA);
707 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP);
708 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA);
709 writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP);
710 writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA);
711
Jayant Shekhar07373922014-05-26 10:13:49 +0530712 /* Base layer for layer mixer 1 */
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700713 if (pinfo->lcdc.split_display)
Jayant Shekhar07373922014-05-26 10:13:49 +0530714 writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1);
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700715 else
Jayant Shekhar07373922014-05-26 10:13:49 +0530716 writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1);
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700717 }
718}
719
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700720void mdss_fbc_cfg(struct msm_panel_info *pinfo)
721{
722 uint32_t mode = 0;
723 uint32_t budget_ctl = 0;
724 uint32_t lossy_mode = 0;
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700725 struct fbc_panel_info *fbc;
Jeevan Shriram1b07e372014-11-30 22:03:50 -0800726 uint32_t enc_mode, width;
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700727
728 fbc = &pinfo->fbc;
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700729
730 if (!pinfo->fbc.enabled)
731 return;
732
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700733 /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */
734 enc_mode = (fbc->comp_ratio == 2) ? 0 : 1;
735
Jeevan Shriram1b07e372014-11-30 22:03:50 -0800736 width = pinfo->xres;
737 if (enc_mode)
738 width = (pinfo->xres/fbc->comp_ratio);
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700739
Jeevan Shriram1b07e372014-11-30 22:03:50 -0800740 if (pinfo->mipi.dual_dsi)
741 width /= 2;
742
743 mode = ((width) << 16) | ((fbc->slice_height) << 11) |
744 ((fbc->pred_mode) << 10) | (enc_mode) << 9 |
745 ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) |
746 ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) |
747 ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1;
748
749 dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \
750 comp_mode %d, qerr_enable = %d, cd_bias = %d\n",
751 width, fbc->slice_height, fbc->pred_mode, enc_mode,
752 fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias);
Veera Sundaram Sankarandb0b2bf2014-12-16 18:09:27 -0800753 dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n",
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700754 fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable);
755
756 budget_ctl = ((fbc->line_x_budget) << 12) |
757 ((fbc->block_x_budget) << 8) | fbc->block_budget;
758
Jeevan Shriram1b07e372014-11-30 22:03:50 -0800759 lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) |
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700760 ((fbc->lossy_mode_thd) << 8) |
761 ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx;
762
Jeevan Shriram1b07e372014-11-30 22:03:50 -0800763 dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n",
764 mode, budget_ctl, lossy_mode);
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700765 writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE);
766 writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
767 writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
768
769 if (pinfo->mipi.dual_dsi) {
770 writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE);
771 writel(budget_ctl, MDP_PP_1_BASE +
772 MDSS_MDP_REG_PP_FBC_BUDGET_CTL);
773 writel(lossy_mode, MDP_PP_1_BASE +
774 MDSS_MDP_REG_PP_FBC_LOSSY_MODE);
775 }
776}
777
Dhaval Patel069d0af2014-01-03 16:55:15 -0800778void mdss_qos_remapper_setup(void)
779{
780 uint32_t mdp_hw_rev = readl(MDP_HW_REV);
781 uint32_t map;
782
783 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) ||
784 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
785 MDSS_MDP_HW_REV_102))
786 map = 0xE9;
787 else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Padmanabhan Komandurua874ae62014-05-14 14:59:50 +0530788 MDSS_MDP_HW_REV_101))
Dhaval Patel069d0af2014-01-03 16:55:15 -0800789 map = 0xA5;
790 else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Padmanabhan Komanduru3908d172014-06-04 18:00:56 +0530791 MDSS_MDP_HW_REV_106) ||
792 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -0700793 MDSS_MDP_HW_REV_108) ||
794 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
795 MDSS_MDP_HW_REV_112))
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530796 map = 0xE4;
Padmanabhan Komandurua874ae62014-05-14 14:59:50 +0530797 else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Chandan Uddaraju18a50372014-10-01 18:45:30 -0700798 MDSS_MDP_HW_REV_105) ||
799 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800800 MDSS_MDP_HW_REV_109) ||
801 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Dhaval Patel44014672015-03-26 10:58:32 -0700802 MDSS_MDP_HW_REV_107) ||
803 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800804 MDSS_MDP_HW_REV_110))
Ingrid Gallardo998ea442014-09-10 17:22:08 -0700805 map = 0xA4;
806 else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev,
807 MDSS_MDP_HW_REV_103))
Dhaval Patel069d0af2014-01-03 16:55:15 -0800808 map = 0xFA;
809 else
810 return;
811
812 writel(map, MDP_QOS_REMAPPER_CLASS_0);
813}
814
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530815void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo)
816{
817 uint32_t mask, reg_val, i;
818 uint32_t left_pipe_xin_id, right_pipe_xin_id;
819 uint32_t mdp_hw_rev = readl(MDP_HW_REV);
820 uint32_t vbif_qos[4] = {0, 0, 0, 0};
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800821 uint32_t vbif_offset;
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530822
823 mdp_select_pipe_xin_id(pinfo,
824 &left_pipe_xin_id, &right_pipe_xin_id);
825
826 if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) ||
Padmanabhan Komandurufdb56832015-04-09 21:08:28 -0700827 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) ||
828 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) {
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530829 vbif_qos[0] = 2;
830 vbif_qos[1] = 2;
831 vbif_qos[2] = 2;
832 vbif_qos[3] = 2;
Chandan Uddaraju18a50372014-10-01 18:45:30 -0700833 } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) ||
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800834 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) ||
Dhaval Patel44014672015-03-26 10:58:32 -0700835 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) ||
Jeevan Shriram47c936d2014-12-19 11:50:13 -0800836 MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) {
Ingrid Gallardo998ea442014-09-10 17:22:08 -0700837 vbif_qos[0] = 1;
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530838 vbif_qos[1] = 2;
839 vbif_qos[2] = 2;
Ingrid Gallardo998ea442014-09-10 17:22:08 -0700840 vbif_qos[3] = 2;
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530841 } else {
842 return;
843 }
844
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800845 vbif_offset = mdss_mdp_vbif_qos_remap_get_offset();
846
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530847 for (i = 0; i < 4; i++) {
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800848 /* VBIF_VBIF_QOS_REMAP_00 */
849 reg_val = readl(REG_MDP(vbif_offset) + i*4);
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530850 mask = 0x3 << (left_pipe_xin_id * 2);
851 reg_val &= ~(mask);
852 reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2);
853
854 if (pinfo->lcdc.dual_pipe) {
855 mask = 0x3 << (right_pipe_xin_id * 2);
856 reg_val &= ~(mask);
857 reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2);
858 }
Jeevan Shriramd8f99a32015-01-07 19:07:05 -0800859 writel(reg_val, REG_MDP(vbif_offset) + i*4);
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530860 }
861}
862
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700863static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo,
864 int is_main_ctl)
865{
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800866 uint32_t mctl_intf_sel;
867 uint32_t sctl_intf_sel;
868
869 if ((pinfo->dest == DISPLAY_2) ||
870 ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) {
871 mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
872 sctl_intf_sel = BIT(5); /* Interface 1 */
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700873 } else {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800874 mctl_intf_sel = BIT(5); /* Interface 1 */
875 sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700876 }
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800877 dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__,
878 (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1",
879 (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1");
880 return is_main_ctl ? mctl_intf_sel : sctl_intf_sel;
881}
882
883static void mdp_set_intf_base(struct msm_panel_info *pinfo,
884 uint32_t *intf_sel, uint32_t *sintf_sel,
885 uint32_t *intf_base, uint32_t *sintf_base)
886{
887 if (pinfo->dest == DISPLAY_2) {
888 *intf_sel = BIT(16);
889 *sintf_sel = BIT(8);
890 *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
891 *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
892 } else {
893 *intf_sel = BIT(8);
894 *sintf_sel = BIT(16);
895 *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
896 *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
897 }
898 dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__,
899 (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1",
900 (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2");
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700901}
902
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700903int mdp_dsi_video_config(struct msm_panel_info *pinfo,
904 struct fbcon_config *fb)
905{
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800906 uint32_t intf_sel, sintf_sel;
907 uint32_t intf_base, sintf_base;
Jayant Shekhar32397f92014-03-27 13:30:41 +0530908 uint32_t left_pipe, right_pipe;
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700909 uint32_t reg;
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700910
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800911 mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
912
913 mdss_intf_tg_setup(pinfo, intf_base);
914 mdss_intf_fetch_start_config(pinfo, intf_base);
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700915
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530916 if (pinfo->mipi.dual_dsi) {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800917 mdss_intf_tg_setup(pinfo, sintf_base);
918 mdss_intf_fetch_start_config(pinfo, sintf_base);
Padmanabhan Komanduru9f546ab2014-09-10 19:56:30 +0530919 }
Siddhartha Agrawal1a87c5d2013-03-06 19:07:53 -0800920
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800921 mdp_clk_gating_ctrl();
922
Jayant Shekhar07373922014-05-26 10:13:49 +0530923 mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -0700924 mdss_vbif_setup();
Dhaval Patel44014672015-03-26 10:58:32 -0700925 if (!has_fixed_size_smp())
926 mdss_smp_setup(pinfo, left_pipe, right_pipe);
Siddhartha Agrawalb1b5a1f2013-04-17 19:53:41 -0700927
Dhaval Patel069d0af2014-01-03 16:55:15 -0800928 mdss_qos_remapper_setup();
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530929 mdss_vbif_qos_remapper_setup(pinfo);
Siddhartha Agrawalb1b5a1f2013-04-17 19:53:41 -0700930
Jayant Shekhar32397f92014-03-27 13:30:41 +0530931 mdss_source_pipe_config(fb, pinfo, left_pipe);
932
Siddhartha Agrawald3893392013-06-11 15:32:19 -0700933 if (pinfo->lcdc.dual_pipe)
Jayant Shekhar32397f92014-03-27 13:30:41 +0530934 mdss_source_pipe_config(fb, pinfo, right_pipe);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800935
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700936 mdss_layer_mixer_setup(fb, pinfo);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800937
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700938 reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
Ujwal Patel190369c2014-11-06 14:18:55 -0800939
940 /* enable 3D mux for dual_pipe but single interface config */
941 if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi &&
942 !pinfo->lcdc.split_display)
943 reg |= BIT(19) | BIT(20);
944
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -0700945 writel(reg, MDP_CTL_0_BASE + CTL_TOP);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800946
Vineet Bajaj2f08a362014-07-24 20:50:42 +0530947 /*If dst_split is enabled only intf 2 needs to be enabled.
948 CTL_1 path should not be set since CTL_0 itself is going
949 to split after DSPP block*/
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -0700950 if (pinfo->fbc.enabled)
951 mdss_fbc_cfg(pinfo);
Vineet Bajaj2f08a362014-07-24 20:50:42 +0530952
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700953 if (pinfo->mipi.dual_dsi) {
Vineet Bajaj2f08a362014-07-24 20:50:42 +0530954 if (!pinfo->lcdc.dst_split) {
955 reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
956 writel(reg, MDP_CTL_1_BASE + CTL_TOP);
957 }
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -0800958 intf_sel |= sintf_sel; /* INTF 2 enable */
Siddhartha Agrawald32ba682013-06-18 12:37:41 -0700959 }
Siddhartha Agrawalf0b41a22013-05-23 20:32:20 -0700960
961 writel(intf_sel, MDP_DISP_INTF_SEL);
962
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -0800963 writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
964 writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
965 writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
966
967 return 0;
968}
969
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300970int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
971{
Jayant Shekhar32397f92014-03-27 13:30:41 +0530972 uint32_t left_pipe, right_pipe;
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300973
974 mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
975
Jayant Shekhar07373922014-05-26 10:13:49 +0530976 mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300977 mdp_clk_gating_ctrl();
978
979 mdss_vbif_setup();
Jayant Shekhar32397f92014-03-27 13:30:41 +0530980 mdss_smp_setup(pinfo, left_pipe, right_pipe);
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300981
Dhaval Patel069d0af2014-01-03 16:55:15 -0800982 mdss_qos_remapper_setup();
Jayant Shekhar2db7dc52014-08-21 10:43:30 +0530983 mdss_vbif_qos_remapper_setup(pinfo);
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300984
Jayant Shekhar32397f92014-03-27 13:30:41 +0530985 mdss_source_pipe_config(fb, pinfo, left_pipe);
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700986 if (pinfo->lcdc.dual_pipe)
Jayant Shekhar32397f92014-03-27 13:30:41 +0530987 mdss_source_pipe_config(fb, pinfo, right_pipe);
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300988
989 mdss_layer_mixer_setup(fb, pinfo);
990
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -0700991 if (pinfo->lcdc.dual_pipe)
992 writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP);
993 else
994 writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP);
995
Asaf Pensoafb8eb72013-07-07 18:17:59 +0300996 writel(0x9, MDP_DISP_INTF_SEL);
997 writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
998 writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
999 writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
1000
1001 return 0;
1002}
1003
Ajay Singh Parmar243d82b2014-07-23 23:01:44 -07001004int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
Ajay Singh Parmar63c18502014-07-23 23:37:19 -07001005{
Ajay Singh Parmar63c18502014-07-23 23:37:19 -07001006 uint32_t left_pipe, right_pipe;
Casey Piper77f69c52015-03-20 15:55:12 -07001007 dprintf(SPEW, "ENTER: %s\n", __func__);
Ajay Singh Parmar63c18502014-07-23 23:37:19 -07001008
Casey Piper77f69c52015-03-20 15:55:12 -07001009 mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset());
1010 pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
Ajay Singh Parmar63c18502014-07-23 23:37:19 -07001011 mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
1012
1013 mdp_clk_gating_ctrl();
1014 mdss_vbif_setup();
1015
1016 mdss_smp_setup(pinfo, left_pipe, right_pipe);
1017
1018 mdss_qos_remapper_setup();
1019
1020 mdss_source_pipe_config(fb, pinfo, left_pipe);
1021 if (pinfo->lcdc.dual_pipe)
1022 mdss_source_pipe_config(fb, pinfo, right_pipe);
1023
1024 mdss_layer_mixer_setup(fb, pinfo);
1025
1026 if (pinfo->lcdc.dual_pipe)
1027 writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
1028 else
1029 writel(0x40, MDP_CTL_0_BASE + CTL_TOP);
1030
1031 writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
1032 writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
1033 writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
1034 writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
1035
1036 return 0;
1037}
1038
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001039int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
1040 struct fbcon_config *fb)
1041{
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001042 uint32_t intf_sel, sintf_sel;
1043 uint32_t intf_base, sintf_base;
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -07001044 uint32_t reg;
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001045 int ret = NO_ERROR;
Jayant Shekhar32397f92014-03-27 13:30:41 +05301046 uint32_t left_pipe, right_pipe;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001047
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001048 struct lcdc_panel_info *lcdc = NULL;
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001049
1050 if (pinfo == NULL)
1051 return ERR_INVALID_ARGS;
1052
1053 lcdc = &(pinfo->lcdc);
1054 if (lcdc == NULL)
1055 return ERR_INVALID_ARGS;
1056
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001057 mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
1058
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001059 if (pinfo->lcdc.split_display) {
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -07001060 reg = BIT(1); /* Command mode */
Jeevan Shriramd9c12652015-01-07 19:09:14 -08001061 if (pinfo->lcdc.dst_split)
1062 reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -07001063 if (pinfo->lcdc.pipe_swap)
1064 reg |= BIT(4); /* Use intf2 as trigger */
1065 else
1066 reg |= BIT(8); /* Use intf1 as trigger */
1067 writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
1068 writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001069 writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
1070 }
1071
Padmanabhan Komanduru4677a122014-09-26 16:55:05 +05301072 if (pinfo->lcdc.dst_split) {
Jeevan Shriramd9c12652015-01-07 19:09:14 -08001073 uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
1074 writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
1075 writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
Padmanabhan Komanduru4677a122014-09-26 16:55:05 +05301076 }
1077
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001078 mdp_clk_gating_ctrl();
1079
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001080 if (pinfo->mipi.dual_dsi)
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001081 intf_sel |= sintf_sel; /* INTF 2 enable */
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001082
1083 writel(intf_sel, MDP_DISP_INTF_SEL);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001084
Jayant Shekhar07373922014-05-26 10:13:49 +05301085 mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
Siddhartha Agrawal703153e2013-05-23 19:35:36 -07001086 mdss_vbif_setup();
Jayant Shekhar32397f92014-03-27 13:30:41 +05301087 mdss_smp_setup(pinfo, left_pipe, right_pipe);
Dhaval Patel069d0af2014-01-03 16:55:15 -08001088 mdss_qos_remapper_setup();
Jayant Shekhar2db7dc52014-08-21 10:43:30 +05301089 mdss_vbif_qos_remapper_setup(pinfo);
Dhaval Patel069d0af2014-01-03 16:55:15 -08001090
Jayant Shekhar32397f92014-03-27 13:30:41 +05301091 mdss_source_pipe_config(fb, pinfo, left_pipe);
1092
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001093 if (pinfo->lcdc.dual_pipe)
Jayant Shekhar32397f92014-03-27 13:30:41 +05301094 mdss_source_pipe_config(fb, pinfo, right_pipe);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001095
Siddhartha Agrawald32ba682013-06-18 12:37:41 -07001096 mdss_layer_mixer_setup(fb, pinfo);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001097
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001098 writel(0x213F, MDP_PANEL_FORMAT + intf_base);
Aravind Venkateswaran5c1c80f2014-06-27 17:20:25 -07001099 reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
1100 writel(reg, MDP_CTL_0_BASE + CTL_TOP);
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001101
Siddhartha Agrawalfe64dcb2014-10-07 12:41:01 -07001102 if (pinfo->fbc.enabled)
1103 mdss_fbc_cfg(pinfo);
1104
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001105 if (pinfo->mipi.dual_dsi) {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001106 writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
Padmanabhan Komanduru4677a122014-09-26 16:55:05 +05301107 if (!pinfo->lcdc.dst_split) {
1108 reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
1109 writel(reg, MDP_CTL_1_BASE + CTL_TOP);
1110 }
Dhaval Patel6ff630b2014-01-03 17:29:22 -08001111 }
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001112
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001113 return ret;
1114}
1115
Jayant Shekhar32397f92014-03-27 13:30:41 +05301116int mdp_dsi_video_on(struct msm_panel_info *pinfo)
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001117{
Jayant Shekhar03e1a222014-05-22 11:03:53 +05301118 uint32_t ctl0_reg_val, ctl1_reg_val;
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001119 uint32_t timing_engine_en;
1120
Jayant Shekhar07373922014-05-26 10:13:49 +05301121 mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
Jayant Shekhar03e1a222014-05-22 11:03:53 +05301122 writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
Jeevan Shriramd9c12652015-01-07 19:09:14 -08001123 if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
1124 writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001125
1126 if (pinfo->dest == DISPLAY_1)
1127 timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
1128 else
1129 timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
1130 writel(0x01, timing_engine_en + mdss_mdp_intf_offset());
Jayant Shekhar32397f92014-03-27 13:30:41 +05301131
1132 return NO_ERROR;
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001133}
1134
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001135int mdp_dsi_video_off(struct msm_panel_info *pinfo)
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001136{
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001137 uint32_t timing_engine_en;
1138
1139 if (pinfo->dest == DISPLAY_1)
1140 timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
1141 else
1142 timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
1143
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001144 if(!target_cont_splash_screen())
1145 {
Aravind Venkateswaranfec354c2014-12-04 18:10:14 -08001146 writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset());
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001147 mdelay(60);
1148 /* Ping-Pong done Tear Check Read/Write */
1149 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
1150 writel(0xFF777713, MDP_INTR_CLEAR);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001151 }
1152
Siddhartha Agrawal6a598222013-02-17 18:33:27 -08001153 writel(0x00000000, MDP_INTR_EN);
1154
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001155 return NO_ERROR;
1156}
1157
1158int mdp_dsi_cmd_off()
1159{
Siddhartha Agrawal7dc3aa92013-04-21 16:04:26 -07001160 if(!target_cont_splash_screen())
1161 {
1162 /* Ping-Pong done Tear Check Read/Write */
1163 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
1164 writel(0xFF777713, MDP_INTR_CLEAR);
1165 }
1166 writel(0x00000000, MDP_INTR_EN);
1167
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001168 return NO_ERROR;
1169}
1170
Jayant Shekhar32397f92014-03-27 13:30:41 +05301171int mdp_dma_on(struct msm_panel_info *pinfo)
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001172{
Jayant Shekhar03e1a222014-05-22 11:03:53 +05301173 uint32_t ctl0_reg_val, ctl1_reg_val;
Jayant Shekhar07373922014-05-26 10:13:49 +05301174 mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
Jayant Shekhar03e1a222014-05-22 11:03:53 +05301175 writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
Jeevan Shriramd9c12652015-01-07 19:09:14 -08001176 if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
1177 writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
1178
Siddhartha Agrawald32ba682013-06-18 12:37:41 -07001179 writel(0x01, MDP_CTL_0_BASE + CTL_START);
Siddhartha Agrawal7e2e2152013-01-23 17:06:58 -08001180 return NO_ERROR;
1181}
1182
Jayant Shekhar32397f92014-03-27 13:30:41 +05301183int mdp_edp_on(struct msm_panel_info *pinfo)
Asaf Pensoafb8eb72013-07-07 18:17:59 +03001184{
Jayant Shekhar07373922014-05-26 10:13:49 +05301185 uint32_t ctl0_reg_val, ctl1_reg_val;
1186 mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
Jayant Shekhar03e1a222014-05-22 11:03:53 +05301187 writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
Asaf Pensoafb8eb72013-07-07 18:17:59 +03001188 writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
1189 return NO_ERROR;
1190}
1191
Ajay Singh Parmar243d82b2014-07-23 23:01:44 -07001192int mdss_hdmi_on(struct msm_panel_info *pinfo)
Ajay Singh Parmar63c18502014-07-23 23:37:19 -07001193{
1194 uint32_t ctl0_reg_val, ctl1_reg_val;
1195
1196 mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
1197 writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
1198
1199 writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
1200
1201 return NO_ERROR;
1202}
1203
Asaf Pensoafb8eb72013-07-07 18:17:59 +03001204int mdp_edp_off(void)
1205{
1206 if (!target_cont_splash_screen()) {
1207
1208 writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN +
1209 mdss_mdp_intf_offset());
1210 mdelay(60);
1211 /* Ping-Pong done Tear Check Read/Write */
1212 /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
1213 writel(0xFF777713, MDP_INTR_CLEAR);
1214 writel(0x00000000, MDP_INTR_EN);
1215 }
1216
Kuogee Hsiehad69c3c2013-08-01 14:34:29 -07001217 writel(0x00000000, MDP_INTR_EN);
1218
Asaf Pensoafb8eb72013-07-07 18:17:59 +03001219 return NO_ERROR;
1220}