Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 36 | /* |
| 37 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 38 | * over cache flushing. |
| 39 | */ |
| 40 | struct pipe_control { |
| 41 | struct drm_i915_gem_object *obj; |
| 42 | volatile u32 *cpu_page; |
| 43 | u32 gtt_offset; |
| 44 | }; |
| 45 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 46 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 47 | { |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 48 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 49 | if (space < 0) |
| 50 | space += ring->size; |
| 51 | return space; |
| 52 | } |
| 53 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 54 | static int |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
| 56 | u32 invalidate_domains, |
| 57 | u32 flush_domains) |
| 58 | { |
| 59 | u32 cmd; |
| 60 | int ret; |
| 61 | |
| 62 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 64 | cmd |= MI_NO_WRITE_FLUSH; |
| 65 | |
| 66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 67 | cmd |= MI_READ_FLUSH; |
| 68 | |
| 69 | ret = intel_ring_begin(ring, 2); |
| 70 | if (ret) |
| 71 | return ret; |
| 72 | |
| 73 | intel_ring_emit(ring, cmd); |
| 74 | intel_ring_emit(ring, MI_NOOP); |
| 75 | intel_ring_advance(ring); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int |
| 81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, |
| 82 | u32 invalidate_domains, |
| 83 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 84 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 85 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 86 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 87 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 88 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 89 | /* |
| 90 | * read/write caches: |
| 91 | * |
| 92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 94 | * also flushed at 2d versus 3d pipeline switches. |
| 95 | * |
| 96 | * read-only caches: |
| 97 | * |
| 98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 99 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 100 | * |
| 101 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 102 | * |
| 103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 104 | * invalidated when MI_EXE_FLUSH is set. |
| 105 | * |
| 106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 107 | * invalidated with every MI_FLUSH. |
| 108 | * |
| 109 | * TLBs: |
| 110 | * |
| 111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 114 | * are flushed at any MI_FLUSH. |
| 115 | */ |
| 116 | |
| 117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 121 | cmd |= MI_EXE_FLUSH; |
| 122 | |
| 123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 124 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 125 | cmd |= MI_INVALIDATE_ISP; |
| 126 | |
| 127 | ret = intel_ring_begin(ring, 2); |
| 128 | if (ret) |
| 129 | return ret; |
| 130 | |
| 131 | intel_ring_emit(ring, cmd); |
| 132 | intel_ring_emit(ring, MI_NOOP); |
| 133 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 134 | |
| 135 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 136 | } |
| 137 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 138 | /** |
| 139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 140 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 142 | * |
| 143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 144 | * produced by non-pipelined state commands), software needs to first |
| 145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 146 | * 0. |
| 147 | * |
| 148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 150 | * |
| 151 | * And the workaround for these two requires this workaround first: |
| 152 | * |
| 153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 154 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 155 | * flushes. |
| 156 | * |
| 157 | * And this last workaround is tricky because of the requirements on |
| 158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 159 | * volume 2 part 1: |
| 160 | * |
| 161 | * "1 of the following must also be set: |
| 162 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 163 | * - Depth Cache Flush Enable ([0] of DW1) |
| 164 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 165 | * - Depth Stall ([13] of DW1) |
| 166 | * - Post-Sync Operation ([13] of DW1) |
| 167 | * - Notify Enable ([8] of DW1)" |
| 168 | * |
| 169 | * The cache flushes require the workaround flush that triggered this |
| 170 | * one, so we can't use it. Depth stall would trigger the same. |
| 171 | * Post-sync nonzero is what triggered this second workaround, so we |
| 172 | * can't use that one either. Notify enable is IRQs, which aren't |
| 173 | * really our business. That leaves only stall at scoreboard. |
| 174 | */ |
| 175 | static int |
| 176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 177 | { |
| 178 | struct pipe_control *pc = ring->private; |
| 179 | u32 scratch_addr = pc->gtt_offset + 128; |
| 180 | int ret; |
| 181 | |
| 182 | |
| 183 | ret = intel_ring_begin(ring, 6); |
| 184 | if (ret) |
| 185 | return ret; |
| 186 | |
| 187 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 188 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 189 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 190 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 191 | intel_ring_emit(ring, 0); /* low dword */ |
| 192 | intel_ring_emit(ring, 0); /* high dword */ |
| 193 | intel_ring_emit(ring, MI_NOOP); |
| 194 | intel_ring_advance(ring); |
| 195 | |
| 196 | ret = intel_ring_begin(ring, 6); |
| 197 | if (ret) |
| 198 | return ret; |
| 199 | |
| 200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 201 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 202 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 203 | intel_ring_emit(ring, 0); |
| 204 | intel_ring_emit(ring, 0); |
| 205 | intel_ring_emit(ring, MI_NOOP); |
| 206 | intel_ring_advance(ring); |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | static int |
| 212 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 213 | u32 invalidate_domains, u32 flush_domains) |
| 214 | { |
| 215 | u32 flags = 0; |
| 216 | struct pipe_control *pc = ring->private; |
| 217 | u32 scratch_addr = pc->gtt_offset + 128; |
| 218 | int ret; |
| 219 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 221 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 222 | if (ret) |
| 223 | return ret; |
| 224 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 225 | /* Just flush everything. Experiments have shown that reducing the |
| 226 | * number of bits based on the write domains has little performance |
| 227 | * impact. |
| 228 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 229 | if (flush_domains) { |
| 230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 231 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 232 | /* |
| 233 | * Ensure that any following seqno writes only happen |
| 234 | * when the render cache is indeed flushed. |
| 235 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 236 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 237 | } |
| 238 | if (invalidate_domains) { |
| 239 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 240 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 241 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 242 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 243 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 244 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 245 | /* |
| 246 | * TLB invalidate requires a post-sync write. |
| 247 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 248 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 249 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 250 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 251 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 252 | if (ret) |
| 253 | return ret; |
| 254 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 255 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 256 | intel_ring_emit(ring, flags); |
| 257 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 258 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 259 | intel_ring_advance(ring); |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 264 | static int |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 265 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) |
| 266 | { |
| 267 | int ret; |
| 268 | |
| 269 | ret = intel_ring_begin(ring, 4); |
| 270 | if (ret) |
| 271 | return ret; |
| 272 | |
| 273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 274 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 275 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 276 | intel_ring_emit(ring, 0); |
| 277 | intel_ring_emit(ring, 0); |
| 278 | intel_ring_advance(ring); |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static int |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 284 | gen7_render_ring_flush(struct intel_ring_buffer *ring, |
| 285 | u32 invalidate_domains, u32 flush_domains) |
| 286 | { |
| 287 | u32 flags = 0; |
| 288 | struct pipe_control *pc = ring->private; |
| 289 | u32 scratch_addr = pc->gtt_offset + 128; |
| 290 | int ret; |
| 291 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 292 | /* |
| 293 | * Ensure that any following seqno writes only happen when the render |
| 294 | * cache is indeed flushed. |
| 295 | * |
| 296 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 297 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 298 | * don't try to be clever and just set it unconditionally. |
| 299 | */ |
| 300 | flags |= PIPE_CONTROL_CS_STALL; |
| 301 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 302 | /* Just flush everything. Experiments have shown that reducing the |
| 303 | * number of bits based on the write domains has little performance |
| 304 | * impact. |
| 305 | */ |
| 306 | if (flush_domains) { |
| 307 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 308 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 309 | } |
| 310 | if (invalidate_domains) { |
| 311 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 312 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 313 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 314 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 315 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 316 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 317 | /* |
| 318 | * TLB invalidate requires a post-sync write. |
| 319 | */ |
| 320 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 321 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 322 | |
| 323 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 324 | * set before a pipe_control command that has the state cache |
| 325 | * invalidate bit set. */ |
| 326 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | ret = intel_ring_begin(ring, 4); |
| 330 | if (ret) |
| 331 | return ret; |
| 332 | |
| 333 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 334 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 335 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 336 | intel_ring_emit(ring, 0); |
| 337 | intel_ring_advance(ring); |
| 338 | |
| 339 | return 0; |
| 340 | } |
| 341 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 342 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 343 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 344 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 345 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 346 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 347 | } |
| 348 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 349 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 350 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 351 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 352 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 353 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 354 | |
| 355 | return I915_READ(acthd_reg); |
| 356 | } |
| 357 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 358 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 359 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 360 | struct drm_device *dev = ring->dev; |
| 361 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 362 | struct drm_i915_gem_object *obj = ring->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 363 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 364 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 365 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 366 | if (HAS_FORCE_WAKE(dev)) |
| 367 | gen6_gt_force_wake_get(dev_priv); |
| 368 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 369 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 370 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 371 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 372 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 373 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 374 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 375 | |
| 376 | /* G45 ring initialization fails to reset head to zero */ |
| 377 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 378 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 379 | "ctl %08x head %08x tail %08x start %08x\n", |
| 380 | ring->name, |
| 381 | I915_READ_CTL(ring), |
| 382 | I915_READ_HEAD(ring), |
| 383 | I915_READ_TAIL(ring), |
| 384 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 385 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 386 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 387 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 388 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 389 | DRM_ERROR("failed to set %s head to zero " |
| 390 | "ctl %08x head %08x tail %08x start %08x\n", |
| 391 | ring->name, |
| 392 | I915_READ_CTL(ring), |
| 393 | I915_READ_HEAD(ring), |
| 394 | I915_READ_TAIL(ring), |
| 395 | I915_READ_START(ring)); |
| 396 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 397 | } |
| 398 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 399 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 400 | * registers with the above sequence (the readback of the HEAD registers |
| 401 | * also enforces ordering), otherwise the hw might lose the new ring |
| 402 | * register values. */ |
| 403 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 404 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 405 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 406 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 407 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 408 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 409 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
| 410 | I915_READ_START(ring) == obj->gtt_offset && |
| 411 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 412 | DRM_ERROR("%s initialization failed " |
| 413 | "ctl %08x head %08x tail %08x start %08x\n", |
| 414 | ring->name, |
| 415 | I915_READ_CTL(ring), |
| 416 | I915_READ_HEAD(ring), |
| 417 | I915_READ_TAIL(ring), |
| 418 | I915_READ_START(ring)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 419 | ret = -EIO; |
| 420 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 421 | } |
| 422 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 423 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 424 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 425 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 426 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 427 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 428 | ring->space = ring_space(ring); |
Chris Wilson | c3b2003 | 2012-05-28 22:33:02 +0100 | [diff] [blame] | 429 | ring->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 430 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 431 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 432 | out: |
| 433 | if (HAS_FORCE_WAKE(dev)) |
| 434 | gen6_gt_force_wake_put(dev_priv); |
| 435 | |
| 436 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 437 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 438 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 439 | static int |
| 440 | init_pipe_control(struct intel_ring_buffer *ring) |
| 441 | { |
| 442 | struct pipe_control *pc; |
| 443 | struct drm_i915_gem_object *obj; |
| 444 | int ret; |
| 445 | |
| 446 | if (ring->private) |
| 447 | return 0; |
| 448 | |
| 449 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 450 | if (!pc) |
| 451 | return -ENOMEM; |
| 452 | |
| 453 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 454 | if (obj == NULL) { |
| 455 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 456 | ret = -ENOMEM; |
| 457 | goto err; |
| 458 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 459 | |
| 460 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 461 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 462 | ret = i915_gem_object_pin(obj, 4096, true, false); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 463 | if (ret) |
| 464 | goto err_unref; |
| 465 | |
| 466 | pc->gtt_offset = obj->gtt_offset; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 467 | pc->cpu_page = kmap(sg_page(obj->pages->sgl)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 468 | if (pc->cpu_page == NULL) |
| 469 | goto err_unpin; |
| 470 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 471 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
| 472 | ring->name, pc->gtt_offset); |
| 473 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 474 | pc->obj = obj; |
| 475 | ring->private = pc; |
| 476 | return 0; |
| 477 | |
| 478 | err_unpin: |
| 479 | i915_gem_object_unpin(obj); |
| 480 | err_unref: |
| 481 | drm_gem_object_unreference(&obj->base); |
| 482 | err: |
| 483 | kfree(pc); |
| 484 | return ret; |
| 485 | } |
| 486 | |
| 487 | static void |
| 488 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 489 | { |
| 490 | struct pipe_control *pc = ring->private; |
| 491 | struct drm_i915_gem_object *obj; |
| 492 | |
| 493 | if (!ring->private) |
| 494 | return; |
| 495 | |
| 496 | obj = pc->obj; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 497 | |
| 498 | kunmap(sg_page(obj->pages->sgl)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 499 | i915_gem_object_unpin(obj); |
| 500 | drm_gem_object_unreference(&obj->base); |
| 501 | |
| 502 | kfree(pc); |
| 503 | ring->private = NULL; |
| 504 | } |
| 505 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 506 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 507 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 508 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 509 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 510 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 511 | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 512 | if (INTEL_INFO(dev)->gen > 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 513 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 514 | |
| 515 | /* We need to disable the AsyncFlip performance optimisations in order |
| 516 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 517 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame^] | 518 | * |
| 519 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 520 | */ |
| 521 | if (INTEL_INFO(dev)->gen >= 6) |
| 522 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 523 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 524 | /* Required for the hardware to program scanline values for waiting */ |
| 525 | if (INTEL_INFO(dev)->gen == 6) |
| 526 | I915_WRITE(GFX_MODE, |
| 527 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); |
| 528 | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 529 | if (IS_GEN7(dev)) |
| 530 | I915_WRITE(GFX_MODE_GEN7, |
| 531 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 532 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 533 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 534 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 535 | ret = init_pipe_control(ring); |
| 536 | if (ret) |
| 537 | return ret; |
| 538 | } |
| 539 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 540 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 541 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 542 | * "If this bit is set, STCunit will have LRA as replacement |
| 543 | * policy. [...] This bit must be reset. LRA replacement |
| 544 | * policy is not supported." |
| 545 | */ |
| 546 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 547 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 12b0286 | 2012-06-04 14:42:50 -0700 | [diff] [blame] | 548 | |
| 549 | /* This is not explicitly set for GEN6, so read the register. |
| 550 | * see intel_ring_mi_set_context() for why we care. |
| 551 | * TODO: consider explicitly setting the bit for GEN5 |
| 552 | */ |
| 553 | ring->itlb_before_ctx_switch = |
| 554 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 555 | } |
| 556 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 557 | if (INTEL_INFO(dev)->gen >= 6) |
| 558 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 559 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 560 | if (HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 561 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 562 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 563 | return ret; |
| 564 | } |
| 565 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 566 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 567 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 568 | struct drm_device *dev = ring->dev; |
| 569 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 570 | if (!ring->private) |
| 571 | return; |
| 572 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 573 | if (HAS_BROKEN_CS_TLB(dev)) |
| 574 | drm_gem_object_unreference(to_gem_object(ring->private)); |
| 575 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 576 | cleanup_pipe_control(ring); |
| 577 | } |
| 578 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 579 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 580 | update_mboxes(struct intel_ring_buffer *ring, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 581 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 582 | { |
Chris Wilson | 1c8b46f | 2012-11-14 09:15:14 +0000 | [diff] [blame] | 583 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 584 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 585 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 586 | } |
| 587 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 588 | /** |
| 589 | * gen6_add_request - Update the semaphore mailbox registers |
| 590 | * |
| 591 | * @ring - ring that is adding a request |
| 592 | * @seqno - return seqno stuck into the ring |
| 593 | * |
| 594 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 595 | * This acts like a signal in the canonical semaphore. |
| 596 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 597 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 598 | gen6_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 599 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 600 | u32 mbox1_reg; |
| 601 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 602 | int ret; |
| 603 | |
| 604 | ret = intel_ring_begin(ring, 10); |
| 605 | if (ret) |
| 606 | return ret; |
| 607 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 608 | mbox1_reg = ring->signal_mbox[0]; |
| 609 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 610 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 611 | update_mboxes(ring, mbox1_reg); |
| 612 | update_mboxes(ring, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 613 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 614 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 615 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 616 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 617 | intel_ring_advance(ring); |
| 618 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 622 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 623 | u32 seqno) |
| 624 | { |
| 625 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 626 | return dev_priv->last_seqno < seqno; |
| 627 | } |
| 628 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 629 | /** |
| 630 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 631 | * |
| 632 | * @waiter - ring that is waiting |
| 633 | * @signaller - ring which has, or will signal |
| 634 | * @seqno - seqno which the waiter will block on |
| 635 | */ |
| 636 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 637 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 638 | struct intel_ring_buffer *signaller, |
| 639 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 640 | { |
| 641 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 642 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 643 | MI_SEMAPHORE_COMPARE | |
| 644 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 645 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 646 | /* Throughout all of the GEM code, seqno passed implies our current |
| 647 | * seqno is >= the last seqno executed. However for hardware the |
| 648 | * comparison is strictly greater than. |
| 649 | */ |
| 650 | seqno -= 1; |
| 651 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 652 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 653 | MI_SEMAPHORE_SYNC_INVALID); |
| 654 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 655 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 656 | if (ret) |
| 657 | return ret; |
| 658 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 659 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 660 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
| 661 | intel_ring_emit(waiter, |
| 662 | dw1 | |
| 663 | signaller->semaphore_register[waiter->id]); |
| 664 | intel_ring_emit(waiter, seqno); |
| 665 | intel_ring_emit(waiter, 0); |
| 666 | intel_ring_emit(waiter, MI_NOOP); |
| 667 | } else { |
| 668 | intel_ring_emit(waiter, MI_NOOP); |
| 669 | intel_ring_emit(waiter, MI_NOOP); |
| 670 | intel_ring_emit(waiter, MI_NOOP); |
| 671 | intel_ring_emit(waiter, MI_NOOP); |
| 672 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 673 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 674 | |
| 675 | return 0; |
| 676 | } |
| 677 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 678 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 679 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 680 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 681 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 682 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 683 | intel_ring_emit(ring__, 0); \ |
| 684 | intel_ring_emit(ring__, 0); \ |
| 685 | } while (0) |
| 686 | |
| 687 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 688 | pc_render_add_request(struct intel_ring_buffer *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 689 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 690 | struct pipe_control *pc = ring->private; |
| 691 | u32 scratch_addr = pc->gtt_offset + 128; |
| 692 | int ret; |
| 693 | |
| 694 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 695 | * incoherent with writes to memory, i.e. completely fubar, |
| 696 | * so we need to use PIPE_NOTIFY instead. |
| 697 | * |
| 698 | * However, we also need to workaround the qword write |
| 699 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 700 | * memory before requesting an interrupt. |
| 701 | */ |
| 702 | ret = intel_ring_begin(ring, 32); |
| 703 | if (ret) |
| 704 | return ret; |
| 705 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 706 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 707 | PIPE_CONTROL_WRITE_FLUSH | |
| 708 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 709 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 710 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 711 | intel_ring_emit(ring, 0); |
| 712 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 713 | scratch_addr += 128; /* write to separate cachelines */ |
| 714 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 715 | scratch_addr += 128; |
| 716 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 717 | scratch_addr += 128; |
| 718 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 719 | scratch_addr += 128; |
| 720 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 721 | scratch_addr += 128; |
| 722 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 723 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 724 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 725 | PIPE_CONTROL_WRITE_FLUSH | |
| 726 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 727 | PIPE_CONTROL_NOTIFY); |
| 728 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 729 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 730 | intel_ring_emit(ring, 0); |
| 731 | intel_ring_advance(ring); |
| 732 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 733 | return 0; |
| 734 | } |
| 735 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 736 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 737 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 738 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 739 | /* Workaround to force correct ordering between irq and seqno writes on |
| 740 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 741 | * ACTHD) before reading the status page. */ |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 742 | if (!lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 743 | intel_ring_get_active_head(ring); |
| 744 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 745 | } |
| 746 | |
| 747 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 748 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 749 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 750 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 751 | } |
| 752 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 753 | static void |
| 754 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 755 | { |
| 756 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 757 | } |
| 758 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 759 | static u32 |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 760 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 761 | { |
| 762 | struct pipe_control *pc = ring->private; |
| 763 | return pc->cpu_page[0]; |
| 764 | } |
| 765 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 766 | static void |
| 767 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 768 | { |
| 769 | struct pipe_control *pc = ring->private; |
| 770 | pc->cpu_page[0] = seqno; |
| 771 | } |
| 772 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 773 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 774 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 775 | { |
| 776 | struct drm_device *dev = ring->dev; |
| 777 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 778 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 779 | |
| 780 | if (!dev->irq_enabled) |
| 781 | return false; |
| 782 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 783 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 784 | if (ring->irq_refcount++ == 0) { |
| 785 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 786 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 787 | POSTING_READ(GTIMR); |
| 788 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 789 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 790 | |
| 791 | return true; |
| 792 | } |
| 793 | |
| 794 | static void |
| 795 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 796 | { |
| 797 | struct drm_device *dev = ring->dev; |
| 798 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 799 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 800 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 801 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 802 | if (--ring->irq_refcount == 0) { |
| 803 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 804 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 805 | POSTING_READ(GTIMR); |
| 806 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 807 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 808 | } |
| 809 | |
| 810 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 811 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 812 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 813 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 814 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 815 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 816 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 817 | if (!dev->irq_enabled) |
| 818 | return false; |
| 819 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 820 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 821 | if (ring->irq_refcount++ == 0) { |
| 822 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 823 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 824 | POSTING_READ(IMR); |
| 825 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 826 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 827 | |
| 828 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 829 | } |
| 830 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 831 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 832 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 833 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 834 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 835 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 836 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 837 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 838 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 839 | if (--ring->irq_refcount == 0) { |
| 840 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 841 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 842 | POSTING_READ(IMR); |
| 843 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 844 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 845 | } |
| 846 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 847 | static bool |
| 848 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) |
| 849 | { |
| 850 | struct drm_device *dev = ring->dev; |
| 851 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 852 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 853 | |
| 854 | if (!dev->irq_enabled) |
| 855 | return false; |
| 856 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 857 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 858 | if (ring->irq_refcount++ == 0) { |
| 859 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 860 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 861 | POSTING_READ16(IMR); |
| 862 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 863 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 864 | |
| 865 | return true; |
| 866 | } |
| 867 | |
| 868 | static void |
| 869 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) |
| 870 | { |
| 871 | struct drm_device *dev = ring->dev; |
| 872 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 873 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 874 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 875 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 876 | if (--ring->irq_refcount == 0) { |
| 877 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 878 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 879 | POSTING_READ16(IMR); |
| 880 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 881 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 882 | } |
| 883 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 884 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 885 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 886 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 887 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 888 | u32 mmio = 0; |
| 889 | |
| 890 | /* The ring status page addresses are no longer next to the rest of |
| 891 | * the ring registers as of gen7. |
| 892 | */ |
| 893 | if (IS_GEN7(dev)) { |
| 894 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 895 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 896 | mmio = RENDER_HWS_PGA_GEN7; |
| 897 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 898 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 899 | mmio = BLT_HWS_PGA_GEN7; |
| 900 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 901 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 902 | mmio = BSD_HWS_PGA_GEN7; |
| 903 | break; |
| 904 | } |
| 905 | } else if (IS_GEN6(ring->dev)) { |
| 906 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 907 | } else { |
| 908 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 909 | } |
| 910 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 911 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 912 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 913 | } |
| 914 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 915 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 916 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 917 | u32 invalidate_domains, |
| 918 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 919 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 920 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 921 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 922 | ret = intel_ring_begin(ring, 2); |
| 923 | if (ret) |
| 924 | return ret; |
| 925 | |
| 926 | intel_ring_emit(ring, MI_FLUSH); |
| 927 | intel_ring_emit(ring, MI_NOOP); |
| 928 | intel_ring_advance(ring); |
| 929 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 930 | } |
| 931 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 932 | static int |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 933 | i9xx_add_request(struct intel_ring_buffer *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 934 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 935 | int ret; |
| 936 | |
| 937 | ret = intel_ring_begin(ring, 4); |
| 938 | if (ret) |
| 939 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 940 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 941 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 942 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 943 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 944 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 945 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 946 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 947 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 948 | } |
| 949 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 950 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 951 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 952 | { |
| 953 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 954 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 955 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 956 | |
| 957 | if (!dev->irq_enabled) |
| 958 | return false; |
| 959 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 960 | /* It looks like we need to prevent the gt from suspending while waiting |
| 961 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 962 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 963 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 964 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 965 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 966 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 967 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 968 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
| 969 | GEN6_RENDER_L3_PARITY_ERROR)); |
| 970 | else |
| 971 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 972 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
| 973 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 974 | POSTING_READ(GTIMR); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 975 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 976 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 977 | |
| 978 | return true; |
| 979 | } |
| 980 | |
| 981 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 982 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 983 | { |
| 984 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 985 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 986 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 987 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 988 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 989 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 990 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 991 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
| 992 | else |
| 993 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 994 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
| 995 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 996 | POSTING_READ(GTIMR); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 997 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 998 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 999 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 1000 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1003 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1004 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1005 | u32 offset, u32 length, |
| 1006 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1007 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1008 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1009 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1010 | ret = intel_ring_begin(ring, 2); |
| 1011 | if (ret) |
| 1012 | return ret; |
| 1013 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1014 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1015 | MI_BATCH_BUFFER_START | |
| 1016 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1017 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1018 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1019 | intel_ring_advance(ring); |
| 1020 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1021 | return 0; |
| 1022 | } |
| 1023 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1024 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1025 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1026 | static int |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1027 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1028 | u32 offset, u32 len, |
| 1029 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1030 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1031 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1032 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1033 | if (flags & I915_DISPATCH_PINNED) { |
| 1034 | ret = intel_ring_begin(ring, 4); |
| 1035 | if (ret) |
| 1036 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1037 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1038 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1039 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1040 | intel_ring_emit(ring, offset + len - 8); |
| 1041 | intel_ring_emit(ring, MI_NOOP); |
| 1042 | intel_ring_advance(ring); |
| 1043 | } else { |
| 1044 | struct drm_i915_gem_object *obj = ring->private; |
| 1045 | u32 cs_offset = obj->gtt_offset; |
| 1046 | |
| 1047 | if (len > I830_BATCH_LIMIT) |
| 1048 | return -ENOSPC; |
| 1049 | |
| 1050 | ret = intel_ring_begin(ring, 9+3); |
| 1051 | if (ret) |
| 1052 | return ret; |
| 1053 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1054 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1055 | * invalidation bug) ... */ |
| 1056 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1057 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1058 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1059 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1060 | intel_ring_emit(ring, 0); |
| 1061 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1062 | intel_ring_emit(ring, cs_offset); |
| 1063 | intel_ring_emit(ring, 0); |
| 1064 | intel_ring_emit(ring, 4096); |
| 1065 | intel_ring_emit(ring, offset); |
| 1066 | intel_ring_emit(ring, MI_FLUSH); |
| 1067 | |
| 1068 | /* ... and execute it. */ |
| 1069 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1070 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1071 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1072 | intel_ring_advance(ring); |
| 1073 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1074 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static int |
| 1079 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1080 | u32 offset, u32 len, |
| 1081 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1082 | { |
| 1083 | int ret; |
| 1084 | |
| 1085 | ret = intel_ring_begin(ring, 2); |
| 1086 | if (ret) |
| 1087 | return ret; |
| 1088 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1089 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1090 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1091 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1092 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1093 | return 0; |
| 1094 | } |
| 1095 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1096 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1097 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1098 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1099 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1100 | obj = ring->status_page.obj; |
| 1101 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1102 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1103 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1104 | kunmap(sg_page(obj->pages->sgl)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1105 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1106 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1107 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1108 | } |
| 1109 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1110 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1111 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1112 | struct drm_device *dev = ring->dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1113 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1114 | int ret; |
| 1115 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1116 | obj = i915_gem_alloc_object(dev, 4096); |
| 1117 | if (obj == NULL) { |
| 1118 | DRM_ERROR("Failed to allocate status page\n"); |
| 1119 | ret = -ENOMEM; |
| 1120 | goto err; |
| 1121 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1122 | |
| 1123 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1124 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1125 | ret = i915_gem_object_pin(obj, 4096, true, false); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1126 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1127 | goto err_unref; |
| 1128 | } |
| 1129 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1130 | ring->status_page.gfx_addr = obj->gtt_offset; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1131 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1132 | if (ring->status_page.page_addr == NULL) { |
Ben Widawsky | 2e6c21e | 2012-07-12 23:16:12 -0700 | [diff] [blame] | 1133 | ret = -ENOMEM; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1134 | goto err_unpin; |
| 1135 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1136 | ring->status_page.obj = obj; |
| 1137 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1138 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1139 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1140 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1141 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1142 | |
| 1143 | return 0; |
| 1144 | |
| 1145 | err_unpin: |
| 1146 | i915_gem_object_unpin(obj); |
| 1147 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1148 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1149 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1150 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1153 | static int init_phys_hws_pga(struct intel_ring_buffer *ring) |
| 1154 | { |
| 1155 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1156 | u32 addr; |
| 1157 | |
| 1158 | if (!dev_priv->status_page_dmah) { |
| 1159 | dev_priv->status_page_dmah = |
| 1160 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1161 | if (!dev_priv->status_page_dmah) |
| 1162 | return -ENOMEM; |
| 1163 | } |
| 1164 | |
| 1165 | addr = dev_priv->status_page_dmah->busaddr; |
| 1166 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 1167 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 1168 | I915_WRITE(HWS_PGA, addr); |
| 1169 | |
| 1170 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1171 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1172 | |
| 1173 | return 0; |
| 1174 | } |
| 1175 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1176 | static int intel_init_ring_buffer(struct drm_device *dev, |
| 1177 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1178 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1179 | struct drm_i915_gem_object *obj; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1180 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1181 | int ret; |
| 1182 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1183 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1184 | INIT_LIST_HEAD(&ring->active_list); |
| 1185 | INIT_LIST_HEAD(&ring->request_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 1186 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1187 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1188 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1189 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1190 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1191 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1192 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1193 | if (ret) |
| 1194 | return ret; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1195 | } else { |
| 1196 | BUG_ON(ring->id != RCS); |
| 1197 | ret = init_phys_hws_pga(ring); |
| 1198 | if (ret) |
| 1199 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1200 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1201 | |
Chris Wilson | ebc052e | 2012-11-15 11:32:28 +0000 | [diff] [blame] | 1202 | obj = NULL; |
| 1203 | if (!HAS_LLC(dev)) |
| 1204 | obj = i915_gem_object_create_stolen(dev, ring->size); |
| 1205 | if (obj == NULL) |
| 1206 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1207 | if (obj == NULL) { |
| 1208 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1209 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1210 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1211 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1212 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1213 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1214 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1215 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1216 | if (ret) |
| 1217 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1218 | |
Chris Wilson | 3eef891 | 2012-06-04 17:05:40 +0100 | [diff] [blame] | 1219 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1220 | if (ret) |
| 1221 | goto err_unpin; |
| 1222 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1223 | ring->virtual_start = |
Ben Widawsky | dabb7a9 | 2013-01-17 12:45:16 -0800 | [diff] [blame] | 1224 | ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset, |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1225 | ring->size); |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1226 | if (ring->virtual_start == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1227 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1228 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1229 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1230 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1231 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1232 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1233 | if (ret) |
| 1234 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1235 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1236 | /* Workaround an erratum on the i830 which causes a hang if |
| 1237 | * the TAIL pointer points to within the last 2 cachelines |
| 1238 | * of the buffer. |
| 1239 | */ |
| 1240 | ring->effective_size = ring->size; |
Chris Wilson | 27c1cbd | 2012-04-09 13:59:46 +0100 | [diff] [blame] | 1241 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1242 | ring->effective_size -= 128; |
| 1243 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 1244 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1245 | |
| 1246 | err_unmap: |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1247 | iounmap(ring->virtual_start); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1248 | err_unpin: |
| 1249 | i915_gem_object_unpin(obj); |
| 1250 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1251 | drm_gem_object_unreference(&obj->base); |
| 1252 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1253 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1254 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1255 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1256 | } |
| 1257 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1258 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1259 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1260 | struct drm_i915_private *dev_priv; |
| 1261 | int ret; |
| 1262 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1263 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1264 | return; |
| 1265 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1266 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1267 | dev_priv = ring->dev->dev_private; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1268 | ret = intel_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1269 | if (ret) |
| 1270 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1271 | ring->name, ret); |
| 1272 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1273 | I915_WRITE_CTL(ring, 0); |
| 1274 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1275 | iounmap(ring->virtual_start); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1276 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1277 | i915_gem_object_unpin(ring->obj); |
| 1278 | drm_gem_object_unreference(&ring->obj->base); |
| 1279 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1280 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1281 | if (ring->cleanup) |
| 1282 | ring->cleanup(ring); |
| 1283 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1284 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1285 | } |
| 1286 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1287 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1288 | { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1289 | int ret; |
| 1290 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1291 | ret = i915_wait_seqno(ring, seqno); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1292 | if (!ret) |
| 1293 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1294 | |
| 1295 | return ret; |
| 1296 | } |
| 1297 | |
| 1298 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1299 | { |
| 1300 | struct drm_i915_gem_request *request; |
| 1301 | u32 seqno = 0; |
| 1302 | int ret; |
| 1303 | |
| 1304 | i915_gem_retire_requests_ring(ring); |
| 1305 | |
| 1306 | if (ring->last_retired_head != -1) { |
| 1307 | ring->head = ring->last_retired_head; |
| 1308 | ring->last_retired_head = -1; |
| 1309 | ring->space = ring_space(ring); |
| 1310 | if (ring->space >= n) |
| 1311 | return 0; |
| 1312 | } |
| 1313 | |
| 1314 | list_for_each_entry(request, &ring->request_list, list) { |
| 1315 | int space; |
| 1316 | |
| 1317 | if (request->tail == -1) |
| 1318 | continue; |
| 1319 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 1320 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1321 | if (space < 0) |
| 1322 | space += ring->size; |
| 1323 | if (space >= n) { |
| 1324 | seqno = request->seqno; |
| 1325 | break; |
| 1326 | } |
| 1327 | |
| 1328 | /* Consume this request in case we need more space than |
| 1329 | * is available and so need to prevent a race between |
| 1330 | * updating last_retired_head and direct reads of |
| 1331 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1332 | */ |
| 1333 | request->tail = -1; |
| 1334 | } |
| 1335 | |
| 1336 | if (seqno == 0) |
| 1337 | return -ENOSPC; |
| 1338 | |
| 1339 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1340 | if (ret) |
| 1341 | return ret; |
| 1342 | |
| 1343 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1344 | return -ENOSPC; |
| 1345 | |
| 1346 | ring->head = ring->last_retired_head; |
| 1347 | ring->last_retired_head = -1; |
| 1348 | ring->space = ring_space(ring); |
| 1349 | if (WARN_ON(ring->space < n)) |
| 1350 | return -ENOSPC; |
| 1351 | |
| 1352 | return 0; |
| 1353 | } |
| 1354 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1355 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1356 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1357 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1358 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1359 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1360 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1361 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1362 | ret = intel_ring_wait_request(ring, n); |
| 1363 | if (ret != -ENOSPC) |
| 1364 | return ret; |
| 1365 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1366 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1367 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1368 | * leaving it early runs the risk of corrupting GEM state (due |
| 1369 | * to running on almost untested codepaths). But on resume |
| 1370 | * timers don't work yet, so prevent a complete hang in that |
| 1371 | * case by choosing an insanely large timeout. */ |
| 1372 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1373 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1374 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1375 | ring->head = I915_READ_HEAD(ring); |
| 1376 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1377 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1378 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1379 | return 0; |
| 1380 | } |
| 1381 | |
| 1382 | if (dev->primary->master) { |
| 1383 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1384 | if (master_priv->sarea_priv) |
| 1385 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1386 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1387 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1388 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1389 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1390 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1391 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1392 | if (ret) |
| 1393 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1394 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1395 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1396 | return -EBUSY; |
| 1397 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1398 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1399 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
| 1400 | { |
| 1401 | uint32_t __iomem *virt; |
| 1402 | int rem = ring->size - ring->tail; |
| 1403 | |
| 1404 | if (ring->space < rem) { |
| 1405 | int ret = ring_wait_for_space(ring, rem); |
| 1406 | if (ret) |
| 1407 | return ret; |
| 1408 | } |
| 1409 | |
| 1410 | virt = ring->virtual_start + ring->tail; |
| 1411 | rem /= 4; |
| 1412 | while (rem--) |
| 1413 | iowrite32(MI_NOOP, virt++); |
| 1414 | |
| 1415 | ring->tail = 0; |
| 1416 | ring->space = ring_space(ring); |
| 1417 | |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
| 1421 | int intel_ring_idle(struct intel_ring_buffer *ring) |
| 1422 | { |
| 1423 | u32 seqno; |
| 1424 | int ret; |
| 1425 | |
| 1426 | /* We need to add any requests required to flush the objects and ring */ |
| 1427 | if (ring->outstanding_lazy_request) { |
| 1428 | ret = i915_add_request(ring, NULL, NULL); |
| 1429 | if (ret) |
| 1430 | return ret; |
| 1431 | } |
| 1432 | |
| 1433 | /* Wait upon the last request to be completed */ |
| 1434 | if (list_empty(&ring->request_list)) |
| 1435 | return 0; |
| 1436 | |
| 1437 | seqno = list_entry(ring->request_list.prev, |
| 1438 | struct drm_i915_gem_request, |
| 1439 | list)->seqno; |
| 1440 | |
| 1441 | return i915_wait_seqno(ring, seqno); |
| 1442 | } |
| 1443 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1444 | static int |
| 1445 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) |
| 1446 | { |
| 1447 | if (ring->outstanding_lazy_request) |
| 1448 | return 0; |
| 1449 | |
| 1450 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request); |
| 1451 | } |
| 1452 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1453 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
| 1454 | int bytes) |
| 1455 | { |
| 1456 | int ret; |
| 1457 | |
| 1458 | if (unlikely(ring->tail + bytes > ring->effective_size)) { |
| 1459 | ret = intel_wrap_ring_buffer(ring); |
| 1460 | if (unlikely(ret)) |
| 1461 | return ret; |
| 1462 | } |
| 1463 | |
| 1464 | if (unlikely(ring->space < bytes)) { |
| 1465 | ret = ring_wait_for_space(ring, bytes); |
| 1466 | if (unlikely(ret)) |
| 1467 | return ret; |
| 1468 | } |
| 1469 | |
| 1470 | ring->space -= bytes; |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1474 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1475 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1476 | { |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1477 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1478 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1479 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1480 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1481 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 1482 | if (ret) |
| 1483 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1484 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1485 | /* Preallocate the olr before touching the ring */ |
| 1486 | ret = intel_ring_alloc_seqno(ring); |
| 1487 | if (ret) |
| 1488 | return ret; |
| 1489 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 1490 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1491 | } |
| 1492 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1493 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1494 | { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1495 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 1496 | |
| 1497 | BUG_ON(ring->outstanding_lazy_request); |
| 1498 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1499 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
| 1500 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 1501 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1502 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1503 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 1504 | ring->set_seqno(ring, seqno); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1505 | } |
| 1506 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1507 | void intel_ring_advance(struct intel_ring_buffer *ring) |
| 1508 | { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1509 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1510 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1511 | ring->tail &= ring->size - 1; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1512 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1513 | return; |
| 1514 | ring->write_tail(ring, ring->tail); |
| 1515 | } |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1516 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1517 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1518 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
| 1519 | u32 value) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1520 | { |
| 1521 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 1522 | |
| 1523 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1524 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1525 | /* Disable notification that the ring is IDLE. The GT |
| 1526 | * will then assume that it is busy and bring it out of rc6. |
| 1527 | */ |
| 1528 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1529 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 1530 | |
| 1531 | /* Clear the context id. Here be magic! */ |
| 1532 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 1533 | |
| 1534 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1535 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1536 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 1537 | 50)) |
| 1538 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1539 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1540 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1541 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1542 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 1543 | |
| 1544 | /* Let the ring send IDLE messages to the GT again, |
| 1545 | * and so let it sleep to conserve power when idle. |
| 1546 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1547 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 1548 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1549 | } |
| 1550 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1551 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1552 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1553 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1554 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1555 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1556 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1557 | ret = intel_ring_begin(ring, 4); |
| 1558 | if (ret) |
| 1559 | return ret; |
| 1560 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1561 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1562 | /* |
| 1563 | * Bspec vol 1c.5 - video engine command streamer: |
| 1564 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1565 | * operation is complete. This bit is only valid when the |
| 1566 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1567 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1568 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1569 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 1570 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1571 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1572 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1573 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1574 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1575 | intel_ring_advance(ring); |
| 1576 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1577 | } |
| 1578 | |
| 1579 | static int |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1580 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1581 | u32 offset, u32 len, |
| 1582 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1583 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1584 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1585 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1586 | ret = intel_ring_begin(ring, 2); |
| 1587 | if (ret) |
| 1588 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1589 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1590 | intel_ring_emit(ring, |
| 1591 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 1592 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 1593 | /* bit0-7 is the length on GEN6+ */ |
| 1594 | intel_ring_emit(ring, offset); |
| 1595 | intel_ring_advance(ring); |
| 1596 | |
| 1597 | return 0; |
| 1598 | } |
| 1599 | |
| 1600 | static int |
| 1601 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
| 1602 | u32 offset, u32 len, |
| 1603 | unsigned flags) |
| 1604 | { |
| 1605 | int ret; |
| 1606 | |
| 1607 | ret = intel_ring_begin(ring, 2); |
| 1608 | if (ret) |
| 1609 | return ret; |
| 1610 | |
| 1611 | intel_ring_emit(ring, |
| 1612 | MI_BATCH_BUFFER_START | |
| 1613 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1614 | /* bit0-7 is the length on GEN6+ */ |
| 1615 | intel_ring_emit(ring, offset); |
| 1616 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1617 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1618 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1619 | } |
| 1620 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1621 | /* Blitter support (SandyBridge+) */ |
| 1622 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1623 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1624 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1625 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1626 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1627 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1628 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1629 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1630 | if (ret) |
| 1631 | return ret; |
| 1632 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1633 | cmd = MI_FLUSH_DW; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1634 | /* |
| 1635 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 1636 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 1637 | * operation is complete. This bit is only valid when the |
| 1638 | * Post-Sync Operation field is a value of 1h or 3h." |
| 1639 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1640 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1641 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 1642 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1643 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 1644 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1645 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1646 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1647 | intel_ring_advance(ring); |
| 1648 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1649 | } |
| 1650 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1651 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1652 | { |
| 1653 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1654 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1655 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1656 | ring->name = "render ring"; |
| 1657 | ring->id = RCS; |
| 1658 | ring->mmio_base = RENDER_RING_BASE; |
| 1659 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1660 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1661 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 1662 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 1663 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 1664 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1665 | ring->irq_get = gen6_ring_get_irq; |
| 1666 | ring->irq_put = gen6_ring_put_irq; |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 1667 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1668 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1669 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1670 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1671 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
| 1672 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; |
| 1673 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; |
| 1674 | ring->signal_mbox[0] = GEN6_VRSYNC; |
| 1675 | ring->signal_mbox[1] = GEN6_BRSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1676 | } else if (IS_GEN5(dev)) { |
| 1677 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1678 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1679 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1680 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1681 | ring->irq_get = gen5_ring_get_irq; |
| 1682 | ring->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1683 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1684 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1685 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1686 | if (INTEL_INFO(dev)->gen < 4) |
| 1687 | ring->flush = gen2_render_ring_flush; |
| 1688 | else |
| 1689 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1690 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1691 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1692 | if (IS_GEN2(dev)) { |
| 1693 | ring->irq_get = i8xx_ring_get_irq; |
| 1694 | ring->irq_put = i8xx_ring_put_irq; |
| 1695 | } else { |
| 1696 | ring->irq_get = i9xx_ring_get_irq; |
| 1697 | ring->irq_put = i9xx_ring_put_irq; |
| 1698 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1699 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1700 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1701 | ring->write_tail = ring_write_tail; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1702 | if (IS_HASWELL(dev)) |
| 1703 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
| 1704 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1705 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 1706 | else if (INTEL_INFO(dev)->gen >= 4) |
| 1707 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1708 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1709 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1710 | else |
| 1711 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1712 | ring->init = init_render_ring; |
| 1713 | ring->cleanup = render_ring_cleanup; |
| 1714 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1715 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 1716 | if (HAS_BROKEN_CS_TLB(dev)) { |
| 1717 | struct drm_i915_gem_object *obj; |
| 1718 | int ret; |
| 1719 | |
| 1720 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 1721 | if (obj == NULL) { |
| 1722 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 1723 | return -ENOMEM; |
| 1724 | } |
| 1725 | |
| 1726 | ret = i915_gem_object_pin(obj, 0, true, false); |
| 1727 | if (ret != 0) { |
| 1728 | drm_gem_object_unreference(&obj->base); |
| 1729 | DRM_ERROR("Failed to ping batch bo\n"); |
| 1730 | return ret; |
| 1731 | } |
| 1732 | |
| 1733 | ring->private = obj; |
| 1734 | } |
| 1735 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1736 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1737 | } |
| 1738 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1739 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1740 | { |
| 1741 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1742 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1743 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1744 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1745 | ring->name = "render ring"; |
| 1746 | ring->id = RCS; |
| 1747 | ring->mmio_base = RENDER_RING_BASE; |
| 1748 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1749 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 1750 | /* non-kms not supported on gen6+ */ |
| 1751 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1752 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1753 | |
| 1754 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 1755 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 1756 | * the special gen5 functions. */ |
| 1757 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 1758 | if (INTEL_INFO(dev)->gen < 4) |
| 1759 | ring->flush = gen2_render_ring_flush; |
| 1760 | else |
| 1761 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1762 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1763 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1764 | if (IS_GEN2(dev)) { |
| 1765 | ring->irq_get = i8xx_ring_get_irq; |
| 1766 | ring->irq_put = i8xx_ring_put_irq; |
| 1767 | } else { |
| 1768 | ring->irq_get = i9xx_ring_get_irq; |
| 1769 | ring->irq_put = i9xx_ring_put_irq; |
| 1770 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 1771 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1772 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1773 | if (INTEL_INFO(dev)->gen >= 4) |
| 1774 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 1775 | else if (IS_I830(dev) || IS_845G(dev)) |
| 1776 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 1777 | else |
| 1778 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1779 | ring->init = init_render_ring; |
| 1780 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1781 | |
| 1782 | ring->dev = dev; |
| 1783 | INIT_LIST_HEAD(&ring->active_list); |
| 1784 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1785 | |
| 1786 | ring->size = size; |
| 1787 | ring->effective_size = ring->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 1788 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1789 | ring->effective_size -= 128; |
| 1790 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 1791 | ring->virtual_start = ioremap_wc(start, size); |
| 1792 | if (ring->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1793 | DRM_ERROR("can not ioremap virtual address for" |
| 1794 | " ring buffer\n"); |
| 1795 | return -ENOMEM; |
| 1796 | } |
| 1797 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1798 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1799 | ret = init_phys_hws_pga(ring); |
| 1800 | if (ret) |
| 1801 | return ret; |
| 1802 | } |
| 1803 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1804 | return 0; |
| 1805 | } |
| 1806 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1807 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1808 | { |
| 1809 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1810 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1811 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1812 | ring->name = "bsd ring"; |
| 1813 | ring->id = VCS; |
| 1814 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1815 | ring->write_tail = ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1816 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1817 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 1818 | /* gen6 bsd needs a special wa for tail updates */ |
| 1819 | if (IS_GEN6(dev)) |
| 1820 | ring->write_tail = gen6_bsd_ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1821 | ring->flush = gen6_ring_flush; |
| 1822 | ring->add_request = gen6_add_request; |
| 1823 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1824 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1825 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; |
| 1826 | ring->irq_get = gen6_ring_get_irq; |
| 1827 | ring->irq_put = gen6_ring_put_irq; |
| 1828 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1829 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1830 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
| 1831 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; |
| 1832 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; |
| 1833 | ring->signal_mbox[0] = GEN6_RVSYNC; |
| 1834 | ring->signal_mbox[1] = GEN6_BVSYNC; |
| 1835 | } else { |
| 1836 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1837 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 1838 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1839 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1840 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1841 | if (IS_GEN5(dev)) { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1842 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1843 | ring->irq_get = gen5_ring_get_irq; |
| 1844 | ring->irq_put = gen5_ring_put_irq; |
| 1845 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1846 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1847 | ring->irq_get = i9xx_ring_get_irq; |
| 1848 | ring->irq_put = i9xx_ring_put_irq; |
| 1849 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1850 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1851 | } |
| 1852 | ring->init = init_ring_common; |
| 1853 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1854 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1855 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1856 | |
| 1857 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1858 | { |
| 1859 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1860 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1861 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1862 | ring->name = "blitter ring"; |
| 1863 | ring->id = BCS; |
| 1864 | |
| 1865 | ring->mmio_base = BLT_RING_BASE; |
| 1866 | ring->write_tail = ring_write_tail; |
| 1867 | ring->flush = blt_ring_flush; |
| 1868 | ring->add_request = gen6_add_request; |
| 1869 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1870 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1871 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; |
| 1872 | ring->irq_get = gen6_ring_get_irq; |
| 1873 | ring->irq_put = gen6_ring_put_irq; |
| 1874 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1875 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1876 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
| 1877 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; |
| 1878 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; |
| 1879 | ring->signal_mbox[0] = GEN6_RBSYNC; |
| 1880 | ring->signal_mbox[1] = GEN6_VBSYNC; |
| 1881 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1882 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1883 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1884 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1885 | |
| 1886 | int |
| 1887 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) |
| 1888 | { |
| 1889 | int ret; |
| 1890 | |
| 1891 | if (!ring->gpu_caches_dirty) |
| 1892 | return 0; |
| 1893 | |
| 1894 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1895 | if (ret) |
| 1896 | return ret; |
| 1897 | |
| 1898 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 1899 | |
| 1900 | ring->gpu_caches_dirty = false; |
| 1901 | return 0; |
| 1902 | } |
| 1903 | |
| 1904 | int |
| 1905 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) |
| 1906 | { |
| 1907 | uint32_t flush_domains; |
| 1908 | int ret; |
| 1909 | |
| 1910 | flush_domains = 0; |
| 1911 | if (ring->gpu_caches_dirty) |
| 1912 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 1913 | |
| 1914 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1915 | if (ret) |
| 1916 | return ret; |
| 1917 | |
| 1918 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 1919 | |
| 1920 | ring->gpu_caches_dirty = false; |
| 1921 | return 0; |
| 1922 | } |