blob: 8a165bbfcedc0d2991a07213cf2fb93996824343 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020071
72static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
73static const char mlxsw_sp_driver_version[] = "1.0";
74
75/* tx_hdr_version
76 * Tx header version.
77 * Must be set to 1.
78 */
79MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
80
81/* tx_hdr_ctl
82 * Packet control type.
83 * 0 - Ethernet control (e.g. EMADs, LACP)
84 * 1 - Ethernet data
85 */
86MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
87
88/* tx_hdr_proto
89 * Packet protocol type. Must be set to 1 (Ethernet).
90 */
91MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
92
93/* tx_hdr_rx_is_router
94 * Packet is sent from the router. Valid for data packets only.
95 */
96MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
97
98/* tx_hdr_fid_valid
99 * Indicates if the 'fid' field is valid and should be used for
100 * forwarding lookup. Valid for data packets only.
101 */
102MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
103
104/* tx_hdr_swid
105 * Switch partition ID. Must be set to 0.
106 */
107MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
108
109/* tx_hdr_control_tclass
110 * Indicates if the packet should use the control TClass and not one
111 * of the data TClasses.
112 */
113MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
114
115/* tx_hdr_etclass
116 * Egress TClass to be used on the egress device on the egress port.
117 */
118MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
119
120/* tx_hdr_port_mid
121 * Destination local port for unicast packets.
122 * Destination multicast ID for multicast packets.
123 *
124 * Control packets are directed to a specific egress port, while data
125 * packets are transmitted through the CPU port (0) into the switch partition,
126 * where forwarding rules are applied.
127 */
128MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
129
130/* tx_hdr_fid
131 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
132 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
133 * Valid for data packets only.
134 */
135MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
136
137/* tx_hdr_type
138 * 0 - Data packets
139 * 6 - Control packets
140 */
141MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
142
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100143int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
144 unsigned int counter_index, u64 *packets,
145 u64 *bytes)
146{
147 char mgpc_pl[MLXSW_REG_MGPC_LEN];
148 int err;
149
150 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
151 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
153 if (err)
154 return err;
155 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
156 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
157 return 0;
158}
159
160static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
161 unsigned int counter_index)
162{
163 char mgpc_pl[MLXSW_REG_MGPC_LEN];
164
165 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
166 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
167 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
168}
169
170int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
171 unsigned int *p_counter_index)
172{
173 int err;
174
175 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
176 p_counter_index);
177 if (err)
178 return err;
179 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
180 if (err)
181 goto err_counter_clear;
182 return 0;
183
184err_counter_clear:
185 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
186 *p_counter_index);
187 return err;
188}
189
190void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
191 unsigned int counter_index)
192{
193 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
194 counter_index);
195}
196
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200197static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
198 const struct mlxsw_tx_info *tx_info)
199{
200 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
201
202 memset(txhdr, 0, MLXSW_TXHDR_LEN);
203
204 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
205 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
206 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
207 mlxsw_tx_hdr_swid_set(txhdr, 0);
208 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
209 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
210 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
211}
212
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200213int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
214 u8 state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 enum mlxsw_reg_spms_state spms_state;
218 char *spms_pl;
219 int err;
220
221 switch (state) {
222 case BR_STATE_FORWARDING:
223 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
224 break;
225 case BR_STATE_LEARNING:
226 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
227 break;
228 case BR_STATE_LISTENING: /* fall-through */
229 case BR_STATE_DISABLED: /* fall-through */
230 case BR_STATE_BLOCKING:
231 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
232 break;
233 default:
234 BUG();
235 }
236
237 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
238 if (!spms_pl)
239 return -ENOMEM;
240 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
241 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
242
243 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
244 kfree(spms_pl);
245 return err;
246}
247
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200248static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
249{
Elad Raz5b090742016-10-28 21:35:46 +0200250 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200251 int err;
252
253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
254 if (err)
255 return err;
256 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
257 return 0;
258}
259
Yotam Gigi763b4b72016-07-21 12:03:17 +0200260static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
261{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200262 int i;
263
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200264 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200265 return -EIO;
266
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200267 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
268 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200269 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
270 sizeof(struct mlxsw_sp_span_entry),
271 GFP_KERNEL);
272 if (!mlxsw_sp->span.entries)
273 return -ENOMEM;
274
275 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
276 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
277
278 return 0;
279}
280
281static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
282{
283 int i;
284
285 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
286 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
287
288 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
289 }
290 kfree(mlxsw_sp->span.entries);
291}
292
293static struct mlxsw_sp_span_entry *
294mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
295{
296 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
297 struct mlxsw_sp_span_entry *span_entry;
298 char mpat_pl[MLXSW_REG_MPAT_LEN];
299 u8 local_port = port->local_port;
300 int index;
301 int i;
302 int err;
303
304 /* find a free entry to use */
305 index = -1;
306 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
307 if (!mlxsw_sp->span.entries[i].used) {
308 index = i;
309 span_entry = &mlxsw_sp->span.entries[i];
310 break;
311 }
312 }
313 if (index < 0)
314 return NULL;
315
316 /* create a new port analayzer entry for local_port */
317 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
318 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
319 if (err)
320 return NULL;
321
322 span_entry->used = true;
323 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100324 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200325 span_entry->local_port = local_port;
326 return span_entry;
327}
328
329static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
330 struct mlxsw_sp_span_entry *span_entry)
331{
332 u8 local_port = span_entry->local_port;
333 char mpat_pl[MLXSW_REG_MPAT_LEN];
334 int pa_id = span_entry->id;
335
336 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
337 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
338 span_entry->used = false;
339}
340
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200341static struct mlxsw_sp_span_entry *
342mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200343{
344 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
345 int i;
346
347 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
348 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
349
350 if (curr->used && curr->local_port == port->local_port)
351 return curr;
352 }
353 return NULL;
354}
355
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200356static struct mlxsw_sp_span_entry
357*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200358{
359 struct mlxsw_sp_span_entry *span_entry;
360
361 span_entry = mlxsw_sp_span_entry_find(port);
362 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100363 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200364 span_entry->ref_count++;
365 return span_entry;
366 }
367
368 return mlxsw_sp_span_entry_create(port);
369}
370
371static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
372 struct mlxsw_sp_span_entry *span_entry)
373{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100374 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200375 if (--span_entry->ref_count == 0)
376 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
377 return 0;
378}
379
380static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
381{
382 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
383 struct mlxsw_sp_span_inspected_port *p;
384 int i;
385
386 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
387 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
388
389 list_for_each_entry(p, &curr->bound_ports_list, list)
390 if (p->local_port == port->local_port &&
391 p->type == MLXSW_SP_SPAN_EGRESS)
392 return true;
393 }
394
395 return false;
396}
397
Ido Schimmel18281f22017-03-24 08:02:51 +0100398static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
399 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200400{
Ido Schimmel18281f22017-03-24 08:02:51 +0100401 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200402}
403
404static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
405{
406 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
407 char sbib_pl[MLXSW_REG_SBIB_LEN];
408 int err;
409
410 /* If port is egress mirrored, the shared buffer size should be
411 * updated according to the mtu value
412 */
413 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100414 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
415
416 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200417 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
418 if (err) {
419 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
420 return err;
421 }
422 }
423
424 return 0;
425}
426
427static struct mlxsw_sp_span_inspected_port *
428mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
429 struct mlxsw_sp_span_entry *span_entry)
430{
431 struct mlxsw_sp_span_inspected_port *p;
432
433 list_for_each_entry(p, &span_entry->bound_ports_list, list)
434 if (port->local_port == p->local_port)
435 return p;
436 return NULL;
437}
438
439static int
440mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
441 struct mlxsw_sp_span_entry *span_entry,
442 enum mlxsw_sp_span_type type)
443{
444 struct mlxsw_sp_span_inspected_port *inspected_port;
445 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
446 char mpar_pl[MLXSW_REG_MPAR_LEN];
447 char sbib_pl[MLXSW_REG_SBIB_LEN];
448 int pa_id = span_entry->id;
449 int err;
450
451 /* if it is an egress SPAN, bind a shared buffer to it */
452 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100453 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
454 port->dev->mtu);
455
456 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200457 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
458 if (err) {
459 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
460 return err;
461 }
462 }
463
464 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200465 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
466 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200467 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
468 if (err)
469 goto err_mpar_reg_write;
470
471 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
472 if (!inspected_port) {
473 err = -ENOMEM;
474 goto err_inspected_port_alloc;
475 }
476 inspected_port->local_port = port->local_port;
477 inspected_port->type = type;
478 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
479
480 return 0;
481
482err_mpar_reg_write:
483err_inspected_port_alloc:
484 if (type == MLXSW_SP_SPAN_EGRESS) {
485 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
486 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
487 }
488 return err;
489}
490
491static void
492mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
493 struct mlxsw_sp_span_entry *span_entry,
494 enum mlxsw_sp_span_type type)
495{
496 struct mlxsw_sp_span_inspected_port *inspected_port;
497 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
498 char mpar_pl[MLXSW_REG_MPAR_LEN];
499 char sbib_pl[MLXSW_REG_SBIB_LEN];
500 int pa_id = span_entry->id;
501
502 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
503 if (!inspected_port)
504 return;
505
506 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200507 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
508 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200509 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
510
511 /* remove the SBIB buffer if it was egress SPAN */
512 if (type == MLXSW_SP_SPAN_EGRESS) {
513 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
514 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
515 }
516
517 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
518
519 list_del(&inspected_port->list);
520 kfree(inspected_port);
521}
522
523static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
524 struct mlxsw_sp_port *to,
525 enum mlxsw_sp_span_type type)
526{
527 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
528 struct mlxsw_sp_span_entry *span_entry;
529 int err;
530
531 span_entry = mlxsw_sp_span_entry_get(to);
532 if (!span_entry)
533 return -ENOENT;
534
535 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
536 span_entry->id);
537
538 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
539 if (err)
540 goto err_port_bind;
541
542 return 0;
543
544err_port_bind:
545 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
546 return err;
547}
548
549static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
550 struct mlxsw_sp_port *to,
551 enum mlxsw_sp_span_type type)
552{
553 struct mlxsw_sp_span_entry *span_entry;
554
555 span_entry = mlxsw_sp_span_entry_find(to);
556 if (!span_entry) {
557 netdev_err(from->dev, "no span entry found\n");
558 return;
559 }
560
561 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
562 span_entry->id);
563 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
564}
565
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100566static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
567 bool enable, u32 rate)
568{
569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
570 char mpsc_pl[MLXSW_REG_MPSC_LEN];
571
572 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
573 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
574}
575
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200576static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
577 bool is_up)
578{
579 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
580 char paos_pl[MLXSW_REG_PAOS_LEN];
581
582 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
583 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
584 MLXSW_PORT_ADMIN_STATUS_DOWN);
585 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
586}
587
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200588static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
589 unsigned char *addr)
590{
591 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
592 char ppad_pl[MLXSW_REG_PPAD_LEN];
593
594 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
595 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
596 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
597}
598
599static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
600{
601 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
602 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
603
604 ether_addr_copy(addr, mlxsw_sp->base_mac);
605 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
606 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
607}
608
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200609static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
610{
611 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
612 char pmtu_pl[MLXSW_REG_PMTU_LEN];
613 int max_mtu;
614 int err;
615
616 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
617 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
618 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
619 if (err)
620 return err;
621 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
622
623 if (mtu > max_mtu)
624 return -EINVAL;
625
626 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
627 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
628}
629
Ido Schimmelbe945352016-06-09 09:51:39 +0200630static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
631 u8 swid)
632{
633 char pspa_pl[MLXSW_REG_PSPA_LEN];
634
635 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
636 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
637}
638
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200639static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
640{
641 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200642
Ido Schimmelbe945352016-06-09 09:51:39 +0200643 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
644 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200645}
646
647static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
648 bool enable)
649{
650 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
651 char svpe_pl[MLXSW_REG_SVPE_LEN];
652
653 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
654 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
655}
656
657int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
658 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
659 u16 vid)
660{
661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
662 char svfa_pl[MLXSW_REG_SVFA_LEN];
663
664 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
665 fid, vid);
666 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
667}
668
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200669int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
670 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200671{
672 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
673 char *spvmlr_pl;
674 int err;
675
676 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
677 if (!spvmlr_pl)
678 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200679 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
680 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200681 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
682 kfree(spvmlr_pl);
683 return err;
684}
685
Ido Schimmelb02eae92017-05-16 19:38:34 +0200686static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
687 u16 vid)
688{
689 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
690 char spvid_pl[MLXSW_REG_SPVID_LEN];
691
692 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
693 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
694}
695
696static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
697 bool allow)
698{
699 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
700 char spaft_pl[MLXSW_REG_SPAFT_LEN];
701
702 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
703 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
704}
705
706int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
707{
708 int err;
709
710 if (!vid) {
711 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
712 if (err)
713 return err;
714 } else {
715 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
716 if (err)
717 return err;
718 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
719 if (err)
720 goto err_port_allow_untagged_set;
721 }
722
723 mlxsw_sp_port->pvid = vid;
724 return 0;
725
726err_port_allow_untagged_set:
727 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
728 return err;
729}
730
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200731static int
732mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
733{
734 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
735 char sspr_pl[MLXSW_REG_SSPR_LEN];
736
737 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
738 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
739}
740
Ido Schimmeld664b412016-06-09 09:51:40 +0200741static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
742 u8 local_port, u8 *p_module,
743 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200744{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200745 char pmlp_pl[MLXSW_REG_PMLP_LEN];
746 int err;
747
Ido Schimmel558c2d52016-02-26 17:32:29 +0100748 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200749 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
750 if (err)
751 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100752 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
753 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200754 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200755 return 0;
756}
757
Ido Schimmel18f1e702016-02-26 17:32:31 +0100758static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
759 u8 module, u8 width, u8 lane)
760{
761 char pmlp_pl[MLXSW_REG_PMLP_LEN];
762 int i;
763
764 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
765 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
766 for (i = 0; i < width; i++) {
767 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
768 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
769 }
770
771 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
772}
773
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100774static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
775{
776 char pmlp_pl[MLXSW_REG_PMLP_LEN];
777
778 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
779 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
780 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
781}
782
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200783static int mlxsw_sp_port_open(struct net_device *dev)
784{
785 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
786 int err;
787
788 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
789 if (err)
790 return err;
791 netif_start_queue(dev);
792 return 0;
793}
794
795static int mlxsw_sp_port_stop(struct net_device *dev)
796{
797 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
798
799 netif_stop_queue(dev);
800 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
801}
802
803static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
804 struct net_device *dev)
805{
806 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
807 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
808 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
809 const struct mlxsw_tx_info tx_info = {
810 .local_port = mlxsw_sp_port->local_port,
811 .is_emad = false,
812 };
813 u64 len;
814 int err;
815
Jiri Pirko307c2432016-04-08 19:11:22 +0200816 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200817 return NETDEV_TX_BUSY;
818
819 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
820 struct sk_buff *skb_orig = skb;
821
822 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
823 if (!skb) {
824 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
825 dev_kfree_skb_any(skb_orig);
826 return NETDEV_TX_OK;
827 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +0100828 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200829 }
830
831 if (eth_skb_pad(skb)) {
832 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
833 return NETDEV_TX_OK;
834 }
835
836 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200837 /* TX header is consumed by HW on the way so we shouldn't count its
838 * bytes as being sent.
839 */
840 len = skb->len - MLXSW_TXHDR_LEN;
841
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200842 /* Due to a race we might fail here because of a full queue. In that
843 * unlikely case we simply drop the packet.
844 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200845 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200846
847 if (!err) {
848 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
849 u64_stats_update_begin(&pcpu_stats->syncp);
850 pcpu_stats->tx_packets++;
851 pcpu_stats->tx_bytes += len;
852 u64_stats_update_end(&pcpu_stats->syncp);
853 } else {
854 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
855 dev_kfree_skb_any(skb);
856 }
857 return NETDEV_TX_OK;
858}
859
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100860static void mlxsw_sp_set_rx_mode(struct net_device *dev)
861{
862}
863
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200864static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
865{
866 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
867 struct sockaddr *addr = p;
868 int err;
869
870 if (!is_valid_ether_addr(addr->sa_data))
871 return -EADDRNOTAVAIL;
872
873 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
874 if (err)
875 return err;
876 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
877 return 0;
878}
879
Ido Schimmel18281f22017-03-24 08:02:51 +0100880static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
881 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200882{
Ido Schimmel18281f22017-03-24 08:02:51 +0100883 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100884}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200885
Ido Schimmelf417f042017-03-24 08:02:50 +0100886#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +0100887
888static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
889 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +0100890{
Ido Schimmel18281f22017-03-24 08:02:51 +0100891 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
892 BITS_PER_BYTE));
893 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
894 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +0100895}
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200896
Ido Schimmel18281f22017-03-24 08:02:51 +0100897/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +0100898 * Assumes 100m cable and maximum MTU.
899 */
Ido Schimmel18281f22017-03-24 08:02:51 +0100900#define MLXSW_SP_PAUSE_DELAY 58752
901
902static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
903 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +0100904{
905 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +0100906 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +0100907 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +0100908 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200909 else
Ido Schimmelf417f042017-03-24 08:02:50 +0100910 return 0;
911}
912
913static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
914 bool lossy)
915{
916 if (lossy)
917 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
918 else
919 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
920 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200921}
922
923int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200924 u8 *prio_tc, bool pause_en,
925 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200926{
927 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200928 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
929 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200930 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200931 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200932
933 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
934 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
935 if (err)
936 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200937
938 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
939 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200940 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +0100941 bool lossy;
942 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200943
944 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
945 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200946 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200947 configure = true;
948 break;
949 }
950 }
951
952 if (!configure)
953 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +0100954
955 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +0100956 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
957 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
958 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +0100959 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200960 }
961
Ido Schimmelff6551e2016-04-06 17:10:03 +0200962 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
963}
964
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200965static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200966 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200967{
968 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
969 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200970 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200971 u8 *prio_tc;
972
973 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200974 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200975
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200976 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200977 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200978}
979
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200980static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
981{
982 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200983 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200984 int err;
985
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200986 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200987 if (err)
988 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200989 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
990 if (err)
991 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200992 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
993 if (err)
994 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200995 dev->mtu = mtu;
996 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200997
998err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +0200999 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1000err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001001 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001002 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001003}
1004
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001005static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001006mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1007 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001008{
1009 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1010 struct mlxsw_sp_port_pcpu_stats *p;
1011 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1012 u32 tx_dropped = 0;
1013 unsigned int start;
1014 int i;
1015
1016 for_each_possible_cpu(i) {
1017 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1018 do {
1019 start = u64_stats_fetch_begin_irq(&p->syncp);
1020 rx_packets = p->rx_packets;
1021 rx_bytes = p->rx_bytes;
1022 tx_packets = p->tx_packets;
1023 tx_bytes = p->tx_bytes;
1024 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1025
1026 stats->rx_packets += rx_packets;
1027 stats->rx_bytes += rx_bytes;
1028 stats->tx_packets += tx_packets;
1029 stats->tx_bytes += tx_bytes;
1030 /* tx_dropped is u32, updated without syncp protection. */
1031 tx_dropped += p->tx_dropped;
1032 }
1033 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001034 return 0;
1035}
1036
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001037static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001038{
1039 switch (attr_id) {
1040 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1041 return true;
1042 }
1043
1044 return false;
1045}
1046
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001047static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1048 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001049{
1050 switch (attr_id) {
1051 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1052 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1053 }
1054
1055 return -EINVAL;
1056}
1057
1058static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1059 int prio, char *ppcnt_pl)
1060{
1061 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1062 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1063
1064 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1065 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1066}
1067
1068static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1069 struct rtnl_link_stats64 *stats)
1070{
1071 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1072 int err;
1073
1074 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1075 0, ppcnt_pl);
1076 if (err)
1077 goto out;
1078
1079 stats->tx_packets =
1080 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1081 stats->rx_packets =
1082 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1083 stats->tx_bytes =
1084 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1085 stats->rx_bytes =
1086 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1087 stats->multicast =
1088 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1089
1090 stats->rx_crc_errors =
1091 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1092 stats->rx_frame_errors =
1093 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1094
1095 stats->rx_length_errors = (
1096 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1097 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1098 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1099
1100 stats->rx_errors = (stats->rx_crc_errors +
1101 stats->rx_frame_errors + stats->rx_length_errors);
1102
1103out:
1104 return err;
1105}
1106
1107static void update_stats_cache(struct work_struct *work)
1108{
1109 struct mlxsw_sp_port *mlxsw_sp_port =
1110 container_of(work, struct mlxsw_sp_port,
1111 hw_stats.update_dw.work);
1112
1113 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1114 goto out;
1115
1116 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1117 mlxsw_sp_port->hw_stats.cache);
1118
1119out:
1120 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1121 MLXSW_HW_STATS_UPDATE_TIME);
1122}
1123
1124/* Return the stats from a cache that is updated periodically,
1125 * as this function might get called in an atomic context.
1126 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001127static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001128mlxsw_sp_port_get_stats64(struct net_device *dev,
1129 struct rtnl_link_stats64 *stats)
1130{
1131 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1132
1133 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001134}
1135
Jiri Pirko93cd0812017-04-18 16:55:35 +02001136static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1137 u16 vid_begin, u16 vid_end,
1138 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001139{
1140 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1141 char *spvm_pl;
1142 int err;
1143
1144 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1145 if (!spvm_pl)
1146 return -ENOMEM;
1147
1148 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1149 vid_end, is_member, untagged);
1150 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1151 kfree(spvm_pl);
1152 return err;
1153}
1154
Jiri Pirko93cd0812017-04-18 16:55:35 +02001155int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1156 u16 vid_end, bool is_member, bool untagged)
1157{
1158 u16 vid, vid_e;
1159 int err;
1160
1161 for (vid = vid_begin; vid <= vid_end;
1162 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1163 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1164 vid_end);
1165
1166 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1167 is_member, untagged);
1168 if (err)
1169 return err;
1170 }
1171
1172 return 0;
1173}
1174
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001175static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1176{
1177 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1178 u16 vid, last_visited_vid;
1179 int err;
1180
1181 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1182 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1183 vid);
1184 if (err) {
1185 last_visited_vid = vid;
1186 goto err_port_vid_to_fid_set;
1187 }
1188 }
1189
1190 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1191 if (err) {
1192 last_visited_vid = VLAN_N_VID;
1193 goto err_port_vid_to_fid_set;
1194 }
1195
1196 return 0;
1197
1198err_port_vid_to_fid_set:
1199 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1200 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1201 vid);
1202 return err;
1203}
1204
1205static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1206{
1207 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1208 u16 vid;
1209 int err;
1210
1211 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1212 if (err)
1213 return err;
1214
1215 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1216 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1217 vid, vid);
1218 if (err)
1219 return err;
1220 }
1221
1222 return 0;
1223}
1224
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001225static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +02001226mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001227{
1228 struct mlxsw_sp_port *mlxsw_sp_vport;
1229
1230 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1231 if (!mlxsw_sp_vport)
1232 return NULL;
1233
1234 /* dev will be set correctly after the VLAN device is linked
1235 * with the real device. In case of bridge SELF invocation, dev
1236 * will remain as is.
1237 */
1238 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1239 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1240 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1241 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +01001242 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1243 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +02001244 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001245
1246 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1247
1248 return mlxsw_sp_vport;
1249}
1250
1251static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1252{
1253 list_del(&mlxsw_sp_vport->vport.list);
1254 kfree(mlxsw_sp_vport);
1255}
1256
Ido Schimmel05978482016-08-17 16:39:30 +02001257static int mlxsw_sp_port_add_vid(struct net_device *dev,
1258 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001259{
1260 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001261 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +02001262 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001263 int err;
1264
1265 /* VLAN 0 is added to HW filter when device goes up, but it is
1266 * reserved in our case, so simply return.
1267 */
1268 if (!vid)
1269 return 0;
1270
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001271 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001272 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001273
Ido Schimmel0355b592016-06-20 23:04:13 +02001274 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001275 if (!mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02001276 return -ENOMEM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001277
1278 /* When adding the first VLAN interface on a bridged port we need to
1279 * transition all the active 802.1Q bridge VLANs to use explicit
1280 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1281 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001282 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001283 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001284 if (err)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001285 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001286 }
1287
Ido Schimmel52697a92016-07-02 11:00:09 +02001288 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001289 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001290 goto err_port_add_vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001291
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001292 return 0;
1293
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001294err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001295 if (list_is_singular(&mlxsw_sp_port->vports_list))
1296 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1297err_port_vp_mode_trans:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001298 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001299 return err;
1300}
1301
Ido Schimmel32d863f2016-07-02 11:00:10 +02001302static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1303 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001304{
1305 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001306 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +02001307 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001308
1309 /* VLAN 0 is removed from HW filter when device goes down, but
1310 * it is reserved in our case, so simply return.
1311 */
1312 if (!vid)
1313 return 0;
1314
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001315 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel7a355832016-08-17 16:39:28 +02001316 if (WARN_ON(!mlxsw_sp_vport))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001317 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001318
Ido Schimmel7a355832016-08-17 16:39:28 +02001319 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001320
Ido Schimmel1c800752016-06-20 23:04:20 +02001321 /* Drop FID reference. If this was the last reference the
1322 * resources will be freed.
1323 */
1324 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1325 if (f && !WARN_ON(!f->leave))
1326 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001327
1328 /* When removing the last VLAN interface on a bridged port we need to
1329 * transition all active 802.1Q bridge VLANs to use VID to FID
1330 * mappings and set port's mode to VLAN mode.
1331 */
Ido Schimmel7a355832016-08-17 16:39:28 +02001332 if (list_is_singular(&mlxsw_sp_port->vports_list))
1333 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001334
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001335 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1336
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001337 return 0;
1338}
1339
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001340static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1341 size_t len)
1342{
1343 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001344 u8 module = mlxsw_sp_port->mapping.module;
1345 u8 width = mlxsw_sp_port->mapping.width;
1346 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001347 int err;
1348
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001349 if (!mlxsw_sp_port->split)
1350 err = snprintf(name, len, "p%d", module + 1);
1351 else
1352 err = snprintf(name, len, "p%ds%d", module + 1,
1353 lane / width);
1354
1355 if (err >= len)
1356 return -EINVAL;
1357
1358 return 0;
1359}
1360
Yotam Gigi763b4b72016-07-21 12:03:17 +02001361static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001362mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1363 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001364 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1365
1366 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1367 if (mall_tc_entry->cookie == cookie)
1368 return mall_tc_entry;
1369
1370 return NULL;
1371}
1372
1373static int
1374mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001375 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001376 const struct tc_action *a,
1377 bool ingress)
1378{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001379 struct net *net = dev_net(mlxsw_sp_port->dev);
1380 enum mlxsw_sp_span_type span_type;
1381 struct mlxsw_sp_port *to_port;
1382 struct net_device *to_dev;
1383 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001384
1385 ifindex = tcf_mirred_ifindex(a);
1386 to_dev = __dev_get_by_index(net, ifindex);
1387 if (!to_dev) {
1388 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1389 return -EINVAL;
1390 }
1391
1392 if (!mlxsw_sp_port_dev_check(to_dev)) {
1393 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001394 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001395 }
1396 to_port = netdev_priv(to_dev);
1397
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001398 mirror->to_local_port = to_port->local_port;
1399 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001400 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001401 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1402}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001403
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001404static void
1405mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1406 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1407{
1408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1409 enum mlxsw_sp_span_type span_type;
1410 struct mlxsw_sp_port *to_port;
1411
1412 to_port = mlxsw_sp->ports[mirror->to_local_port];
1413 span_type = mirror->ingress ?
1414 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1415 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001416}
1417
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001418static int
1419mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1420 struct tc_cls_matchall_offload *cls,
1421 const struct tc_action *a,
1422 bool ingress)
1423{
1424 int err;
1425
1426 if (!mlxsw_sp_port->sample)
1427 return -EOPNOTSUPP;
1428 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1429 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1430 return -EEXIST;
1431 }
1432 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1433 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1434 return -EOPNOTSUPP;
1435 }
1436
1437 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1438 tcf_sample_psample_group(a));
1439 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1440 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1441 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1442
1443 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1444 if (err)
1445 goto err_port_sample_set;
1446 return 0;
1447
1448err_port_sample_set:
1449 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1450 return err;
1451}
1452
1453static void
1454mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1455{
1456 if (!mlxsw_sp_port->sample)
1457 return;
1458
1459 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1460 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1461}
1462
Yotam Gigi763b4b72016-07-21 12:03:17 +02001463static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1464 __be16 protocol,
1465 struct tc_cls_matchall_offload *cls,
1466 bool ingress)
1467{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001468 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001469 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001470 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001471 int err;
1472
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001473 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001474 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001475 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001476 }
1477
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001478 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1479 if (!mall_tc_entry)
1480 return -ENOMEM;
1481 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001482
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001483 tcf_exts_to_list(cls->exts, &actions);
1484 a = list_first_entry(&actions, struct tc_action, list);
1485
1486 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1487 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1488
1489 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1490 mirror = &mall_tc_entry->mirror;
1491 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1492 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001493 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1494 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1495 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1496 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001497 } else {
1498 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001499 }
1500
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001501 if (err)
1502 goto err_add_action;
1503
1504 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001505 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001506
1507err_add_action:
1508 kfree(mall_tc_entry);
1509 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001510}
1511
1512static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1513 struct tc_cls_matchall_offload *cls)
1514{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001515 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001516
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001517 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1518 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001519 if (!mall_tc_entry) {
1520 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1521 return;
1522 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001523 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001524
1525 switch (mall_tc_entry->type) {
1526 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001527 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1528 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001529 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001530 case MLXSW_SP_PORT_MALL_SAMPLE:
1531 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1532 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001533 default:
1534 WARN_ON(1);
1535 }
1536
Yotam Gigi763b4b72016-07-21 12:03:17 +02001537 kfree(mall_tc_entry);
1538}
1539
1540static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1541 __be16 proto, struct tc_to_netdev *tc)
1542{
1543 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1544 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1545
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001546 switch (tc->type) {
1547 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001548 switch (tc->cls_mall->command) {
1549 case TC_CLSMATCHALL_REPLACE:
1550 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1551 proto,
1552 tc->cls_mall,
1553 ingress);
1554 case TC_CLSMATCHALL_DESTROY:
1555 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1556 tc->cls_mall);
1557 return 0;
1558 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001559 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001560 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001561 case TC_SETUP_CLSFLOWER:
1562 switch (tc->cls_flower->command) {
1563 case TC_CLSFLOWER_REPLACE:
1564 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1565 proto, tc->cls_flower);
1566 case TC_CLSFLOWER_DESTROY:
1567 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1568 tc->cls_flower);
1569 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001570 case TC_CLSFLOWER_STATS:
1571 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1572 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001573 default:
1574 return -EOPNOTSUPP;
1575 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001576 }
1577
Yotam Gigie915ac62017-01-09 11:25:48 +01001578 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001579}
1580
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001581static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1582 .ndo_open = mlxsw_sp_port_open,
1583 .ndo_stop = mlxsw_sp_port_stop,
1584 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001585 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001586 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001587 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1588 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1589 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001590 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1591 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001592 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1593 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1594 .ndo_fdb_add = switchdev_port_fdb_add,
1595 .ndo_fdb_del = switchdev_port_fdb_del,
1596 .ndo_fdb_dump = switchdev_port_fdb_dump,
1597 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1598 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1599 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001600 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001601};
1602
1603static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1604 struct ethtool_drvinfo *drvinfo)
1605{
1606 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1607 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1608
1609 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1610 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1611 sizeof(drvinfo->version));
1612 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1613 "%d.%d.%d",
1614 mlxsw_sp->bus_info->fw_rev.major,
1615 mlxsw_sp->bus_info->fw_rev.minor,
1616 mlxsw_sp->bus_info->fw_rev.subminor);
1617 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1618 sizeof(drvinfo->bus_info));
1619}
1620
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001621static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1622 struct ethtool_pauseparam *pause)
1623{
1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1625
1626 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1627 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1628}
1629
1630static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1631 struct ethtool_pauseparam *pause)
1632{
1633 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1634
1635 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1636 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1637 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1638
1639 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1640 pfcc_pl);
1641}
1642
1643static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1644 struct ethtool_pauseparam *pause)
1645{
1646 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1647 bool pause_en = pause->tx_pause || pause->rx_pause;
1648 int err;
1649
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001650 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1651 netdev_err(dev, "PFC already enabled on port\n");
1652 return -EINVAL;
1653 }
1654
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001655 if (pause->autoneg) {
1656 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1657 return -EINVAL;
1658 }
1659
1660 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1661 if (err) {
1662 netdev_err(dev, "Failed to configure port's headroom\n");
1663 return err;
1664 }
1665
1666 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1667 if (err) {
1668 netdev_err(dev, "Failed to set PAUSE parameters\n");
1669 goto err_port_pause_configure;
1670 }
1671
1672 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1673 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1674
1675 return 0;
1676
1677err_port_pause_configure:
1678 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1679 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1680 return err;
1681}
1682
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001683struct mlxsw_sp_port_hw_stats {
1684 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001685 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001686 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001687};
1688
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001689static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001690 {
1691 .str = "a_frames_transmitted_ok",
1692 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1693 },
1694 {
1695 .str = "a_frames_received_ok",
1696 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1697 },
1698 {
1699 .str = "a_frame_check_sequence_errors",
1700 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1701 },
1702 {
1703 .str = "a_alignment_errors",
1704 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1705 },
1706 {
1707 .str = "a_octets_transmitted_ok",
1708 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1709 },
1710 {
1711 .str = "a_octets_received_ok",
1712 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1713 },
1714 {
1715 .str = "a_multicast_frames_xmitted_ok",
1716 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1717 },
1718 {
1719 .str = "a_broadcast_frames_xmitted_ok",
1720 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1721 },
1722 {
1723 .str = "a_multicast_frames_received_ok",
1724 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1725 },
1726 {
1727 .str = "a_broadcast_frames_received_ok",
1728 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1729 },
1730 {
1731 .str = "a_in_range_length_errors",
1732 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1733 },
1734 {
1735 .str = "a_out_of_range_length_field",
1736 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1737 },
1738 {
1739 .str = "a_frame_too_long_errors",
1740 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1741 },
1742 {
1743 .str = "a_symbol_error_during_carrier",
1744 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1745 },
1746 {
1747 .str = "a_mac_control_frames_transmitted",
1748 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1749 },
1750 {
1751 .str = "a_mac_control_frames_received",
1752 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1753 },
1754 {
1755 .str = "a_unsupported_opcodes_received",
1756 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1757 },
1758 {
1759 .str = "a_pause_mac_ctrl_frames_received",
1760 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1761 },
1762 {
1763 .str = "a_pause_mac_ctrl_frames_xmitted",
1764 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1765 },
1766};
1767
1768#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1769
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001770static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1771 {
1772 .str = "rx_octets_prio",
1773 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1774 },
1775 {
1776 .str = "rx_frames_prio",
1777 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1778 },
1779 {
1780 .str = "tx_octets_prio",
1781 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1782 },
1783 {
1784 .str = "tx_frames_prio",
1785 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1786 },
1787 {
1788 .str = "rx_pause_prio",
1789 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1790 },
1791 {
1792 .str = "rx_pause_duration_prio",
1793 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1794 },
1795 {
1796 .str = "tx_pause_prio",
1797 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1798 },
1799 {
1800 .str = "tx_pause_duration_prio",
1801 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1802 },
1803};
1804
1805#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1806
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001807static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1808 {
1809 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001810 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1811 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001812 },
1813 {
1814 .str = "tc_no_buffer_discard_uc_tc",
1815 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1816 },
1817};
1818
1819#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1820
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001821#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001822 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1823 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001824 IEEE_8021QAZ_MAX_TCS)
1825
1826static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1827{
1828 int i;
1829
1830 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1831 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1832 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1833 *p += ETH_GSTRING_LEN;
1834 }
1835}
1836
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001837static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1838{
1839 int i;
1840
1841 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1842 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1843 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1844 *p += ETH_GSTRING_LEN;
1845 }
1846}
1847
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001848static void mlxsw_sp_port_get_strings(struct net_device *dev,
1849 u32 stringset, u8 *data)
1850{
1851 u8 *p = data;
1852 int i;
1853
1854 switch (stringset) {
1855 case ETH_SS_STATS:
1856 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1857 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1858 ETH_GSTRING_LEN);
1859 p += ETH_GSTRING_LEN;
1860 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001861
1862 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1863 mlxsw_sp_port_get_prio_strings(&p, i);
1864
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001865 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1866 mlxsw_sp_port_get_tc_strings(&p, i);
1867
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001868 break;
1869 }
1870}
1871
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001872static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1873 enum ethtool_phys_id_state state)
1874{
1875 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1877 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1878 bool active;
1879
1880 switch (state) {
1881 case ETHTOOL_ID_ACTIVE:
1882 active = true;
1883 break;
1884 case ETHTOOL_ID_INACTIVE:
1885 active = false;
1886 break;
1887 default:
1888 return -EOPNOTSUPP;
1889 }
1890
1891 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1892 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1893}
1894
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001895static int
1896mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1897 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1898{
1899 switch (grp) {
1900 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1901 *p_hw_stats = mlxsw_sp_port_hw_stats;
1902 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1903 break;
1904 case MLXSW_REG_PPCNT_PRIO_CNT:
1905 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1906 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1907 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001908 case MLXSW_REG_PPCNT_TC_CNT:
1909 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1910 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1911 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001912 default:
1913 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01001914 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001915 }
1916 return 0;
1917}
1918
1919static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1920 enum mlxsw_reg_ppcnt_grp grp, int prio,
1921 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001922{
Ido Schimmel18281f22017-03-24 08:02:51 +01001923 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1924 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001925 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001926 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001927 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001928 int err;
1929
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001930 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1931 if (err)
1932 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001933 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01001934 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01001935 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01001936 if (!hw_stats[i].cells_bytes)
1937 continue;
1938 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
1939 data[data_index + i]);
1940 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001941}
1942
1943static void mlxsw_sp_port_get_stats(struct net_device *dev,
1944 struct ethtool_stats *stats, u64 *data)
1945{
1946 int i, data_index = 0;
1947
1948 /* IEEE 802.3 Counters */
1949 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1950 data, data_index);
1951 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1952
1953 /* Per-Priority Counters */
1954 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1955 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1956 data, data_index);
1957 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1958 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001959
1960 /* Per-TC Counters */
1961 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1962 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1963 data, data_index);
1964 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1965 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001966}
1967
1968static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1969{
1970 switch (sset) {
1971 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001972 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001973 default:
1974 return -EOPNOTSUPP;
1975 }
1976}
1977
1978struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001979 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001980 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001981 u32 speed;
1982};
1983
1984static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1985 {
1986 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001987 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1988 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001989 },
1990 {
1991 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1992 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001993 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1994 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001995 },
1996 {
1997 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02001998 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1999 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002000 },
2001 {
2002 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2003 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002004 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2005 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002006 },
2007 {
2008 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2009 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2010 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2011 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002012 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2013 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002014 },
2015 {
2016 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002017 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2018 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002019 },
2020 {
2021 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002022 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2023 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002024 },
2025 {
2026 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002027 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2028 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002029 },
2030 {
2031 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002032 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2033 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002034 },
2035 {
2036 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002037 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2038 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002039 },
2040 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002041 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2042 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2043 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002044 },
2045 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002046 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2047 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2048 .speed = SPEED_25000,
2049 },
2050 {
2051 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2052 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2053 .speed = SPEED_25000,
2054 },
2055 {
2056 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2057 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2058 .speed = SPEED_25000,
2059 },
2060 {
2061 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2062 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2063 .speed = SPEED_50000,
2064 },
2065 {
2066 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2067 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2068 .speed = SPEED_50000,
2069 },
2070 {
2071 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2072 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2073 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002074 },
2075 {
2076 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002077 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2078 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002079 },
2080 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002081 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2082 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2083 .speed = SPEED_56000,
2084 },
2085 {
2086 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2087 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2088 .speed = SPEED_56000,
2089 },
2090 {
2091 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2092 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2093 .speed = SPEED_56000,
2094 },
2095 {
2096 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2097 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2098 .speed = SPEED_100000,
2099 },
2100 {
2101 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2102 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2103 .speed = SPEED_100000,
2104 },
2105 {
2106 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2107 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2108 .speed = SPEED_100000,
2109 },
2110 {
2111 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2112 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2113 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114 },
2115};
2116
2117#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2118
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002119static void
2120mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2121 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002122{
2123 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2124 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2125 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2126 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2127 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2128 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002129 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002130
2131 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2132 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2133 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2134 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2135 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002136 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002137}
2138
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002139static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002141 int i;
2142
2143 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2144 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002145 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2146 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002147 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002148}
2149
2150static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002151 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002152{
2153 u32 speed = SPEED_UNKNOWN;
2154 u8 duplex = DUPLEX_UNKNOWN;
2155 int i;
2156
2157 if (!carrier_ok)
2158 goto out;
2159
2160 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2161 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2162 speed = mlxsw_sp_port_link_mode[i].speed;
2163 duplex = DUPLEX_FULL;
2164 break;
2165 }
2166 }
2167out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002168 cmd->base.speed = speed;
2169 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002170}
2171
2172static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2173{
2174 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2175 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2176 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2177 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2178 return PORT_FIBRE;
2179
2180 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2181 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2182 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2183 return PORT_DA;
2184
2185 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2186 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2187 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2188 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2189 return PORT_NONE;
2190
2191 return PORT_OTHER;
2192}
2193
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002194static u32
2195mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002196{
2197 u32 ptys_proto = 0;
2198 int i;
2199
2200 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002201 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2202 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002203 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2204 }
2205 return ptys_proto;
2206}
2207
2208static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2209{
2210 u32 ptys_proto = 0;
2211 int i;
2212
2213 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2214 if (speed == mlxsw_sp_port_link_mode[i].speed)
2215 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2216 }
2217 return ptys_proto;
2218}
2219
Ido Schimmel18f1e702016-02-26 17:32:31 +01002220static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2221{
2222 u32 ptys_proto = 0;
2223 int i;
2224
2225 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2226 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2227 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2228 }
2229 return ptys_proto;
2230}
2231
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002232static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2233 struct ethtool_link_ksettings *cmd)
2234{
2235 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2236 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2237 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2238
2239 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2240 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2241}
2242
2243static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2244 struct ethtool_link_ksettings *cmd)
2245{
2246 if (!autoneg)
2247 return;
2248
2249 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2250 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2251}
2252
2253static void
2254mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2255 struct ethtool_link_ksettings *cmd)
2256{
2257 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2258 return;
2259
2260 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2261 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2262}
2263
2264static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2265 struct ethtool_link_ksettings *cmd)
2266{
2267 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2268 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2270 char ptys_pl[MLXSW_REG_PTYS_LEN];
2271 u8 autoneg_status;
2272 bool autoneg;
2273 int err;
2274
2275 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002276 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002277 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2278 if (err)
2279 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002280 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2281 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002282
2283 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2284
2285 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2286
2287 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2288 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2289 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2290
2291 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2292 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2293 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2294 cmd);
2295
2296 return 0;
2297}
2298
2299static int
2300mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2301 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002302{
2303 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2304 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2305 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002306 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002307 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002308 int err;
2309
Elad Raz401c8b42016-10-28 21:35:52 +02002310 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002311 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002312 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002313 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002314 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002315
2316 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2317 eth_proto_new = autoneg ?
2318 mlxsw_sp_to_ptys_advert_link(cmd) :
2319 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002320
2321 eth_proto_new = eth_proto_new & eth_proto_cap;
2322 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002323 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324 return -EINVAL;
2325 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002326
Elad Raz401c8b42016-10-28 21:35:52 +02002327 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2328 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002329 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002330 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002331 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002332
Ido Schimmel6277d462016-07-15 11:14:58 +02002333 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002334 return 0;
2335
Ido Schimmel0c83f882016-09-12 13:26:23 +02002336 mlxsw_sp_port->link.autoneg = autoneg;
2337
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002338 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2339 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002340
2341 return 0;
2342}
2343
2344static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2345 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2346 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002347 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2348 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002349 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002350 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002351 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2352 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002353 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2354 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002355};
2356
Ido Schimmel18f1e702016-02-26 17:32:31 +01002357static int
2358mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2359{
2360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2361 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2362 char ptys_pl[MLXSW_REG_PTYS_LEN];
2363 u32 eth_proto_admin;
2364
2365 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002366 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2367 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002368 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2369}
2370
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002371int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2372 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2373 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002374{
2375 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2376 char qeec_pl[MLXSW_REG_QEEC_LEN];
2377
2378 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2379 next_index);
2380 mlxsw_reg_qeec_de_set(qeec_pl, true);
2381 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2382 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2383 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2384}
2385
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002386int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2387 enum mlxsw_reg_qeec_hr hr, u8 index,
2388 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002389{
2390 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2391 char qeec_pl[MLXSW_REG_QEEC_LEN];
2392
2393 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2394 next_index);
2395 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2396 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2398}
2399
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002400int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2401 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002402{
2403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2404 char qtct_pl[MLXSW_REG_QTCT_LEN];
2405
2406 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2407 tclass);
2408 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2409}
2410
2411static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2412{
2413 int err, i;
2414
2415 /* Setup the elements hierarcy, so that each TC is linked to
2416 * one subgroup, which are all member in the same group.
2417 */
2418 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2419 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2420 0);
2421 if (err)
2422 return err;
2423 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2424 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2425 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2426 0, false, 0);
2427 if (err)
2428 return err;
2429 }
2430 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2431 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2432 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2433 false, 0);
2434 if (err)
2435 return err;
2436 }
2437
2438 /* Make sure the max shaper is disabled in all hierarcies that
2439 * support it.
2440 */
2441 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2442 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2443 MLXSW_REG_QEEC_MAS_DIS);
2444 if (err)
2445 return err;
2446 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2447 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2448 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2449 i, 0,
2450 MLXSW_REG_QEEC_MAS_DIS);
2451 if (err)
2452 return err;
2453 }
2454 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2455 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2456 MLXSW_REG_QEEC_HIERARCY_TC,
2457 i, i,
2458 MLXSW_REG_QEEC_MAS_DIS);
2459 if (err)
2460 return err;
2461 }
2462
2463 /* Map all priorities to traffic class 0. */
2464 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2465 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2466 if (err)
2467 return err;
2468 }
2469
2470 return 0;
2471}
2472
Ido Schimmel05978482016-08-17 16:39:30 +02002473static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2474{
2475 mlxsw_sp_port->pvid = 1;
2476
2477 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2478}
2479
2480static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2481{
2482 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2483}
2484
Jiri Pirko67963a32016-10-28 21:35:55 +02002485static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2486 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002487{
2488 struct mlxsw_sp_port *mlxsw_sp_port;
2489 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002490 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002491 int err;
2492
2493 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2494 if (!dev)
2495 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002496 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002497 mlxsw_sp_port = netdev_priv(dev);
2498 mlxsw_sp_port->dev = dev;
2499 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2500 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002501 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002502 mlxsw_sp_port->mapping.module = module;
2503 mlxsw_sp_port->mapping.width = width;
2504 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002505 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002506 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2507 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2508 if (!mlxsw_sp_port->active_vlans) {
2509 err = -ENOMEM;
2510 goto err_port_active_vlans_alloc;
2511 }
Elad Razfc1273a2016-01-06 13:01:11 +01002512 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2513 if (!mlxsw_sp_port->untagged_vlans) {
2514 err = -ENOMEM;
2515 goto err_port_untagged_vlans_alloc;
2516 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002517 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002518 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002519
2520 mlxsw_sp_port->pcpu_stats =
2521 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2522 if (!mlxsw_sp_port->pcpu_stats) {
2523 err = -ENOMEM;
2524 goto err_alloc_stats;
2525 }
2526
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002527 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2528 GFP_KERNEL);
2529 if (!mlxsw_sp_port->sample) {
2530 err = -ENOMEM;
2531 goto err_alloc_sample;
2532 }
2533
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002534 mlxsw_sp_port->hw_stats.cache =
2535 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2536
2537 if (!mlxsw_sp_port->hw_stats.cache) {
2538 err = -ENOMEM;
2539 goto err_alloc_hw_stats;
2540 }
2541 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2542 &update_stats_cache);
2543
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002544 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2545 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2546
Ido Schimmel3247ff22016-09-08 08:16:02 +02002547 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2548 if (err) {
2549 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2550 mlxsw_sp_port->local_port);
2551 goto err_port_swid_set;
2552 }
2553
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002554 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2555 if (err) {
2556 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2557 mlxsw_sp_port->local_port);
2558 goto err_dev_addr_init;
2559 }
2560
2561 netif_carrier_off(dev);
2562
2563 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002564 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2565 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002566
Jarod Wilsond894be52016-10-20 13:55:16 -04002567 dev->min_mtu = 0;
2568 dev->max_mtu = ETH_MAX_MTU;
2569
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002570 /* Each packet needs to have a Tx header (metadata) on top all other
2571 * headers.
2572 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002573 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002574
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002575 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2576 if (err) {
2577 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2578 mlxsw_sp_port->local_port);
2579 goto err_port_system_port_mapping_set;
2580 }
2581
Ido Schimmel18f1e702016-02-26 17:32:31 +01002582 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2583 if (err) {
2584 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2585 mlxsw_sp_port->local_port);
2586 goto err_port_speed_by_width_set;
2587 }
2588
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002589 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2590 if (err) {
2591 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2592 mlxsw_sp_port->local_port);
2593 goto err_port_mtu_set;
2594 }
2595
2596 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2597 if (err)
2598 goto err_port_admin_status_set;
2599
2600 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2601 if (err) {
2602 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2603 mlxsw_sp_port->local_port);
2604 goto err_port_buffers_init;
2605 }
2606
Ido Schimmel90183b92016-04-06 17:10:08 +02002607 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2608 if (err) {
2609 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2610 mlxsw_sp_port->local_port);
2611 goto err_port_ets_init;
2612 }
2613
Ido Schimmelf00817d2016-04-06 17:10:09 +02002614 /* ETS and buffers must be initialized before DCB. */
2615 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2616 if (err) {
2617 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2618 mlxsw_sp_port->local_port);
2619 goto err_port_dcb_init;
2620 }
2621
Ido Schimmel45a4a162017-05-16 19:38:35 +02002622 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2623 if (err) {
2624 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set non-virtual mode\n",
2625 mlxsw_sp_port->local_port);
2626 goto err_port_vp_mode_set;
2627 }
2628
Ido Schimmel05978482016-08-17 16:39:30 +02002629 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2630 if (err) {
2631 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2632 mlxsw_sp_port->local_port);
2633 goto err_port_pvid_vport_create;
2634 }
2635
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002636 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002637 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002638 err = register_netdev(dev);
2639 if (err) {
2640 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2641 mlxsw_sp_port->local_port);
2642 goto err_register_netdev;
2643 }
2644
Elad Razd808c7e2016-10-28 21:35:57 +02002645 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2646 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2647 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002648 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002649 return 0;
2650
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002651err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002652 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002653 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002654 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2655err_port_pvid_vport_create:
Ido Schimmel45a4a162017-05-16 19:38:35 +02002656err_port_vp_mode_set:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002657 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002658err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002659err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002660err_port_buffers_init:
2661err_port_admin_status_set:
2662err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002663err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002664err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002665err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002666 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2667err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002668 kfree(mlxsw_sp_port->hw_stats.cache);
2669err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002670 kfree(mlxsw_sp_port->sample);
2671err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002672 free_percpu(mlxsw_sp_port->pcpu_stats);
2673err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01002674 kfree(mlxsw_sp_port->untagged_vlans);
2675err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002676 kfree(mlxsw_sp_port->active_vlans);
2677err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002678 free_netdev(dev);
2679 return err;
2680}
2681
Jiri Pirko67963a32016-10-28 21:35:55 +02002682static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2683 bool split, u8 module, u8 width, u8 lane)
2684{
2685 int err;
2686
2687 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2688 if (err) {
2689 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2690 local_port);
2691 return err;
2692 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002693 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002694 module, width, lane);
2695 if (err)
2696 goto err_port_create;
2697 return 0;
2698
2699err_port_create:
2700 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2701 return err;
2702}
2703
2704static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002705{
2706 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2707
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002708 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002709 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002710 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002711 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002712 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002713 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002714 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002715 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2716 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002717 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002718 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002719 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01002720 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002721 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02002722 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002723 free_netdev(mlxsw_sp_port->dev);
2724}
2725
Jiri Pirko67963a32016-10-28 21:35:55 +02002726static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2727{
2728 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2729 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2730}
2731
Jiri Pirkof83e2102016-10-28 21:35:49 +02002732static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2733{
2734 return mlxsw_sp->ports[local_port] != NULL;
2735}
2736
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002737static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2738{
2739 int i;
2740
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002741 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002742 if (mlxsw_sp_port_created(mlxsw_sp, i))
2743 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002744 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002745 kfree(mlxsw_sp->ports);
2746}
2747
2748static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2749{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002750 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002751 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002752 size_t alloc_size;
2753 int i;
2754 int err;
2755
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002756 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002757 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2758 if (!mlxsw_sp->ports)
2759 return -ENOMEM;
2760
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002761 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2762 if (!mlxsw_sp->port_to_module) {
2763 err = -ENOMEM;
2764 goto err_port_to_module_alloc;
2765 }
2766
2767 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002768 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002769 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002770 if (err)
2771 goto err_port_module_info_get;
2772 if (!width)
2773 continue;
2774 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002775 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2776 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002777 if (err)
2778 goto err_port_create;
2779 }
2780 return 0;
2781
2782err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002783err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002784 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002785 if (mlxsw_sp_port_created(mlxsw_sp, i))
2786 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002787 kfree(mlxsw_sp->port_to_module);
2788err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002789 kfree(mlxsw_sp->ports);
2790 return err;
2791}
2792
Ido Schimmel18f1e702016-02-26 17:32:31 +01002793static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2794{
2795 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2796
2797 return local_port - offset;
2798}
2799
Ido Schimmelbe945352016-06-09 09:51:39 +02002800static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2801 u8 module, unsigned int count)
2802{
2803 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2804 int err, i;
2805
2806 for (i = 0; i < count; i++) {
2807 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2808 width, i * width);
2809 if (err)
2810 goto err_port_module_map;
2811 }
2812
2813 for (i = 0; i < count; i++) {
2814 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2815 if (err)
2816 goto err_port_swid_set;
2817 }
2818
2819 for (i = 0; i < count; i++) {
2820 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02002821 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02002822 if (err)
2823 goto err_port_create;
2824 }
2825
2826 return 0;
2827
2828err_port_create:
2829 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002830 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2831 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02002832 i = count;
2833err_port_swid_set:
2834 for (i--; i >= 0; i--)
2835 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2836 MLXSW_PORT_SWID_DISABLED_PORT);
2837 i = count;
2838err_port_module_map:
2839 for (i--; i >= 0; i--)
2840 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2841 return err;
2842}
2843
2844static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2845 u8 base_port, unsigned int count)
2846{
2847 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2848 int i;
2849
2850 /* Split by four means we need to re-create two ports, otherwise
2851 * only one.
2852 */
2853 count = count / 2;
2854
2855 for (i = 0; i < count; i++) {
2856 local_port = base_port + i * 2;
2857 module = mlxsw_sp->port_to_module[local_port];
2858
2859 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2860 0);
2861 }
2862
2863 for (i = 0; i < count; i++)
2864 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2865
2866 for (i = 0; i < count; i++) {
2867 local_port = base_port + i * 2;
2868 module = mlxsw_sp->port_to_module[local_port];
2869
2870 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002871 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02002872 }
2873}
2874
Jiri Pirkob2f10572016-04-08 19:11:23 +02002875static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2876 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002877{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002878 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002879 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002880 u8 module, cur_width, base_port;
2881 int i;
2882 int err;
2883
2884 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2885 if (!mlxsw_sp_port) {
2886 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2887 local_port);
2888 return -EINVAL;
2889 }
2890
Ido Schimmeld664b412016-06-09 09:51:40 +02002891 module = mlxsw_sp_port->mapping.module;
2892 cur_width = mlxsw_sp_port->mapping.width;
2893
Ido Schimmel18f1e702016-02-26 17:32:31 +01002894 if (count != 2 && count != 4) {
2895 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2896 return -EINVAL;
2897 }
2898
Ido Schimmel18f1e702016-02-26 17:32:31 +01002899 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2900 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2901 return -EINVAL;
2902 }
2903
2904 /* Make sure we have enough slave (even) ports for the split. */
2905 if (count == 2) {
2906 base_port = local_port;
2907 if (mlxsw_sp->ports[base_port + 1]) {
2908 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2909 return -EINVAL;
2910 }
2911 } else {
2912 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2913 if (mlxsw_sp->ports[base_port + 1] ||
2914 mlxsw_sp->ports[base_port + 3]) {
2915 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2916 return -EINVAL;
2917 }
2918 }
2919
2920 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002921 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2922 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002923
Ido Schimmelbe945352016-06-09 09:51:39 +02002924 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2925 if (err) {
2926 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2927 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002928 }
2929
2930 return 0;
2931
Ido Schimmelbe945352016-06-09 09:51:39 +02002932err_port_split_create:
2933 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002934 return err;
2935}
2936
Jiri Pirkob2f10572016-04-08 19:11:23 +02002937static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002938{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002939 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002940 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002941 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002942 unsigned int count;
2943 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002944
2945 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2946 if (!mlxsw_sp_port) {
2947 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2948 local_port);
2949 return -EINVAL;
2950 }
2951
2952 if (!mlxsw_sp_port->split) {
2953 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2954 return -EINVAL;
2955 }
2956
Ido Schimmeld664b412016-06-09 09:51:40 +02002957 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002958 count = cur_width == 1 ? 4 : 2;
2959
2960 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2961
2962 /* Determine which ports to remove. */
2963 if (count == 2 && local_port >= base_port + 2)
2964 base_port = base_port + 2;
2965
2966 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002967 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2968 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002969
Ido Schimmelbe945352016-06-09 09:51:39 +02002970 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002971
2972 return 0;
2973}
2974
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002975static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2976 char *pude_pl, void *priv)
2977{
2978 struct mlxsw_sp *mlxsw_sp = priv;
2979 struct mlxsw_sp_port *mlxsw_sp_port;
2980 enum mlxsw_reg_pude_oper_status status;
2981 u8 local_port;
2982
2983 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2984 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002985 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002986 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002987
2988 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2989 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2990 netdev_info(mlxsw_sp_port->dev, "link up\n");
2991 netif_carrier_on(mlxsw_sp_port->dev);
2992 } else {
2993 netdev_info(mlxsw_sp_port->dev, "link down\n");
2994 netif_carrier_off(mlxsw_sp_port->dev);
2995 }
2996}
2997
Nogah Frankel14eeda92016-11-25 10:33:32 +01002998static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2999 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003000{
3001 struct mlxsw_sp *mlxsw_sp = priv;
3002 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3003 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3004
3005 if (unlikely(!mlxsw_sp_port)) {
3006 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3007 local_port);
3008 return;
3009 }
3010
3011 skb->dev = mlxsw_sp_port->dev;
3012
3013 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3014 u64_stats_update_begin(&pcpu_stats->syncp);
3015 pcpu_stats->rx_packets++;
3016 pcpu_stats->rx_bytes += skb->len;
3017 u64_stats_update_end(&pcpu_stats->syncp);
3018
3019 skb->protocol = eth_type_trans(skb, skb->dev);
3020 netif_receive_skb(skb);
3021}
3022
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003023static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3024 void *priv)
3025{
3026 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003027 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003028}
3029
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003030static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3031 void *priv)
3032{
3033 struct mlxsw_sp *mlxsw_sp = priv;
3034 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3035 struct psample_group *psample_group;
3036 u32 size;
3037
3038 if (unlikely(!mlxsw_sp_port)) {
3039 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3040 local_port);
3041 goto out;
3042 }
3043 if (unlikely(!mlxsw_sp_port->sample)) {
3044 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3045 local_port);
3046 goto out;
3047 }
3048
3049 size = mlxsw_sp_port->sample->truncate ?
3050 mlxsw_sp_port->sample->trunc_size : skb->len;
3051
3052 rcu_read_lock();
3053 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3054 if (!psample_group)
3055 goto out_unlock;
3056 psample_sample_packet(psample_group, skb, size,
3057 mlxsw_sp_port->dev->ifindex, 0,
3058 mlxsw_sp_port->sample->rate);
3059out_unlock:
3060 rcu_read_unlock();
3061out:
3062 consume_skb(skb);
3063}
3064
Nogah Frankel117b0da2016-11-25 10:33:44 +01003065#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003066 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003067 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003068
Nogah Frankel117b0da2016-11-25 10:33:44 +01003069#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003070 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003071 _is_ctrl, SP_##_trap_group, DISCARD)
3072
3073#define MLXSW_SP_EVENTL(_func, _trap_id) \
3074 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003075
Nogah Frankel45449132016-11-25 10:33:35 +01003076static const struct mlxsw_listener mlxsw_sp_listener[] = {
3077 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003078 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003079 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003080 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3081 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3082 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3083 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3084 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3085 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3086 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3087 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3088 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3089 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3090 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003091 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003092 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003093 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3094 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3095 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3096 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3097 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3098 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3099 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3100 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003101 /* PKT Sample trap */
3102 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3103 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003104};
3105
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003106static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3107{
3108 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3109 enum mlxsw_reg_qpcr_ir_units ir_units;
3110 int max_cpu_policers;
3111 bool is_bytes;
3112 u8 burst_size;
3113 u32 rate;
3114 int i, err;
3115
3116 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3117 return -EIO;
3118
3119 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3120
3121 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3122 for (i = 0; i < max_cpu_policers; i++) {
3123 is_bytes = false;
3124 switch (i) {
3125 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3126 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3127 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3128 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3129 rate = 128;
3130 burst_size = 7;
3131 break;
3132 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3133 rate = 16 * 1024;
3134 burst_size = 10;
3135 break;
3136 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3137 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3138 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3139 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3140 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3141 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3142 rate = 1024;
3143 burst_size = 7;
3144 break;
3145 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3146 is_bytes = true;
3147 rate = 4 * 1024;
3148 burst_size = 4;
3149 break;
3150 default:
3151 continue;
3152 }
3153
3154 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3155 burst_size);
3156 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3157 if (err)
3158 return err;
3159 }
3160
3161 return 0;
3162}
3163
Nogah Frankel579c82e2016-11-25 10:33:42 +01003164static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003165{
3166 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003167 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003168 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003169 int max_trap_groups;
3170 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003171 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003172 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003173
3174 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3175 return -EIO;
3176
3177 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003178 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003179
3180 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003181 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003182 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003183 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3184 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3185 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3186 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3187 priority = 5;
3188 tc = 5;
3189 break;
3190 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3191 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3192 priority = 4;
3193 tc = 4;
3194 break;
3195 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3196 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3197 priority = 3;
3198 tc = 3;
3199 break;
3200 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3201 priority = 2;
3202 tc = 2;
3203 break;
3204 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3205 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3206 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3207 priority = 1;
3208 tc = 1;
3209 break;
3210 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003211 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3212 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003213 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003214 break;
3215 default:
3216 continue;
3217 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003218
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003219 if (max_cpu_policers <= policer_id &&
3220 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3221 return -EIO;
3222
3223 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003224 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3225 if (err)
3226 return err;
3227 }
3228
3229 return 0;
3230}
3231
3232static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3233{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003234 int i;
3235 int err;
3236
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003237 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3238 if (err)
3239 return err;
3240
Nogah Frankel579c82e2016-11-25 10:33:42 +01003241 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003242 if (err)
3243 return err;
3244
Nogah Frankel45449132016-11-25 10:33:35 +01003245 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003246 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003247 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003248 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003249 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003250 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003251
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003252 }
3253 return 0;
3254
Nogah Frankel45449132016-11-25 10:33:35 +01003255err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003256 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003257 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003258 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003259 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003260 }
3261 return err;
3262}
3263
3264static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3265{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003266 int i;
3267
Nogah Frankel45449132016-11-25 10:33:35 +01003268 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003269 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003270 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003271 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003272 }
3273}
3274
3275static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3276 enum mlxsw_reg_sfgc_type type,
3277 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3278{
3279 enum mlxsw_flood_table_type table_type;
3280 enum mlxsw_sp_flood_table flood_table;
3281 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3282
Ido Schimmel19ae6122015-12-15 16:03:39 +01003283 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003284 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003285 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003286 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003287
Nogah Frankel71c365b2017-02-09 14:54:46 +01003288 switch (type) {
3289 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003290 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003291 break;
3292 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003293 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3294 break;
3295 default:
3296 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3297 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003298
3299 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3300 flood_table);
3301 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3302}
3303
3304static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3305{
3306 int type, err;
3307
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003308 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3309 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3310 continue;
3311
3312 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3313 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3314 if (err)
3315 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003316
3317 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3318 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3319 if (err)
3320 return err;
3321 }
3322
3323 return 0;
3324}
3325
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003326static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3327{
3328 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003329 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003330
3331 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3332 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3333 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3334 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3335 MLXSW_REG_SLCR_LAG_HASH_SIP |
3336 MLXSW_REG_SLCR_LAG_HASH_DIP |
3337 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3338 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3339 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003340 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3341 if (err)
3342 return err;
3343
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003344 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3345 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003346 return -EIO;
3347
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003348 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003349 sizeof(struct mlxsw_sp_upper),
3350 GFP_KERNEL);
3351 if (!mlxsw_sp->lags)
3352 return -ENOMEM;
3353
3354 return 0;
3355}
3356
3357static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3358{
3359 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003360}
3361
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003362static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3363{
3364 char htgt_pl[MLXSW_REG_HTGT_LEN];
3365
Nogah Frankel579c82e2016-11-25 10:33:42 +01003366 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3367 MLXSW_REG_HTGT_INVALID_POLICER,
3368 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3369 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003370 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3371}
3372
Jiri Pirko202d6f42017-04-18 16:55:33 +02003373static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create);
3374
3375static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3376{
3377 return mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
3378}
3379
3380static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3381{
3382 mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
3383}
3384
Jiri Pirkob2f10572016-04-08 19:11:23 +02003385static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003386 const struct mlxsw_bus_info *mlxsw_bus_info)
3387{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003388 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003389 int err;
3390
3391 mlxsw_sp->core = mlxsw_core;
3392 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003393 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003394 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003395
3396 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3397 if (err) {
3398 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3399 return err;
3400 }
3401
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003402 err = mlxsw_sp_traps_init(mlxsw_sp);
3403 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003404 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3405 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003406 }
3407
3408 err = mlxsw_sp_flood_init(mlxsw_sp);
3409 if (err) {
3410 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3411 goto err_flood_init;
3412 }
3413
3414 err = mlxsw_sp_buffers_init(mlxsw_sp);
3415 if (err) {
3416 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3417 goto err_buffers_init;
3418 }
3419
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003420 err = mlxsw_sp_lag_init(mlxsw_sp);
3421 if (err) {
3422 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3423 goto err_lag_init;
3424 }
3425
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003426 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3427 if (err) {
3428 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3429 goto err_switchdev_init;
3430 }
3431
Ido Schimmel464dce12016-07-02 11:00:15 +02003432 err = mlxsw_sp_router_init(mlxsw_sp);
3433 if (err) {
3434 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3435 goto err_router_init;
3436 }
3437
Yotam Gigi763b4b72016-07-21 12:03:17 +02003438 err = mlxsw_sp_span_init(mlxsw_sp);
3439 if (err) {
3440 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3441 goto err_span_init;
3442 }
3443
Jiri Pirko22a67762017-02-03 10:29:07 +01003444 err = mlxsw_sp_acl_init(mlxsw_sp);
3445 if (err) {
3446 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3447 goto err_acl_init;
3448 }
3449
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003450 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3451 if (err) {
3452 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3453 goto err_counter_pool_init;
3454 }
3455
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003456 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3457 if (err) {
3458 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3459 goto err_dpipe_init;
3460 }
3461
Jiri Pirko202d6f42017-04-18 16:55:33 +02003462 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3463 if (err) {
3464 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3465 goto err_dummy_fid_init;
3466 }
3467
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003468 err = mlxsw_sp_ports_create(mlxsw_sp);
3469 if (err) {
3470 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3471 goto err_ports_create;
3472 }
3473
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003474 return 0;
3475
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003476err_ports_create:
Jiri Pirko202d6f42017-04-18 16:55:33 +02003477 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3478err_dummy_fid_init:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003479 mlxsw_sp_dpipe_fini(mlxsw_sp);
3480err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003481 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3482err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003483 mlxsw_sp_acl_fini(mlxsw_sp);
3484err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003485 mlxsw_sp_span_fini(mlxsw_sp);
3486err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003487 mlxsw_sp_router_fini(mlxsw_sp);
3488err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003489 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003490err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003491 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003492err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003493 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003494err_buffers_init:
3495err_flood_init:
3496 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003497 return err;
3498}
3499
Jiri Pirkob2f10572016-04-08 19:11:23 +02003500static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003501{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003502 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003503
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003504 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003505 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003506 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003507 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003508 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003509 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003510 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003511 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003512 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003513 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003514 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003515 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003516 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003517}
3518
3519static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3520 .used_max_vepa_channels = 1,
3521 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003522 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003523 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003524 .used_max_pgt = 1,
3525 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003526 .used_flood_tables = 1,
3527 .used_flood_mode = 1,
3528 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003529 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003530 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003531 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003532 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003533 .used_max_ib_mc = 1,
3534 .max_ib_mc = 0,
3535 .used_max_pkey = 1,
3536 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003537 .used_kvd_split_data = 1,
3538 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3539 .kvd_hash_single_parts = 2,
3540 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003541 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542 .swid_config = {
3543 {
3544 .used_type = 1,
3545 .type = MLXSW_PORT_SWID_TYPE_ETH,
3546 }
3547 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003548 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003549};
3550
3551static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003552 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003553 .priv_size = sizeof(struct mlxsw_sp),
3554 .init = mlxsw_sp_init,
3555 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003556 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003557 .port_split = mlxsw_sp_port_split,
3558 .port_unsplit = mlxsw_sp_port_unsplit,
3559 .sb_pool_get = mlxsw_sp_sb_pool_get,
3560 .sb_pool_set = mlxsw_sp_sb_pool_set,
3561 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3562 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3563 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3564 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3565 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3566 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3567 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3568 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3569 .txhdr_construct = mlxsw_sp_txhdr_construct,
3570 .txhdr_len = MLXSW_TXHDR_LEN,
3571 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003572};
3573
Jiri Pirko22a67762017-02-03 10:29:07 +01003574bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003575{
3576 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3577}
3578
Jiri Pirko1182e532017-03-06 21:25:20 +01003579static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003580{
Jiri Pirko1182e532017-03-06 21:25:20 +01003581 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003582 int ret = 0;
3583
3584 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003585 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003586 ret = 1;
3587 }
3588
3589 return ret;
3590}
3591
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003592static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3593{
Jiri Pirko1182e532017-03-06 21:25:20 +01003594 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003595
3596 if (mlxsw_sp_port_dev_check(dev))
3597 return netdev_priv(dev);
3598
Jiri Pirko1182e532017-03-06 21:25:20 +01003599 mlxsw_sp_port = NULL;
3600 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003601
Jiri Pirko1182e532017-03-06 21:25:20 +01003602 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003603}
3604
Ido Schimmel4724ba562017-03-10 08:53:39 +01003605struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003606{
3607 struct mlxsw_sp_port *mlxsw_sp_port;
3608
3609 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3610 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3611}
3612
3613static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3614{
Jiri Pirko1182e532017-03-06 21:25:20 +01003615 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003616
3617 if (mlxsw_sp_port_dev_check(dev))
3618 return netdev_priv(dev);
3619
Jiri Pirko1182e532017-03-06 21:25:20 +01003620 mlxsw_sp_port = NULL;
3621 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3622 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003623
Jiri Pirko1182e532017-03-06 21:25:20 +01003624 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003625}
3626
3627struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3628{
3629 struct mlxsw_sp_port *mlxsw_sp_port;
3630
3631 rcu_read_lock();
3632 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3633 if (mlxsw_sp_port)
3634 dev_hold(mlxsw_sp_port->dev);
3635 rcu_read_unlock();
3636 return mlxsw_sp_port;
3637}
3638
3639void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3640{
3641 dev_put(mlxsw_sp_port->dev);
3642}
3643
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003644static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3645 u16 fid)
3646{
3647 if (mlxsw_sp_fid_is_vfid(fid))
3648 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3649 else
3650 return test_bit(fid, lag_port->active_vlans);
3651}
3652
3653static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3654 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003655{
3656 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003657 u8 local_port = mlxsw_sp_port->local_port;
3658 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003659 u64 max_lag_members;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003660 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003661
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003662 if (!mlxsw_sp_port->lagged)
3663 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003664
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003665 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3666 MAX_LAG_MEMBERS);
3667 for (i = 0; i < max_lag_members; i++) {
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003668 struct mlxsw_sp_port *lag_port;
3669
3670 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3671 if (!lag_port || lag_port->local_port == local_port)
3672 continue;
3673 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3674 count++;
3675 }
3676
3677 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003678}
3679
3680static int
3681mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3682 u16 fid)
3683{
3684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3685 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3686
3687 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3688 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3689 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3690 mlxsw_sp_port->local_port);
3691
Ido Schimmel22305372016-06-20 23:04:21 +02003692 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3693 mlxsw_sp_port->local_port, fid);
3694
Ido Schimmel039c49a2016-01-27 15:20:18 +01003695 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3696}
3697
3698static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003699mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3700 u16 fid)
3701{
3702 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3703 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3704
3705 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3706 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3707 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3708
Ido Schimmel22305372016-06-20 23:04:21 +02003709 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3710 mlxsw_sp_port->lag_id, fid);
3711
Ido Schimmel039c49a2016-01-27 15:20:18 +01003712 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3713}
3714
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003715int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003716{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003717 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3718 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003719
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003720 if (mlxsw_sp_port->lagged)
3721 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003722 fid);
3723 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003724 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003725}
3726
Ido Schimmel701b1862016-07-04 08:23:16 +02003727static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3728{
3729 struct mlxsw_sp_fid *f, *tmp;
3730
3731 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3732 if (--f->ref_count == 0)
3733 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3734 else
3735 WARN_ON_ONCE(1);
3736}
3737
Ido Schimmel7117a572016-06-20 23:04:06 +02003738static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3739 struct net_device *br_dev)
3740{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003741 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3742
3743 return !master_bridge->dev || master_bridge->dev == br_dev;
Ido Schimmel7117a572016-06-20 23:04:06 +02003744}
3745
3746static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3747 struct net_device *br_dev)
3748{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003749 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3750
3751 master_bridge->dev = br_dev;
3752 master_bridge->ref_count++;
Ido Schimmel7117a572016-06-20 23:04:06 +02003753}
3754
3755static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3756{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003757 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3758
3759 if (--master_bridge->ref_count == 0) {
3760 master_bridge->dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02003761 /* It's possible upper VLAN devices are still holding
3762 * references to underlying FIDs. Drop the reference
3763 * and release the resources if it was the last one.
3764 * If it wasn't, then something bad happened.
3765 */
3766 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3767 }
Ido Schimmel7117a572016-06-20 23:04:06 +02003768}
3769
3770static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3771 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003772{
3773 struct net_device *dev = mlxsw_sp_port->dev;
3774 int err;
3775
3776 /* When port is not bridged untagged packets are tagged with
3777 * PVID=VID=1, thereby creating an implicit VLAN interface in
3778 * the device. Remove it and let bridge code take care of its
3779 * own VLANs.
3780 */
3781 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003782 if (err)
3783 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784
Ido Schimmel7117a572016-06-20 23:04:06 +02003785 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3786
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003787 mlxsw_sp_port->learning = 1;
3788 mlxsw_sp_port->learning_sync = 1;
3789 mlxsw_sp_port->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003790 mlxsw_sp_port->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003791 mlxsw_sp_port->mc_router = 0;
3792 mlxsw_sp_port->mc_disabled = 1;
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003793 mlxsw_sp_port->bridged = 1;
3794
3795 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003796}
3797
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003798static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003799{
3800 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003801
Ido Schimmel28a01d22016-02-18 11:30:02 +01003802 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3803
Ido Schimmel7117a572016-06-20 23:04:06 +02003804 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3805
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01003806 mlxsw_sp_port->learning = 0;
3807 mlxsw_sp_port->learning_sync = 0;
3808 mlxsw_sp_port->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003809 mlxsw_sp_port->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01003810 mlxsw_sp_port->mc_router = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01003811 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003812
3813 /* Add implicit VLAN interface in the device, so that untagged
3814 * packets will be classified to the default vFID.
3815 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02003816 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003817}
3818
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003819static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003820{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003821 char sldr_pl[MLXSW_REG_SLDR_LEN];
3822
3823 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3825}
3826
3827static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3828{
3829 char sldr_pl[MLXSW_REG_SLDR_LEN];
3830
3831 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3832 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3833}
3834
3835static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3836 u16 lag_id, u8 port_index)
3837{
3838 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3839 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3840
3841 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3842 lag_id, port_index);
3843 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3844}
3845
3846static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3847 u16 lag_id)
3848{
3849 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3850 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3851
3852 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3853 lag_id);
3854 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3855}
3856
3857static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3858 u16 lag_id)
3859{
3860 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3861 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3862
3863 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3864 lag_id);
3865 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3866}
3867
3868static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3869 u16 lag_id)
3870{
3871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3872 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3873
3874 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3875 lag_id);
3876 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3877}
3878
3879static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3880 struct net_device *lag_dev,
3881 u16 *p_lag_id)
3882{
3883 struct mlxsw_sp_upper *lag;
3884 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003885 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003886 int i;
3887
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003888 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3889 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003890 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3891 if (lag->ref_count) {
3892 if (lag->dev == lag_dev) {
3893 *p_lag_id = i;
3894 return 0;
3895 }
3896 } else if (free_lag_id < 0) {
3897 free_lag_id = i;
3898 }
3899 }
3900 if (free_lag_id < 0)
3901 return -EBUSY;
3902 *p_lag_id = free_lag_id;
3903 return 0;
3904}
3905
3906static bool
3907mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3908 struct net_device *lag_dev,
3909 struct netdev_lag_upper_info *lag_upper_info)
3910{
3911 u16 lag_id;
3912
3913 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3914 return false;
3915 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3916 return false;
3917 return true;
3918}
3919
3920static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3921 u16 lag_id, u8 *p_port_index)
3922{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003923 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003924 int i;
3925
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003926 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3927 MAX_LAG_MEMBERS);
3928 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003929 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3930 *p_port_index = i;
3931 return 0;
3932 }
3933 }
3934 return -EBUSY;
3935}
3936
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003937static void
3938mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel186962e2017-03-10 08:53:36 +01003939 struct net_device *lag_dev, u16 lag_id)
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003940{
3941 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003942 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003943
3944 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3945 if (WARN_ON(!mlxsw_sp_vport))
3946 return;
3947
Ido Schimmel11943ff2016-07-02 11:00:12 +02003948 /* If vPort is assigned a RIF, then leave it since it's no
3949 * longer valid.
3950 */
3951 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3952 if (f)
3953 f->leave(mlxsw_sp_vport);
3954
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003955 mlxsw_sp_vport->lag_id = lag_id;
3956 mlxsw_sp_vport->lagged = 1;
Ido Schimmel186962e2017-03-10 08:53:36 +01003957 mlxsw_sp_vport->dev = lag_dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003958}
3959
3960static void
3961mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3962{
3963 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02003964 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003965
3966 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3967 if (WARN_ON(!mlxsw_sp_vport))
3968 return;
3969
Ido Schimmel11943ff2016-07-02 11:00:12 +02003970 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3971 if (f)
3972 f->leave(mlxsw_sp_vport);
3973
Ido Schimmel186962e2017-03-10 08:53:36 +01003974 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003975 mlxsw_sp_vport->lagged = 0;
3976}
3977
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003978static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3979 struct net_device *lag_dev)
3980{
3981 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3982 struct mlxsw_sp_upper *lag;
3983 u16 lag_id;
3984 u8 port_index;
3985 int err;
3986
3987 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3988 if (err)
3989 return err;
3990 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3991 if (!lag->ref_count) {
3992 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3993 if (err)
3994 return err;
3995 lag->dev = lag_dev;
3996 }
3997
3998 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3999 if (err)
4000 return err;
4001 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4002 if (err)
4003 goto err_col_port_add;
4004 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4005 if (err)
4006 goto err_col_port_enable;
4007
4008 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4009 mlxsw_sp_port->local_port);
4010 mlxsw_sp_port->lag_id = lag_id;
4011 mlxsw_sp_port->lagged = 1;
4012 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004013
Ido Schimmel186962e2017-03-10 08:53:36 +01004014 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004015
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004016 return 0;
4017
Ido Schimmel51554db2016-05-06 22:18:39 +02004018err_col_port_enable:
4019 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004020err_col_port_add:
4021 if (!lag->ref_count)
4022 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004023 return err;
4024}
4025
Ido Schimmel82e6db02016-06-20 23:04:04 +02004026static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4027 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004028{
4029 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004030 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004031 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004032
4033 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004034 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004035 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4036 WARN_ON(lag->ref_count == 0);
4037
Ido Schimmel82e6db02016-06-20 23:04:04 +02004038 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4039 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004040
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004041 if (mlxsw_sp_port->bridged) {
4042 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004043 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004044 }
4045
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004046 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004047 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004048
4049 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4050 mlxsw_sp_port->local_port);
4051 mlxsw_sp_port->lagged = 0;
4052 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004053
4054 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004055}
4056
Jiri Pirko74581202015-12-03 12:12:30 +01004057static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4058 u16 lag_id)
4059{
4060 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4061 char sldr_pl[MLXSW_REG_SLDR_LEN];
4062
4063 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4064 mlxsw_sp_port->local_port);
4065 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4066}
4067
4068static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4069 u16 lag_id)
4070{
4071 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4072 char sldr_pl[MLXSW_REG_SLDR_LEN];
4073
4074 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4075 mlxsw_sp_port->local_port);
4076 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4077}
4078
4079static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4080 bool lag_tx_enabled)
4081{
4082 if (lag_tx_enabled)
4083 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4084 mlxsw_sp_port->lag_id);
4085 else
4086 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4087 mlxsw_sp_port->lag_id);
4088}
4089
4090static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4091 struct netdev_lag_lower_state_info *info)
4092{
4093 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4094}
4095
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004096static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4097 struct net_device *vlan_dev)
4098{
4099 struct mlxsw_sp_port *mlxsw_sp_vport;
4100 u16 vid = vlan_dev_vlan_id(vlan_dev);
4101
4102 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004103 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004104 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004105
4106 mlxsw_sp_vport->dev = vlan_dev;
4107
4108 return 0;
4109}
4110
Ido Schimmel82e6db02016-06-20 23:04:04 +02004111static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4112 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004113{
4114 struct mlxsw_sp_port *mlxsw_sp_vport;
4115 u16 vid = vlan_dev_vlan_id(vlan_dev);
4116
4117 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004118 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02004119 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004120
4121 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004122}
4123
Jiri Pirko2b94e582017-04-18 16:55:37 +02004124static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4125 bool enable)
4126{
4127 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4128 enum mlxsw_reg_spms_state spms_state;
4129 char *spms_pl;
4130 u16 vid;
4131 int err;
4132
4133 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4134 MLXSW_REG_SPMS_STATE_DISCARDING;
4135
4136 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4137 if (!spms_pl)
4138 return -ENOMEM;
4139 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4140
4141 for (vid = 0; vid < VLAN_N_VID; vid++)
4142 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4143
4144 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4145 kfree(spms_pl);
4146 return err;
4147}
4148
4149static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4150{
4151 int err;
4152
4153 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4154 if (err)
4155 return err;
4156 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4157 true, false);
4158 if (err)
4159 goto err_port_vlan_set;
4160 return 0;
4161
4162err_port_vlan_set:
4163 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4164 return err;
4165}
4166
4167static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4168{
4169 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4170 false, false);
4171 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4172}
4173
Jiri Pirko74581202015-12-03 12:12:30 +01004174static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4175 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004176{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004177 struct netdev_notifier_changeupper_info *info;
4178 struct mlxsw_sp_port *mlxsw_sp_port;
4179 struct net_device *upper_dev;
4180 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004181 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004182
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004183 mlxsw_sp_port = netdev_priv(dev);
4184 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4185 info = ptr;
4186
4187 switch (event) {
4188 case NETDEV_PRECHANGEUPPER:
4189 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004190 if (!is_vlan_dev(upper_dev) &&
4191 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004192 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004193 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004194 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004195 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004196 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004197 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004198 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004199 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004200 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004201 if (netif_is_lag_master(upper_dev) &&
4202 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4203 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004204 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004205 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4206 return -EINVAL;
4207 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4208 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4209 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004210 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4211 return -EINVAL;
4212 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4213 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004214 break;
4215 case NETDEV_CHANGEUPPER:
4216 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004217 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004218 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004219 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4220 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004221 else
Jiri Pirkob51df792017-04-18 16:55:31 +02004222 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4223 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004224 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004225 if (info->linking)
4226 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4227 upper_dev);
4228 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004229 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004230 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004231 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004232 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4233 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004234 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004235 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4236 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004237 } else if (netif_is_ovs_master(upper_dev)) {
4238 if (info->linking)
4239 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4240 else
4241 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004242 } else {
4243 err = -EINVAL;
4244 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004245 }
4246 break;
4247 }
4248
Ido Schimmel80bedf12016-06-20 23:03:59 +02004249 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004250}
4251
Jiri Pirko74581202015-12-03 12:12:30 +01004252static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4253 unsigned long event, void *ptr)
4254{
4255 struct netdev_notifier_changelowerstate_info *info;
4256 struct mlxsw_sp_port *mlxsw_sp_port;
4257 int err;
4258
4259 mlxsw_sp_port = netdev_priv(dev);
4260 info = ptr;
4261
4262 switch (event) {
4263 case NETDEV_CHANGELOWERSTATE:
4264 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4265 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4266 info->lower_state_info);
4267 if (err)
4268 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4269 }
4270 break;
4271 }
4272
Ido Schimmel80bedf12016-06-20 23:03:59 +02004273 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004274}
4275
4276static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4277 unsigned long event, void *ptr)
4278{
4279 switch (event) {
4280 case NETDEV_PRECHANGEUPPER:
4281 case NETDEV_CHANGEUPPER:
4282 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4283 case NETDEV_CHANGELOWERSTATE:
4284 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4285 }
4286
Ido Schimmel80bedf12016-06-20 23:03:59 +02004287 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004288}
4289
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004290static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4291 unsigned long event, void *ptr)
4292{
4293 struct net_device *dev;
4294 struct list_head *iter;
4295 int ret;
4296
4297 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4298 if (mlxsw_sp_port_dev_check(dev)) {
4299 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004300 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004301 return ret;
4302 }
4303 }
4304
Ido Schimmel80bedf12016-06-20 23:03:59 +02004305 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004306}
4307
Ido Schimmel701b1862016-07-04 08:23:16 +02004308static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4309 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004310{
Ido Schimmel701b1862016-07-04 08:23:16 +02004311 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004312 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004313
Ido Schimmel701b1862016-07-04 08:23:16 +02004314 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4315 if (!f) {
4316 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4317 if (IS_ERR(f))
4318 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004319 }
4320
Ido Schimmel701b1862016-07-04 08:23:16 +02004321 f->ref_count++;
4322
4323 return 0;
4324}
4325
4326static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4327 struct net_device *vlan_dev)
4328{
4329 u16 fid = vlan_dev_vlan_id(vlan_dev);
4330 struct mlxsw_sp_fid *f;
4331
4332 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004333 if (f && f->rif)
4334 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel701b1862016-07-04 08:23:16 +02004335 if (f && --f->ref_count == 0)
4336 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4337}
4338
4339static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4340 unsigned long event, void *ptr)
4341{
4342 struct netdev_notifier_changeupper_info *info;
4343 struct net_device *upper_dev;
4344 struct mlxsw_sp *mlxsw_sp;
Ido Schimmelb4149702017-03-10 08:53:34 +01004345 int err = 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004346
4347 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4348 if (!mlxsw_sp)
4349 return 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004350
4351 info = ptr;
4352
4353 switch (event) {
Ido Schimmelb4149702017-03-10 08:53:34 +01004354 case NETDEV_PRECHANGEUPPER:
Ido Schimmel701b1862016-07-04 08:23:16 +02004355 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004356 if (!is_vlan_dev(upper_dev))
Ido Schimmelb4149702017-03-10 08:53:34 +01004357 return -EINVAL;
4358 if (is_vlan_dev(upper_dev) &&
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004359 br_dev != mlxsw_sp_master_bridge(mlxsw_sp)->dev)
Ido Schimmelb4149702017-03-10 08:53:34 +01004360 return -EINVAL;
4361 break;
4362 case NETDEV_CHANGEUPPER:
4363 upper_dev = info->upper_dev;
4364 if (is_vlan_dev(upper_dev)) {
4365 if (info->linking)
4366 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4367 upper_dev);
4368 else
4369 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4370 upper_dev);
Ido Schimmel701b1862016-07-04 08:23:16 +02004371 } else {
Ido Schimmelb4149702017-03-10 08:53:34 +01004372 err = -EINVAL;
4373 WARN_ON(1);
Ido Schimmel701b1862016-07-04 08:23:16 +02004374 }
4375 break;
4376 }
4377
Ido Schimmelb4149702017-03-10 08:53:34 +01004378 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004379}
4380
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004381static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004382{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004383 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02004384 MLXSW_SP_VFID_MAX);
4385}
4386
4387static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4388{
4389 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4390
4391 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4392 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004393}
4394
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004395static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel1c800752016-06-20 23:04:20 +02004396
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004397static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4398 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004399{
4400 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004401 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004402 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004403 int err;
4404
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004405 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004406 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004407 dev_err(dev, "No available vFIDs\n");
4408 return ERR_PTR(-ERANGE);
4409 }
4410
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004411 fid = mlxsw_sp_vfid_to_fid(vfid);
4412 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004413 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004414 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004415 return ERR_PTR(err);
4416 }
4417
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004418 f = kzalloc(sizeof(*f), GFP_KERNEL);
4419 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004420 goto err_allocate_vfid;
4421
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004422 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004423 f->fid = fid;
4424 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004425
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004426 list_add(&f->list, &mlxsw_sp->vfids.list);
4427 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004428
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004429 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004430
4431err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004432 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004433 return ERR_PTR(-ENOMEM);
4434}
4435
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004436static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4437 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004438{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004439 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004440 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004441
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004442 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004443 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004444
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004445 if (f->rif)
4446 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004447
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004448 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004449
4450 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004451}
4452
Ido Schimmel99724c12016-07-04 08:23:14 +02004453static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4454 bool valid)
4455{
4456 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4457 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4458
4459 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4460 vid);
4461}
4462
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004463static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4464 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004465{
Ido Schimmel0355b592016-06-20 23:04:13 +02004466 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004467 int err;
4468
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004469 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004470 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004471 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004472 if (IS_ERR(f))
4473 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004474 }
4475
Ido Schimmel0355b592016-06-20 23:04:13 +02004476 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4477 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004478 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004479
Ido Schimmel0355b592016-06-20 23:04:13 +02004480 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4481 if (err)
4482 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01004483
Ido Schimmel41b996c2016-06-20 23:04:17 +02004484 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004485 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01004486
Ido Schimmel22305372016-06-20 23:04:21 +02004487 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4488
Ido Schimmel0355b592016-06-20 23:04:13 +02004489 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004490
Ido Schimmel9c4d4422016-06-20 23:04:10 +02004491err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02004492 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4493err_vport_flood_set:
4494 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004495 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004496 return err;
4497}
4498
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004499static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004500{
Ido Schimmel41b996c2016-06-20 23:04:17 +02004501 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004502
Ido Schimmel22305372016-06-20 23:04:21 +02004503 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4504
Ido Schimmel0355b592016-06-20 23:04:13 +02004505 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4506
4507 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4508
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004509 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4510
Ido Schimmel41b996c2016-06-20 23:04:17 +02004511 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +02004512 if (--f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004513 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004514}
4515
4516static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4517 struct net_device *br_dev)
4518{
Ido Schimmel99724c12016-07-04 08:23:14 +02004519 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004520 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4521 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004522 int err;
4523
Ido Schimmel99724c12016-07-04 08:23:14 +02004524 if (f && !WARN_ON(!f->leave))
4525 f->leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004526
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004527 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004528 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02004529 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02004530 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004531 }
4532
4533 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4534 if (err) {
4535 netdev_err(dev, "Failed to enable learning\n");
4536 goto err_port_vid_learning_set;
4537 }
4538
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004539 mlxsw_sp_vport->learning = 1;
4540 mlxsw_sp_vport->learning_sync = 1;
4541 mlxsw_sp_vport->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004542 mlxsw_sp_vport->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004543 mlxsw_sp_vport->mc_router = 0;
4544 mlxsw_sp_vport->mc_disabled = 1;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004545 mlxsw_sp_vport->bridged = 1;
4546
4547 return 0;
4548
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004549err_port_vid_learning_set:
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004550 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004551 return err;
4552}
4553
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004554static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004555{
4556 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004557
4558 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4559
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004560 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004561
Ido Schimmel0355b592016-06-20 23:04:13 +02004562 mlxsw_sp_vport->learning = 0;
4563 mlxsw_sp_vport->learning_sync = 0;
4564 mlxsw_sp_vport->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004565 mlxsw_sp_vport->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004566 mlxsw_sp_vport->mc_router = 0;
Ido Schimmel0355b592016-06-20 23:04:13 +02004567 mlxsw_sp_vport->bridged = 0;
4568}
4569
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004570static bool
4571mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4572 const struct net_device *br_dev)
4573{
4574 struct mlxsw_sp_port *mlxsw_sp_vport;
4575
4576 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4577 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004578 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02004579
4580 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004581 return false;
4582 }
4583
4584 return true;
4585}
4586
4587static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4588 unsigned long event, void *ptr,
4589 u16 vid)
4590{
4591 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4592 struct netdev_notifier_changeupper_info *info = ptr;
4593 struct mlxsw_sp_port *mlxsw_sp_vport;
4594 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004595 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004596
4597 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel1f880612017-03-10 08:53:35 +01004598 if (!mlxsw_sp_vport)
4599 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004600
4601 switch (event) {
4602 case NETDEV_PRECHANGEUPPER:
4603 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004604 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004605 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02004606 if (!info->linking)
4607 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004608 /* We can't have multiple VLAN interfaces configured on
4609 * the same port and being members in the same bridge.
4610 */
Ido Schimmel7179eb52017-03-16 09:08:18 +01004611 if (netif_is_bridge_master(upper_dev) &&
4612 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004613 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004614 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004615 break;
4616 case NETDEV_CHANGEUPPER:
4617 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004618 if (netif_is_bridge_master(upper_dev)) {
4619 if (info->linking)
4620 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4621 upper_dev);
4622 else
4623 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004624 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004625 err = -EINVAL;
4626 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004627 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004628 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004629 }
4630
Ido Schimmel80bedf12016-06-20 23:03:59 +02004631 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004632}
4633
Ido Schimmel272c4472015-12-15 16:03:47 +01004634static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4635 unsigned long event, void *ptr,
4636 u16 vid)
4637{
4638 struct net_device *dev;
4639 struct list_head *iter;
4640 int ret;
4641
4642 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4643 if (mlxsw_sp_port_dev_check(dev)) {
4644 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4645 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004646 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004647 return ret;
4648 }
4649 }
4650
Ido Schimmel80bedf12016-06-20 23:03:59 +02004651 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004652}
4653
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004654static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4655 unsigned long event, void *ptr)
4656{
4657 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4658 u16 vid = vlan_dev_vlan_id(vlan_dev);
4659
Ido Schimmel272c4472015-12-15 16:03:47 +01004660 if (mlxsw_sp_port_dev_check(real_dev))
4661 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4662 vid);
4663 else if (netif_is_lag_master(real_dev))
4664 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4665 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004666
Ido Schimmel80bedf12016-06-20 23:03:59 +02004667 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004668}
4669
Ido Schimmelb1e45522017-04-30 19:47:14 +03004670static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4671{
4672 struct netdev_notifier_changeupper_info *info = ptr;
4673
4674 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4675 return false;
4676 return netif_is_l3_master(info->upper_dev);
4677}
4678
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004679static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4680 unsigned long event, void *ptr)
4681{
4682 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004683 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004684
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004685 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4686 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004687 else if (mlxsw_sp_is_vrf_event(event, ptr))
4688 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004689 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004690 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4691 else if (netif_is_lag_master(dev))
4692 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004693 else if (netif_is_bridge_master(dev))
4694 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004695 else if (is_vlan_dev(dev))
4696 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004697
Ido Schimmel80bedf12016-06-20 23:03:59 +02004698 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004699}
4700
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004701static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4702 .notifier_call = mlxsw_sp_netdevice_event,
4703};
4704
Ido Schimmel99724c12016-07-04 08:23:14 +02004705static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4706 .notifier_call = mlxsw_sp_inetaddr_event,
4707 .priority = 10, /* Must be called before FIB notifier block */
4708};
4709
Jiri Pirkoe7322632016-09-01 10:37:43 +02004710static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4711 .notifier_call = mlxsw_sp_router_netevent_event,
4712};
4713
Jiri Pirko1d20d232016-10-27 15:12:59 +02004714static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4715 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4716 {0, },
4717};
4718
4719static struct pci_driver mlxsw_sp_pci_driver = {
4720 .name = mlxsw_sp_driver_name,
4721 .id_table = mlxsw_sp_pci_id_table,
4722};
4723
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004724static int __init mlxsw_sp_module_init(void)
4725{
4726 int err;
4727
4728 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004729 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004730 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4731
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004732 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4733 if (err)
4734 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004735
4736 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4737 if (err)
4738 goto err_pci_driver_register;
4739
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004740 return 0;
4741
Jiri Pirko1d20d232016-10-27 15:12:59 +02004742err_pci_driver_register:
4743 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004744err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004745 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004746 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004747 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4748 return err;
4749}
4750
4751static void __exit mlxsw_sp_module_exit(void)
4752{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004753 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004754 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004755 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004756 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004757 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4758}
4759
4760module_init(mlxsw_sp_module_init);
4761module_exit(mlxsw_sp_module_exit);
4762
4763MODULE_LICENSE("Dual BSD/GPL");
4764MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4765MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004766MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);