sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3 | /*--- Begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
florian | 33b0243 | 2012-08-25 21:48:04 +0000 | [diff] [blame] | 37 | #include "libvex_emnote.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 41 | #include "libvex_guest_arm64.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 42 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 43 | #include "libvex_guest_ppc64.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 44 | #include "libvex_guest_s390x.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 45 | #include "libvex_guest_mips32.h" |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 46 | #include "libvex_guest_mips64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 47 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 48 | #include "main_globals.h" |
| 49 | #include "main_util.h" |
| 50 | #include "host_generic_regs.h" |
| 51 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 52 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 53 | #include "host_x86_defs.h" |
| 54 | #include "host_amd64_defs.h" |
| 55 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 56 | #include "host_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 57 | #include "host_arm64_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 58 | #include "host_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 59 | #include "host_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 60 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 61 | #include "guest_generic_bb_to_IR.h" |
| 62 | #include "guest_x86_defs.h" |
| 63 | #include "guest_amd64_defs.h" |
| 64 | #include "guest_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 65 | #include "guest_arm64_defs.h" |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 66 | #include "guest_ppc_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 67 | #include "guest_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 68 | #include "guest_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 69 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 70 | #include "host_generic_simd128.h" |
| 71 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 72 | |
| 73 | /* This file contains the top level interface to the library. */ |
| 74 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 75 | /* --------- fwds ... --------- */ |
| 76 | |
| 77 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 78 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 79 | |
| 80 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 81 | /* --------- helpers --------- */ |
| 82 | |
| 83 | __attribute__((noinline)) |
| 84 | static UInt udiv32 ( UInt x, UInt y ) { return x/y; } |
| 85 | __attribute__((noinline)) |
| 86 | static Int sdiv32 ( Int x, Int y ) { return x/y; } |
| 87 | |
| 88 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 89 | /* --------- Initialise the library. --------- */ |
| 90 | |
| 91 | /* Exported to library client. */ |
| 92 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 93 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 94 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 95 | vex_bzero(vcon, sizeof(*vcon)); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 96 | vcon->iropt_verbosity = 0; |
| 97 | vcon->iropt_level = 2; |
philippe | c8e2f98 | 2012-08-01 22:04:13 +0000 | [diff] [blame] | 98 | vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 99 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 100 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 101 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 102 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | |
| 106 | /* Exported to library client. */ |
| 107 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 108 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 109 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 110 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 111 | void (*failure_exit) ( void ), |
| 112 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 113 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 114 | /* debug paranoia level */ |
| 115 | Int debuglevel, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 116 | /* Control ... */ |
florian | f72c2c1 | 2014-09-05 21:52:29 +0000 | [diff] [blame] | 117 | const VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 118 | ) |
| 119 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 120 | /* First off, do enough minimal setup so that the following |
| 121 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 122 | vex_failure_exit = failure_exit; |
| 123 | vex_log_bytes = log_bytes; |
| 124 | |
| 125 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 126 | vassert(!vex_initdone); |
| 127 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 128 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 129 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 130 | |
| 131 | vassert(vcon->iropt_verbosity >= 0); |
| 132 | vassert(vcon->iropt_level >= 0); |
| 133 | vassert(vcon->iropt_level <= 2); |
| 134 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 135 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 136 | vassert(vcon->guest_max_insns >= 1); |
| 137 | vassert(vcon->guest_max_insns <= 100); |
| 138 | vassert(vcon->guest_chase_thresh >= 0); |
| 139 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 140 | vassert(vcon->guest_chase_cond == True |
| 141 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 142 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 143 | /* Check that Vex has been built with sizes of basic types as |
| 144 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 145 | a serious configuration error and should be corrected |
| 146 | immediately. If any of these assertions fail you can fully |
| 147 | expect Vex not to work properly, if at all. */ |
| 148 | |
| 149 | vassert(1 == sizeof(UChar)); |
| 150 | vassert(1 == sizeof(Char)); |
| 151 | vassert(2 == sizeof(UShort)); |
| 152 | vassert(2 == sizeof(Short)); |
| 153 | vassert(4 == sizeof(UInt)); |
| 154 | vassert(4 == sizeof(Int)); |
| 155 | vassert(8 == sizeof(ULong)); |
| 156 | vassert(8 == sizeof(Long)); |
| 157 | vassert(4 == sizeof(Float)); |
| 158 | vassert(8 == sizeof(Double)); |
| 159 | vassert(1 == sizeof(Bool)); |
| 160 | vassert(4 == sizeof(Addr32)); |
| 161 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 162 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 163 | vassert(16 == sizeof(V128)); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 164 | vassert(32 == sizeof(U256)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 165 | |
| 166 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 167 | vassert(sizeof(void*) == sizeof(int*)); |
| 168 | vassert(sizeof(void*) == sizeof(HWord)); |
| 169 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 170 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 171 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 172 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 173 | /* These take a lot of space, so make sure we don't have |
| 174 | any unnoticed size regressions. */ |
| 175 | if (VEX_HOST_WORDSIZE == 4) { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 176 | vassert(sizeof(IRExpr) == 16); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 177 | vassert(sizeof(IRStmt) == 20 /* x86 */ |
| 178 | || sizeof(IRStmt) == 24 /* arm */); |
| 179 | } else { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 180 | vassert(sizeof(IRExpr) == 32); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 181 | vassert(sizeof(IRStmt) == 32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 182 | } |
| 183 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 184 | /* Check that signed integer division on the host rounds towards |
| 185 | zero. If not, h_calc_sdiv32_w_arm_semantics() won't work |
| 186 | correctly. */ |
| 187 | /* 100.0 / 7.0 == 14.2857 */ |
| 188 | vassert(udiv32(100, 7) == 14); |
| 189 | vassert(sdiv32(100, 7) == 14); |
| 190 | vassert(sdiv32(-100, 7) == -14); /* and not -15 */ |
| 191 | vassert(sdiv32(100, -7) == -14); /* ditto */ |
| 192 | vassert(sdiv32(-100, -7) == 14); /* not sure what this proves */ |
| 193 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 194 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 195 | vex_debuglevel = debuglevel; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 196 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 197 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 198 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | |
| 202 | /* --------- Make a translation. --------- */ |
| 203 | |
| 204 | /* Exported to library client. */ |
| 205 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 206 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 207 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 208 | /* This the bundle of functions we need to do the back-end stuff |
| 209 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 210 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 211 | HReg* available_real_regs; |
| 212 | Int n_available_real_regs; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 213 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 214 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 215 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 216 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 217 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 218 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
| 219 | void (*ppInstr) ( HInstr*, Bool ); |
| 220 | void (*ppReg) ( HReg ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 221 | HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo*, |
| 222 | Int, Int, Bool, Bool, Addr64 ); |
| 223 | Int (*emit) ( /*MB_MOD*/Bool*, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 224 | UChar*, Int, HInstr*, Bool, VexEndness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 225 | void*, void*, void*, void* ); |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 226 | IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 227 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 228 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 229 | DisOneInstrFn disInstrFn; |
| 230 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 231 | VexGuestLayout* guest_layout; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 232 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 233 | HInstrArray* vcode; |
| 234 | HInstrArray* rcode; |
| 235 | Int i, j, k, out_used, guest_sizeB; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 236 | Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 237 | Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 238 | UChar insn_bytes[128]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 239 | IRType guest_word_type; |
| 240 | IRType host_word_type; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 241 | Bool mode64, chainingAllowed; |
| 242 | Addr64 max_ga; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 243 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 244 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 245 | available_real_regs = NULL; |
| 246 | n_available_real_regs = 0; |
| 247 | isMove = NULL; |
| 248 | getRegUsage = NULL; |
| 249 | mapRegs = NULL; |
| 250 | genSpill = NULL; |
| 251 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 252 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 253 | ppInstr = NULL; |
| 254 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 255 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 256 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 257 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 258 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 259 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 260 | guest_word_type = Ity_INVALID; |
| 261 | host_word_type = Ity_INVALID; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 262 | offB_CMSTART = 0; |
| 263 | offB_CMLEN = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 264 | offB_GUEST_IP = 0; |
| 265 | szB_GUEST_IP = 0; |
| 266 | offB_HOST_EvC_COUNTER = 0; |
| 267 | offB_HOST_EvC_FAILADDR = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 268 | mode64 = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 269 | chainingAllowed = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 270 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 271 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 272 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 273 | vassert(vex_initdone); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 274 | vassert(vta->needs_self_check != NULL); |
| 275 | vassert(vta->disp_cp_xassisted != NULL); |
| 276 | /* Both the chainers and the indir are either NULL or non-NULL. */ |
| 277 | if (vta->disp_cp_chain_me_to_slowEP != NULL) { |
| 278 | vassert(vta->disp_cp_chain_me_to_fastEP != NULL); |
| 279 | vassert(vta->disp_cp_xindir != NULL); |
| 280 | chainingAllowed = True; |
| 281 | } else { |
| 282 | vassert(vta->disp_cp_chain_me_to_fastEP == NULL); |
| 283 | vassert(vta->disp_cp_xindir == NULL); |
| 284 | } |
florian | 2eeeb9b | 2011-09-23 18:03:21 +0000 | [diff] [blame] | 285 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 286 | vexSetAllocModeTEMP_and_clear(); |
| 287 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 288 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 289 | /* First off, check that the guest and host insn sets |
| 290 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 291 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 292 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 293 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 294 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 295 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 296 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 297 | &available_real_regs ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 298 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 299 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 300 | getRegUsage_X86Instr; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 301 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 302 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 303 | genSpill_X86; |
| 304 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 305 | genReload_X86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 306 | directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86; |
| 307 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
| 308 | ppReg = (void(*)(HReg)) ppHRegX86; |
| 309 | iselSB = iselSB_X86; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 310 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 311 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 312 | emit_X86Instr; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 313 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 314 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 315 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 316 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 317 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 318 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 319 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 320 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 321 | &available_real_regs ); |
| 322 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 323 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 324 | getRegUsage_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 325 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 326 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 327 | genSpill_AMD64; |
| 328 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 329 | genReload_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 330 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 331 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 332 | iselSB = iselSB_AMD64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 333 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 334 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 335 | emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 336 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 337 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 338 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 339 | break; |
| 340 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 341 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 342 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 343 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 344 | &available_real_regs, mode64 ); |
| 345 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 346 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr; |
| 347 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 348 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 349 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 350 | ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; |
| 351 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 352 | iselSB = iselSB_PPC; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 353 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 354 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 355 | emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 356 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 357 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 358 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 359 | break; |
| 360 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 361 | case VexArchPPC64: |
| 362 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 363 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 364 | &available_real_regs, mode64 ); |
| 365 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr; |
| 366 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr; |
| 367 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr; |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 368 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC; |
| 369 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 370 | ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; |
| 371 | ppReg = (void(*)(HReg)) ppHRegPPC; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 372 | iselSB = iselSB_PPC; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 373 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 374 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 375 | emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 376 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 377 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 378 | vassert(vta->archinfo_host.endness == VexEndnessBE || |
| 379 | vta->archinfo_host.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 380 | break; |
| 381 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 382 | case VexArchS390X: |
| 383 | mode64 = True; |
| 384 | getAllocableRegs_S390 ( &n_available_real_regs, |
| 385 | &available_real_regs, mode64 ); |
| 386 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_S390Instr; |
| 387 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_S390Instr; |
| 388 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_S390Instr; |
| 389 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_S390; |
| 390 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_S390; |
| 391 | ppInstr = (void(*)(HInstr*, Bool)) ppS390Instr; |
| 392 | ppReg = (void(*)(HReg)) ppHRegS390; |
| 393 | iselSB = iselSB_S390; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 394 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 395 | void*,void*,void*,void*)) emit_S390Instr; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 396 | host_word_type = Ity_I64; |
| 397 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 398 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 399 | break; |
| 400 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 401 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 402 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 403 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 404 | &available_real_regs ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 405 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr; |
| 406 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr; |
| 407 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr; |
| 408 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM; |
| 409 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM; |
| 410 | ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; |
| 411 | ppReg = (void(*)(HReg)) ppHRegARM; |
| 412 | iselSB = iselSB_ARM; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 413 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 414 | void*,void*,void*,void*)) |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 415 | emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 416 | host_word_type = Ity_I32; |
| 417 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 418 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 419 | break; |
| 420 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 421 | case VexArchARM64: |
| 422 | mode64 = True; |
| 423 | getAllocableRegs_ARM64 ( &n_available_real_regs, |
| 424 | &available_real_regs ); |
| 425 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARM64Instr; |
| 426 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) |
| 427 | getRegUsage_ARM64Instr; |
| 428 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) |
| 429 | mapRegs_ARM64Instr; |
| 430 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 431 | genSpill_ARM64; |
| 432 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) |
| 433 | genReload_ARM64; |
| 434 | ppInstr = (void(*)(HInstr*, Bool)) ppARM64Instr; |
| 435 | ppReg = (void(*)(HReg)) ppHRegARM64; |
| 436 | iselSB = iselSB_ARM64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 437 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 438 | void*,void*,void*,void*)) |
| 439 | emit_ARM64Instr; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 440 | host_word_type = Ity_I64; |
| 441 | vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 442 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 443 | break; |
| 444 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 445 | case VexArchMIPS32: |
| 446 | mode64 = False; |
| 447 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 448 | &available_real_regs, mode64 ); |
| 449 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_MIPSInstr; |
| 450 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_MIPSInstr; |
| 451 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_MIPSInstr; |
| 452 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_MIPS; |
| 453 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_MIPS; |
| 454 | ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr; |
| 455 | ppReg = (void(*)(HReg)) ppHRegMIPS; |
| 456 | iselSB = iselSB_MIPS; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 457 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 458 | void*,void*,void*,void*)) |
| 459 | emit_MIPSInstr; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 460 | host_word_type = Ity_I32; |
| 461 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 462 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 463 | || vta->archinfo_host.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 464 | break; |
| 465 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 466 | case VexArchMIPS64: |
| 467 | mode64 = True; |
| 468 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 469 | &available_real_regs, mode64 ); |
| 470 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_MIPSInstr; |
| 471 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_MIPSInstr; |
| 472 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_MIPSInstr; |
| 473 | genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_MIPS; |
| 474 | genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_MIPS; |
| 475 | ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr; |
| 476 | ppReg = (void(*)(HReg)) ppHRegMIPS; |
| 477 | iselSB = iselSB_MIPS; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 478 | emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 479 | void*,void*,void*,void*)) |
| 480 | emit_MIPSInstr; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 481 | host_word_type = Ity_I64; |
| 482 | vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 483 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 484 | || vta->archinfo_host.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 485 | break; |
| 486 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 487 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 488 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 489 | } |
| 490 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 491 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 492 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 493 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 494 | case VexArchX86: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 495 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
| 496 | disInstrFn = disInstr_X86; |
| 497 | specHelper = guest_x86_spechelper; |
| 498 | guest_sizeB = sizeof(VexGuestX86State); |
| 499 | guest_word_type = Ity_I32; |
| 500 | guest_layout = &x86guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 501 | offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART); |
| 502 | offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 503 | offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); |
| 504 | szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); |
| 505 | offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); |
| 506 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 507 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 508 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 509 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 510 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4); |
| 511 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 512 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 513 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 514 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 515 | case VexArchAMD64: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 516 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 517 | disInstrFn = disInstr_AMD64; |
| 518 | specHelper = guest_amd64_spechelper; |
| 519 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 520 | guest_word_type = Ity_I64; |
| 521 | guest_layout = &amd64guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 522 | offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART); |
| 523 | offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 524 | offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); |
| 525 | szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); |
| 526 | offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); |
| 527 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 528 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 529 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 530 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 531 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8); |
| 532 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 533 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 534 | break; |
| 535 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 536 | case VexArchPPC32: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 537 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 538 | disInstrFn = disInstr_PPC; |
| 539 | specHelper = guest_ppc32_spechelper; |
| 540 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 541 | guest_word_type = Ity_I32; |
| 542 | guest_layout = &ppc32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 543 | offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART); |
| 544 | offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 545 | offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); |
| 546 | szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); |
| 547 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); |
| 548 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 549 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 550 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 551 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 552 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4); |
| 553 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 554 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 555 | break; |
| 556 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 557 | case VexArchPPC64: |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 558 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
| 559 | disInstrFn = disInstr_PPC; |
| 560 | specHelper = guest_ppc64_spechelper; |
| 561 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 562 | guest_word_type = Ity_I64; |
| 563 | guest_layout = &ppc64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 564 | offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART); |
| 565 | offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN); |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 566 | offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA); |
| 567 | szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA ); |
| 568 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); |
| 569 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 570 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 571 | vassert(vta->archinfo_guest.endness == VexEndnessBE || |
| 572 | vta->archinfo_guest.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 573 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 574 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8); |
| 575 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 576 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 577 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 578 | break; |
| 579 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 580 | case VexArchS390X: |
| 581 | preciseMemExnsFn = guest_s390x_state_requires_precise_mem_exns; |
| 582 | disInstrFn = disInstr_S390; |
| 583 | specHelper = guest_s390x_spechelper; |
| 584 | guest_sizeB = sizeof(VexGuestS390XState); |
| 585 | guest_word_type = Ity_I64; |
| 586 | guest_layout = &s390xGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 587 | offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART); |
| 588 | offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 589 | offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); |
| 590 | szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); |
| 591 | offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); |
| 592 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 593 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 594 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 595 | vassert(0 == sizeof(VexGuestS390XState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 596 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8); |
| 597 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 598 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); |
| 599 | break; |
| 600 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 601 | case VexArchARM: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 602 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 603 | disInstrFn = disInstr_ARM; |
| 604 | specHelper = guest_arm_spechelper; |
| 605 | guest_sizeB = sizeof(VexGuestARMState); |
| 606 | guest_word_type = Ity_I32; |
| 607 | guest_layout = &armGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 608 | offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART); |
| 609 | offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 610 | offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); |
| 611 | szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); |
| 612 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); |
| 613 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 614 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 615 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 616 | vassert(0 == sizeof(VexGuestARMState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 617 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4); |
| 618 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 619 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 620 | break; |
| 621 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 622 | case VexArchARM64: |
| 623 | preciseMemExnsFn = guest_arm64_state_requires_precise_mem_exns; |
| 624 | disInstrFn = disInstr_ARM64; |
| 625 | specHelper = guest_arm64_spechelper; |
| 626 | guest_sizeB = sizeof(VexGuestARM64State); |
| 627 | guest_word_type = Ity_I64; |
| 628 | guest_layout = &arm64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 629 | offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART); |
| 630 | offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 631 | offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC); |
| 632 | szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC ); |
| 633 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); |
| 634 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); |
| 635 | vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 636 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 637 | vassert(0 == sizeof(VexGuestARM64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 638 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8); |
| 639 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 640 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); |
| 641 | break; |
| 642 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 643 | case VexArchMIPS32: |
| 644 | preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; |
| 645 | disInstrFn = disInstr_MIPS; |
| 646 | specHelper = guest_mips32_spechelper; |
| 647 | guest_sizeB = sizeof(VexGuestMIPS32State); |
| 648 | guest_word_type = Ity_I32; |
| 649 | guest_layout = &mips32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 650 | offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART); |
| 651 | offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 652 | offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC); |
| 653 | szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC ); |
| 654 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); |
| 655 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); |
| 656 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 657 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 658 | || vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 659 | vassert(0 == sizeof(VexGuestMIPS32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 660 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4); |
| 661 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 662 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); |
| 663 | break; |
| 664 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 665 | case VexArchMIPS64: |
| 666 | preciseMemExnsFn = guest_mips64_state_requires_precise_mem_exns; |
| 667 | disInstrFn = disInstr_MIPS; |
| 668 | specHelper = guest_mips64_spechelper; |
| 669 | guest_sizeB = sizeof(VexGuestMIPS64State); |
| 670 | guest_word_type = Ity_I64; |
| 671 | guest_layout = &mips64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 672 | offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART); |
| 673 | offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 674 | offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC); |
| 675 | szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC ); |
| 676 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); |
| 677 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); |
| 678 | vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 679 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 680 | || vta->archinfo_guest.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 681 | vassert(0 == sizeof(VexGuestMIPS64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 682 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8); |
| 683 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 684 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); |
| 685 | break; |
| 686 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 687 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 688 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 689 | } |
| 690 | |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 691 | /* Set up result struct. */ |
| 692 | VexTranslateResult res; |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 693 | res.status = VexTransOK; |
| 694 | res.n_sc_extents = 0; |
| 695 | res.offs_profInc = -1; |
| 696 | res.n_guest_instrs = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 697 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 698 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 699 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 700 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 701 | we are simulating one flavour of an architecture a different |
| 702 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 703 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 704 | /* ditto */ |
| 705 | vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 706 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 707 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 708 | vexAllocSanityCheck(); |
| 709 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 710 | if (vex_traceflags & VEX_TRACE_FE) |
| 711 | vex_printf("\n------------------------" |
| 712 | " Front end " |
| 713 | "------------------------\n\n"); |
| 714 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 715 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 716 | &res.n_sc_extents, |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 717 | &res.n_guest_instrs, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 718 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 719 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 720 | vta->guest_bytes, |
| 721 | vta->guest_bytes_addr, |
| 722 | vta->chase_into_ok, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 723 | vta->archinfo_host.endness, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 724 | vta->sigill_diag, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 725 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 726 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 727 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 728 | guest_word_type, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 729 | vta->needs_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 730 | vta->preamble_function, |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 731 | offB_CMSTART, |
| 732 | offB_CMLEN, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 733 | offB_GUEST_IP, |
| 734 | szB_GUEST_IP ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 735 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 736 | vexAllocSanityCheck(); |
| 737 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 738 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 739 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 740 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 741 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 742 | res.status = VexTransAccessFail; return res; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 743 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 744 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 745 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 746 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 747 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 748 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 749 | } |
| 750 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 751 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 752 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 753 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 754 | vex_printf("can't show code due to extents > 1\n"); |
| 755 | } else { |
| 756 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 757 | UChar* p = (UChar*)vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 758 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 759 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 760 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 761 | guest_bytes_read ); |
| 762 | for (i = 0; i < guest_bytes_read; i++) { |
| 763 | UInt b = (UInt)p[i]; |
| 764 | vex_printf(" %02x", b ); |
| 765 | sum = (sum << 1) ^ b; |
| 766 | } |
| 767 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 768 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 772 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 773 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 774 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 775 | vexAllocSanityCheck(); |
| 776 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 777 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 778 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 779 | vta->guest_bytes_addr, |
| 780 | vta->arch_guest ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 781 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 782 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 783 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 784 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 785 | vex_printf("\n------------------------" |
| 786 | " After pre-instr IR optimisation " |
| 787 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 788 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 789 | vex_printf("\n"); |
| 790 | } |
| 791 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 792 | vexAllocSanityCheck(); |
| 793 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 794 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 795 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 796 | irsb = vta->instrument1(vta->callback_opaque, |
| 797 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 798 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 799 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 800 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 801 | vexAllocSanityCheck(); |
| 802 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 803 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 804 | irsb = vta->instrument2(vta->callback_opaque, |
| 805 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 806 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 807 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 808 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 809 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 810 | if (vex_traceflags & VEX_TRACE_INST) { |
| 811 | vex_printf("\n------------------------" |
| 812 | " After instrumentation " |
| 813 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 814 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 815 | vex_printf("\n"); |
| 816 | } |
| 817 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 818 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 819 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 820 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 821 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 822 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 823 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 824 | do_deadcode_BB( irsb ); |
| 825 | irsb = cprop_BB( irsb ); |
| 826 | do_deadcode_BB( irsb ); |
| 827 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 828 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 829 | } |
| 830 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 831 | vexAllocSanityCheck(); |
| 832 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 833 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 834 | vex_printf("\n------------------------" |
| 835 | " After post-instr IR optimisation " |
| 836 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 837 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 838 | vex_printf("\n"); |
| 839 | } |
| 840 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 841 | /* Turn it into virtual-registerised code. Build trees -- this |
| 842 | also throws away any dead bindings. */ |
florian | 62140c1 | 2013-01-20 03:51:04 +0000 | [diff] [blame] | 843 | max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 844 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 845 | if (vta->finaltidy) { |
| 846 | irsb = vta->finaltidy(irsb); |
| 847 | } |
| 848 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 849 | vexAllocSanityCheck(); |
| 850 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 851 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 852 | vex_printf("\n------------------------" |
| 853 | " After tree-building " |
| 854 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 855 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 856 | vex_printf("\n"); |
| 857 | } |
| 858 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 859 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 860 | if (0) { |
| 861 | *(vta->host_bytes_used) = 0; |
| 862 | res.status = VexTransOK; return res; |
| 863 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 864 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 865 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 866 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 867 | vex_printf("\n------------------------" |
| 868 | " Instruction selection " |
| 869 | "------------------------\n"); |
| 870 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 871 | /* No guest has its IP field at offset zero. If this fails it |
| 872 | means some transformation pass somewhere failed to update/copy |
| 873 | irsb->offsIP properly. */ |
| 874 | vassert(irsb->offsIP >= 16); |
| 875 | |
| 876 | vcode = iselSB ( irsb, vta->arch_host, |
| 877 | &vta->archinfo_host, |
| 878 | &vta->abiinfo_both, |
| 879 | offB_HOST_EvC_COUNTER, |
| 880 | offB_HOST_EvC_FAILADDR, |
| 881 | chainingAllowed, |
| 882 | vta->addProfInc, |
| 883 | max_ga ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 884 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 885 | vexAllocSanityCheck(); |
| 886 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 887 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 888 | vex_printf("\n"); |
| 889 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 890 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 891 | for (i = 0; i < vcode->arr_used; i++) { |
| 892 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 893 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 894 | vex_printf("\n"); |
| 895 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 896 | vex_printf("\n"); |
| 897 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 898 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 899 | /* Register allocate. */ |
| 900 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 901 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 902 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 903 | genSpill, genReload, directReload, |
| 904 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 905 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 906 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 907 | vexAllocSanityCheck(); |
| 908 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 909 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 910 | vex_printf("\n------------------------" |
| 911 | " Register-allocated code " |
| 912 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 913 | for (i = 0; i < rcode->arr_used; i++) { |
| 914 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 915 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 916 | vex_printf("\n"); |
| 917 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 918 | vex_printf("\n"); |
| 919 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 920 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 921 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 922 | if (0) { |
| 923 | *(vta->host_bytes_used) = 0; |
| 924 | res.status = VexTransOK; return res; |
| 925 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 926 | /* end HACK */ |
| 927 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 928 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 929 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 930 | vex_printf("\n------------------------" |
| 931 | " Assembly " |
| 932 | "------------------------\n\n"); |
| 933 | } |
| 934 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 935 | out_used = 0; /* tracks along the host_bytes array */ |
| 936 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 937 | HInstr* hi = rcode->arr[i]; |
| 938 | Bool hi_isProfInc = False; |
| 939 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
| 940 | ppInstr(hi, mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 941 | vex_printf("\n"); |
| 942 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 943 | j = emit( &hi_isProfInc, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 944 | insn_bytes, sizeof insn_bytes, hi, |
| 945 | mode64, vta->archinfo_host.endness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 946 | vta->disp_cp_chain_me_to_slowEP, |
| 947 | vta->disp_cp_chain_me_to_fastEP, |
| 948 | vta->disp_cp_xindir, |
| 949 | vta->disp_cp_xassisted ); |
| 950 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 951 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 952 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 953 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 954 | else |
| 955 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 956 | vex_printf("\n\n"); |
| 957 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 958 | if (UNLIKELY(out_used + j > vta->host_bytes_size)) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 959 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 960 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 961 | res.status = VexTransOutputFull; |
| 962 | return res; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 963 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 964 | if (UNLIKELY(hi_isProfInc)) { |
| 965 | vassert(vta->addProfInc); /* else where did it come from? */ |
| 966 | vassert(res.offs_profInc == -1); /* there can be only one (tm) */ |
| 967 | vassert(out_used >= 0); |
| 968 | res.offs_profInc = out_used; |
| 969 | } |
| 970 | { UChar* dst = &vta->host_bytes[out_used]; |
| 971 | for (k = 0; k < j; k++) { |
| 972 | dst[k] = insn_bytes[k]; |
| 973 | } |
| 974 | out_used += j; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 975 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 976 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 977 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 978 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 979 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 980 | vexAllocSanityCheck(); |
| 981 | |
| 982 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 983 | |
sewardj | 65ea17e | 2012-12-28 09:01:59 +0000 | [diff] [blame] | 984 | if (vex_traceflags) { |
| 985 | /* Print the expansion ratio for this SB. */ |
| 986 | j = 0; /* total guest bytes */ |
| 987 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 988 | j += vta->guest_extents->len[i]; |
| 989 | } |
| 990 | if (1) vex_printf("VexExpansionRatio %d %d %d :10\n\n", |
| 991 | j, out_used, (10 * out_used) / (j == 0 ? 1 : j)); |
| 992 | } |
| 993 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 994 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 995 | res.status = VexTransOK; |
| 996 | return res; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1000 | /* --------- Chain/Unchain XDirects. --------- */ |
| 1001 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1002 | VexInvalRange LibVEX_Chain ( VexArch arch_host, |
| 1003 | VexEndness endness_host, |
| 1004 | void* place_to_chain, |
| 1005 | const void* disp_cp_chain_me_EXPECTED, |
| 1006 | const void* place_to_jump_to ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1007 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1008 | switch (arch_host) { |
| 1009 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1010 | return chainXDirect_X86(endness_host, |
| 1011 | place_to_chain, |
| 1012 | disp_cp_chain_me_EXPECTED, |
| 1013 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1014 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1015 | return chainXDirect_AMD64(endness_host, |
| 1016 | place_to_chain, |
| 1017 | disp_cp_chain_me_EXPECTED, |
| 1018 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1019 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1020 | return chainXDirect_ARM(endness_host, |
| 1021 | place_to_chain, |
| 1022 | disp_cp_chain_me_EXPECTED, |
| 1023 | place_to_jump_to); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1024 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1025 | return chainXDirect_ARM64(endness_host, |
| 1026 | place_to_chain, |
| 1027 | disp_cp_chain_me_EXPECTED, |
| 1028 | place_to_jump_to); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1029 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1030 | return chainXDirect_S390(endness_host, |
| 1031 | place_to_chain, |
| 1032 | disp_cp_chain_me_EXPECTED, |
| 1033 | place_to_jump_to); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1034 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1035 | return chainXDirect_PPC(endness_host, |
| 1036 | place_to_chain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1037 | disp_cp_chain_me_EXPECTED, |
| 1038 | place_to_jump_to, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1039 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1040 | return chainXDirect_PPC(endness_host, |
| 1041 | place_to_chain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1042 | disp_cp_chain_me_EXPECTED, |
| 1043 | place_to_jump_to, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1044 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1045 | return chainXDirect_MIPS(endness_host, |
| 1046 | place_to_chain, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1047 | disp_cp_chain_me_EXPECTED, |
| 1048 | place_to_jump_to, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1049 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1050 | return chainXDirect_MIPS(endness_host, |
| 1051 | place_to_chain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1052 | disp_cp_chain_me_EXPECTED, |
| 1053 | place_to_jump_to, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1054 | default: |
| 1055 | vassert(0); |
| 1056 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1057 | } |
| 1058 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1059 | VexInvalRange LibVEX_UnChain ( VexArch arch_host, |
| 1060 | VexEndness endness_host, |
| 1061 | void* place_to_unchain, |
| 1062 | const void* place_to_jump_to_EXPECTED, |
| 1063 | const void* disp_cp_chain_me ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1064 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1065 | switch (arch_host) { |
| 1066 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1067 | return unchainXDirect_X86(endness_host, |
| 1068 | place_to_unchain, |
| 1069 | place_to_jump_to_EXPECTED, |
| 1070 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1071 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1072 | return unchainXDirect_AMD64(endness_host, |
| 1073 | place_to_unchain, |
| 1074 | place_to_jump_to_EXPECTED, |
| 1075 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1076 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1077 | return unchainXDirect_ARM(endness_host, |
| 1078 | place_to_unchain, |
| 1079 | place_to_jump_to_EXPECTED, |
| 1080 | disp_cp_chain_me); |
sewardj | c6acaa4 | 2014-02-19 17:42:59 +0000 | [diff] [blame] | 1081 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1082 | return unchainXDirect_ARM64(endness_host, |
| 1083 | place_to_unchain, |
| 1084 | place_to_jump_to_EXPECTED, |
| 1085 | disp_cp_chain_me); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1086 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1087 | return unchainXDirect_S390(endness_host, |
| 1088 | place_to_unchain, |
| 1089 | place_to_jump_to_EXPECTED, |
| 1090 | disp_cp_chain_me); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1091 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1092 | return unchainXDirect_PPC(endness_host, |
| 1093 | place_to_unchain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1094 | place_to_jump_to_EXPECTED, |
| 1095 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1096 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1097 | return unchainXDirect_PPC(endness_host, |
| 1098 | place_to_unchain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1099 | place_to_jump_to_EXPECTED, |
| 1100 | disp_cp_chain_me, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1101 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1102 | return unchainXDirect_MIPS(endness_host, |
| 1103 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1104 | place_to_jump_to_EXPECTED, |
| 1105 | disp_cp_chain_me, False/*!mode64*/); |
| 1106 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1107 | return unchainXDirect_MIPS(endness_host, |
| 1108 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1109 | place_to_jump_to_EXPECTED, |
| 1110 | disp_cp_chain_me, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1111 | default: |
| 1112 | vassert(0); |
| 1113 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1114 | } |
| 1115 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1116 | Int LibVEX_evCheckSzB ( VexArch arch_host, |
| 1117 | VexEndness endness_host ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1118 | { |
| 1119 | static Int cached = 0; /* DO NOT MAKE NON-STATIC */ |
| 1120 | if (UNLIKELY(cached == 0)) { |
| 1121 | switch (arch_host) { |
| 1122 | case VexArchX86: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1123 | cached = evCheckSzB_X86(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1124 | case VexArchAMD64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1125 | cached = evCheckSzB_AMD64(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1126 | case VexArchARM: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1127 | cached = evCheckSzB_ARM(endness_host); break; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1128 | case VexArchARM64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1129 | cached = evCheckSzB_ARM64(endness_host); break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1130 | case VexArchS390X: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1131 | cached = evCheckSzB_S390(endness_host); break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1132 | case VexArchPPC32: |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1133 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1134 | cached = evCheckSzB_PPC(endness_host); break; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1135 | case VexArchMIPS32: |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1136 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1137 | cached = evCheckSzB_MIPS(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1138 | default: |
| 1139 | vassert(0); |
| 1140 | } |
| 1141 | } |
| 1142 | return cached; |
| 1143 | } |
| 1144 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1145 | VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, |
| 1146 | VexEndness endness_host, |
| 1147 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1148 | const ULong* location_of_counter ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1149 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1150 | switch (arch_host) { |
| 1151 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1152 | return patchProfInc_X86(endness_host, place_to_patch, |
| 1153 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1154 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1155 | return patchProfInc_AMD64(endness_host, place_to_patch, |
| 1156 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1157 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1158 | return patchProfInc_ARM(endness_host, place_to_patch, |
| 1159 | location_of_counter); |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 1160 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1161 | return patchProfInc_ARM64(endness_host, place_to_patch, |
| 1162 | location_of_counter); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1163 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame^] | 1164 | return patchProfInc_S390(endness_host, place_to_patch, |
| 1165 | location_of_counter); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1166 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1167 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1168 | location_of_counter, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1169 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1170 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1171 | location_of_counter, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1172 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1173 | return patchProfInc_MIPS(endness_host, place_to_patch, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1174 | location_of_counter, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1175 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1176 | return patchProfInc_MIPS(endness_host, place_to_patch, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1177 | location_of_counter, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1178 | default: |
| 1179 | vassert(0); |
| 1180 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1184 | /* --------- Emulation warnings. --------- */ |
| 1185 | |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 1186 | const HChar* LibVEX_EmNote_string ( VexEmNote ew ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1187 | { |
| 1188 | switch (ew) { |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1189 | case EmNote_NONE: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1190 | return "none"; |
| 1191 | case EmWarn_X86_x87exns: |
| 1192 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1193 | case EmWarn_X86_x87precision: |
| 1194 | return "Selection of non-80-bit x87 FP precision"; |
| 1195 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 1196 | return "Unmasking SSE FP exceptions"; |
| 1197 | case EmWarn_X86_fz: |
| 1198 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 1199 | case EmWarn_X86_daz: |
| 1200 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 1201 | case EmWarn_X86_acFlag: |
| 1202 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1203 | case EmWarn_PPCexns: |
| 1204 | return "Unmasking PPC32/64 FP exceptions"; |
| 1205 | case EmWarn_PPC64_redir_overflow: |
| 1206 | return "PPC64 function redirection stack overflow"; |
| 1207 | case EmWarn_PPC64_redir_underflow: |
| 1208 | return "PPC64 function redirection stack underflow"; |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1209 | case EmWarn_S390X_fpext_rounding: |
| 1210 | return "The specified rounding mode cannot be supported. That\n" |
| 1211 | " feature requires the floating point extension facility.\n" |
| 1212 | " which is not available on this host. Continuing using\n" |
| 1213 | " the rounding mode from FPC. Results may differ!"; |
florian | f0fa1be | 2012-09-18 20:24:38 +0000 | [diff] [blame] | 1214 | case EmWarn_S390X_invalid_rounding: |
| 1215 | return "The specified rounding mode is invalid.\n" |
| 1216 | " Continuing using 'round to nearest'. Results may differ!"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1217 | case EmFail_S390X_stfle: |
florian | 4e0083e | 2012-08-26 03:41:56 +0000 | [diff] [blame] | 1218 | return "Instruction stfle is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1219 | case EmFail_S390X_stckf: |
florian | c5c669b | 2012-08-26 14:32:28 +0000 | [diff] [blame] | 1220 | return "Instruction stckf is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1221 | case EmFail_S390X_ecag: |
florian | 8c88cb6 | 2012-08-26 18:58:13 +0000 | [diff] [blame] | 1222 | return "Instruction ecag is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1223 | case EmFail_S390X_fpext: |
| 1224 | return "Encountered an instruction that requires the floating " |
| 1225 | "point extension facility.\n" |
| 1226 | " That facility is not available on this host"; |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1227 | case EmFail_S390X_invalid_PFPO_rounding_mode: |
| 1228 | return "The rounding mode specified in GPR 0 for PFPO instruction" |
| 1229 | " is invalid"; |
| 1230 | case EmFail_S390X_invalid_PFPO_function: |
| 1231 | return "The function code specified in GPR 0 for PFPO instruction" |
| 1232 | " is invalid"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1233 | default: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1234 | vpanic("LibVEX_EmNote_string: unknown warning"); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1235 | } |
| 1236 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1237 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1238 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1239 | |
| 1240 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 1241 | { |
| 1242 | switch (arch) { |
| 1243 | case VexArch_INVALID: return "INVALID"; |
| 1244 | case VexArchX86: return "X86"; |
| 1245 | case VexArchAMD64: return "AMD64"; |
| 1246 | case VexArchARM: return "ARM"; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1247 | case VexArchARM64: return "ARM64"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 1248 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1249 | case VexArchPPC64: return "PPC64"; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1250 | case VexArchS390X: return "S390X"; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1251 | case VexArchMIPS32: return "MIPS32"; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1252 | case VexArchMIPS64: return "MIPS64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1253 | default: return "VexArch???"; |
| 1254 | } |
| 1255 | } |
| 1256 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1257 | const HChar* LibVEX_ppVexEndness ( VexEndness endness ) |
| 1258 | { |
| 1259 | switch (endness) { |
| 1260 | case VexEndness_INVALID: return "INVALID"; |
| 1261 | case VexEndnessLE: return "LittleEndian"; |
| 1262 | case VexEndnessBE: return "BigEndian"; |
| 1263 | default: return "VexEndness???"; |
| 1264 | } |
| 1265 | } |
| 1266 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1267 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1268 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1269 | const HChar* str = show_hwcaps(arch,hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1270 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1273 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1274 | /* Write default settings info *vai. */ |
| 1275 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 1276 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1277 | vex_bzero(vai, sizeof(*vai)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1278 | vai->hwcaps = 0; |
| 1279 | vai->endness = VexEndness_INVALID; |
| 1280 | vai->ppc_icache_line_szB = 0; |
| 1281 | vai->ppc_dcbz_szB = 0; |
| 1282 | vai->ppc_dcbzl_szB = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1283 | vai->arm64_dMinLine_lg2_szB = 0; |
| 1284 | vai->arm64_iMinLine_lg2_szB = 0; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1285 | vai->hwcache_info.num_levels = 0; |
| 1286 | vai->hwcache_info.num_caches = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1287 | vai->hwcache_info.caches = NULL; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1288 | vai->hwcache_info.icaches_maintain_coherence = True; // whatever |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1289 | } |
| 1290 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1291 | /* Write default settings info *vbi. */ |
| 1292 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1293 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1294 | vex_bzero(vbi, sizeof(*vbi)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1295 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 1296 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 1297 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1298 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 1299 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1300 | vbi->host_ppc_calls_use_fndescrs = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1301 | } |
| 1302 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1303 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1304 | /* Return a string showing the hwcaps in a nice way. The string will |
| 1305 | be NULL for invalid combinations of flags, so these functions also |
| 1306 | serve as a way to validate hwcaps values. */ |
| 1307 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1308 | static const HChar* show_hwcaps_x86 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1309 | { |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1310 | /* Monotonic, LZCNT > SSE3 > SSE2 > SSE1 > MMXEXT > baseline. */ |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1311 | switch (hwcaps) { |
| 1312 | case 0: |
| 1313 | return "x86-sse0"; |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1314 | case VEX_HWCAPS_X86_MMXEXT: |
| 1315 | return "x86-mmxext"; |
| 1316 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1: |
| 1317 | return "x86-mmxext-sse1"; |
| 1318 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2: |
| 1319 | return "x86-mmxext-sse1-sse2"; |
| 1320 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1321 | | VEX_HWCAPS_X86_LZCNT: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1322 | return "x86-mmxext-sse1-sse2-lzcnt"; |
| 1323 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1324 | | VEX_HWCAPS_X86_SSE3: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1325 | return "x86-mmxext-sse1-sse2-sse3"; |
| 1326 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1327 | | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1328 | return "x86-mmxext-sse1-sse2-sse3-lzcnt"; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1329 | default: |
| 1330 | return NULL; |
| 1331 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1332 | } |
| 1333 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1334 | static const HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1335 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1336 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 1337 | don't expect to come across anything which can do SSE3 but can't |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1338 | do CX16. Still, we can handle that case. LZCNT is similarly |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1339 | orthogonal. */ |
| 1340 | |
| 1341 | /* Throw out obviously stupid cases: */ |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1342 | Bool have_sse3 = (hwcaps & VEX_HWCAPS_AMD64_SSE3) != 0; |
| 1343 | Bool have_avx = (hwcaps & VEX_HWCAPS_AMD64_AVX) != 0; |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1344 | Bool have_bmi = (hwcaps & VEX_HWCAPS_AMD64_BMI) != 0; |
| 1345 | Bool have_avx2 = (hwcaps & VEX_HWCAPS_AMD64_AVX2) != 0; |
| 1346 | /* AVX without SSE3 */ |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1347 | if (have_avx && !have_sse3) |
| 1348 | return NULL; |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1349 | /* AVX2 or BMI without AVX */ |
| 1350 | if ((have_avx2 || have_bmi) && !have_avx) |
| 1351 | return NULL; |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1352 | |
| 1353 | /* This isn't threadsafe. We might need to fix it at some point. */ |
| 1354 | static HChar buf[100] = { 0 }; |
| 1355 | if (buf[0] != 0) return buf; /* already constructed */ |
| 1356 | |
| 1357 | vex_bzero(buf, sizeof(buf)); |
| 1358 | |
| 1359 | HChar* p = &buf[0]; |
| 1360 | |
| 1361 | p = p + vex_sprintf(p, "%s", "amd64"); |
| 1362 | if (hwcaps == 0) { |
| 1363 | /* special-case the baseline case */ |
| 1364 | p = p + vex_sprintf(p, "%s", "-sse2"); |
| 1365 | goto out; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1366 | } |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1367 | if (hwcaps & VEX_HWCAPS_AMD64_CX16) { |
| 1368 | p = p + vex_sprintf(p, "%s", "-cx16"); |
| 1369 | } |
| 1370 | if (hwcaps & VEX_HWCAPS_AMD64_LZCNT) { |
| 1371 | p = p + vex_sprintf(p, "%s", "-lzcnt"); |
| 1372 | } |
| 1373 | if (hwcaps & VEX_HWCAPS_AMD64_RDTSCP) { |
| 1374 | p = p + vex_sprintf(p, "%s", "-rdtscp"); |
| 1375 | } |
| 1376 | if (hwcaps & VEX_HWCAPS_AMD64_SSE3) { |
| 1377 | p = p + vex_sprintf(p, "%s", "-sse3"); |
| 1378 | } |
| 1379 | if (hwcaps & VEX_HWCAPS_AMD64_AVX) { |
| 1380 | p = p + vex_sprintf(p, "%s", "-avx"); |
| 1381 | } |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1382 | if (hwcaps & VEX_HWCAPS_AMD64_AVX2) { |
| 1383 | p = p + vex_sprintf(p, "%s", "-avx2"); |
| 1384 | } |
| 1385 | if (hwcaps & VEX_HWCAPS_AMD64_BMI) { |
| 1386 | p = p + vex_sprintf(p, "%s", "-bmi"); |
| 1387 | } |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1388 | |
| 1389 | out: |
| 1390 | vassert(buf[sizeof(buf)-1] == 0); |
| 1391 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1392 | } |
| 1393 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1394 | static const HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1395 | { |
| 1396 | /* Monotonic with complications. Basically V > F > baseline, |
| 1397 | but once you have F then you can have FX or GX too. */ |
| 1398 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 1399 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 1400 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 1401 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1402 | const UInt VX = VEX_HWCAPS_PPC32_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1403 | const UInt DFP = VEX_HWCAPS_PPC32_DFP; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1404 | const UInt ISA2_07 = VEX_HWCAPS_PPC32_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1405 | UInt c = hwcaps; |
| 1406 | if (c == 0) return "ppc32-int"; |
| 1407 | if (c == F) return "ppc32-int-flt"; |
| 1408 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 1409 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 1410 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 1411 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 1412 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 1413 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 1414 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1415 | if (c == (F|V|FX|GX|DFP)) return "ppc32-int-flt-vmx-FX-GX-DFP"; |
| 1416 | if (c == (F|V|FX|GX|VX|DFP)) return "ppc32-int-flt-vmx-FX-GX-VX-DFP"; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1417 | if (c == (F|V|FX|GX|VX|DFP|ISA2_07)) |
| 1418 | return "ppc32-int-flt-vmx-FX-GX-VX-DFP-ISA2_07"; |
| 1419 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1420 | return NULL; |
| 1421 | } |
| 1422 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1423 | static const HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1424 | { |
| 1425 | /* Monotonic with complications. Basically V > baseline(==F), |
| 1426 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1427 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 1428 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 1429 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1430 | const UInt VX = VEX_HWCAPS_PPC64_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1431 | const UInt DFP = VEX_HWCAPS_PPC64_DFP; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1432 | const UInt ISA2_07 = VEX_HWCAPS_PPC64_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1433 | UInt c = hwcaps; |
| 1434 | if (c == 0) return "ppc64-int-flt"; |
| 1435 | if (c == FX) return "ppc64-int-flt-FX"; |
| 1436 | if (c == GX) return "ppc64-int-flt-GX"; |
| 1437 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 1438 | if (c == V) return "ppc64-int-flt-vmx"; |
| 1439 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 1440 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 1441 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1442 | if (c == (V|FX|GX|DFP)) return "ppc64-int-flt-vmx-FX-GX-DFP"; |
| 1443 | if (c == (V|FX|GX|VX|DFP)) return "ppc64-int-flt-vmx-FX-GX-VX-DFP"; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1444 | if (c == (V|FX|GX|VX|DFP|ISA2_07)) |
| 1445 | return "ppc64-int-flt-vmx-FX-GX-VX-DFP-ISA2_07"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1446 | return NULL; |
| 1447 | } |
| 1448 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1449 | static const HChar* show_hwcaps_arm ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1450 | { |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 1451 | Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); |
| 1452 | Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP | |
| 1453 | VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0); |
| 1454 | switch (VEX_ARM_ARCHLEVEL(hwcaps)) { |
| 1455 | case 5: |
| 1456 | if (N) |
| 1457 | return NULL; |
| 1458 | if (vfp) |
| 1459 | return "ARMv5-vfp"; |
| 1460 | else |
| 1461 | return "ARMv5"; |
| 1462 | return NULL; |
| 1463 | case 6: |
| 1464 | if (N) |
| 1465 | return NULL; |
| 1466 | if (vfp) |
| 1467 | return "ARMv6-vfp"; |
| 1468 | else |
| 1469 | return "ARMv6"; |
| 1470 | return NULL; |
| 1471 | case 7: |
| 1472 | if (vfp) { |
| 1473 | if (N) |
| 1474 | return "ARMv7-vfp-neon"; |
| 1475 | else |
| 1476 | return "ARMv7-vfp"; |
| 1477 | } else { |
| 1478 | if (N) |
| 1479 | return "ARMv7-neon"; |
| 1480 | else |
| 1481 | return "ARMv7"; |
| 1482 | } |
| 1483 | default: |
| 1484 | return NULL; |
| 1485 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1486 | return NULL; |
| 1487 | } |
| 1488 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1489 | static const HChar* show_hwcaps_arm64 ( UInt hwcaps ) |
| 1490 | { |
| 1491 | /* Since there are no variants, just insist that hwcaps is zero, |
| 1492 | and declare it invalid otherwise. */ |
| 1493 | if (hwcaps == 0) |
| 1494 | return "baseline"; |
| 1495 | return NULL; |
| 1496 | } |
| 1497 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1498 | static const HChar* show_hwcaps_s390x ( UInt hwcaps ) |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1499 | { |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1500 | static const HChar prefix[] = "s390x"; |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1501 | static const struct { |
| 1502 | UInt hwcaps_bit; |
| 1503 | HChar name[6]; |
| 1504 | } hwcaps_list[] = { |
| 1505 | { VEX_HWCAPS_S390X_LDISP, "ldisp" }, |
| 1506 | { VEX_HWCAPS_S390X_EIMM, "eimm" }, |
| 1507 | { VEX_HWCAPS_S390X_GIE, "gie" }, |
| 1508 | { VEX_HWCAPS_S390X_DFP, "dfp" }, |
| 1509 | { VEX_HWCAPS_S390X_FGX, "fgx" }, |
| 1510 | { VEX_HWCAPS_S390X_STFLE, "stfle" }, |
| 1511 | { VEX_HWCAPS_S390X_ETF2, "etf2" }, |
| 1512 | { VEX_HWCAPS_S390X_ETF3, "etf3" }, |
| 1513 | { VEX_HWCAPS_S390X_STCKF, "stckf" }, |
| 1514 | { VEX_HWCAPS_S390X_FPEXT, "fpext" }, |
| 1515 | { VEX_HWCAPS_S390X_LSC, "lsc" }, |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1516 | { VEX_HWCAPS_S390X_PFPO, "pfpo" }, |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1517 | }; |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1518 | #define NUM_HWCAPS (sizeof hwcaps_list / sizeof hwcaps_list[0]) |
| 1519 | static HChar buf[sizeof prefix + |
| 1520 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + |
| 1521 | 1]; // '\0' |
| 1522 | HChar *p; |
| 1523 | UInt i; |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1524 | |
| 1525 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1526 | |
sewardj | 652b56a | 2011-04-13 15:38:17 +0000 | [diff] [blame] | 1527 | hwcaps = VEX_HWCAPS_S390X(hwcaps); |
| 1528 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1529 | p = buf + vex_sprintf(buf, "%s", prefix); |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1530 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1531 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1532 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1533 | } |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1534 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1535 | /* If there are no facilities, add "zarch" */ |
| 1536 | if (hwcaps == 0) |
| 1537 | vex_sprintf(p, "-%s", "zarch"); |
| 1538 | |
| 1539 | return buf; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1540 | } |
| 1541 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1542 | static const HChar* show_hwcaps_mips32 ( UInt hwcaps ) |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1543 | { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1544 | /* MIPS baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1545 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1546 | /* MIPS baseline with dspr2. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1547 | if (VEX_MIPS_PROC_DSP2(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1548 | return "MIPS-baseline-dspr2"; |
| 1549 | } |
| 1550 | /* MIPS baseline with dsp. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1551 | if (VEX_MIPS_PROC_DSP(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1552 | return "MIPS-baseline-dsp"; |
| 1553 | } |
| 1554 | return "MIPS-baseline"; |
| 1555 | } |
| 1556 | |
| 1557 | /* Broadcom baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1558 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_BROADCOM) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1559 | return "Broadcom-baseline"; |
| 1560 | } |
| 1561 | |
| 1562 | /* Netlogic baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1563 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_NETLOGIC) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1564 | return "Netlogic-baseline"; |
| 1565 | } |
| 1566 | |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1567 | /* Cavium baseline. */ |
| 1568 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_CAVIUM) { |
| 1569 | return "Cavium-baseline"; |
| 1570 | } |
| 1571 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1572 | return NULL; |
| 1573 | } |
| 1574 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1575 | static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) |
| 1576 | { |
| 1577 | return "mips64-baseline"; |
| 1578 | } |
| 1579 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1580 | /* ---- */ |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1581 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1582 | { |
| 1583 | switch (arch) { |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1584 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
| 1585 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 1586 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 1587 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
| 1588 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1589 | case VexArchARM64: return show_hwcaps_arm64(hwcaps); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1590 | case VexArchS390X: return show_hwcaps_s390x(hwcaps); |
| 1591 | case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1592 | case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1593 | default: return NULL; |
| 1594 | } |
| 1595 | } |
| 1596 | |
| 1597 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1598 | { |
| 1599 | return show_hwcaps(arch,hwcaps) != NULL; |
| 1600 | } |
| 1601 | |
| 1602 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1603 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1604 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1605 | /*---------------------------------------------------------------*/ |